diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/CMakeLists.txt b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/CMakeLists.txt index 798e419..30e3967 100644 --- a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/CMakeLists.txt +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/CMakeLists.txt @@ -5,6 +5,8 @@ add_subdirectory(TARGET_M480) elseif("NUC472" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NUC472) +elseif("M460" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_M460) endif() target_include_directories(mbed-emac diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/CMakeLists.txt b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/CMakeLists.txt new file mode 100644 index 0000000..222154c --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_include_directories(mbed-emac + INTERFACE + . +) + +target_sources(mbed-emac + INTERFACE + m460_eth.c + synopGMAC_Dev.c + synopGMAC_network_interface.c +) diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.c b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.c new file mode 100644 index 0000000..7a69c09 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.c @@ -0,0 +1,670 @@ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + * Copyright (c) 2022 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Description: M460 MAC driver source file + */ +//#include +#include "m460_eth.h" +#include "mbed_toolchain.h" +//#define NU_TRACE +#include "numaker_eth_hal.h" + +#include "synopGMAC_network_interface.h" + +#ifdef NU_TRACE_ISR +#define NU_RAW_Debug(x) { mbed_error_printf x; } +#else +#define NU_RAW_Debug(x) +#endif + +#define NU_M460_INTF 0 // Device EMAC Interface port +#define NU_M460_RMII_PIN_GRP 0 // Device EMAC RMII pin group 0 or 1 + +extern synopGMACdevice GMACdev[GMAC_CNT]; +extern struct sk_buff tx_buf[GMAC_CNT][TRANSMIT_DESC_SIZE]; +extern struct sk_buff rx_buf[GMAC_CNT][RECEIVE_DESC_SIZE]; + +eth_callback_t nu_eth_txrx_cb = NULL; +void *nu_userData = NULL; + +extern void ack_emac_rx_isr(void); + +void plat_delay(uint32_t delay) +{ + volatile uint32_t loop = delay*200; + while (loop--); +} + +static void mdio_write(int addr, int reg, int data) +{ + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + synopGMAC_write_phy_reg((u32 *) gmacdev->MacBase, addr, reg, data); +} + +static int mdio_read(int addr, int reg) +{ + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + uint16_t data; + synopGMAC_read_phy_reg((u32 *) gmacdev->MacBase, addr, reg, &data); + return data; +} + + +static int reset_phy(void) +{ + + uint16_t reg; + uint32_t delayCnt; + int retVal = 0; + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + + mdio_write(CONFIG_PHY_ADDR, MII_BMCR, BMCR_RESET); + + delayCnt = 2000; + while (delayCnt > 0) { + delayCnt--; + if ((mdio_read(CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0) { + break; + } + } + + if (delayCnt == 0) { + NU_DEBUGF(("Reset phy failed\n")); + return (-1); + } + + delayCnt = 200000; + while (delayCnt > 0) { + delayCnt--; + if (numaker_eth_link_ok()) { + gmacdev->LinkState = LINKUP; + NU_DEBUGF(("Link Up\n")); + break; + } + } + if (delayCnt == 0) { + gmacdev->LinkState = LINKDOWN; + NU_DEBUGF(("Link Down\n")); + return (-1); + } + + mdio_write(CONFIG_PHY_ADDR, MII_ADVERTISE, ADVERTISE_CSMA | + ADVERTISE_10HALF | + ADVERTISE_10FULL | + ADVERTISE_100HALF | + ADVERTISE_100FULL); + + reg = mdio_read(CONFIG_PHY_ADDR, MII_BMCR); + mdio_write(CONFIG_PHY_ADDR, MII_BMCR, reg | BMCR_ANRESTART); + + delayCnt = 200000; + while (delayCnt > 0) { + delayCnt--; + if ((mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) + == (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) { + break; + } + } + + if( delayCnt == 0 ) { + NU_DEBUGF(("AN failed. Set to 100 FULL\n")); + synopGMAC_set_full_duplex(gmacdev); + synopGMAC_set_mode(NU_M460_INTF, 1); // Set mode 1: 100Mbps; 2: 10Mbps + return (-1); + } else { + reg = mdio_read(CONFIG_PHY_ADDR, MII_LPA); + if (reg & ADVERTISE_100FULL) { + NU_DEBUGF(("100 full\n")); + gmacdev->DuplexMode = FULLDUPLEX; + gmacdev->Speed = SPEED100; + synopGMAC_set_full_duplex(gmacdev); + synopGMAC_set_mode(NU_M460_INTF, 1); // Set mode 1: 100Mbps; 2: 10Mbps + } else if (reg & ADVERTISE_100HALF) { + NU_DEBUGF(("100 half\n")); + gmacdev->DuplexMode = HALFDUPLEX; + gmacdev->Speed = SPEED100; + synopGMAC_set_half_duplex(gmacdev); + synopGMAC_set_mode(NU_M460_INTF, 1); // Set mode 1: 100Mbps; 2: 10Mbps + } else if (reg & ADVERTISE_10FULL) { + NU_DEBUGF(("10 full\n")); + gmacdev->DuplexMode = FULLDUPLEX; + gmacdev->Speed = SPEED10; + synopGMAC_set_full_duplex(gmacdev); + synopGMAC_set_mode(NU_M460_INTF, 2); // Set mode 1: 100Mbps; 2: 10Mbps + } else { + NU_DEBUGF(("10 half\n")); + gmacdev->DuplexMode = HALFDUPLEX; + gmacdev->Speed = SPEED10; + synopGMAC_set_half_duplex(gmacdev); + synopGMAC_set_mode(NU_M460_INTF, 2); // Set mode 1: 100Mbps; 2: 10Mbps + } + } + + printf("PHY ID 1:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID1)); + printf("PHY ID 2:0x%x\r\n", mdio_read(CONFIG_PHY_ADDR, MII_PHYSID2)); + + return (retVal); + +} + + +void numaker_set_mac_addr(uint8_t *addr) +{ + + synopGMAC_set_mac_address(NU_M460_INTF, addr); + +} + +static void __set_mac_pins(uint32_t group) +{ + if(group == 0) + { + SET_EMAC0_RMII_MDC_PE8(); + SET_EMAC0_RMII_MDIO_PE9(); + SET_EMAC0_RMII_TXD0_PE10(); + SET_EMAC0_RMII_TXD1_PE11(); + SET_EMAC0_RMII_TXEN_PE12(); + SET_EMAC0_RMII_REFCLK_PC8(); + SET_EMAC0_RMII_RXD0_PC7(); + SET_EMAC0_RMII_RXD1_PC6(); + SET_EMAC0_RMII_CRSDV_PA7(); + SET_EMAC0_RMII_RXERR_PA6(); + + SET_EMAC0_PPS_PB6(); + } + else + { + SET_EMAC0_RMII_MDC_PB11(); + SET_EMAC0_RMII_MDIO_PB10(); + SET_EMAC0_RMII_TXD0_PB9(); + SET_EMAC0_RMII_TXD1_PB8(); + SET_EMAC0_RMII_TXEN_PB7(); + SET_EMAC0_RMII_REFCLK_PB5(); + SET_EMAC0_RMII_RXD0_PB4(); + SET_EMAC0_RMII_RXD1_PB3(); + SET_EMAC0_RMII_CRSDV_PB2(); + SET_EMAC0_RMII_RXERR_PB1(); + + SET_EMAC0_PPS_PE13(); + } +} + +static void __eth_clk_pin_init() +{ + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Enable IP clock */ + CLK_EnableModuleClock(EMAC0_MODULE); + + // Configure MDC clock rate + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /*---------------------------------------------------------------------------------------------------------*/ + /* Init I/O Multi-function */ + /*---------------------------------------------------------------------------------------------------------*/ + // Configure RMII pins + __set_mac_pins(NU_M460_RMII_PIN_GRP); + + /* Lock protected registers */ + SYS_LockReg(); + +} + +void numaker_eth_init(uint8_t *mac_addr) +{ + int status = 0; + int retval = 0; + int i; + uint32_t offload_needed = 0; + uint32_t dma_addr; + struct sk_buff *skb; + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + + NVIC_DisableIRQ(EMAC0_TXRX_IRQn); + /* init CLK & pins */ + __eth_clk_pin_init(); + + /*Attach the device to MAC struct This will configure all the required base addresses + such as Mac base, configuration base, phy base address(out of 32 possible phys )*/ + synopGMAC_attach(gmacdev, GMAC0MappedAddr + MACBASE, GMAC0MappedAddr + DMABASE, DEFAULT_PHY_BASE); + + // Reset MAC + synopGMAC_reset(gmacdev); + gmacdev->Intf = NU_M460_INTF; + synopGMAC_read_version(gmacdev); + + /*Check for Phy initialization*/ + synopGMAC_set_mdc_clk_div(gmacdev,GmiiCsrClk5); + gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev); + + /*Reset PHY*/ + //status = synopGMAC_check_phy_init(gmacdev); + status = reset_phy(); + + /*Set up the tx and rx descriptor queue/ring*/ + synopGMAC_setup_tx_desc_queue(gmacdev,TRANSMIT_DESC_SIZE, RINGMODE); + synopGMAC_init_tx_desc_base(gmacdev); //Program the transmit descriptor base address in to DmaTxBase addr + + synopGMAC_setup_rx_desc_queue(gmacdev,RECEIVE_DESC_SIZE, RINGMODE); + synopGMAC_init_rx_desc_base(gmacdev); //Program the transmit descriptor base address in to DmaTxBase addr + + /*Initialize the dma interface*/ + synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip0/*DmaDescriptorSkip2*/ | DmaDescriptor8Words ); synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward |DmaTxSecondFrame|DmaRxThreshCtrl128); + + /*Initialize the mac interface*/ + synopGMAC_mac_init(gmacdev); + synopGMAC_promisc_enable(gmacdev); + + synopGMAC_pause_control(gmacdev); // This enables the pause control in Full duplex mode of operation + +#if defined(NU_USING_HW_CHECKSUM) + /*IPC Checksum offloading is enabled for this driver. Should only be used if Full Ip checksumm offload engine is configured in the hardware*/ + offload_needed = 1; + synopGMAC_enable_rx_chksum_offload(gmacdev); //Enable the offload engine in the receive path + synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); // This is default configuration, DMA drops the packets if error in encapsulated ethernet payload +#endif + + for(i = 0; i < RECEIVE_DESC_SIZE; i ++) { + skb = &rx_buf[NU_M460_INTF][i]; + synopGMAC_set_rx_qptr(gmacdev, (u32)((u64)(skb->data) & 0xFFFFFFFF), sizeof(skb->data), (u32)((u64)skb & 0xFFFFFFFF)); + } + + for(i = 0; i < TRANSMIT_DESC_SIZE; i ++) { + skb = &tx_buf[NU_M460_INTF][i]; + synopGMAC_set_tx_qptr(gmacdev, (u32)((u64)(skb->data) & 0xFFFFFFFF), sizeof(skb->data), (u32)((u64)skb & 0xFFFFFFFF), offload_needed ,0); + } + + numaker_set_mac_addr(mac_addr); // need to reconfigure hardware address 'cos we just RESET emc... + + synopGMAC_clear_interrupt(gmacdev); + + synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); + NVIC_EnableIRQ(EMAC0_TXRX_IRQn); +} + + + +void ETH_halt(void) +{ + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + + synopGMAC_tx_disable(gmacdev); + synopGMAC_rx_disable(gmacdev); +} + +unsigned int m_status; + +/*---------------------------------------------------------------------------- + EMAC IRQ Handler + *----------------------------------------------------------------------------*/ +void EMAC0_IRQHandler(void) +{ + synopGMACdevice * gmacdev = &GMACdev[0]; + uint32_t interrupt,dma_status_reg, mac_status_reg; + int status; + uint32_t dma_addr; + + // Check GMAC interrupt + mac_status_reg = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacInterruptStatus); + if(mac_status_reg & GmacTSIntSts) { + gmacdev->synopGMACNetStats.ts_int = 1; + status = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacTSStatus); + if(!(status & (1 << 1))) { + NU_RAW_Debug(("TS alarm flag not set??\n")); + } else { + NU_RAW_Debug(("TS alarm!!!!!!!!!!!!!!!!\n")); + } + } + if(mac_status_reg & GmacLPIIntSts) { + //NU_RAW_Debug("LPI\n"); + //LPIStsChange = 1; + //LPIReg = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacLPICtrlSts); + ; + } + if(mac_status_reg & GmacRgmiiIntSts) { + uint32_t volatile reg; + reg = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacRgmiiCtrlSts); + + } + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacInterruptStatus ,mac_status_reg); + + /*Read the Dma interrupt status to know whether the interrupt got generated by our device or not*/ + dma_status_reg = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus); + NU_RAW_Debug(("i %08x %08x\n", mac_status_reg, dma_status_reg)); + + if(dma_status_reg == 0) + return; + + synopGMAC_disable_interrupt_all(gmacdev); + + NU_RAW_Debug(("%s:Dma Status Reg: 0x%08x\n",__FUNCTION__,dma_status_reg)); + + if(dma_status_reg & GmacPmtIntr) { + NU_RAW_Debug(("%s:: Interrupt due to PMT module\n",__FUNCTION__)); + synopGMAC_powerup_mac(gmacdev); + } + + if(dma_status_reg & GmacLineIntfIntr) { + NU_RAW_Debug(("%s:: Interrupt due to GMAC LINE module\n",__FUNCTION__)); + } + + /*Now lets handle the DMA interrupts*/ + interrupt = synopGMAC_get_interrupt_type(gmacdev); + NU_RAW_Debug(("%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt)); + + if(interrupt & synopGMACDmaError) { + uint8_t hwaddr[6]; + mbed_mac_address((char *)hwaddr); + NU_RAW_Debug(("%s::Fatal Bus Error Interrupt Seen\n",__FUNCTION__)); + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_disable_dma_rx(gmacdev); + + synopGMAC_take_desc_ownership_tx(gmacdev); + synopGMAC_take_desc_ownership_rx(gmacdev); + + synopGMAC_init_tx_rx_desc_queue(gmacdev); + + synopGMAC_reset(gmacdev);//reset the DMA engine and the GMAC ip + synopGMAC_set_mac_address(NU_M460_INTF, (uint8_t*)hwaddr); + synopGMAC_dma_bus_mode_init(gmacdev,DmaFixedBurstEnable| DmaBurstLength8 | DmaDescriptorSkip0/*DmaDescriptorSkip2*/ ); + synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward); + synopGMAC_init_rx_desc_base(gmacdev); + synopGMAC_init_tx_desc_base(gmacdev); + synopGMAC_mac_init(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + + } + + if(interrupt & synopGMACDmaRxNormal) { + //NU_RAW_Debug(("rx\n")); + NU_RAW_Debug(("%s:: Rx Normal \r\n", __FUNCTION__)); + // to handle received data + if (nu_eth_txrx_cb != NULL) { + nu_eth_txrx_cb('R', nu_userData); + } + } + + if(interrupt & synopGMACDmaRxAbnormal) { + mbed_error_printf("%s::Abnormal Rx Interrupt Seen \r\n",__FUNCTION__); + gmacdev->synopGMACNetStats.rx_over_errors++; + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + synopGMAC_resume_dma_rx(gmacdev);//To handle GBPS with 12 descriptors + } + } + + if(interrupt & synopGMACDmaRxStopped) { + mbed_error_printf("%s::Receiver stopped seeing Rx interrupts \r\n",__FUNCTION__); //Receiver gone in to stopped state + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + gmacdev->synopGMACNetStats.rx_over_errors++; + synopGMAC_enable_dma_rx(gmacdev); + } + } + + if(interrupt & synopGMACDmaTxNormal) { + //NU_RAW_Debug(("rx\n")); + //xmit function has done its job + NU_RAW_Debug(("%s::Finished Normal Transmission \n",__FUNCTION__)); + synop_handle_transmit_over(0);//Do whatever you want after the transmission is over + if (nu_eth_txrx_cb != NULL) { + nu_eth_txrx_cb('T', nu_userData); + } + } + + if(interrupt & synopGMACDmaTxAbnormal) { + mbed_error_printf("%s::Abnormal Tx Interrupt Seen\n",__FUNCTION__); + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + synop_handle_transmit_over(0); + if (nu_eth_txrx_cb != NULL) { + nu_eth_txrx_cb('T', nu_userData); + } + } + } + + if(interrupt & synopGMACDmaTxStopped) { + mbed_error_printf("%s::Transmitter stopped sending the packets\n",__FUNCTION__); + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_take_desc_ownership_tx(gmacdev); + + synopGMAC_enable_dma_tx(gmacdev); + mbed_error_printf("%s::Transmission Resumed\n",__FUNCTION__); + } + } + + /* Enable the interrupt before returning from ISR*/ +// if( !(interrupt & synopGMACDmaRxNormal)) { /* RxNormal will enable INT in numaker_eth_trigger_rx */ + synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); +// } + return; +} + +static void dump_desc(DmaDesc *desc) +{ +#if 1 + NU_DEBUGF(("###--- %s... Desc[0x%08x] status[0x%08x] ---###\r\n", __FUNCTION__, desc, desc->status)); + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + DmaDesc *tmp_desc; +#endif +#if 0 + int i=0; + for ( i=0; i< RECEIVE_DESC_SIZE; i++ ) { + tmp_desc = gmacdev->RxDesc + i; + NU_DEBUGF(("### RX %s... desc[0x%08x] status[0x%08x] length[0x%08x] buffer1[0x%08x] buffer2[0x%08x]\r\n", + __FUNCTION__, tmp_desc, tmp_desc->status, tmp_desc->length, tmp_desc->buffer1, tmp_desc->buffer2)); + //NU_DEBUGF(("### %s... length[0x%x]\r\n", __FUNCTION__, desc->length)); + //NU_DEBUGF(("### %s... buffer1[0x%x]\r\n", __FUNCTION__, desc->buffer1)); + //NU_DEBUGF(("### %s... buffer2[0x%x]\r\n", __FUNCTION__, desc->buffer2)); + } + for ( i=0; i< TRANSMIT_DESC_SIZE; i++ ) { + tmp_desc = gmacdev->TxDesc + i; + NU_DEBUGF(("### TX %s... desc[0x%08x] status[0x%08x] length[0x%08x] buffer1[0x%08x] buffer2[0x%08x]\r\n", + __FUNCTION__, tmp_desc, tmp_desc->status, tmp_desc->length, tmp_desc->buffer1, tmp_desc->buffer2)); + } +#endif +} + +void numaker_eth_trigger_rx(void) +{ + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + NU_DEBUGF(("=== %s... ---Start---\r\n", __FUNCTION__)); + dump_desc(gmacdev->RxBusyDesc); + /* Enable the interrupt */ + synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + /* Trigger RX DMA */ + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_resume_dma_rx(gmacdev); + NU_DEBUGF(("%s... resume RX DMA\r\n", __FUNCTION__)); + NU_DEBUGF(("=== %s... ---End---\r\n", __FUNCTION__)); +} + +int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf) +{ + + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + NU_DEBUGF(("=== %s... ---Start---\r\n", __FUNCTION__)); + DmaDesc * rxdesc = gmacdev->RxBusyDesc; + dump_desc(rxdesc); + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; + if(synopGMAC_is_desc_empty(rxdesc)) + return -1; + +// synopGMAC_disable_dma_rx(gmacdev); // it will encounter DMA interrupt status as "Receiver stopped seeing Rx interrupts" + *len = synop_handle_received_data(NU_M460_INTF, buf); + dump_desc(gmacdev->RxBusyDesc); + if( *len <= 0 ) return -1; /* No available RX frame */ + + // length of payload should be <= 1514 + if (*len > (NU_ETH_MAX_FLEN - 4)) { + NU_DEBUGF(("%s... unexpected long packet length=%d, buf=0x%x\r\n", __FUNCTION__, *len, *buf)); + *len = 0; // Skip this unexpected long packet + } + NU_DEBUGF(("=== %s... ---End---\r\n", __FUNCTION__)); + return 0; +} + +void numaker_eth_rx_next(void) +{ + NU_DEBUGF(("=== %s... ---Start---\r\n", __FUNCTION__)); + /* Already did in synop_handle_received_data */ + /* No-op at this stage */ +#if 0 + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + DmaDesc * rxdesc = (gmacdev->RxBusyDesc - 1); + + rxdesc->status = DescOwnByDma; +#endif + +} + +uint8_t *numaker_eth_get_tx_buf(void) +{ + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + DmaDesc * txdesc = gmacdev->TxNextDesc; + + if(!synopGMAC_is_desc_empty(txdesc)) { + return (NULL); + } + + if (synopGMAC_is_desc_owned_by_dma(txdesc)) + { + return (NULL); + } else { + dump_desc(txdesc); + return (uint8_t *) (txdesc->buffer1); + } + +} + +void numaker_eth_trigger_tx(uint16_t length, void *p) +{ + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + DmaDesc * txdesc = gmacdev->TxNextDesc; + uint32_t txnext = gmacdev->TxNext; +#if defined(NU_USING_HW_CHECKSUM) + uint32_t offload_needed = 1; +#else + uint32_t offload_needed = 0; +#endif + + (gmacdev->BusyTxDesc)++; //busy tx descriptor is incremented by one as it will be handed over to DMA + txdesc->length |= ((length <status |= (DescTxFirst | DescTxLast | DescTxIntEnable ); //ENH_DESC + + if(offload_needed) { + /* + Make sure that the OS you are running supports the IP and TCP checksum offloading, + before calling any of the functions given below. + */ + synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } else { + synopGMAC_tx_checksum_offload_bypass(gmacdev, txdesc); + } + __DSB(); + txdesc->status |= DescOwnByDma;//ENH_DESC + + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + + /* Enable the interrupt */ + synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + /* Trigger TX DMA */ + synopGMAC_resume_dma_tx(gmacdev); +// synopGMAC_enable_dma_tx(gmacdev); + +} + +int numaker_eth_link_ok(void) +{ + /* first, a dummy read to latch */ + mdio_read(CONFIG_PHY_ADDR, MII_BMSR); + if (mdio_read(CONFIG_PHY_ADDR, MII_BMSR) & BMSR_LSTATUS) { + return 1; + } + return 0; +} + +void numaker_eth_set_cb(eth_callback_t eth_cb, void *userData) +{ + nu_eth_txrx_cb = eth_cb; + nu_userData = userData; +} + +// Override mbed_mac_address of mbed_interface.c to provide ethernet devices with a semi-unique MAC address +void mbed_mac_address(char *mac) +{ + uint32_t uID1; + // Fetch word 0 + uint32_t word0 = *(uint32_t *)0xFF804; // 2KB Data Flash at 0xFF800 + // Fetch word 1 + // we only want bottom 16 bits of word1 (MAC bits 32-47) + // and bit 9 forced to 1, bit 8 forced to 0 + // Locally administered MAC, reduced conflicts + // http://en.wikipedia.org/wiki/MAC_address + uint32_t word1 = *(uint32_t *)0xFF800; // 2KB Data Flash at 0xFF800 + + if (word0 == 0xFFFFFFFF) { // Not burn any mac address at 1st 2 words of Data Flash + // with a semi-unique MAC address from the UUID + /* Enable FMC ISP function */ + SYS_UnlockReg(); + FMC_Open(); + // = FMC_ReadUID(0); + uID1 = FMC_ReadUID(1); + word1 = (uID1 & 0x003FFFFF) | ((uID1 & 0x030000) << 6) >> 8; + word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uID1 & 0xFF) << 12) | (FMC_ReadUID(2) & 0xFFF); + /* Disable FMC ISP function */ + FMC_Close(); + /* Lock protected registers */ + SYS_LockReg(); + } + + word1 |= 0x00000200; + word1 &= 0x0000FEFF; + + mac[0] = (word1 & 0x0000ff00) >> 8; + mac[1] = (word1 & 0x000000ff); + mac[2] = (word0 & 0xff000000) >> 24; + mac[3] = (word0 & 0x00ff0000) >> 16; + mac[4] = (word0 & 0x0000ff00) >> 8; + mac[5] = (word0 & 0x000000ff); + + NU_DEBUGF(("mac address %02x-%02x-%02x-%02x-%02x-%02x \r\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5])); +} + +void numaker_eth_enable_interrupts(void) +{ + synopGMACdevice *gmacdev = &GMACdev[NU_M460_INTF]; + + /* Enable the interrupt */ + synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + + NVIC_EnableIRQ(EMAC0_TXRX_IRQn); +} + +void numaker_eth_disable_interrupts(void) +{ + NVIC_DisableIRQ(EMAC0_TXRX_IRQn); +} diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.h b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.h new file mode 100644 index 0000000..2850a8e --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/m460_eth.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + * Copyright (c) 2022 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Description: M460 EMAC driver header file + */ + +#include "numaker_emac_config.h" +#include "M460.h" +#ifndef _M460_ETH_ +#define _M460_ETH_ + +/* Generic MII registers. */ + +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x007f /* Unused... */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x07c0 /* Unused... */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_RESV 0x1c00 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define PACKET_BUFFER_SIZE ( NU_ETH_MAX_FLEN + ((NU_ETH_MAX_FLEN%4) ? (4 - (NU_ETH_MAX_FLEN%4)) : 0) ) //For DMA 4 bytes alignment + +#define CONFIG_PHY_ADDR 1 + + +#endif /* _M460_ETH_ */ diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_Dev.c b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_Dev.c new file mode 100644 index 0000000..11a8e9e --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_Dev.c @@ -0,0 +1,2947 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + +/** \file + * This file defines the synopsys GMAC device dependent functions. + * Most of the operations on the GMAC device are available in this file. + * Functions for initiliasing and accessing MAC/DMA/PHY registers and the DMA descriptors + * are encapsulated in this file. The functions are platform/host/OS independent. + * These functions in turn use the low level device dependent (HAL) functions to + * access the register space. + * \internal + * ------------------------REVISION HISTORY--------------------------------- + * Synopsys 01/Aug/2007 Created + */ +#include +#include "synopGMAC_Dev.h" +#include "synopGMAC_network_interface.h" + +/** + * Function to set the MDC clock for mdio transactiona + * + * @param[in] pointer to device structure. + * @param[in] clk divider value. + * \return Reuturns 0 on success else return the error value. + */ +s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val) +{ + u32 orig_data; + orig_data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacGmiiAddr); //set the mdc clock to the user defined value + orig_data &= (~ GmiiCsrClkMask); + orig_data |= clk_div_val; + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiAddr ,orig_data); + return 0; +} + +/** + * Returns the current MDC divider value programmed in the ip. + * + * @param[in] pointer to device structure. + * @param[in] clk divider value. + * \return Returns the MDC divider value read. + */ +u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacGmiiAddr); + data &= GmiiCsrClkMask; + return data; +} + + + +/** + * Function to read the Phy register. The access to phy register + * is a slow process as the data is moved accross MDI/MDO interface + * @param[in] pointer to Register Base (It is the mac base in our case) . + * @param[in] PhyBase register is the index of one of supported 32 PHY devices. + * @param[in] Register offset is the index of one of the 32 phy register. + * @param[out] u16 data read from the respective phy register (only valid iff return value is 0). + * \return Returns 0 on success else return the error status. + */ +s32 synopGMAC_read_phy_reg(u32 *RegBase,u32 PhyBase, u32 RegOffset, u16 * data) +{ + u32 addr; + u32 loop_variable; + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask); + addr = addr | GmiiCsrClk0 | GmiiBusy ; //Gmii busy bit + + synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip + + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) { //Wait till the busy bit gets cleared with in a certain amount of time + if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)) { + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + * data = (u16)(synopGMACReadReg(RegBase,GmacGmiiData) & 0xFFFF); + else { + TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; +} + +/** + * Function to write to the Phy register. The access to phy register + * is a slow process as the data is moved accross MDI/MDO interface + * @param[in] pointer to Register Base (It is the mac base in our case) . + * @param[in] PhyBase register is the index of one of supported 32 PHY devices. + * @param[in] Register offset is the index of one of the 32 phy register. + * @param[in] data to be written to the respective phy register. + * \return Returns 0 on success else return the error status. + */ +s32 synopGMAC_write_phy_reg(u32 *RegBase, u32 PhyBase, u32 RegOffset, u16 data) +{ + u32 addr; + u32 loop_variable; + + synopGMACWriteReg(RegBase,GmacGmiiData,data); // write the data in to GmacGmiiData register of synopGMAC ip + + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite; + + addr = addr | GmiiCsrClk0 | GmiiBusy ; //set Gmii clk to 20-35 Mhz and Gmii busy bit + + synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) { + if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)) { + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + + if(loop_variable < DEFAULT_LOOP_VARIABLE) { + return 0; + } else { + TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } +} + +/** + * Function to configure the phy in loopback mode. + * + * @param[in] pointer to synopGMACdevice. + * @param[in] enable or disable the loopback. + * \return 0 on success else return the error status. + * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) + * and synopGMAC_loopback_off(synopGMACdevice *) functions. + */ +s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback) +{ + s32 status = 0; +#ifndef EMULATION + if(loopback) + status = synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, Mii_Loopback); + else + status = synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, Mii_NoLoopback); +#endif + return status; +} + + + +/** + * Function to read the GMAC IP Version and populates the same in device data structure. + * @param[in] pointer to synopGMACdevice. + * \return Always return 0. + */ + +s32 synopGMAC_read_version (synopGMACdevice * gmacdev) +{ + u32 data = 0; + data = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacVersion ); + gmacdev->Version = data; + TR("The data read from %08x is %08x\n",(gmacdev->MacBase+GmacVersion),data); + return 0; +} + + +/** + * Function to reset the GMAC core. + * This reests the DMA and GMAC core. After reset all the registers holds their respective reset value + * @param[in] pointer to synopGMACdevice. + * \return 0 on success else return the error status. + */ + +s32 synopGMAC_reset (synopGMACdevice * gmacdev ) +{ + u32 data = 0; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaBusMode ,DmaResetOn); + plat_delay(DEFAULT_LOOP_VARIABLE); + + do { + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaBusMode); + }while(data & 1); + + TR("DATA after Reset = %08x\n",data); + + return 0; +} + +s32 synopGMAC_reset_nocheck (synopGMACdevice * gmacdev ) +{ + u32 data = 0; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaBusMode ,DmaResetOn); + plat_delay(DEFAULT_LOOP_VARIABLE); + + TR("DATA after Reset = %08x\n",data); + + return 0; +} + +/** + * Function to program DMA bus mode register. + * + * The Bus Mode register is programmed with the value given. The bits to be set are + * bit wise or'ed and sent as the second argument to this function. + * @param[in] pointer to synopGMACdevice. + * @param[in] the data to be programmed. + * \return 0 on success else return the error status. + */ +s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ) +{ + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaBusMode ,init_value); + return 0; + +} + +/** + * Function to program DMA Control register. + * + * The Dma Control register is programmed with the value given. The bits to be set are + * bit wise or'ed and sent as the second argument to this function. + * @param[in] pointer to synopGMACdevice. + * @param[in] the data to be programmed. + * \return 0 on success else return the error status. + */ +s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value) +{ + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl, init_value); + return 0; +} + + +/*Gmac configuration functions*/ + +/** + * Enable the watchdog timer on the receiver. + * When enabled, Gmac enables Watchdog timer, and GMAC allows no more than + * 2048 bytes of data (10,240 if Jumbo frame enabled). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_wd_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; +} +/** + * Disable the watchdog timer on the receiver. + * When disabled, Gmac disabled watchdog timer, and can receive frames up to + * 16,384 bytes. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_wd_disable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; +} + +/** + * Enables the Jabber frame support. + * When enabled, GMAC disabled the jabber timer, and can transfer 16,384 byte frames. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jab_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJabber); + return; +} +/** + * Disables the Jabber frame support. + * When disabled, GMAC enables jabber timer. It cuts of transmitter if application + * sends more than 2048 bytes of data (10240 if Jumbo frame enabled). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jab_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJabber); + return; +} + +/** + * Enables Frame bursting (Only in Half Duplex Mode). + * When enabled, GMAC allows frame bursting in GMII Half Duplex mode. + * Reserved in 10/100 and Full-Duplex configurations. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; +} +/** + * Disables Frame bursting. + * When Disabled, frame bursting is not supported. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; +} + +/** + * Enable Jumbo frame support. + * When Enabled GMAC supports jumbo frames of 9018/9022(VLAN tagged). + * Giant frame error is not reported in receive frame status. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; +} +/** + * Disable Jumbo frame support. + * When Disabled GMAC does not supports jumbo frames. + * Giant frame error is reported in receive frame status. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; +} + +/** + * Disable Carrier sense. + * When Disabled GMAC ignores CRS signal during frame transmission + * in half duplex mode. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ + +void synopGMAC_disable_crs(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDisableCrs); + return; +} + + + +/** + * Selects the GMII port. + * When called GMII (1000Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_select_gmii(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; +} +/** + * Selects the MII port. + * When called MII (10/100Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_select_mii(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; +} + +/** + * Enables Receive Own bit (Only in Half Duplex Mode). + * When enaled GMAC receives all the packets given by phy while transmitting. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; +} +/** + * Disables Receive Own bit (Only in Half Duplex Mode). + * When enaled GMAC disables the reception of frames when gmii_txen_o is asserted. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; +} + +/** + * Sets the GMAC in loopback mode. + * When on GMAC operates in loop-back mode at GMII/MII. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note (G)MII Receive clock is required for loopback to work properly, as transmit clock is + * not looped back internally. + */ +void synopGMAC_loopback_on(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacLoopback); + return; +} +/** + * Sets the GMAC in Normal mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_loopback_off(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacLoopback); + return; +} + +/** + * Sets the GMAC core in Full-Duplex mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_set_full_duplex(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDuplex); + return; +} +/** + * Sets the GMAC core in Half-Duplex mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_set_half_duplex(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDuplex); + return; +} + +/** + * GMAC tries retransmission (Only in Half Duplex mode). + * If collision occurs on the GMII/MII, GMAC attempt retries based on the + * back off limit configured. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note This function is tightly coupled with synopGMAC_back_off_limit(synopGMACdev *, u32). + */ +void synopGMAC_retry_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRetry); + return; +} +/** + * GMAC tries only one transmission (Only in Half Duplex mode). + * If collision occurs on the GMII/MII, GMAC will ignore the current frami + * transmission and report a frame abort with excessive collision in tranmit frame status. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_retry_disable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRetry); + return; +} + +/** + * GMAC strips the Pad/FCS field of incoming frames. + * This is true only if the length field value is less than or equal to + * 1500 bytes. All received frames with length field greater than or equal to + * 1501 bytes are passed to the application without stripping the Pad/FCS field. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pad_crc_strip_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + return; +} +/** + * GMAC doesnot strips the Pad/FCS field of incoming frames. + * GMAC will pass all the incoming frames to Host unmodified. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + return; +} +/** + * GMAC programmed with the back off limit value. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note This function is tightly coupled with synopGMAC_retry_enable(synopGMACdevice * gmacdev) + */ +void synopGMAC_back_off_limit(synopGMACdevice * gmacdev, u32 value) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacConfig); + data &= (~GmacBackoffLimit); + data |= value; + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacConfig,data); + return; +} + +/** + * Enables the Deferral check in GMAC (Only in Half Duplex mode) + * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the + * transmit frame status when transmit state machine is deferred for more than + * - 24,288 bit times in 10/100Mbps mode + * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note Deferral begins when transmitter is ready to transmit, but is prevented because of + * an active CRS (carrier sense) + */ +void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; +} +/** + * Disables the Deferral check in GMAC (Only in Half Duplex mode). + * GMAC defers until the CRS signal goes inactive. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; +} +/** + * Enable the reception of frames on GMII/MII. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRx); + return; +} +/** + * Disable the reception of frames on GMII/MII. + * GMAC receive state machine is disabled after completion of reception of current frame. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacRx); + return; +} +/** + * Enable the transmission of frames on GMII/MII. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacConfig, GmacTx); + return; +} +/** + * Disable the transmission of frames on GMII/MII. + * GMAC transmit state machine is disabled after completion of transmission of current frame. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacConfig, GmacTx); + return; +} + + +/*Receive frame filter configuration functions*/ + +/** + * Enables reception of all the frames to application. + * GMAC passes all the frames received to application irrespective of whether they + * pass SA/DA address filtering or not. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_frame_filter_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; +} +/** + * Disables reception of all the frames to application. + * GMAC passes only those received frames to application which + * pass SA/DA address filtering. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; +} + +/** + * Populates the Hash High register with the data supplied. + * This function is called when the Hash filtering is to be enabled. + * @param[in] pointer to synopGMACdevice. + * @param[in] data to be written to hash table high register. + * \return void. + */ +void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacHashHigh,data); + return; +} + +/** + * Populates the Hash Low register with the data supplied. + * This function is called when the Hash filtering is to be enabled. + * @param[in] pointer to synopGMACdevice. + * @param[in] data to be written to hash table low register. + * \return void. + */ +void synopGMAC_write_hash_table_low(synopGMACdevice * gmacdev, u32 data) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacHashLow,data); + return; +} + +/** + * Enables Hash or Perfect filter (only if Hash filter is enabled in H/W). + * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC + * configuration are sent to application. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_hash_perfect_filter_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; +} + +/** + * Enables only Hash(only if Hash filter is enabled in H/W). + * Only frames matching Hash Filtering as per HMC and HUC + * configuration are sent to application. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_Hash_filter_only_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; +} + +/** + * Enables Source address filtering. + * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with + * SAMatch bit of RxStatus is set. GMAC drops failed frames. + * @param[in] pointer to synopGMACdevice. + * \return void. + * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) + */ +void synopGMAC_src_addr_filter_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; +} +/** + * Disables Source address filtering. + * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; +} +/** + * Enables Inverse Destination address filtering. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; +} +/** + * Enables the normal Destination address filtering. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; +} + +/** + * Enables forwarding of control frames. + * When set forwards all the control frames (incl. unicast and multicast PAUSE frames). + * @param[in] pointer to synopGMACdevice. + * \return void. + * \note Depends on RFE of FlowControlRegister[2] + */ +void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacFrameFilter); + data &= (~GmacPassControl); + data |= passcontrol; + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacFrameFilter,data); + return; +} + +/** + * Enables Broadcast frames. + * When enabled Address filtering module passes all incoming broadcast frames. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); + return; +} +/** + * Disable Broadcast frames. + * When disabled Address filtering module filters all incoming broadcast frames. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); + return; +} + +/** + * Enables Multicast frames. + * When enabled all multicast frames are passed. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; +} +/** + * Disable Multicast frames. + * When disabled multicast frame filtering depends on HMC bit. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; +} + +/** + * Enables multicast hash filtering. + * When enabled GMAC performs teh destination address filtering according to the hash table. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_hash_filter_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; +} +/** + * Disables multicast hash filtering. + * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares + * DA field with the value programmed in DA register. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; +} + +/** + * Enables promiscous mode. + * When enabled Address filter modules pass all incoming frames regardless of their Destination + * and source addresses. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_promisc_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; +} +/** + * Clears promiscous mode. + * When called the GMAC falls back to normal operation from promiscous mode. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_promisc_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; +} + + +/** + * Enables unicast hash filtering. + * When enabled GMAC performs the destination address filtering of unicast frames according to the hash table. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_hash_filter_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; +} +/** + * Disables multicast hash filtering. + * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares + * DA field with the value programmed in DA register. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; +} + +/*Flow control configuration functions*/ + +/** + * Enables detection of pause frames with stations unicast address. + * When enabled GMAC detects the pause frames with stations unicast address in addition to the + * detection of pause frames with unique multicast address. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; +} +/** + * Disables detection of pause frames with stations unicast address. + * When disabled GMAC only detects with the unique multicast address (802.3x). + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; +} +/** + * Rx flow control enable. + * When Enabled GMAC will decode the rx pause frame and disable the tx for a specified time. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; +} +/** + * Rx flow control disable. + * When disabled GMAC will not decode pause frame. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_rx_flow_control_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; +} +/** + * Tx flow control enable. + * When Enabled + * - In full duplex GMAC enables flow control operation to transmit pause frames. + * - In Half duplex GMAC enables the back pressure operation + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_flow_control_enable(synopGMACdevice * gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; +} + +/** + * Tx flow control disable. + * When Disabled + * - In full duplex GMAC will not transmit any pause frames. + * - In Half duplex GMAC disables the back pressure feature. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_flow_control_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; +} + +/** + * Initiate Flowcontrol operation. + * When Set + * - In full duplex GMAC initiates pause control frame. + * - In Half duplex GMAC initiates back pressure function. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev) +{ + //In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that + //control frame transmission is in progress. + if(gmacdev->Speed == FULLDUPLEX) { + if(!synopGMACCheckBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure)) + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } else { //if half duplex mode + + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + + return; +} + +/** + * stops Flowcontrol operation. + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev) +{ + //In full duplex this bit is automatically cleared after transmitting a pause control frame. + if(gmacdev->Speed == HALFDUPLEX) { + synopGMACSetBits((u32 *)gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + return; +} + +/** + * This enables the pause frame generation after programming the appropriate registers. + * presently activation is set at 3k and deactivation set at 4k. These may have to tweaked + * if found any issues + * @param[in] pointer to synopGMACdevice. + * \return void. + */ +void synopGMAC_pause_control(synopGMACdevice *gmacdev) +{ + u32 omr_reg; + u32 mac_flow_control_reg; + omr_reg = synopGMACReadReg((u32 *)gmacdev->DmaBase,DmaControl); + omr_reg |= DmaRxFlowCtrlAct4K | DmaRxFlowCtrlDeact5K |DmaEnHwFlowCtrl; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl, omr_reg); + + mac_flow_control_reg = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacFlowControl); + mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacFlowControl,mac_flow_control_reg); + + return; + +} + +/** + * Example mac initialization sequence. + * This function calls the initialization routines to initialize the GMAC register. + * One can change the functions invoked here to have different configuration as per the requirement + * @param[in] pointer to synopGMACdevice. + * \return Returns 0 on success. + */ +s32 synopGMAC_mac_init(synopGMACdevice * gmacdev) +{ + u32 PHYreg; + + if(gmacdev->DuplexMode == FULLDUPLEX) { + synopGMAC_wd_enable(gmacdev); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); + synopGMAC_loopback_off(gmacdev); + synopGMAC_set_full_duplex(gmacdev); + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); + + + if(gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else + synopGMAC_select_mii(gmacdev); + + // Cannot enable tx/rx while changing Speed/mode. + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); + synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + synopGMAC_dst_addr_filter_normal(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + synopGMAC_promisc_disable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); + + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_enable(gmacdev); + synopGMAC_tx_flow_control_enable(gmacdev); + } else { //for Half Duplex configuration + + synopGMAC_wd_enable(gmacdev); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); + synopGMAC_loopback_off(gmacdev); + synopGMAC_set_half_duplex(gmacdev); + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); + + + if(gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else + synopGMAC_select_mii(gmacdev); + + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); + synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + synopGMAC_dst_addr_filter_normal(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + synopGMAC_promisc_disable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); + + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_disable(gmacdev); + synopGMAC_tx_flow_control_disable(gmacdev); + + /*To set PHY register to enable CRS on Transmit*/ + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiAddr, GmiiBusy | 0x00000408); + PHYreg = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacGmiiData); + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiData, PHYreg | 0x00000800); + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacGmiiAddr, GmiiBusy | 0x0000040a); + } + return 0; +} + + +/** + * Checks and initialze phy. + * This function checks whether the phy initialization is complete. + * @param[in] pointer to synopGMACdevice. + * \return 0 if success else returns the error number. + */ +s32 synopGMAC_check_phy_init (synopGMACdevice * gmacdev) +{ + //u32 addr; + u16 data; + s32 status = 0; + s32 loop_count; + + loop_count = DEFAULT_LOOP_VARIABLE; + while(loop_count-- > 0) { + + status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_STATUS_REG, &data); + if(status) + return status; + + if((data & Mii_AutoNegCmplt) != 0) { + //printf("Autonegotiation Complete\n"); + break; + } + } + + status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_SPECIFIC_STATUS_REG, &data); + if(status) + return status; + + if((data & Mii_phy_status_link_up) == 0) { + //printf("No Link\n"); + gmacdev->LinkState = LINKDOWN; + return -ESYNOPGMACPHYERR; + } else { + gmacdev->LinkState = LINKUP; + //printf("Link UP\n"); + } + + status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_SPECIFIC_STATUS_REG, &data); + if(status) + return status; + + + + gmacdev->DuplexMode = (data & Mii_phy_status_full_duplex) ? FULLDUPLEX: HALFDUPLEX ; + //printf("Link is up in %s mode\n",(gmacdev->DuplexMode == FULLDUPLEX) ? "FULL DUPLEX": "HALF DUPLEX"); + + /*if not set to Master configuration in case of Half duplex mode set it manually as Master*/ + if(gmacdev->DuplexMode == HALFDUPLEX) { + status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_CONTROL_REG, &data); + if(status) + return status; + //status = synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_CONTROL_REG, data | Mii_Manual_Master_Config ); + //if(status) + // return status; + } + + status = synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase,gmacdev->PhyBase,PHY_SPECIFIC_STATUS_REG, &data); + if(status) + return status; + if(data & Mii_phy_status_speed_1000) + gmacdev->Speed = SPEED1000; + else if(data & Mii_phy_status_speed_100) + gmacdev->Speed = SPEED100; + else + gmacdev->Speed = SPEED10; + + return 0; +} + +/** + * Sets the Mac address in to GMAC register. + * This function sets the MAC address to the MAC register in question. + * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses. + * @param[in] Register offset for Mac address high + * @param[in] Register offset for Mac address low + * @param[in] buffer containing mac address to be programmed. + * \return 0 upon success. Error code upon failure. + */ +s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) +{ + u32 data; + + data = (MacAddr[5] << 8) | MacAddr[4]; + synopGMACWriteReg((u32 *)gmacdev->MacBase,MacHigh,data); + data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0] ; + synopGMACWriteReg((u32 *)gmacdev->MacBase,MacLow,data); + return 0; +} + + + + +/** + * Attaches the synopGMAC device structure to the hardware. + * Device structure is populated with MAC/DMA and PHY base addresses. + * @param[in] pointer to synopGMACdevice to populate mac dma and phy addresses. + * @param[in] GMAC IP mac base address. + * @param[in] GMAC IP dma base address. + * @param[in] GMAC IP phy base address. + * \return 0 upon success. Error code upon failure. + * \note This is important function. No kernel api provided by Synopsys + */ + +s32 synopGMAC_attach (synopGMACdevice *gmacdev, u32 macBase, u32 dmaBase, u32 phyBase) +{ + u8 mac_addr0[6] = DEFAULT_MAC0_ADDRESS; + u8 mac_addr1[6] = DEFAULT_MAC1_ADDRESS; + /*Make sure the Device data strucure is cleared before we proceed further*/ + memset((void *) gmacdev,0,sizeof(synopGMACdevice)); + /*Populate the mac and dma base addresses*/ + gmacdev->MacBase = macBase; + gmacdev->DmaBase = dmaBase; + gmacdev->PhyBase = phyBase; + + /* Program/flash in the station/IP's Mac address */ + synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, gmacdev->Intf == 0 ? mac_addr0 : mac_addr1); + + return 0; +} + + + +/** + * Initialize the rx descriptors for ring or chain mode operation. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) + * @param[in] pointer to DmaDesc structure. + * @param[in] whether end of ring + * \return void. + * \note Initialization of the buffer1, buffer2, data1,data2 and status are not done here. This only initializes whether one wants to use this descriptor + * in chain mode or ring mode. For chain mode of operation the buffer2 and data2 are programmed before calling this function. + */ +void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) +{ + desc->status = 0; + desc->length = last_ring_desc ? RxDescEndOfRing : 0; + desc->buffer1 = 0; + desc->buffer2 = 0; + //desc->data1 = 0; + //desc->data2 = 0; + return; +} +/** + * Initialize the tx descriptors for ring or chain mode operation. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) + * @param[in] pointer to DmaDesc structure. + * @param[in] whether end of ring + * \return void. + * \note Initialization of the buffer1, buffer2, data1,data2 and status are not done here. This only initializes whether one wants to use this descriptor + * in chain mode or ring mode. For chain mode of operation the buffer2 and data2 are programmed before calling this function. + */ +void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) +{ + + desc->status = last_ring_desc? TxDescEndOfRing : 0; + desc->length = 0; + + // desc->buffer1 = 0; // Chris: to keep pointer for get-tx buffer + desc->buffer2 = 0; + //desc->data1 = 0; + //desc->data2 = 0; + return; +} + +s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev) +{ + s32 i; + for(i =0; i < gmacdev -> TxDescCount; i++) { + synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1); + } + TR("At line %d\n",__LINE__); + for(i =0; i < gmacdev -> RxDescCount; i++) { + synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1); + } + + gmacdev->TxNext = 0; + gmacdev->TxBusy = 0; + gmacdev->RxNext = 0; + gmacdev->RxBusy = 0; + + return 0; +} + +/** + * Programs the DmaRxBaseAddress with the Rx descriptor base address. + * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Dma Rx Base address with the starting address of the descriptor ring or chain. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg((u32 *)gmacdev->DmaBase,DmaRxBaseAddr,(u32)((u64)gmacdev->RxDescDma & 0xFFFFFFFF)); + return; +} + +/** + * Programs the DmaTxBaseAddress with the Tx descriptor base address. + * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Dma Tx Base address with the starting address of the descriptor ring or chain. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg((u32 *)gmacdev->DmaBase,DmaTxBaseAddr,(u32)((u64)gmacdev->TxDescDma & 0xFFFFFFFF)); + return; +} + + +/** + * Checks whether the descriptor is owned by DMA. + * If descriptor is owned by DMA then the OWN bit is set to 1. This API is same for both ring and chain mode. + * @param[in] pointer to DmaDesc structure. + * \return returns true if Dma owns descriptor and false if not. + */ +bool synopGMAC_is_desc_owned_by_dma(DmaDesc *desc) +{ + return ((desc->status & DescOwnByDma) == DescOwnByDma ); +} + +/** + * returns the byte length of received frame including CRC. + * This returns the no of bytes received in the received ethernet frame including CRC(FCS). + * @param[in] pointer to DmaDesc structure. + * \return returns the length of received frame lengths in bytes. + */ +u32 synopGMAC_get_rx_desc_frame_length(u32 status) +{ + return ((status & DescFrameLengthMask) >> DescFrameLengthShift); +} + +/** + * Checks whether the descriptor is valid + * if no errors such as CRC/Receive Error/Watchdog Timeout/Late collision/Giant Frame/Overflow/Descriptor + * error the descritpor is said to be a valid descriptor. + * @param[in] pointer to DmaDesc structure. + * \return True if desc valid. false if error. + */ +bool synopGMAC_is_desc_valid(u32 status) +{ + return ((status & DescError) == 0); +} + +/** + * Checks whether the descriptor is empty. + * If the buffer1 and buffer2 lengths are zero in ring mode descriptor is empty. + * In chain mode buffer2 length is 0 but buffer2 itself contains the next descriptor address. + * @param[in] pointer to DmaDesc structure. + * \return returns true if descriptor is empty, false if not empty. + */ +bool synopGMAC_is_desc_empty(DmaDesc *desc) +{ + //if both the buffer1 length and buffer2 length are zero desc is empty + return(((desc->length & DescSize1Mask) == 0) && ((desc->length & DescSize2Mask) == 0) ); +} + + +/** + * Checks whether the rx descriptor is valid. + * if rx descripor is not in error and complete frame is available in the same descriptor + * @param[in] pointer to DmaDesc structure. + * \return returns true if no error and first and last desc bits are set, otherwise it returns false. + */ +bool synopGMAC_is_rx_desc_valid(u32 status) +{ + return ((status & DescError) == 0) && ((status & DescRxFirst) == DescRxFirst) && ((status & DescRxLast) == DescRxLast); +} + +/** + * Checks whether the tx is aborted due to collisions. + * @param[in] pointer to DmaDesc structure. + * \return returns true if collisions, else returns false. + */ +bool synopGMAC_is_tx_aborted(u32 status) +{ + return (((status & DescTxLateCollision) == DescTxLateCollision) | ((status & DescTxExcCollisions) == DescTxExcCollisions)); + +} + +/** + * Checks whether the tx carrier error. + * @param[in] pointer to DmaDesc structure. + * \return returns true if carrier error occured, else returns falser. + */ +bool synopGMAC_is_tx_carrier_error(u32 status) +{ + return (((status & DescTxLostCarrier) == DescTxLostCarrier) | ((status & DescTxNoCarrier) == DescTxNoCarrier)); +} + + +/** + * Gives the transmission collision count. + * returns the transmission collision count indicating number of collisions occured before the frame was transmitted. + * Make sure to check excessive collision didnot happen to ensure the count is valid. + * @param[in] pointer to DmaDesc structure. + * \return returns the count value of collision. + */ +u32 synopGMAC_get_tx_collision_count(u32 status) +{ + return ((status & DescTxCollMask) >> DescTxCollShift); +} +u32 synopGMAC_is_exc_tx_collisions(u32 status) +{ + return ((status & DescTxExcCollisions) == DescTxExcCollisions); +} + + +/** + * Check for damaged frame due to overflow or collision. + * Retruns true if rx frame was damaged due to buffer overflow in MTL or late collision in half duplex mode. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_frame_damaged(u32 status) +{ +//bool synopGMAC_dma_rx_collisions(u32 status) + return (((status & DescRxDamaged) == DescRxDamaged) | ((status & DescRxCollision) == DescRxCollision)); +} + +/** + * Check for damaged frame due to collision. + * Retruns true if rx frame was damaged due to late collision in half duplex mode. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_frame_collision(u32 status) +{ +//bool synopGMAC_dma_rx_collisions(u32 status) + return ((status & DescRxCollision) == DescRxCollision); +} + +/** + * Check for receive CRC error. + * Retruns true if rx frame CRC error occured. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_crc(u32 status) +{ +//u32 synopGMAC_dma_rx_crc(u32 status) + return ((status & DescRxCrc) == DescRxCrc); +} + +/** + * Indicates rx frame has non integer multiple of bytes. (odd nibbles). + * Retruns true if dribbling error in rx frame. + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_frame_dribbling_errors(u32 status) +{ +//u32 synopGMAC_dma_rx_frame_errors(u32 status) + return ((status & DescRxDribbling) == DescRxDribbling); +} + +/** + * Indicates error in rx frame length. + * Retruns true if received frame length doesnot match with the length field + * @param[in] pointer to DmaDesc structure. + * \return returns true if error else returns false. + */ +bool synopGMAC_is_rx_frame_length_errors(u32 status) +{ +//u32 synopGMAC_dma_rx_length_errors(u32 status) + return((status & DescRxLengthError) == DescRxLengthError); +} + +/** + * Checks whether this rx descriptor is last rx descriptor. + * This returns true if it is last descriptor either in ring mode or in chain mode. + * @param[in] pointer to devic structure. + * @param[in] pointer to DmaDesc structure. + * \return returns true if it is last descriptor, false if not. + * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init(). + */ +bool synopGMAC_is_last_rx_desc(synopGMACdevice * gmacdev,DmaDesc *desc) +{ +//bool synopGMAC_is_last_desc(DmaDesc *desc) + return (((desc->length & RxDescEndOfRing) == RxDescEndOfRing) /*|| ((u32)((u64)gmacdev->RxDesc & 0xFFFFFFFF) == desc->data2)*/); +} + +/** + * Checks whether this tx descriptor is last tx descriptor. + * This returns true if it is last descriptor either in ring mode or in chain mode. + * @param[in] pointer to devic structure. + * @param[in] pointer to DmaDesc structure. + * \return returns true if it is last descriptor, false if not. + * \note This function should not be called before initializing the descriptor using synopGMAC_desc_init(). + */ +bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc) +{ +//bool synopGMAC_is_last_desc(DmaDesc *desc) + + return (((desc->status & TxDescEndOfRing) == TxDescEndOfRing) /*|| ((u32)((u64)gmacdev->TxDesc & 0xFFFFFFFF) == desc->data2)*/); + +} + + +/** + * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor + * Get the index and address of Tx desc. + * This api is same for both ring mode and chain mode. + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * over. This returns the descriptor fields to the caller. + * @param[in] pointer to synopGMACdevice. + * @param[out] status field of the descriptor. + * @param[out] Dma-able buffer1 pointer. + * @param[out] length of buffer1 (Max is 2048). + * @param[out] virtual pointer for buffer1. + * @param[out] u32 data indicating whether the descriptor is in ring mode or chain mode. + * \return returns present tx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) +{ + u32 txover = gmacdev->TxBusy; +#ifdef CACHE_ON + DmaDesc * txdesc = (DmaDesc *)((uint64_t)(gmacdev->TxBusyDesc) | 0x100000000); +#else + DmaDesc * txdesc = gmacdev->TxBusyDesc; +#endif + if(synopGMAC_is_desc_owned_by_dma(txdesc)) + return -1; + if(synopGMAC_is_desc_empty(txdesc)) + return -1; + + (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + + if(Status != 0) + *Status = txdesc->status; + + if(Ext_Status != 0) + *Ext_Status = txdesc->extstatus; + if(Time_Stamp_High != 0) + *Time_Stamp_High = txdesc->timestamphigh; + if(Time_Stamp_Low != 0) + *Time_Stamp_Low = txdesc->timestamplow; + + if(Buffer1 != 0) + *Buffer1 = txdesc->buffer1; + if(Length1 != 0) + *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; + //if(Data1 != 0) + // *Data1 = txdesc->data1; + + + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; + + if(1 /* ring mode */) { + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); + } + TR("(get)%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)((u64)txdesc & 0xFFFFFFFF),txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + + return txover; +} + +DmaDesc * prevtx; +void synopGMAC_set_crc_replacement(synopGMACdevice * gmacdev) +{ +#ifdef CACHE_ON + DmaDesc * txdesc = (DmaDesc *)((uint64_t)(gmacdev->TxNextDesc) | 0x100000000); +#else + DmaDesc * txdesc = gmacdev->TxNextDesc; +#endif + txdesc->status |= DescTxDisableCrc | DescTxCrcReplacement; + + prevtx = txdesc; +} + +void synopGMAC_clr_crc_replacement(synopGMACdevice * gmacdev) +{ + prevtx->status &= ~(DescTxDisableCrc | DescTxCrcReplacement); + prevtx = NULL; +} + +/** + * Populate the tx desc structure with the buffer address. + * Once the driver has a packet ready to be transmitted, this function is called with the + * valid dma-able buffer addresses and their lengths. This function populates the descriptor + * and make the DMA the owner for the descriptor. This function also controls whetther Checksum + * offloading to be done in hardware or not. + * This api is same for both ring mode and chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] Dma-able buffer1 pointer. + * @param[in] length of buffer1 (Max is 2048). + * @param[in] virtual pointer for buffer1. + + * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode. + * @param[in] u32 indicating whether the checksum offloading in HW/SW. + * \return returns present tx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 offload_needed, u32 ts) +{ + u32 txnext = gmacdev->TxNext; +#ifdef CACHE_ON + DmaDesc * txdesc = (DmaDesc *)((uint64_t)(gmacdev->TxNextDesc) | 0x100000000); +#else + DmaDesc * txdesc = gmacdev->TxNextDesc; +#endif + if(!synopGMAC_is_desc_empty(txdesc)) + return -1; + + (gmacdev->BusyTxDesc)++; //busy tx descriptor is incremented by one as it will be handed over to DMA + + if(1 /* ring mode */) { + txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable | (ts == 1 ? DescTxTSEnable : 0) ); //ENH_DESC // FIXME: Need to set DescTxTSEnable? + + //memcpy((void *)((u64)(tx_buf[][txnext]->Data) | 0x100000000), (void *)((u64)Buffer1), Length1); + txdesc->buffer1 = Buffer1; + //txdesc->data1 = Data1; + + if(offload_needed) { + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ + + //TODO: + //synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + //synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } else { + synopGMAC_tx_checksum_offload_bypass(gmacdev, txdesc); + } + __DSB(); + txdesc->status |= DescOwnByDma;//ENH_DESC + + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + } + + TR("(set)%02d %08x %08x %08x %08x %08x %08x %08x\n",txnext,(u32)((u64)txdesc & 0xFFFFFFFF),txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + return txnext; +} + +/** + * Prepares the descriptor to receive packets. + * The descriptor is allocated with the valid buffer addresses (sk_buff address) and the length fields + * and handed over to DMA by setting the ownership. After successful return from this function the + * descriptor is added to the receive descriptor pool/queue. + * This api is same for both ring mode and chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] Dma-able buffer1 pointer. + * @param[in] length of buffer1 (Max is 2048). + * @param[in] Dma-able buffer2 pointer. + * @param[in] length of buffer2 (Max is 2048). + * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode. + * \return returns present rx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1) +{ + u32 rxnext = gmacdev->RxNext; +#ifdef CACHE_ON + DmaDesc * rxdesc = (DmaDesc *)((uint64_t)(gmacdev->RxNextDesc) | 0x100000000); +#else + DmaDesc * rxdesc = gmacdev->RxNextDesc; +#endif + if(!synopGMAC_is_desc_empty(rxdesc)) + return -1; + + rxdesc->length |= ((Length1 <buffer1 = Buffer1; + //rxdesc->data1 = Data1; + + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; + + rxdesc->buffer2 = 0; + //rxdesc->data2 = 0; + + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; + + rxdesc->status = DescOwnByDma; + + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)((u64)rxdesc & 0xFFFFFFFF),rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + return rxnext; +} + + +/** + * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor + * Get back the descriptor from DMA after data has been received. + * When the DMA indicates that the data is received (interrupt is generated), this function should be + * called to get the descriptor and hence the data buffers received. With successful return from this + * function caller gets the descriptor fields for processing. check the parameters to understand the + * fields returned.` + * @param[in] pointer to synopGMACdevice. + * @param[out] pointer to hold the status of DMA. + * @param[out] Dma-able buffer1 pointer. + * @param[out] pointer to hold length of buffer1 (Max is 2048). + * @param[out] virtual pointer for buffer1. + * \return returns present rx descriptor index on success. Negative value if error. + */ +s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, + u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) +{ + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors +#ifdef CACHE_ON + DmaDesc * rxdesc = (DmaDesc *)((uint64_t)(gmacdev->RxBusyDesc) | 0x100000000); +#else + DmaDesc * rxdesc = gmacdev->RxBusyDesc; +#endif + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; + if(synopGMAC_is_desc_empty(rxdesc)) + return -1; + + + if(Status != 0) + *Status = rxdesc->status;// send the status of this descriptor + + if(Ext_Status != 0) + *Ext_Status = rxdesc->extstatus; + if(Time_Stamp_High != 0) + *Time_Stamp_High = rxdesc->timestamphigh; + if(Time_Stamp_Low != 0) + *Time_Stamp_Low = rxdesc->timestamplow; + + if(Length1 != 0) + *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Buffer1 != 0) + *Buffer1 = rxdesc->buffer1; + //if(Data1 != 0) + // *Data1 = rxdesc->data1; + + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + // why init here.... should change onwer to DMA --ya + //synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); + rxdesc->status = DescOwnByDma; + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)((u64)rxdesc & 0xFFFFFFFF),rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + (gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + return(rxnext); + +} + + +/** + * Clears all the pending interrupts. + * If the Dma status register is read then all the interrupts gets cleared + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus); + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaStatus ,data); +} + +/** + * Returns the all unmasked interrupt status after reading the DmaStatus register. + * @param[in] pointer to synopGMACdevice. + * \return 0 upon success. Error code upon failure. + */ +u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) +{ + u32 data; + u32 interrupts = 0; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus); + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaStatus ,data); //This is the appropriate location to clear the interrupts + TR("DMA status reg is %08x\n",data); + if(data & DmaIntErrorMask) interrupts |= synopGMACDmaError; + if(data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; + if(data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; + if(data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; + if(data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; + if(data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; + if(data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; + + //printf("%08x\n", data); + //if((interrupts != 0) && (interrupts != 1) && (interrupts != 8) && (interrupts != 9)) { + // printf("....\n"); + // while(1); + //} + return interrupts; +} + + +/** + * Enable all the interrupts. + * Enables the DMA interrupt as specified by the bit mask. + * @param[in] pointer to synopGMACdevice. + * @param[in] bit mask of interrupts to be enabled. + * \return returns void. + */ +void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) +{ +// synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaInterrupt, interrupts); + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaInterrupt); + data |= interrupts; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaInterrupt, data); + return; +} + + +/** + * Disable all the interrupts. + * Disables all DMA interrupts. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note This function disabled all the interrupts, if you want to disable a particular interrupt then + * use synopGMAC_disable_interrupt(). + */ +void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev) +{ + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaInterrupt, DmaIntDisable); + return; +} + +/** + * Disable interrupt according to the bitfield supplied. + * Disables only those interrupts specified in the bit mask in second argument. + * @param[in] pointer to synopGMACdevice. + * @param[in] bit mask for interrupts to be disabled. + * \return returns void. + */ +void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) +{ + synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaInterrupt, interrupts); + return; +} +/** + * Enable the DMA Reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev) +{ +// synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data |= DmaRxStart; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); + +} + +/** + * Enable the DMA Transmission. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev) +{ +// synopGMACSetBits((u32 *)gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data |= DmaTxStart; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); + +} + +void synopGMAC_enable_under_size_pkt(synopGMACdevice * gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data |= DmaFwdUnderSzFrames; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); + +} + +void synopGMAC_disable_under_size_pkt(synopGMACdevice * gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data &= ~DmaFwdUnderSzFrames; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); + +} + +void synopGMAC_enable_crc_err_pkt(synopGMACdevice * gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data |= DmaFwdErrorFrames; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); + +} + +void synopGMAC_disable_crc_err_pkt(synopGMACdevice * gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data &= ~DmaFwdErrorFrames; + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); + +} + + +/** + * Resumes the DMA Transmission. + * the DmaTxPollDemand is written. (the data writeen could be anything). + * This forces the DMA to resume transmission. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev) +{ + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaTxPollDemand, 0); + +} +/** + * Resumes the DMA Reception. + * the DmaRxPollDemand is written. (the data writeen could be anything). + * This forces the DMA to resume reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev) +{ + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaRxPollDemand, 0); + +} +/** + * Take ownership of this Descriptor. + * The function is same for both the ring mode and the chain mode DMA structures. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_take_desc_ownership(DmaDesc * desc) +{ + if(desc) { + desc->status &= ~DescOwnByDma; //Clear the DMA own bit +// desc->status |= DescError; // Set the error to indicate this descriptor is bad + } +} + +/** + * Take ownership of all the rx Descriptors. + * This function is called when there is fatal error in DMA transmission. + * When called it takes the ownership of all the rx descriptor in rx descriptor pool/queue from DMA. + * The function is same for both the ring mode and the chain mode DMA structures. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation. + */ +void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev) +{ + s32 i; + DmaDesc *desc; + desc = gmacdev->RxDesc; + for(i = 0; i < gmacdev->RxDescCount; i++) { + if(1 /* ring mode */) { + synopGMAC_take_desc_ownership(desc + i); + } + } +} + +/** + * Take ownership of all the rx Descriptors. + * This function is called when there is fatal error in DMA transmission. + * When called it takes the ownership of all the tx descriptor in tx descriptor pool/queue from DMA. + * The function is same for both the ring mode and the chain mode DMA structures. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + * \note Make sure to disable the transmission before calling this function, otherwise may result in racing situation. + */ +void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) +{ + s32 i; + DmaDesc *desc; + desc = gmacdev->TxDesc; + for(i = 0; i < gmacdev->TxDescCount; i++) { + if(1 /* ring mode */) { + synopGMAC_take_desc_ownership(desc + i); + } + } + +} + +/** + * Disable the DMA for Transmission. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ + +void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev) +{ +// synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data &= (~DmaTxStart); + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); +} +/** + * Disable the DMA for Reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) +{ +// synopGMACClearBits((u32 *)gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaControl); + data &= (~DmaRxStart); + synopGMACWriteReg((u32 *)gmacdev->DmaBase, DmaControl ,data); +} + + + +/*******************PMT APIs***************************************/ + + + + +/** + * Enables the assertion of PMT interrupt. + * This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame + * reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + return; +} +/** + * Disables the assertion of PMT interrupt. + * This disables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame + * reception. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + return; +} +/** + * Enables the power down mode of GMAC. + * This function puts the Gmac in power down mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + return; +} +/** + * Disables the powerd down setting of GMAC. + * If the driver wants to bring up the GMAC from powerdown mode, even though the magic packet or the + * wake up frames received from the network, this function should be called. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + return; +} +/** + * Enables the pmt interrupt generation in powerdown mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); +} +/** + * Disables the pmt interrupt generation in powerdown mode. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); +} +/** + * Enables GMAC to look for Magic packet. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable); + return; +} + +void synopGMAC_magic_packet_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable); + return; +} + +/** + * Enables GMAC to look for wake up frame. + * Wake up frame is defined by the user. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtWakeupFrameEnable); + return; +} + +/** + * Enables wake-up frame filter to handle unicast packets. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtGlobalUnicast); + return; +} +/** + * Checks whether the packet received is a magic packet?. + * @param[in] pointer to synopGMACdevice. + * \return returns True if magic packet received else returns false. + */ +bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus); + return((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); +} +/** + * Checks whether the packet received is a wakeup frame?. + * @param[in] pointer to synopGMACdevice. + * \return returns true if wakeup frame received else returns false. + */ +bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) +{ + u32 data; + data = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus); + return((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); +} + +/** + * Populates the remote wakeup frame registers. + * Consecutive 8 writes to GmacWakeupAddr writes the wakeup frame filter registers. + * Before commensing a new write, frame filter pointer is reset to 0x0000. + * A small delay is introduced to allow frame filter pointer reset operation. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to frame filter contents array. + * \return returns void. + */ +#if 0 +void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents) +{ + s32 i; + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtFrmFilterPtrReset); + plat_delay(10); + for(i =0; iMacBase, GmacWakeupAddr, *(filter_contents + i)); + return; + +} +#endif +/*******************PMT APIs***************************************/ + +/*******************Ip checksum offloading APIs***************************************/ + +/** + * Enables the ip checksum offloading in receive path. + * When set GMAC calculates 16 bit 1's complement of all received ethernet frame payload. + * It also checks IPv4 Header checksum is correct. GMAC core appends the 16 bit checksum calculated + * for payload of IP datagram and appends it to Ethernet frame transferred to the application. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); + return; +} +/** + * Disable the ip checksum offloading in receive path. + * Ip checksum offloading is disabled in the receive path. + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_disable_rx_chksum_offload(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); +} +/** + * Instruct the DMA to drop the packets fails tcp ip checksum. + * This is to instruct the receive DMA engine to drop the recevied packet if they + * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + return; +} +/** + * Instruct the DMA not to drop the packets even if it fails tcp ip checksum. + * This is to instruct the receive DMA engine to allow the packets even if recevied packet + * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2). + * @param[in] pointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + return; +} + +/** + * When the Enhanced Descriptor is enabled then the bit 0 of RDES0 indicates whether the + * Extended Status is available (RDES4). Time Stamp feature and the Checksum Offload Engine2 + * makes use of this extended status to provide the status of the received packet. + * @param[in] pointer to synopGMACdevice + * \return returns TRUE or FALSE + */ + + +/** + * This function indicates whether extended status is available in the RDES0. + * Any function which accesses the fields of extended status register must ensure a check on this has been made + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // extended status present indicates that the RDES4 need to be probed +{ + return((status & DescRxEXTsts ) != 0 ); // if extstatus set then it returns 1 +} +/** + * This function returns true if the IP header checksum bit is set in the extended status. + * Valid only when enhaced status available is set in RDES0 bit 0. + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status) // IP header (IPV4) checksum error +{ + return((ext_status & DescRxIpHeaderError) != 0 ); // if IPV4 header error return 1 +} +/** + * This function returns true if the Checksum is bypassed in the hardware. + * Valid only when enhaced status available is set in RDES0 bit 0. + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status) // Hardware engine bypassed the checksum computation/checking +{ + return((ext_status & DescRxChkSumBypass ) != 0 ); // if checksum offloading bypassed return 1 +} +/** + * This function returns true if payload checksum error is set in the extended status. + * Valid only when enhaced status available is set in RDES0 bit 0. + * This is valid only for Enhanced Descriptor. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns TRUE or FALSE. + */ +bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) // IP payload checksum is in error (UDP/TCP/ICMP checksum error) +{ + return((ext_status & DescRxIpPayloadError) != 0 ); // if IP payload error return 1 +} + + + + +/** + * Decodes the Rx Descriptor status to various checksum error conditions. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns decoded enum (u32) indicating the status. + */ +u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) +{ + if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxLenLT600; + else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkBypass; + else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxChkBypass; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxNoChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxPayLoadChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) + return RxIpHdrChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkError; + else + return RxIpHdrPayLoadRes; +} +/** + * Checks if any Ipv4 header checksum error in the frame just transmitted. + * This serves as indication that error occureed in the IPv4 header checksum insertion. + * The sent out frame doesnot carry any ipv4 header checksum inserted by the hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns true if error in ipv4 header checksum, else returns false. + */ +bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status) +{ + return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); +} + + +/** + * Checks if any payload checksum error in the frame just transmitted. + * This serves as indication that error occureed in the payload checksum insertion. + * The sent out frame doesnot carry any payload checksum inserted by the hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] u32 status field of the corresponding descriptor. + * \return returns true if error in ipv4 header checksum, else returns false. + */ +bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status) +{ + return((status & DescTxPayChkError) == DescTxPayChkError); +} +/** + * The check summ offload engine is bypassed in the tx path. + * Checksum is not computed in the Hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + desc->status = (desc->status & (~DescTxCisMask));//ENH_DESC + + +} +/** + * The check summ offload engine is enabled to do only IPV4 header checksum. + * IPV4 header Checksum is computed in the Hardware. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC + + +} + +/** + * The check summ offload engine is enabled to do TCPIP checsum assuming Pseudo header is available. + * Hardware computes the tcp ip checksum assuming pseudo header checksum is computed in software. + * Ipv4 header checksum is also inserted. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC + + +} +/** + * The check summ offload engine is enabled to do complete checksum computation. + * Hardware computes the tcp ip checksum including the pseudo header checksum. + * Here the tcp payload checksum field should be set to 0000. + * Ipv4 header checksum is also inserted. + * @param[in] pointer to synopGMACdevice. + * @param[in] Pointer to tx descriptor for which ointer to synopGMACdevice. + * \return returns void. + */ +void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc) +{ + + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); + + +} +/*******************Ip checksum offloading APIs***************************************/ + + + + + +/*******************IEEE 1588 Timestamping API***************************************/ + + +/* + * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled. + * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced + * Please make sure you have enabled the Advanced timestamp feature in the hardware and the driver should + * be compiled with the ADV_TME_STAMP feature. + * Some of the APIs provided here may not be valid for all configurations. Please make sure you call the + * API with due care. + */ + +/** + * This function enables the timestamping. This enables the timestamping for transmit and receive frames. + * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENA); + return; +} +/** + * This function disables the timestamping. + * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl, GmacTSENA); + return; +} + + +/** + * Enable the interrupt to get timestamping interrupt. + * This enables the host to get the interrupt when (1) system time is greater or equal to the + * target time high and low register or (2) there is a overflow in th esecond register. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev) +{ + //synopGMACClearBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacTSIntMask); + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSTRIG); + return; +} + +/** + * Disable the interrupt to get timestamping interrupt. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) +{ + //synopGMACSetBits((u32 *)gmacdev->MacBase,GmacInterruptMask,GmacTSIntMask); + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSTRIG); + return; +} + +/** + * Enable MAC address for PTP frame filtering. + * When enabled, uses MAC address (apart from MAC address 0) to filter the PTP frames when + * PTP is sent directly over Ethernet. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + return; +} + +/** + * Disables MAC address for PTP frame filtering. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + return; +} + + +/** + * Selet the type of clock mode for PTP. + * Please note to use one of the follwoing as the clk_type argument. + * GmacTSOrdClk = 0x00000000, 00=> Ordinary clock + * GmacTSBouClk = 0x00010000, 01=> Boundary clock + * GmacTSEtoEClk = 0x00020000, 10=> End-to-End transparent clock + * GmacTSPtoPClk = 0x00030000, 11=> P-to-P transparent clock + * @param[in] pointer to synopGMACdevice + * @param[in] u32 value representing one of the above clk value + * \return returns void + */ +void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) +{ + u32 clkval; + clkval = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl); //set the mdc clock to the user defined value + clkval = (clkval & ~GmacTSCLKTYPE)| clk_type; + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSControl,clkval); + return; +} + +/** + * Enable Snapshot for messages relevant to Master. + * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant + * to slave node. + * Valid only for Ordinary clock and Boundary clock + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + return; +} +/** + * Disable Snapshot for messages relevant to Master. + * When disabled, snapshot is taken for messages relevant + * to slave node. + * Valid only for Ordinary clock and Boundary clock + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + return; +} +/** + * Enable Snapshot for Event messages. + * When enabled, snapshot is taken for event messages only (SYNC, Delay_Req, Pdelay_Req or Pdelay_Resp) + * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + return; +} +/** + * Disable Snapshot for Event messages. + * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + return; +} + +/** + * Enable time stamp snapshot for IPV4 frames. + * When enabled, time stamp snapshot is taken for IPV4 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + return; +} +/** + * Disable time stamp snapshot for IPV4 frames. + * When disabled, time stamp snapshot is not taken for IPV4 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + return; +} // Only for "Advanced Time Stamp" +/** + * Enable time stamp snapshot for IPV6 frames. + * When enabled, time stamp snapshot is taken for IPV6 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + return; +} +/** + * Disable time stamp snapshot for IPV6 frames. + * When disabled, time stamp snapshot is not taken for IPV6 frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + return; +} + +/** + * Enable time stamp snapshot for PTP over Ethernet frames. + * When enabled, time stamp snapshot is taken for PTP over Ethernet frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + return; +} +/** + * Disable time stamp snapshot for PTP over Ethernet frames. + * When disabled, time stamp snapshot is not taken for PTP over Ethernet frames + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + return; +} + + +/** + * Snoop PTP packet for version 2 format + * When set the PTP packets are snooped using the version 2 format. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + return; +} +/** + * Snoop PTP packet for version 2 format + * When set the PTP packets are snooped using the version 2 format. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + return; +} + +/** + * Timestamp digital rollover + * When set the timestamp low register rolls over after 0x3B9A_C9FF value. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + return; +} +/** + * Timestamp binary rollover + * When set the timestamp low register rolls over after 0x7FFF_FFFF value. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + return; +} +/** + * Enable Time Stamp for All frames + * When set the timestamp snap shot is enabled for all frames received by the core. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENALL); + return; +} +/** + * Disable Time Stamp for All frames + * When reset the timestamp snap shot is not enabled for all frames received by the core. + * Reserved when "Advanced Time Stamp" is not selected + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSENALL); + return; +} +/** + * Addend Register Update + * This function loads the contents of Time stamp addend register with the supplied 32 value. + * This is reserved function when only coarse correction option is selected + * @param[in] pointer to synopGMACdevice + * @param[in] 32 bit addend value + * \return returns 0 for Success or else Failure + */ +s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) +{ + u32 loop_variable; + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSAddend,addend_value);// Load the addend_value in to Addend register + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) { //Wait till the busy bit gets cleared with in a certain amount of time + if(!((synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)) { // if it is cleared then break + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSADDREG); + else { + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; + +} +/** + * time stamp Update + * This function updates (adds/subtracts) with the value specified in the Timestamp High Update and + * Timestamp Low Update register. + * @param[in] pointer to synopGMACdevice + * @param[in] Timestamp High Update value + * @param[in] Timestamp Low Update value + * \return returns 0 for Success or else Failure + */ +s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) +{ + u32 loop_variable; + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) { //Wait till the busy bit gets cleared with in a certain amount of time + if(!((synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)) { // if it is cleared then break + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSUPDT); + else { + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; +} + +/** + * time stamp Initialize + * This function Loads/Initializes h the value specified in the Timestamp High Update and + * Timestamp Low Update register. + * @param[in] pointer to synopGMACdevice + * @param[in] Timestamp High Load value + * @param[in] Timestamp Low Load value + * \return returns 0 for Success or else Failure + */ +s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) +{ + u32 loop_variable; + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++) { //Wait till the busy bit gets cleared with in a certain amount of time + if(!((synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSControl)) & GmacTSINT)) { // if it is cleared then break + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSINT); + else { + TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + return 0; +} + +/** + * Time Stamp Update Coarse + * When reset the timestamp update is done using coarse method. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + return; +} +/** + * Time Stamp Update Fine + * When reset the timestamp update is done using Fine method. + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev) +{ + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + return; +} + +/** + * Load the Sub Second Increment value in to Sub Second increment register + * @param[in] pointer to synopGMACdevice + * \return returns void + */ +void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSSubSecIncr,(sub_sec_inc_value & GmacSSINCMsk)); + return; +} +/** + * Reads the time stamp contents in to the respective pointers + * These registers are readonly. + * This function returns the 48 bit time stamp assuming Version 2 timestamp with higher word is selected. + * @param[in] pointer to synopGMACdevice + * @param[in] pointer to hold 16 higher bit second register contents + * @param[in] pointer to hold 32 bit second register contents + * @param[in] pointer to hold 32 bit subnanosecond register contents + * \return returns void + * \note Please note that since the atomic access to the timestamp registers is not possible, + * the contents read may be different from the actual time stamp. + */ +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val) +{ + * higher_sec_val = (u16)(synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); + * sec_val = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSHigh); + * sub_sec_val = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSLow); + return; +} +/** + * Loads the time stamp higher sec value from the value supplied + * @param[in] pointer to synopGMACdevice + * @param[in] 16 higher bit second register contents passed as 32 bit value + * \return returns void + */ +void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); + return; +} +/** + * Reads the time stamp higher sec value to respective pointers + * @param[in] pointer to synopGMACdevice + * @param[in] pointer to hold 16 higher bit second register contents + * \return returns void + */ +void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val) +{ + * higher_sec_val = (u16)(synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); + return; +} +/** + * Load the Target time stamp registers + * This function Loads the target time stamp registers with the values proviced + * @param[in] pointer to synopGMACdevice + * @param[in] target Timestamp High value + * @param[in] target Timestamp Low value + * \return returns 0 for Success or else Failure + */ +void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeHigh,sec_val); + synopGMACWriteReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeLow,sub_sec_val); + return; +} +/** + * Reads the Target time stamp registers + * This function Loads the target time stamp registers with the values proviced + * @param[in] pointer to synopGMACdevice + * @param[in] pointer to hold target Timestamp High value + * @param[in] pointer to hold target Timestamp Low value + * \return returns 0 for Success or else Failure + */ +void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val) +{ + * sec_val = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeHigh); + * sub_sec_val = synopGMACReadReg((u32 *)gmacdev->MacBase,GmacTSTargetTimeLow); + return; +} + +void synopGMAC_src_addr_insert_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacSrcAddrInsRpl); + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacSrcAddrIns); + +} +void synopGMAC_src_addr_insert_disable(synopGMACdevice * gmacdev) +{ + + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacSrcAddrInsRpl); + +} +void synopGMAC_src_addr_replace_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacSrcAddrInsRpl); + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacSrcAddrRpl); + + +} +void synopGMAC_src_addr_replace_disable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacSrcAddrInsRpl); + +} + + +void synopGMAC_svlan_insertion_enable(synopGMACdevice * gmacdev, u16 vlantag) +{ + + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacSVLAN | GmacVLANIns| vlantag); + + +} + +void synopGMAC_cvlan_insertion_enable(synopGMACdevice * gmacdev, u16 vlantag) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacCVLAN | GmacVLANIns | vlantag); + + +} + +void synopGMAC_svlan_replace_enable(synopGMACdevice * gmacdev, u16 vlantag) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacSVLAN | GmacVLANRep | vlantag); + +} + +void synopGMAC_cvlan_replace_enable(synopGMACdevice * gmacdev, u16 vlantag) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacCVLAN | GmacVLANRep | vlantag); + +} + +void synopGMAC_vlan_deletion_enable(synopGMACdevice * gmacdev) +{ + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacVLANIncRep, GmacVLP | GmacVLANDel); + + +} + + +void synopGMAC_vlan_no_act_enable(synopGMACdevice * gmacdev) +{ + synopGMACClearBits((u32 *)gmacdev->MacBase, GmacVLANIncRep, 0xFFFFFFFF); +} + + diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_Dev.h b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_Dev.h new file mode 100644 index 0000000..4410ea7 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_Dev.h @@ -0,0 +1,1500 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + +/**\file + * This file defines the function prototypes for the Synopsys GMAC device and the + * Marvell 88E1011/88E1011S integrated 10/100/1000 Gigabit Ethernet Transceiver. + * Since the phy register mapping are standardised, the phy register map and the + * bit definitions remain the same for other phy as well. + * This also defines some of the Ethernet related parmeters. + * \internal + * -----------------------------REVISION HISTORY------------------------------------ + * Synopsys 01/Aug/2007 Created + */ + + +#ifndef SYNOP_GMAC_DEV_H +#define SYNOP_GMAC_DEV_H 1 + +#include "synopGMAC_plat.h" + +#define GMAC_CNT 1 + +/*SynopGMAC can support up to 32 phys*/ + +enum GMACPhyBase { + PHY0 = 0, //The device can support 32 phys, but we use first phy only + PHY1 = 1, + PHY31 = 31, +}; + +#define DEFAULT_PHY_BASE PHY1 //We use First Phy + +#define GMAC0MappedAddr EMAC_BASE //0x40012000 +#define GMAC1MappedAddr EMAC_BASE +#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 +#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 + + +#define TRANSMIT_DESC_SIZE 8//256 //Tx Descriptors needed in the Descriptor pool/queue +#define RECEIVE_DESC_SIZE 16//256 //Rx Descriptors needed in the Descriptor pool/queue + +#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type +#define ETHERNET_CRC 4 //Ethernet CRC +#define ETHERNET_EXTRA 2 //Only God knows about this????? +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define VLAN_TAG 4 //optional 802.1q VLAN Tag +#define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size +#define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size +#define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size + +#define TX_BUF_SIZE ETHERNET_HEADER + ETHERNET_CRC + MAX_ETHERNET_PAYLOAD + VLAN_TAG + + +// This is the IP's phy address. This is unique address for every MAC in the universe +#define DEFAULT_MAC0_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF7} +#define DEFAULT_MAC1_ADDRESS {0x00, 0x55, 0x7B, 0xB5, 0x7D, 0xF8} +/* +DMA Descriptor Structure +The structure is common for both receive and transmit descriptors +The descriptor is of 4 words, but our structrue contains 6 words where +last two words are to hold the virtual address of the network buffer pointers +for driver's use +From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed. +The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal +descriptor structure. +Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and + TX/RX DESC7 provides the upper 32 bits of Timestamp value +In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information +*/ + +#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for +// descriptor whose index%MODULO_INTERRUPT is zero +typedef struct DmaDescStruct { + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ + u32 extstatus; /* Extended status of a Rx Descriptor */ + u32 reserved1; /* Reserved word */ + u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ + u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ + //u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + //u32 data2; /* This holds virtual address of buffer2, not used by DMA */ +} DmaDesc; + +enum DescMode { + RINGMODE = 0x00000001, + CHAINMODE = 0x00000002, +}; + +enum BufferMode { + SINGLEBUF = 0x00000001, + DUALBUF = 0x00000002, +}; + +typedef u32 * dma_addr_t; + +/* synopGMAC device data */ + +struct sk_buff { + unsigned char data[2048]; + unsigned int len; + unsigned int volatile rdy; +}; + +struct net_device_stats { + u32 tx_bytes; + u32 tx_packets; + u32 tx_errors; + u32 tx_aborted_errors; + u32 tx_carrier_errors; + u32 tx_ip_header_errors; + u32 tx_ip_payload_errors; + u32 collisions; + u32 rx_bytes; + u32 rx_packets; + u32 rx_errors; + u32 rx_crc_errors; + u32 rx_frame_errors; + u32 rx_length_errors; + u32 rx_dropped; + u32 rx_over_errors; + u32 rx_ip_header_errors; + u32 rx_ip_payload_errors; + volatile u32 ts_int; +}; + +typedef struct synopGMACDeviceStruct { + u64 MacBase; /* base address of MAC registers */ + u64 DmaBase; /* base address of DMA registers */ + u64 PhyBase; /* PHY device address on MII interface */ + u64 Version; /* Gmac Revision version */ + + + /*dma_addr_t*/ DmaDesc *TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ + /*dma_addr_t*/ DmaDesc *RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ + DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ + + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ + + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ + u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ + + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ + u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ + u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ + u32 RxNext; /* index of the rx descriptor next available with driver, given to DMA by synopGMAC_set_rx_qptr() */ + + DmaDesc * TxBusyDesc; /* Tx Descriptor address corresponding to the index TxBusy */ + DmaDesc * TxNextDesc; /* Tx Descriptor address corresponding to the index TxNext */ + DmaDesc * RxBusyDesc; /* Rx Descriptor address corresponding to the index TxBusy */ + DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ + + + /*Phy related stuff*/ + u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ + /* The status of the link */ + u32 LinkState; /* Link status as reported by the Marvel Phy */ + u32 DuplexMode; /* Duplex mode of the Phy */ + u32 Speed; /* Speed of the Phy */ + u32 LoopBackMode; /* Loopback status of the Phy */ + u32 Intf; + struct net_device_stats synopGMACNetStats; + + u32 tx_sec; + u32 tx_subsec; + u32 rx_sec; + u32 rx_subsec; + + u32 GMAC_Power_down; + +} synopGMACdevice; + + +/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" + * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. + * Since the Phy register map is standard, this map hardly changes to a different Ppy + */ + +enum MiiRegisters { + PHY_CONTROL_REG = 0x0000, /*Control Register*/ + PHY_STATUS_REG = 0x0001, /*Status Register */ + PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ + PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ + PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ + PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ + PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ + PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ + PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ + PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ + PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ + PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ + PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ + PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ + PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ + PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ + PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ + PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ + PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ + PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ + PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ +}; + + +/* This is Control register layout. Control register is of 16 bit wide. +*/ + +enum Mii_GEN_CTRL { + /* Description bits R/W default value */ + Mii_reset = 0x8000, + Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ + Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ + Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ + + Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ + + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ + + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ + Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ +}; + +enum Mii_Phy_Status { + Mii_phy_status_speed_10 = 0x0000, + Mii_phy_status_speed_100 = 0x4000, + Mii_phy_status_speed_1000 = 0x8000, + + Mii_phy_status_full_duplex = 0x2000, + Mii_phy_status_half_duplex = 0x0000, + + Mii_phy_status_link_up = 0x0400, +}; +/* This is Status register layout. Status register is of 16 bit wide. +*/ +enum Mii_GEN_STATUS { + Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ + Mii_Link = 0x0004, /* Link status 2 RW */ +}; + +enum Mii_Link_Status { + LINKDOWN = 0, + LINKUP = 1, +}; + +enum Mii_Duplex_Mode { + HALFDUPLEX = 1, + FULLDUPLEX = 2, +}; +enum Mii_Link_Speed { + SPEED10 = 1, + SPEED100 = 2, + SPEED1000 = 3, +}; + +enum Mii_Loop_Back { + NOLOOPBACK = 0, + LOOPBACK = 1, +}; + + + +/********************************************************** + * GMAC registers Map + * For Pci based system address is BARx + GmacRegisterBase + * For any other system translation is done accordingly + **********************************************************/ +enum GmacRegisters { + GmacConfig = 0x0000, /* Mac config Register */ + GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ + GmacHashHigh = 0x0008, /* Multi-cast hash table high */ + GmacHashLow = 0x000C, /* Multi-cast hash table low */ + GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ + GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ + GmacFlowControl = 0x0018, /* Flow control Register */ + GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ + + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacDebug = 0x0024, /* GMAC Debug Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + + + GmacLPICtrlSts = 0x0030, /* LPI (low power idle) Control and Status Register */ + GmacLPITimerCtrl = 0x0034, /* LPI timer control register */ + + + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + + GmacAddr0High = 0x0040, /* Mac address0 high Register */ + GmacAddr0Low = 0x0044, /* Mac address0 low Register */ + GmacAddr1High = 0x0048, /* Mac address1 high Register */ + GmacAddr1Low = 0x004C, /* Mac address1 low Register */ + GmacAddr2High = 0x0050, /* Mac address2 high Register */ + GmacAddr2Low = 0x0054, /* Mac address2 low Register */ + GmacAddr3High = 0x0058, /* Mac address3 high Register */ + GmacAddr3Low = 0x005C, /* Mac address3 low Register */ + GmacAddr4High = 0x0060, /* Mac address4 high Register */ + GmacAddr4Low = 0x0064, /* Mac address4 low Register */ + GmacAddr5High = 0x0068, /* Mac address5 high Register */ + GmacAddr5Low = 0x006C, /* Mac address5 low Register */ + GmacAddr6High = 0x0070, /* Mac address6 high Register */ + GmacAddr6Low = 0x0074, /* Mac address6 low Register */ + GmacAddr7High = 0x0078, /* Mac address7 high Register */ + GmacAddr7Low = 0x007C, /* Mac address7 low Register */ + GmacAddr8High = 0x0080, /* Mac address8 high Register */ + GmacAddr8Low = 0x0084, /* Mac address8 low Register */ + GmacAddr9High = 0x0088, /* Mac address9 high Register */ + GmacAddr9Low = 0x008C, /* Mac address9 low Register */ + GmacAddr10High = 0x0090, /* Mac address10 high Register */ + GmacAddr10Low = 0x0094, /* Mac address10 low Register */ + GmacAddr11High = 0x0098, /* Mac address11 high Register */ + GmacAddr11Low = 0x009C, /* Mac address11 low Register */ + GmacAddr12High = 0x00A0, /* Mac address12 high Register */ + GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ + GmacAddr13High = 0x00A8, /* Mac address13 high Register */ + GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ + GmacAddr14High = 0x00B0, /* Mac address14 high Register */ + GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ + GmacAddr15High = 0x00B8, /* Mac address15 high Register */ + GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ + GmacRgmiiCtrlSts = 0x00D8, /*SGMII_RGMII_SMII_Control_Status Register */ + GmacVLANIncRep = 0x0584, + /*Time Stamp Register Map*/ + GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + + GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ + //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ + + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ + GmacPPSCtrl = 0x072C, /* PPS Control Register */ + GmacPPSInt = 0x0760, /* PPS0 Interval Register */ + GmacPPSWidth = 0x0764, /* PPS0 Width Register */ +}; + +/********************************************************** + * GMAC Network interface registers + * This explains the Register's Layout + + * FES is Read only by default and is enabled only when Tx + * Config Parameter is enabled for RGMII/SGMII interface + * during CoreKit Config. + + * DM is Read only with value 1'b1 in Full duplex only Config + **********************************************************/ + +/* GmacConfig = 0x0000, Mac config Register Layout */ +enum GmacConfigReg { + /* Bit description Bits R/W Reset value */ + + GmacSrcAddrInsRpl = 0x70000000, + GmacSrcAddrIns = 0x20000000, + GmacSrcAddrRpl = 0x30000000, + GmacWatchdog = 0x00800000, + GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ + GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ + + GmacJabber = 0x00400000, + GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ + GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ + + GmacFrameBurst = 0x00200000, + GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ + GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ + + GmacJumboFrame = 0x00100000, + GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ + GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ + + GmacInterFrameGap7 = 0x000E0000, /* (IFG) Config7 - 40 bit times 19:17 RW */ + GmacInterFrameGap6 = 0x000C0000, /* (IFG) Config6 - 48 bit times */ + GmacInterFrameGap5 = 0x000A0000, /* (IFG) Config5 - 56 bit times */ + GmacInterFrameGap4 = 0x00080000, /* (IFG) Config4 - 64 bit times */ + GmacInterFrameGap3 = 0x00040000, /* (IFG) Config3 - 72 bit times */ + GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ + GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ + GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ + + GmacDisableCrs = 0x00010000, + GmacMiiGmii = 0x00008000, + GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ + GmacSelectGmii = 0x00000000, /* GMII mode 0 */ + + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + + GmacRxOwn = 0x00002000, + GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ + GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ + + GmacLoopback = 0x00001000, + GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ + GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ + + GmacDuplex = 0x00000800, + GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ + GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ + + GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ + + GmacRetry = 0x00000200, + GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ + GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ + + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ + + GmacPadCrcStrip = 0x00000080, + GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ + GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ + + GmacBackoffLimit = 0x00000060, + GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ + GmacBackoffLimit2 = 0x00000040, /* */ + GmacBackoffLimit1 = 0x00000020, /* */ + GmacBackoffLimit0 = 0x00000000, /* 00 */ + + GmacDeferralCheck = 0x00000010, + GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ + GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ + + GmacTx = 0x00000008, + GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ + GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ + + GmacRx = 0x00000004, + GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ + GmacRxDisable = 0x00000000, /* Receiver disable 0 */ +}; + +/* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ +enum GmacFrameFilterReg { + GmacFilter = 0x80000000, + GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ + GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ + GmacVlanTagFilter = 0x00010000, /*VLAN tag filter enable 16 RW 0 */ + GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ + + GmacSrcAddrFilter = 0x00000200, + GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ + GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ + + GmacSrcInvaAddrFilter = 0x00000100, + GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ + GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ + + GmacPassControl = 0x000000C0, + GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ + GmacPassControl2 = 0x00000080, /* Forwards all control frames */ + GmacPassControl1 = 0x00000040, /* Does not pass control frames */ + GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ + + GmacBroadcast = 0x00000020, + GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ + GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ + + GmacMulticastFilter = 0x00000010, + GmacMulticastFilterOff = 0x00000010, /* (PM) Pass all multicast packets 4 RW */ + GmacMulticastFilterOn = 0x00000000, /* Pass filtered multicast packets 0 */ + + GmacDestAddrFilter = 0x00000008, + GmacDestAddrFilterInv = 0x00000008, /* (DAIF)Inverse filtering for DA 3 RW */ + GmacDestAddrFilterNor = 0x00000000, /* Normal filtering for DA 0 */ + + GmacMcastHashFilter = 0x00000004, + GmacMcastHashFilterOn = 0x00000004, /* (HMC)perfom multicast hash filtering 2 RW */ + GmacMcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + + GmacUcastHashFilter = 0x00000002, + GmacUcastHashFilterOn = 0x00000002, /* (HUC)Unicast Hash filtering only 1 RW */ + GmacUcastHashFilterOff = 0x00000000, /* perfect filtering only 0 */ + + GmacPromiscuousMode = 0x00000001, + GmacPromiscuousModeOn = 0x00000001, /* Receive all frames 0 RW */ + GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ +}; + + +/*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ +enum GmacGmiiAddrReg { + GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ + GmiiDevShift = 11, + + GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ + GmiiRegShift = 6, + + GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ + GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ + GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ + GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ + GmiiCsrClk2 = 0x00000008, /* 20-35 MHz */ + GmiiCsrClk1 = 0x00000004, /* 100-150 MHz */ + GmiiCsrClk0 = 0x00000000, /* 60-100 MHz */ + + GmiiWrite = 0x00000002, /* (GW)Write to register 1 RW */ + GmiiRead = 0x00000000, /* Read from register 0 */ + + GmiiBusy = 0x00000001, /* (GB)GMII interface is busy 0 RW 0 */ +}; + +enum GmacVlanTagReg { + GmacEnableSVlan = 0x00040000, /* (ESVL) Enabe S-Vlan */ + GmacVlanInvMatch = 0x00020000, /* (VTIM) VLAN tag inverse match enable */ + GmacEnable12BitComp = 0x00010000, /* (ETV) Enable 12-bit VLAN tag comparision */ + GmacVlanTagMsk = 0x0000FFFF /* (VL) VLAN tag */ + +}; + + +enum GmacLPICtrlStsReg { + GmacLPITxAuto = 0x00080000, + GmacLPIPhyStsEn = 0x00040000, + GmacLPIPhySts = 0x00020000, + GmacLPIEn = 0x00010000, + GmacRxLPISts = 0x00000200, + GmacTxLPISts = 0x00000100, + GmacRxLPIExit = 0x00000008, + GmacRxLPIEnter = 0x00000004, + GmacTxLPIExit = 0x00000002, + GmacTxLPIEnter = 0x00000001, +}; + +enum GmacLPITimerCtrlReg { + GmacLPILinkStableTimerMsk = 0x03FF0000, + GmacLPITxWaitTimerMsk = 0x0000FFFF, +}; + + +/* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ +enum GmacGmiiDataReg { + GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ +}; + + +/*GmacFlowControl = 0x0018, Flow control Register Layout */ +enum GmacFlowControlReg { + GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ + GmacPauseTimeShift = 16, + + GmacPauseLowThresh = 0x00000030, + GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ + GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ + GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ + GmacPauseLowThresh0 = 0x00000000, /* 4 slot time 000 */ + + GmacUnicastPauseFrame = 0x00000008, + GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ + GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ + + GmacRxFlowControl = 0x00000004, + GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ + GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ + + GmacTxFlowControl = 0x00000002, + GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ + GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ + + GmacFlowControlBackPressure= 0x00000001, + GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ +}; + + +enum GmacVLANIncRepReg { + GmacSVLAN = 0x00080000, + GmacCVLAN = 0x00000000, + GmacVLP = 0x00040000, + GmacVLANNoACT = 0x00000000, + GmacVLANDel = 0x00010000, + GmacVLANIns = 0x00020000, + GmacVLANRep = 0x00030000, + GmacVLANMsk = 0x0000FFFF + +}; + +/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ +enum GmacInterruptStatusBitDefinition { + GmacLPIIntSts = 0x00000400, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ + GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ + GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ + GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ + GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ + GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ + GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ + +}; + +/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ +enum GmacInterruptMaskBitDefinition { + GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ + GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ + GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ + GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ + GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ +}; + +/********************************************************** + * GMAC DMA registers + * For Pci based system address is BARx + GmaDmaBase + * For any other system translation is done accordingly + **********************************************************/ + +enum DmaRegisters { + DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ + DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ + DmaRxPollDemand = 0x0008, /* CSR2 - Receive Poll Demand Register */ + DmaRxBaseAddr = 0x000C, /* CSR3 - Receive Descriptor list base address */ + DmaTxBaseAddr = 0x0010, /* CSR4 - Transmit Descriptor list base address */ + DmaStatus = 0x0014, /* CSR5 - Dma status Register */ + DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ + DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ + DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ + DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ + + +}; + +/********************************************************** + * DMA Engine registers Layout + **********************************************************/ + +/*DmaBusMode = 0x0000, CSR0 - Bus Mode */ +enum DmaBusModeReg { + /* Bit description Bits R/W Reset value */ + + DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ + DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ + + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ + DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ + DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ + DmaBurstLength16 = 0x00001000, /* Dma burst length = 16 */ + DmaBurstLength8 = 0x00000800, /* Dma burst length = 8 */ + DmaBurstLength4 = 0x00000400, /* Dma burst length = 4 */ + DmaBurstLength2 = 0x00000200, /* Dma burst length = 2 */ + DmaBurstLength1 = 0x00000100, /* Dma burst length = 1 */ + DmaBurstLength0 = 0x00000000, /* Dma burst length = 0 0x00 */ + + DmaDescriptor8Words = 0x00000080, /* Enh Descriptor works 1=> 8 word descriptor 7 0 */ + DmaDescriptor4Words = 0x00000000, /* Enh Descriptor works 0=> 4 word descriptor 7 0 */ + + DmaDescriptorSkip16 = 0x00000040, /* (DSL)Descriptor skip length (no.of dwords) 6:2 RW */ + DmaDescriptorSkip8 = 0x00000020, /* between two unchained descriptors */ + DmaDescriptorSkip4 = 0x00000010, /* */ + DmaDescriptorSkip2 = 0x00000008, /* */ + DmaDescriptorSkip1 = 0x00000004, /* */ + DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ + + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ + DmaResetOff = 0x00000000, /* 0 */ +}; + + +/*DmaStatus = 0x0014, CSR5 - Dma status Register */ +enum DmaStatusReg { + /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ + + + GmacLPIIntr = 0x40000000, /* GMC LPI interrupt 31 RO 0 */ + + + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ + GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ + + DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ + DmaErrorBit1 = 0x01000000, /* (EB)Error bits 0-write trnsf, 1-read transfr 24 RO 0 */ + DmaErrorBit0 = 0x00800000, /* (EB)Error bits 0-Rx DMA, 1-Tx DMA 23 RO 0 */ + + DmaTxState = 0x00700000, /* (TS)Transmit process state 22:20 RO */ + DmaTxStopped = 0x00000000, /* Stopped - Reset or Stop Tx Command issued 000 */ + DmaTxFetching = 0x00100000, /* Running - fetching the Tx descriptor */ + DmaTxWaiting = 0x00200000, /* Running - waiting for status */ + DmaTxReading = 0x00300000, /* Running - reading the data from host memory */ + DmaTxSuspended = 0x00600000, /* Suspended - Tx Descriptor unavailabe */ + DmaTxClosing = 0x00700000, /* Running - closing Rx descriptor */ + + DmaRxState = 0x000E0000, /* (RS)Receive process state 19:17 RO */ + DmaRxStopped = 0x00000000, /* Stopped - Reset or Stop Rx Command issued 000 */ + DmaRxFetching = 0x00020000, /* Running - fetching the Rx descriptor */ + DmaRxWaiting = 0x00060000, /* Running - waiting for packet */ + DmaRxSuspended = 0x00080000, /* Suspended - Rx Descriptor unavailable */ + DmaRxClosing = 0x000A0000, /* Running - closing descriptor */ + DmaRxQueuing = 0x000E0000, /* Running - queuing the recieve frame into host memory */ + + DmaIntNormal = 0x00010000, /* (NIS)Normal interrupt summary 16 RW 0 */ + DmaIntAbnormal = 0x00008000, /* (AIS)Abnormal interrupt summary 15 RW 0 */ + + DmaIntEarlyRx = 0x00004000, /* Early receive interrupt (Normal) RW 0 */ + DmaIntBusError = 0x00002000, /* Fatal bus error (Abnormal) RW 0 */ + DmaIntEarlyTx = 0x00000400, /* Early transmit interrupt (Abnormal) RW 0 */ + DmaIntRxWdogTO = 0x00000200, /* Receive Watchdog Timeout (Abnormal) RW 0 */ + DmaIntRxStopped = 0x00000100, /* Receive process stopped (Abnormal) RW 0 */ + DmaIntRxNoBuffer = 0x00000080, /* Receive buffer unavailable (Abnormal) RW 0 */ + DmaIntRxCompleted = 0x00000040, /* Completion of frame reception (Normal) RW 0 */ + DmaIntTxUnderflow = 0x00000020, /* Transmit underflow (Abnormal) RW 0 */ + DmaIntRcvOverflow = 0x00000010, /* Receive Buffer overflow interrupt RW 0 */ + DmaIntTxJabberTO = 0x00000008, /* Transmit Jabber Timeout (Abnormal) RW 0 */ + DmaIntTxNoBuffer = 0x00000004, /* Transmit buffer unavailable (Normal) RW 0 */ + DmaIntTxStopped = 0x00000002, /* Transmit process stopped (Abnormal) RW 0 */ + DmaIntTxCompleted = 0x00000001, /* Transmit completed (Normal) RW 0 */ +}; + +/*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ +enum DmaControlReg { + DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ + + DmaStoreAndForward = 0x00200000, /* (SF)Store and forward 21 RW 0 */ + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ + + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ + + DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ + DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ + DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ + DmaRxStart = 0x00000002, /* (SR)Start/Stop reception 1 RW 0 */ +}; + + +/*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ +enum DmaInterruptReg { + DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ + DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ + + DmaIeEarlyRx = DmaIntEarlyRx , /* Early receive interrupt enable RW 0 */ + DmaIeBusError = DmaIntBusError , /* Fatal bus error enable RW 0 */ + DmaIeEarlyTx = DmaIntEarlyTx , /* Early transmit interrupt enable RW 0 */ + DmaIeRxWdogTO = DmaIntRxWdogTO , /* Receive Watchdog Timeout enable RW 0 */ + DmaIeRxStopped = DmaIntRxStopped , /* Receive process stopped enable RW 0 */ + DmaIeRxNoBuffer = DmaIntRxNoBuffer , /* Receive buffer unavailable enable RW 0 */ + DmaIeRxCompleted = DmaIntRxCompleted, /* Completion of frame reception enable RW 0 */ + DmaIeTxUnderflow = DmaIntTxUnderflow, /* Transmit underflow enable RW 0 */ + + DmaIeRxOverflow = DmaIntRcvOverflow, /* Receive Buffer overflow interrupt RW 0 */ + DmaIeTxJabberTO = DmaIntTxJabberTO , /* Transmit Jabber Timeout enable RW 0 */ + DmaIeTxNoBuffer = DmaIntTxNoBuffer , /* Transmit buffer unavailable enable RW 0 */ + DmaIeTxStopped = DmaIntTxStopped , /* Transmit process stopped enable RW 0 */ + DmaIeTxCompleted = DmaIntTxCompleted, /* Transmit completed enable RW 0 */ +}; + + +/********************************************************** + * DMA Engine descriptors + **********************************************************/ + +/* +**********Enhanced Descritpor structure to support 8K buffer per buffer **************************** + +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a +32 bit Data bus is as shown below + +Similarly +DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address +DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a +32 bit Data bus is as shown below + -------------------------------------------------------------------------- + RDES0 |OWN (31)| Status | + -------------------------------------------------------------------------- + RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + RDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- + RDES3 | Buffer 2 Address / Next Descriptor Address | + -------------------------------------------------------------------------- + + -------------------------------------------------------------------------- + TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | + -------------------------------------------------------------------------- + TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + TDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- + TDES3 | Buffer 2 Address / Next Descriptor Address | + -------------------------------------------------------------------------- + +*/ + +enum DmaDescriptorStatus /* status word of DMA descriptor */ +{ + + DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ + + DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ + + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ + DescFrameLengthShift = 16, + + DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ + /* DE || OE || IPC || LC || RWT || RE || CE */ + DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ + DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ + DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ + DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ + DescRxLast = 0x00000100, /* (LS)Rx - last descriptor of the frame 8 */ + DescRxLongFrame = 0x00000080, /* (Giant Frame)Rx - frame is longer than 1518/1522 7 */ + DescRxTSAvailable = 0x00000080, /* Share bit with (Giant Frame)Rx 7 */ + DescRxCollision = 0x00000040, /* (LC)Rx - late collision occurred during reception 6 */ + DescRxFrameEther = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescRxWatchdog = 0x00000010, /* (RWT)Rx - watchdog timer expired during reception 4 */ + DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ + DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ + DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ +// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ + + DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ + DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ + DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ + DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ + DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ + DescTxTSEnable = 0x02000000, /* (TTSE) Transmit Timestamp Enable 25 */ + DescTxCrcReplacement = 0x01000000, /* (CRCR) CRC Replacement Control 24 */ + DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + + TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ + TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescTxTSStatus = 0x00020000, /* (TTSS) Transmit Timestamp Status 17 */ + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ + DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ + DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ + DescTxPayChkError = 0x00001000, /* (PCE) Tx Payload checksum Error 12 */ + DescTxLostCarrier = 0x00000800, /* (LC)Tx - carrier lost during tramsmission 11 */ + DescTxNoCarrier = 0x00000400, /* (NC)Tx - no carrier signal from the tranceiver 10 */ + DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ + DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ + DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ + + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ + DescTxCollShift = 3, + + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ + DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ + DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ + + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- + + */ +// DmaDescriptorLength length word of DMA descriptor + + + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ + RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ + + + DescSize2Mask = 0x1FFF0000, /* (TBS2) Buffer 2 size 28:16 */ + DescSize2Shift = 16, + DescSize1Mask = 0x00001FFF, /* (TBS1) Buffer 1 size 12:0 */ + DescSize1Shift = 0, + + + /* + This explains the RDES4 Extended Status bits layout + -------------------------------------------------------------------- + RDES4 | Extended Status | + -------------------------------------------------------------------- + */ + + DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ + DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ + DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ + DescRxPtpMessageType = 0x00000F00, /* Message Type 11:8 */ + DescRxPtpNo = 0x00000000, /* 0000 => No PTP message received */ + DescRxPtpSync = 0x00000100, /* 0001 => Sync (all clock types) received */ + DescRxPtpFollowUp = 0x00000200, /* 0010 => Follow_Up (all clock types) received */ + DescRxPtpDelayReq = 0x00000300, /* 0011 => Delay_Req (all clock types) received */ + DescRxPtpDelayResp = 0x00000400, /* 0100 => Delay_Resp (all clock types) received */ + DescRxPtpPdelayReq = 0x00000500, /* 0101 => Pdelay_Req (in P to P tras clk) or Announce in Ord and Bound clk */ + DescRxPtpPdelayResp = 0x00000600, /* 0110 => Pdealy_Resp(in P to P trans clk) or Management in Ord and Bound clk */ + DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ + DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ + DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ + + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 + is bypassed */ + DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ + DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 + error or IP datagram version is not consistent + with Ethernet type value */ + DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 + in IPdatagram processed by COE (Rx) */ + DescRxIpPayloadUnknown= 0x00000000, /* Unknown or didnot process IP payload */ + DescRxIpPayloadUDP = 0x00000001, /* UDP */ + DescRxIpPayloadTCP = 0x00000002, /* TCP */ + DescRxIpPayloadICMP = 0x00000003, /* ICMP */ + +}; + + +// Rx Descriptor COE type2 encoding +enum RxDescCOEEncode { + RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ + RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ + RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ + RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ + RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ + RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ + RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ + RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ +}; + +/********************************************************** + * DMA engine interrupt handling functions + **********************************************************/ + +enum synopGMACDmaIntEnum /* Intrerrupt types */ +{ + synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ + synopGMACDmaRxAbnormal = 0x02, /* abnormal receiver interrupt */ + synopGMACDmaRxStopped = 0x04, /* receiver stopped */ + synopGMACDmaTxNormal = 0x08, /* normal transmitter interrupt */ + synopGMACDmaTxAbnormal = 0x10, /* abnormal transmitter interrupt */ + synopGMACDmaTxStopped = 0x20, /* transmitter stopped */ + synopGMACDmaError = 0x80, /* Dma engine error */ + +}; + + +/********************************************************** + * Initial register values + **********************************************************/ +enum InitialRegisters { + /* Full-duplex mode with perfect filter on */ + GmacConfigInitFdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Full-duplex mode with perfect filter on */ + GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff + | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Full-duplex mode */ + // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast + // Hash filter. + /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ + GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable + | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff + | GmacPromiscuousModeOff | GmacUcastHashFilterOff, + + /* Full-duplex mode */ + GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, + + /* Full-duplex mode */ + GmacGmiiAddrInitFdx = GmiiCsrClk2, + + + /* Half-duplex mode with perfect filter on */ + // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, + /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ + GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Half-duplex mode with perfect filter on */ + GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable + | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, + + /* Half-duplex mode */ + GmacFrameFilterInitHdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable + | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff + | GmacUcastHashFilterOff| GmacPromiscuousModeOff, + + /* Half-duplex mode */ + GmacFlowControlInitHdx = GmacUnicastPauseFrameOff | GmacRxFlowControlDisable | GmacTxFlowControlDisable, + + /* Half-duplex mode */ + GmacGmiiAddrInitHdx = GmiiCsrClk2, + + + + /********************************************** + *DMA configurations + **********************************************/ + + DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip2 | DmaResetOff, +// DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, + + /* 1000 Mb/s mode */ + DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , + + /* 100 Mb/s mode */ + DmaControlInit100 = DmaStoreAndForward, + + /* 10 Mb/s mode */ + DmaControlInit10 = DmaStoreAndForward, + + /* Interrupt groups */ + DmaIntErrorMask = DmaIntBusError, /* Error */ + DmaIntRxAbnMask = DmaIntRxNoBuffer, /* receiver abnormal interrupt */ + DmaIntRxNormMask = DmaIntRxCompleted, /* receiver normal interrupt */ + DmaIntRxStoppedMask = DmaIntRxStopped, /* receiver stopped */ + DmaIntTxAbnMask = DmaIntTxUnderflow, /* transmitter abnormal interrupt */ + DmaIntTxNormMask = DmaIntTxCompleted, /* transmitter normal interrupt */ + DmaIntTxStoppedMask = DmaIntTxStopped, /* transmitter stopped */ + + DmaIntEnable = DmaIeNormal | DmaIeAbnormal | DmaIntErrorMask + | DmaIntRxAbnMask | DmaIntRxNormMask | DmaIntRxStoppedMask + | DmaIntTxAbnMask | DmaIntTxNormMask | DmaIntTxStoppedMask, + DmaIntDisable = 0, +}; + + + + +/********************************************************** + * Power Management (PMT) Block + **********************************************************/ + +/** + * PMT supports the reception of network (remote) wake-up frames and Magic packet frames. + * It generates interrupts for wake-up frames and Magic packets received by GMAC. + * PMT sits in Rx path and is enabled with remote wake-up frame enable and Magic packet enable. + * These enable are in PMT control and Status register and are programmed by apllication. + * + * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes + * out of power down mode only when either Magic packe tor a Remote wake-up frame is received + * and the corresponding detection is enabled. + * + * Driver need not be modified to support this feature. Only Api to put the device in to power + * down mode is sufficient + */ + +#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ + +enum GmacPmtCtrlStatusBitDefinition { + GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ + GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ + GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ + GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ + GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ + GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ + GmacPmtPowerDown = 0x00000001, /* Power Down */ +}; + + + + +/********************************************************** + * IEEE 1588-2008 Precision Time Protocol (PTP) Support + **********************************************************/ +enum PTPMessageType { + SYNC = 0x0, + Delay_Req = 0x1, + Pdelay_Req = 0x2, + Pdelay_Resp = 0x3, + Follow_up = 0x8, + Delay_Resp = 0x9, + Pdelay_Resp_Follow_Up = 0xA, + Announce = 0xB, + Signaling = 0xC, + Management = 0xD, +}; + + + +typedef struct TimeStampStruct { + u32 TSversion; /* PTP Version 1 or PTP version2 */ + u32 TSmessagetype; /* Message type associated with this time stamp */ + + u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ + u32 TSupper32; /* Most significant 32 bit time stamp value */ + u32 TSlower32; /* Least Significat 32 bit time stamp value */ + +} TimeStamp; + + +/** + * IEEE 1588-2008 is the optional module to support Ethernet frame time stamping. + * Sixty four (+16) bit time stamps are given in each frames transmit and receive status. + * The driver assumes the following + * 1. "IEEE 1588 Time Stamping" "TIME_STAMPING"is ENABLED in corekit + * 2. "IEEE 1588 External Time Stamp Input Enable" "EXT_TIME_STAMPING" is DISABLED in corekit + * 3. "IEEE 1588 Advanced Time Stamp support" "ADV_TIME_STAMPING" is ENABLED in corekit + * 4. "IEEE 1588 Higher Word Register Enable" "ADV_TIME_HIGH_WORD" is ENABLED in corekit + */ + +/* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ +enum GmacTSControlReg { + GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ + + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ + /* + TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken + 00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP + 00/01 1 0 DELAY_REQ + 00/01 0 1 SYNC + 10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP + 10 NA 1 SYNC, FOLLOW_UP + 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP + 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP + */ + GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ + GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ + GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ + GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ + + GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ + GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ + GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ + GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ + GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ + GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ + + GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ + + GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ + + GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ + GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ + GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ + + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ + + GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ + GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ + GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + + GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ +}; + + +/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ +enum GmacTSSubSecIncrReg { + GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ +}; + +/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ +enum GmacTSSign { + GmacTSSign = 0x80000000, /* PSNT 31 RW 0 */ + GmacTSPositive = 0x00000000, + GmacTSNegative = 0x80000000, +}; + +/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ +enum GmacTSLowReg { + GmacTSDecThr = 0x3B9AC9FF, /*when TSCTRLSSR is set the max value for GmacTargetTimeLowReg and GmacTimeStampLow register is 0x3B9AC9FF at 1ns precision */ +}; + +/* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ +enum GmacTSHighWordReg { + GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ +}; +/*GmacTSStatus = 0x0728, Time Stamp Status Register */ +enum GmacTSStatusReg { + GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */ + GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ +}; + + +/********************************************************** + * Time stamp related functions + **********************************************************/ +void synopGMAC_TS_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_disable(synopGMACdevice *gmacdev); + +void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev); + +void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev); +void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type); +void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" + +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" + +s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value); +s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); +s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); + +void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled + +void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, + u32 * sec_val, u32 * sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents +void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided + +void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val); +void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val); +void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val); //Read the target time stamp register contents + + +/********************************************************** + * Common functions + **********************************************************/ +s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val); +u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev); +s32 synopGMAC_read_phy_reg(u32 *RegBase,u32 PhyBase, u32 RegOffset, u16 * data); +s32 synopGMAC_write_phy_reg(u32 *RegBase, u32 PhyBase, u32 RegOffset, u16 data); +s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback); +s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ; +s32 synopGMAC_reset (synopGMACdevice * gmacdev ); +s32 synopGMAC_reset_nocheck (synopGMACdevice * gmacdev ); +s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ); +s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value); +void synopGMAC_wd_enable(synopGMACdevice * gmacdev); +void synopGMAC_wd_disable(synopGMACdevice * gmacdev); +void synopGMAC_jab_enable(synopGMACdevice * gmacdev); +void synopGMAC_jab_disable(synopGMACdevice * gmacdev); +void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev); +void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev); +void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev); +void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev); +void synopGMAC_select_gmii(synopGMACdevice * gmacdev); +void synopGMAC_select_mii(synopGMACdevice * gmacdev); +void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev); +void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev); +void synopGMAC_loopback_on(synopGMACdevice * gmacdev); +void synopGMAC_loopback_off(synopGMACdevice * gmacdev); +void synopGMAC_set_full_duplex(synopGMACdevice * gmacdev); +void synopGMAC_set_half_duplex(synopGMACdevice * gmacdev); +void synopGMAC_retry_enable(synopGMACdevice * gmacdev); +void synopGMAC_retry_disable(synopGMACdevice * gmacdev); +void synopGMAC_pad_crc_strip_enable(synopGMACdevice * gmacdev); +void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev); +void synopGMAC_back_off_limit(synopGMACdevice * gmacdev, u32 value); +void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev); +void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev); +void synopGMAC_rx_enable(synopGMACdevice * gmacdev); +void synopGMAC_rx_disable(synopGMACdevice * gmacdev); +void synopGMAC_tx_enable(synopGMACdevice * gmacdev); +void synopGMAC_tx_disable(synopGMACdevice * gmacdev); +void synopGMAC_frame_filter_enable(synopGMACdevice * gmacdev); +void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev); +void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data); +void synopGMAC_write_hash_table_low(synopGMACdevice * gmacdev, u32 data); +void synopGMAC_hash_perfect_filter_enable(synopGMACdevice * gmacdev); +void synopGMAC_Hash_filter_only_enable(synopGMACdevice * gmacdev); +void synopGMAC_src_addr_filter_enable(synopGMACdevice * gmacdev); +void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev); +void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev); +void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev); +void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol); +void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev); +void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev); +void synopGMAC_multicast_enable(synopGMACdevice * gmacdev); +void synopGMAC_multicast_disable(synopGMACdevice * gmacdev); +void synopGMAC_multicast_hash_filter_enable(synopGMACdevice * gmacdev); +void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev); +void synopGMAC_promisc_enable(synopGMACdevice * gmacdev); +void synopGMAC_promisc_disable(synopGMACdevice * gmacdev); +void synopGMAC_unicast_hash_filter_enable(synopGMACdevice * gmacdev); +void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev); +void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev); +void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev); +void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev); +void synopGMAC_rx_flow_control_disable(synopGMACdevice * gmacdev); +void synopGMAC_tx_flow_control_enable(synopGMACdevice * gmacdev); +void synopGMAC_tx_flow_control_disable(synopGMACdevice * gmacdev); +void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev); +void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev); +void synopGMAC_pause_control(synopGMACdevice *gmacdev); +s32 synopGMAC_mac_init(synopGMACdevice * gmacdev); +s32 synopGMAC_check_phy_init (synopGMACdevice * gmacdev); +s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr); +s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr); +s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 phyBase); +void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc); +void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc); +void synopGMAC_rx_desc_init_chain(DmaDesc * desc); +void synopGMAC_tx_desc_init_chain(DmaDesc * desc); +s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev); +void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev); +void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev); +void synopGMAC_set_owner_dma(DmaDesc *desc); +void synopGMAC_set_desc_sof(DmaDesc *desc); +void synopGMAC_set_desc_eof(DmaDesc *desc); +bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc); +bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc); +bool synopGMAC_is_da_filter_failed(DmaDesc *desc); +bool synopGMAC_is_sa_filter_failed(DmaDesc *desc); +bool synopGMAC_is_desc_owned_by_dma(DmaDesc *desc); +u32 synopGMAC_get_rx_desc_frame_length(u32 status); +bool synopGMAC_is_desc_valid(u32 status); +bool synopGMAC_is_desc_empty(DmaDesc *desc); +bool synopGMAC_is_rx_desc_valid(u32 status); +bool synopGMAC_is_tx_aborted(u32 status); +bool synopGMAC_is_tx_carrier_error(u32 status); +u32 synopGMAC_get_tx_collision_count(u32 status); +u32 synopGMAC_is_exc_tx_collisions(u32 status); +bool synopGMAC_is_rx_frame_damaged(u32 status); +bool synopGMAC_is_rx_frame_collision(u32 status); +bool synopGMAC_is_rx_crc(u32 status); +bool synopGMAC_is_frame_dribbling_errors(u32 status); +bool synopGMAC_is_rx_frame_length_errors(u32 status); +bool synopGMAC_is_last_rx_desc(synopGMACdevice * gmacdev,DmaDesc *desc); +bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc); +bool synopGMAC_is_rx_desc_chained(DmaDesc * desc); +bool synopGMAC_is_tx_desc_chained(DmaDesc * desc); +void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1); + +s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); + +s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 offload_needed, u32 ts); +s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1); + +s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); + +void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev); +u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev); +u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev); +void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts); +void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev); +void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts); +void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev); +void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev); +void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev); +void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev); +void synopGMAC_take_desc_ownership(DmaDesc * desc); +void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev); +void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev); +void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev); +void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev); +/******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/ +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); +bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status); +bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status); +/*******************PMT APIs***************************************/ +void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev); +void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev); +void synopGMAC_power_down_enable(synopGMACdevice *gmacdev); +void synopGMAC_power_down_disable(synopGMACdevice *gmacdev); +void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev); +void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev); +void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev); +void synopGMAC_magic_packet_disable(synopGMACdevice *gmacdev); +void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev); +void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev); +bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev); +bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev); +void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents); + +/*******************Ip checksum offloading APIs***************************************/ +void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev); +void synopGMAC_disable_rx_chksum_offload(synopGMACdevice *gmacdev); +void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev); +void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev); +u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status); +bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status); +bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status); +void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc); +void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc); +void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc); +void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc); + + +// For testing --ya +void synopGMAC_src_addr_insert_enable(synopGMACdevice * gmacdev); +void synopGMAC_src_addr_insert_disable(synopGMACdevice * gmacdev); +void synopGMAC_src_addr_replace_enable(synopGMACdevice * gmacdev); +void synopGMAC_src_addr_replace_disable(synopGMACdevice * gmacdev); + +void synopGMAC_svlan_insertion_enable(synopGMACdevice * gmacdev, u16 vlantag); +void synopGMAC_cvlan_insertion_enable(synopGMACdevice * gmacdev, u16 vlantag); +void synopGMAC_svlan_replace_enable(synopGMACdevice * gmacdev, u16 vlantag); +void synopGMAC_cvlan_replace_enable(synopGMACdevice * gmacdev, u16 vlantag); +void synopGMAC_vlan_deletion_enable(synopGMACdevice * gmacdev); +void synopGMAC_vlan_no_act_enable(synopGMACdevice * gmacdev); + +void synopGMAC_set_crc_replacement(synopGMACdevice * gmacdev); +void synopGMAC_clr_crc_replacement(synopGMACdevice * gmacdev); + +void synopGMAC_enable_under_size_pkt(synopGMACdevice * gmacdev); +void synopGMAC_disable_under_size_pkt(synopGMACdevice * gmacdev); + +void synopGMAC_enable_crc_err_pkt(synopGMACdevice * gmacdev); +void synopGMAC_disable_crc_err_pkt(synopGMACdevice * gmacdev); + +#endif /* End of file */ diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_network_interface.c b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_network_interface.c new file mode 100644 index 0000000..53d7c3d --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_network_interface.c @@ -0,0 +1,942 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + + +/** \file + * This is the network dependent layer to handle network related functionality. + * This file is tightly coupled to neworking frame work of linux 2.6.xx kernel. + * The functionality carried out in this file should be treated as an example only + * if the underlying operating system is not Linux. + * + * \note Many of the functions other than the device specific functions + * changes for operating system other than Linux 2.6.xx + * \internal + *-----------------------------REVISION HISTORY----------------------------------- + * Synopsys 01/Aug/2007 Created + */ + +#include "string.h" +#include "synopGMAC_network_interface.h" + + +synopGMACdevice GMACdev[GMAC_CNT]; +static DmaDesc tx_desc[GMAC_CNT][TRANSMIT_DESC_SIZE] __attribute__ ((aligned (64))); +static DmaDesc rx_desc[GMAC_CNT][RECEIVE_DESC_SIZE] __attribute__ ((aligned (64))); + +//static struct sk_buff tx_buf[GMAC_CNT][TRANSMIT_DESC_SIZE] __attribute__ ((aligned (64))); +//static struct sk_buff rx_buf[GMAC_CNT][RECEIVE_DESC_SIZE] __attribute__ ((aligned (64))); +struct sk_buff tx_buf[GMAC_CNT][TRANSMIT_DESC_SIZE] __attribute__ ((aligned (64))); +struct sk_buff rx_buf[GMAC_CNT][RECEIVE_DESC_SIZE] __attribute__ ((aligned (64))); + +// These 2 are accessable from application +struct sk_buff txbuf[GMAC_CNT] __attribute__ ((aligned (64))); // set align to separate cacheable and non-cacheable data to different cache line. +struct sk_buff rxbuf[GMAC_CNT] __attribute__ ((aligned (64))); + +u8 mac_addr0[6] = DEFAULT_MAC0_ADDRESS; +u8 mac_addr1[6] = DEFAULT_MAC1_ADDRESS; + +//static struct timer_list synopGMAC_cable_unplug_timer; +//static u32 GMAC_Power_down; // This global variable is used to indicate the ISR whether the interrupts occured in the process of powering down the mac or not + + +/** + * Function used to detect the cable plugging and unplugging. + * This function gets scheduled once in every second and polls + * the PHY register for network cable plug/unplug. Once the + * connection is back the GMAC device is configured as per + * new Duplex mode and Speed of the connection. + * @param[in] u32 type but is not used currently. + * \return returns void. + * \note This function is tightly coupled with Linux 2.6.xx. + * \callgraph + */ + + + +void synopGMAC_powerdown_mac(synopGMACdevice *gmacdev) +{ + TR0("Put the GMAC to power down mode..\n"); + // Disable the Dma engines in tx path + gmacdev->GMAC_Power_down = 1; // Let ISR know that Mac is going to be in the power down mode + synopGMAC_disable_dma_tx(gmacdev); + plat_delay(10000); //allow any pending transmission to complete + // Disable the Mac for both tx and rx + synopGMAC_tx_disable(gmacdev); + synopGMAC_rx_disable(gmacdev); + plat_delay(10000); //Allow any pending buffer to be read by host + //Disable the Dma in rx path + synopGMAC_disable_dma_rx(gmacdev); + + //enable the power down mode + //synopGMAC_pmt_unicast_enable(gmacdev); + + //prepare the gmac for magic packet reception and wake up frame reception + synopGMAC_magic_packet_enable(gmacdev); + + //gate the application and transmit clock inputs to the code. This is not done in this driver :). + + //enable the Mac for reception + synopGMAC_rx_enable(gmacdev); + + //Enable the assertion of PMT interrupt + synopGMAC_pmt_int_enable(gmacdev); + //enter the power down mode + synopGMAC_power_down_enable(gmacdev); + return; +} + +void synopGMAC_powerup_mac(synopGMACdevice *gmacdev) +{ + gmacdev->GMAC_Power_down = 0; // Let ISR know that MAC is out of power down now + if( synopGMAC_is_magic_packet_received(gmacdev)) + TR("GMAC wokeup due to Magic Pkt Received\n"); + if(synopGMAC_is_wakeup_frame_received(gmacdev)) + TR("GMAC wokeup due to Wakeup Frame Received\n"); + //Disable the assertion of PMT interrupt + synopGMAC_pmt_int_disable(gmacdev); + //Enable the mac and Dma rx and tx paths + synopGMAC_rx_enable(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); + + synopGMAC_tx_enable(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + return; +} + +/** + * This sets up the transmit Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Device is interested only after the descriptors are setup. Therefore this function + * is not included in the device driver API. This function should be treated as an + * example code to design the descriptor structures for ring mode or chain mode. + * This function depends on the pcidev structure for allocation consistent dma-able memory in case of linux. + * This limitation is due to the fact that linux uses pci structure to allocate a dmable memory + * - Allocates the memory for the descriptors. + * - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor). + * - Initialize the Busy and Next descriptors to first descriptor address. + * - Initialize the last descriptor with the endof ring in case of ring mode. + * - Initialize the descriptors in chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in tx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note This function fails if allocation fails for required number of descriptors in Ring mode, but in chain mode + * function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from this function + * user should for gmacdev->TxDescCount to see how many descriptors are there in the chain. Should continue further + * only if the number of descriptors in the chain meets the requirements + */ + +s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode) +{ + s32 i; + + DmaDesc *first_desc = &tx_desc[gmacdev->Intf][0]; + dma_addr_t dma_addr; + gmacdev->TxDescCount = 0; + + TR("Total size of memory required for Tx Descriptors in Ring Mode = 0x%08x\n",((sizeof(DmaDesc) * no_of_desc))); + + gmacdev->TxDescCount = no_of_desc; + gmacdev->TxDesc = first_desc; +#ifdef CACHE_ON + gmacdev->TxDescDma = (DmaDesc *)((u64)first_desc | 0x100000000); +#else + gmacdev->TxDescDma = (DmaDesc *)((u64)first_desc); +#endif + for(i =0; i < gmacdev -> TxDescCount; i++) { + synopGMAC_tx_desc_init_ring(gmacdev->TxDescDma + i, i == gmacdev->TxDescCount-1); + TR("%02d %08x \n",i, (unsigned int)(gmacdev->TxDesc + i) ); + } + + + gmacdev->TxNext = 0; + gmacdev->TxBusy = 0; + gmacdev->TxNextDesc = gmacdev->TxDesc; + gmacdev->TxBusyDesc = gmacdev->TxDesc; + gmacdev->BusyTxDesc = 0; + + return 0; +} + + +/** + * This sets up the receive Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Device is interested only after the descriptors are setup. Therefore this function + * is not included in the device driver API. This function should be treated as an + * example code to design the descriptor structures in ring mode or chain mode. + * This function depends on the pcidev structure for allocation of consistent dma-able memory in case of linux. + * This limitation is due to the fact that linux uses pci structure to allocate a dmable memory + * - Allocates the memory for the descriptors. + * - Initialize the Busy and Next descriptors indices to 0(Indicating first descriptor). + * - Initialize the Busy and Next descriptors to first descriptor address. + * - Initialize the last descriptor with the endof ring in case of ring mode. + * - Initialize the descriptors in chain mode. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in rx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note This function fails if allocation fails for required number of descriptors in Ring mode, but in chain mode + * function returns -ESYNOPGMACNOMEM in the process of descriptor chain creation. once returned from this function + * user should for gmacdev->RxDescCount to see how many descriptors are there in the chain. Should continue further + * only if the number of descriptors in the chain meets the requirements + */ +s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode) +{ + s32 i; + + DmaDesc *first_desc = &rx_desc[gmacdev->Intf][0]; + dma_addr_t dma_addr; + gmacdev->RxDescCount = 0; + + + TR("total size of memory required for Rx Descriptors in Ring Mode = 0x%08x\n",((sizeof(DmaDesc) * no_of_desc))); + + gmacdev->RxDescCount = no_of_desc; + gmacdev->RxDesc = first_desc; +#ifdef CACHE_ON + gmacdev->RxDescDma = (DmaDesc *)((u64)first_desc | 0x100000000); +#else + gmacdev->RxDescDma = (DmaDesc *)((u64)first_desc); +#endif + for(i =0; i < gmacdev -> RxDescCount; i++) { + synopGMAC_rx_desc_init_ring(gmacdev->RxDescDma + i, i == gmacdev->RxDescCount-1); + TR("%02d %08x \n",i, (unsigned int)(gmacdev->RxDesc + i)); + } + + + gmacdev->RxNext = 0; + gmacdev->RxBusy = 0; + gmacdev->RxNextDesc = gmacdev->RxDesc; + gmacdev->RxBusyDesc = gmacdev->RxDesc; + + gmacdev->BusyRxDesc = 0; + + return 0; +} + + +/** + * This gives up the receive Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Once device's Dma is stopped the memory descriptor memory and the buffer memory deallocation, + * is completely handled by the operating system, this call is kept outside the device driver Api. + * This function should be treated as an example code to de-allocate the descriptor structures in ring mode or chain mode + * and network buffer deallocation. + * This function depends on the pcidev structure for dma-able memory deallocation for both descriptor memory and the + * network buffer memory under linux. + * The responsibility of this function is to + * - Free the network buffer memory if any. + * - Fee the memory allocated for the descriptors. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in rx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note No referece should be made to descriptors once this function is called. This function is invoked when the device is closed. + */ +void synopGMAC_giveup_rx_desc_queue(synopGMACdevice * gmacdev, u32 desc_mode) +{ + gmacdev->RxDesc = NULL; + gmacdev->RxDescDma = 0; + return; +} + +/** + * This gives up the transmit Descriptor queue in ring or chain mode. + * This function is tightly coupled to the platform and operating system + * Once device's Dma is stopped the memory descriptor memory and the buffer memory deallocation, + * is completely handled by the operating system, this call is kept outside the device driver Api. + * This function should be treated as an example code to de-allocate the descriptor structures in ring mode or chain mode + * and network buffer deallocation. + * This function depends on the pcidev structure for dma-able memory deallocation for both descriptor memory and the + * network buffer memory under linux. + * The responsibility of this function is to + * - Free the network buffer memory if any. + * - Fee the memory allocated for the descriptors. + * @param[in] pointer to synopGMACdevice. + * @param[in] pointer to pci_device structure. + * @param[in] number of descriptor expected in tx descriptor queue. + * @param[in] whether descriptors to be created in RING mode or CHAIN mode. + * \return 0 upon success. Error code upon failure. + * \note No reference should be made to descriptors once this function is called. This function is invoked when the device is closed. + */ +void synopGMAC_giveup_tx_desc_queue(synopGMACdevice * gmacdev, u32 desc_mode) +{ + + + gmacdev->TxDesc = NULL; + gmacdev->TxDescDma = 0; + return; +} + +/** + * Function to handle housekeeping after a packet is transmitted over the wire. + * After the transmission of a packet DMA generates corresponding interrupt + * (if it is enabled). It takes care of returning the sk_buff to the linux + * kernel, updating the networking statistics and tracking the descriptors. + * @param[in] pointer to net_device structure. + * \return void. + * \note This function runs in interrupt context + */ +void synop_handle_transmit_over(int intf) +{ + synopGMACdevice * gmacdev; + s32 desc_index; + u32 data1; + u32 status; + u32 length1; + u32 dma_addr1; + + u32 ext_status; + //u16 time_stamp_higher; + u32 time_stamp_high; + u32 time_stamp_low; + + + gmacdev = &GMACdev[intf]; + + /*Handle the transmit Descriptors*/ + do { + + desc_index = synopGMAC_get_tx_qptr(gmacdev, &status, &dma_addr1, &length1, &data1,&ext_status,&time_stamp_high,&time_stamp_low); + //synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher); + + if(desc_index >= 0 /*&& data1 != 0*/) { + TR("Finished Transmit at Tx Descriptor %d for skb 0x%08x and buffer = %08x whose status is %08x \n", desc_index,data1,dma_addr1,status); + + if(synopGMAC_is_tx_ipv4header_checksum_error(gmacdev, status)) { + TR("Harware Failed to Insert IPV4 Header Checksum\n"); + gmacdev->synopGMACNetStats.tx_ip_header_errors++; + } + if(synopGMAC_is_tx_payload_checksum_error(gmacdev, status)) { + TR("Harware Failed to Insert Payload Checksum\n"); + gmacdev->synopGMACNetStats.tx_ip_payload_errors++; + } + + + + if(synopGMAC_is_desc_valid(status)) { + gmacdev->synopGMACNetStats.tx_bytes += length1; + gmacdev->synopGMACNetStats.tx_packets++; + if(status & DescTxTSStatus) { + gmacdev->tx_sec = time_stamp_high; + gmacdev->tx_subsec = time_stamp_low; + } else { + gmacdev->tx_sec = 0; + gmacdev->tx_subsec = 0; + } + } else { + TR("Error in Status %08x\n",status); + gmacdev->synopGMACNetStats.tx_errors++; + gmacdev->synopGMACNetStats.tx_aborted_errors += synopGMAC_is_tx_aborted(status); + gmacdev->synopGMACNetStats.tx_carrier_errors += synopGMAC_is_tx_carrier_error(status); + } + } + gmacdev->synopGMACNetStats.collisions += synopGMAC_get_tx_collision_count(status); + } while(desc_index >= 0); + +} + + + + +/** + * Function to Receive a packet from the interface. + * After Receiving a packet, DMA transfers the received packet to the system memory + * and generates corresponding interrupt (if it is enabled). This function prepares + * the sk_buff for received packet after removing the ethernet CRC, and hands it over + * to linux networking stack. + * - Updataes the networking interface statistics + * - Keeps track of the rx descriptors + * @param[in] pointer to net_device structure. + * \return void. + * \note This function runs in interrupt context. + */ +extern DmaDesc * prevtx; // for CRC test +s32 synop_handle_received_data(int intf, u8 **buf) // Chris, to get RX buffer pointer +{ + + synopGMACdevice * gmacdev; + s32 desc_index; + + u32 data1; + u32 len = 0; + u32 status; + u32 dma_addr1; + + u32 ext_status; + //u16 time_stamp_higher; + u32 time_stamp_high; + u32 time_stamp_low; + struct sk_buff *rb = &rxbuf[intf]; + + //struct sk_buff *skb; //This is the pointer to hold the received data + + TR("%s\n",__FUNCTION__); + + + + gmacdev = &GMACdev[intf]; + + /*Handle the Receive Descriptors*/ + do { + + desc_index = synopGMAC_get_rx_qptr(gmacdev, &status, + &dma_addr1, NULL, &data1, + &ext_status, &time_stamp_high, &time_stamp_low); + if(desc_index >0) { + //synopGMAC_TS_read_timestamp_higher_val(gmacdev, &time_stamp_higher); + //TR("S:%08x ES:%08x DA1:%08x d1:%08x TSH:%08x TSL:%08x TSHW:%08x \n",status,ext_status,dma_addr1, data1,time_stamp_high,time_stamp_low,time_stamp_higher); + TR("S:%08x ES:%08x DA1:%08x d1:%08x TSH:%08x TSL:%08x\n",status,ext_status,dma_addr1, data1,time_stamp_high,time_stamp_low); + } + + if(desc_index >= 0 /*&& data1 != 0*/) { + TR("Received Data at Rx Descriptor %d for skb 0x%08x whose status is %08x\n",desc_index,data1,status); + + + //skb = (struct sk_buff *)((u64)data1); + if(1/*synopGMAC_is_rx_desc_valid(status)*/) { + // Always enter this loop. synopGMAC_is_rx_desc_valid() also report invalid descriptor + // if there's packet error generated by test code and drop it. But we need to execute ext_status + // check code to tell what's going on. --ya + + len = synopGMAC_get_rx_desc_frame_length(status) - 4; //Not interested in Ethernet CRC bytes + + + // Now lets check for the IPC offloading + /* Since we have enabled the checksum offloading in hardware, lets inform the kernel + not to perform the checksum computation on the incoming packet. Note that ip header + checksum will be computed by the kernel immaterial of what we inform. Similary TCP/UDP/ICMP + pseudo header checksum will be computed by the stack. What we can inform is not to perform + payload checksum. + When CHECKSUM_UNNECESSARY is set kernel bypasses the checksum computation. + */ + + TR("Checksum Offloading will be done now\n"); + + if(synopGMAC_is_ext_status(gmacdev, status)) { // extended status present indicates that the RDES4 need to be probed + TR("Extended Status present\n"); + if(synopGMAC_ES_is_IP_header_error(gmacdev,ext_status)) { // IP header (IPV4) checksum error + //Linux Kernel doesnot care for ipv4 header checksum. So we will simply proceed by printing a warning .... + TR("(EXTSTS)Error in IP header error\n"); + gmacdev->synopGMACNetStats.rx_ip_header_errors++; + } + if(synopGMAC_ES_is_rx_checksum_bypassed(gmacdev,ext_status)) { // Hardware engine bypassed the checksum computation/checking + TR("(EXTSTS)Hardware bypassed checksum computation\n"); + } + if(synopGMAC_ES_is_IP_payload_error(gmacdev,ext_status)) { // IP payload checksum is in error (UDP/TCP/ICMP checksum error) + TR("(EXTSTS) Error in EP payload\n"); + gmacdev->synopGMACNetStats.rx_ip_payload_errors++; + } + } else { // No extended status. So relevant information is available in the status itself + if(synopGMAC_is_rx_checksum_error(gmacdev, status) == RxNoChkError ) { + TR("Ip header and TCP/UDP payload checksum Bypassed \n"); + } + if(synopGMAC_is_rx_checksum_error(gmacdev, status) == RxIpHdrChkError ) { + //Linux Kernel doesnot care for ipv4 header checksum. So we will simply proceed by printing a warning .... + TR(" Error in 16bit IPV4 Header Checksum \n"); + gmacdev->synopGMACNetStats.rx_ip_header_errors++; + } + if(synopGMAC_is_rx_checksum_error(gmacdev, status) == RxLenLT600 ) { + TR("IEEE 802.3 type frame with Length field Lesss than 0x0600 \n"); + } + if(synopGMAC_is_rx_checksum_error(gmacdev, status) == RxIpHdrPayLoadChkBypass ) { + TR("Ip header and TCP/UDP payload checksum Bypassed \n"); + } + if(synopGMAC_is_rx_checksum_error(gmacdev, status) == RxChkBypass ) { + TR("Ip header and TCP/UDP payload checksum Bypassed \n"); + } + if(synopGMAC_is_rx_checksum_error(gmacdev, status) == RxPayLoadChkError ) { + TR(" TCP/UDP payload checksum Error \n"); + gmacdev->synopGMACNetStats.rx_ip_payload_errors++; + } + if(synopGMAC_is_rx_checksum_error(gmacdev, status) == RxIpHdrPayLoadChkError ) { + //Linux Kernel doesnot care for ipv4 header checksum. So we will simply proceed by printing a warning .... + TR(" Both IP header and Payload Checksum Error \n"); + gmacdev->synopGMACNetStats.rx_ip_header_errors++; + gmacdev->synopGMACNetStats.rx_ip_payload_errors++; + } + } +#if 0 +#ifdef CACHE_ON + memcpy((void *)rb->data, (void *)((u64)dma_addr1 | 0x100000000), len); +#else + memcpy((void *)rb->data, (void *)((u64)dma_addr1), len); +#endif + if(prevtx != NULL) { +#ifdef CACHE_ON + memcpy((void *)(rb->data + len), (void *)((u64)(dma_addr1 | 0x100000000) + len), 4); +#else + memcpy((void *)(rb->data + len), (void *)((u64)dma_addr1 + len), 4); +#endif + } +#else + *buf = (u8 *)(u32)((u64)dma_addr1); +#endif + rb->rdy = 1; + rb->len = len; + gmacdev->synopGMACNetStats.rx_packets++; + gmacdev->synopGMACNetStats.rx_bytes += len; + if(status & DescRxTSAvailable) { + gmacdev->rx_sec = time_stamp_high; + gmacdev->rx_subsec = time_stamp_low; + } else { + gmacdev->rx_sec = 0; + gmacdev->rx_subsec = 0; + } + } else { + /*Now the present skb should be set free*/ + TR("s: %08x\n",status); + gmacdev->synopGMACNetStats.rx_errors++; + gmacdev->synopGMACNetStats.collisions += synopGMAC_is_rx_frame_collision(status); + gmacdev->synopGMACNetStats.rx_crc_errors += synopGMAC_is_rx_crc(status); + gmacdev->synopGMACNetStats.rx_frame_errors += synopGMAC_is_frame_dribbling_errors(status); + gmacdev->synopGMACNetStats.rx_length_errors += synopGMAC_is_rx_frame_length_errors(status); + } + } + } while(0); //while(desc_index >= 0); + return len; +} + +u32 volatile LPIStsChange = 0; +u32 volatile LPIReg = 0; +/** + * Interrupt service routing. + * This is the function registered as ISR for device interrupts. + * @param[in] interrupt number. + * @param[in] void pointer to device unique structure (Required for shared interrupts in Linux). + * @param[in] pointer to pt_regs (not used). + * \return Returns IRQ_NONE if not device interrupts IRQ_HANDLED for device interrupts. + * \note This function runs in interrupt context + * + */ +void synopGMAC0_intr_handler(void) +{ + synopGMACdevice * gmacdev = &GMACdev[0]; + u32 interrupt,dma_status_reg, mac_status_reg; + s32 status; + u32 dma_addr; + + // Check GMAC interrupt + mac_status_reg = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacInterruptStatus); + if(mac_status_reg & GmacTSIntSts) { + gmacdev->synopGMACNetStats.ts_int = 1; + status = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacTSStatus); + if(!(status & (1 << 1))) + printf("TS alarm flag not set??\n"); + else + printf("TS alarm!!!!!!!!!!!!!!!!\n"); + + } + if(mac_status_reg & GmacLPIIntSts) { + //printf("LPI\n"); + LPIStsChange = 1; + LPIReg = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacLPICtrlSts); + + } + if(mac_status_reg & GmacRgmiiIntSts) { + u32 volatile reg; + reg = synopGMACReadReg((u32 *)gmacdev->MacBase, GmacRgmiiCtrlSts); + + } + synopGMACWriteReg((u32 *)gmacdev->MacBase, GmacInterruptStatus ,mac_status_reg); + + /*Read the Dma interrupt status to know whether the interrupt got generated by our device or not*/ + dma_status_reg = synopGMACReadReg((u32 *)gmacdev->DmaBase, DmaStatus); + //printf("i"); + //printf("i %08x %08x\n", mac_status_reg, dma_status_reg); + + if(dma_status_reg == 0) + return; + + synopGMAC_disable_interrupt_all(gmacdev); + + TR("%s:Dma Status Reg: 0x%08x\n",__FUNCTION__,dma_status_reg); + + if(dma_status_reg & GmacPmtIntr) { + TR("%s:: Interrupt due to PMT module\n",__FUNCTION__); + synopGMAC_powerup_mac(gmacdev); + } + + if(dma_status_reg & GmacLineIntfIntr) { + TR("%s:: Interrupt due to GMAC LINE module\n",__FUNCTION__); + } + + /*Now lets handle the DMA interrupts*/ + interrupt = synopGMAC_get_interrupt_type(gmacdev); + TR("%s:Interrupts to be handled: 0x%08x\n",__FUNCTION__,interrupt); + + + if(interrupt & synopGMACDmaError) { + + TR("%s::Fatal Bus Error Inetrrupt Seen\n",__FUNCTION__); + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_disable_dma_rx(gmacdev); + + synopGMAC_take_desc_ownership_tx(gmacdev); + synopGMAC_take_desc_ownership_rx(gmacdev); + + synopGMAC_init_tx_rx_desc_queue(gmacdev); + + synopGMAC_reset(gmacdev);//reset the DMA engine and the GMAC ip + + synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, gmacdev->Intf == 0 ? mac_addr0 : mac_addr1); + synopGMAC_dma_bus_mode_init(gmacdev,DmaFixedBurstEnable| DmaBurstLength8 | DmaDescriptorSkip0/*DmaDescriptorSkip2*/ ); + synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward); + synopGMAC_init_rx_desc_base(gmacdev); + synopGMAC_init_tx_desc_base(gmacdev); + synopGMAC_mac_init(gmacdev); + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + + } + + + if(interrupt & synopGMACDmaRxNormal) { + u8 **buf + //printf("rx\n"); + TR("%s:: Rx Normal \n", __FUNCTION__); + synop_handle_received_data(0, buf); // Chris, to get RX buffer pointer + } + + if(interrupt & synopGMACDmaRxAbnormal) { + TR("%s::Abnormal Rx Interrupt Seen\n",__FUNCTION__); + gmacdev->synopGMACNetStats.rx_over_errors++; +#if 1 + + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + synopGMAC_resume_dma_rx(gmacdev);//To handle GBPS with 12 descriptors + } +#endif + } + + if(interrupt & synopGMACDmaRxStopped) { + TR("%s::Receiver stopped seeing Rx interrupts\n",__FUNCTION__); //Receiver gone in to stopped state +#if 1 + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + gmacdev->synopGMACNetStats.rx_over_errors++; + synopGMAC_enable_dma_rx(gmacdev); + } +#endif + } + + if(interrupt & synopGMACDmaTxNormal) { + //printf("tx\n"); + //xmit function has done its job + TR("%s::Finished Normal Transmission \n",__FUNCTION__); + synop_handle_transmit_over(0);//Do whatever you want after the transmission is over + + + } + + if(interrupt & synopGMACDmaTxAbnormal) { + TR("%s::Abnormal Tx Interrupt Seen\n",__FUNCTION__); +#if 1 + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + synop_handle_transmit_over(0); + } +#endif + } + + + + if(interrupt & synopGMACDmaTxStopped) { + TR("%s::Transmitter stopped sending the packets\n",__FUNCTION__); +#if 1 + if(gmacdev->GMAC_Power_down == 0) { // If Mac is not in powerdown + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_take_desc_ownership_tx(gmacdev); + + synopGMAC_enable_dma_tx(gmacdev); + TR("%s::Transmission Resumed\n",__FUNCTION__); + } +#endif + } + + /* Enable the interrupt before returning from ISR*/ + synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + return; +} + +void synopGMAC_set_speed(int intf) +{ + + synopGMACdevice *gmacdev = &GMACdev[intf]; + + switch (gmacdev->Speed) { + case SPEED1000: + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacMiiGmii); + break; + case SPEED100: + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacMiiGmii); + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacFESpeed100); + break; + case SPEED10: + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacMiiGmii); + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacFESpeed100); + default: + break; + } + +} + +/** + * Function used when the interface is opened for use. + * We register synopGMAC_linux_open function to linux open(). Basically this + * function prepares the the device for operation . This function is called whenever ifconfig (in Linux) + * activates the device (for example "ifconfig eth0 up"). This function registers + * system resources needed + * - Attaches device to device specific structure + * - Programs the MDC clock for PHY configuration + * - Check and initialize the PHY interface + * - ISR registration + * - Setup and initialize Tx and Rx descriptors + * - Initialize MAC and DMA + * - Allocate Memory for RX descriptors (The should be DMAable) + * - Initialize one second timer to detect cable plug/unplug + * - Configure and Enable Interrupts + * - Enable Tx and Rx + * - start the Linux network queue interface + * @param[in] pointer to net_device structure. + * \return Returns 0 on success and error status upon failure. + * \callgraph + */ + +s32 synopGMAC_open(int intf) +{ + //s32 status = 0; + s32 retval = 0; + s32 i; + //s32 reserve_len=2; + u32 dma_addr; + struct sk_buff *skb; + synopGMACdevice * gmacdev = &GMACdev[intf]; + + /*Attach the device to MAC struct This will configure all the required base addresses + such as Mac base, configuration base, phy base address(out of 32 possible phys )*/ + if(intf == 0) + synopGMAC_attach(gmacdev, GMAC0MappedAddr + MACBASE, GMAC0MappedAddr + DMABASE, DEFAULT_PHY_BASE); + else + synopGMAC_attach(gmacdev, GMAC1MappedAddr + MACBASE, GMAC1MappedAddr + DMABASE, DEFAULT_PHY_BASE); + + synopGMAC_reset(gmacdev); // Reset to make RGMII/RMII setting take affect --ya + gmacdev->Intf = intf; + /*Lets read the version of ip in to device structure*/ + synopGMAC_read_version(gmacdev); + + /*Check for Phy initialization*/ + synopGMAC_set_mdc_clk_div(gmacdev,GmiiCsrClk5); + //synopGMAC_set_mdc_clk_div(gmacdev, (GmiiCsrClk2|BIT5)); + gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev); + //status = synopGMAC_check_phy_init(gmacdev); + synopGMAC_check_phy_init(gmacdev); + + /*Set up the tx and rx descriptor queue/ring*/ + + synopGMAC_setup_tx_desc_queue(gmacdev,TRANSMIT_DESC_SIZE, RINGMODE); + synopGMAC_init_tx_desc_base(gmacdev); //Program the transmit descriptor base address in to DmaTxBase addr + + synopGMAC_setup_rx_desc_queue(gmacdev,RECEIVE_DESC_SIZE, RINGMODE); + synopGMAC_init_rx_desc_base(gmacdev); //Program the transmit descriptor base address in to DmaTxBase addr + + + synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip0/*DmaDescriptorSkip2*/ | DmaDescriptor8Words ); //pbl32 incr with rxthreshold 128 and Desc is 8 Words + + synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward |DmaTxSecondFrame|DmaRxThreshCtrl128); + + /*Initialize the mac interface*/ + + synopGMAC_mac_init(gmacdev); + synopGMAC_promisc_enable(gmacdev); + + synopGMAC_pause_control(gmacdev); // This enables the pause control in Full duplex mode of operation + +#if 0 + /*IPC Checksum offloading is enabled for this driver. Should only be used if Full Ip checksumm offload engine is configured in the hardware*/ + synopGMAC_enable_rx_chksum_offload(gmacdev); //Enable the offload engine in the receive path + synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); // This is default configuration, DMA drops the packets if error in encapsulated ethernet payload +#endif + + for(i = 0; i < RECEIVE_DESC_SIZE; i ++) { + skb = &rx_buf[intf][i]; + synopGMAC_set_rx_qptr(gmacdev, (u32)((u64)(skb->data) & 0xFFFFFFFF), sizeof(skb->data), (u32)((u64)skb & 0xFFFFFFFF)); + } + + synopGMAC_clear_interrupt(gmacdev); + + synopGMAC_enable_interrupt(gmacdev,DmaIntEnable); + synopGMAC_enable_dma_rx(gmacdev); + synopGMAC_enable_dma_tx(gmacdev); + + + synopGMAC_set_mac_address(intf, intf == 0 ? mac_addr0 : mac_addr1); + + + return 0; + +} + +/** + * Function used when the interface is closed. + * + * This function is registered to linux stop() function. This function is + * called whenever ifconfig (in Linux) closes the device (for example "ifconfig eth0 down"). + * This releases all the system resources allocated during open call. + * system resources int needs + * - Disable the device interrupts + * - Stop the receiver and get back all the rx descriptors from the DMA + * - Stop the transmitter and get back all the tx descriptors from the DMA + * - Stop the Linux network queue interface + * - Free the irq (ISR registered is removed from the kernel) + * - Release the TX and RX descripor memory + * - De-initialize one second timer rgistered for cable plug/unplug tracking + * @param[in] pointer to net_device structure. + * \return Returns 0 on success and error status upon failure. + * \callgraph + */ + +s32 synopGMAC_close(int intf) +{ + + synopGMACdevice * gmacdev = &GMACdev[intf];; + + //TR0("%s\n",__FUNCTION__); + + /*Disable all the interrupts*/ + synopGMAC_disable_interrupt_all(gmacdev); + + + TR("the synopGMAC interrupt has been disabled\n"); + + /*Disable the reception*/ + synopGMAC_disable_dma_rx(gmacdev); + synopGMAC_take_desc_ownership_rx(gmacdev); + TR("the synopGMAC Reception has been disabled\n"); + + /*Disable the transmission*/ + synopGMAC_disable_dma_tx(gmacdev); + synopGMAC_take_desc_ownership_tx(gmacdev); + + TR("the synopGMAC interrupt handler has been removed\n"); + + /*Free the Rx Descriptor contents*/ + TR("Now calling synopGMAC_giveup_rx_desc_queue \n"); + synopGMAC_giveup_rx_desc_queue(gmacdev, RINGMODE); + + TR("Now calling synopGMAC_giveup_tx_desc_queue \n"); + synopGMAC_giveup_tx_desc_queue(gmacdev, RINGMODE); + + return 0; + +} + + +/** + * Function to transmit a given packet on the wire. + * Whenever Linux Kernel has a packet ready to be transmitted, this function is called. + * The function prepares a packet and prepares the descriptor and + * enables/resumes the transmission. + * @param[in] pointer to sk_buff structure. + * @param[in] pointer to net_device structure. + * \return Returns 0 on success and Error code on failure. + * \note structure sk_buff is used to hold packet in Linux networking stacks. + */ +s32 synopGMAC_xmit_frames(struct sk_buff *skb, int intf, u32 offload_needed, u32 ts) +{ + s32 status = 0; + + u32 dma_addr = (u32)((u64)skb->data & 0xFFFFFFFF); + + synopGMACdevice * gmacdev; + + + gmacdev = &GMACdev[intf]; + + /*Now we have skb ready and OS invoked this function. Lets make our DMA know about this*/ + status = synopGMAC_set_tx_qptr(gmacdev, dma_addr, skb->len, (u32)((u64)skb & 0xFFFFFFFF), offload_needed, ts); + if(status < 0) { + TR0("%s No More Free Tx Descriptors\n",__FUNCTION__); + return -1; + } + + /*Now force the DMA to start transmission*/ + synopGMAC_resume_dma_tx(gmacdev); + + + return 0; +} + + +/** + * Function to set ethernet address of the NIC. + * @param[in] pointer to net_device structure. + * @param[in] pointer to an address structure. + * \return Returns 0 on success Errorcode on failure. + */ +s32 synopGMAC_set_mac_address(int intf, u8* macaddr) +{ + + + synopGMACdevice * gmacdev = NULL; + + gmacdev = &GMACdev[intf]; + + + synopGMAC_set_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, macaddr); + + return 0; +} + +// mode 0: 1000Mbps, 1: 100Mbps, 2: 10Mbps + +void synopGMAC_set_mode(int intf, int mode) +{ + + synopGMACdevice *gmacdev = &GMACdev[intf]; + + // Must stop Tx/Rx before change speed/mode + synopGMAC_tx_disable(gmacdev); + synopGMAC_rx_disable(gmacdev); + switch (mode) { + case 0: + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacMiiGmii); + gmacdev->Speed = SPEED1000; + break; + case 1: + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacMiiGmii); + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacFESpeed100); + gmacdev->Speed = SPEED100; + break; + case 2: + synopGMACSetBits((u32 *)gmacdev->MacBase,GmacConfig,GmacMiiGmii); + synopGMACClearBits((u32 *)gmacdev->MacBase,GmacConfig,GmacFESpeed100); + gmacdev->Speed = SPEED10; + default: + break; + } + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); +} + diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_network_interface.h b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_network_interface.h new file mode 100644 index 0000000..0c95eee --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_network_interface.h @@ -0,0 +1,63 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + +/** \file + * Header file for the nework dependent functionality. + * The function prototype listed here are linux dependent. + * + * \internal + * ---------------------------REVISION HISTORY------------------- + * Synopsys 01/Aug/2007 Created + */ +#include "synopGMAC_Dev.h" + + +#ifndef SYNOP_GMAC_NETWORK_INTERFACE_H +#define SYNOP_GMAC_NETWORK_INTERFACE_H 1 + +//#define EMULATION + +//#define TEST_RGMII +#define TEST_RMII + +//#define CACHE_ON + + +s32 synopGMAC_open(int intf); +s32 synopGMAC_open_selftest(int intf); +s32 synopGMAC_close(int intf); +s32 synopGMAC_xmit_frames(struct sk_buff *, int intf, u32 offload_needed, u32 ts); +void synopGMAC_set_multicast_list(int intf); +s32 synopGMAC_set_mac_address(int intf, u8*); +s32 synopGMAC_change_mtu(int intf,s32); +void synop_handle_transmit_over(int intf); +//void synop_handle_received_data(int intf); +s32 synop_handle_received_data(int intf, u8 **buf); // Chris, to get RX buffer pointer +void synopGMAC_set_mode(int intf, int mode); + +void synopGMAC_powerup_mac(synopGMACdevice *gmacdev); +void synopGMAC_powerdown_mac(synopGMACdevice *gmacdev); +s32 synopGMAC_setup_tx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode); +s32 synopGMAC_setup_rx_desc_queue(synopGMACdevice * gmacdev,u32 no_of_desc, u32 desc_mode); + + +#endif /* End of file */ diff --git a/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_plat.h b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_plat.h new file mode 100644 index 0000000..b3daf4a --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NUVOTON_EMAC/TARGET_M460/synopGMAC_plat.h @@ -0,0 +1,183 @@ +/* =================================================================================== + * Copyright (c) <2009> Synopsys, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software annotated with this license and associated documentation files + * (the "Software"), to deal in the Software without restriction, including without + * limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * =================================================================================== */ + +/**\file + * This file serves as the wrapper for the platform/OS dependent functions + * It is needed to modify these functions accordingly based on the platform and the + * OS. Whenever the synopsys GMAC driver ported on to different platform, this file + * should be handled at most care. + * The corresponding function definitions for non-inline functions are available in + * synopGMAC_plat.c file. + * \internal + * -------------------------------------REVISION HISTORY--------------------------- + * Synopsys 01/Aug/2007 Created + */ + + +#ifndef SYNOP_GMAC_PLAT_H +#define SYNOP_GMAC_PLAT_H 1 + +#include +#include "NuMicro.h" + +#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args) + +//#define DEBUG +#ifdef DEBUG +#undef TR +# define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) +#else +# define TR(fmt, args...) /* not debugging: nothing */ +#endif + +typedef unsigned char u8; ///< Define 8-bit unsigned data type +typedef unsigned short u16; ///< Define 16-bit unsigned data type +typedef unsigned int u32; ///< Define 32-bit unsigned data type +typedef signed int s32; ///< Define 32-bit signed data type +//typedef unsigned long long u64; +typedef unsigned int u64; + + +typedef int bool; +enum synopGMAC_boolean { + false = 0, + true = 1 +}; + +#define DEFAULT_DELAY_VARIABLE 10 +#define DEFAULT_LOOP_VARIABLE 10000 + +/* There are platform related endian conversions + * + */ + +#define LE32_TO_CPU __le32_to_cpu +#define BE32_TO_CPU __be32_to_cpu +#define CPU_TO_LE32 __cpu_to_le32 + +/* Error Codes */ +#define ESYNOPGMACNOERR 0 +#define ESYNOPGMACNOMEM 1 +#define ESYNOPGMACPHYERR 2 +#define ESYNOPGMACBUSY 3 + + +/** + * These are the wrapper function prototypes for OS/platform related routines + */ + +extern void plat_delay(uint32_t ticks); + + +/** + * The Low level function to read register contents from Hardware. + * + * @param[in] pointer to the base of register map + * @param[in] Offset from the base + * \return Returns the register contents + */ +static u32 __INLINE synopGMACReadReg(u32 *RegBase, u32 RegOffset) +{ + + u64 addr = (u64)RegBase + RegOffset; + u32 data = inp32((void *)addr); + return data; + +} + +/** + * The Low level function to write to a register in Hardware. + * + * @param[in] pointer to the base of register map + * @param[in] Offset from the base + * @param[in] Data to be written + * \return void + */ +static void __INLINE synopGMACWriteReg(u32 *RegBase, u32 RegOffset, u32 RegData) +{ + + u64 addr = (u64)RegBase + RegOffset; + if(RegOffset == 0) + plat_delay(1); + outp32((void *)addr, RegData); + return; +} + +/** + * The Low level function to set bits of a register in Hardware. + * + * @param[in] pointer to the base of register map + * @param[in] Offset from the base + * @param[in] Bit mask to set bits to logical 1 + * \return void + */ +static void __INLINE synopGMACSetBits(u32 *RegBase, u32 RegOffset, u32 BitPos) +{ + u64 addr = (u64)RegBase + RegOffset; + u32 data = inp32((void *)addr); + data |= BitPos; + + outp32((void *)addr, data); + + return; +} + + +/** + * The Low level function to clear bits of a register in Hardware. + * + * @param[in] pointer to the base of register map + * @param[in] Offset from the base + * @param[in] Bit mask to clear bits to logical 0 + * \return void + */ +static void __INLINE synopGMACClearBits(u32 *RegBase, u32 RegOffset, u32 BitPos) +{ + u64 addr = (u64)RegBase + RegOffset; + u32 data = inp32((void *)addr); + data &= (~BitPos); + + outp32((void *)addr, data); + return; +} + +/** + * The Low level function to Check the setting of the bits. + * + * @param[in] pointer to the base of register map + * @param[in] Offset from the base + * @param[in] Bit mask to set bits to logical 1 + * \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument. + * + */ +static bool __INLINE synopGMACCheckBits(u32 *RegBase, u32 RegOffset, u32 BitPos) +{ + u64 addr = (u64)RegBase + RegOffset; + u32 data = inp32((void *)addr); + data &= BitPos; + if(data) return true; + else return false; + +} + + +#endif diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt index fc8668c..f4271f1 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt @@ -9,6 +9,8 @@ add_subdirectory(TARGET_NUCLEO_H743ZI) elseif("NUCLEO_H743ZI2" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NUCLEO_H743ZI2) +elseif("NUCLEO_H723ZG" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_NUCLEO_H723ZG) endif() target_include_directories(mbed-emac diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/CMakeLists.txt new file mode 100644 index 0000000..5e6c9d6 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-emac + INTERFACE + stm32h7_eth_init.c +) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c new file mode 100644 index 0000000..0690d7b --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c @@ -0,0 +1,163 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT + +#include "stm32h7xx_hal.h" +#include "platform/mbed_critical.h" + +#define MCO_Pin GPIO_PIN_0 +#define MCO_GPIO_Port GPIOH +#define RMII_MDC_Pin GPIO_PIN_1 +#define RMII_MDC_GPIO_Port GPIOC +#define RMII_REF_CLK_Pin GPIO_PIN_1 +#define RMII_REF_CLK_GPIO_Port GPIOA +#define RMII_MDIO_Pin GPIO_PIN_2 +#define RMII_MDIO_GPIO_Port GPIOA +#define RMII_CRS_DV_Pin GPIO_PIN_7 +#define RMII_CRS_DV_GPIO_Port GPIOA +#define RMII_RXD0_Pin GPIO_PIN_4 +#define RMII_RXD0_GPIO_Port GPIOC +#define RMII_RXD1_Pin GPIO_PIN_5 +#define RMII_RXD1_GPIO_Port GPIOC +#define RMII_TXD1_Pin GPIO_PIN_13 +#define RMII_TXD1_GPIO_Port GPIOB +#define TMS_Pin GPIO_PIN_13 +#define TMS_GPIO_Port GPIOA +#define TCK_Pin GPIO_PIN_14 +#define TCK_GPIO_Port GPIOA +#define RMII_TX_EN_Pin GPIO_PIN_11 +#define RMII_TX_EN_GPIO_Port GPIOG +#define RMII_TXD0_Pin GPIO_PIN_13 +#define RMII_TXD0_GPIO_Port GPIOG + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + GPIO_InitTypeDef GPIO_InitStruct; + if (heth->Instance == ETH) { + /* Disable DCache for STM32H7 family */ + core_util_critical_section_enter(); + SCB_DisableDCache(); + core_util_critical_section_exit(); + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /* Enable Peripheral clock */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + __HAL_RCC_ETH1TX_CLK_ENABLE(); + __HAL_RCC_ETH1RX_CLK_ENABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = RMII_MDC_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(RMII_MDC_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = RMII_RXD0_Pin | RMII_RXD1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = RMII_TXD1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = RMII_TX_EN_Pin | RMII_TXD0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + if (heth->Instance == ETH) { + /* Disable Peripheral clock */ + __HAL_RCC_ETH1MAC_CLK_DISABLE(); + __HAL_RCC_ETH1TX_CLK_DISABLE(); + __HAL_RCC_ETH1RX_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin | RMII_RXD0_Pin | RMII_RXD1_Pin); + + HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin | RMII_MDIO_Pin | RMII_CRS_DV_Pin); + + HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin); + + HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin | RMII_TXD0_Pin); + } +} + +#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/CMakeLists.txt b/connectivity/drivers/mbedtls/TARGET_NUVOTON/CMakeLists.txt index 2a28282..dc8246c 100644 --- a/connectivity/drivers/mbedtls/TARGET_NUVOTON/CMakeLists.txt +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/CMakeLists.txt @@ -1,7 +1,9 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -if("M480" IN_LIST MBED_TARGET_LABELS) +if("M460" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_M460) +elseif("M480" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_M480) elseif("NUC472" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NUC472) diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt new file mode 100644 index 0000000..ba705f5 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2022 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_include_directories(mbed-mbedtls + INTERFACE + . + ./aes + ./ecp + ./rsa + ./sha + ./gcm + ./ccm +) + +target_sources(mbed-mbedtls + INTERFACE + aes/aes_alt.c + ecp/crypto_ecc_hw.c + ecp/ecp_alt.c + ecp/ecp_curves_alt.c + ecp/ecp_helper.c + ecp/ecp_internal_alt.c + rsa/crypto_rsa_hw.c + rsa/rsa_alt.c + sha/sha1_alt.c + sha/sha256_alt.c + sha/sha512_alt.c + sha/sha_alt_hw.c + gcm/gcm_alt.c + ccm/ccm_alt.c +) diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/aes/aes_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/aes/aes_alt.c new file mode 100644 index 0000000..4f6bd23 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/aes/aes_alt.c @@ -0,0 +1,469 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#include "mbedtls/aes.h" + +#if defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_AES_ALT) + +#include +#include + +#include "M460.h" +#include "mbed_toolchain.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize( void *v, size_t n ) +{ + volatile unsigned char *p = (unsigned char*)v; + while( n-- ) *p++ = 0; +} + +/* AES DMA compatible backup buffer if user buffer doesn't meet requirements + * + * AES DMA buffer location requires to be: + * (1) Word-aligned + * (2) Located in 0x2xxxxxxx region. Check linker files to ensure global variables are placed in this region. + * + * AES DMA buffer size MAX_DMA_CHAIN_SIZE must be a multiple of 16-byte block size. + * Its value is estimated to trade memory footprint off against performance. + * + */ +#define MAX_DMA_CHAIN_SIZE (16*12) +MBED_ALIGN(4) static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE]; +MBED_ALIGN(4) static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE]; + +void mbedtls_aes_init( mbedtls_aes_context *ctx ) +{ + memset( ctx, 0, sizeof( mbedtls_aes_context ) ); + /* Init crypto module */ + crypto_init(); +} + +void mbedtls_aes_free( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) + return; + + /* Uninit crypto module */ + crypto_uninit(); + mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) ); +} + +/* + * AES key schedule (encryption) + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + unsigned int i; + + switch( keybits ) { + case 128: + ctx->keySize = AES_KEY_SIZE_128; + break; + case 192: + ctx->keySize = AES_KEY_SIZE_192; + break; + case 256: + ctx->keySize = AES_KEY_SIZE_256; + break; + default : + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + /* Fetch key byte data in big-endian */ + for( i = 0; i < ( keybits >> 5 ); i++ ) { + ctx->keys[i] = nu_get32_be(key + i * 4); + } + + return( 0 ); +} + +/* + * AES key schedule (decryption) + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + int ret; + + /* Also checks keybits */ + if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 ) + goto exit; + +exit: + return( ret ); +} + +/* Do AES encrypt/decrypt with H/W accelerator + * + * NOTE: As input/output buffer doesn't follow constraint of DMA buffer, static allocated + * DMA compatible buffer is used for DMA instead and this needs extra copy. + * + * NOTE: dataSize requires to be: + * 1) Multiple of block size 16 + * 2) <= MAX_DMA_CHAIN_SIZE + */ +static void __nvt_aes_crypt( mbedtls_aes_context *ctx, + const unsigned char *input, + unsigned char *output, size_t dataSize) +{ + const unsigned char* pIn; + unsigned char* pOut; + + MBED_ASSERT((dataSize % 16 == 0) && (dataSize <= MAX_DMA_CHAIN_SIZE)); + + /* AES DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) 16-byte aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region + */ + if ((! crypto_dma_buff_compat(au8OutputData, MAX_DMA_CHAIN_SIZE, 16)) || + (! crypto_dma_buff_compat(au8InputData, MAX_DMA_CHAIN_SIZE, 16))) { + error("Buffer for AES alter. DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); + } + + /* Acquire ownership of AES H/W */ + crypto_aes_acquire(); + + /* Force AES free */ + CRPT->AES_CTL = CRPT_AES_CTL_STOP_Msk; + + /* Enable AES interrupt */ + AES_ENABLE_INT(CRPT); + + /* We support multiple contexts with context save & restore and so needs just one + * H/W channel. Always use H/W channel #0. */ + + /* AES_IN_OUT_SWAP: Let H/W know both input/output data are arranged in little-endian */ + AES_Open(CRPT, 0, ctx->encDec, ctx->opMode, ctx->keySize, AES_IN_OUT_SWAP); + AES_SetInitVect(CRPT, 0, ctx->iv); + AES_SetKey(CRPT, 0, ctx->keys, ctx->keySize); + + /* AES DMA buffer requirements same as above */ + if (! crypto_dma_buff_compat(input, dataSize, 16)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } else { + pIn = input; + } + /* AES DMA buffer requirements same as above */ + if (! crypto_dma_buff_compat(output, dataSize, 16)) { + pOut = au8OutputData; + } else { + pOut = output; + } + + /* Even though AES H/W has limited support for overlapped DMA input/output buffers, + * we still seek to one backup buffer to make them non-overlapped for simplicity. */ + if (crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)) { + memcpy(au8InputData, input, dataSize); + pIn = au8InputData; + } + MBED_ASSERT(! crypto_dma_buffs_overlap(pIn, dataSize, pOut, dataSize)); + + AES_SetDMATransfer(CRPT, 0, (uint32_t)pIn, (uint32_t)pOut, dataSize); + + crypto_aes_prestart(); + AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT); + crypto_aes_wait(); + + if( pOut != output ) { + memcpy(output, au8OutputData, dataSize); + } + + /* Save IV for next block */ + ctx->iv[0] = CRPT->AES_FDBCK[0]; + ctx->iv[1] = CRPT->AES_FDBCK[1]; + ctx->iv[2] = CRPT->AES_FDBCK[2]; + ctx->iv[3] = CRPT->AES_FDBCK[3]; + + /* Disable AES interrupt */ + AES_DISABLE_INT(CRPT); + + /* Release ownership of AES H/W */ + crypto_aes_release(); +} + +/* + * AES-ECB block encryption + */ +void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + ctx->encDec = 1; + __nvt_aes_crypt(ctx, input, output, 16); +} + +/* + * AES-ECB block decryption + */ +void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + ctx->encDec = 0; + __nvt_aes_crypt(ctx, input, output, 16); +} + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + ctx->opMode = AES_MODE_ECB; + if( mode == MBEDTLS_AES_ENCRYPT ) + mbedtls_aes_encrypt( ctx, input, output ); + else + mbedtls_aes_decrypt( ctx, input, output ); + + + return( 0 ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t len, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int length = len; + int blockChainLen; + + if( length % 16 ) + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + + + ctx->opMode = AES_MODE_CBC; + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + if( mode == MBEDTLS_AES_ENCRYPT ) { + ctx->encDec = 1; + } + else { + ctx->encDec = 0; + } + + while( length > 0 ) { + blockChainLen = (length > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : length; + + __nvt_aes_crypt(ctx, input, output, blockChainLen); + + length -= blockChainLen; + input += blockChainLen; + output += blockChainLen; + } + + /* Save IV for next block cipher */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int c; + size_t n = *iv_off; + + /* First incomplete block */ + if (n % 16) { + while (n && length) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } + + n = ( n + 1 ) & 0x0F; + length --; + } + } + + /* Middle complete block(s) */ + size_t block_chain_len = length - (length % 16); + + if (block_chain_len) { + ctx->opMode = AES_MODE_CFB; + if (mode == MBEDTLS_AES_DECRYPT) { + ctx->encDec = 0; + } + else { + ctx->encDec = 1; + } + + /* Fetch IV byte data in big-endian */ + ctx->iv[0] = nu_get32_be(iv); + ctx->iv[1] = nu_get32_be(iv + 4); + ctx->iv[2] = nu_get32_be(iv + 8); + ctx->iv[3] = nu_get32_be(iv + 12); + + while (block_chain_len) { + size_t block_chain_len2 = (block_chain_len > MAX_DMA_CHAIN_SIZE) ? MAX_DMA_CHAIN_SIZE : block_chain_len; + + __nvt_aes_crypt(ctx, input, output, block_chain_len2); + + input += block_chain_len2; + output += block_chain_len2; + length -= block_chain_len2; + + block_chain_len -= block_chain_len2; + } + + /* NOTE: Buffers input/output could overlap. See ctx->iv rather than input/output + * for iv of next block cipher. */ + /* Fetch IV byte data in big-endian */ + nu_set32_be(iv, ctx->iv[0]); + nu_set32_be(iv + 4, ctx->iv[1]); + nu_set32_be(iv + 8, ctx->iv[2]); + nu_set32_be(iv + 12, ctx->iv[3]); + } + + /* Last incomplete block */ + if (length) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + while (length --) { + if (mode == MBEDTLS_AES_DECRYPT) { + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + else { + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + } + + n = ( n + 1 ) & 0x0F; + } + } + + *iv_off = n; + + return( 0 ); +} + + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + + while( length-- ) { + memcpy( ov, iv, 16 ); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + if( mode == MBEDTLS_AES_DECRYPT ) + ov[16] = *input; + + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if( mode == MBEDTLS_AES_ENCRYPT ) + ov[16] = c; + + memcpy( iv, ov + 1, 16 ); + } + + return( 0 ); +} +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + int c, i; + size_t n = *nc_off; + + while( length-- ) { + if( n == 0 ) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); + + for( i = 16; i > 0; i-- ) + if( ++nonce_counter[i - 1] != 0 ) + break; + } + c = *input++; + *output++ = (unsigned char)( c ^ stream_block[n] ); + + n = ( n + 1 ) & 0x0F; + } + + *nc_off = n; + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#endif /* MBEDTLS_AES_ALT */ + + +#endif /* MBEDTLS_AES_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/aes/aes_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/aes/aes_alt.h new file mode 100644 index 0000000..23625b5 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/aes/aes_alt.h @@ -0,0 +1,262 @@ +/** + * \file aes_alt.h + * + * \brief AES block cipher + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ +#ifndef MBEDTLS_AES_ALT_H +#define MBEDTLS_AES_ALT_H + +#include "mbedtls/aes.h" + +#if defined(MBEDTLS_AES_ALT) +// Regular implementation +// +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief AES context structure + */ +typedef struct { + uint32_t keySize; /* Key size: AES_KEY_SIZE_128/192/256 */ + uint32_t encDec; /* 0: decrypt, 1: encrypt */ + uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ + uint32_t iv[4]; /* IV for next block cipher */ + uint32_t keys[8]; /* Cipher key */ +} +mbedtls_aes_context; + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void mbedtls_aes_init( mbedtls_aes_context *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void mbedtls_aes_free( mbedtls_aes_context *ctx ); + +/** + * \brief AES key schedule (encryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +/** + * \brief AES key schedule (decryption) + * + * \param ctx AES context to be initialized + * \param key decryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +#ifdef __cplusplus +} +#endif + + +#endif /* MBEDTLS_AES_ALT */ + +#endif /* aes_alt.h */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ccm/ccm_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ccm/ccm_alt.c new file mode 100644 index 0000000..b85b452 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ccm/ccm_alt.c @@ -0,0 +1,738 @@ +/* + * NIST SP800-38C compliant CCM implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (c) 2022, Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +/* + * Definition of CCM: + * http://csrc.nist.gov/publications/nistpubs/800-38C/SP800-38C_updated-July20_2007.pdf + * RFC 3610 "Counter with CBC-MAC (CCM)" + * + * Related: + * RFC 5116 "An Interface and Algorithms for Authenticated Encryption" + */ + +#include "common.h" +#include "mbedtls/aes.h" + +#if defined(MBEDTLS_CCM_C) + +#include "mbedtls/ccm.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + +#if defined(MBEDTLS_CCM_ALT) + +#include "M460.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" + +#define CCM_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_CCM_BAD_INPUT ) +#define CCM_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#define CCM_ENCRYPT 1 +#define CCM_DECRYPT 0 + + + +#define CCM_MODE (AES_MODE_CCM << CRPT_AES_CTL_OPMODE_Pos) +#define START CRPT_AES_CTL_START_Msk +#define DMAEN CRPT_AES_CTL_DMAEN_Msk +#define DMALAST CRPT_AES_CTL_DMALAST_Msk +#define DMACC CRPT_AES_CTL_DMACSCAD_Msk +#define START CRPT_AES_CTL_START_Msk +#define FBIN CRPT_AES_CTL_FBIN_Msk +#define FBOUT CRPT_AES_CTL_FBOUT_Msk + + +#define Debug_CCM_Info(x) {} +//#define Debug_CCM_Info(x) { printf x; } + +int32_t ToBigEndian(uint8_t *pbuf, uint32_t u32Size) +{ + uint32_t i; + uint8_t u8Tmp; + uint32_t u32Tmp; + + /* pbuf must be word alignment */ + if((uint32_t)pbuf & 0x3) + { + printf("The buffer must be 32-bit alignment."); + return -1; + } + + while(u32Size >= 4) + { + u8Tmp = *pbuf; + *(pbuf) = *(pbuf + 3); + *(pbuf + 3) = u8Tmp; + + u8Tmp = *(pbuf + 1); + *(pbuf + 1) = *(pbuf + 2); + *(pbuf + 2) = u8Tmp; + + u32Size -= 4; + pbuf += 4; + } + + if(u32Size > 0) + { + u32Tmp = 0; + for(i = 0; i < u32Size; i++) + { + u32Tmp |= *(pbuf + i) << (24 - i * 8); + } + + *((uint32_t *)pbuf) = u32Tmp; + } + + return 0; +} + + +/* + CCM input format must be block alignment. The block size is 16 bytes. + + ---------------------------------------------------------------------- + Block B0 + Formatting of the Control Information and the Nonce + ---------------------------------------------------------------------- + First block B_0: + 0 .. 0 flags + 1 .. iv_len nonce (aka iv) + iv_len+1 .. 15 length + + + flags: + With flags as (bits): + 7 0 + 6 add present? + 5 .. 3 (t - 2) / 2 + 2 .. 0 q - 1 + +*/ + +int32_t CCMPacker(const uint8_t *iv, uint32_t ivlen, const uint8_t *A, uint32_t alen, const uint8_t *P, uint32_t plen, uint8_t *pbuf, uint32_t *psize, uint32_t tlen, int32_t enc) +{ + uint32_t i, j; + uint32_t alen_aligned, plen_aligned; + uint32_t u32Offset = 0; + uint8_t u8Tmp; + uint32_t q = 0; + + + /* Flags in B0 + *With flags as(bits) : + 7 0 + 6 add present ? + 5 .. 3 (t - 2) / 2 + 2 .. 0 q - 1, q = 15 - nlen + */ + if( tlen > 0 ) + { + q = 15 - ivlen; + u8Tmp = (q - 1) | ((tlen - 2) / 2 << 3) | ((alen > 0) ? 0x40 : 0); + pbuf[0] = u8Tmp; // flags + for(i = 0; i < ivlen; i++) // N + pbuf[i + 1] = iv[i]; + for(i = ivlen + 1, j = q - 1; i < 16; i++, j--) // Q + { + if(j >= 4) + pbuf[i] = 0; + else + { + pbuf[i] = (plen >> j * 8) & 0xfful; + } + } + + u32Offset = 16; + } + /* Formatting addition data */ + /* alen. It is limited to be smaller than 2^16-2^8 */ + if(alen > 0) + { + pbuf[u32Offset] = (alen >> 8) & 0xfful; + pbuf[u32Offset + 1] = alen & 0xfful; + + for(i = 0; i < alen; i++) + pbuf[u32Offset + i + 2] = A[i]; + + alen_aligned = ((alen + 2 + 15) / 16) * 16; + for(i = u32Offset + 2 + alen; i < alen_aligned; i++) + { + pbuf[i] = (enc) ? 0:0xff; // padding zero or 0xff + } + + u32Offset += alen_aligned; + } + + /* Formatting payload */ + if( (plen > 0) && (P != 0x00)) + { + plen_aligned = ((plen + 15) / 16) * 16; + for(i = 0; i < plen; i++) + { + pbuf[u32Offset + i] = P[i]; + } + for(; i < plen_aligned; i++) + { + pbuf[u32Offset + i] = 0; // padding zero + } + + u32Offset += plen_aligned; + } + + + /* Formatting Ctr0 */ + if( ivlen > 0 ) + { + pbuf[u32Offset] = q - 1; // Flags + for(i = 0; i < ivlen; i++) // N + { + pbuf[u32Offset + 1 + i] = iv[i]; + } + for(; i < 16; i++) + { + pbuf[u32Offset + 1 + i] = 0; // padding zero to block alignment + } + } + *psize = u32Offset; + + return 0; +} + +#ifdef NVT_CCM_DEBUG +static void DumpBuffHex(uint8_t *pucBuff, int nBytes) +{ + int32_t i32Idx, i, len; + + + i32Idx = 0; + while(nBytes > 0) + { + printf("0x%04X ", i32Idx); + + len = (nBytes < 16) ? nBytes : 16; + for(i = 0; i < len; i++) + printf("%02x ", pucBuff[i32Idx + i]); + for(; i < 16; i++) + { + printf(" "); + } + printf(" "); + for(i = 0; i < len; i++) + { + if((pucBuff[i32Idx + i] >= 0x20) && (pucBuff[i32Idx + i] < 127)) + printf("%c", pucBuff[i32Idx + i]); + else + printf("."); + nBytes--; + } + i32Idx += len; + printf("\n"); + } + printf("\n"); +} + +static void DumpBuffHex2(uint8_t *pucBuff, int nBytes) +{ + int32_t i32Idx, i; + + i32Idx = 0; + while(nBytes > 0) + { + printf("0x%04X ", i32Idx); + for(i = 0; i < 16; i += 4) + printf("%08x ", *((uint32_t *)&pucBuff[i32Idx + i])); + i32Idx += 16; + nBytes -= 16; + printf("\n"); + } + printf("\n"); +} +#endif + + +static int32_t _CCM_OneShot(mbedtls_ccm_context *ctx, int32_t encDec, const uint8_t *iv, uint32_t ivlen, const uint8_t *A, uint32_t alen, const uint8_t *P, uint32_t plen, uint8_t *buf, uint8_t *tag, uint32_t tlen) +{ + uint32_t size, plen_aligned; + const uint8_t* pIn; + uint8_t* pOut; + bool ret; + + + Debug_CCM_Info(("## FUNC: %s, alen=%lu, plen=%lu, ivlen=%lu, tlen=%lu\n", __FUNCTION__, alen, plen, ivlen, tlen)); +#ifdef NVT_CCM_DEBUG + printf("\n"); + + printf("key (%d):\n", (4 + 2*ctx->keySize)*4 ); + DumpBuffHex(ctx->keys, (4 + 2*ctx->keySize)*4); + + printf("N (%d):\n", ivlen); + DumpBuffHex(iv, ivlen); + + printf("A (%d):\n", alen); + DumpBuffHex(A, alen); + + printf("P (%d):\n", plen); + DumpBuffHex(P, plen); + + printf("T len = %d\n", tlen); +#endif + + + /* Prepare the blocked buffer for CCM */ + memset(ctx->ccm_buf, 0, MAX_CCM_BUF); + CCMPacker(iv, ivlen, A, alen, P, plen, ctx->ccm_buf, &size, tlen, encDec); + + ToBigEndian(ctx->ccm_buf, size + 16); + + plen_aligned = (plen & 0xful) ? ((plen + 15) / 16) * 16 : plen; + +#ifdef NVT_CCM_DEBUG + printf("input blocks (%d):\n", size); + DumpBuffHex2(ctx->ccm_buf, size); + + printf("input key (%d):\n", size); + DumpBuffHex2(ctx->keys, (4 + 2*ctx->keySize)*4); + + printf("input Ctr0:\n"); + DumpBuffHex2(&(ctx->ccm_buf[size]), 16); +#endif + + AES_Open(CRPT, 0, encDec, ctx->opMode, ctx->keySize, AES_OUT_SWAP); + /* Set AES Key into H/W */ + AES_SetKey(CRPT, 0, ctx->keys, ctx->keySize); + + /* For ctr0 */ + AES_SetInitVect(CRPT, 0, (uint32_t *)&ctx->ccm_buf[size]); + + + /* Set bytes count of A */ + CRPT->AES_GCM_ACNT[0] = size - plen_aligned; + CRPT->AES_GCM_ACNT[1] = 0; + CRPT->AES_GCM_PCNT[0] = plen; + CRPT->AES_GCM_PCNT[1] = 0; + + pIn = ctx->ccm_buf; + pOut = ctx->out_buf; + AES_SetDMATransfer(CRPT, 0, (uint32_t)pIn, (uint32_t)pOut, size); + + crypto_aes_prestart(); + + /* Start AES crypt */ + AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT); + + /* Waiting for AES calculation */ + ret = crypto_aes_wait(); + if( ret == false ) + { + printf("###[WARN] AES CCM got NU_CRYPTO_DONE_ERR \n"); + return (-1); + } + + memcpy(buf, ctx->out_buf, plen); + + if(tlen > 16) + { + tlen = 16; + } + memcpy(tag, &ctx->out_buf[plen_aligned], tlen); + + Debug_CCM_Info(("OneShot output blocks (%lu)(%lu):\n", size, plen)); +#ifdef NVT_CCM_DEBUG + DumpBuffHex2(buf, plen); + printf("OneShot output blocks Tag :\n"); + DumpBuffHex2(&ctx->out_buf[plen_aligned], 16); +#endif + return 0; +} + +static int32_t AES_Run(mbedtls_ccm_context *ctx, uint32_t u32Option) +{ + + bool ret; + + crypto_aes_prestart(); + CRPT->AES_CTL = u32Option | START; + ret = crypto_aes_wait(); + if( ret == false ) + { + printf("###[WARN] AES CCM got NU_CRYPTO_DONE_ERR \n"); + } + + return 0; +} + +static int32_t _CCM_Cascade(mbedtls_ccm_context *ctx, int32_t encDec, const uint8_t *iv, uint32_t ivlen, const uint8_t *A, uint32_t alen, const uint8_t *P, uint32_t plen, uint8_t *buf, uint8_t *tag, uint32_t tlen) +{ + uint32_t size, plen_aligned; + uint32_t u32OptBasic; + int32_t plen_cur; + int32_t len; + const uint8_t *pin; + uint8_t *pout; + + Debug_CCM_Info(("## FUNC: %s, alen=%lu, plen=%lu, ivlen=%lu, tlen=%lu\n", __FUNCTION__, alen, plen, ivlen, tlen)); + /* Prepare the blocked buffer for CCM */ + memset(ctx->ccm_buf, 0, MAX_CCM_BUF); + CCMPacker(iv, ivlen, A, alen, 0, plen, ctx->ccm_buf, &size, tlen, encDec); + + ToBigEndian(ctx->ccm_buf, size + 16); + + plen_aligned = (plen & 0xful) ? ((plen + 15) / 16) * 16 : plen; + + + AES_Open(CRPT, 0, encDec, ctx->opMode, ctx->keySize, AES_OUT_SWAP); + /* Set AES Key into H/W */ + AES_SetKey(CRPT, 0, ctx->keys, ctx->keySize); + +#ifdef NVT_CCM_DEBUG + printf("input blocks (%d):\n", size); + DumpBuffHex2(ctx->ccm_buf, size); + printf("input Ctr0:\n"); + DumpBuffHex2(&(ctx->ccm_buf[size]), 16); +#endif + + /* For ctr0 */ + AES_SetInitVect(CRPT, 0, (uint32_t *)&ctx->ccm_buf[size]); + + /* Set bytes count of A */ + CRPT->AES_GCM_ACNT[0] = size; + CRPT->AES_GCM_ACNT[1] = 0; + CRPT->AES_GCM_PCNT[0] = plen; //plen_aligned; /* set plen_aligned will get wrong tag @plen=24 */ + CRPT->AES_GCM_PCNT[1] = 0; + + AES_SetDMATransfer(CRPT, 0, (uint32_t)ctx->ccm_buf, (uint32_t)ctx->out_buf, size); + + /* feedback buffer is necessary for cascade mode */ + CRPT->AES_FBADDR = (uint32_t)ctx->fb_buf;; + + u32OptBasic = CRPT->AES_CTL ; + + AES_Run(ctx, u32OptBasic | CCM_MODE | FBOUT | DMAEN); + + plen_cur = plen; + pin = P; + pout = buf; + while(plen_cur) + { + len = plen_cur; + if(len > CCM_PBLOCK_SIZE) + { + len = CCM_PBLOCK_SIZE; + } + plen_cur -= len; + + /* Prepare the blocked buffer for CCM */ + CCMPacker(0, 0, 0, 0, pin, len, ctx->ccm_buf, &size, 0, encDec); + + ToBigEndian(ctx->ccm_buf, size); + + AES_SetDMATransfer(CRPT, 0, (uint32_t)ctx->ccm_buf, (uint32_t)pout, size); + + /* Start AES Eecrypt */ + if(plen_cur) + { + /* casecade n */ + AES_Run(ctx, u32OptBasic | CCM_MODE | FBIN | FBOUT | DMAEN | DMACC); + } + else + { + /* last cascade */ + AES_SetDMATransfer(CRPT, 0, (uint32_t)ctx->ccm_buf, (uint32_t)ctx->out_buf, size); + AES_Run(ctx, u32OptBasic | CCM_MODE | FBIN | FBOUT | DMAEN | DMACC | DMALAST); + memcpy(pout, ctx->out_buf, len); + } + Debug_CCM_Info(("output blocks (%lu)(%lu):\n", size, len)); +#ifdef NVT_CCM_DEBUG + DumpBuffHex2(pout, len); +#endif + pin += len; + pout += size; + } +#ifdef NVT_CCM_DEBUG + printf("output blocks Tag :\n"); + DumpBuffHex2(&ctx->out_buf[size], 16); +#endif + if(tlen > 16) + { + tlen = 16; + } + memcpy(tag, &ctx->out_buf[size], tlen); + + return 0; +} + + +static int32_t _CCM(mbedtls_ccm_context *ctx, int32_t encDec, const uint8_t *iv, uint32_t ivlen, const uint8_t *A, uint32_t alen, const uint8_t *P, uint32_t plen, uint8_t *buf, uint8_t *tag, uint32_t tlen) +{ + uint32_t plen_aligned, alen_aligned; + int32_t ret; + + Debug_CCM_Info(("## FUNC: %s, alen=%lu, plen=%lu, ivlen=%lu, tlen=%lu\n", __FUNCTION__, alen, plen, ivlen, tlen)); + + if(ivlen > 16) + return -1; + + /* Formatting addition data: 2 bytes to store A's length */ + alen_aligned = ((alen + 2 + 15) / 16) * 16; + plen_aligned = ((plen + 15) / 16) * 16; + + /* Length of B0's formatting nonce (aka iv): 16 */ + if( (16 + alen_aligned + plen_aligned ) < CCM_PBLOCK_SIZE ) + { + ret = _CCM_OneShot(ctx, encDec, iv, ivlen, A, alen, P, plen, buf, tag, tlen); + } else { + ret = _CCM_Cascade(ctx, encDec, iv, ivlen, A, alen, P, plen, buf, tag, tlen); + } + + return(ret); +} + +/* + * Initialize context + */ +void mbedtls_ccm_init( mbedtls_ccm_context *ctx ) +{ + CCM_VALIDATE( ctx != NULL ); + memset( ctx, 0, sizeof( mbedtls_ccm_context ) ); + + ctx->opMode = AES_MODE_CCM; + /* Init crypto module */ + crypto_init(); +} + +int mbedtls_ccm_setkey( mbedtls_ccm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ) +{ + int32_t klen; + + CCM_VALIDATE_RET( ctx != NULL ); + CCM_VALIDATE_RET( key != NULL ); + CCM_VALIDATE_RET( keybits == 128 || keybits == 192 || keybits == 256 ); + + + klen = keybits / 8; + + memcpy(ctx->keys, key, klen); + ToBigEndian((uint8_t *)ctx->keys, klen); + + switch( keybits ) { + case 128: + ctx->keySize = AES_KEY_SIZE_128; + break; + case 192: + ctx->keySize = AES_KEY_SIZE_192; + break; + case 256: + ctx->keySize = AES_KEY_SIZE_256; + break; + default : + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + return( 0 ); +} + +/* + * Free context + */ +void mbedtls_ccm_free( mbedtls_ccm_context *ctx ) +{ + if( ctx == NULL ) + return; + + /* Uninit crypto module */ + crypto_uninit(); + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_ccm_context ) ); +} + + +/* + * Authenticated encryption or decryption + */ +static int ccm_auth_crypt( mbedtls_ccm_context *ctx, int mode, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len ) +{ + int ret; + + /* + * Check length requirements: SP800-38C A.1 + * Additional requirement: a < 2^16 - 2^8 to simplify the code. + * 'length' checked later (when writing it to the first block) + * + * Also, loosen the requirements to enable support for CCM* (IEEE 802.15.4). + */ + + if( tag_len == 2 || tag_len > 16 || tag_len % 2 != 0 ) + return( MBEDTLS_ERR_CCM_BAD_INPUT ); + + /* Also implies q is within bounds */ + if( iv_len < 7 || iv_len > 13 ) + return( MBEDTLS_ERR_CCM_BAD_INPUT ); + + if( add_len >= 0xFF00 ) + return( MBEDTLS_ERR_CCM_BAD_INPUT ); + + + ctx->opMode = AES_MODE_CCM; + ctx->encDec = mode; + + + /* Acquire ownership of AES H/W */ + crypto_aes_acquire(); +#if 1 + /* Force AES free */ + CRPT->AES_CTL = CRPT_AES_CTL_STOP_Msk; +#endif + AES_ENABLE_INT(CRPT); + + ret = _CCM(ctx, mode, iv, iv_len, add, add_len, input, length, output, tag, tag_len); + + /* Release ownership of AES H/W */ + crypto_aes_release(); + + return( ret ); +} + +/* + * Authenticated encryption + */ +int mbedtls_ccm_star_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len ) +{ + Debug_CCM_Info(("## FUNC: %s, alen=%u, plen=%u, ivlen=%u, tlen=%u\n", __FUNCTION__, add_len, length, iv_len, tag_len)); + CCM_VALIDATE_RET( ctx != NULL ); + CCM_VALIDATE_RET( iv != NULL ); + CCM_VALIDATE_RET( add_len == 0 || add != NULL ); + CCM_VALIDATE_RET( length == 0 || input != NULL ); + CCM_VALIDATE_RET( length == 0 || output != NULL ); + CCM_VALIDATE_RET( tag_len == 0 || tag != NULL ); + return( ccm_auth_crypt( ctx, CCM_ENCRYPT, length, iv, iv_len, + add, add_len, input, output, tag, tag_len ) ); +} + +int mbedtls_ccm_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len ) +{ + Debug_CCM_Info(("## FUNC: %s, alen=%u, plen=%u, ivlen=%u, tlen=%u\n", __FUNCTION__, add_len, length, iv_len, tag_len)); + CCM_VALIDATE_RET( ctx != NULL ); + CCM_VALIDATE_RET( iv != NULL ); + CCM_VALIDATE_RET( add_len == 0 || add != NULL ); + CCM_VALIDATE_RET( length == 0 || input != NULL ); + CCM_VALIDATE_RET( length == 0 || output != NULL ); + CCM_VALIDATE_RET( tag_len == 0 || tag != NULL ); + if( tag_len == 0 ) + return( MBEDTLS_ERR_CCM_BAD_INPUT ); + + return( mbedtls_ccm_star_encrypt_and_tag( ctx, length, iv, iv_len, add, + add_len, input, output, tag, tag_len ) ); +} + +/* + * Authenticated decryption + */ +int mbedtls_ccm_star_auth_decrypt( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len ) +{ + int ret; + unsigned char check_tag[16]; + unsigned char i; + int diff; + + Debug_CCM_Info(("## FUNC: %s, alen=%u, plen=%u, ivlen=%u, tlen=%u\n", __FUNCTION__, add_len, length, iv_len, tag_len)); + CCM_VALIDATE_RET( ctx != NULL ); + CCM_VALIDATE_RET( iv != NULL ); + CCM_VALIDATE_RET( add_len == 0 || add != NULL ); + CCM_VALIDATE_RET( length == 0 || input != NULL ); + CCM_VALIDATE_RET( length == 0 || output != NULL ); + CCM_VALIDATE_RET( tag_len == 0 || tag != NULL ); + + if( ( ret = ccm_auth_crypt( ctx, CCM_DECRYPT, length, + iv, iv_len, add, add_len, + input, output, check_tag, tag_len ) ) != 0 ) + { + return( ret ); + } + + /* Check tag in "constant-time" */ + for( diff = 0, i = 0; i < tag_len; i++ ) + diff |= tag[i] ^ check_tag[i]; + + if( diff != 0 ) + { + mbedtls_platform_zeroize( output, length ); + return( MBEDTLS_ERR_CCM_AUTH_FAILED ); + } + + return( 0 ); +} + +int mbedtls_ccm_auth_decrypt( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len ) +{ + Debug_CCM_Info(("## FUNC: %s, alen=%u, plen=%u, ivlen=%u, tlen=%u\n", __FUNCTION__, add_len, length, iv_len, tag_len)); + CCM_VALIDATE_RET( ctx != NULL ); + CCM_VALIDATE_RET( iv != NULL ); + CCM_VALIDATE_RET( add_len == 0 || add != NULL ); + CCM_VALIDATE_RET( length == 0 || input != NULL ); + CCM_VALIDATE_RET( length == 0 || output != NULL ); + CCM_VALIDATE_RET( tag_len == 0 || tag != NULL ); + + if( tag_len == 0 ) + return( MBEDTLS_ERR_CCM_BAD_INPUT ); + + return( mbedtls_ccm_star_auth_decrypt( ctx, length, iv, iv_len, add, + add_len, input, output, tag, tag_len ) ); +} +#endif /* MBEDTLS_CCM_ALT */ +#endif /* MBEDTLS_CCM_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ccm/ccm_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ccm/ccm_alt.h new file mode 100644 index 0000000..1c1345e --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ccm/ccm_alt.h @@ -0,0 +1,318 @@ +/** + * \file ccm.h + * + * \brief This file provides an API for the CCM authenticated encryption + * mode for block ciphers. + * + * CCM combines Counter mode encryption with CBC-MAC authentication + * for 128-bit block ciphers. + * + * Input to CCM includes the following elements: + *
  • Payload - data that is both authenticated and encrypted.
    • + *
  • Associated data (Adata) - data that is authenticated but not + * encrypted, For example, a header.
    • + *
  • Nonce - A unique value that is assigned to the payload and the + * associated data.
+ * + * Definition of CCM: + * http://csrc.nist.gov/publications/nistpubs/800-38C/SP800-38C_updated-July20_2007.pdf + * RFC 3610 "Counter with CBC-MAC (CCM)" + * + * Related: + * RFC 5116 "An Interface and Algorithms for Authenticated Encryption" + * + * Definition of CCM*: + * IEEE 802.15.4 - IEEE Standard for Local and metropolitan area networks + * Integer representation is fixed most-significant-octet-first order and + * the representation of octets is most-significant-bit-first order. This is + * consistent with RFC 3610. + */ +/* + * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved + * Copyright (c) 2022, Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +#ifndef MBEDTLS_CCM_ALT_H +#define MBEDTLS_CCM_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "mbed_toolchain.h" +#include "mbedtls/cipher.h" +#include "NuMicro.h" + +#define MBEDTLS_ERR_CCM_BAD_INPUT -0x000D /**< Bad input parameters to the function. */ +#define MBEDTLS_ERR_CCM_AUTH_FAILED -0x000F /**< Authenticated decryption failed. */ + +/* MBEDTLS_ERR_CCM_HW_ACCEL_FAILED is deprecated and should not be used. */ +#define MBEDTLS_ERR_CCM_HW_ACCEL_FAILED -0x0011 /**< CCM hardware accelerator failed. */ + +#ifdef __cplusplus +extern "C" { +#endif + +// Regular implementation +// + +#define MAX_CCM_BUF 256 +#define CCM_PBLOCK_SIZE MAX_CCM_BUF + +/** + * \brief The CCM context-type definition. The CCM context is passed + * to the APIs called. + */ +typedef struct mbedtls_ccm_context +{ + MBED_ALIGN(4) uint8_t ccm_buf[MAX_CCM_BUF + 16]; /* 16 bytes for ctr0 in packer */ + MBED_ALIGN(4) uint8_t out_buf[MAX_CCM_BUF + 16]; /* 16 bytes for tag */ + MBED_ALIGN(4) uint8_t fb_buf[72]; /* feedback buffer for GCM DMA */ + uint32_t keySize; + uint32_t keys[8]; /* Cipher key */ + uint32_t encDec; /* 0: decrypt, 1: encrypt */ + uint32_t opMode; /* AES_MODE CCM */ + +} +mbedtls_ccm_context; + +/** + * \brief This function initializes the specified CCM context, + * to make references valid, and prepare the context + * for mbedtls_ccm_setkey() or mbedtls_ccm_free(). + * + * \param ctx The CCM context to initialize. This must not be \c NULL. + */ +void mbedtls_ccm_init( mbedtls_ccm_context *ctx ); + +/** + * \brief This function initializes the CCM context set in the + * \p ctx parameter and sets the encryption key. + * + * \param ctx The CCM context to initialize. This must be an initialized + * context. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. This must not be \c NULL. + * \param keybits The key size in bits. This must be acceptable by the cipher. + * + * \return \c 0 on success. + * \return A CCM or cipher-specific error code on failure. + */ +int mbedtls_ccm_setkey( mbedtls_ccm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function releases and clears the specified CCM context + * and underlying cipher sub-context. + * + * \param ctx The CCM context to clear. If this is \c NULL, the function + * has no effect. Otherwise, this must be initialized. + */ +void mbedtls_ccm_free( mbedtls_ccm_context *ctx ); + +/** + * \brief This function encrypts a buffer using CCM. + * + * \note The tag is written to a separate buffer. To concatenate + * the \p tag with the \p output, as done in RFC-3610: + * Counter with CBC-MAC (CCM), use + * \p tag = \p output + \p length, and make sure that the + * output buffer is at least \p length + \p tag_len wide. + * + * \param ctx The CCM context to use for encryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param add The additional data field. If \p add_len is greater than + * zero, \p add must be a readable buffer of at least that + * length. + * \param add_len The length of additional data in Bytes. + * This must be less than `2^16 - 2^8`. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field to generate in Bytes: + * 4, 6, 8, 10, 12, 14 or 16. + * + * \return \c 0 on success. + * \return A CCM or cipher-specific error code on failure. + */ +int mbedtls_ccm_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len ); + +/** + * \brief This function encrypts a buffer using CCM*. + * + * \note The tag is written to a separate buffer. To concatenate + * the \p tag with the \p output, as done in RFC-3610: + * Counter with CBC-MAC (CCM), use + * \p tag = \p output + \p length, and make sure that the + * output buffer is at least \p length + \p tag_len wide. + * + * \note When using this function in a variable tag length context, + * the tag length has to be encoded into the \p iv passed to + * this function. + * + * \param ctx The CCM context to use for encryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param add The additional data field. This must be a readable buffer of + * at least \p add_len Bytes. + * \param add_len The length of additional data in Bytes. + * This must be less than 2^16 - 2^8. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field to generate in Bytes: + * 0, 4, 6, 8, 10, 12, 14 or 16. + * + * \warning Passing \c 0 as \p tag_len means that the message is no + * longer authenticated. + * + * \return \c 0 on success. + * \return A CCM or cipher-specific error code on failure. + */ +int mbedtls_ccm_star_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len ); + +/** + * \brief This function performs a CCM authenticated decryption of a + * buffer. + * + * \param ctx The CCM context to use for decryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param add The additional data field. This must be a readable buffer + * of at least that \p add_len Bytes.. + * \param add_len The length of additional data in Bytes. + * This must be less than 2^16 - 2^8. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field to generate in Bytes: + * 4, 6, 8, 10, 12, 14 or 16. + * + * \return \c 0 on success. This indicates that the message is authentic. + * \return #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match. + * \return A cipher-specific error code on calculation failure. + */ +int mbedtls_ccm_auth_decrypt( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len ); + +/** + * \brief This function performs a CCM* authenticated decryption of a + * buffer. + * + * \note When using this function in a variable tag length context, + * the tag length has to be decoded from \p iv and passed to + * this function as \p tag_len. (\p tag needs to be adjusted + * accordingly.) + * + * \param ctx The CCM context to use for decryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param add The additional data field. This must be a readable buffer of + * at least that \p add_len Bytes. + * \param add_len The length of additional data in Bytes. + * This must be less than 2^16 - 2^8. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field in Bytes. + * 0, 4, 6, 8, 10, 12, 14 or 16. + * + * \warning Passing \c 0 as \p tag_len means that the message is nos + * longer authenticated. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match. + * \return A cipher-specific error code on calculation failure. + */ +int mbedtls_ccm_star_auth_decrypt( mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len ); + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +/** + * \brief The CCM checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_ccm_self_test( int verbose ); +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CCM_ALT_H */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/crypto_ecc_hw.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/crypto_ecc_hw.c new file mode 100644 index 0000000..f7c9035 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/crypto_ecc_hw.c @@ -0,0 +1,673 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbedtls/common.h" + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_ECP_ALT) || defined(MBEDTLS_ECP_INTERNAL_ALT) + +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbed_toolchain.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "mbed_toolchain.h" +#include "nu_bitutil.h" +#include "nu_timer.h" +#include "crypto-misc.h" +#include "crypto_ecc_hw.h" +#include "ecp_helper.h" + +/* Enable ECC debug */ +//#define NU_CRYPTO_ECC_ENABLE_DEBUG + +/* Max key size supported */ +#define NU_ECC_MAXKEYBITS 571 +/* Max ECC big-number words */ +#define NU_ECC_BIGNUM_MAXWORD 18 +/* words in limb */ +#define wiL (sizeof (mbedtls_mpi_uint) / sizeof (uint32_t)) +/* Min MPI limbs for ECC big-number */ +#define NU_ECC_BIGNUM_MINLIMB (NU_ECC_BIGNUM_MAXWORD / wiL) + +/* + * Convert between words and number of limbs + * Divide first in order to avoid potential overflows + */ +#define WORDS_TO_LIMBS(i) ( (i) / wiL + ( (i) % wiL != 0 ) ) + +/* Notes for Crypto ECC H/W port + * + * The following point operations are not supported and will cause engine to trap: + * 1. P + P. Workaround by 2*P. + * 2. m*P with SCAP enabled, esp m = 2 or close to (order - 1). Cannot work around by + * fallback to S/W, because following operations are easily to fail with data error. + * Disable SCAP temporarily. + */ + +int crypto_ecc_capable(const mbedtls_ecp_group *grp) +{ + /* Curve types + * + * - Short Weierstrass + * - Montgomery + */ + mbedtls_ecp_curve_type curve_type = mbedtls_ecp_get_type(grp); + if (curve_type == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS) { + return 1; + } else if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + if (grp->id == MBEDTLS_ECP_DP_CURVE25519 || + grp->id == MBEDTLS_ECP_DP_CURVE448) { + return 1; + } else { + return 0; + } + } else { + return 0; + } +} + +int crypto_ecc_init(const mbedtls_ecp_group *grp) +{ + /* Behavior of mbedtls_internal_ecp_init()/mbedtls_internal_ecp_free() + * + * mbedtls_internal_ecp_init()/mbedtls_internal_ecp_free() are like pre-op/post-op calls + * and they guarantee: + * + * 1. Paired + * 2. No overlapping + * 3. Upper public function cannot return when ECP alter. is still activated. + */ + + /* Acquire ownership of ECC accelerator */ + crypto_ecc_acquire(); + + /* Initialize crypto module */ + crypto_init(); + + /* Release ownership of ECC accelerator */ + crypto_ecc_release(); + + return 0; +} + +void crypto_ecc_free(const mbedtls_ecp_group *grp) +{ + /* Acquire ownership of ECC accelerator */ + crypto_ecc_acquire(); + + /* Uninit crypto module */ + crypto_uninit(); + + /* Release ownership of ECC accelerator */ + crypto_ecc_release(); +} + +int crypto_ecc_run_eccop_add(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q, + bool blinding) +{ + /* SCAP is applicable only for PM. */ + blinding = false; + + return crypto_ecc_run_eccop(grp, R, NULL, P, NULL, Q, ECCOP_POINT_ADD, blinding); +} + +int crypto_ecc_run_eccop_double(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, + bool blinding) +{ + /* SCAP is applicable only for PM. */ + blinding = false; + + return crypto_ecc_run_eccop(grp, R, NULL, P, NULL, NULL, ECCOP_POINT_DOUBLE, blinding); +} + +int crypto_ecc_run_eccop_mul(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + bool blinding) +{ + /* NOTE: Engine can trap when SCAP is enabled. See above. */ + blinding = false; + return crypto_ecc_run_eccop(grp, R, m, P, NULL, NULL, ECCOP_POINT_MUL, blinding); +} + +int crypto_ecc_run_eccop(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + MBED_UNUSED const mbedtls_mpi *n, + const mbedtls_ecp_point *Q, + uint32_t eccop, + bool blinding) +{ + /* Check necessary arguments for all ECC operations */ + if (grp == NULL || R == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Check grp->P is positive */ + if (mbedtls_mpi_cmp_int(&grp->P, 0) <= 0) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Check supported maximum key bits */ + if (grp->pbits > NU_ECC_MAXKEYBITS) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + /* NOTE: Engine doesn't support P + Q when P and Q are the same. Workaround by 2*P */ + if (eccop == ECCOP_POINT_ADD) { + if (P == NULL || Q == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + if (mbedtls_ecp_point_cmp(P, Q) == 0) { + return crypto_ecc_run_eccop(grp, R, NULL, P, NULL, NULL, ECCOP_POINT_DOUBLE, blinding); + } + } + + /* Acquire ownership of ECC accelerator */ + crypto_ecc_acquire(); + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + bool ecc_done; + + mbedtls_mpi N_; + const mbedtls_mpi *Np; + + mbedtls_mpi_init(&N_); + + /* Use ECP_HELPER_MPI_NORM(Np, N1, N_, P) to get normalized MPI + * + * N_: Holds normalized MPI if the passed-in MPI N1 is not + * Np: Pointer to normalized MPI, which could be N1 or N_ + */ + + /* Check necessary arguments and handle special cases for specified ECC operation + * + * ECCOP_POINT_MUL R = m*P + * ECCOP_POINT_ADD R = P + Q + * ECCOP_POINT_DOUBLE R = 2*P + * + * ECC accelerator doesn't support R = 0, and we need to detect it. + */ + if (eccop == ECCOP_POINT_MUL) { + /* R = m*P */ + if (m == NULL || P == NULL) { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + /* R = 0*P = 0 or R = P = 0 */ + if (mbedtls_mpi_cmp_int(m, 0) == 0 || mbedtls_mpi_cmp_int(&P->Z, 0) == 0) { + ret = mbedtls_ecp_set_zero(R); + goto cleanup; + } + + /* R = 1*P */ + if (mbedtls_mpi_cmp_int(m, 1) == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_copy(R, P)); + /* Unnecessary because passed-in P and Q are required to be normalized */ + //MBEDTLS_MPI_CHK(internal_ecp_normalize(grp, R)); + goto cleanup; + } + + /* R = m*P = (multiple of order)*G = 0 */ + /* NOTE: If grp->N (order) is a prime, we could detect R = 0 for all m*P cases + * by just checking if m is a multiple of grp->N. Otherwise, sigh. */ + /* TODO: Find an approach to detecting R = 0 for all m*P cases */ + ECP_HELPER_MPI_NORM(&Np, *m, N_, grp->N); + if (mbedtls_mpi_cmp_int(Np, 0) == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_set_zero(R)); + goto cleanup; + } + } else if (eccop == ECCOP_POINT_ADD) { + /* R = P + Q */ + if (P == NULL || Q == NULL) { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + /* R = 0 + Q = Q */ + if (mbedtls_mpi_cmp_int(&P->Z, 0) == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_copy(R, Q)); + /* Unnecessary because passed-in P and Q are required to be normalized */ + //MBEDTLS_MPI_CHK(internal_ecp_normalize(grp, R)); + goto cleanup; + } + + /* R = P + 0 = P */ + if (mbedtls_mpi_cmp_int(&Q->Z, 0) == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_copy(R, P)); + /* Unnecessary because passed-in P and Q are required to be normalized */ + //MBEDTLS_MPI_CHK(internal_ecp_normalize(grp, R)); + goto cleanup; + } + + /* R = P + Q = P + (-P) = 0 */ + MBEDTLS_MPI_CHK(crypto_ecc_run_modop(&N_, &P->Y, &Q->Y, &grp->P, grp->pbits, MODOP_ADD)); + if (mbedtls_mpi_cmp_int(&N_, 0) == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_set_zero(R)); + goto cleanup; + } + } else if (eccop == ECCOP_POINT_DOUBLE) { + /* R = 2*P */ + if (P == NULL) { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + /* R = 2*0 = 0 */ + if (mbedtls_mpi_cmp_int(&P->Z, 0) == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_set_zero(R)); + goto cleanup; + } + + /* R = 2*P = P + P = P + (-P) = 0 */ + MBEDTLS_MPI_CHK(crypto_ecc_run_modop(&N_, &P->Y, &P->Y, &grp->P, grp->pbits, MODOP_ADD)); + if (mbedtls_mpi_cmp_int(&N_, 0) == 0) { + MBEDTLS_MPI_CHK(mbedtls_ecp_set_zero(R)); + goto cleanup; + } + } else { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + /* ECC curve type */ + mbedtls_ecp_curve_type curve_type = mbedtls_ecp_get_type(grp); + uint32_t curve_sel = 0; + switch (curve_type) { + case MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS: + curve_sel = 0; // Short Weierstrass + break; + + case MBEDTLS_ECP_TYPE_MONTGOMERY: + curve_sel = CRPT_ECC_CTL_CSEL_Msk; // Montgomery + break; + + default: + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + + /* Enable ECC interrupt */ + ECC_ENABLE_INT(CRPT); + + /* For safe, recover from previous failure if ever */ + MBEDTLS_MPI_CHK(crypto_ecc_abort(5*1000*1000)); + + /* Configure ECC curve coefficient A */ + if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + /* + * In S/W impl, A is used as (A + 2) / 4. Figure out its original value for engine. + * https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/include/mbedtls/ecp.h#L219-L220 + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_int(&N_, &grp->A, 4)); + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(&N_, &N_, 2)); + Np = &N_; + } else { + /* Special case for A = -3 */ + if (grp->A.p == NULL) { + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&N_, -3)); + ECP_HELPER_MPI_NORM(&Np, N_, N_, grp->P); + } else { + ECP_HELPER_MPI_NORM(&Np, grp->A, N_, grp->P); + } + } + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_A, NU_ECC_BIGNUM_MAXWORD)); + + /* Configure ECC curve coefficient B */ + if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + /* + * In S/W impl, B is unused. Actually, B is 1 for Curve25519/Curve448. + * https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/include/mbedtls/ecp.h#L221-L222 + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&N_, 1)); + Np = &N_; + } else { + ECP_HELPER_MPI_NORM(&Np, grp->B, N_, grp->P); + } + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_B, NU_ECC_BIGNUM_MAXWORD)); + + /* Configure ECC prime modulus */ + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(&grp->P, (uint32_t *) CRPT->ECC_N, NU_ECC_BIGNUM_MAXWORD)); + + /* Configure ECC scalar for point multiplication + * + * Normalize m to within [1, order - 1] which ECCOP_POINT_MUL supports + * Special cases R = 0 should have been detected out above. + */ + if (eccop == ECCOP_POINT_MUL) { + ECP_HELPER_MPI_NORM(&Np, *m, N_, grp->N); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_K, NU_ECC_BIGNUM_MAXWORD)); + /* To enable SCAP, must write order of G into X2 */ + if (blinding) { + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(&grp->N, (uint32_t *) CRPT->ECC_X2, NU_ECC_BIGNUM_MAXWORD)); + } + } + + /* Configure ECC point (X1, Y1) */ + ECP_HELPER_MPI_NORM(&Np, P->X, N_, grp->P); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_X1, NU_ECC_BIGNUM_MAXWORD)); + if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + /* Deduce Y from X for Montgomery curve + * + * For Montgomery curve, y-coord is absent. Deduce it from x-coord. + * https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/source/ecp_curves.c#L702-L706 + * https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/source/ecp_curves.c#L741-L745 + * + * Per real test, y-coord is necessary for engine. + */ + MBEDTLS_MPI_CHK(ecp_helper_deduce_y(grp, &N_, &P->X)); + Np = &N_; + } else { + ECP_HELPER_MPI_NORM(&Np, P->Y, N_, grp->P); + } + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_Y1, NU_ECC_BIGNUM_MAXWORD)); + + /* Configure ECC points (X2, Y2) */ + if (eccop == ECCOP_POINT_ADD) { + ECP_HELPER_MPI_NORM(&Np, Q->X, N_, grp->P); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_X2, NU_ECC_BIGNUM_MAXWORD)); + if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + /* Deduce Y from X (see above) */ + MBEDTLS_MPI_CHK(ecp_helper_deduce_y(grp, &N_, &Q->X)); + Np = &N_; + } else { + ECP_HELPER_MPI_NORM(&Np, Q->Y, N_, grp->P); + } + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_Y2, NU_ECC_BIGNUM_MAXWORD)); + } + + /* Configure for point operation */ + uint32_t ecc_ctl = 0 | + CRPT_ECC_CTL_START_Msk | // Start + CRPT_ECC_CTL_FSEL_Msk | // Prime field (GF(p)) + eccop | // Point operation + curve_sel | // Curve selection + (grp->pbits << CRPT_ECC_CTL_CURVEM_Pos) | // Key length of elliptic curve + (blinding ? CRPT_ECC_CTL_SCAP_Msk : 0) | // SCAP + 0; + + crypto_ecc_prestart(); +#if defined(NU_CRYPTO_ECC_ENABLE_DEBUG) && !defined(MBEDTLS_ECP_INTERNAL_ALT) + mbedtls_printf("[CRPT][ECC] Crypto ECC ...\n"); +#endif + CRPT->ECC_CTL = ecc_ctl; + ecc_done = crypto_ecc_wait2(1000*1000); // 1s timeout +#if defined(NU_CRYPTO_ECC_ENABLE_DEBUG) && !defined(MBEDTLS_ECP_INTERNAL_ALT) + mbedtls_printf("[CRPT][ECC] Crypto ECC ... %s\n", ecc_done ? "Done" : "Error"); +#endif + + /* For safe, recover from current failure */ + if (!ecc_done) { + crypto_ecc_abort(5*1000*1000); + } + + /* Disable ECC interrupt */ + ECC_DISABLE_INT(CRPT); + + MBEDTLS_MPI_CHK(ecc_done ? 0 : MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + + /* (X1, Y1) hold the normalized result. */ + MBEDTLS_MPI_CHK(crypto_ecc_mpi_read_eccreg(&R->X, (uint32_t *) CRPT->ECC_X1, NU_ECC_BIGNUM_MAXWORD)); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_read_eccreg(&R->Y, (uint32_t *) CRPT->ECC_Y1, NU_ECC_BIGNUM_MAXWORD)); + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&R->Z, 1)); + +cleanup: + + mbedtls_mpi_free(&N_); + + /* Release ownership of ECC accelerator */ + crypto_ecc_release(); + + return ret; +} + +int crypto_ecc_run_modop(mbedtls_mpi *r, + const mbedtls_mpi *o1, + const mbedtls_mpi *o2, + const mbedtls_mpi *p, + uint32_t pbits, + uint32_t modop) +{ + if (r == NULL || + o1 == NULL || + o2 == NULL || + p == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Check o1/o2 are not negative */ + if (mbedtls_mpi_cmp_int(o1, 0) < 0 || + mbedtls_mpi_cmp_int(o2, 0) < 0) { + return MBEDTLS_ERR_MPI_NEGATIVE_VALUE; + } + + /* Check p is positive */ + if (mbedtls_mpi_cmp_int(p, 0) <= 0) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Check supported maximum key bits */ + if (pbits > NU_ECC_MAXKEYBITS) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + /* Check MODOP operations are legal */ + if (modop != MODOP_DIV && + modop != MODOP_MUL && + modop != MODOP_ADD && + modop != MODOP_SUB) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Check divisor is not zero in MODOP_DIV operation */ + if (modop == MODOP_DIV && mbedtls_mpi_cmp_int(o2, 0) == 0) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Acquire ownership of ECC accelerator */ + crypto_ecc_acquire(); + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + bool ecc_done; + + mbedtls_mpi N_; + const mbedtls_mpi *Np; + + mbedtls_mpi_init(&N_); + + /* Enable ECC interrupt */ + ECC_ENABLE_INT(CRPT); + + /* For safe, recover from previous failure if ever */ + MBEDTLS_MPI_CHK(crypto_ecc_abort(5*1000*1000)); + + /* Use ECP_HELPER_MPI_NORM(Np, N1, N_, P) to get normalized MPI + * + * N_: Holds normalized MPI if the passed-in MPI N1 is not + * Np: Pointer to normalized MPI, which could be N1 or N_ + */ + + if (modop == MODOP_MUL || + modop == MODOP_ADD || + modop == MODOP_SUB) { + ECP_HELPER_MPI_NORM(&Np, *o1, N_, *p); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_X1, NU_ECC_BIGNUM_MAXWORD)); + ECP_HELPER_MPI_NORM(&Np, *o2, N_, *p); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_Y1, NU_ECC_BIGNUM_MAXWORD)); + } else if (modop == MODOP_DIV) { + ECP_HELPER_MPI_NORM(&Np, *o2, N_, *p); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_X1, NU_ECC_BIGNUM_MAXWORD)); + ECP_HELPER_MPI_NORM(&Np, *o1, N_, *p); + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(Np, (uint32_t *) CRPT->ECC_Y1, NU_ECC_BIGNUM_MAXWORD)); + } else { + MBEDTLS_MPI_CHK(MBEDTLS_ERR_ECP_BAD_INPUT_DATA); + } + + MBEDTLS_MPI_CHK(crypto_ecc_mpi_write_eccreg(p, (uint32_t *) CRPT->ECC_N, NU_ECC_BIGNUM_MAXWORD)); + + /* Configure for modulus operation */ + uint32_t ecc_ctl = 0 | + CRPT_ECC_CTL_START_Msk | // Start + CRPT_ECC_CTL_FSEL_Msk | // Prime field (GF(p)) + ECCOP_MODULE | // No point operation + modop | // Modulus operation + (pbits << CRPT_ECC_CTL_CURVEM_Pos) | // Key length of elliptic curve + 0; + + crypto_ecc_prestart(); +#if defined(NU_CRYPTO_ECC_ENABLE_DEBUG) && !defined(MBEDTLS_ECP_INTERNAL_ALT) + mbedtls_printf("[CRPT][ECC] Crypto Modulus ...\n"); +#endif + CRPT->ECC_CTL = ecc_ctl; + ecc_done = crypto_ecc_wait2(1000*1000); // 1s timeout +#if defined(NU_CRYPTO_ECC_ENABLE_DEBUG) && !defined(MBEDTLS_ECP_INTERNAL_ALT) + mbedtls_printf("[CRPT][ECC] Crypto Modulus ... %s\n", ecc_done ? "Done" : "Fallback"); +#endif + + /* For safe, recover from current failure */ + if (!ecc_done) { + crypto_ecc_abort(5*1000*1000); + } + + /* Disable ECC interrupt */ + ECC_DISABLE_INT(CRPT); + + MBEDTLS_MPI_CHK(ecc_done ? 0 : MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + + /* X1 holds the result. */ + MBEDTLS_MPI_CHK(crypto_ecc_mpi_read_eccreg(r, (uint32_t *) CRPT->ECC_X1, NU_ECC_BIGNUM_MAXWORD)); + +cleanup: + + mbedtls_mpi_free(&N_); + + /* Release ownership of ECC accelerator */ + crypto_ecc_release(); + + return ret; +} + +int crypto_ecc_mpi_read_eccreg(mbedtls_mpi *x, const volatile uint32_t *eccreg, size_t eccreg_num) +{ + if (x == NULL) { + return MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + } + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i, n; + + for (n = eccreg_num; n > 0; n --) { + if (eccreg[n - 1] != 0) { + break; + } + } + + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(x, 0)); + MBEDTLS_MPI_CHK(mbedtls_mpi_grow(x, WORDS_TO_LIMBS(n))); + + for (i = 0; i < n; i ++) { + x->p[i / wiL] |= ((mbedtls_mpi_uint) eccreg[i]) << ((i % wiL) << 5); + } + +cleanup: + + return ret; +} + +int crypto_ecc_mpi_write_eccreg( const mbedtls_mpi *x, volatile uint32_t *eccreg, size_t eccreg_num ) +{ + if (x == NULL) { + return MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + } + + if (mbedtls_mpi_cmp_int(x, 0) < 0) { + return MBEDTLS_ERR_MPI_NEGATIVE_VALUE; + } + + size_t i, n; + + /* How many words needed? */ + n = (mbedtls_mpi_size(x) + sizeof (uint32_t) - 1) / sizeof (uint32_t); + + if (eccreg_num < n) { + return MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL; + } + + /* Fill non-zero part */ + for (i = 0; i < n; i ++) { + eccreg[i] = (uint32_t) (x->p[i / wiL] >> ((i % wiL) << 5)); + } + + /* Zeroize remaining part + * + * crypto_zeroize32() has excluded optimization doubt, so we can safely set H/W registers to 0 via it. + */ + crypto_zeroize32((uint32_t *) eccreg + n, eccreg_num - n); + + return 0; +} + +int crypto_ecc_abort(uint32_t timeout_us) +{ + /* Acquire ownership of ECC H/W */ + crypto_ecc_acquire(); + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + CRPT->ECC_CTL = CRPT_ECC_CTL_STOP_Msk; + struct nu_countdown_ctx_s cd_ctx; + nu_countdown_init(&cd_ctx, timeout_us); + while (CRPT->ECC_STS & CRPT_ECC_STS_BUSY_Msk) { + if (nu_countdown_expired(&cd_ctx)) { + break; + } + } + nu_countdown_free(&cd_ctx); + if (CRPT->ECC_STS & CRPT_ECC_STS_BUSY_Msk) { +#if defined(NU_CRYPTO_ECC_ENABLE_DEBUG) && !defined(MBEDTLS_ECP_INTERNAL_ALT) + mbedtls_printf("[CRPT][ECC] Crypto ECC ... Busy\n"); +#endif + ret = MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + goto cleanup; + } + + ret = 0; + +cleanup: + + /* Release ownership of ECC accelerator */ + crypto_ecc_release(); + + return ret; +} + +#endif /* MBEDTLS_ECP_ALT || MBEDTLS_ECP_INTERNAL_ALT */ +#endif /* MBEDTLS_ECP_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/crypto_ecc_hw.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/crypto_ecc_hw.h new file mode 100644 index 0000000..3bcb43c --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/crypto_ecc_hw.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef CRYPTO_ECC_HW_H +#define CRYPTO_ECC_HW_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECP_ALT) || defined(MBEDTLS_ECP_INTERNAL_ALT) + +#include "mbedtls/ecp.h" +#include + +/* Crypto ECC H/W point operations */ +#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_DOUBLE (0x3UL << CRPT_ECC_CTL_ECCOP_Pos) + +/* Crypto ECC H/W modulus operations */ +#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief This function checks whether a given group can be used + * for Crypto ECC H/W. + * + * \param grp ECP group + * + * \return \c 1 if the group can be used, \c 0 otherwise + */ +int crypto_ecc_capable(const mbedtls_ecp_group *grp); + +/** + * \brief Initialize/Free Crypto ECC H/W + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + * + * \note crypto_ecp_init()/crypto_ecp_free() are like pre-op/post-op calls + * and they guarantee: + * + * 1. Paired + * 2. No overlapping + * 3. Upper public function cannot return when ECP alter. is still activated. + */ +int crypto_ecc_init(const mbedtls_ecp_group *grp); +void crypto_ecc_free(const mbedtls_ecp_group *grp); +/** + * \brief Configure ECCOP operation, start it, and wait for its completion + * + * \param grp ECP group + * \param R Destination point + * \param m Integer by which to multiply P + * \param P Point to multiply by m + * \param n Integer by which to multiply Q + * \param Q Point to be multiplied by n + * \param eccop ECCOP code. Could be ECCOP_POINT_MUL/ADD/DOUBLE + * \param blinding Blinding (SCAP) or not. + * Dependent on passed-in eccop, only partial parameters among m/P/n/Q are needed and checked. + * ECCOP_POINT_MUL R = m*P + * ECCOP_POINT_ADD R = P + Q + * ECCOP_POINT_DOUBLE R = 2*P + * + * \return 0 if successful + * + * \note P/Q must be normalized (= affine). R would be normalized. + * + * \note m/n could be negative. + * + * \note ECC accelerator doesn't support R = 0, and we need to detect it additionally. + * For R = P + Q or R = 2*P, we can detect all R = 0 cases. + * For R = m*P, we can detect all R = 0 cases only if grp->N (order) is a prime. + * + * \note According to ECCOP operation, n is unnecessary. But to be consistent with R = m*P + n*Q, + * n is kept with unused modifier. + * + * \note Blinding (SCAP) is applicable only for point multiplication. But for future extension, + * blinding is kept with all point operations. + * + */ +int crypto_ecc_run_eccop_add(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q, + bool blinding); +int crypto_ecc_run_eccop_double(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, + bool blinding); +int crypto_ecc_run_eccop_mul(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + bool blinding); +int crypto_ecc_run_eccop(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + const mbedtls_mpi *n, + const mbedtls_ecp_point *Q, + uint32_t eccop, + bool blinding); + +/** + * \brief Configure MODOP operation and wait for its completion + * + * \param r Destination MPI + * \param o1 Input MPI for first operand of MODOP + * \param o2 Input MPI for second operand of MODOP + * \param p Prime modulus + * \param pbits Bit number of p + * \param modop ECCOP code. Could be MODOP_ADD/SUB/MUL/DIV + * MODOP_ADD r = o1 + o2 mod p + * MODOP_SUB r = o1 - o2 mod p + * MODOP_MUL r = o1 * o2 mod p + * MODOP_DIV r = o1 / o2 mod p + * + * \return 0 if successful + * + * \note o1/o2 must be normalized (within [0, p - 1]). r would be normalized. + */ +int crypto_ecc_run_modop(mbedtls_mpi *r, + const mbedtls_mpi *o1, + const mbedtls_mpi *o2, + const mbedtls_mpi *p, + uint32_t pbits, + uint32_t modop); + +/** + * \brief Import X from ECC registers, little endian + * + * \param X Destination MPI + * \param eccreg Start of input ECC register + * \param eccreg_num Number of input ECC register + * + * \return 0 if successful + * + * \note Destination MPI is always non-negative. + */ +int crypto_ecc_mpi_read_eccreg( mbedtls_mpi *X, const volatile uint32_t *eccreg, size_t eccreg_num ); + +/** + * \brief Export X into ECC registers, little endian + * + * \param X Source MPI + * \param eccreg Start of ECC output registers + * \param eccreg_num Number of ECC output registers + * + * \return 0 if successful + * + * \note Source MPI cannot be negative. + * \note Fills the remaining MSB ECC registers with zeros if X doesn't cover all. + */ +int crypto_ecc_mpi_write_eccreg( const mbedtls_mpi *X, volatile uint32_t *eccreg, size_t eccreg_num ); + +/** + * \brief Abort Crypto ECC H/W + * + * \param timeout_us Timeout in microseconds. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int crypto_ecc_abort(uint32_t timeout_us); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_ECP_ALT || MBEDTLS_ECP_INTERNAL_ALT */ +#endif /* CRYPTO_ECC_HW_H */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_alt.c new file mode 100644 index 0000000..ffd6ebe --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_alt.c @@ -0,0 +1,3605 @@ +/* + * Elliptic curves over GF(p): generic functions + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * References: + * + * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone + * FIPS 186-3 http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf + * RFC 4492 for the related TLS structures and constants + * RFC 7748 for the Curve448 and Curve25519 curve definitions + * + * [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf + * + * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis + * for elliptic curve cryptosystems. In : Cryptographic Hardware and + * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. + * + * + * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to + * render ECC resistant against Side Channel Attacks. IACR Cryptology + * ePrint Archive, 2004, vol. 2004, p. 342. + * + */ + +#include "common.h" + +/** + * \brief Function level alternative implementation. + * + * The MBEDTLS_ECP_INTERNAL_ALT macro enables alternative implementations to + * replace certain functions in this module. The alternative implementations are + * typically hardware accelerators and need to activate the hardware before the + * computation starts and deactivate it after it finishes. The + * mbedtls_internal_ecp_init() and mbedtls_internal_ecp_free() functions serve + * this purpose. + * + * To preserve the correct functionality the following conditions must hold: + * + * - The alternative implementation must be activated by + * mbedtls_internal_ecp_init() before any of the replaceable functions is + * called. + * - mbedtls_internal_ecp_free() must \b only be called when the alternative + * implementation is activated. + * - mbedtls_internal_ecp_init() must \b not be called when the alternative + * implementation is activated. + * - Public functions must not return while the alternative implementation is + * activated. + * - Replaceable functions are guarded by \c MBEDTLS_ECP_XXX_ALT macros and + * before calling them an \code if( mbedtls_internal_ecp_grp_capable( grp ) ) + * \endcode ensures that the alternative implementation supports the current + * group. + */ +#if defined(MBEDTLS_ECP_INTERNAL_ALT) +#endif + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/threading.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" + +#include + +#if defined(NU_CRYPTO_ECC_ENABLE) +#include "crypto_ecc_hw.h" +#endif + +#if defined(MBEDTLS_ECP_ALT) + +/* Parameter validation macros based on platform_util.h */ +#define ECP_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECP_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include "mbedtls/ecp_internal.h" + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) +#if defined(MBEDTLS_HMAC_DRBG_C) +#include "mbedtls/hmac_drbg.h" +#elif defined(MBEDTLS_CTR_DRBG_C) +#include "mbedtls/ctr_drbg.h" +#else +#error "Invalid configuration detected. Include check_config.h to ensure that the configuration is valid." +#endif +#endif /* MBEDTLS_ECP_NO_INTERNAL_RNG */ + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#if defined(MBEDTLS_SELF_TEST) +/* + * Counts of point addition and doubling, and field multiplications. + * Used to test resistance of point multiplication to simple timing attacks. + */ +static unsigned long add_count, dbl_count, mul_count; +#endif + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) +/* + * Currently ecp_mul() takes a RNG function as an argument, used for + * side-channel protection, but it can be NULL. The initial reasoning was + * that people will pass non-NULL RNG when they care about side-channels, but + * unfortunately we have some APIs that call ecp_mul() with a NULL RNG, with + * no opportunity for the user to do anything about it. + * + * The obvious strategies for addressing that include: + * - change those APIs so that they take RNG arguments; + * - require a global RNG to be available to all crypto modules. + * + * Unfortunately those would break compatibility. So what we do instead is + * have our own internal DRBG instance, seeded from the secret scalar. + * + * The following is a light-weight abstraction layer for doing that with + * HMAC_DRBG (first choice) or CTR_DRBG. + */ + +#if defined(MBEDTLS_HMAC_DRBG_C) + +/* DRBG context type */ +typedef mbedtls_hmac_drbg_context ecp_drbg_context; + +/* DRBG context init */ +static inline void ecp_drbg_init( ecp_drbg_context *ctx ) +{ + mbedtls_hmac_drbg_init( ctx ); +} + +/* DRBG context free */ +static inline void ecp_drbg_free( ecp_drbg_context *ctx ) +{ + mbedtls_hmac_drbg_free( ctx ); +} + +/* DRBG function */ +static inline int ecp_drbg_random( void *p_rng, + unsigned char *output, size_t output_len ) +{ + return( mbedtls_hmac_drbg_random( p_rng, output, output_len ) ); +} + +/* DRBG context seeding */ +static int ecp_drbg_seed( ecp_drbg_context *ctx, + const mbedtls_mpi *secret, size_t secret_len ) +{ + int ret; + unsigned char secret_bytes[MBEDTLS_ECP_MAX_BYTES]; + /* The list starts with strong hashes */ + const mbedtls_md_type_t md_type = mbedtls_md_list()[0]; + const mbedtls_md_info_t *md_info = mbedtls_md_info_from_type( md_type ); + + if( secret_len > MBEDTLS_ECP_MAX_BYTES ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( secret, + secret_bytes, secret_len ) ); + + ret = mbedtls_hmac_drbg_seed_buf( ctx, md_info, secret_bytes, secret_len ); + +cleanup: + mbedtls_platform_zeroize( secret_bytes, secret_len ); + + return( ret ); +} + +#elif defined(MBEDTLS_CTR_DRBG_C) + +/* DRBG context type */ +typedef mbedtls_ctr_drbg_context ecp_drbg_context; + +/* DRBG context init */ +static inline void ecp_drbg_init( ecp_drbg_context *ctx ) +{ + mbedtls_ctr_drbg_init( ctx ); +} + +/* DRBG context free */ +static inline void ecp_drbg_free( ecp_drbg_context *ctx ) +{ + mbedtls_ctr_drbg_free( ctx ); +} + +/* DRBG function */ +static inline int ecp_drbg_random( void *p_rng, + unsigned char *output, size_t output_len ) +{ + return( mbedtls_ctr_drbg_random( p_rng, output, output_len ) ); +} + +/* + * Since CTR_DRBG doesn't have a seed_buf() function the way HMAC_DRBG does, + * we need to pass an entropy function when seeding. So we use a dummy + * function for that, and pass the actual entropy as customisation string. + * (During seeding of CTR_DRBG the entropy input and customisation string are + * concatenated before being used to update the secret state.) + */ +static int ecp_ctr_drbg_null_entropy(void *ctx, unsigned char *out, size_t len) +{ + (void) ctx; + memset( out, 0, len ); + return( 0 ); +} + +/* DRBG context seeding */ +static int ecp_drbg_seed( ecp_drbg_context *ctx, + const mbedtls_mpi *secret, size_t secret_len ) +{ + int ret; + unsigned char secret_bytes[MBEDTLS_ECP_MAX_BYTES]; + + if( secret_len > MBEDTLS_ECP_MAX_BYTES ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( secret, + secret_bytes, secret_len ) ); + + ret = mbedtls_ctr_drbg_seed( ctx, ecp_ctr_drbg_null_entropy, NULL, + secret_bytes, secret_len ); + +cleanup: + mbedtls_platform_zeroize( secret_bytes, secret_len ); + + return( ret ); +} + +#else +#error "Invalid configuration detected. Include check_config.h to ensure that the configuration is valid." +#endif /* DRBG modules */ +#endif /* MBEDTLS_ECP_NO_INTERNAL_RNG */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/* + * Maximum number of "basic operations" to be done in a row. + * + * Default value 0 means that ECC operations will not yield. + * Note that regardless of the value of ecp_max_ops, always at + * least one step is performed before yielding. + * + * Setting ecp_max_ops=1 can be suitable for testing purposes + * as it will interrupt computation at all possible points. + */ +static unsigned ecp_max_ops = 0; + +/* + * Set ecp_max_ops + */ +void mbedtls_ecp_set_max_ops( unsigned max_ops ) +{ + ecp_max_ops = max_ops; +} + +/* + * Check if restart is enabled + */ +int mbedtls_ecp_restart_is_enabled( void ) +{ + return( ecp_max_ops != 0 ); +} + +/* + * Restart sub-context for ecp_mul_comb() + */ +struct mbedtls_ecp_restart_mul +{ + mbedtls_ecp_point R; /* current intermediate result */ + size_t i; /* current index in various loops, 0 outside */ + mbedtls_ecp_point *T; /* table for precomputed points */ + unsigned char T_size; /* number of points in table T */ + enum { /* what were we doing last time we returned? */ + ecp_rsm_init = 0, /* nothing so far, dummy initial state */ + ecp_rsm_pre_dbl, /* precompute 2^n multiples */ + ecp_rsm_pre_norm_dbl, /* normalize precomputed 2^n multiples */ + ecp_rsm_pre_add, /* precompute remaining points by adding */ + ecp_rsm_pre_norm_add, /* normalize all precomputed points */ + ecp_rsm_comb_core, /* ecp_mul_comb_core() */ + ecp_rsm_final_norm, /* do the final normalization */ + } state; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_context drbg_ctx; + unsigned char drbg_seeded; +#endif +}; + +/* + * Init restart_mul sub-context + */ +static void ecp_restart_rsm_init( mbedtls_ecp_restart_mul_ctx *ctx ) +{ + mbedtls_ecp_point_init( &ctx->R ); + ctx->i = 0; + ctx->T = NULL; + ctx->T_size = 0; + ctx->state = ecp_rsm_init; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_init( &ctx->drbg_ctx ); + ctx->drbg_seeded = 0; +#endif +} + +/* + * Free the components of a restart_mul sub-context + */ +static void ecp_restart_rsm_free( mbedtls_ecp_restart_mul_ctx *ctx ) +{ + unsigned char i; + + if( ctx == NULL ) + return; + + mbedtls_ecp_point_free( &ctx->R ); + + if( ctx->T != NULL ) + { + for( i = 0; i < ctx->T_size; i++ ) + mbedtls_ecp_point_free( ctx->T + i ); + mbedtls_free( ctx->T ); + } + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_free( &ctx->drbg_ctx ); +#endif + + ecp_restart_rsm_init( ctx ); +} + +/* + * Restart context for ecp_muladd() + */ +struct mbedtls_ecp_restart_muladd +{ + mbedtls_ecp_point mP; /* mP value */ + mbedtls_ecp_point R; /* R intermediate result */ + enum { /* what should we do next? */ + ecp_rsma_mul1 = 0, /* first multiplication */ + ecp_rsma_mul2, /* second multiplication */ + ecp_rsma_add, /* addition */ + ecp_rsma_norm, /* normalization */ + } state; +}; + +/* + * Init restart_muladd sub-context + */ +static void ecp_restart_ma_init( mbedtls_ecp_restart_muladd_ctx *ctx ) +{ + mbedtls_ecp_point_init( &ctx->mP ); + mbedtls_ecp_point_init( &ctx->R ); + ctx->state = ecp_rsma_mul1; +} + +/* + * Free the components of a restart_muladd sub-context + */ +static void ecp_restart_ma_free( mbedtls_ecp_restart_muladd_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_ecp_point_free( &ctx->mP ); + mbedtls_ecp_point_free( &ctx->R ); + + ecp_restart_ma_init( ctx ); +} + +/* + * Initialize a restart context + */ +void mbedtls_ecp_restart_init( mbedtls_ecp_restart_ctx *ctx ) +{ + ECP_VALIDATE( ctx != NULL ); + ctx->ops_done = 0; + ctx->depth = 0; + ctx->rsm = NULL; + ctx->ma = NULL; +} + +/* + * Free the components of a restart context + */ +void mbedtls_ecp_restart_free( mbedtls_ecp_restart_ctx *ctx ) +{ + if( ctx == NULL ) + return; + + ecp_restart_rsm_free( ctx->rsm ); + mbedtls_free( ctx->rsm ); + + ecp_restart_ma_free( ctx->ma ); + mbedtls_free( ctx->ma ); + + mbedtls_ecp_restart_init( ctx ); +} + +/* + * Check if we can do the next step + */ +int mbedtls_ecp_check_budget( const mbedtls_ecp_group *grp, + mbedtls_ecp_restart_ctx *rs_ctx, + unsigned ops ) +{ + ECP_VALIDATE_RET( grp != NULL ); + + if( rs_ctx != NULL && ecp_max_ops != 0 ) + { + /* scale depending on curve size: the chosen reference is 256-bit, + * and multiplication is quadratic. Round to the closest integer. */ + if( grp->pbits >= 512 ) + ops *= 4; + else if( grp->pbits >= 384 ) + ops *= 2; + + /* Avoid infinite loops: always allow first step. + * Because of that, however, it's not generally true + * that ops_done <= ecp_max_ops, so the check + * ops_done > ecp_max_ops below is mandatory. */ + if( ( rs_ctx->ops_done != 0 ) && + ( rs_ctx->ops_done > ecp_max_ops || + ops > ecp_max_ops - rs_ctx->ops_done ) ) + { + return( MBEDTLS_ERR_ECP_IN_PROGRESS ); + } + + /* update running count */ + rs_ctx->ops_done += ops; + } + + return( 0 ); +} + +/* Call this when entering a function that needs its own sub-context */ +#define ECP_RS_ENTER( SUB ) do { \ + /* reset ops count for this call if top-level */ \ + if( rs_ctx != NULL && rs_ctx->depth++ == 0 ) \ + rs_ctx->ops_done = 0; \ + \ + /* set up our own sub-context if needed */ \ + if( mbedtls_ecp_restart_is_enabled() && \ + rs_ctx != NULL && rs_ctx->SUB == NULL ) \ + { \ + rs_ctx->SUB = mbedtls_calloc( 1, sizeof( *rs_ctx->SUB ) ); \ + if( rs_ctx->SUB == NULL ) \ + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); \ + \ + ecp_restart_## SUB ##_init( rs_ctx->SUB ); \ + } \ +} while( 0 ) + +/* Call this when leaving a function that needs its own sub-context */ +#define ECP_RS_LEAVE( SUB ) do { \ + /* clear our sub-context when not in progress (done or error) */ \ + if( rs_ctx != NULL && rs_ctx->SUB != NULL && \ + ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) \ + { \ + ecp_restart_## SUB ##_free( rs_ctx->SUB ); \ + mbedtls_free( rs_ctx->SUB ); \ + rs_ctx->SUB = NULL; \ + } \ + \ + if( rs_ctx != NULL ) \ + rs_ctx->depth--; \ +} while( 0 ) + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +#define ECP_RS_ENTER( sub ) (void) rs_ctx; +#define ECP_RS_LEAVE( sub ) (void) rs_ctx; + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/* + * List of supported curves: + * - internal ID + * - TLS NamedCurve ID (RFC 4492 sec. 5.1.1, RFC 7071 sec. 2, RFC 8446 sec. 4.2.7) + * - size in bits + * - readable name + * + * Curves are listed in order: largest curves first, and for a given size, + * fastest curves first. This provides the default order for the SSL module. + * + * Reminder: update profiles in x509_crt.c when adding a new curves! + */ +static const mbedtls_ecp_curve_info ecp_supported_curves[] = +{ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + { MBEDTLS_ECP_DP_SECP521R1, 25, 521, "secp521r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + { MBEDTLS_ECP_DP_BP512R1, 28, 512, "brainpoolP512r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + { MBEDTLS_ECP_DP_SECP384R1, 24, 384, "secp384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + { MBEDTLS_ECP_DP_BP384R1, 27, 384, "brainpoolP384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + { MBEDTLS_ECP_DP_SECP256R1, 23, 256, "secp256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + { MBEDTLS_ECP_DP_SECP256K1, 22, 256, "secp256k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + { MBEDTLS_ECP_DP_BP256R1, 26, 256, "brainpoolP256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + { MBEDTLS_ECP_DP_SECP224R1, 21, 224, "secp224r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + { MBEDTLS_ECP_DP_SECP224K1, 20, 224, "secp224k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + { MBEDTLS_ECP_DP_SECP192R1, 19, 192, "secp192r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + { MBEDTLS_ECP_DP_SECP192K1, 18, 192, "secp192k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + { MBEDTLS_ECP_DP_CURVE25519, 29, 256, "x25519" }, +#endif +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + { MBEDTLS_ECP_DP_CURVE448, 30, 448, "x448" }, +#endif + { MBEDTLS_ECP_DP_NONE, 0, 0, NULL }, +}; + +#define ECP_NB_CURVES sizeof( ecp_supported_curves ) / \ + sizeof( ecp_supported_curves[0] ) + +static mbedtls_ecp_group_id ecp_supported_grp_id[ECP_NB_CURVES]; + +/* + * List of supported curves and associated info + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list( void ) +{ + return( ecp_supported_curves ); +} + +/* + * List of supported curves, group ID only + */ +const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list( void ) +{ + static int init_done = 0; + + if( ! init_done ) + { + size_t i = 0; + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + ecp_supported_grp_id[i++] = curve_info->grp_id; + } + ecp_supported_grp_id[i] = MBEDTLS_ECP_DP_NONE; + + init_done = 1; + } + + return( ecp_supported_grp_id ); +} + +/* + * Get the curve info for the internal identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id( mbedtls_ecp_group_id grp_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->grp_id == grp_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the TLS identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id( uint16_t tls_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->tls_id == tls_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the name + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name( const char *name ) +{ + const mbedtls_ecp_curve_info *curve_info; + + if( name == NULL ) + return( NULL ); + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( strcmp( curve_info->name, name ) == 0 ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the type of a curve + */ +mbedtls_ecp_curve_type mbedtls_ecp_get_type( const mbedtls_ecp_group *grp ) +{ + if( grp->G.X.p == NULL ) + return( MBEDTLS_ECP_TYPE_NONE ); + + if( grp->G.Y.p == NULL ) + return( MBEDTLS_ECP_TYPE_MONTGOMERY ); + else + return( MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ); +} + +/* + * Initialize (the components of) a point + */ +void mbedtls_ecp_point_init( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE( pt != NULL ); + + mbedtls_mpi_init( &pt->X ); + mbedtls_mpi_init( &pt->Y ); + mbedtls_mpi_init( &pt->Z ); +} + +/* + * Initialize (the components of) a group + */ +void mbedtls_ecp_group_init( mbedtls_ecp_group *grp ) +{ + ECP_VALIDATE( grp != NULL ); + + grp->id = MBEDTLS_ECP_DP_NONE; + mbedtls_mpi_init( &grp->P ); + mbedtls_mpi_init( &grp->A ); + mbedtls_mpi_init( &grp->B ); + mbedtls_ecp_point_init( &grp->G ); + mbedtls_mpi_init( &grp->N ); + grp->pbits = 0; + grp->nbits = 0; + grp->h = 0; + grp->modp = NULL; + grp->t_pre = NULL; + grp->t_post = NULL; + grp->t_data = NULL; + grp->T = NULL; + grp->T_size = 0; + +#if defined(NU_CRYPTO_ECC_ENABLE) + grp->hw_init = 0; +#endif +} + +/* + * Initialize (the components of) a key pair + */ +void mbedtls_ecp_keypair_init( mbedtls_ecp_keypair *key ) +{ + ECP_VALIDATE( key != NULL ); + + mbedtls_ecp_group_init( &key->grp ); + mbedtls_mpi_init( &key->d ); + mbedtls_ecp_point_init( &key->Q ); +} + +/* + * Unallocate (the components of) a point + */ +void mbedtls_ecp_point_free( mbedtls_ecp_point *pt ) +{ + if( pt == NULL ) + return; + + mbedtls_mpi_free( &( pt->X ) ); + mbedtls_mpi_free( &( pt->Y ) ); + mbedtls_mpi_free( &( pt->Z ) ); +} + +/* + * Unallocate (the components of) a group + */ +void mbedtls_ecp_group_free( mbedtls_ecp_group *grp ) +{ + size_t i; + + if( grp == NULL ) + return; + +#if defined(NU_CRYPTO_ECC_ENABLE) + if (grp->hw_init) { + crypto_ecc_free(grp); + grp->hw_init = 0; + } +#endif + + if( grp->h != 1 ) + { + mbedtls_mpi_free( &grp->P ); + mbedtls_mpi_free( &grp->A ); + mbedtls_mpi_free( &grp->B ); + mbedtls_ecp_point_free( &grp->G ); + mbedtls_mpi_free( &grp->N ); + } + + if( grp->T != NULL ) + { + for( i = 0; i < grp->T_size; i++ ) + mbedtls_ecp_point_free( &grp->T[i] ); + mbedtls_free( grp->T ); + } + + mbedtls_platform_zeroize( grp, sizeof( mbedtls_ecp_group ) ); +} + +/* + * Unallocate (the components of) a key pair + */ +void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key ) +{ + if( key == NULL ) + return; + + mbedtls_ecp_group_free( &key->grp ); + mbedtls_mpi_free( &key->d ); + mbedtls_ecp_point_free( &key->Q ); +} + +/* + * Copy the contents of a point + */ +int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->X, &Q->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Y, &Q->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Z, &Q->Z ) ); + +cleanup: + return( ret ); +} + +/* + * Copy the contents of a group object + */ +int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst, const mbedtls_ecp_group *src ) +{ + ECP_VALIDATE_RET( dst != NULL ); + ECP_VALIDATE_RET( src != NULL ); + + return( mbedtls_ecp_group_load( dst, src->id ) ); +} + +/* + * Set point to zero + */ +int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + ECP_VALIDATE_RET( pt != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->X , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Y , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z , 0 ) ); + +cleanup: + return( ret ); +} + +/* + * Tell if a point is zero + */ +int mbedtls_ecp_is_zero( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( pt != NULL ); + + return( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ); +} + +/* + * Compare two points lazily + */ +int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( mbedtls_mpi_cmp_mpi( &P->X, &Q->X ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Y, &Q->Y ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Z, &Q->Z ) == 0 ) + { + return( 0 ); + } + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Import a non-zero point from ASCII strings + */ +int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix, + const char *x, const char *y ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( x != NULL ); + ECP_VALIDATE_RET( y != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->X, radix, x ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->Y, radix, y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Export a point into unsigned binary data (SEC1 2.3.3 and RFC7748) + */ +int mbedtls_ecp_point_write_binary( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *P, + int format, size_t *olen, + unsigned char *buf, size_t buflen ) +{ + int ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + plen = mbedtls_mpi_size( &grp->P ); + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + (void) format; /* Montgomery curves always use the same point format */ + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + *olen = plen; + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary_le( &P->X, buf, plen ) ); + } +#endif +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* + * Common case: P == 0 + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + { + if( buflen < 1 ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x00; + *olen = 1; + + return( 0 ); + } + + if( format == MBEDTLS_ECP_PF_UNCOMPRESSED ) + { + *olen = 2 * plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x04; + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->Y, buf + 1 + plen, plen ) ); + } + else if( format == MBEDTLS_ECP_PF_COMPRESSED ) + { + *olen = plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x02 + mbedtls_mpi_get_bit( &P->Y, 0 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + } + } +#endif + +cleanup: + return( ret ); +} + +/* + * Import a point from unsigned binary data (SEC1 2.3.4 and RFC7748) + */ +int mbedtls_ecp_point_read_binary( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char *buf, size_t ilen ) +{ + int ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + + if( ilen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + plen = mbedtls_mpi_size( &grp->P ); + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + if( plen != ilen ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary_le( &pt->X, buf, plen ) ); + mbedtls_mpi_free( &pt->Y ); + + if( grp->id == MBEDTLS_ECP_DP_CURVE25519 ) + /* Set most significant bit to 0 as prescribed in RFC7748 §5 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &pt->X, plen * 8 - 1, 0 ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + } +#endif +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + if( buf[0] == 0x00 ) + { + if( ilen == 1 ) + return( mbedtls_ecp_set_zero( pt ) ); + else + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + if( buf[0] != 0x04 ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + if( ilen != 2 * plen + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->Y, + buf + 1 + plen, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + } +#endif + +cleanup: + return( ret ); +} + +/* + * Import a point from a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_read_point( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char **buf, size_t buf_len ) +{ + unsigned char data_len; + const unsigned char *buf_start; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We must have at least two bytes (1 for length, at least one for data) + */ + if( buf_len < 2 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + data_len = *(*buf)++; + if( data_len < 1 || data_len > buf_len - 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Save buffer start for read_binary and update buf + */ + buf_start = *buf; + *buf += data_len; + + return( mbedtls_ecp_point_read_binary( grp, pt, buf_start, data_len ) ); +} + +/* + * Export a point as a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt, + int format, size_t *olen, + unsigned char *buf, size_t blen ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + /* + * buffer length must be at least one, for our length byte + */ + if( blen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( ( ret = mbedtls_ecp_point_write_binary( grp, pt, format, + olen, buf + 1, blen - 1) ) != 0 ) + return( ret ); + + /* + * write length to the first byte and update total length + */ + buf[0] = (unsigned char) *olen; + ++*olen; + + return( 0 ); +} + +/* + * Set a group from an ECParameters record (RFC 4492) + */ +int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, + const unsigned char **buf, size_t len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_group_id grp_id; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + if( ( ret = mbedtls_ecp_tls_read_group_id( &grp_id, buf, len ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_group_load( grp, grp_id ) ); +} + +/* + * Read a group id from an ECParameters record (RFC 4492) and convert it to + * mbedtls_ecp_group_id. + */ +int mbedtls_ecp_tls_read_group_id( mbedtls_ecp_group_id *grp, + const unsigned char **buf, size_t len ) +{ + uint16_t tls_id; + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We expect at least three bytes (see below) + */ + if( len < 3 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * First byte is curve_type; only named_curve is handled + */ + if( *(*buf)++ != MBEDTLS_ECP_TLS_NAMED_CURVE ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Next two bytes are the namedcurve value + */ + tls_id = *(*buf)++; + tls_id <<= 8; + tls_id |= *(*buf)++; + + if( ( curve_info = mbedtls_ecp_curve_info_from_tls_id( tls_id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + *grp = curve_info->grp_id; + + return( 0 ); +} + +/* + * Write the ECParameters record corresponding to a group (RFC 4492) + */ +int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, size_t *olen, + unsigned char *buf, size_t blen ) +{ + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + + if( ( curve_info = mbedtls_ecp_curve_info_from_grp_id( grp->id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * We are going to write 3 bytes (see below) + */ + *olen = 3; + if( blen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + /* + * First byte is curve_type, always named_curve + */ + *buf++ = MBEDTLS_ECP_TLS_NAMED_CURVE; + + /* + * Next two bytes are the namedcurve value + */ + buf[0] = curve_info->tls_id >> 8; + buf[1] = curve_info->tls_id & 0xFF; + + return( 0 ); +} + +/* + * Wrapper around fast quasi-modp functions, with fall-back to mbedtls_mpi_mod_mpi. + * See the documentation of struct mbedtls_ecp_group. + * + * This function is in the critial loop for mbedtls_ecp_mul, so pay attention to perf. + */ +static int ecp_modp( mbedtls_mpi *N, const mbedtls_ecp_group *grp ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if( grp->modp == NULL ) + return( mbedtls_mpi_mod_mpi( N, N, &grp->P ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + if( ( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) || + mbedtls_mpi_bitlen( N ) > 2 * grp->pbits ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + MBEDTLS_MPI_CHK( grp->modp( N ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + while( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &grp->P ) ); + + while( mbedtls_mpi_cmp_mpi( N, &grp->P ) >= 0 ) + /* we known P, N and the result are positive */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, N, &grp->P ) ); + +cleanup: + return( ret ); +} + +/* + * Fast mod-p functions expect their argument to be in the 0..p^2 range. + * + * In order to guarantee that, we need to ensure that operands of + * mbedtls_mpi_mul_mpi are in the 0..p range. So, after each operation we will + * bring the result back to this range. + * + * The following macros are shortcuts for doing that. + */ + +/* + * Reduce a mbedtls_mpi mod p in-place, general case, to use after mbedtls_mpi_mul_mpi + */ +#if defined(MBEDTLS_SELF_TEST) +#define INC_MUL_COUNT mul_count++; +#else +#define INC_MUL_COUNT +#endif + +#define MOD_MUL( N ) \ + do \ + { \ + MBEDTLS_MPI_CHK( ecp_modp( &(N), grp ) ); \ + INC_MUL_COUNT \ + } while( 0 ) + +static inline int mbedtls_mpi_mul_mod( const mbedtls_ecp_group *grp, + mbedtls_mpi *X, + const mbedtls_mpi *A, + const mbedtls_mpi *B ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( X, A, B ) ); + MOD_MUL( *X ); +cleanup: + return( ret ); +} + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_sub_mpi + * N->s < 0 is a very fast test, which fails only if N is 0 + */ +#define MOD_SUB( N ) \ + while( (N).s < 0 && mbedtls_mpi_cmp_int( &(N), 0 ) != 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &(N), &(N), &grp->P ) ) + +static inline int mbedtls_mpi_sub_mod( const mbedtls_ecp_group *grp, + mbedtls_mpi *X, + const mbedtls_mpi *A, + const mbedtls_mpi *B ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( X, A, B ) ); + MOD_SUB( *X ); +cleanup: + return( ret ); +} + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_add_mpi and mbedtls_mpi_mul_int. + * We known P, N and the result are positive, so sub_abs is correct, and + * a bit faster. + */ +#define MOD_ADD( N ) \ + while( mbedtls_mpi_cmp_mpi( &(N), &grp->P ) >= 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( &(N), &(N), &grp->P ) ) + +static inline int mbedtls_mpi_add_mod( const mbedtls_ecp_group *grp, + mbedtls_mpi *X, + const mbedtls_mpi *A, + const mbedtls_mpi *B ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( X, A, B ) ); + MOD_ADD( *X ); +cleanup: + return( ret ); +} + +static inline int mbedtls_mpi_shift_l_mod( const mbedtls_ecp_group *grp, + mbedtls_mpi *X, + size_t count ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( X, count ) ); + MOD_ADD( *X ); +cleanup: + return( ret ); +} + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) +/* + * For curves in short Weierstrass form, we do all the internal operations in + * Jacobian coordinates. + * + * For multiplication, we'll use a comb method with coutermeasueres against + * SPA, hence timing attacks. + */ + +/* + * Normalize jacobian coordinates so that Z == 0 || Z == 1 (GECC 3.2.1) + * Cost: 1N := 1I + 3M + 1S + */ +static int ecp_normalize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi Zi, ZZi; + + if( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ) + return( 0 ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac( grp, pt ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_JAC_ALT */ + + mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * X = X / Z^2 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &Zi, &pt->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &ZZi, &Zi, &Zi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &pt->X, &pt->X, &ZZi ) ); + + /* + * Y = Y / Z^3 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &pt->Y, &pt->Y, &ZZi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &pt->Y, &pt->Y, &Zi ) ); + + /* + * Z = 1 + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + +cleanup: + + mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + + return( ret ); +} + +/* + * Normalize jacobian coordinates of an array of (pointers to) points, + * using Montgomery's trick to perform only one inversion mod P. + * (See for example Cohen's "A Course in Computational Algebraic Number + * Theory", Algorithm 10.3.4.) + * + * Warning: fails (returning an error) if one of the points is zero! + * This should never happen, see choice of w in ecp_mul_comb(). + * + * Cost: 1N(t) := 1I + (6t - 3)M + 1S + */ +static int ecp_normalize_jac_many( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], size_t T_size ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i; + mbedtls_mpi *c, u, Zi, ZZi; + + if( T_size < 2 ) + return( ecp_normalize_jac( grp, *T ) ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac_many( grp, T, T_size ) ); +#endif + + if( ( c = mbedtls_calloc( T_size, sizeof( mbedtls_mpi ) ) ) == NULL ) + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); + + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_init( &c[i] ); + + mbedtls_mpi_init( &u ); mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * c[i] = Z_0 * ... * Z_i + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &c[0], &T[0]->Z ) ); + for( i = 1; i < T_size; i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &c[i], &c[i-1], &T[i]->Z ) ); + } + + /* + * u = 1 / (Z_0 * ... * Z_n) mod P + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &u, &c[T_size-1], &grp->P ) ); + + for( i = T_size - 1; ; i-- ) + { + /* + * Zi = 1 / Z_i mod p + * u = 1 / (Z_0 * ... * Z_i) mod P + */ + if( i == 0 ) { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Zi, &u ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &Zi, &u, &c[i-1] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &u, &u, &T[i]->Z ) ); + } + + /* + * proceed as in normalize() + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &ZZi, &Zi, &Zi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T[i]->X, &T[i]->X, &ZZi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T[i]->Y, &T[i]->Y, &ZZi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T[i]->Y, &T[i]->Y, &Zi ) ); + + /* + * Post-precessing: reclaim some memory by shrinking coordinates + * - not storing Z (always 1) + * - shrinking other coordinates, but still keeping the same number of + * limbs as P, as otherwise it will too likely be regrown too fast. + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->X, grp->P.n ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->Y, grp->P.n ) ); + mbedtls_mpi_free( &T[i]->Z ); + + if( i == 0 ) + break; + } + +cleanup: + + mbedtls_mpi_free( &u ); mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_free( &c[i] ); + mbedtls_free( c ); + + return( ret ); +} + +/* + * Conditional point inversion: Q -> -Q = (Q.X, -Q.Y, Q.Z) without leak. + * "inv" must be 0 (don't invert) or 1 (invert) or the result will be invalid + */ +static int ecp_safe_invert_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *Q, + unsigned char inv ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char nonzero; + mbedtls_mpi mQY; + + mbedtls_mpi_init( &mQY ); + + /* Use the fact that -Q.Y mod P = P - Q.Y unless Q.Y == 0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mQY, &grp->P, &Q->Y ) ); + nonzero = mbedtls_mpi_cmp_int( &Q->Y, 0 ) != 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &Q->Y, &mQY, inv & nonzero ) ); + +cleanup: + mbedtls_mpi_free( &mQY ); + + return( ret ); +} + +/* + * Point doubling R = 2 P, Jacobian coordinates + * + * Based on http://www.hyperelliptic.org/EFD/g1p/auto-shortw-jacobian.html#doubling-dbl-1998-cmo-2 . + * + * We follow the variable naming fairly closely. The formula variations that trade a MUL for a SQR + * (plus a few ADDs) aren't useful as our bignum implementation doesn't distinguish squaring. + * + * Standard optimizations are applied when curve parameter A is one of { 0, -3 }. + * + * Cost: 1D := 3M + 4S (A == 0) + * 4M + 4S (A == -3) + * 3M + 6S + 1a otherwise + */ +static int ecp_double_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi M, S, T, U; + +#if defined(MBEDTLS_SELF_TEST) + dbl_count++; +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_jac( grp, R, P ) ); +#endif /* MBEDTLS_ECP_DOUBLE_JAC_ALT */ + + mbedtls_mpi_init( &M ); mbedtls_mpi_init( &S ); mbedtls_mpi_init( &T ); mbedtls_mpi_init( &U ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + /* M = 3(X + Z^2)(X - Z^2) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S, &P->Z, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &T, &P->X, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &U, &P->X, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S, &T, &U ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + } + else + { + /* M = 3.X^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S, &P->X, &P->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + + /* Optimize away for "koblitz" curves with A = 0 */ + if( mbedtls_mpi_cmp_int( &grp->A, 0 ) != 0 ) + { + /* M += A.Z^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S, &P->Z, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T, &S, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S, &T, &grp->A ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &M, &M, &S ) ); + } + } + + /* S = 4.X.Y^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T, &P->Y, &P->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l_mod( grp, &T, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S, &P->X, &T ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l_mod( grp, &S, 1 ) ); + + /* U = 8.Y^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &U, &T, &T ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l_mod( grp, &U, 1 ) ); + + /* T = M^2 - 2.S */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T, &M, &M ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &T, &T, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &T, &T, &S ) ); + + /* S = M(S - T) - U */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &S, &S, &T ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S, &S, &M ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &S, &S, &U ) ); + + /* U = 2.Y.Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &U, &P->Y, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l_mod( grp, &U, 1 ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &T ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &U ) ); + +cleanup: + mbedtls_mpi_free( &M ); mbedtls_mpi_free( &S ); mbedtls_mpi_free( &T ); mbedtls_mpi_free( &U ); + + return( ret ); +} + +/* + * Addition: R = P + Q, mixed affine-Jacobian coordinates (GECC 3.22) + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * Special cases: (1) P or Q is zero, (2) R is zero, (3) P == Q. + * None of these cases can happen as intermediate step in ecp_mul_comb(): + * - at each step, P, Q and R are multiples of the base point, the factor + * being less than its order, so none of them is zero; + * - Q is an odd multiple of the base point, P an even multiple, + * due to the choice of precomputed points in the modified comb method. + * So branches for these cases do not leak secret information. + * + * We accept Q->Z being unset (saving memory in tables) as meaning 1. + * + * Cost: 1A := 8M + 3S + */ +static int ecp_add_mixed( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi T1, T2, T3, T4, X, Y, Z; + +#if defined(MBEDTLS_SELF_TEST) + add_count++; +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_add_mixed( grp, R, P, Q ) ); +#endif /* MBEDTLS_ECP_ADD_MIXED_ALT */ + + /* + * Trivial cases: P == 0 or Q == 0 (case 1) + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, Q ) ); + + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, P ) ); + + /* + * Make sure Q coordinates are normalized + */ + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &T1 ); mbedtls_mpi_init( &T2 ); mbedtls_mpi_init( &T3 ); mbedtls_mpi_init( &T4 ); + mbedtls_mpi_init( &X ); mbedtls_mpi_init( &Y ); mbedtls_mpi_init( &Z ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T1, &P->Z, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T2, &T1, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T1, &T1, &Q->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T2, &T2, &Q->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &T1, &T1, &P->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &T2, &T2, &P->Y ) ); + + /* Special cases (2) and (3) */ + if( mbedtls_mpi_cmp_int( &T1, 0 ) == 0 ) + { + if( mbedtls_mpi_cmp_int( &T2, 0 ) == 0 ) + { + ret = ecp_double_jac( grp, R, P ); + goto cleanup; + } + else + { + ret = mbedtls_ecp_set_zero( R ); + goto cleanup; + } + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &Z, &P->Z, &T1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T3, &T1, &T1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T4, &T3, &T1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T3, &T3, &P->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &T1, &T3 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l_mod( grp, &T1, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &X, &T2, &T2 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &X, &X, &T1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &X, &X, &T4 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &T3, &T3, &X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T3, &T3, &T2 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &T4, &T4, &P->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &Y, &T3, &T4 ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &Z ) ); + +cleanup: + + mbedtls_mpi_free( &T1 ); mbedtls_mpi_free( &T2 ); mbedtls_mpi_free( &T3 ); mbedtls_mpi_free( &T4 ); + mbedtls_mpi_free( &X ); mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &Z ); + + return( ret ); +} + +/* + * Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_jac(). + * + * This countermeasure was first suggested in [2]. + */ +static int ecp_randomize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi l, ll; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_jac( grp, pt, f_rng, p_rng ) ); +#endif /* MBEDTLS_ECP_RANDOMIZE_JAC_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); mbedtls_mpi_init( &ll ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + /* Z = l * Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &pt->Z, &pt->Z, &l ) ); + + /* X = l^2 * X */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &ll, &l, &l ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &pt->X, &pt->X, &ll ) ); + + /* Y = l^3 * Y */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &ll, &ll, &l ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &pt->Y, &pt->Y, &ll ) ); + +cleanup: + mbedtls_mpi_free( &l ); mbedtls_mpi_free( &ll ); + + return( ret ); +} + +/* + * Check and define parameters used by the comb method (see below for details) + */ +#if MBEDTLS_ECP_WINDOW_SIZE < 2 || MBEDTLS_ECP_WINDOW_SIZE > 7 +#error "MBEDTLS_ECP_WINDOW_SIZE out of bounds" +#endif + +/* d = ceil( n / w ) */ +#define COMB_MAX_D ( MBEDTLS_ECP_MAX_BITS + 1 ) / 2 + +/* number of precomputed points */ +#define COMB_MAX_PRE ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + +/* + * Compute the representation of m that will be used with our comb method. + * + * The basic comb method is described in GECC 3.44 for example. We use a + * modified version that provides resistance to SPA by avoiding zero + * digits in the representation as in [3]. We modify the method further by + * requiring that all K_i be odd, which has the small cost that our + * representation uses one more K_i, due to carries, but saves on the size of + * the precomputed table. + * + * Summary of the comb method and its modifications: + * + * - The goal is to compute m*P for some w*d-bit integer m. + * + * - The basic comb method splits m into the w-bit integers + * x[0] .. x[d-1] where x[i] consists of the bits in m whose + * index has residue i modulo d, and computes m * P as + * S[x[0]] + 2 * S[x[1]] + .. + 2^(d-1) S[x[d-1]], where + * S[i_{w-1} .. i_0] := i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + i_0 P. + * + * - If it happens that, say, x[i+1]=0 (=> S[x[i+1]]=0), one can replace the sum by + * .. + 2^{i-1} S[x[i-1]] - 2^i S[x[i]] + 2^{i+1} S[x[i]] + 2^{i+2} S[x[i+2]] .., + * thereby successively converting it into a form where all summands + * are nonzero, at the cost of negative summands. This is the basic idea of [3]. + * + * - More generally, even if x[i+1] != 0, we can first transform the sum as + * .. - 2^i S[x[i]] + 2^{i+1} ( S[x[i]] + S[x[i+1]] ) + 2^{i+2} S[x[i+2]] .., + * and then replace S[x[i]] + S[x[i+1]] = S[x[i] ^ x[i+1]] + 2 S[x[i] & x[i+1]]. + * Performing and iterating this procedure for those x[i] that are even + * (keeping track of carry), we can transform the original sum into one of the form + * S[x'[0]] +- 2 S[x'[1]] +- .. +- 2^{d-1} S[x'[d-1]] + 2^d S[x'[d]] + * with all x'[i] odd. It is therefore only necessary to know S at odd indices, + * which is why we are only computing half of it in the first place in + * ecp_precompute_comb and accessing it with index abs(i) / 2 in ecp_select_comb. + * + * - For the sake of compactness, only the seven low-order bits of x[i] + * are used to represent its absolute value (K_i in the paper), and the msb + * of x[i] encodes the sign (s_i in the paper): it is set if and only if + * if s_i == -1; + * + * Calling conventions: + * - x is an array of size d + 1 + * - w is the size, ie number of teeth, of the comb, and must be between + * 2 and 7 (in practice, between 2 and MBEDTLS_ECP_WINDOW_SIZE) + * - m is the MPI, expected to be odd and such that bitlength(m) <= w * d + * (the result will be incorrect if these assumptions are not satisfied) + */ +static void ecp_comb_recode_core( unsigned char x[], size_t d, + unsigned char w, const mbedtls_mpi *m ) +{ + size_t i, j; + unsigned char c, cc, adjust; + + memset( x, 0, d+1 ); + + /* First get the classical comb values (except for x_d = 0) */ + for( i = 0; i < d; i++ ) + for( j = 0; j < w; j++ ) + x[i] |= mbedtls_mpi_get_bit( m, i + d * j ) << j; + + /* Now make sure x_1 .. x_d are odd */ + c = 0; + for( i = 1; i <= d; i++ ) + { + /* Add carry and update it */ + cc = x[i] & c; + x[i] = x[i] ^ c; + c = cc; + + /* Adjust if needed, avoiding branches */ + adjust = 1 - ( x[i] & 0x01 ); + c |= x[i] & ( x[i-1] * adjust ); + x[i] = x[i] ^ ( x[i-1] * adjust ); + x[i-1] |= adjust << 7; + } +} + +/* + * Precompute points for the adapted comb method + * + * Assumption: T must be able to hold 2^{w - 1} elements. + * + * Operation: If i = i_{w-1} ... i_1 is the binary representation of i, + * sets T[i] = i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + P. + * + * Cost: d(w-1) D + (2^{w-1} - 1) A + 1 N(w-1) + 1 N(2^{w-1} - 1) + * + * Note: Even comb values (those where P would be omitted from the + * sum defining T[i] above) are not needed in our adaption + * the comb method. See ecp_comb_recode_core(). + * + * This function currently works in four steps: + * (1) [dbl] Computation of intermediate T[i] for 2-power values of i + * (2) [norm_dbl] Normalization of coordinates of these T[i] + * (3) [add] Computation of all T[i] + * (4) [norm_add] Normalization of all T[i] + * + * Step 1 can be interrupted but not the others; together with the final + * coordinate normalization they are the largest steps done at once, depending + * on the window size. Here are operation counts for P-256: + * + * step (2) (3) (4) + * w = 5 142 165 208 + * w = 4 136 77 160 + * w = 3 130 33 136 + * w = 2 124 11 124 + * + * So if ECC operations are blocking for too long even with a low max_ops + * value, it's useful to set MBEDTLS_ECP_WINDOW_SIZE to a lower value in order + * to minimize maximum blocking time. + */ +static int ecp_precompute_comb( const mbedtls_ecp_group *grp, + mbedtls_ecp_point T[], const mbedtls_ecp_point *P, + unsigned char w, size_t d, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char i; + size_t j = 0; + const unsigned char T_size = 1U << ( w - 1 ); + mbedtls_ecp_point *cur, *TT[COMB_MAX_PRE - 1]; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + goto dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_dbl ) + goto norm_dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_add ) + goto add; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_add ) + goto norm_add; + } +#else + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + rs_ctx->rsm->state = ecp_rsm_pre_dbl; + + /* initial state for the loop */ + rs_ctx->rsm->i = 0; + } + +dbl: +#endif + /* + * Set T[0] = P and + * T[2^{l-1}] = 2^{dl} P for l = 1 .. w-1 (this is not the final value) + */ + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &T[0], P ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + j = rs_ctx->rsm->i; + else +#endif + j = 0; + + for( ; j < d * ( w - 1 ); j++ ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL ); + + i = 1U << ( j / d ); + cur = T + i; + + if( j % d == 0 ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( cur, T + ( i >> 1 ) ) ); + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, cur, cur ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_dbl; + +norm_dbl: +#endif + /* + * Normalize current elements in T. As T has holes, + * use an auxiliary array of pointers to elements in T. + */ + j = 0; + for( i = 1; i < T_size; i <<= 1 ) + TT[j++] = T + i; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_add; + +add: +#endif + /* + * Compute the remaining ones using the minimal number of additions + * Be careful to update T[2^l] only after using it! + */ + MBEDTLS_ECP_BUDGET( ( T_size - 1 ) * MBEDTLS_ECP_OPS_ADD ); + + for( i = 1; i < T_size; i <<= 1 ) + { + j = i; + while( j-- ) + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, &T[i + j], &T[j], &T[i] ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_add; + +norm_add: +#endif + /* + * Normalize final elements in T. Even though there are no holes now, we + * still need the auxiliary array for homogeneity with the previous + * call. Also, skip T[0] which is already normalised, being a copy of P. + */ + for( j = 0; j + 1 < T_size; j++ ) + TT[j] = T + j + 1; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +cleanup: +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + rs_ctx->rsm->i = j; + } +#endif + + return( ret ); +} + +/* + * Select precomputed point: R = sign(i) * T[ abs(i) / 2 ] + * + * See ecp_comb_recode_core() for background + */ +static int ecp_select_comb( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + unsigned char i ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char ii, j; + + /* Ignore the "sign" bit and scale down */ + ii = ( i & 0x7Fu ) >> 1; + + /* Read the whole table to thwart cache-based timing attacks */ + for( j = 0; j < T_size; j++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->X, &T[j].X, j == ii ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->Y, &T[j].Y, j == ii ) ); + } + + /* Safely invert result if i is "negative" */ + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, R, i >> 7 ) ); + +cleanup: + return( ret ); +} + +/* + * Core multiplication algorithm for the (modified) comb method. + * This part is actually common with the basic comb method (GECC 3.44) + * + * Cost: d A + d D + 1 R + */ +static int ecp_mul_comb_core( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + const unsigned char x[], size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_point Txi; + size_t i; + + mbedtls_ecp_point_init( &Txi ); + +#if !defined(MBEDTLS_ECP_RESTARTABLE) + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + rs_ctx->rsm->state != ecp_rsm_comb_core ) + { + rs_ctx->rsm->i = 0; + rs_ctx->rsm->state = ecp_rsm_comb_core; + } + + /* new 'if' instead of nested for the sake of the 'else' branch */ + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + { + /* restore current index (R already pointing to rs_ctx->rsm->R) */ + i = rs_ctx->rsm->i; + } + else +#endif + { + /* Start with a non-zero point and randomize its coordinates */ + i = d; + MBEDTLS_MPI_CHK( ecp_select_comb( grp, R, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 1 ) ); +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != 0 ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_jac( grp, R, f_rng, p_rng ) ); + } + + while( i != 0 ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL + MBEDTLS_ECP_OPS_ADD ); + --i; + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, R, R ) ); + MBEDTLS_MPI_CHK( ecp_select_comb( grp, &Txi, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, R, R, &Txi ) ); + } + +cleanup: + + mbedtls_ecp_point_free( &Txi ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + rs_ctx->rsm->i = i; + /* no need to save R, already pointing to rs_ctx->rsm->R */ + } +#endif + + return( ret ); +} + +/* + * Recode the scalar to get constant-time comb multiplication + * + * As the actual scalar recoding needs an odd scalar as a starting point, + * this wrapper ensures that by replacing m by N - m if necessary, and + * informs the caller that the result of multiplication will be negated. + * + * This works because we only support large prime order for Short Weierstrass + * curves, so N is always odd hence either m or N - m is. + * + * See ecp_comb_recode_core() for background. + */ +static int ecp_comb_recode_scalar( const mbedtls_ecp_group *grp, + const mbedtls_mpi *m, + unsigned char k[COMB_MAX_D + 1], + size_t d, + unsigned char w, + unsigned char *parity_trick ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi M, mm; + + mbedtls_mpi_init( &M ); + mbedtls_mpi_init( &mm ); + + /* N is always odd (see above), just make extra sure */ + if( mbedtls_mpi_get_bit( &grp->N, 0 ) != 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* do we need the parity trick? */ + *parity_trick = ( mbedtls_mpi_get_bit( m, 0 ) == 0 ); + + /* execute parity fix in constant time */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &M, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mm, &grp->N, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &M, &mm, *parity_trick ) ); + + /* actual scalar recoding */ + ecp_comb_recode_core( k, d, w, &M ); + +cleanup: + mbedtls_mpi_free( &mm ); + mbedtls_mpi_free( &M ); + + return( ret ); +} + +/* + * Perform comb multiplication (for short Weierstrass curves) + * once the auxiliary table has been pre-computed. + * + * Scalar recoding may use a parity trick that makes us compute -m * P, + * if that is the case we'll need to recover m * P at the end. + */ +static int ecp_mul_comb_after_precomp( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *T, + unsigned char T_size, + unsigned char w, + size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char parity_trick; + unsigned char k[COMB_MAX_D + 1]; + mbedtls_ecp_point *RR = R; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + RR = &rs_ctx->rsm->R; + + if( rs_ctx->rsm->state == ecp_rsm_final_norm ) + goto final_norm; + } +#endif + + MBEDTLS_MPI_CHK( ecp_comb_recode_scalar( grp, m, k, d, w, + &parity_trick ) ); + MBEDTLS_MPI_CHK( ecp_mul_comb_core( grp, RR, T, T_size, k, d, + f_rng, p_rng, rs_ctx ) ); + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, RR, parity_trick ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_final_norm; + +final_norm: + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); +#endif + /* + * Knowledge of the jacobian coordinates may leak the last few bits of the + * scalar [1], and since our MPI implementation isn't constant-flow, + * inversion (used for coordinate normalization) may leak the full value + * of its input via side-channels [2]. + * + * [1] https://eprint.iacr.org/2003/191 + * [2] https://eprint.iacr.org/2020/055 + * + * Avoid the leak by randomizing coordinates before we normalize them. + */ +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != 0 ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_jac( grp, RR, f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, RR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, RR ) ); +#endif + +cleanup: + return( ret ); +} + +/* + * Pick window size based on curve size and whether we optimize for base point + */ +static unsigned char ecp_pick_window_size( const mbedtls_ecp_group *grp, + unsigned char p_eq_g ) +{ + unsigned char w; + + /* + * Minimize the number of multiplications, that is minimize + * 10 * d * w + 18 * 2^(w-1) + 11 * d + 7 * w, with d = ceil( nbits / w ) + * (see costs of the various parts, with 1S = 1M) + */ + w = grp->nbits >= 384 ? 5 : 4; + + /* + * If P == G, pre-compute a bit more, since this may be re-used later. + * Just adding one avoids upping the cost of the first mul too much, + * and the memory cost too. + */ + if( p_eq_g ) + w++; + + /* + * Make sure w is within bounds. + * (The last test is useful only for very small curves in the test suite.) + */ +#if( MBEDTLS_ECP_WINDOW_SIZE < 6 ) + if( w > MBEDTLS_ECP_WINDOW_SIZE ) + w = MBEDTLS_ECP_WINDOW_SIZE; +#endif + if( w >= grp->nbits ) + w = 2; + + return( w ); +} + +/* + * Multiplication using the comb method - for curves in short Weierstrass form + * + * This function is mainly responsible for administrative work: + * - managing the restart context if enabled + * - managing the table of precomputed points (passed between the below two + * functions): allocation, computation, ownership tranfer, freeing. + * + * It delegates the actual arithmetic work to: + * ecp_precompute_comb() and ecp_mul_comb_with_precomp() + * + * See comments on ecp_comb_recode_core() regarding the computation strategy. + */ +static int ecp_mul_comb( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char w, p_eq_g, i; + size_t d; + unsigned char T_size = 0, T_ok = 0; + mbedtls_ecp_point *T = NULL; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_context drbg_ctx; + + ecp_drbg_init( &drbg_ctx ); +#endif + + ECP_RS_ENTER( rsm ); + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng == NULL ) + { + /* Adjust pointers */ + f_rng = &ecp_drbg_random; +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + p_rng = &rs_ctx->rsm->drbg_ctx; + else +#endif + p_rng = &drbg_ctx; + + /* Initialize internal DRBG if necessary */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx == NULL || rs_ctx->rsm == NULL || + rs_ctx->rsm->drbg_seeded == 0 ) +#endif + { + const size_t m_len = ( grp->nbits + 7 ) / 8; + MBEDTLS_MPI_CHK( ecp_drbg_seed( p_rng, m, m_len ) ); + } +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->drbg_seeded = 1; +#endif + } +#endif /* !MBEDTLS_ECP_NO_INTERNAL_RNG */ + + /* Is P the base point ? */ +#if MBEDTLS_ECP_FIXED_POINT_OPTIM == 1 + p_eq_g = ( mbedtls_mpi_cmp_mpi( &P->Y, &grp->G.Y ) == 0 && + mbedtls_mpi_cmp_mpi( &P->X, &grp->G.X ) == 0 ); +#else + p_eq_g = 0; +#endif + + /* Pick window size and deduce related sizes */ + w = ecp_pick_window_size( grp, p_eq_g ); + T_size = 1U << ( w - 1 ); + d = ( grp->nbits + w - 1 ) / w; + + /* Pre-computed table: do we have it already for the base point? */ + if( p_eq_g && grp->T != NULL ) + { + /* second pointer to the same table, will be deleted on exit */ + T = grp->T; + T_ok = 1; + } + else +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* Pre-computed table: do we have one in progress? complete? */ + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->T != NULL ) + { + /* transfer ownership of T from rsm to local function */ + T = rs_ctx->rsm->T; + rs_ctx->rsm->T = NULL; + rs_ctx->rsm->T_size = 0; + + /* This effectively jumps to the call to mul_comb_after_precomp() */ + T_ok = rs_ctx->rsm->state >= ecp_rsm_comb_core; + } + else +#endif + /* Allocate table if we didn't have any */ + { + T = mbedtls_calloc( T_size, sizeof( mbedtls_ecp_point ) ); + if( T == NULL ) + { + ret = MBEDTLS_ERR_ECP_ALLOC_FAILED; + goto cleanup; + } + + for( i = 0; i < T_size; i++ ) + mbedtls_ecp_point_init( &T[i] ); + + T_ok = 0; + } + + /* Compute table (or finish computing it) if not done already */ + if( !T_ok ) + { + MBEDTLS_MPI_CHK( ecp_precompute_comb( grp, T, P, w, d, rs_ctx ) ); + + if( p_eq_g ) + { + /* almost transfer ownership of T to the group, but keep a copy of + * the pointer to use for calling the next function more easily */ + grp->T = T; + grp->T_size = T_size; + } + } + + /* Actual comb multiplication using precomputed points */ + MBEDTLS_MPI_CHK( ecp_mul_comb_after_precomp( grp, R, m, + T, T_size, w, d, + f_rng, p_rng, rs_ctx ) ); + +cleanup: + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_free( &drbg_ctx ); +#endif + + /* does T belong to the group? */ + if( T == grp->T ) + T = NULL; + + /* does T belong to the restart context? */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && ret == MBEDTLS_ERR_ECP_IN_PROGRESS && T != NULL ) + { + /* transfer ownership of T from local function to rsm */ + rs_ctx->rsm->T_size = T_size; + rs_ctx->rsm->T = T; + T = NULL; + } +#endif + + /* did T belong to us? then let's destroy it! */ + if( T != NULL ) + { + for( i = 0; i < T_size; i++ ) + mbedtls_ecp_point_free( &T[i] ); + mbedtls_free( T ); + } + + /* don't free R while in progress in case R == P */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( ret != MBEDTLS_ERR_ECP_IN_PROGRESS ) +#endif + /* prevent caller from using invalid value */ + if( ret != 0 ) + mbedtls_ecp_point_free( R ); + + ECP_RS_LEAVE( rsm ); + + return( ret ); +} + +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) +/* + * For Montgomery curves, we do all the internal arithmetic in projective + * coordinates. Import/export of points uses only the x coordinates, which is + * internaly represented as X / Z. + * + * For scalar multiplication, we'll use a Montgomery ladder. + */ + +/* + * Normalize Montgomery x/z coordinates: X = X/Z, Z = 1 + * Cost: 1M + 1I + */ +static int ecp_normalize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_mxz( grp, P ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_MXZ_ALT */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &P->Z, &P->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &P->X, &P->X, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Randomize projective x/z coordinates: + * (X, Z) -> (l X, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_mxz(). + * + * This countermeasure was first suggested in [2]. + * Cost: 2M + */ +static int ecp_randomize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi l; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_mxz( grp, P, f_rng, p_rng ) ); +#endif /* MBEDTLS_ECP_RANDOMIZE_MXZ_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &P->X, &P->X, &l ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &P->Z, &P->Z, &l ) ); + +cleanup: + mbedtls_mpi_free( &l ); + + return( ret ); +} + +/* + * Double-and-add: R = 2P, S = P + Q, with d = X(P - Q), + * for Montgomery curves in x/z coordinates. + * + * http://www.hyperelliptic.org/EFD/g1p/auto-code/montgom/xz/ladder/mladd-1987-m.op3 + * with + * d = X1 + * P = (X2, Z2) + * Q = (X3, Z3) + * R = (X4, Z4) + * S = (X5, Z5) + * and eliminating temporary variables tO, ..., t4. + * + * Cost: 5M + 4S + */ +static int ecp_double_add_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, mbedtls_ecp_point *S, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q, + const mbedtls_mpi *d ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi A, AA, B, BB, E, C, D, DA, CB; + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_add_mxz( grp, R, S, P, Q, d ) ); +#endif /* MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT */ + + mbedtls_mpi_init( &A ); mbedtls_mpi_init( &AA ); mbedtls_mpi_init( &B ); + mbedtls_mpi_init( &BB ); mbedtls_mpi_init( &E ); mbedtls_mpi_init( &C ); + mbedtls_mpi_init( &D ); mbedtls_mpi_init( &DA ); mbedtls_mpi_init( &CB ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &A, &P->X, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &AA, &A, &A ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &B, &P->X, &P->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &BB, &B, &B ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &E, &AA, &BB ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &C, &Q->X, &Q->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &D, &Q->X, &Q->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &DA, &D, &A ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &CB, &C, &B ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &S->X, &DA, &CB ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S->X, &S->X, &S->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mod( grp, &S->Z, &DA, &CB ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S->Z, &S->Z, &S->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &S->Z, d, &S->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &R->X, &AA, &BB ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &R->Z, &grp->A, &E ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &R->Z, &BB, &R->Z ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &R->Z, &E, &R->Z ) ); + +cleanup: + mbedtls_mpi_free( &A ); mbedtls_mpi_free( &AA ); mbedtls_mpi_free( &B ); + mbedtls_mpi_free( &BB ); mbedtls_mpi_free( &E ); mbedtls_mpi_free( &C ); + mbedtls_mpi_free( &D ); mbedtls_mpi_free( &DA ); mbedtls_mpi_free( &CB ); + + return( ret ); +} + +/* + * Multiplication with Montgomery ladder in x/z coordinates, + * for curves in Montgomery form + */ +static int ecp_mul_mxz( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i; + unsigned char b; + mbedtls_ecp_point RP; + mbedtls_mpi PX; +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_context drbg_ctx; + + ecp_drbg_init( &drbg_ctx ); +#endif + mbedtls_ecp_point_init( &RP ); mbedtls_mpi_init( &PX ); + +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng == NULL ) + { + const size_t m_len = ( grp->nbits + 7 ) / 8; + MBEDTLS_MPI_CHK( ecp_drbg_seed( &drbg_ctx, m, m_len ) ); + f_rng = &ecp_drbg_random; + p_rng = &drbg_ctx; + } +#endif /* !MBEDTLS_ECP_NO_INTERNAL_RNG */ + + /* Save PX and read from P before writing to R, in case P == R */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &PX, &P->X ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &RP, P ) ); + + /* Set R to zero in modified x/z coordinates */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->X, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 0 ) ); + mbedtls_mpi_free( &R->Y ); + + /* RP.X might be sligtly larger than P, so reduce it */ + MOD_ADD( RP.X ); + + /* Randomize coordinates of the starting point */ +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != NULL ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_mxz( grp, &RP, f_rng, p_rng ) ); + + /* Loop invariant: R = result so far, RP = R + P */ + i = mbedtls_mpi_bitlen( m ); /* one past the (zero-based) most significant bit */ + while( i-- > 0 ) + { + b = mbedtls_mpi_get_bit( m, i ); + /* + * if (b) R = 2R + P else R = 2R, + * which is: + * if (b) double_add( RP, R, RP, R ) + * else double_add( R, RP, R, RP ) + * but using safe conditional swaps to avoid leaks + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + MBEDTLS_MPI_CHK( ecp_double_add_mxz( grp, R, &RP, R, &RP, &PX ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + } + + /* + * Knowledge of the projective coordinates may leak the last few bits of the + * scalar [1], and since our MPI implementation isn't constant-flow, + * inversion (used for coordinate normalization) may leak the full value + * of its input via side-channels [2]. + * + * [1] https://eprint.iacr.org/2003/191 + * [2] https://eprint.iacr.org/2020/055 + * + * Avoid the leak by randomizing coordinates before we normalize them. + */ +#if defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + if( f_rng != NULL ) +#endif + MBEDTLS_MPI_CHK( ecp_randomize_mxz( grp, R, f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( ecp_normalize_mxz( grp, R ) ); + +cleanup: +#if !defined(MBEDTLS_ECP_NO_INTERNAL_RNG) + ecp_drbg_free( &drbg_ctx ); +#endif + + mbedtls_ecp_point_free( &RP ); mbedtls_mpi_free( &PX ); + + return( ret ); +} + +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + +/* + * Restartable multiplication R = m * P + */ +int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(NU_CRYPTO_ECC_ENABLE) + bool hw_go = false; + bool hw_capable = false; + bool sw_fallback = false; +#endif +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + +#if defined(NU_CRYPTO_ECC_ENABLE) + hw_capable = crypto_ecc_capable(grp); + if (!grp->hw_init) { + grp->hw_init = (crypto_ecc_init(grp) == 0) ? 1 : 0; + } + hw_go = hw_capable && grp->hw_init; + if (hw_go) { + ret = crypto_ecc_run_eccop_mul(grp, R, m, P, f_rng != NULL); + if (ret == 0) { + goto cleanup; + } + + /* Fall back to S/W on H/W failure */ + sw_fallback = true; + } +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* reset ops count for this call if top-level */ + if( rs_ctx != NULL && rs_ctx->depth++ == 0 ) + rs_ctx->ops_done = 0; +#else + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* skip argument check when restarting */ + if( rs_ctx == NULL || rs_ctx->rsm == NULL ) +#endif + { + /* check_privkey is free */ + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_CHK ); + + /* Common sanity checks */ + MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( grp, m ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_check_pubkey( grp, P ) ); + } + + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + MBEDTLS_MPI_CHK( ecp_mul_mxz( grp, R, m, P, f_rng, p_rng ) ); +#endif +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + MBEDTLS_MPI_CHK( ecp_mul_comb( grp, R, m, P, f_rng, p_rng, rs_ctx ) ); +#endif + +cleanup: + +#if defined(NU_CRYPTO_ECC_ENABLE) + if (hw_go) { + /* Premature return on H/W success, or continue to do other S/W clean-up + * because it is involved as fallback. */ + if (!sw_fallback) { + return ret; + } + } +#endif + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL ) + rs_ctx->depth--; +#endif + + return( ret ); +} + +/* + * Multiplication R = m * P + */ +int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + return( mbedtls_ecp_mul_restartable( grp, R, m, P, f_rng, p_rng, NULL ) ); +} + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) +/* + * Check that an affine point is valid as a public key, + * short weierstrass curves (SEC1 3.2.3.1) + */ +static int ecp_check_pubkey_sw( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi YY, RHS; + + /* pt coordinates must be normalized for our checks */ + if( mbedtls_mpi_cmp_int( &pt->X, 0 ) < 0 || + mbedtls_mpi_cmp_int( &pt->Y, 0 ) < 0 || + mbedtls_mpi_cmp_mpi( &pt->X, &grp->P ) >= 0 || + mbedtls_mpi_cmp_mpi( &pt->Y, &grp->P ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + mbedtls_mpi_init( &YY ); mbedtls_mpi_init( &RHS ); + + /* + * YY = Y^2 + * RHS = X (X^2 + A) + B = X^3 + A X + B + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &YY, &pt->Y, &pt->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &RHS, &pt->X, &pt->X ) ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &RHS, &RHS, 3 ) ); MOD_SUB( RHS ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &RHS, &RHS, &grp->A ) ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mod( grp, &RHS, &RHS, &pt->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mod( grp, &RHS, &RHS, &grp->B ) ); + + if( mbedtls_mpi_cmp_mpi( &YY, &RHS ) != 0 ) + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + +cleanup: + + mbedtls_mpi_free( &YY ); mbedtls_mpi_free( &RHS ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) +/* + * R = m * P with shortcuts for m == 1 and m == -1 + * NOT constant-time - ONLY for short Weierstrass! + */ +static int mbedtls_ecp_mul_shortcuts( mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if( mbedtls_mpi_cmp_int( m, 1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + } + else if( mbedtls_mpi_cmp_int( m, -1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + if( mbedtls_mpi_cmp_int( &R->Y, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &R->Y, &grp->P, &R->Y ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, R, m, P, + NULL, NULL, rs_ctx ) ); + } + +cleanup: + return( ret ); +} + +/* + * Restartable linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd_restartable( + mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; +#if defined(NU_CRYPTO_ECC_ENABLE) + bool hw_go = false; + bool hw_capable = false; + bool sw_fallback = false; + mbedtls_ecp_point R1, R2; +#endif + mbedtls_ecp_point mP; + mbedtls_ecp_point *pmP = &mP; + mbedtls_ecp_point *pR = R; +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( mbedtls_ecp_get_type( grp ) != MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + +#if defined(NU_CRYPTO_ECC_ENABLE) + hw_capable = crypto_ecc_capable(grp); + if (!grp->hw_init) { + grp->hw_init = (crypto_ecc_init(grp) == 0) ? 1 : 0; + } + hw_go = hw_capable && grp->hw_init; + if (hw_go) { + mbedtls_ecp_point_init(&R1); + mbedtls_ecp_point_init(&R2); + do { + /* R1 = m*P */ + ret = crypto_ecc_run_eccop_mul(grp, &R1, m, P, false); + if (ret != 0) { + break; + } + + /* R2 = n*Q */ + ret = crypto_ecc_run_eccop_mul(grp, &R2, n, Q, false); + if (ret != 0) { + break; + } + + /* R = m*P + n*Q = R1 + R2 */ + ret = crypto_ecc_run_eccop_add(grp, R, &R1, &R2, false); + if (ret != 0) { + break; + } + + goto cleanup; + } while (0); + + /* Fall back to S/W on H/W failure */ + sw_fallback = true; + } +#endif + + mbedtls_ecp_point_init( &mP ); + + ECP_RS_ENTER( ma ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + { + /* redirect intermediate results to restart context */ + pmP = &rs_ctx->ma->mP; + pR = &rs_ctx->ma->R; + + /* jump to next operation */ + if( rs_ctx->ma->state == ecp_rsma_mul2 ) + goto mul2; + if( rs_ctx->ma->state == ecp_rsma_add ) + goto add; + if( rs_ctx->ma->state == ecp_rsma_norm ) + goto norm; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pmP, m, P, rs_ctx ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_mul2; + +mul2: +#endif + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pR, n, Q, rs_ctx ) ); + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_add; + +add: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_ADD ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, pR, pmP, pR ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_norm; + +norm: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, pR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, pR ) ); +#endif + +cleanup: +#if defined(NU_CRYPTO_ECC_ENABLE) + if (hw_go) { + mbedtls_ecp_point_free(&R1); + mbedtls_ecp_point_free(&R2); + /* Premature return on H/W success, or continue to do other S/W clean-up + * because it is involved as fallback. */ + if (!sw_fallback) { + return ret; + } + } +#endif +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + + mbedtls_ecp_point_free( &mP ); + + ECP_RS_LEAVE( ma ); + + return( ret ); +} + +/* + * Linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + return( mbedtls_ecp_muladd_restartable( grp, R, m, P, n, Q, NULL ) ); +} +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) +/* + * Check validity of a public key for Montgomery curves with x-only schemes + */ +static int ecp_check_pubkey_mx( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + /* [Curve25519 p. 5] Just check X is the correct number of bytes */ + /* Allow any public value, if it's too big then we'll just reduce it mod p + * (RFC 7748 sec. 5 para. 3). */ + if( mbedtls_mpi_size( &pt->X ) > ( grp->nbits + 7 ) / 8 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( 0 ); +} +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + +/* + * Check that a point is valid as a public key + */ +int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + + /* Must use affine coordinates */ + if( mbedtls_mpi_cmp_int( &pt->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + return( ecp_check_pubkey_mx( grp, pt ) ); +#endif +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + return( ecp_check_pubkey_sw( grp, pt ) ); +#endif + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Check that an mbedtls_mpi is valid as a private key + */ +int mbedtls_ecp_check_privkey( const mbedtls_ecp_group *grp, + const mbedtls_mpi *d ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + /* see RFC 7748 sec. 5 para. 5 */ + if( mbedtls_mpi_get_bit( d, 0 ) != 0 || + mbedtls_mpi_get_bit( d, 1 ) != 0 || + mbedtls_mpi_bitlen( d ) - 1 != grp->nbits ) /* mbedtls_mpi_bitlen is one-based! */ + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + /* see [Curve25519] page 5 */ + if( grp->nbits == 254 && mbedtls_mpi_get_bit( d, 2 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( 0 ); + } +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* see SEC1 3.2 */ + if( mbedtls_mpi_cmp_int( d, 1 ) < 0 || + mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + else + return( 0 ); + } +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Generate a private key + */ +int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp, + mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + size_t n_size; + + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + n_size = ( grp->nbits + 7 ) / 8; + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + /* [M225] page 5 */ + size_t b; + + do { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + } while( mbedtls_mpi_bitlen( d ) == 0); + + /* Make sure the most significant bit is nbits */ + b = mbedtls_mpi_bitlen( d ) - 1; /* mbedtls_mpi_bitlen is one-based */ + if( b > grp->nbits ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, b - grp->nbits ) ); + else + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, grp->nbits, 1 ) ); + + /* Make sure the last two bits are unset for Curve448, three bits for + Curve25519 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 0, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 1, 0 ) ); + if( grp->nbits == 254 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 2, 0 ) ); + } + } +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* SEC1 3.2.1: Generate d such that 1 <= n < N */ + int count = 0; + unsigned cmp = 0; + + /* + * Match the procedure given in RFC 6979 (deterministic ECDSA): + * - use the same byte ordering; + * - keep the leftmost nbits bits of the generated octet string; + * - try until result is in the desired range. + * This also avoids any biais, which is especially important for ECDSA. + */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, 8 * n_size - grp->nbits ) ); + + /* + * Each try has at worst a probability 1/2 of failing (the msb has + * a probability 1/2 of being 0, and then the result will be < N), + * so after 30 tries failure probability is a most 2**(-30). + * + * For most curves, 1 try is enough with overwhelming probability, + * since N starts with a lot of 1s in binary, but some curves + * such as secp224k1 are actually very close to the worst case. + */ + if( ++count > 30 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + + ret = mbedtls_mpi_lt_mpi_ct( d, &grp->N, &cmp ); + if( ret != 0 ) + { + goto cleanup; + } + } + while( mbedtls_mpi_cmp_int( d, 1 ) < 0 || cmp != 1 ); + } +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +cleanup: + return( ret ); +} + +/* + * Generate a keypair with configurable base point + */ +int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp, + const mbedtls_ecp_point *G, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( G != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, d, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( grp, Q, d, G, f_rng, p_rng ) ); + +cleanup: + return( ret ); +} + +/* + * Generate key pair, wrapper for conventional base point + */ +int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + return( mbedtls_ecp_gen_keypair_base( grp, &grp->G, d, Q, f_rng, p_rng ) ); +} + +/* + * Generate a keypair, prettier wrapper + */ +int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + ECP_VALIDATE_RET( key != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + if( ( ret = mbedtls_ecp_group_load( &key->grp, grp_id ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_gen_keypair( &key->grp, &key->d, &key->Q, f_rng, p_rng ) ); +} + +#define ECP_CURVE25519_KEY_SIZE 32 +/* + * Read a private key. + */ +int mbedtls_ecp_read_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + const unsigned char *buf, size_t buflen ) +{ + int ret = 0; + + ECP_VALIDATE_RET( key != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + + if( ( ret = mbedtls_ecp_group_load( &key->grp, grp_id ) ) != 0 ) + return( ret ); + + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( mbedtls_ecp_get_type( &key->grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + /* + * If it is Curve25519 curve then mask the key as mandated by RFC7748 + */ + if( grp_id == MBEDTLS_ECP_DP_CURVE25519 ) + { + if( buflen != ECP_CURVE25519_KEY_SIZE ) + return MBEDTLS_ERR_ECP_INVALID_KEY; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary_le( &key->d, buf, buflen ) ); + + /* Set the three least significant bits to 0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &key->d, 0, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &key->d, 1, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &key->d, 2, 0 ) ); + + /* Set the most significant bit to 0 */ + MBEDTLS_MPI_CHK( + mbedtls_mpi_set_bit( &key->d, + ECP_CURVE25519_KEY_SIZE * 8 - 1, 0 ) + ); + + /* Set the second most significant bit to 1 */ + MBEDTLS_MPI_CHK( + mbedtls_mpi_set_bit( &key->d, + ECP_CURVE25519_KEY_SIZE * 8 - 2, 1 ) + ); + } + else + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } + +#endif +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( &key->grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &key->d, buf, buflen ) ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( &key->grp, &key->d ) ); + } + +#endif +cleanup: + + if( ret != 0 ) + mbedtls_mpi_free( &key->d ); + + return( ret ); +} + +/* + * Write a private key. + */ +int mbedtls_ecp_write_key( mbedtls_ecp_keypair *key, + unsigned char *buf, size_t buflen ) +{ + int ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + + ECP_VALIDATE_RET( key != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( mbedtls_ecp_get_type( &key->grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + if( key->grp.id == MBEDTLS_ECP_DP_CURVE25519 ) + { + if( buflen < ECP_CURVE25519_KEY_SIZE ) + return MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL; + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary_le( &key->d, buf, buflen ) ); + } + else + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } + +#endif +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + if( mbedtls_ecp_get_type( &key->grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &key->d, buf, buflen ) ); + } + +#endif +cleanup: + + return( ret ); +} + + +/* + * Check a public-private key pair + */ +int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_point Q; + mbedtls_ecp_group grp; + ECP_VALIDATE_RET( pub != NULL ); + ECP_VALIDATE_RET( prv != NULL ); + + if( pub->grp.id == MBEDTLS_ECP_DP_NONE || + pub->grp.id != prv->grp.id || + mbedtls_mpi_cmp_mpi( &pub->Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Z, &prv->Q.Z ) ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + mbedtls_ecp_point_init( &Q ); + mbedtls_ecp_group_init( &grp ); + + /* mbedtls_ecp_mul() needs a non-const group... */ + mbedtls_ecp_group_copy( &grp, &prv->grp ); + + /* Also checks d is valid */ + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &Q, &prv->d, &prv->grp.G, NULL, NULL ) ); + + if( mbedtls_mpi_cmp_mpi( &Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &Q.Z, &prv->Q.Z ) ) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + +cleanup: + mbedtls_ecp_point_free( &Q ); + mbedtls_ecp_group_free( &grp ); + + return( ret ); +} + +#if defined(MBEDTLS_SELF_TEST) + +/* Adjust the exponent to be a valid private point for the specified curve. + * This is sometimes necessary because we use a single set of exponents + * for all curves but the validity of values depends on the curve. */ +static int self_test_adjust_exponent( const mbedtls_ecp_group *grp, + mbedtls_mpi *m ) +{ + int ret = 0; + switch( grp->id ) + { + /* If Curve25519 is available, then that's what we use for the + * Montgomery test, so we don't need the adjustment code. */ +#if ! defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + case MBEDTLS_ECP_DP_CURVE448: + /* Move highest bit from 254 to N-1. Setting bit N-1 is + * necessary to enforce the highest-bit-set constraint. */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( m, 254, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( m, grp->nbits, 1 ) ); + /* Copy second-highest bit from 253 to N-2. This is not + * necessary but improves the test variety a bit. */ + MBEDTLS_MPI_CHK( + mbedtls_mpi_set_bit( m, grp->nbits - 1, + mbedtls_mpi_get_bit( m, 253 ) ) ); + break; +#endif +#endif /* ! defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) */ + default: + /* Non-Montgomery curves and Curve25519 need no adjustment. */ + (void) grp; + (void) m; + goto cleanup; + } +cleanup: + return( ret ); +} + +/* Calculate R = m.P for each m in exponents. Check that the number of + * basic operations doesn't depend on the value of m. */ +static int self_test_point( int verbose, + mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + mbedtls_mpi *m, + const mbedtls_ecp_point *P, + const char *const *exponents, + size_t n_exponents ) +{ + int ret = 0; + size_t i = 0; + unsigned long add_c_prev, dbl_c_prev, mul_c_prev; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( m, 16, exponents[0] ) ); + MBEDTLS_MPI_CHK( self_test_adjust_exponent( grp, m ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( grp, R, m, P, NULL, NULL ) ); + + for( i = 1; i < n_exponents; i++ ) + { + add_c_prev = add_count; + dbl_c_prev = dbl_count; + mul_c_prev = mul_count; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( m, 16, exponents[i] ) ); + MBEDTLS_MPI_CHK( self_test_adjust_exponent( grp, m ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( grp, R, m, P, NULL, NULL ) ); + + if( add_count != add_c_prev || + dbl_count != dbl_c_prev || + mul_count != mul_c_prev ) + { + ret = 1; + break; + } + } + +cleanup: + if( verbose != 0 ) + { + if( ret != 0 ) + mbedtls_printf( "failed (%u)\n", (unsigned int) i ); + else + mbedtls_printf( "passed\n" ); + } + return( ret ); +} + +/* + * Checkup routine + */ +int mbedtls_ecp_self_test( int verbose ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_group grp; + mbedtls_ecp_point R, P; + mbedtls_mpi m; + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + /* Exponents especially adapted for secp192k1, which has the lowest + * order n of all supported curves (secp192r1 is in a slightly larger + * field but the order of its base point is slightly smaller). */ + const char *sw_exponents[] = + { + "000000000000000000000000000000000000000000000001", /* one */ + "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8C", /* n - 1 */ + "5EA6F389A38B8BC81E767753B15AA5569E1782E30ABE7D25", /* random */ + "400000000000000000000000000000000000000000000000", /* one and zeros */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* all ones */ + "555555555555555555555555555555555555555555555555", /* 101010... */ + }; +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + const char *m_exponents[] = + { + /* Valid private values for Curve25519. In a build with Curve448 + * but not Curve25519, they will be adjusted in + * self_test_adjust_exponent(). */ + "4000000000000000000000000000000000000000000000000000000000000000", + "5C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C30", + "5715ECCE24583F7A7023C24164390586842E816D7280A49EF6DF4EAE6B280BF8", + "41A2B017516F6D254E1F002BCCBADD54BE30F8CEC737A0E912B4963B6BA74460", + "5555555555555555555555555555555555555555555555555555555555555550", + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8", + }; +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + + mbedtls_ecp_group_init( &grp ); + mbedtls_ecp_point_init( &R ); + mbedtls_ecp_point_init( &P ); + mbedtls_mpi_init( &m ); + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + /* Use secp192r1 if available, or any available curve */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, MBEDTLS_ECP_DP_SECP192R1 ) ); +#else + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, mbedtls_ecp_curve_list()->grp_id ) ); +#endif + + if( verbose != 0 ) + mbedtls_printf( " ECP SW test #1 (constant op_count, base point G): " ); + /* Do a dummy multiplication first to trigger precomputation */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &m, 2 ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &P, &m, &grp.G, NULL, NULL ) ); + ret = self_test_point( verbose, + &grp, &R, &m, &grp.G, + sw_exponents, + sizeof( sw_exponents ) / sizeof( sw_exponents[0] )); + if( ret != 0 ) + goto cleanup; + + if( verbose != 0 ) + mbedtls_printf( " ECP SW test #2 (constant op_count, other point): " ); + /* We computed P = 2G last time, use it */ + ret = self_test_point( verbose, + &grp, &R, &m, &P, + sw_exponents, + sizeof( sw_exponents ) / sizeof( sw_exponents[0] )); + if( ret != 0 ) + goto cleanup; + + mbedtls_ecp_group_free( &grp ); + mbedtls_ecp_point_free( &R ); +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + if( verbose != 0 ) + mbedtls_printf( " ECP Montgomery test (constant op_count): " ); +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, MBEDTLS_ECP_DP_CURVE25519 ) ); +#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, MBEDTLS_ECP_DP_CURVE448 ) ); +#else +#error "MBEDTLS_ECP_MONTGOMERY_ENABLED is defined, but no curve is supported for self-test" +#endif + ret = self_test_point( verbose, + &grp, &R, &m, &grp.G, + m_exponents, + sizeof( m_exponents ) / sizeof( m_exponents[0] )); + if( ret != 0 ) + goto cleanup; +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + +cleanup: + + if( ret < 0 && verbose != 0 ) + mbedtls_printf( "Unexpected error, return code = %08X\n", (unsigned int) ret ); + + mbedtls_ecp_group_free( &grp ); + mbedtls_ecp_point_free( &R ); + mbedtls_ecp_point_free( &P ); + mbedtls_mpi_free( &m ); + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_alt.h new file mode 100644 index 0000000..8c7c8d1 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_alt.h @@ -0,0 +1,187 @@ +/** + * \file ecp_alt.h + * + * \brief This file provides an API for Elliptic Curves over GF(P) (ECP). + * + * The use of ECP in cryptography and TLS is defined in + * Standards for Efficient Cryptography Group (SECG): SEC1 + * Elliptic Curve Cryptography and + * RFC-4492: Elliptic Curve Cryptography (ECC) Cipher Suites + * for Transport Layer Security (TLS). + * + * RFC-2409: The Internet Key Exchange (IKE) defines ECP + * group types. + * + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_ECP_ALT_H +#define MBEDTLS_ECP_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "mbedtls/bignum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_ECP_ALT) + +/* Enable Nuvoton's Crypto ECC H/W */ +#define NU_CRYPTO_ECC_ENABLE + +/* + * default mbed TLS elliptic curve arithmetic implementation + * + * (in case MBEDTLS_ECP_ALT is defined then the developer has to provide an + * alternative implementation for the whole module and it will replace this + * one.) + */ + +/** + * \brief The ECP group structure. + * + * We consider two types of curve equations: + *
  • Short Weierstrass: y^2 = x^3 + A x + B mod P + * (SEC1 + RFC-4492)
    • + *
  • Montgomery: y^2 = x^3 + A x^2 + x mod P (Curve25519, + * Curve448)
+ * In both cases, the generator (\p G) for a prime-order subgroup is fixed. + * + * For Short Weierstrass, this subgroup is the whole curve, and its + * cardinality is denoted by \p N. Our code requires that \p N is an + * odd prime as mbedtls_ecp_mul() requires an odd number, and + * mbedtls_ecdsa_sign() requires that it is prime for blinding purposes. + * + * For Montgomery curves, we do not store \p A, but (A + 2) / 4, + * which is the quantity used in the formulas. Additionally, \p nbits is + * not the size of \p N but the required size for private keys. + * + * If \p modp is NULL, reduction modulo \p P is done using a generic algorithm. + * Otherwise, \p modp must point to a function that takes an \p mbedtls_mpi in the + * range of 0..2^(2*pbits)-1, and transforms it in-place to an integer + * which is congruent mod \p P to the given MPI, and is close enough to \p pbits + * in size, so that it may be efficiently brought in the 0..P-1 range by a few + * additions or subtractions. Therefore, it is only an approximative modular + * reduction. It must return 0 on success and non-zero on failure. + * + * \note Alternative implementations must keep the group IDs distinct. If + * two group structures have the same ID, then they must be + * identical. + * + */ +typedef struct mbedtls_ecp_group +{ + mbedtls_ecp_group_id id; /*!< An internal group identifier. */ + mbedtls_mpi P; /*!< The prime modulus of the base field. */ + mbedtls_mpi A; /*!< For Short Weierstrass: \p A in the equation. For + Montgomery curves: (A + 2) / 4. */ + mbedtls_mpi B; /*!< For Short Weierstrass: \p B in the equation. + For Montgomery curves: unused. */ + mbedtls_ecp_point G; /*!< The generator of the subgroup used. */ + mbedtls_mpi N; /*!< The order of \p G. */ + size_t pbits; /*!< The number of bits in \p P.*/ + size_t nbits; /*!< For Short Weierstrass: The number of bits in \p P. + For Montgomery curves: the number of bits in the + private keys. */ + unsigned int h; /*!< \internal 1 if the constants are static. */ + int (*modp)(mbedtls_mpi *); /*!< The function for fast pseudo-reduction + mod \p P (see above).*/ + int (*t_pre)(mbedtls_ecp_point *, void *); /*!< Unused. */ + int (*t_post)(mbedtls_ecp_point *, void *); /*!< Unused. */ + void *t_data; /*!< Unused. */ + mbedtls_ecp_point *T; /*!< Pre-computed points for ecp_mul_comb(). */ + size_t T_size; /*!< The number of pre-computed points. */ + +#if defined(NU_CRYPTO_ECC_ENABLE) + int hw_init; /*!< Initialized Crypto ECC H/W or not. */ +#endif +} +mbedtls_ecp_group; + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h, or define them using the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_ECP_MAX_BITS) +/** + * The maximum size of the groups, that is, of \c N and \c P. + */ +#define MBEDTLS_ECP_MAX_BITS 521 /**< The maximum size of groups, in bits. */ +#endif + +#define MBEDTLS_ECP_MAX_BYTES ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 ) +#define MBEDTLS_ECP_MAX_PT_LEN ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 ) + +#if !defined(MBEDTLS_ECP_WINDOW_SIZE) +/* + * Maximum "window" size used for point multiplication. + * Default: 6. + * Minimum value: 2. Maximum value: 7. + * + * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + * points used for point multiplication. This value is directly tied to EC + * peak memory usage, so decreasing it by one should roughly cut memory usage + * by two (if large curves are in use). + * + * Reduction in size may reduce speed, but larger curves are impacted first. + * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1): + * w-size: 6 5 4 3 2 + * 521 145 141 135 120 97 + * 384 214 209 198 177 146 + * 256 320 320 303 262 226 + * 224 475 475 453 398 342 + * 192 640 640 633 587 476 + */ +#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< The maximum window size used. */ +#endif /* MBEDTLS_ECP_WINDOW_SIZE */ + +#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM) +/* + * Trade memory for speed on fixed-point multiplication. + * + * This speeds up repeated multiplication of the generator (that is, the + * multiplication in ECDSA signatures, and half of the multiplications in + * ECDSA verification and ECDHE) by a factor roughly 3 to 4. + * + * The cost is increasing EC peak memory usage by a factor roughly 2. + * + * Change this value to 0 to reduce peak memory usage. + */ +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up. */ +#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */ + +/* \} name SECTION: Module settings */ + +#endif /* MBEDTLS_ECP_ALT */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecp.h */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_curves_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_curves_alt.c new file mode 100644 index 0000000..69b6ddb --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_curves_alt.c @@ -0,0 +1,1490 @@ +/* + * Elliptic curves over GF(p): curve-specific data and functions + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" + +#include + +#if defined(MBEDTLS_ECP_ALT) + +/* Parameter validation macros based on platform_util.h */ +#define ECP_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECP_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +/* + * Conversion macros for embedded constants: + * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 + */ +#if defined(MBEDTLS_HAVE_INT32) + +#define BYTES_TO_T_UINT_4( a, b, c, d ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) + +#define BYTES_TO_T_UINT_2( a, b ) \ + BYTES_TO_T_UINT_4( a, b, 0, 0 ) + +#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + BYTES_TO_T_UINT_4( a, b, c, d ), \ + BYTES_TO_T_UINT_4( e, f, g, h ) + +#else /* 64-bits */ + +#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) | \ + ( (mbedtls_mpi_uint) (e) << 32 ) | \ + ( (mbedtls_mpi_uint) (f) << 40 ) | \ + ( (mbedtls_mpi_uint) (g) << 48 ) | \ + ( (mbedtls_mpi_uint) (h) << 56 ) + +#define BYTES_TO_T_UINT_4( a, b, c, d ) \ + BYTES_TO_T_UINT_8( a, b, c, d, 0, 0, 0, 0 ) + +#define BYTES_TO_T_UINT_2( a, b ) \ + BYTES_TO_T_UINT_8( a, b, 0, 0, 0, 0, 0, 0 ) + +#endif /* bits in mbedtls_mpi_uint */ + +/* + * Note: the constants are in little-endian order + * to be directly usable in MPIs + */ + +/* + * Domain parameters for secp192r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static const mbedtls_mpi_uint secp192r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192r1_b[] = { + BYTES_TO_T_UINT_8( 0xB1, 0xB9, 0x46, 0xC1, 0xEC, 0xDE, 0xB8, 0xFE ), + BYTES_TO_T_UINT_8( 0x49, 0x30, 0x24, 0x72, 0xAB, 0xE9, 0xA7, 0x0F ), + BYTES_TO_T_UINT_8( 0xE7, 0x80, 0x9C, 0xE5, 0x19, 0x05, 0x21, 0x64 ), +}; +static const mbedtls_mpi_uint secp192r1_gx[] = { + BYTES_TO_T_UINT_8( 0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4 ), + BYTES_TO_T_UINT_8( 0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C ), + BYTES_TO_T_UINT_8( 0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18 ), +}; +static const mbedtls_mpi_uint secp192r1_gy[] = { + BYTES_TO_T_UINT_8( 0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73 ), + BYTES_TO_T_UINT_8( 0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63 ), + BYTES_TO_T_UINT_8( 0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07 ), +}; +static const mbedtls_mpi_uint secp192r1_n[] = { + BYTES_TO_T_UINT_8( 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14 ), + BYTES_TO_T_UINT_8( 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +/* + * Domain parameters for secp224r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static const mbedtls_mpi_uint secp224r1_p[] = { + BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224r1_b[] = { + BYTES_TO_T_UINT_8( 0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27 ), + BYTES_TO_T_UINT_8( 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50 ), + BYTES_TO_T_UINT_8( 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C ), + BYTES_TO_T_UINT_4( 0x85, 0x0A, 0x05, 0xB4 ), +}; +static const mbedtls_mpi_uint secp224r1_gx[] = { + BYTES_TO_T_UINT_8( 0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34 ), + BYTES_TO_T_UINT_8( 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A ), + BYTES_TO_T_UINT_8( 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B ), + BYTES_TO_T_UINT_4( 0xBD, 0x0C, 0x0E, 0xB7 ), +}; +static const mbedtls_mpi_uint secp224r1_gy[] = { + BYTES_TO_T_UINT_8( 0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44 ), + BYTES_TO_T_UINT_8( 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD ), + BYTES_TO_T_UINT_8( 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5 ), + BYTES_TO_T_UINT_4( 0x88, 0x63, 0x37, 0xBD ), +}; +static const mbedtls_mpi_uint secp224r1_n[] = { + BYTES_TO_T_UINT_8( 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13 ), + BYTES_TO_T_UINT_8( 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +/* + * Domain parameters for secp256r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static const mbedtls_mpi_uint secp256r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256r1_b[] = { + BYTES_TO_T_UINT_8( 0x4B, 0x60, 0xD2, 0x27, 0x3E, 0x3C, 0xCE, 0x3B ), + BYTES_TO_T_UINT_8( 0xF6, 0xB0, 0x53, 0xCC, 0xB0, 0x06, 0x1D, 0x65 ), + BYTES_TO_T_UINT_8( 0xBC, 0x86, 0x98, 0x76, 0x55, 0xBD, 0xEB, 0xB3 ), + BYTES_TO_T_UINT_8( 0xE7, 0x93, 0x3A, 0xAA, 0xD8, 0x35, 0xC6, 0x5A ), +}; +static const mbedtls_mpi_uint secp256r1_gx[] = { + BYTES_TO_T_UINT_8( 0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4 ), + BYTES_TO_T_UINT_8( 0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77 ), + BYTES_TO_T_UINT_8( 0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8 ), + BYTES_TO_T_UINT_8( 0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B ), +}; +static const mbedtls_mpi_uint secp256r1_gy[] = { + BYTES_TO_T_UINT_8( 0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB ), + BYTES_TO_T_UINT_8( 0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B ), + BYTES_TO_T_UINT_8( 0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E ), + BYTES_TO_T_UINT_8( 0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F ), +}; +static const mbedtls_mpi_uint secp256r1_n[] = { + BYTES_TO_T_UINT_8( 0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3 ), + BYTES_TO_T_UINT_8( 0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +/* + * Domain parameters for secp384r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static const mbedtls_mpi_uint secp384r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp384r1_b[] = { + BYTES_TO_T_UINT_8( 0xEF, 0x2A, 0xEC, 0xD3, 0xED, 0xC8, 0x85, 0x2A ), + BYTES_TO_T_UINT_8( 0x9D, 0xD1, 0x2E, 0x8A, 0x8D, 0x39, 0x56, 0xC6 ), + BYTES_TO_T_UINT_8( 0x5A, 0x87, 0x13, 0x50, 0x8F, 0x08, 0x14, 0x03 ), + BYTES_TO_T_UINT_8( 0x12, 0x41, 0x81, 0xFE, 0x6E, 0x9C, 0x1D, 0x18 ), + BYTES_TO_T_UINT_8( 0x19, 0x2D, 0xF8, 0xE3, 0x6B, 0x05, 0x8E, 0x98 ), + BYTES_TO_T_UINT_8( 0xE4, 0xE7, 0x3E, 0xE2, 0xA7, 0x2F, 0x31, 0xB3 ), +}; +static const mbedtls_mpi_uint secp384r1_gx[] = { + BYTES_TO_T_UINT_8( 0xB7, 0x0A, 0x76, 0x72, 0x38, 0x5E, 0x54, 0x3A ), + BYTES_TO_T_UINT_8( 0x6C, 0x29, 0x55, 0xBF, 0x5D, 0xF2, 0x02, 0x55 ), + BYTES_TO_T_UINT_8( 0x38, 0x2A, 0x54, 0x82, 0xE0, 0x41, 0xF7, 0x59 ), + BYTES_TO_T_UINT_8( 0x98, 0x9B, 0xA7, 0x8B, 0x62, 0x3B, 0x1D, 0x6E ), + BYTES_TO_T_UINT_8( 0x74, 0xAD, 0x20, 0xF3, 0x1E, 0xC7, 0xB1, 0x8E ), + BYTES_TO_T_UINT_8( 0x37, 0x05, 0x8B, 0xBE, 0x22, 0xCA, 0x87, 0xAA ), +}; +static const mbedtls_mpi_uint secp384r1_gy[] = { + BYTES_TO_T_UINT_8( 0x5F, 0x0E, 0xEA, 0x90, 0x7C, 0x1D, 0x43, 0x7A ), + BYTES_TO_T_UINT_8( 0x9D, 0x81, 0x7E, 0x1D, 0xCE, 0xB1, 0x60, 0x0A ), + BYTES_TO_T_UINT_8( 0xC0, 0xB8, 0xF0, 0xB5, 0x13, 0x31, 0xDA, 0xE9 ), + BYTES_TO_T_UINT_8( 0x7C, 0x14, 0x9A, 0x28, 0xBD, 0x1D, 0xF4, 0xF8 ), + BYTES_TO_T_UINT_8( 0x29, 0xDC, 0x92, 0x92, 0xBF, 0x98, 0x9E, 0x5D ), + BYTES_TO_T_UINT_8( 0x6F, 0x2C, 0x26, 0x96, 0x4A, 0xDE, 0x17, 0x36 ), +}; +static const mbedtls_mpi_uint secp384r1_n[] = { + BYTES_TO_T_UINT_8( 0x73, 0x29, 0xC5, 0xCC, 0x6A, 0x19, 0xEC, 0xEC ), + BYTES_TO_T_UINT_8( 0x7A, 0xA7, 0xB0, 0x48, 0xB2, 0x0D, 0x1A, 0x58 ), + BYTES_TO_T_UINT_8( 0xDF, 0x2D, 0x37, 0xF4, 0x81, 0x4D, 0x63, 0xC7 ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +/* + * Domain parameters for secp521r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static const mbedtls_mpi_uint secp521r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_b[] = { + BYTES_TO_T_UINT_8( 0x00, 0x3F, 0x50, 0x6B, 0xD4, 0x1F, 0x45, 0xEF ), + BYTES_TO_T_UINT_8( 0xF1, 0x34, 0x2C, 0x3D, 0x88, 0xDF, 0x73, 0x35 ), + BYTES_TO_T_UINT_8( 0x07, 0xBF, 0xB1, 0x3B, 0xBD, 0xC0, 0x52, 0x16 ), + BYTES_TO_T_UINT_8( 0x7B, 0x93, 0x7E, 0xEC, 0x51, 0x39, 0x19, 0x56 ), + BYTES_TO_T_UINT_8( 0xE1, 0x09, 0xF1, 0x8E, 0x91, 0x89, 0xB4, 0xB8 ), + BYTES_TO_T_UINT_8( 0xF3, 0x15, 0xB3, 0x99, 0x5B, 0x72, 0xDA, 0xA2 ), + BYTES_TO_T_UINT_8( 0xEE, 0x40, 0x85, 0xB6, 0xA0, 0x21, 0x9A, 0x92 ), + BYTES_TO_T_UINT_8( 0x1F, 0x9A, 0x1C, 0x8E, 0x61, 0xB9, 0x3E, 0x95 ), + BYTES_TO_T_UINT_2( 0x51, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gx[] = { + BYTES_TO_T_UINT_8( 0x66, 0xBD, 0xE5, 0xC2, 0x31, 0x7E, 0x7E, 0xF9 ), + BYTES_TO_T_UINT_8( 0x9B, 0x42, 0x6A, 0x85, 0xC1, 0xB3, 0x48, 0x33 ), + BYTES_TO_T_UINT_8( 0xDE, 0xA8, 0xFF, 0xA2, 0x27, 0xC1, 0x1D, 0xFE ), + BYTES_TO_T_UINT_8( 0x28, 0x59, 0xE7, 0xEF, 0x77, 0x5E, 0x4B, 0xA1 ), + BYTES_TO_T_UINT_8( 0xBA, 0x3D, 0x4D, 0x6B, 0x60, 0xAF, 0x28, 0xF8 ), + BYTES_TO_T_UINT_8( 0x21, 0xB5, 0x3F, 0x05, 0x39, 0x81, 0x64, 0x9C ), + BYTES_TO_T_UINT_8( 0x42, 0xB4, 0x95, 0x23, 0x66, 0xCB, 0x3E, 0x9E ), + BYTES_TO_T_UINT_8( 0xCD, 0xE9, 0x04, 0x04, 0xB7, 0x06, 0x8E, 0x85 ), + BYTES_TO_T_UINT_2( 0xC6, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gy[] = { + BYTES_TO_T_UINT_8( 0x50, 0x66, 0xD1, 0x9F, 0x76, 0x94, 0xBE, 0x88 ), + BYTES_TO_T_UINT_8( 0x40, 0xC2, 0x72, 0xA2, 0x86, 0x70, 0x3C, 0x35 ), + BYTES_TO_T_UINT_8( 0x61, 0x07, 0xAD, 0x3F, 0x01, 0xB9, 0x50, 0xC5 ), + BYTES_TO_T_UINT_8( 0x40, 0x26, 0xF4, 0x5E, 0x99, 0x72, 0xEE, 0x97 ), + BYTES_TO_T_UINT_8( 0x2C, 0x66, 0x3E, 0x27, 0x17, 0xBD, 0xAF, 0x17 ), + BYTES_TO_T_UINT_8( 0x68, 0x44, 0x9B, 0x57, 0x49, 0x44, 0xF5, 0x98 ), + BYTES_TO_T_UINT_8( 0xD9, 0x1B, 0x7D, 0x2C, 0xB4, 0x5F, 0x8A, 0x5C ), + BYTES_TO_T_UINT_8( 0x04, 0xC0, 0x3B, 0x9A, 0x78, 0x6A, 0x29, 0x39 ), + BYTES_TO_T_UINT_2( 0x18, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_n[] = { + BYTES_TO_T_UINT_8( 0x09, 0x64, 0x38, 0x91, 0x1E, 0xB7, 0x6F, 0xBB ), + BYTES_TO_T_UINT_8( 0xAE, 0x47, 0x9C, 0x89, 0xB8, 0xC9, 0xB5, 0x3B ), + BYTES_TO_T_UINT_8( 0xD0, 0xA5, 0x09, 0xF7, 0x48, 0x01, 0xCC, 0x7F ), + BYTES_TO_T_UINT_8( 0x6B, 0x96, 0x2F, 0xBF, 0x83, 0x87, 0x86, 0x51 ), + BYTES_TO_T_UINT_8( 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static const mbedtls_mpi_uint secp192k1_p[] = { + BYTES_TO_T_UINT_8( 0x37, 0xEE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_b[] = { + BYTES_TO_T_UINT_2( 0x03, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_gx[] = { + BYTES_TO_T_UINT_8( 0x7D, 0x6C, 0xE0, 0xEA, 0xB1, 0xD1, 0xA5, 0x1D ), + BYTES_TO_T_UINT_8( 0x34, 0xF4, 0xB7, 0x80, 0x02, 0x7D, 0xB0, 0x26 ), + BYTES_TO_T_UINT_8( 0xAE, 0xE9, 0x57, 0xC0, 0x0E, 0xF1, 0x4F, 0xDB ), +}; +static const mbedtls_mpi_uint secp192k1_gy[] = { + BYTES_TO_T_UINT_8( 0x9D, 0x2F, 0x5E, 0xD9, 0x88, 0xAA, 0x82, 0x40 ), + BYTES_TO_T_UINT_8( 0x34, 0x86, 0xBE, 0x15, 0xD0, 0x63, 0x41, 0x84 ), + BYTES_TO_T_UINT_8( 0xA7, 0x28, 0x56, 0x9C, 0x6D, 0x2F, 0x2F, 0x9B ), +}; +static const mbedtls_mpi_uint secp192k1_n[] = { + BYTES_TO_T_UINT_8( 0x8D, 0xFD, 0xDE, 0x74, 0x6A, 0x46, 0x69, 0x0F ), + BYTES_TO_T_UINT_8( 0x17, 0xFC, 0xF2, 0x26, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static const mbedtls_mpi_uint secp224k1_p[] = { + BYTES_TO_T_UINT_8( 0x6D, 0xE5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp224k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_b[] = { + BYTES_TO_T_UINT_2( 0x05, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_gx[] = { + BYTES_TO_T_UINT_8( 0x5C, 0xA4, 0xB7, 0xB6, 0x0E, 0x65, 0x7E, 0x0F ), + BYTES_TO_T_UINT_8( 0xA9, 0x75, 0x70, 0xE4, 0xE9, 0x67, 0xA4, 0x69 ), + BYTES_TO_T_UINT_8( 0xA1, 0x28, 0xFC, 0x30, 0xDF, 0x99, 0xF0, 0x4D ), + BYTES_TO_T_UINT_4( 0x33, 0x5B, 0x45, 0xA1 ), +}; +static const mbedtls_mpi_uint secp224k1_gy[] = { + BYTES_TO_T_UINT_8( 0xA5, 0x61, 0x6D, 0x55, 0xDB, 0x4B, 0xCA, 0xE2 ), + BYTES_TO_T_UINT_8( 0x59, 0xBD, 0xB0, 0xC0, 0xF7, 0x19, 0xE3, 0xF7 ), + BYTES_TO_T_UINT_8( 0xD6, 0xFB, 0xCA, 0x82, 0x42, 0x34, 0xBA, 0x7F ), + BYTES_TO_T_UINT_4( 0xED, 0x9F, 0x08, 0x7E ), +}; +static const mbedtls_mpi_uint secp224k1_n[] = { + BYTES_TO_T_UINT_8( 0xF7, 0xB1, 0x9F, 0x76, 0x71, 0xA9, 0xF0, 0xCA ), + BYTES_TO_T_UINT_8( 0x84, 0x61, 0xEC, 0xD2, 0xE8, 0xDC, 0x01, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static const mbedtls_mpi_uint secp256k1_p[] = { + BYTES_TO_T_UINT_8( 0x2F, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_b[] = { + BYTES_TO_T_UINT_2( 0x07, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_gx[] = { + BYTES_TO_T_UINT_8( 0x98, 0x17, 0xF8, 0x16, 0x5B, 0x81, 0xF2, 0x59 ), + BYTES_TO_T_UINT_8( 0xD9, 0x28, 0xCE, 0x2D, 0xDB, 0xFC, 0x9B, 0x02 ), + BYTES_TO_T_UINT_8( 0x07, 0x0B, 0x87, 0xCE, 0x95, 0x62, 0xA0, 0x55 ), + BYTES_TO_T_UINT_8( 0xAC, 0xBB, 0xDC, 0xF9, 0x7E, 0x66, 0xBE, 0x79 ), +}; +static const mbedtls_mpi_uint secp256k1_gy[] = { + BYTES_TO_T_UINT_8( 0xB8, 0xD4, 0x10, 0xFB, 0x8F, 0xD0, 0x47, 0x9C ), + BYTES_TO_T_UINT_8( 0x19, 0x54, 0x85, 0xA6, 0x48, 0xB4, 0x17, 0xFD ), + BYTES_TO_T_UINT_8( 0xA8, 0x08, 0x11, 0x0E, 0xFC, 0xFB, 0xA4, 0x5D ), + BYTES_TO_T_UINT_8( 0x65, 0xC4, 0xA3, 0x26, 0x77, 0xDA, 0x3A, 0x48 ), +}; +static const mbedtls_mpi_uint secp256k1_n[] = { + BYTES_TO_T_UINT_8( 0x41, 0x41, 0x36, 0xD0, 0x8C, 0x5E, 0xD2, 0xBF ), + BYTES_TO_T_UINT_8( 0x3B, 0xA0, 0x48, 0xAF, 0xE6, 0xDC, 0xAE, 0xBA ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +/* + * Domain parameters for brainpoolP256r1 (RFC 5639 3.4) + */ +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP256r1_p[] = { + BYTES_TO_T_UINT_8( 0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20 ), + BYTES_TO_T_UINT_8( 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E ), + BYTES_TO_T_UINT_8( 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_a[] = { + BYTES_TO_T_UINT_8( 0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9 ), + BYTES_TO_T_UINT_8( 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB ), + BYTES_TO_T_UINT_8( 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE ), + BYTES_TO_T_UINT_8( 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_b[] = { + BYTES_TO_T_UINT_8( 0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B ), + BYTES_TO_T_UINT_8( 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95 ), + BYTES_TO_T_UINT_8( 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3 ), + BYTES_TO_T_UINT_8( 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gx[] = { + BYTES_TO_T_UINT_8( 0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A ), + BYTES_TO_T_UINT_8( 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9 ), + BYTES_TO_T_UINT_8( 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C ), + BYTES_TO_T_UINT_8( 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gy[] = { + BYTES_TO_T_UINT_8( 0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C ), + BYTES_TO_T_UINT_8( 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2 ), + BYTES_TO_T_UINT_8( 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97 ), + BYTES_TO_T_UINT_8( 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_n[] = { + BYTES_TO_T_UINT_8( 0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90 ), + BYTES_TO_T_UINT_8( 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C ), + BYTES_TO_T_UINT_8( 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +/* + * Domain parameters for brainpoolP384r1 (RFC 5639 3.6) + */ +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP384r1_p[] = { + BYTES_TO_T_UINT_8( 0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87 ), + BYTES_TO_T_UINT_8( 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC ), + BYTES_TO_T_UINT_8( 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12 ), + BYTES_TO_T_UINT_8( 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_a[] = { + BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), + BYTES_TO_T_UINT_8( 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A ), + BYTES_TO_T_UINT_8( 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13 ), + BYTES_TO_T_UINT_8( 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2 ), + BYTES_TO_T_UINT_8( 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C ), + BYTES_TO_T_UINT_8( 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_b[] = { + BYTES_TO_T_UINT_8( 0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A ), + BYTES_TO_T_UINT_8( 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C ), + BYTES_TO_T_UINT_8( 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E ), + BYTES_TO_T_UINT_8( 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F ), + BYTES_TO_T_UINT_8( 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B ), + BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gx[] = { + BYTES_TO_T_UINT_8( 0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF ), + BYTES_TO_T_UINT_8( 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8 ), + BYTES_TO_T_UINT_8( 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB ), + BYTES_TO_T_UINT_8( 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88 ), + BYTES_TO_T_UINT_8( 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2 ), + BYTES_TO_T_UINT_8( 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gy[] = { + BYTES_TO_T_UINT_8( 0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42 ), + BYTES_TO_T_UINT_8( 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E ), + BYTES_TO_T_UINT_8( 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1 ), + BYTES_TO_T_UINT_8( 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62 ), + BYTES_TO_T_UINT_8( 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C ), + BYTES_TO_T_UINT_8( 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_n[] = { + BYTES_TO_T_UINT_8( 0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B ), + BYTES_TO_T_UINT_8( 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF ), + BYTES_TO_T_UINT_8( 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F ), + BYTES_TO_T_UINT_8( 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +/* + * Domain parameters for brainpoolP512r1 (RFC 5639 3.7) + */ +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP512r1_p[] = { + BYTES_TO_T_UINT_8( 0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28 ), + BYTES_TO_T_UINT_8( 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28 ), + BYTES_TO_T_UINT_8( 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE ), + BYTES_TO_T_UINT_8( 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D ), + BYTES_TO_T_UINT_8( 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_a[] = { + BYTES_TO_T_UINT_8( 0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7 ), + BYTES_TO_T_UINT_8( 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F ), + BYTES_TO_T_UINT_8( 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A ), + BYTES_TO_T_UINT_8( 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D ), + BYTES_TO_T_UINT_8( 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8 ), + BYTES_TO_T_UINT_8( 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94 ), + BYTES_TO_T_UINT_8( 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2 ), + BYTES_TO_T_UINT_8( 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_b[] = { + BYTES_TO_T_UINT_8( 0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28 ), + BYTES_TO_T_UINT_8( 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98 ), + BYTES_TO_T_UINT_8( 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77 ), + BYTES_TO_T_UINT_8( 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B ), + BYTES_TO_T_UINT_8( 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B ), + BYTES_TO_T_UINT_8( 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8 ), + BYTES_TO_T_UINT_8( 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA ), + BYTES_TO_T_UINT_8( 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gx[] = { + BYTES_TO_T_UINT_8( 0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B ), + BYTES_TO_T_UINT_8( 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C ), + BYTES_TO_T_UINT_8( 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50 ), + BYTES_TO_T_UINT_8( 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF ), + BYTES_TO_T_UINT_8( 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4 ), + BYTES_TO_T_UINT_8( 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85 ), + BYTES_TO_T_UINT_8( 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A ), + BYTES_TO_T_UINT_8( 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gy[] = { + BYTES_TO_T_UINT_8( 0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78 ), + BYTES_TO_T_UINT_8( 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1 ), + BYTES_TO_T_UINT_8( 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B ), + BYTES_TO_T_UINT_8( 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2 ), + BYTES_TO_T_UINT_8( 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0 ), + BYTES_TO_T_UINT_8( 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2 ), + BYTES_TO_T_UINT_8( 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0 ), + BYTES_TO_T_UINT_8( 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_n[] = { + BYTES_TO_T_UINT_8( 0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5 ), + BYTES_TO_T_UINT_8( 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D ), + BYTES_TO_T_UINT_8( 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41 ), + BYTES_TO_T_UINT_8( 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55 ), + BYTES_TO_T_UINT_8( 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* For these curves, we build the group parameters dynamically. */ +#define ECP_LOAD_GROUP +#endif + +#if defined(ECP_LOAD_GROUP) +/* + * Create an MPI from embedded constants + * (assumes len is an exact multiple of sizeof mbedtls_mpi_uint) + */ +static inline void ecp_mpi_load( mbedtls_mpi *X, const mbedtls_mpi_uint *p, size_t len ) +{ + X->s = 1; + X->n = len / sizeof( mbedtls_mpi_uint ); + X->p = (mbedtls_mpi_uint *) p; +} + +/* + * Set an MPI to static value 1 + */ +static inline void ecp_mpi_set1( mbedtls_mpi *X ) +{ + static mbedtls_mpi_uint one[] = { 1 }; + X->s = 1; + X->n = 1; + X->p = one; +} + +/* + * Make group available from embedded constants + */ +static int ecp_group_load( mbedtls_ecp_group *grp, + const mbedtls_mpi_uint *p, size_t plen, + const mbedtls_mpi_uint *a, size_t alen, + const mbedtls_mpi_uint *b, size_t blen, + const mbedtls_mpi_uint *gx, size_t gxlen, + const mbedtls_mpi_uint *gy, size_t gylen, + const mbedtls_mpi_uint *n, size_t nlen) +{ + ecp_mpi_load( &grp->P, p, plen ); + if( a != NULL ) + ecp_mpi_load( &grp->A, a, alen ); + ecp_mpi_load( &grp->B, b, blen ); + ecp_mpi_load( &grp->N, n, nlen ); + + ecp_mpi_load( &grp->G.X, gx, gxlen ); + ecp_mpi_load( &grp->G.Y, gy, gylen ); + ecp_mpi_set1( &grp->G.Z ); + + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + grp->nbits = mbedtls_mpi_bitlen( &grp->N ); + + grp->h = 1; + + return( 0 ); +} +#endif /* ECP_LOAD_GROUP */ + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* Forward declarations */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static int ecp_mod_p192( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static int ecp_mod_p224( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static int ecp_mod_p256( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static int ecp_mod_p384( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static int ecp_mod_p521( mbedtls_mpi * ); +#endif + +#define NIST_MODP( P ) grp->modp = ecp_mod_ ## P; +#else +#define NIST_MODP( P ) +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +/* Additional forward declarations */ +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +static int ecp_mod_p255( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +static int ecp_mod_p448( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static int ecp_mod_p192k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static int ecp_mod_p224k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static int ecp_mod_p256k1( mbedtls_mpi * ); +#endif + +#if defined(ECP_LOAD_GROUP) +#define LOAD_GROUP_A( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + G ## _a, sizeof( G ## _a ), \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) + +#define LOAD_GROUP( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + NULL, 0, \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) +#endif /* ECP_LOAD_GROUP */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +/* + * Specialized function for creating the Curve25519 group + */ +static int ecp_use_curve25519( mbedtls_ecp_group *grp ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "01DB42" ) ); + + /* P = 2^255 - 19 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 255 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 19 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* N = 2^252 + 27742317777372353535851937790883648493 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->N, 16, + "14DEF9DEA2F79CD65812631A5CF5D3ED" ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 252, 1 ) ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 9 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* Actually, the required msb for private keys */ + grp->nbits = 254; + +cleanup: + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +/* + * Specialized function for creating the Curve448 group + */ +static int ecp_use_curve448( mbedtls_ecp_group *grp ) +{ + mbedtls_mpi Ns; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + mbedtls_mpi_init( &Ns ); + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "98AA" ) ); + + /* P = 2^448 - 2^224 - 1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 5 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* N = 2^446 - 13818066809895115352007386748515426880336692474882178609894547503885 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 446, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &Ns, 16, + "8335DC163BB124B65129C96FDE933D8D723A70AADC873D6D54A7BB0D" ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &grp->N, &grp->N, &Ns ) ); + + /* Actually, the required msb for private keys */ + grp->nbits = 447; + +cleanup: + mbedtls_mpi_free( &Ns ); + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +/* + * Set a group using well-known domain parameters + */ +int mbedtls_ecp_group_load( mbedtls_ecp_group *grp, mbedtls_ecp_group_id id ) +{ + ECP_VALIDATE_RET( grp != NULL ); + mbedtls_ecp_group_free( grp ); + + /* Fix Curve448 has wrong order value + * + * https://github.com/Mbed-TLS/mbedtls/pull/5811 + */ + mbedtls_ecp_group_init( grp ); + + grp->id = id; + + switch( id ) + { +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + case MBEDTLS_ECP_DP_SECP192R1: + NIST_MODP( p192 ); + return( LOAD_GROUP( secp192r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + case MBEDTLS_ECP_DP_SECP224R1: + NIST_MODP( p224 ); + return( LOAD_GROUP( secp224r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + case MBEDTLS_ECP_DP_SECP256R1: + NIST_MODP( p256 ); + return( LOAD_GROUP( secp256r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + case MBEDTLS_ECP_DP_SECP384R1: + NIST_MODP( p384 ); + return( LOAD_GROUP( secp384r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + case MBEDTLS_ECP_DP_SECP521R1: + NIST_MODP( p521 ); + return( LOAD_GROUP( secp521r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + case MBEDTLS_ECP_DP_SECP192K1: + grp->modp = ecp_mod_p192k1; + return( LOAD_GROUP_A( secp192k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + case MBEDTLS_ECP_DP_SECP224K1: + grp->modp = ecp_mod_p224k1; + return( LOAD_GROUP_A( secp224k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + case MBEDTLS_ECP_DP_SECP256K1: + grp->modp = ecp_mod_p256k1; + return( LOAD_GROUP_A( secp256k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + case MBEDTLS_ECP_DP_BP256R1: + return( LOAD_GROUP_A( brainpoolP256r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + case MBEDTLS_ECP_DP_BP384R1: + return( LOAD_GROUP_A( brainpoolP384r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + case MBEDTLS_ECP_DP_BP512R1: + return( LOAD_GROUP_A( brainpoolP512r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + case MBEDTLS_ECP_DP_CURVE25519: + grp->modp = ecp_mod_p255; + return( ecp_use_curve25519( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + case MBEDTLS_ECP_DP_CURVE448: + grp->modp = ecp_mod_p448; + return( ecp_use_curve448( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + + default: + grp->id = MBEDTLS_ECP_DP_NONE; + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + } +} + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* + * Fast reduction modulo the primes used by the NIST curves. + * + * These functions are critical for speed, but not needed for correct + * operations. So, we make the choice to heavily rely on the internals of our + * bignum library, which creates a tight coupling between these functions and + * our MPI implementation. However, the coupling between the ECP module and + * MPI remains loose, since these functions can be deactivated at will. + */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +/* + * Compared to the way things are presented in FIPS 186-3 D.2, + * we proceed in columns, from right (least significant chunk) to left, + * adding chunks to N in place, and keeping a carry for the next chunk. + * This avoids moving things around in memory, and uselessly adding zeros, + * compared to the more straightforward, line-oriented approach. + * + * For this prime we need to handle data in chunks of 64 bits. + * Since this is always a multiple of our basic mbedtls_mpi_uint, we can + * use a mbedtls_mpi_uint * to designate such a chunk, and small loops to handle it. + */ + +/* Add 64-bit chunks (dst += src) and update carry */ +static inline void add64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *src, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + mbedtls_mpi_uint c = 0; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++, src++ ) + { + *dst += c; c = ( *dst < c ); + *dst += *src; c += ( *dst < *src ); + } + *carry += c; +} + +/* Add carry to a 64-bit chunk and update carry */ +static inline void carry64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++ ) + { + *dst += *carry; + *carry = ( *dst < *carry ); + } +} + +#define WIDTH 8 / sizeof( mbedtls_mpi_uint ) +#define A( i ) N->p + (i) * WIDTH +#define ADD( i ) add64( p, A( i ), &c ) +#define NEXT p += WIDTH; carry64( p, &c ) +#define LAST p += WIDTH; *p = c; while( ++p < end ) *p = 0 + +/* + * Fast quasi-reduction modulo p192 (FIPS 186-3 D.2.1) + */ +static int ecp_mod_p192( mbedtls_mpi *N ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi_uint c = 0; + mbedtls_mpi_uint *p, *end; + + /* Make sure we have enough blocks so that A(5) is legal */ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, 6 * WIDTH ) ); + + p = N->p; + end = p + N->n; + + ADD( 3 ); ADD( 5 ); NEXT; // A0 += A3 + A5 + ADD( 3 ); ADD( 4 ); ADD( 5 ); NEXT; // A1 += A3 + A4 + A5 + ADD( 4 ); ADD( 5 ); LAST; // A2 += A4 + A5 + +cleanup: + return( ret ); +} + +#undef WIDTH +#undef A +#undef ADD +#undef NEXT +#undef LAST +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * The reader is advised to first understand ecp_mod_p192() since the same + * general structure is used here, but with additional complications: + * (1) chunks of 32 bits, and (2) subtractions. + */ + +/* + * For these primes, we need to handle data in chunks of 32 bits. + * This makes it more complicated if we use 64 bits limbs in MPI, + * which prevents us from using a uniform access method as for p192. + * + * So, we define a mini abstraction layer to access 32 bit chunks, + * load them in 'cur' for work, and store them back from 'cur' when done. + * + * While at it, also define the size of N in terms of 32-bit chunks. + */ +#define LOAD32 cur = A( i ); + +#if defined(MBEDTLS_HAVE_INT32) /* 32 bit */ + +#define MAX32 N->n +#define A( j ) N->p[j] +#define STORE32 N->p[i] = cur; + +#else /* 64-bit */ + +#define MAX32 N->n * 2 +#define A( j ) (j) % 2 ? (uint32_t)( N->p[(j)/2] >> 32 ) : \ + (uint32_t)( N->p[(j)/2] ) +#define STORE32 \ + if( i % 2 ) { \ + N->p[i/2] &= 0x00000000FFFFFFFF; \ + N->p[i/2] |= ((mbedtls_mpi_uint) cur) << 32; \ + } else { \ + N->p[i/2] &= 0xFFFFFFFF00000000; \ + N->p[i/2] |= (mbedtls_mpi_uint) cur; \ + } + +#endif /* sizeof( mbedtls_mpi_uint ) */ + +/* + * Helpers for addition and subtraction of chunks, with signed carry. + */ +static inline void add32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *dst += src; + *carry += ( *dst < src ); +} + +static inline void sub32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *carry -= ( *dst < src ); + *dst -= src; +} + +#define ADD( j ) add32( &cur, A( j ), &c ); +#define SUB( j ) sub32( &cur, A( j ), &c ); + +/* + * Helpers for the main 'loop' + * (see fix_negative for the motivation of C) + */ +#define INIT( b ) \ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; \ + signed char c = 0, cc; \ + uint32_t cur; \ + size_t i = 0, bits = (b); \ + mbedtls_mpi C; \ + mbedtls_mpi_uint Cp[ (b) / 8 / sizeof( mbedtls_mpi_uint) + 1 ]; \ + \ + C.s = 1; \ + C.n = (b) / 8 / sizeof( mbedtls_mpi_uint) + 1; \ + C.p = Cp; \ + memset( Cp, 0, C.n * sizeof( mbedtls_mpi_uint ) ); \ + \ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, (b) * 2 / 8 / \ + sizeof( mbedtls_mpi_uint ) ) ); \ + LOAD32; + +#define NEXT \ + STORE32; i++; LOAD32; \ + cc = c; c = 0; \ + if( cc < 0 ) \ + sub32( &cur, -cc, &c ); \ + else \ + add32( &cur, cc, &c ); \ + +#define LAST \ + STORE32; i++; \ + cur = c > 0 ? c : 0; STORE32; \ + cur = 0; while( ++i < MAX32 ) { STORE32; } \ + if( c < 0 ) MBEDTLS_MPI_CHK( fix_negative( N, c, &C, bits ) ); + +/* + * If the result is negative, we get it in the form + * c * 2^(bits + 32) + N, with c negative and N positive shorter than 'bits' + */ +static inline int fix_negative( mbedtls_mpi *N, signed char c, mbedtls_mpi *C, size_t bits ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + /* C = - c * 2^(bits + 32) */ +#if !defined(MBEDTLS_HAVE_INT64) + ((void) bits); +#else + if( bits == 224 ) + C->p[ C->n - 1 ] = ((mbedtls_mpi_uint) -c) << 32; + else +#endif + C->p[ C->n - 1 ] = (mbedtls_mpi_uint) -c; + + /* N = - ( C - N ) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, C, N ) ); + N->s = -1; + +cleanup: + + return( ret ); +} + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +/* + * Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) + */ +static int ecp_mod_p224( mbedtls_mpi *N ) +{ + INIT( 224 ); + + SUB( 7 ); SUB( 11 ); NEXT; // A0 += -A7 - A11 + SUB( 8 ); SUB( 12 ); NEXT; // A1 += -A8 - A12 + SUB( 9 ); SUB( 13 ); NEXT; // A2 += -A9 - A13 + SUB( 10 ); ADD( 7 ); ADD( 11 ); NEXT; // A3 += -A10 + A7 + A11 + SUB( 11 ); ADD( 8 ); ADD( 12 ); NEXT; // A4 += -A11 + A8 + A12 + SUB( 12 ); ADD( 9 ); ADD( 13 ); NEXT; // A5 += -A12 + A9 + A13 + SUB( 13 ); ADD( 10 ); LAST; // A6 += -A13 + A10 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +/* + * Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) + */ +static int ecp_mod_p256( mbedtls_mpi *N ) +{ + INIT( 256 ); + + ADD( 8 ); ADD( 9 ); + SUB( 11 ); SUB( 12 ); SUB( 13 ); SUB( 14 ); NEXT; // A0 + + ADD( 9 ); ADD( 10 ); + SUB( 12 ); SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A1 + + ADD( 10 ); ADD( 11 ); + SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A2 + + ADD( 11 ); ADD( 11 ); ADD( 12 ); ADD( 12 ); ADD( 13 ); + SUB( 15 ); SUB( 8 ); SUB( 9 ); NEXT; // A3 + + ADD( 12 ); ADD( 12 ); ADD( 13 ); ADD( 13 ); ADD( 14 ); + SUB( 9 ); SUB( 10 ); NEXT; // A4 + + ADD( 13 ); ADD( 13 ); ADD( 14 ); ADD( 14 ); ADD( 15 ); + SUB( 10 ); SUB( 11 ); NEXT; // A5 + + ADD( 14 ); ADD( 14 ); ADD( 15 ); ADD( 15 ); ADD( 14 ); ADD( 13 ); + SUB( 8 ); SUB( 9 ); NEXT; // A6 + + ADD( 15 ); ADD( 15 ); ADD( 15 ); ADD( 8 ); + SUB( 10 ); SUB( 11 ); SUB( 12 ); SUB( 13 ); LAST; // A7 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * Fast quasi-reduction modulo p384 (FIPS 186-3 D.2.4) + */ +static int ecp_mod_p384( mbedtls_mpi *N ) +{ + INIT( 384 ); + + ADD( 12 ); ADD( 21 ); ADD( 20 ); + SUB( 23 ); NEXT; // A0 + + ADD( 13 ); ADD( 22 ); ADD( 23 ); + SUB( 12 ); SUB( 20 ); NEXT; // A2 + + ADD( 14 ); ADD( 23 ); + SUB( 13 ); SUB( 21 ); NEXT; // A2 + + ADD( 15 ); ADD( 12 ); ADD( 20 ); ADD( 21 ); + SUB( 14 ); SUB( 22 ); SUB( 23 ); NEXT; // A3 + + ADD( 21 ); ADD( 21 ); ADD( 16 ); ADD( 13 ); ADD( 12 ); ADD( 20 ); ADD( 22 ); + SUB( 15 ); SUB( 23 ); SUB( 23 ); NEXT; // A4 + + ADD( 22 ); ADD( 22 ); ADD( 17 ); ADD( 14 ); ADD( 13 ); ADD( 21 ); ADD( 23 ); + SUB( 16 ); NEXT; // A5 + + ADD( 23 ); ADD( 23 ); ADD( 18 ); ADD( 15 ); ADD( 14 ); ADD( 22 ); + SUB( 17 ); NEXT; // A6 + + ADD( 19 ); ADD( 16 ); ADD( 15 ); ADD( 23 ); + SUB( 18 ); NEXT; // A7 + + ADD( 20 ); ADD( 17 ); ADD( 16 ); + SUB( 19 ); NEXT; // A8 + + ADD( 21 ); ADD( 18 ); ADD( 17 ); + SUB( 20 ); NEXT; // A9 + + ADD( 22 ); ADD( 19 ); ADD( 18 ); + SUB( 21 ); NEXT; // A10 + + ADD( 23 ); ADD( 20 ); ADD( 19 ); + SUB( 22 ); LAST; // A11 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#undef A +#undef LOAD32 +#undef STORE32 +#undef MAX32 +#undef INIT +#undef NEXT +#undef LAST + +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED || + MBEDTLS_ECP_DP_SECP256R1_ENABLED || + MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +/* + * Here we have an actual Mersenne prime, so things are more straightforward. + * However, chunks are aligned on a 'weird' boundary (521 bits). + */ + +/* Size of p521 in terms of mbedtls_mpi_uint */ +#define P521_WIDTH ( 521 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* Bits to keep in the most significant mbedtls_mpi_uint */ +#define P521_MASK 0x01FF + +/* + * Fast quasi-reduction modulo p521 (FIPS 186-3 D.2.5) + * Write N as A1 + 2^521 A0, return A0 + A1 + */ +static int ecp_mod_p521( mbedtls_mpi *N ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P521_WIDTH + 1]; + /* Worst case for the size of M is when mbedtls_mpi_uint is 16 bits: + * we need to hold bits 513 to 1056, which is 34 limbs, that is + * P521_WIDTH + 1. Otherwise P521_WIDTH is enough. */ + + if( N->n < P521_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P521_WIDTH - 1 ); + if( M.n > P521_WIDTH + 1 ) + M.n = P521_WIDTH + 1; + M.p = Mp; + memcpy( Mp, N->p + P521_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 521 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + + /* N = A0 */ + N->p[P521_WIDTH - 1] &= P521_MASK; + for( i = P521_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} + +#undef P521_WIDTH +#undef P521_MASK +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + +/* Size of p255 in terms of mbedtls_mpi_uint */ +#define P255_WIDTH ( 255 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* + * Fast quasi-reduction modulo p255 = 2^255 - 19 + * Write N as A0 + 2^255 A1, return A0 + 19 * A1 + */ +static int ecp_mod_p255( mbedtls_mpi *N ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P255_WIDTH + 2]; + + if( N->n < P255_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P255_WIDTH - 1 ); + if( M.n > P255_WIDTH + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + P255_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 255 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + M.n++; /* Make room for multiplication by 19 */ + + /* N = A0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( N, 255, 0 ) ); + for( i = P255_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + 19 * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &M, 19 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + +/* Size of p448 in terms of mbedtls_mpi_uint */ +#define P448_WIDTH ( 448 / 8 / sizeof( mbedtls_mpi_uint ) ) + +/* Number of limbs fully occupied by 2^224 (max), and limbs used by it (min) */ +#define DIV_ROUND_UP( X, Y ) ( ( ( X ) + ( Y ) - 1 ) / ( Y ) ) +#define P224_WIDTH_MIN ( 28 / sizeof( mbedtls_mpi_uint ) ) +#define P224_WIDTH_MAX DIV_ROUND_UP( 28, sizeof( mbedtls_mpi_uint ) ) +#define P224_UNUSED_BITS ( ( P224_WIDTH_MAX * sizeof( mbedtls_mpi_uint ) * 8 ) - 224 ) + +/* + * Fast quasi-reduction modulo p448 = 2^448 - 2^224 - 1 + * Write N as A0 + 2^448 A1 and A1 as B0 + 2^224 B1, and return + * A0 + A1 + B1 + (B0 + B1) * 2^224. This is different to the reference + * implementation of Curve448, which uses its own special 56-bit limbs rather + * than a generic bignum library. We could squeeze some extra speed out on + * 32-bit machines by splitting N up into 32-bit limbs and doing the + * arithmetic using the limbs directly as we do for the NIST primes above, + * but for 64-bit targets it should use half the number of operations if we do + * the reduction with 224-bit limbs, since mpi_add_mpi will then use 64-bit adds. + */ +static int ecp_mod_p448( mbedtls_mpi *N ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i; + mbedtls_mpi M, Q; + mbedtls_mpi_uint Mp[P448_WIDTH + 1], Qp[P448_WIDTH]; + + if( N->n <= P448_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P448_WIDTH ); + if( M.n > P448_WIDTH ) + /* Shouldn't be called with N larger than 2^896! */ + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof( Mp ) ); + memcpy( Mp, N->p + P448_WIDTH, M.n * sizeof( mbedtls_mpi_uint ) ); + + /* N = A0 */ + for( i = P448_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N += A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + + /* Q = B1, N += B1 */ + Q = M; + Q.p = Qp; + memcpy( Qp, Mp, sizeof( Qp ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &Q, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &Q ) ); + + /* M = (B0 + B1) * 2^224, N += M */ + if( sizeof( mbedtls_mpi_uint ) > 4 ) + Mp[P224_WIDTH_MIN] &= ( (mbedtls_mpi_uint)-1 ) >> ( P224_UNUSED_BITS ); + for( i = P224_WIDTH_MAX; i < M.n; ++i ) + Mp[i] = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &M, &M, &Q ) ); + M.n = P448_WIDTH + 1; /* Make room for shifted carry bit from the addition */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &M, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo P = 2^s - R, + * with R about 33 bits, used by the Koblitz curves. + * + * Write N as A0 + 2^224 A1, return A0 + R * A1. + * Actually do two passes, since R is big. + */ +#define P_KOBLITZ_MAX ( 256 / 8 / sizeof( mbedtls_mpi_uint ) ) // Max limbs in P +#define P_KOBLITZ_R ( 8 / sizeof( mbedtls_mpi_uint ) ) // Limbs in R +static inline int ecp_mod_koblitz( mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p_limbs, + size_t adjust, size_t shift, mbedtls_mpi_uint mask ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t i; + mbedtls_mpi M, R; + mbedtls_mpi_uint Mp[P_KOBLITZ_MAX + P_KOBLITZ_R + 1]; + + if( N->n < p_limbs ) + return( 0 ); + + /* Init R */ + R.s = 1; + R.p = Rp; + R.n = P_KOBLITZ_R; + + /* Common setup for M */ + M.s = 1; + M.p = Mp; + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + + /* Second pass */ + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED) || + MBEDTLS_ECP_DP_SECP224K1_ENABLED) || + MBEDTLS_ECP_DP_SECP256K1_ENABLED) */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +/* + * Fast quasi-reduction modulo p192k1 = 2^192 - R, + * with R = 2^32 + 2^12 + 2^8 + 2^7 + 2^6 + 2^3 + 1 = 0x0100001119 + */ +static int ecp_mod_p192k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0xC9, 0x11, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + + return( ecp_mod_koblitz( N, Rp, 192 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +/* + * Fast quasi-reduction modulo p224k1 = 2^224 - R, + * with R = 2^32 + 2^12 + 2^11 + 2^9 + 2^7 + 2^4 + 2 + 1 = 0x0100001A93 + */ +static int ecp_mod_p224k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0x93, 0x1A, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + +#if defined(MBEDTLS_HAVE_INT64) + return( ecp_mod_koblitz( N, Rp, 4, 1, 32, 0xFFFFFFFF ) ); +#else + return( ecp_mod_koblitz( N, Rp, 224 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +#endif +} + +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo p256k1 = 2^256 - R, + * with R = 2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1 = 0x01000003D1 + */ +static int ecp_mod_p256k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0xD1, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + return( ecp_mod_koblitz( N, Rp, 256 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#endif /* MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_helper.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_helper.c new file mode 100644 index 0000000..5a7970b --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_helper.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/threading.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" + +#include + +#if defined(MBEDTLS_ECP_ALT) + +int ecp_helper_deduce_y(const mbedtls_ecp_group *grp, + mbedtls_mpi *y, + const mbedtls_mpi *x) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + mbedtls_mpi A; + mbedtls_mpi B; + mbedtls_mpi xx; // x^2 + mbedtls_mpi yy; // y^2 + mbedtls_mpi T1; // Scratch + mbedtls_mpi T2; // Scratch + mbedtls_mpi T3; // Scratch + mbedtls_mpi T4; // Scratch + + mbedtls_mpi_init(&A); + mbedtls_mpi_init(&B); + mbedtls_mpi_init(&xx); + mbedtls_mpi_init(&yy); + mbedtls_mpi_init(&T1); + mbedtls_mpi_init(&T2); + mbedtls_mpi_init(&T3); + mbedtls_mpi_init(&T4); + + /* ECC curve type */ + mbedtls_ecp_curve_type curve_type = mbedtls_ecp_get_type(grp); + + /* Resolve A */ + if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + /* + * In S/W impl, A is used as (A + 2) / 4. Figure out its original value for engine. + * https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/include/mbedtls/ecp.h#L219-L220 + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_int(&A, &grp->A, 4)); + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(&A, &A, 2)); + } else { + MBEDTLS_MPI_CHK(mbedtls_mpi_copy(&A, &grp->A)); + } + + /* Resolve B */ + if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + /* + * In S/W impl, B is unused. Actually, B is 1 for Curve25519/Curve448. + * https://github.com/ARMmbed/mbed-os/blob/2eb06e76208588afc6cb7580a8dd64c5429a10ce/connectivity/mbedtls/include/mbedtls/ecp.h#L221-L222 + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&B, 1)); + } else { + MBEDTLS_MPI_CHK(mbedtls_mpi_copy(&B, &grp->B)); + } + + /* y^2 = C(x) (mod P) */ + if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + /* Montgomery curve: B y^2 = x^3 + A x^2 + x (mod P) + * For Curve25519/Curve448, B = 1 */ + MBEDTLS_MPI_CHK(mbedtls_mpi_copy(&yy, x)); // yy = x (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&yy, &yy, &grp->P)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&xx, x, x)); // xx = x^2 (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&xx, &xx, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&T1, &A, &xx)); // T1 = A x^2 (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T1, &T1, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_add_mpi(&yy, &T1, &yy)); // yy = A x^2 + x (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&yy, &yy, &grp->P)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&T1, &xx, x)); // T1 = x^3 (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T1, &T1, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_add_mpi(&yy, &T1, &yy)); // yy = x^3 + A x^2 + x (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&yy, &yy, &grp->P)); + } else { + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + goto cleanup; + } + + mbedtls_mpi_uint rmn_4 = 0, rmn_8 = 0; + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_int(&rmn_4, &grp->P, 4)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_int(&rmn_8, &grp->P, 8)); + + /* y = sqrt(y^2) (mod P) */ + if (rmn_8 == 5) { + /* + * Modulus congruent to 5 modulo 8 (Curve25519), apply the formula below: + * https://www.rieselprime.de/ziki/Modular_square_root#Modulus_congruent_to_5_modulo_8 + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(&T1, &grp->P, 5)); // T1 = (P - 5) / 8 (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_div_int(&T1, NULL, &T1, 8)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T1, &T1, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_int(&T2, &yy, 2)); // T2 = 2 y^2 (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T2, &T2, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&T3, &T2, &T1, &grp->P, NULL)); // T3 = T2^T1 (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&T4, &T2, &T3)); // T4 = T2 T3^2 (mod P) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T4, &T4, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(&T4, &T4, &T3)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&T4, &T4, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(y, &T4, 1)); // y = yy T3 (T4 - 1) + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(y, y, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(y, &T3, y)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(y, y, &grp->P)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mul_mpi(y, &yy, y)); + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(y, y, &grp->P)); + } else if (rmn_4 == 3) { + /* + * Modulus congruent to 3 modulo 4 (Curve448), apply the formula below: + * https://www.rieselprime.de/ziki/Modular_square_root#Modulus_congruent_to_3_modulo_4 + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_add_int(&T1, &grp->P, 1)); // T1 = (P + 1) / 4 + MBEDTLS_MPI_CHK(mbedtls_mpi_div_int(&T1, NULL, &T1, 4)); + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(y, &yy, &T1, &grp->P, NULL)); // y = yy^T1 (mod P) + } else { + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + goto cleanup; + } + + /* y = min(y, P - y) */ + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_mpi(&T1, &grp->P, y)); + if (mbedtls_mpi_cmp_mpi(y, &T1) > 0) { + MBEDTLS_MPI_CHK(mbedtls_mpi_copy(y, &T1)); + } + +cleanup: + + mbedtls_mpi_free(&T4); + mbedtls_mpi_free(&T3); + mbedtls_mpi_free(&T2); + mbedtls_mpi_free(&T1); + mbedtls_mpi_free(&yy); + mbedtls_mpi_free(&xx); + mbedtls_mpi_free(&B); + mbedtls_mpi_free(&A); + + return ret; +} + +#endif /* MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_helper.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_helper.h new file mode 100644 index 0000000..6903af4 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_helper.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ECP_HELPER_H +#define ECP_HELPER_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "mbedtls/bignum.h" + +/** + * \brief Check if MPI has been normalized + * + * \param N Input MPI which is to check + * \param P Prime modulus + * + * \return 0 if not normalized, + * 1 if normalized + */ +#define ECP_HELPER_MPI_IS_NORM(N, P) \ + ((mbedtls_mpi_cmp_int(&N, 0) >= 0) && (mbedtls_mpi_cmp_mpi(&N, &P) < 0)) + +/** + * \brief Normalize MPI if it is not normalized yet + * + * \param R Holds pointer to normalized MPI (N1 or N2) + * \param N1 Input MPI which is to normalize + * \param N2 Output MPI which holds normalized N1 if N1 is not normalized yet + * \param P Prime modulus + */ +#define ECP_HELPER_MPI_NORM(R, N1, N2, P) \ + do { \ + if (ECP_HELPER_MPI_IS_NORM(N1, P)) { \ + *R = &N1; \ + } else { \ + MBEDTLS_MPI_CHK(mbedtls_mpi_mod_mpi(&N2, &N1, &P)); \ + *R = &N2; \ + } \ + } while(0) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief This function deduces y coordinate from x coordinate + * for a ECP point expressed in compact representation. + * + * \param grp The ECP group to be exported. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param y Deduced y coordinate which is smaller. The other would be + * \p grp->P - \p y. \p y must point to an initialized MPI. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p grp does not + * designate a Curve25519 or Curve448 curve. + * \return Another negative error code on other kinds of failure. + */ +int ecp_helper_deduce_y(const mbedtls_ecp_group *grp, + mbedtls_mpi *y, + const mbedtls_mpi *x); + +#ifdef __cplusplus +} +#endif + +#endif /* ECP_HELPER_H */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_internal_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_internal_alt.c new file mode 100644 index 0000000..51b99dd --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/ecp/ecp_internal_alt.c @@ -0,0 +1,625 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbedtls/common.h" + +/* Some internal functions are used for Nuvoton internal self-test. + * Remove the static modifier for self-test compile. */ +#if defined(NU_CRYPTO_SELF_TEST) && NU_CRYPTO_SELF_TEST +#define NU_STATIC +#else +#define NU_STATIC static +#endif + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/threading.h" +#include "mbedtls/error.h" + +#include + +#if !defined(MBEDTLS_ECP_ALT) +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + +#include "mbedtls/platform.h" +#include "mbedtls/ecp_internal.h" +#include "mbed_toolchain.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "mbed_toolchain.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" +#include "crypto_ecc_hw.h" +#include "ecp_helper.h" + +/** + * \brief Normalize Jacobian coordinates or Montgomery x/z coordinates, dependent on curve type. + * + * \param grp Pointer to the group representing the curve. + * + * \param pt pointer to the point to be normalized. This is an + * input/output parameter. + * + * \return 0 if successful. + */ +NU_STATIC int internal_ecp_normalize(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt); + +/** + * \note See \c crypto_ecc_run_eccop. + */ +NU_STATIC int internal_run_eccop(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + const mbedtls_mpi *n, + const mbedtls_ecp_point *Q, + uint32_t eccop); + +/** + * \note See \c crypto_ecc_run_modop. + */ +NU_STATIC int internal_run_modop(mbedtls_mpi *r, + const mbedtls_mpi *o1, + const mbedtls_mpi *o2, + const mbedtls_mpi *p, + uint32_t pbits, + uint32_t modop); + +/** + * \note See \c crypto_ecc_mpi_read_eccreg. + */ +NU_STATIC int internal_mpi_read_eccreg( mbedtls_mpi *X, const volatile uint32_t *eccreg, size_t eccreg_num ); + +/** + * \note See \c crypto_ecc_mpi_write_eccreg. + */ +NU_STATIC int internal_mpi_write_eccreg( const mbedtls_mpi *X, volatile uint32_t *eccreg, size_t eccreg_num ); + +unsigned char mbedtls_internal_ecp_grp_capable( const mbedtls_ecp_group *grp ) +{ + /* Curve types + * + * - Short Weierstrass + * - Montgomery + */ + mbedtls_ecp_curve_type curve_type = mbedtls_ecp_get_type(grp); + if (curve_type == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS || + curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + return 1; + } else { + return 0; + } +} + +int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) +{ + return crypto_ecc_init( grp ); +} + +void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) +{ + crypto_ecc_free( grp ); +} + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) +/** + * \brief Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_jac(). + * + * \param grp Pointer to the group representing the curve. + * + * \param pt Pointer to a point structure to randomize. + * + * \param f_rng The RNG function. This may be \c NULL if randomization + * of intermediate results isn't desired (discouraged). + * + * \param p_rng The RNG context to be passed to \p p_rng. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_randomize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi l, ll; + size_t p_size; + int count = 0; + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); mbedtls_mpi_init( &ll ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + /* Z = l * Z */ + MBEDTLS_MPI_CHK(internal_run_modop(&pt->Z, &pt->Z, &l, &grp->P, grp->pbits, MODOP_MUL)); + + /* X = l^2 * X */ + MBEDTLS_MPI_CHK(internal_run_modop(&ll, &l, &l, &grp->P, grp->pbits, MODOP_MUL)); + MBEDTLS_MPI_CHK(internal_run_modop(&pt->X, &pt->X, &ll, &grp->P, grp->pbits, MODOP_MUL)); + + /* Y = l^3 * Y */ + MBEDTLS_MPI_CHK(internal_run_modop(&ll, &ll, &l, &grp->P, grp->pbits, MODOP_MUL)); + MBEDTLS_MPI_CHK(internal_run_modop(&pt->Y, &pt->Y, &ll, &grp->P, grp->pbits, MODOP_MUL)); + +cleanup: + + mbedtls_mpi_free( &l ); + mbedtls_mpi_free( &ll ); + + return ret; +} +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) +/** + * \brief Addition: R = P + Q, mixed affine-Jacobian coordinates. + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * We accept Q->Z being unset (saving memory in tables) as + * meaning 1. + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the first summand, given with Jacobian + * coordinates + * + * \param Q Pointer to the second summand, given with affine + * coordinates. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_add_mixed( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_point P_, Q_; + + mbedtls_ecp_point_init(&P_); + mbedtls_ecp_point_init(&Q_); + + /* P_ = normalized P */ + MBEDTLS_MPI_CHK(mbedtls_ecp_copy(&P_, P)); + MBEDTLS_MPI_CHK(mbedtls_internal_ecp_normalize_jac(grp, &P_)); + + /* Q_ = normalized Q */ + MBEDTLS_MPI_CHK(mbedtls_ecp_copy(&Q_, Q)); + /* NOTE: We accept Q->Z being unset (saving memory in tables) as meaning 1. + * + * Q->Z.p == NULL ==> Q->Z = 1 + * Q->Z.p != NULL && mbedtls_mpi_cmp_int(&Q->Z, 0) == 0 ==> Q->Z = 0 + * Q->Z.p != NULL && mbedtls_mpi_cmp_int(&Q->Z, 0) != 0 ==> Q->Z = 1 + */ + if (Q->Z.p != NULL && mbedtls_mpi_cmp_int(&Q->Z, 0) == 0) { + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&Q_.Z, 0)); + } else { + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&Q_.Z, 1)); + } + + /* Run ECC point addition: R = P + Q */ + MBEDTLS_MPI_CHK(internal_run_eccop(grp, R, NULL, &P_, NULL, &Q_, ECCOP_POINT_ADD)); + +cleanup: + + mbedtls_ecp_point_free(&Q_); + mbedtls_ecp_point_free(&P_); + + return ret; +} +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) +/** + * \brief Point doubling R = 2 P, Jacobian coordinates. + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the point that has to be doubled, given with + * Jacobian coordinates. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_double_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, const mbedtls_ecp_point *P ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_point P_; + + mbedtls_ecp_point_init(&P_); + + /* P_ = normalized P */ + MBEDTLS_MPI_CHK(mbedtls_ecp_copy(&P_, P)); + MBEDTLS_MPI_CHK(mbedtls_internal_ecp_normalize_jac(grp, &P_)); + + /* Run ECC point doubling: R = 2*P */ + MBEDTLS_MPI_CHK(internal_run_eccop(grp, R, NULL, &P_, NULL, NULL, ECCOP_POINT_DOUBLE)); + +cleanup: + + mbedtls_ecp_point_free(&P_); + + return ret; +} +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) +/** + * \brief Normalize jacobian coordinates so that Z == 0 || Z == 1. + * + * \param grp Pointer to the group representing the curve. + * + * \param pt pointer to the point to be normalised. This is an + * input/output parameter. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_normalize_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt ) +{ + if (grp == NULL || pt == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Is a zero point + * + * Z = 0 + */ + if (mbedtls_mpi_cmp_int(&pt->Z, 0) == 0) { + return 0; + } + + /* Is a non-zero point which has been normalized + * + * Z = 1 + * 0 <= X < P + * 0 <= y < P + */ + if (mbedtls_mpi_cmp_int(&pt->Z, 1) == 0 && + mbedtls_mpi_cmp_int(&pt->X, 0) >= 0 && + mbedtls_mpi_cmp_mpi(&pt->X, &grp->P) < 0 && + mbedtls_mpi_cmp_int(&pt->Y, 0) >= 0 && + mbedtls_mpi_cmp_mpi(&pt->Y, &grp->P) < 0) { + return 0; + } + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi N, Zi, ZZi; + const mbedtls_mpi *Np; + + mbedtls_mpi_init(&N); + mbedtls_mpi_init(&Zi); + mbedtls_mpi_init(&ZZi); + + /* Use ECP_HELPER_MPI_NORM(Np, N1, N_, P) to get normalized MPI + * + * N_: Holds normalized MPI if the passed-in MPI N1 is not + * Np: Pointer to normalized MPI, which could be N1 or N_ + */ + + /* Zi = 1 / Z */ + mbedtls_mpi_lset(&Zi, 1); + ECP_HELPER_MPI_NORM(&Np, pt->Z, N, grp->P); + MBEDTLS_MPI_CHK(internal_run_modop(&Zi, &Zi, Np, &grp->P, grp->pbits, MODOP_DIV)); + + /* ZZi = 1 / Z^2 = Zi * Zi */ + MBEDTLS_MPI_CHK(internal_run_modop(&ZZi, &Zi, &Zi, &grp->P, grp->pbits, MODOP_MUL)); + + /* X = X / Z^2 = X * ZZi */ + ECP_HELPER_MPI_NORM(&Np, pt->X, N, grp->P); + MBEDTLS_MPI_CHK(internal_run_modop(&pt->X, Np, &ZZi, &grp->P, grp->pbits, MODOP_MUL)); + + /* Y = Y / Z^3 = Y * ZZi * Zi */ + ECP_HELPER_MPI_NORM(&Np, pt->Y, N, grp->P); + MBEDTLS_MPI_CHK(internal_run_modop(&pt->Y, Np, &ZZi, &grp->P, grp->pbits, MODOP_MUL)); + MBEDTLS_MPI_CHK(internal_run_modop(&pt->Y, &pt->Y, &Zi, &grp->P, grp->pbits, MODOP_MUL)); + + /* Z = 1 */ + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&pt->Z, 1)); + +cleanup: + + mbedtls_mpi_free(&ZZi); + mbedtls_mpi_free(&Zi); + mbedtls_mpi_free(&N); + + return ret; +} +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) +/** + * \brief Normalize jacobian coordinates of an array of (pointers to) + * points. + * + * \param grp Pointer to the group representing the curve. + * + * \param T Array of pointers to the points to normalise. + * + * \param t_len Number of elements in the array. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_normalize_jac_many(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], size_t t_len) +{ + if (T == NULL || t_len == 0) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + mbedtls_ecp_point **ecp_point = T; + mbedtls_ecp_point **ecp_point_end = T + t_len; + + for (; ecp_point != ecp_point_end; ecp_point ++) { + MBEDTLS_MPI_CHK(mbedtls_internal_ecp_normalize_jac(grp, *ecp_point)); + } + +cleanup: + + return ret; +} +#endif + +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) +/** + * \brief Double-and-add: R = 2P, S = P + Q, with d = X(P - Q), + * for Montgomery curves in x/z coordinates. + * + * http://www.hyperelliptic.org/EFD/g1p/auto-code/montgom/xz/ladder/mladd-1987-m.op3 + * with + * d = X1 + * P = (X2, Z2) + * Q = (X3, Z3) + * R = (X4, Z4) + * S = (X5, Z5) + * and eliminating temporary variables tO, ..., t4. + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result of 2P. + * + * \param S Pointer to a point structure to hold the result of P + Q. + * + * \param P Pointer to a point structure for P + Q and 2P, given with Jacobian + * coordinates + * + * \param Q Pointer to a point structure for P + Q, given with affine + * coordinates. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_double_add_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, mbedtls_ecp_point *S, const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d ) +{ + /* Mbed TLS's implementation for Montgomery curve has optimized and + * becomes incompatible with ECC H/W, for example, on mbedtls_mpi A/B. */ + #error "Incompatible with ECC HW. Undefine MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT in mbedtls_device.h" +} +#endif + +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) +/** + * \brief Randomize projective x/z coordinates: + * (X, Z) -> (l X, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_mxz(). + * + * \param grp Pointer to the group representing the curve. + * + * \param P Pointer to a point structure to randomize. + * + * \param f_rng The RNG function. This may be \c NULL if randomization + * of intermediate results isn't desired (discouraged). + * + * \param p_rng The RNG context to be passed to \p p_rng. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_randomize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi l; + size_t p_size; + int count = 0; + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + { + ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; + goto cleanup; + } + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + /* X = l * X */ + MBEDTLS_MPI_CHK(internal_run_modop(&P->X, &P->X, &l, &grp->P, grp->pbits, MODOP_MUL)); + + /* Z = l * Z */ + MBEDTLS_MPI_CHK(internal_run_modop(&P->Z, &P->Z, &l, &grp->P, grp->pbits, MODOP_MUL)); + +cleanup: + + mbedtls_mpi_free( &l ); + + return( ret ); +} +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) +/** + * \brief Normalize Montgomery x/z coordinates: X = X/Z, Z = 1. + * + * \param grp pointer to the group representing the curve + * + * \param P pointer to the point to be normalised. This is an + * input/output parameter. + * + * \return 0 if successful + */ +int mbedtls_internal_ecp_normalize_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt ) +{ + if (grp == NULL || pt == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + /* Is a zero point + * + * Z = 0 + */ + if (mbedtls_mpi_cmp_int(&pt->Z, 0) == 0) { + return 0; + } + + /* Is a non-zero point which has been normalized + * + * Z = 1 + * 0 <= X < P + * + * NOTE: Y not used + */ + if (mbedtls_mpi_cmp_int(&pt->Z, 1) == 0 && + mbedtls_mpi_cmp_int(&pt->X, 0) >= 0 && + mbedtls_mpi_cmp_mpi(&pt->X, &grp->P) < 0) { + return 0; + } + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi N, Zi; + const mbedtls_mpi *Np; + + mbedtls_mpi_init(&N); + mbedtls_mpi_init(&Zi); + + /* Use ECP_HELPER_MPI_NORM(Np, N1, N_, P) to get normalized MPI + * + * N_: Holds normalized MPI if the passed-in MPI N1 is not + * Np: Pointer to normalized MPI, which could be N1 or N_ + */ + + /* Zi = 1 / Z */ + mbedtls_mpi_lset(&Zi, 1); + ECP_HELPER_MPI_NORM(&Np, pt->Z, N, grp->P); + MBEDTLS_MPI_CHK(internal_run_modop(&Zi, &Zi, Np, &grp->P, grp->pbits, MODOP_DIV)); + + /* X = X / Z = X * Zi */ + ECP_HELPER_MPI_NORM(&Np, pt->X, N, grp->P); + MBEDTLS_MPI_CHK(internal_run_modop(&pt->X, Np, &Zi, &grp->P, grp->pbits, MODOP_MUL)); + + /* Z = 1 */ + MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&pt->Z, 1)); + +cleanup: + + mbedtls_mpi_free(&Zi); + mbedtls_mpi_free(&N); + + return ret; +} +#endif + +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + +NU_STATIC int internal_ecp_normalize(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt) +{ + mbedtls_ecp_curve_type curve_type = mbedtls_ecp_get_type(grp); + if (curve_type == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS) { + return mbedtls_internal_ecp_normalize_jac(grp, pt); + } else if (curve_type == MBEDTLS_ECP_TYPE_MONTGOMERY) { + return mbedtls_internal_ecp_normalize_mxz(grp, pt); + } else { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +} + +NU_STATIC int internal_run_eccop(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + const mbedtls_mpi *n, + const mbedtls_ecp_point *Q, + uint32_t eccop) +{ + return crypto_ecc_run_eccop( grp, R, m, P, n, Q, eccop, false ); +} + +NU_STATIC int internal_run_modop(mbedtls_mpi *r, + const mbedtls_mpi *o1, + const mbedtls_mpi *o2, + const mbedtls_mpi *p, + uint32_t pbits, + uint32_t modop) +{ + return crypto_ecc_run_modop( r, o1, o2, p, pbits, modop ); +} + +NU_STATIC int internal_mpi_read_eccreg(mbedtls_mpi *x, const volatile uint32_t *eccreg, size_t eccreg_num) +{ + return crypto_ecc_mpi_read_eccreg( x, eccreg, eccreg_num); +} + +NU_STATIC int internal_mpi_write_eccreg( const mbedtls_mpi *x, volatile uint32_t *eccreg, size_t eccreg_num ) +{ + return crypto_ecc_mpi_write_eccreg( x, eccreg, eccreg_num ); +} + +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ +#endif /* ! MBEDTLS_ECP_ALT */ +#endif /* MBEDTLS_ECP_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/gcm/gcm_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/gcm/gcm_alt.c new file mode 100644 index 0000000..6385ca2 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/gcm/gcm_alt.c @@ -0,0 +1,1131 @@ +/* + * NIST SP800-38D compliant GCM implementation + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2022, Nuvoton Technology Corp., All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +/* + * http://csrc.nist.gov/publications/nistpubs/800-38D/SP-800-38D.pdf + * + * See also: + * [MGV] http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf + * + * We use the algorithm described as Shoup's method with 4-bit tables in + * [MGV] 4.1, pp. 12-13, to enhance speed without using too much memory. + */ + + +#include "common.h" + + +#if defined(MBEDTLS_GCM_C) + +#include "mbedtls/gcm.h" +#include "mbedtls/platform_util.h" + +#include + +#if defined(MBEDTLS_AESNI_C) +#include "config.h" +#endif + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#if !defined(MBEDTLS_PLATFORM_C) +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_C */ +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + + +#if defined(MBEDTLS_GCM_ALT) + +#include "M460.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" + +/* Parameter validation macros */ +#define GCM_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_GCM_BAD_INPUT ) +#define GCM_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + + +#define START CRPT_AES_CTL_START_Msk +#define DMAEN CRPT_AES_CTL_DMAEN_Msk +#define DMALAST CRPT_AES_CTL_DMALAST_Msk +#define DMACC CRPT_AES_CTL_DMACSCAD_Msk +#define START CRPT_AES_CTL_START_Msk +#define FBIN CRPT_AES_CTL_FBIN_Msk +#define FBOUT CRPT_AES_CTL_FBOUT_Msk + +#define GCM_MODE (AES_MODE_GCM << CRPT_AES_CTL_OPMODE_Pos) +#define GHASH_MODE (AES_MODE_GHASH << CRPT_AES_CTL_OPMODE_Pos) +#define CTR_MODE (AES_MODE_CTR << CRPT_AES_CTL_OPMODE_Pos) + +#define Debug_GCM_Info(x) {} +//#define Debug_GCM_Info(x) { printf x; } + +/* + * Initialize a context + */ +void mbedtls_gcm_init( mbedtls_gcm_context *ctx ) +{ + GCM_VALIDATE( ctx != NULL ); + memset( ctx, 0, sizeof( mbedtls_gcm_context ) ); + + /* Init crypto module including Reset Crypto */ + crypto_init(); + +} + +void mbedtls_gcm_free( mbedtls_gcm_context *ctx ) +{ + if( ctx == NULL ) + return; + + /* Uninit crypto module */ + crypto_uninit(); + mbedtls_platform_zeroize( ctx, sizeof( mbedtls_gcm_context ) ); +} + +static int32_t ToBigEndian(uint8_t *pbuf, uint32_t u32Size) +{ + uint32_t i; + uint8_t u8Tmp; + uint32_t u32Tmp; + + /* pbuf must be word alignment */ + if((uint32_t)pbuf & 0x3) + { + /* The buffer must be 32-bit alignment. */ + return -1; + } + + while(u32Size >= 4) + { + u8Tmp = *pbuf; + *(pbuf) = *(pbuf + 3); + *(pbuf + 3) = u8Tmp; + + u8Tmp = *(pbuf + 1); + *(pbuf + 1) = *(pbuf + 2); + *(pbuf + 2) = u8Tmp; + + u32Size -= 4; + pbuf += 4; + } + + if(u32Size > 0) + { + u32Tmp = 0; + for(i = 0; i < u32Size; i++) + { + u32Tmp |= *(pbuf + i) << (24 - i * 8); + } + + *((uint32_t *)pbuf) = u32Tmp; + } + + return 0; +} + + + +int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ) +{ + + int32_t i, klen; + uint32_t keySizeOpt; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( key != NULL ); + GCM_VALIDATE_RET( keybits == 128 || keybits == 192 || keybits == 256 ); + + klen = keybits / 8; + ctx->keySize = klen; + + memcpy(ctx->keys, key, klen); + ToBigEndian((uint8_t *)ctx->keys, klen); + + /* Prepare key size option */ + i = klen >> 3; + keySizeOpt = (((i >> 2) << 1) | (i & 1)) << CRPT_AES_CTL_KEYSZ_Pos; + + /* Basic options for AES */ + ctx->basicOpt = CRPT_AES_CTL_INSWAP_Msk | + CRPT_AES_CTL_OUTSWAP_Msk | + CRPT_AES_CTL_DMAEN_Msk | + GCM_MODE | + keySizeOpt; + + return( 0 ); +} + + +#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff) +static void swap64(uint8_t *p) +{ + uint8_t tmp; + int32_t i; + + for(i = 0; i < 4; i++) + { + tmp = p[i]; + p[i] = p[7 - i]; + p[7 - i] = tmp; + } +} + + +/* +NOTE: pbuf must be word alignment + + GCM input format must be block alignment. The block size is 16 bytes. + {IV}{IV nbits}{A}{P/C} + + +*/ + +int32_t AES_GCMPacker(const uint8_t *iv, uint32_t iv_len, const uint8_t *A, uint32_t A_len, const uint8_t *P, uint32_t P_len, uint8_t *pbuf, uint32_t *psize) +{ + uint32_t i; + uint32_t iv_len_aligned, A_len_aligned, P_len_aligned; + uint32_t u32Offset = 0; + uint8_t *pu8; + + /* IV Section: + + if bitlen(IV) == 96 + IV section = IV || 31'bit 0 || 1 + + if bitlen(IV) != 96 + IV section = 128'align(IV) || 64'bit 0 || 64'bitlen(IV) + */ + if(iv_len > 0) + { + iv_len_aligned = iv_len; + if(iv_len & 0xful) + iv_len_aligned = ((iv_len + 16) >> 4) << 4; + + /* fill iv to output */ + for(i = 0; i < iv_len_aligned; i++) + { + if(i < iv_len) + pbuf[i] = iv[i]; + else + pbuf[i] = 0; // padding zero + } + + /* fill iv len to putput */ + if(iv_len == 12) + { + pbuf[15] = 1; + u32Offset += iv_len_aligned; + } + else + { + /* Padding zero. 64'bit 0 */ + memset(&pbuf[iv_len_aligned], 0, 8); + + /* 64'bitlen(IV) */ + pu8 = &pbuf[iv_len_aligned + 8]; + *((uint64_t *)pu8) = iv_len * 8; + swap64(pu8); + u32Offset += iv_len_aligned + 16; + } + } + + + /* A Section = 128'align(A) */ + if(A_len > 0) + { + A_len_aligned = A_len; + if(A_len & 0xful) + A_len_aligned = ((A_len + 16) >> 4) << 4; + + for(i = 0; i < A_len_aligned; i++) + { + if(i < A_len) + pbuf[u32Offset + i] = A[i]; + else + pbuf[u32Offset + i] = 0; // padding zero + } + + u32Offset += A_len_aligned; + } + + /* P/C Section = 128'align(P/C) */ + if(P_len > 0) + { + P_len_aligned = P_len; + if(P_len & 0xful) + P_len_aligned = ((P_len + 16) >> 4) << 4; + + for(i = 0; i < P_len_aligned; i++) + { + if(i < P_len) + pbuf[u32Offset + i] = P[i]; + else + pbuf[u32Offset + i] = 0; // padding zero + } + u32Offset += P_len_aligned; + } + + *psize = u32Offset; + + return 0; +} + + +static int32_t AES_Run(mbedtls_gcm_context *ctx, uint32_t u32Option) +{ + int32_t i, klen; + bool ret; + + klen = ctx->keySize; + + /* Set AES Key into H/W */ + for( i = 0; i < klen / 4; i++) + { + CRPT->AES_KEY[i] = ctx->keys[i]; + } + + crypto_aes_prestart(); + CRPT->AES_CTL = u32Option | START; + ret = crypto_aes_wait(); + if( ret == false ) + { + printf("###[WARN] AES GCM got NU_CRYPTO_DONE_ERR \n"); + } + + return 0; +} + + +#if 0 +static void dump(char* buf, int size, char* str) +{ + int i; + printf("\r\n%s:", str); + for(i = 0; i < size; i++) + { + if((i % 16) == 0) + printf("\r\n"); + printf("%02x ", buf[i]); + } + printf("\r\n"); + +} +#endif + + + +int mbedtls_gcm_starts( mbedtls_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len ) +{ + + + uint32_t size; + size_t *pSz; + int32_t ret; + + if( ctx-> pcntLen == 0 ) ctx-> pcntLen = -1; + ctx->len= 0x00; + + Debug_GCM_Info(("## FUNC: %s, mode=%s, pcnt=%d, ctx->len=%d\n", __FUNCTION__, (mode) ? "Enc":"Dec", ctx-> pcntLen, ctx->len)); + /* Acquire ownership of AES H/W */ + crypto_aes_acquire(); + +#if 1 + /* Force AES free */ + CRPT->AES_CTL = CRPT_AES_CTL_STOP_Msk; +#endif + + AES_ENABLE_INT(CRPT); + + if(mode == MBEDTLS_GCM_ENCRYPT) + { + ctx->basicOpt |= CRPT_AES_CTL_ENCRPT_Msk; + } + else + { + ctx->basicOpt &= ~CRPT_AES_CTL_ENCRPT_Msk; + } + /* Set byte count of IV */ + pSz = (size_t *)CRPT->AES_GCM_IVCNT; + *pSz = iv_len; + /* Set bytes count of A */ + pSz = (size_t *)CRPT->AES_GCM_ACNT; + *pSz = add_len; + + AES_GCMPacker(iv, iv_len, add, add_len, 0, 0, ctx->gcm_buf, &size); + ctx->gcm_buf_bytes = size; + + /* Configure DMA */ + CRPT->AES_SADDR = (uint32_t)ctx->gcm_buf; + CRPT->AES_DADDR = (uint32_t)ctx->out_buf; + CRPT->AES_FBADDR = (uint32_t)ctx->fb_buf; + CRPT->AES_CNT = ctx->gcm_buf_bytes; + + /* Set a big number for unknown P length */ + CRPT->AES_GCM_PCNT[0] = ctx-> pcntLen; //(uint32_t)-1; + CRPT->AES_GCM_PCNT[1] = 0; + + /* Start with cascade mode */ +// if((ret = AES_Run(ctx, ctx->basicOpt | FBOUT))) + if((ret = AES_Run(ctx, ctx->basicOpt | GCM_MODE | FBOUT | DMAEN))) + { + return ret; + } + + ctx->firstFlag = 1; + ctx->endFlag = 0; + + return( 0 ); +} + + + +int mbedtls_gcm_update( mbedtls_gcm_context *ctx, + size_t input_length, + const unsigned char *input, + unsigned char *output ) +{ + + + int32_t ret; + int32_t len, len_aligned; + uint32_t u32Size; + Debug_GCM_Info(("## FUNC: %s, input_length=%d\n", __FUNCTION__, input_length)); + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( input_length == 0 || input != NULL ); + GCM_VALIDATE_RET( input_length == 0 || output != NULL ); + + len = (int32_t)input_length; + /* Error if length too large */ + if( (size_t)len != input_length) + return( MBEDTLS_ERR_GCM_BAD_INPUT ); + + + len_aligned = (len & 0xf) ? (int32_t)(len & (~0xful))+16:len; + + if(len == 0) + { + CRPT->AES_GCM_PCNT[0] = ctx->len; + CRPT->AES_CNT = ctx->gcm_buf_bytes; + if(ctx->firstFlag == 1) + { + /* No any P/C data, just use one shot to redo */ + AES_Run(ctx, ctx->basicOpt); + ctx->gcm_buf_bytes = 0; + + /* The tag should be in out_buf if P len is 0 */ + memcpy(ctx->tag, ctx->out_buf, 16); + ctx->endFlag = 1; + ctx->firstFlag = 0; + + } + else + { + /* zero block, it should be end of gcm. Restore feedback buffer and do GCM again with last cascade */ + memcpy(ctx->fb_buf, ctx->fb_buf2, 72); + CRPT->AES_GCM_PCNT[0] = ctx->len; + if((ret = AES_Run(ctx, ctx->basicOpt | FBIN | FBOUT | DMACC | DMALAST))) + { + return ret; + } + ctx->gcm_buf_bytes = 0; + ctx->endFlag = 1; + + /* Output p/c data */ + memcpy(output, ctx->out_buf, len); + + /* Output tag */ + memcpy(ctx->tag, ctx->out_buf+len_aligned, 16); + } + } + else + { + if(len <= MAX_GCM_BUF) + { + AES_GCMPacker(0, 0, 0, 0, input, len, ctx->gcm_buf, &u32Size); + ctx->len += len; + ctx->gcm_buf_bytes = u32Size; + } + else + { + + /* Over buffer size */ + return (MBEDTLS_ERR_GCM_BAD_INPUT); + } + + /* Do GCM with cascade */ + if(len & 0xf) + { + /* No 16 bytes alignment, it should be last */ + + CRPT->AES_GCM_PCNT[0] = ctx->len; + CRPT->AES_GCM_PCNT[1] = 0; + CRPT->AES_CNT = u32Size; + + if((ret = AES_Run(ctx, ctx->basicOpt | FBIN | FBOUT | DMACC | DMALAST))) + { + return ret; + } + ctx->endFlag = 1; + } + else + { + /* backup feedback buffer. If this is last block, we could back feedback buffer to do it again. */ + memcpy(ctx->fb_buf2, ctx->fb_buf, 72); +// ctx->firstFlag = 0; + CRPT->AES_CNT = u32Size; + + if((ret = AES_Run(ctx, ctx->basicOpt | FBIN | FBOUT | DMACC))) + { + return ret; + } + + } + + /* Output p/c data */ + memcpy(output, ctx->out_buf, len); + + if(ctx->endFlag) + { + /* Output tag */ + memcpy(ctx->tag, ctx->out_buf+len_aligned, 16); + } + } + + return( 0 ); +} + + +int mbedtls_gcm_finish( mbedtls_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ) +{ + + int32_t ret = 0; + Debug_GCM_Info(("## FUNC: %s, tag_len=%d, pcnt=%d\n", __FUNCTION__, tag_len, ctx->len)); + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + + if(ctx->endFlag == 0) + { + /* end the gcm */ + CRPT->AES_GCM_PCNT[0] = ctx->len; + memcpy(ctx->fb_buf, ctx->fb_buf2, 72); + if((ret = AES_Run(ctx, ctx->basicOpt | FBIN | FBOUT | DMACC | DMALAST))) + { + goto gcm_exit; + } + ctx->endFlag = 1; + + /* The tag should be in out_buf if P len is 0 */ + + memcpy(ctx->tag, ctx->out_buf+ctx->gcm_buf_bytes, 16); + } + + + if(tag_len > 16) + { + tag_len = 16; + } + memcpy(tag, ctx->tag, tag_len); + +gcm_exit: + /* Release ownership of AES H/W */ + crypto_aes_release(); + + return( ret ); +} + + +//#define NVT_GCM_USE_GHASH_CTR_MODE + +#ifndef NVT_GCM_USE_GHASH_CTR_MODE +/* +* Apply GCM mode only for Decrypt, Encrypt & Tag +*/ +int mbedtls_gcm_crypt_and_tag( mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ) +{ + int32_t plen_cur; + int32_t len, len_aligned; + const uint8_t *pin; + uint8_t *pout; + + int ret = MBEDTLS_ERR_GCM_AUTH_FAILED; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( iv != NULL ); + GCM_VALIDATE_RET( add_len == 0 || add != NULL ); + GCM_VALIDATE_RET( length == 0 || input != NULL ); + GCM_VALIDATE_RET( length == 0 || output != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + ctx-> pcntLen = length; + if( ( ret = mbedtls_gcm_starts( ctx, mode, iv, iv_len, add, add_len ) ) != 0 ) + return( ret ); + + if( length == 0 ) /* if P length > 0, mbedtls_gcm_update not need gcm_buf_bytes for AES_CNT */ + { + ctx->gcm_buf_bytes = 16; + }else{ + ctx->gcm_buf_bytes = 0; + } + plen_cur = length; + pin = input; + pout = output; + do + { + len = plen_cur; + if(len > GCM_PBLOCK_SIZE) + { + len = GCM_PBLOCK_SIZE; + } + plen_cur -= len; + + /* Prepare the blocked buffer for GCM */ + memcpy(ctx->gcm_buf, pin, len); + + if( ( ret = mbedtls_gcm_update( ctx, len, pin, pout ) ) != 0 ) + return( ret ); + pin += len; + pout += len; + }while(plen_cur); + + if( ( ret = mbedtls_gcm_finish( ctx, tag, tag_len ) ) != 0 ) + return( ret ); + + return( 0 ); +} + +int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ) +{ + int ret = MBEDTLS_ERR_GCM_AUTH_FAILED; + unsigned char check_tag[16]; + size_t i; + int diff; + + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( iv != NULL ); + GCM_VALIDATE_RET( add_len == 0 || add != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + GCM_VALIDATE_RET( length == 0 || input != NULL ); + GCM_VALIDATE_RET( length == 0 || output != NULL ); + + if( ( ret = mbedtls_gcm_crypt_and_tag( ctx, MBEDTLS_GCM_DECRYPT, length, + iv, iv_len, add, add_len, + input, output, tag_len, check_tag ) ) != 0 ) + { + return( ret ); + } + + /* Check tag in "constant-time" */ + for( diff = 0, i = 0; i < tag_len; i++ ) + diff |= tag[i] ^ check_tag[i]; + + if( diff != 0 ) + { + mbedtls_platform_zeroize( output, length ); + return( MBEDTLS_ERR_GCM_AUTH_FAILED ); + } + + return( 0 ); +} + +#else /* NVT_GCM_USE_GHASH_CTR_MODE */ + +/* +* Apply GHASH & CTR mode for Tag calculation @GCMEnc +*/ +/* + AES_GCMTag is only used by AES_GCMEnc to calculate tag. +*/ +static int32_t _GCMTag(mbedtls_gcm_context *ctx, const uint8_t *iv, uint32_t ivlen, const uint8_t *A, uint32_t alen, const uint8_t *P, uint32_t plen, uint8_t *tagbuf) +{ + int32_t ret; + int32_t i, len, plen_cur; + const uint8_t *pin; + uint8_t *pout; + uint32_t inputblock[MAX_GCM_BUF * 2] = {0}; /* 2 block buffer, 1 for A, 1 for P */ + uint32_t ghashbuf[MAX_GCM_BUF + 16] = {0}; + uint8_t *pblock; + uint32_t u32OptBasic; + uint32_t u32OptKeySize; + uint32_t tag[4]; + + Debug_GCM_Info(("## FUNC: %s\n", __FUNCTION__)); + /* Prepare key size option */ + i = ctx->keySize >> 3; + u32OptKeySize = (((i >> 2) << 1) | (i & 1)) << CRPT_AES_CTL_KEYSZ_Pos; + + /* Basic options for AES */ + u32OptBasic = CRPT_AES_CTL_ENCRPT_Msk | CRPT_AES_CTL_INSWAP_Msk | CRPT_AES_CTL_OUTSWAP_Msk | u32OptKeySize; + + /* Set byte count of IV */ + CRPT->AES_GCM_IVCNT[0] = ivlen; + CRPT->AES_GCM_IVCNT[1] = 0; + /* Set bytes count of A */ + CRPT->AES_GCM_ACNT[0] = alen; + CRPT->AES_GCM_ACNT[1] = 0; + /* Set bytes count of P */ + CRPT->AES_GCM_PCNT[0] = plen; + CRPT->AES_GCM_PCNT[1] = 0; + + + // GHASH(128'align(A) || 128'align(C) || 64'bitlen(A) || 64'bitlen(C)) + // GHASH Calculation + if(plen <= GCM_PBLOCK_SIZE) + { + /* Just one shot if plen < maximum block size */ + + pblock = (uint8_t *)&inputblock[0]; + AES_GCMPacker(0, 0, A, alen, P, plen, pblock, (uint32_t *)&len); + + /* append 64'bitlen(A) || 64'bitlen(C) */ + pblock += len; + *((uint64_t *)pblock) = alen * 8; + swap64(pblock); + pblock += 8; + + *((uint64_t *)pblock) = plen * 8; + swap64(pblock); + pblock += 8; + + /* adding the length of 64'bitlen(A) and 64'bitlen(C) */ + len += 16; + + pblock = (uint8_t *)&inputblock[0]; + + CRPT->AES_SADDR = (uint32_t)pblock; + CRPT->AES_DADDR = (uint32_t)&ghashbuf[0]; + CRPT->AES_CNT = len; + + AES_Run(ctx, u32OptBasic | GHASH_MODE | DMAEN /*| DMALAST*/); + } + else + { + /* Calculate GHASH block by block, DMA casecade mode */ + + /* feedback buffer is necessary for casecade mode */ + CRPT->AES_FBADDR = (uint32_t)ctx->fb_buf; + memset(ctx->fb_buf, 0, sizeof(ctx->fb_buf)); + + /* inital DMA for GHASH casecade */ + if(alen) + { + /* Prepare the blocked buffer for GCM */ + AES_GCMPacker(0, 0, A, alen, 0, 0, ctx->gcm_buf, (uint32_t *)&len); + + CRPT->AES_SADDR = (uint32_t)ctx->gcm_buf; + CRPT->AES_DADDR = (uint32_t)&ghashbuf[0]; + CRPT->AES_CNT = len; + + AES_Run(ctx, u32OptBasic | GHASH_MODE | FBOUT | DMAEN); + } + + /* Calculate GHASH block by block */ + pin = P; + pout = (uint8_t *)&ghashbuf[0]; + plen_cur = plen; + len = GCM_PBLOCK_SIZE; + while(plen_cur) + { + + len = plen_cur; + if(len > GCM_PBLOCK_SIZE) + len = GCM_PBLOCK_SIZE; + plen_cur -= len; + + if(plen_cur) + { + /* Sill has data for next block, it means current block size is full size */ + + /* len should be alway 16 bytes alignment in here */ + CRPT->AES_SADDR = (uint32_t)pin; + CRPT->AES_DADDR = (uint32_t)pout; + CRPT->AES_CNT = len; + + AES_Run(ctx, u32OptBasic | GHASH_MODE | FBIN | FBOUT | DMAEN | DMACC); + } + else + { + /* Next block data size is 0, it means current block size is not full size and this is last block */ + + /* copy last C data to inputblock for zero padding */ + memcpy((uint8_t *)&inputblock[0], pin, len); + pin = (uint8_t *)&inputblock[0]; + + /* 16 bytes alignment check */ + if(len & 0xf) + { + /* zero padding */ + memset((void *)(pin + len), 0, 16 - (len & 0xf)); + + /* len must be 16 bytes alignment */ + len = ((len + 16) >> 4) << 4; + } + + /* append 64'bitlen(A) || 64'bitlen(C) */ + pblock = (uint8_t *)pin + len; + *((uint64_t *)pblock) = alen * 8; + swap64(pblock); + pblock += 8; + + *((uint64_t *)pblock) = plen * 8; + swap64(pblock); + pblock += 8; + + /* adding the length of 64'bitlen(A) and 64'bitlen(C) */ + len += 16; + + CRPT->AES_SADDR = (uint32_t)pin; + CRPT->AES_DADDR = (uint32_t)pout; + CRPT->AES_CNT = len; + + AES_Run(ctx, u32OptBasic | GHASH_MODE | FBIN | FBOUT | DMAEN | DMACC | DMALAST); + + } + + pin += len; + } + } + + // CTR(IV, GHASH(128'align(A) || 128'align(C) || 64'bitlen(A) || 64'bitlen(C))) + // CTR calculation + + /* Prepare IV */ + if(ivlen != 12) + { + uint32_t u32ivbuf[4] = {0}; + uint8_t *piv; + + // IV = GHASH(128'align(IV) || 64'bitlen(0) || 64'bitlen(IV)) + + piv = (uint8_t *)&u32ivbuf[0]; + AES_GCMPacker(iv, ivlen, 0, 0, 0, 0, ctx->gcm_buf, (uint32_t *)&len); + + CRPT->AES_SADDR = (uint32_t)ctx->gcm_buf; + CRPT->AES_DADDR = (uint32_t)piv; + CRPT->AES_CNT = len; + + if((ret = AES_Run(ctx, u32OptBasic | GHASH_MODE | DMAEN/* | DMALAST*/))) + { + return ret; + } + + /* SET CTR IV */ + for(i = 0; i < 4; i++) + { + CRPT->AES_IV[i] = (piv[i * 4 + 0] << 24) | (piv[i * 4 + 1] << 16) | + (piv[i * 4 + 2] << 8) | piv[i * 4 + 3]; + } + } + else + { + // IV = 128'align(IV) || 31'bitlen(0) || 1 + + /* SET CTR IV */ + for(i = 0; i < 3; i++) + { + CRPT->AES_IV[i] = (iv[i * 4 + 0] << 24) | (iv[i * 4 + 1] << 16) | + (iv[i * 4 + 2] << 8) | iv[i * 4 + 3]; + } + CRPT->AES_IV[3] = 0x00000001; + } + + CRPT->AES_SADDR = (uint32_t)&ghashbuf[0]; + CRPT->AES_DADDR = (uint32_t)&tag[0]; + CRPT->AES_CNT = 16; + + ret = AES_Run(ctx, u32OptBasic | CTR_MODE | DMAEN /*| DMALAST*/); + + memcpy(tagbuf, tag, 16); + Debug_GCM_Info(("## FUNC: %s finish tag 0x%x, 0x%x, 0x%x, 0x%x\n", __FUNCTION__, tag[0], tag[1], tag[2], tag[3])); + + return ret; +} + + +static int32_t _GCM(mbedtls_gcm_context *ctx, const uint8_t *iv, uint32_t ivlen, const uint8_t *A, uint32_t alen, const uint8_t *P, uint32_t plen, uint8_t *buf, uint8_t *tag, uint32_t tag_len) +{ + int32_t ret; + int32_t plen_cur; + int32_t len, len_aligned; + const uint8_t *pin; + uint8_t *pout; + uint32_t u32OptBasic; + uint32_t plen_aligned; + uint32_t size; + +#if 0 + SYS->IPRST0 = SYS_IPRST0_CRPTRST_Msk; + SYS->IPRST0 = 0; +#endif + + u32OptBasic = ctx->basicOpt; + + /* Set byte count of IV */ + CRPT->AES_GCM_IVCNT[0] = ivlen; + CRPT->AES_GCM_IVCNT[1] = 0; + + /* Set bytes count of A */ + CRPT->AES_GCM_ACNT[0] = alen; + CRPT->AES_GCM_ACNT[1] = 0; + + /* Set bytes count of P */ + CRPT->AES_GCM_PCNT[0] = plen; + CRPT->AES_GCM_PCNT[1] = 0; + + plen_aligned = (plen & 0xful) ? ((plen + 16) / 16) * 16 : plen; + + if(plen == 0) /* For AWS-IoT connection case, force go cascade instead of if(plen <= GCM_PBLOCK_SIZE) */ + { + /* Just one shot */ + + /* Prepare the blocked buffer for GCM */ + AES_GCMPacker(iv, ivlen, A, alen, P, plen, ctx->gcm_buf, &size); + + CRPT->AES_SADDR = (uint32_t)ctx->gcm_buf; + CRPT->AES_DADDR = (uint32_t)ctx->out_buf; + CRPT->AES_CNT = size; + + ret = AES_Run(ctx, u32OptBasic | GCM_MODE | DMAEN); + + memcpy(buf, ctx->out_buf, plen); + memcpy(tag, ctx->out_buf + plen_aligned, tag_len); + + } + else + { + + /* Process P block by block, DMA casecade mode */ + + /* inital DMA for AES-GCM casecade */ + + /* Prepare the blocked buffer for GCM */ + AES_GCMPacker(iv, ivlen, A, alen, 0, 0, ctx->gcm_buf, &size); + + CRPT->AES_SADDR = (uint32_t)ctx->gcm_buf; + CRPT->AES_DADDR = (uint32_t)ctx->out_buf; + CRPT->AES_CNT = size; + + /* feedback buffer is necessary for casecade mode */ + CRPT->AES_FBADDR = (uint32_t)ctx->fb_buf; + + AES_Run(ctx, u32OptBasic | GCM_MODE | FBOUT | DMAEN); + + /* Start to encrypt P data */ + plen_cur = plen; + pin = P; + pout = buf; + while(plen_cur) + { + len = plen_cur; + if(len > GCM_PBLOCK_SIZE) + { + len = GCM_PBLOCK_SIZE; + } + plen_cur -= len; + + /* Prepare the blocked buffer for GCM */ + memcpy(ctx->gcm_buf, pin, len); + /* padding 0 if necessary */ + if(len & 0xf) + { + memset(&ctx->gcm_buf[len], 0, 16 - (len & 0xf)); + len_aligned = ((len + 16) >> 4) << 4; + } + else + { + len_aligned = len; + } + + CRPT->AES_SADDR = (uint32_t)ctx->gcm_buf; + CRPT->AES_DADDR = (uint32_t)ctx->out_buf; + CRPT->AES_CNT = len_aligned; + + + if(plen_cur) + { + /* casecade n */ + ret = AES_Run(ctx, u32OptBasic | GCM_MODE | FBIN | FBOUT | DMAEN | DMACC); + } + else + { + /* last casecade */ + ret = AES_Run(ctx, u32OptBasic | GCM_MODE | FBIN | FBOUT | DMAEN | DMACC | DMALAST); + } + if(ret < 0) + { + return ret; + } + + memcpy(pout, ctx->out_buf, len); + + pin += len; + pout += len; + } + + memcpy(tag, ctx->out_buf+len_aligned, tag_len); + Debug_GCM_Info(("## Tag in FUNC: %s, plen=%d, tag=0x%x, 0x%x, 0x%x, 0x%x\n", __FUNCTION__, plen, + *((uint32_t*)tag), *((uint32_t*)(tag+4)), *((uint32_t*)(tag+8)), *((uint32_t*)(tag+16)) )); + } + + if(ctx->mode) + { + /* H/W limitation under plen%16 as 1 or 15, need re-calculate tag by _GCMTag */ + /* Need to calculate Tag when plen % 16 == 1 or 15 */ + if(( (plen & 0xf) == 1) || ((plen & 0xf) == 15)) + { + if((ret = _GCMTag(ctx, iv, ivlen, A, alen, ctx->out_buf, plen, tag))) + { + return ret; + } + } + } + + return 0; +} + +int mbedtls_gcm_crypt_and_tag( mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ) +{ + int ret; + Debug_GCM_Info(("## FUNC: %s, mode=%s, length=%d, tag_len=%d, in/out=0x%x/0x%x\n", __FUNCTION__, (mode) ? "Enc":"Dec", length, tag_len, input, output)); + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( iv != NULL ); + GCM_VALIDATE_RET( add_len == 0 || add != NULL ); + GCM_VALIDATE_RET( length == 0 || input != NULL ); + GCM_VALIDATE_RET( length == 0 || output != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + + ctx->mode = mode; + + if(mode) + { + ctx->basicOpt |= CRPT_AES_CTL_ENCRPT_Msk; + } + else + { + ctx->basicOpt &= ~CRPT_AES_CTL_ENCRPT_Msk; + } + + /* Acquire ownership of AES H/W */ + crypto_aes_acquire(); +#if 1 + /* Force AES free */ + CRPT->AES_CTL = CRPT_AES_CTL_STOP_Msk; +#endif + AES_ENABLE_INT(CRPT); + + ret = _GCM(ctx, iv, iv_len, add, add_len, input, length, output, tag, tag_len); + + /* Release ownership of AES H/W */ + crypto_aes_release(); + + return (ret); +} + +int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ) +{ + int ret; + unsigned char check_tag[16]; + size_t i; + int diff; + Debug_GCM_Info(("## FUNC: %s\n", __FUNCTION__)); + GCM_VALIDATE_RET( ctx != NULL ); + GCM_VALIDATE_RET( iv != NULL ); + GCM_VALIDATE_RET( add_len == 0 || add != NULL ); + GCM_VALIDATE_RET( tag != NULL ); + GCM_VALIDATE_RET( length == 0 || input != NULL ); + GCM_VALIDATE_RET( length == 0 || output != NULL ); + + if( ( ret = mbedtls_gcm_crypt_and_tag( ctx, MBEDTLS_GCM_DECRYPT, length, + iv, iv_len, add, add_len, + input, output, tag_len, check_tag ) ) != 0 ) + { + return( ret ); + } + + /* Check tag in "constant-time" */ + for( diff = 0, i = 0; i < tag_len; i++ ) + diff |= tag[i] ^ check_tag[i]; + + if( diff != 0 ) + { + mbedtls_platform_zeroize( output, length ); + return( MBEDTLS_ERR_GCM_AUTH_FAILED ); + } + + return( 0 ); +} + + +#endif /* NVT_GCM_USE_GHASH_CTR_MODE */ +#endif /* MBEDTLS_GCM_ALT */ +#endif /* MBEDTLS_GCM_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/gcm/gcm_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/gcm/gcm_alt.h new file mode 100644 index 0000000..a680e89 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/gcm/gcm_alt.h @@ -0,0 +1,72 @@ +/** + * \file gcm.h + * + * \brief This file contains GCM definitions and functions. + * + * The Galois/Counter Mode (GCM) for 128-bit block ciphers is defined + * in D. McGrew, J. Viega, The Galois/Counter Mode of Operation + * (GCM), Natl. Inst. Stand. Technol. + * + * For more information on GCM, see NIST SP 800-38D: Recommendation for + * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_GCM_ALT_H +#define MBEDTLS_GCM_ALT_H + +#if defined(MBEDTLS_GCM_ALT) +#include "mbed_toolchain.h" +#define MAX_GCM_BUF 256 +#define GCM_PBLOCK_SIZE (MAX_GCM_BUF) /* NOTE: This value must be 16 bytes alignment. This value must > size of A */ + + +/** + * \brief The GCM context structure. + */ +typedef struct mbedtls_gcm_context +{ + uint32_t len; /*!< The total length of the encrypted data. */ + int mode; /*!< The operation to perform: + #MBEDTLS_GCM_ENCRYPT or + #MBEDTLS_GCM_DECRYPT. */ + + uint32_t keySize; /* Key size unit is bytes: 16(128 bits)/24(192 bits)/32(256 bits) */ + uint32_t encDec; /* 0: decrypt, 1: encrypt */ + uint32_t opMode; /* AES_MODE_ECB/CBC/CFB */ + uint32_t iv[4]; /* IV for next block cipher */ + uint32_t keys[8]; /* Cipher key */ + uint32_t basicOpt; /* Basic option of AES controller */ + MBED_ALIGN(4) uint8_t gcm_buf[MAX_GCM_BUF]; /* buffer for GCM DMA input */ + MBED_ALIGN(4) uint8_t out_buf[MAX_GCM_BUF+16]; /* buffer for GCM DMA output */ + MBED_ALIGN(4) uint8_t fb_buf[72]; /* feedback buffer for GCM DMA */ + MBED_ALIGN(4) uint8_t fb_buf2[72]; /* feedback buffer 2 for GCM DMA */ + uint8_t tag[16]; /* Tag */ + uint32_t gcm_buf_bytes; /* Bytes in gcm_buf */ + uint32_t firstFlag; /* A flag for the first data block */ + uint32_t endFlag; /* final block is done */ + uint32_t pcntLen; /* PCNT length*/ +// uint8_t *add; +// size_t addlen; +} +mbedtls_gcm_context; + +#endif /* MBEDTLS_GCM_ALT */ + +#endif /* gcm.h */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/mbedtls_device.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/mbedtls_device.h new file mode 100644 index 0000000..71ed198 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/mbedtls_device.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_DEVICE_H +#define MBEDTLS_DEVICE_H + +#define MBEDTLS_SHA1_ALT +#define MBEDTLS_SHA256_ALT +#define MBEDTLS_SHA512_ALT + +#define MBEDTLS_AES_ALT +#define MBEDTLS_GCM_ALT +#define MBEDTLS_CCM_ALT + +#define MBEDTLS_ECP_ALT + +#if !defined(MBEDTLS_ECP_ALT) + +#define MBEDTLS_ECP_INTERNAL_ALT + +/* Support for Weierstrass curves with Jacobi representation */ +#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT +#define MBEDTLS_ECP_ADD_MIXED_ALT +#define MBEDTLS_ECP_DOUBLE_JAC_ALT +#define MBEDTLS_ECP_NORMALIZE_JAC_ALT +#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT + +/* Support for curves with Montgomery arithmetic */ +//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT +#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT +#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT + +#endif /* !MBEDTLS_ECP_ALT */ + +#define MBEDTLS_RSA_ALT + +#endif /* MBEDTLS_DEVICE_H */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/crypto_rsa_hw.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/crypto_rsa_hw.c new file mode 100644 index 0000000..40cba47 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/crypto_rsa_hw.c @@ -0,0 +1,427 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_RSA_C) + +#include "mbedtls/rsa.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_RSA_ALT) + +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbed_toolchain.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "mbed_toolchain.h" +#include "nu_bitutil.h" +#include "nu_timer.h" +#include "crypto-misc.h" + +#include "crypto_rsa_hw.h" + +/* Enable RSA debug */ +//#define NU_CRYPTO_RSA_ENABLE_DEBUG +//#define NU_CRYPTO_RSA_ENABLE_DEBUG_V + +/* Notes for RSA H/W port + * + * 1. For non-CRT+SCAP (excluding CRT+SCAP) mode, DMA buffer for MADDR6 must be key length plus 128 bits. + * 2. DMA buffer must be 4-word aligned, or RSA H/W will trap. + * 3. CRT is not well-tested yet, esp with 4096 key bits. + * 4. Following designer's resolution, disable SCAP. + */ + +/* RSA context for DMA */ +static struct { + struct { + uint32_t mode; // RSA_MODE_NORMAL/CRT/SCAP/CRT_SCAP + uint32_t keybits_code; // RSA_KEY_SIZE_1024/2048/3072/4096 + void * dmabuf; // Pointer to active DMA buffer + uint32_t dmabuf_size; // Active DMA buffer in bytes + } config; + + union { + RSA_BUF_NORMAL_T norm; + RSA_BUF_CRT_T crt; + RSA_BUF_SCAP_T scap; + RSA_BUF_CRT_SCAP_T crt_scap; + } dmabuf_u; + + struct { + MBED_ALIGN(4) char R[RSA_KBUF_HLEN]; // Output result + MBED_ALIGN(4) char M[RSA_KBUF_HLEN]; // Input message + MBED_ALIGN(4) char N[RSA_KBUF_HLEN]; // Modulus + MBED_ALIGN(4) char E[RSA_KBUF_HLEN]; // Exponent (public or private) + MBED_ALIGN(4) char P[RSA_KBUF_HLEN]; // First prime factor + MBED_ALIGN(4) char Q[RSA_KBUF_HLEN]; // Second prime factor + } keyctx_hs; +} rsa_hw_ctx_inst; + +int crypto_rsa_init(mbedtls_rsa_context *ctx) +{ + /* Acquire ownership of RSA H/W */ + crypto_rsa_acquire(); + + /* Initialize crypto module */ + crypto_init(); + + /* RSA H/W DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) Word-aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region */ + if ((! crypto_dma_buff_compat(&(rsa_hw_ctx_inst.dmabuf_u), sizeof(rsa_hw_ctx_inst.dmabuf_u), 4))) { + error("Buffer for RSA H/W DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); + } + + /* Release ownership of RSA accelerator */ + crypto_rsa_release(); + + return 0; +} + +void crypto_rsa_free(mbedtls_rsa_context *ctx) +{ + /* Acquire ownership of RSA H/W */ + crypto_rsa_acquire(); + + /* Uninit crypto module */ + crypto_uninit(); + + /* Release ownership of RSA accelerator */ + crypto_rsa_release(); +} + +int crypto_rsa_encrypt_norm_capable(const mbedtls_rsa_context *ctx) +{ + return crypto_rsa_crypt_capable(ctx, + false, // Encrypt operation + false, // Normal algorithm + false); // No blinding +} + +int crypto_rsa_decrypt_norm_capable(const mbedtls_rsa_context *ctx, bool blinding) +{ + return crypto_rsa_crypt_capable(ctx, + true, // Decrypt operation + false, // Normal algorithm + blinding); +} + +int crypto_rsa_decrypt_crt_capable(const mbedtls_rsa_context *ctx, bool blinding) +{ + return crypto_rsa_crypt_capable(ctx, + true, // Decrypt operation + true, // CRT algorithm + blinding); +} + +int crypto_rsa_crypt_capable(const mbedtls_rsa_context *ctx, + bool decrypt, + bool crt, + bool blinding) +{ + /* CRT is applicable only for decrypt operation */ + if (!decrypt && crt) { + return 0; + } + + /* NOTE: Check above RSA H/W comment for disabling crt */ + if (crt) { + return 0; + } + + /* Blinding (SCAP) is applicable only for decrypt operation */ + if (!decrypt && blinding) { + return 0; + } + + /* Support key bits + * + * Normal algorithm: 1024/2048/3072/4096 + * CRT algorithm: 2048/3072/4096 + */ + uint32_t keybits = ctx->len * 8; + if (keybits == 1024) { + return crt ? 0 : 1; + } else if (keybits == 2048 || keybits == 3072 || keybits == 4096) { + return 1; + } else { + return 0; + } +} + +int crypto_rsa_encrypt_norm(mbedtls_rsa_context *ctx, + const unsigned char *input, + unsigned char *output) +{ + return crypto_rsa_crypt(ctx, + false, // Encrypt operation + false, // Normal algorithm + false, + input, + output); +} + +int crypto_rsa_decrypt_norm(mbedtls_rsa_context *ctx, + bool blinding, + const unsigned char *input, + unsigned char *output) +{ + return crypto_rsa_crypt(ctx, + true, // Decrypt operation + false, // Normal algorithm + blinding, + input, + output); +} + +int crypto_rsa_decrypt_crt(mbedtls_rsa_context *ctx, + bool blinding, + const unsigned char *input, + unsigned char *output) +{ + return crypto_rsa_crypt(ctx, + true, // Decrypt operation + true, // CRT algorithm + blinding, + input, + output); +} + +int crypto_rsa_crypt(mbedtls_rsa_context *ctx, + bool decrypt, + bool crt, + bool blinding, + const unsigned char *input, + unsigned char *output) +{ + /* Acquire ownership of RSA H/W */ + crypto_rsa_acquire(); + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + bool rsa_done; + size_t olen; + uint32_t keybits; + + /* NOTE: Check above RSA H/W comment for disabling blinding */ + blinding = false; + +#if defined(NU_CRYPTO_RSA_ENABLE_DEBUG) + mbedtls_printf("[CRPT][RSA] decrypt=%d, crt=%d, blinding=%d\n", decrypt, crt, blinding); +#endif + + mbedtls_mpi M, R; + + mbedtls_mpi_init(&M); + mbedtls_mpi_init(&R); + + /* Read input message */ + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&M, input, ctx->len)); + + /* Driver key context requests hex string form. */ + + /* Populate M (input) into driver key context */ + MBEDTLS_MPI_CHK(mbedtls_mpi_write_string(&M, 16, rsa_hw_ctx_inst.keyctx_hs.M, RSA_KBUF_HLEN, &olen)); + + /* Populate N (modulus) into driver key context */ + MBEDTLS_MPI_CHK(mbedtls_mpi_write_string(&ctx->N, 16, rsa_hw_ctx_inst.keyctx_hs.N, RSA_KBUF_HLEN, &olen)); + + if (decrypt) { + /* Populate D (private key) into driver key context (exponent) */ + MBEDTLS_MPI_CHK(mbedtls_mpi_write_string(&ctx->D, 16, rsa_hw_ctx_inst.keyctx_hs.E, RSA_KBUF_HLEN, &olen)); + + /* Populate P/Q (first/second prime factor) into driver key context */ + MBEDTLS_MPI_CHK(mbedtls_mpi_write_string(&ctx->P, 16, rsa_hw_ctx_inst.keyctx_hs.P, RSA_KBUF_HLEN, &olen)); + MBEDTLS_MPI_CHK(mbedtls_mpi_write_string(&ctx->Q, 16, rsa_hw_ctx_inst.keyctx_hs.Q, RSA_KBUF_HLEN, &olen)); + } else { + /* Populate E (public key) into driver key context (exponent) */ + MBEDTLS_MPI_CHK(mbedtls_mpi_write_string(&ctx->E, 16, rsa_hw_ctx_inst.keyctx_hs.E, RSA_KBUF_HLEN, &olen)); + } + +#if defined(NU_CRYPTO_RSA_ENABLE_DEBUG_V) + mbedtls_printf("[CRPT][RSA] M:\n%s\n", rsa_hw_ctx_inst.keyctx_hs.M); + mbedtls_printf("[CRPT][RSA] N:\n%s\n", rsa_hw_ctx_inst.keyctx_hs.N); + mbedtls_printf("[CRPT][RSA] E:\n%s\n", rsa_hw_ctx_inst.keyctx_hs.E); + if (decrypt) { + mbedtls_printf("[CRPT][RSA] P:\n%s\n", rsa_hw_ctx_inst.keyctx_hs.P); + mbedtls_printf("[CRPT][RSA] Q:\n%s\n", rsa_hw_ctx_inst.keyctx_hs.Q); + } +#endif + + /* Resolve CRT/SCAP mode and corresponding DMA buffer */ + if (crt) { + if (blinding) { + rsa_hw_ctx_inst.config.mode = RSA_MODE_CRT_SCAP; + rsa_hw_ctx_inst.config.dmabuf = &rsa_hw_ctx_inst.dmabuf_u.crt_scap; + rsa_hw_ctx_inst.config.dmabuf_size = sizeof(rsa_hw_ctx_inst.dmabuf_u.crt_scap); + } else { + rsa_hw_ctx_inst.config.mode = RSA_MODE_CRT; + rsa_hw_ctx_inst.config.dmabuf = &rsa_hw_ctx_inst.dmabuf_u.crt; + rsa_hw_ctx_inst.config.dmabuf_size = sizeof(rsa_hw_ctx_inst.dmabuf_u.crt); + } + } else { + if (blinding) { + rsa_hw_ctx_inst.config.mode = RSA_MODE_SCAP; + rsa_hw_ctx_inst.config.dmabuf = &rsa_hw_ctx_inst.dmabuf_u.scap; + rsa_hw_ctx_inst.config.dmabuf_size = sizeof(rsa_hw_ctx_inst.dmabuf_u.scap); + } else { + rsa_hw_ctx_inst.config.mode = RSA_MODE_NORMAL; + rsa_hw_ctx_inst.config.dmabuf = &rsa_hw_ctx_inst.dmabuf_u.norm; + rsa_hw_ctx_inst.config.dmabuf_size = sizeof(rsa_hw_ctx_inst.dmabuf_u.norm); + } + } + + /* Resolve key bits code */ + keybits = ctx->len * 8; + switch (keybits) { + case 1024: + rsa_hw_ctx_inst.config.keybits_code = RSA_KEY_SIZE_1024; + break; + + case 2048: + rsa_hw_ctx_inst.config.keybits_code = RSA_KEY_SIZE_2048; + break; + + case 3072: + rsa_hw_ctx_inst.config.keybits_code = RSA_KEY_SIZE_3072; + break; + + case 4096: + rsa_hw_ctx_inst.config.keybits_code = RSA_KEY_SIZE_4096; + break; + + default: + ret = MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + goto cleanup; + } + + /* Enable RSA interrupt */ + RSA_ENABLE_INT(CRPT); + + /* For safe, recover from previous failure if ever */ + MBEDTLS_MPI_CHK(crypto_rsa_abort(ctx, 5*1000*1000)); + + /* NOTE: Driver (RSA_SetKey()/RSA_SetDMATransfer()) requests zero-padded + * hex string to configure DMA buffer (via Hex2Reg), but + * mbedtls_mpi_write_string() doesn't support this. Pre-clean + * DMA buffer as workaround. */ + mbedtls_platform_zeroize(rsa_hw_ctx_inst.config.dmabuf, rsa_hw_ctx_inst.config.dmabuf_size); + + MBED_ASSERT(rsa_hw_ctx_inst.config.dmabuf != NULL); + MBED_ASSERT(rsa_hw_ctx_inst.config.dmabuf_size != 0); + MBEDTLS_MPI_CHK((RSA_Open(CRPT, rsa_hw_ctx_inst.config.mode, + rsa_hw_ctx_inst.config.keybits_code, + rsa_hw_ctx_inst.config.dmabuf, + rsa_hw_ctx_inst.config.dmabuf_size, + 0) == 0) ? 0 : MBEDTLS_ERR_RSA_BAD_INPUT_DATA); + + /* Set exponent (public/private key) into DMA buffer */ + RSA_SetKey(CRPT, rsa_hw_ctx_inst.keyctx_hs.E); + + /* Set most other parameters into DMA buffer */ + RSA_SetDMATransfer(CRPT, + rsa_hw_ctx_inst.keyctx_hs.M, + rsa_hw_ctx_inst.keyctx_hs.N, + rsa_hw_ctx_inst.keyctx_hs.P, + rsa_hw_ctx_inst.keyctx_hs.Q); + + /* Trigger and wait */ + crypto_rsa_prestart(); +#if defined(NU_CRYPTO_RSA_ENABLE_DEBUG) + mbedtls_printf("[CRPT][RSA] Crypto RSA ...\n"); +#endif + RSA_Start(CRPT); + rsa_done = crypto_rsa_wait2(1000*1000); // 1s timeout +#if defined(NU_CRYPTO_RSA_ENABLE_DEBUG) + mbedtls_printf("[CRPT][RSA] Crypto RSA ... %s\n", rsa_done ? "Done" : "Error"); +#endif + + /* For safe, recover from current failure */ + if (!rsa_done) { + crypto_rsa_abort(ctx, 5*1000*1000); + } + + /* Disable RSA interrupt */ + RSA_DISABLE_INT(CRPT); + + MBEDTLS_MPI_CHK(rsa_done ? 0 : MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + + /* Write output result */ + RSA_Read(CRPT, rsa_hw_ctx_inst.keyctx_hs.R); + MBEDTLS_MPI_CHK(mbedtls_mpi_read_string(&R, 16, rsa_hw_ctx_inst.keyctx_hs.R)); + MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&R, output, ctx->len)); + +#if defined(NU_CRYPTO_RSA_ENABLE_DEBUG_V) + mbedtls_printf("[CRPT][RSA] R:\n%s\n", rsa_hw_ctx_inst.keyctx_hs.R); +#endif + +cleanup: + + mbedtls_mpi_free(&M); + mbedtls_mpi_free(&R); + + /* Release ownership of RSA accelerator */ + crypto_rsa_release(); + + return ret; +} + +int crypto_rsa_abort(MBED_UNUSED mbedtls_rsa_context *ctx, + uint32_t timeout_us) +{ + /* Acquire ownership of RSA H/W */ + crypto_rsa_acquire(); + + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + CRPT->RSA_CTL = CRPT_RSA_CTL_STOP_Msk; + struct nu_countdown_ctx_s cd_ctx; + nu_countdown_init(&cd_ctx, timeout_us); + while (CRPT->RSA_STS & CRPT_RSA_STS_BUSY_Msk) { + if (nu_countdown_expired(&cd_ctx)) { + break; + } + } + nu_countdown_free(&cd_ctx); + if (CRPT->RSA_STS & CRPT_RSA_STS_BUSY_Msk) { +#if defined(NU_CRYPTO_RSA_ENABLE_DEBUG) + mbedtls_printf("[CRPT][RSA] Crypto RSA ... Busy\n"); +#endif + ret = MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + goto cleanup; + } + + ret = 0; + +cleanup: + + /* Release ownership of RSA accelerator */ + crypto_rsa_release(); + + return ret; +} + +#endif /* MBEDTLS_RSA_ALT */ +#endif /* MBEDTLS_RSA_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/crypto_rsa_hw.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/crypto_rsa_hw.h new file mode 100644 index 0000000..b3bd67a --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/crypto_rsa_hw.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef CRYPTO_RSA_HW_H +#define CRYPTO_RSA_HW_H + +#include "mbedtls/rsa.h" + +#if defined(MBEDTLS_RSA_ALT) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Initialize/Free Crypto RSA H/W + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + * + * \note crypto_rsa_init()/crypto_rsa_free() are like pre-op/post-op calls + * and they guarantee: + * + * 1. Paired + * 2. No overlapping + * 3. Upper public function cannot return when RSA alter. is still activated. + */ +int crypto_rsa_init(mbedtls_rsa_context *ctx); +void crypto_rsa_free(mbedtls_rsa_context *ctx); + +/** + * \brief Query whether or not RSA H/W supports encrypt/decrypt operation in this context + * in normal/CRT algorithm + * + * \param ctx The initialized RSA context to use. + * \param decrypt true for decrypt, or encrypt. + * \param crt true for CRT algorithm, or normal. + * \param blinding Blinding (SCAP) or not. + * + * \return \c 1 on capable, or 0 on incapable. + * + * \note Blinding is applicable only for decrypt operation. + * \note CRT is applicable only for decrypt operation. + */ +int crypto_rsa_encrypt_norm_capable(const mbedtls_rsa_context *ctx); +int crypto_rsa_decrypt_norm_capable(const mbedtls_rsa_context *ctx, bool blinding); +int crypto_rsa_decrypt_crt_capable(const mbedtls_rsa_context *ctx, bool blinding); +int crypto_rsa_crypt_capable(const mbedtls_rsa_context *ctx, + bool decrypt, + bool crt, + bool blinding); +/** + * \brief Run RSA encrypt/decrypt operation in normal/CRT algorithm + * + * \param ctx The initialized RSA context to use. + * \param decrypt true for decrypt, or encrypt. + * \param crt true for CRT algorithm, or normal. + * \param blinding Blinding (SCAP) or not. + * \param input The input buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int crypto_rsa_encrypt_norm(mbedtls_rsa_context *ctx, + const unsigned char *input, + unsigned char *output); +int crypto_rsa_decrypt_norm(mbedtls_rsa_context *ctx, + bool blinding, + const unsigned char *input, + unsigned char *output); +int crypto_rsa_decrypt_crt(mbedtls_rsa_context *ctx, + bool blinding, + const unsigned char *input, + unsigned char *output); +int crypto_rsa_crypt(mbedtls_rsa_context *ctx, + bool decrypt, + bool crt, + bool blinding, + const unsigned char *input, + unsigned char *output); + +/** + * \brief Abort Crypto RSA H/W + * + * \param ctx The initialized RSA context to use. + * \param timeout_us Timeout in microseconds. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int crypto_rsa_abort(mbedtls_rsa_context *ctx, + uint32_t timeout_us); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_RSA_ALT */ + +#endif /* CRYPTO_RSA_HW_H */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/rsa_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/rsa_alt.c new file mode 100644 index 0000000..bab2fb6 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/rsa_alt.c @@ -0,0 +1,2653 @@ +/* + * The RSA public-key cryptosystem + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * The following sources were referenced in the design of this implementation + * of the RSA algorithm: + * + * [1] A method for obtaining digital signatures and public-key cryptosystems + * R Rivest, A Shamir, and L Adleman + * http://people.csail.mit.edu/rivest/pubs.html#RSA78 + * + * [2] Handbook of Applied Cryptography - 1997, Chapter 8 + * Menezes, van Oorschot and Vanstone + * + * [3] Malware Guard Extension: Using SGX to Conceal Cache Attacks + * Michael Schwarz, Samuel Weiser, Daniel Gruss, Clémentine Maurice and + * Stefan Mangard + * https://arxiv.org/abs/1702.08719v2 + * + */ + +#include "common.h" + +#if defined(MBEDTLS_RSA_C) + +#include "mbedtls/rsa.h" +#include "mbedtls/rsa_internal.h" +#include "mbedtls/oid.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" + +#include + +#if defined(MBEDTLS_PKCS1_V21) +#include "mbedtls/md.h" +#endif + +#if defined(MBEDTLS_PKCS1_V15) && !defined(__OpenBSD__) && !defined(__NetBSD__) +#include +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#if defined(NU_CRYPTO_RSA_ENABLE) +#include "crypto_rsa_hw.h" +#endif + +#if defined(MBEDTLS_RSA_ALT) + +/* Parameter validation macros */ +#define RSA_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_RSA_BAD_INPUT_DATA ) +#define RSA_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_PKCS1_V15) +/* constant-time buffer comparison */ +static inline int mbedtls_safer_memcmp( const void *a, const void *b, size_t n ) +{ + size_t i; + const unsigned char *A = (const unsigned char *) a; + const unsigned char *B = (const unsigned char *) b; + unsigned char diff = 0; + + for( i = 0; i < n; i++ ) + diff |= A[i] ^ B[i]; + + return( diff ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +int mbedtls_rsa_import( mbedtls_rsa_context *ctx, + const mbedtls_mpi *N, + const mbedtls_mpi *P, const mbedtls_mpi *Q, + const mbedtls_mpi *D, const mbedtls_mpi *E ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + RSA_VALIDATE_RET( ctx != NULL ); + + if( ( N != NULL && ( ret = mbedtls_mpi_copy( &ctx->N, N ) ) != 0 ) || + ( P != NULL && ( ret = mbedtls_mpi_copy( &ctx->P, P ) ) != 0 ) || + ( Q != NULL && ( ret = mbedtls_mpi_copy( &ctx->Q, Q ) ) != 0 ) || + ( D != NULL && ( ret = mbedtls_mpi_copy( &ctx->D, D ) ) != 0 ) || + ( E != NULL && ( ret = mbedtls_mpi_copy( &ctx->E, E ) ) != 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } + + if( N != NULL ) + ctx->len = mbedtls_mpi_size( &ctx->N ); + + return( 0 ); +} + +int mbedtls_rsa_import_raw( mbedtls_rsa_context *ctx, + unsigned char const *N, size_t N_len, + unsigned char const *P, size_t P_len, + unsigned char const *Q, size_t Q_len, + unsigned char const *D, size_t D_len, + unsigned char const *E, size_t E_len ) +{ + int ret = 0; + RSA_VALIDATE_RET( ctx != NULL ); + + if( N != NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->N, N, N_len ) ); + ctx->len = mbedtls_mpi_size( &ctx->N ); + } + + if( P != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->P, P, P_len ) ); + + if( Q != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->Q, Q, Q_len ) ); + + if( D != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->D, D, D_len ) ); + + if( E != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->E, E, E_len ) ); + +cleanup: + + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + + return( 0 ); +} + +/* + * Checks whether the context fields are set in such a way + * that the RSA primitives will be able to execute without error. + * It does *not* make guarantees for consistency of the parameters. + */ +static int rsa_check_context( mbedtls_rsa_context const *ctx, int is_priv, + int blinding_needed ) +{ +#if !defined(MBEDTLS_RSA_NO_CRT) + /* blinding_needed is only used for NO_CRT to decide whether + * P,Q need to be present or not. */ + ((void) blinding_needed); +#endif + + if( ctx->len != mbedtls_mpi_size( &ctx->N ) || + ctx->len > MBEDTLS_MPI_MAX_SIZE ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + + /* + * 1. Modular exponentiation needs positive, odd moduli. + */ + + /* Modular exponentiation wrt. N is always used for + * RSA public key operations. */ + if( mbedtls_mpi_cmp_int( &ctx->N, 0 ) <= 0 || + mbedtls_mpi_get_bit( &ctx->N, 0 ) == 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* Modular exponentiation for P and Q is only + * used for private key operations and if CRT + * is used. */ + if( is_priv && + ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) <= 0 || + mbedtls_mpi_get_bit( &ctx->P, 0 ) == 0 || + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) <= 0 || + mbedtls_mpi_get_bit( &ctx->Q, 0 ) == 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif /* !MBEDTLS_RSA_NO_CRT */ + + /* + * 2. Exponents must be positive + */ + + /* Always need E for public key operations */ + if( mbedtls_mpi_cmp_int( &ctx->E, 0 ) <= 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_RSA_NO_CRT) + /* For private key operations, use D or DP & DQ + * as (unblinded) exponents. */ + if( is_priv && mbedtls_mpi_cmp_int( &ctx->D, 0 ) <= 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); +#else + if( is_priv && + ( mbedtls_mpi_cmp_int( &ctx->DP, 0 ) <= 0 || + mbedtls_mpi_cmp_int( &ctx->DQ, 0 ) <= 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* Blinding shouldn't make exponents negative either, + * so check that P, Q >= 1 if that hasn't yet been + * done as part of 1. */ +#if defined(MBEDTLS_RSA_NO_CRT) + if( is_priv && blinding_needed && + ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) <= 0 || + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) <= 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif + + /* It wouldn't lead to an error if it wasn't satisfied, + * but check for QP >= 1 nonetheless. */ +#if !defined(MBEDTLS_RSA_NO_CRT) + if( is_priv && + mbedtls_mpi_cmp_int( &ctx->QP, 0 ) <= 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } +#endif + + return( 0 ); +} + +int mbedtls_rsa_complete( mbedtls_rsa_context *ctx ) +{ + int ret = 0; + int have_N, have_P, have_Q, have_D, have_E; +#if !defined(MBEDTLS_RSA_NO_CRT) + int have_DP, have_DQ, have_QP; +#endif + int n_missing, pq_missing, d_missing, is_pub, is_priv; + + RSA_VALIDATE_RET( ctx != NULL ); + + have_N = ( mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 ); + have_P = ( mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 ); + have_Q = ( mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 ); + have_D = ( mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 ); + have_E = ( mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0 ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + have_DP = ( mbedtls_mpi_cmp_int( &ctx->DP, 0 ) != 0 ); + have_DQ = ( mbedtls_mpi_cmp_int( &ctx->DQ, 0 ) != 0 ); + have_QP = ( mbedtls_mpi_cmp_int( &ctx->QP, 0 ) != 0 ); +#endif + + /* + * Check whether provided parameters are enough + * to deduce all others. The following incomplete + * parameter sets for private keys are supported: + * + * (1) P, Q missing. + * (2) D and potentially N missing. + * + */ + + n_missing = have_P && have_Q && have_D && have_E; + pq_missing = have_N && !have_P && !have_Q && have_D && have_E; + d_missing = have_P && have_Q && !have_D && have_E; + is_pub = have_N && !have_P && !have_Q && !have_D && have_E; + + /* These three alternatives are mutually exclusive */ + is_priv = n_missing || pq_missing || d_missing; + + if( !is_priv && !is_pub ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Step 1: Deduce N if P, Q are provided. + */ + + if( !have_N && have_P && have_Q ) + { + if( ( ret = mbedtls_mpi_mul_mpi( &ctx->N, &ctx->P, + &ctx->Q ) ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } + + ctx->len = mbedtls_mpi_size( &ctx->N ); + } + + /* + * Step 2: Deduce and verify all remaining core parameters. + */ + + if( pq_missing ) + { + ret = mbedtls_rsa_deduce_primes( &ctx->N, &ctx->E, &ctx->D, + &ctx->P, &ctx->Q ); + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + + } + else if( d_missing ) + { + if( ( ret = mbedtls_rsa_deduce_private_exponent( &ctx->P, + &ctx->Q, + &ctx->E, + &ctx->D ) ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } + } + + /* + * Step 3: Deduce all additional parameters specific + * to our current RSA implementation. + */ + +#if !defined(MBEDTLS_RSA_NO_CRT) + if( is_priv && ! ( have_DP && have_DQ && have_QP ) ) + { + ret = mbedtls_rsa_deduce_crt( &ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP ); + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* + * Step 3: Basic sanity checks + */ + + return( rsa_check_context( ctx, is_priv, 1 ) ); +} + +int mbedtls_rsa_export_raw( const mbedtls_rsa_context *ctx, + unsigned char *N, size_t N_len, + unsigned char *P, size_t P_len, + unsigned char *Q, size_t Q_len, + unsigned char *D, size_t D_len, + unsigned char *E, size_t E_len ) +{ + int ret = 0; + int is_priv; + RSA_VALIDATE_RET( ctx != NULL ); + + /* Check if key is private or public */ + is_priv = + mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0; + + if( !is_priv ) + { + /* If we're trying to export private parameters for a public key, + * something must be wrong. */ + if( P != NULL || Q != NULL || D != NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + } + + if( N != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->N, N, N_len ) ); + + if( P != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->P, P, P_len ) ); + + if( Q != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->Q, Q, Q_len ) ); + + if( D != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->D, D, D_len ) ); + + if( E != NULL ) + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &ctx->E, E, E_len ) ); + +cleanup: + + return( ret ); +} + +int mbedtls_rsa_export( const mbedtls_rsa_context *ctx, + mbedtls_mpi *N, mbedtls_mpi *P, mbedtls_mpi *Q, + mbedtls_mpi *D, mbedtls_mpi *E ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + int is_priv; + RSA_VALIDATE_RET( ctx != NULL ); + + /* Check if key is private or public */ + is_priv = + mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0; + + if( !is_priv ) + { + /* If we're trying to export private parameters for a public key, + * something must be wrong. */ + if( P != NULL || Q != NULL || D != NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + } + + /* Export all requested core parameters. */ + + if( ( N != NULL && ( ret = mbedtls_mpi_copy( N, &ctx->N ) ) != 0 ) || + ( P != NULL && ( ret = mbedtls_mpi_copy( P, &ctx->P ) ) != 0 ) || + ( Q != NULL && ( ret = mbedtls_mpi_copy( Q, &ctx->Q ) ) != 0 ) || + ( D != NULL && ( ret = mbedtls_mpi_copy( D, &ctx->D ) ) != 0 ) || + ( E != NULL && ( ret = mbedtls_mpi_copy( E, &ctx->E ) ) != 0 ) ) + { + return( ret ); + } + + return( 0 ); +} + +/* + * Export CRT parameters + * This must also be implemented if CRT is not used, for being able to + * write DER encoded RSA keys. The helper function mbedtls_rsa_deduce_crt + * can be used in this case. + */ +int mbedtls_rsa_export_crt( const mbedtls_rsa_context *ctx, + mbedtls_mpi *DP, mbedtls_mpi *DQ, mbedtls_mpi *QP ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + int is_priv; + RSA_VALIDATE_RET( ctx != NULL ); + + /* Check if key is private or public */ + is_priv = + mbedtls_mpi_cmp_int( &ctx->N, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->P, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->Q, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 && + mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0; + + if( !is_priv ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* Export all requested blinding parameters. */ + if( ( DP != NULL && ( ret = mbedtls_mpi_copy( DP, &ctx->DP ) ) != 0 ) || + ( DQ != NULL && ( ret = mbedtls_mpi_copy( DQ, &ctx->DQ ) ) != 0 ) || + ( QP != NULL && ( ret = mbedtls_mpi_copy( QP, &ctx->QP ) ) != 0 ) ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } +#else + if( ( ret = mbedtls_rsa_deduce_crt( &ctx->P, &ctx->Q, &ctx->D, + DP, DQ, QP ) ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA + ret ); + } +#endif + + return( 0 ); +} + +/* + * Initialize an RSA context + */ +void mbedtls_rsa_init( mbedtls_rsa_context *ctx, + int padding, + int hash_id ) +{ + RSA_VALIDATE( ctx != NULL ); + RSA_VALIDATE( padding == MBEDTLS_RSA_PKCS_V15 || + padding == MBEDTLS_RSA_PKCS_V21 ); + + memset( ctx, 0, sizeof( mbedtls_rsa_context ) ); + + mbedtls_rsa_set_padding( ctx, padding, hash_id ); + +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_init( &ctx->mutex ); +#endif + +#if defined(NU_CRYPTO_RSA_ENABLE) + ctx->hw_init = 0; +#endif +} + +/* + * Set padding for an existing RSA context + */ +void mbedtls_rsa_set_padding( mbedtls_rsa_context *ctx, int padding, + int hash_id ) +{ + RSA_VALIDATE( ctx != NULL ); + RSA_VALIDATE( padding == MBEDTLS_RSA_PKCS_V15 || + padding == MBEDTLS_RSA_PKCS_V21 ); + + ctx->padding = padding; + ctx->hash_id = hash_id; +} + +/* + * Get length in bytes of RSA modulus + */ + +size_t mbedtls_rsa_get_len( const mbedtls_rsa_context *ctx ) +{ + return( ctx->len ); +} + + +#if defined(MBEDTLS_GENPRIME) + +/* + * Generate an RSA keypair + * + * This generation method follows the RSA key pair generation procedure of + * FIPS 186-4 if 2^16 < exponent < 2^256 and nbits = 2048 or nbits = 3072. + */ +int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + unsigned int nbits, int exponent ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi H, G, L; + int prime_quality = 0; + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( f_rng != NULL ); + + if( nbits < 128 || exponent < 3 || nbits % 2 != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * If the modulus is 1024 bit long or shorter, then the security strength of + * the RSA algorithm is less than or equal to 80 bits and therefore an error + * rate of 2^-80 is sufficient. + */ + if( nbits > 1024 ) + prime_quality = MBEDTLS_MPI_GEN_PRIME_FLAG_LOW_ERR; + + mbedtls_mpi_init( &H ); + mbedtls_mpi_init( &G ); + mbedtls_mpi_init( &L ); + + /* + * find primes P and Q with Q < P so that: + * 1. |P-Q| > 2^( nbits / 2 - 100 ) + * 2. GCD( E, (P-1)*(Q-1) ) == 1 + * 3. E^-1 mod LCM(P-1, Q-1) > 2^( nbits / 2 ) + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &ctx->E, exponent ) ); + + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->P, nbits >> 1, + prime_quality, f_rng, p_rng ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_gen_prime( &ctx->Q, nbits >> 1, + prime_quality, f_rng, p_rng ) ); + + /* make sure the difference between p and q is not too small (FIPS 186-4 §B.3.3 step 5.4) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &H, &ctx->P, &ctx->Q ) ); + if( mbedtls_mpi_bitlen( &H ) <= ( ( nbits >= 200 ) ? ( ( nbits >> 1 ) - 99 ) : 0 ) ) + continue; + + /* not required by any standards, but some users rely on the fact that P > Q */ + if( H.s < 0 ) + mbedtls_mpi_swap( &ctx->P, &ctx->Q ); + + /* Temporarily replace P,Q by P-1, Q-1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &ctx->P, &ctx->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &ctx->Q, &ctx->Q, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &H, &ctx->P, &ctx->Q ) ); + + /* check GCD( E, (P-1)*(Q-1) ) == 1 (FIPS 186-4 §B.3.1 criterion 2(a)) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( &G, &ctx->E, &H ) ); + if( mbedtls_mpi_cmp_int( &G, 1 ) != 0 ) + continue; + + /* compute smallest possible D = E^-1 mod LCM(P-1, Q-1) (FIPS 186-4 §B.3.1 criterion 3(b)) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( &G, &ctx->P, &ctx->Q ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_div_mpi( &L, NULL, &H, &G ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &ctx->D, &ctx->E, &L ) ); + + if( mbedtls_mpi_bitlen( &ctx->D ) <= ( ( nbits + 1 ) / 2 ) ) // (FIPS 186-4 §B.3.1 criterion 3(a)) + continue; + + break; + } + while( 1 ); + + /* Restore P,Q */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( &ctx->P, &ctx->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_int( &ctx->Q, &ctx->Q, 1 ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->N, &ctx->P, &ctx->Q ) ); + + ctx->len = mbedtls_mpi_size( &ctx->N ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* + * DP = D mod (P - 1) + * DQ = D mod (Q - 1) + * QP = Q^-1 mod P + */ + MBEDTLS_MPI_CHK( mbedtls_rsa_deduce_crt( &ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP ) ); +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* Double-check */ + MBEDTLS_MPI_CHK( mbedtls_rsa_check_privkey( ctx ) ); + +cleanup: + + mbedtls_mpi_free( &H ); + mbedtls_mpi_free( &G ); + mbedtls_mpi_free( &L ); + + if( ret != 0 ) + { + mbedtls_rsa_free( ctx ); + return( MBEDTLS_ERR_RSA_KEY_GEN_FAILED + ret ); + } + + return( 0 ); +} + +#endif /* MBEDTLS_GENPRIME */ + +/* + * Check a public RSA key + */ +int mbedtls_rsa_check_pubkey( const mbedtls_rsa_context *ctx ) +{ + RSA_VALIDATE_RET( ctx != NULL ); + + if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) != 0 ) + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + + if( mbedtls_mpi_bitlen( &ctx->N ) < 128 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + if( mbedtls_mpi_get_bit( &ctx->E, 0 ) == 0 || + mbedtls_mpi_bitlen( &ctx->E ) < 2 || + mbedtls_mpi_cmp_mpi( &ctx->E, &ctx->N ) >= 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + return( 0 ); +} + +/* + * Check for the consistency of all fields in an RSA private key context + */ +int mbedtls_rsa_check_privkey( const mbedtls_rsa_context *ctx ) +{ + RSA_VALIDATE_RET( ctx != NULL ); + + if( mbedtls_rsa_check_pubkey( ctx ) != 0 || + rsa_check_context( ctx, 1 /* private */, 1 /* blinding */ ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + if( mbedtls_rsa_validate_params( &ctx->N, &ctx->P, &ctx->Q, + &ctx->D, &ctx->E, NULL, NULL ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + +#if !defined(MBEDTLS_RSA_NO_CRT) + else if( mbedtls_rsa_validate_crt( &ctx->P, &ctx->Q, &ctx->D, + &ctx->DP, &ctx->DQ, &ctx->QP ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } +#endif + + return( 0 ); +} + +/* + * Check if contexts holding a public and private key match + */ +int mbedtls_rsa_check_pub_priv( const mbedtls_rsa_context *pub, + const mbedtls_rsa_context *prv ) +{ + RSA_VALIDATE_RET( pub != NULL ); + RSA_VALIDATE_RET( prv != NULL ); + + if( mbedtls_rsa_check_pubkey( pub ) != 0 || + mbedtls_rsa_check_privkey( prv ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + if( mbedtls_mpi_cmp_mpi( &pub->N, &prv->N ) != 0 || + mbedtls_mpi_cmp_mpi( &pub->E, &prv->E ) != 0 ) + { + return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); + } + + return( 0 ); +} + +/* + * Do an RSA public key operation + */ +int mbedtls_rsa_public( mbedtls_rsa_context *ctx, + const unsigned char *input, + unsigned char *output ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; +#if defined(NU_CRYPTO_RSA_ENABLE) + bool hw_go = false; + bool hw_encrypt_norm_capable = false; + bool sw_fallback = false; +#endif /* NU_CRYPTO_RSA_ENABLE */ + size_t olen; + mbedtls_mpi T; + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( input != NULL ); + RSA_VALIDATE_RET( output != NULL ); + + if( rsa_check_context( ctx, 0 /* public */, 0 /* no blinding */ ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &T ); + +#if defined(MBEDTLS_THREADING_C) + if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 ) + return( ret ); +#endif + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &T, input, ctx->len ) ); + + if( mbedtls_mpi_cmp_mpi( &T, &ctx->N ) >= 0 ) + { + ret = MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + goto cleanup; + } + +#if defined(NU_CRYPTO_RSA_ENABLE) + hw_encrypt_norm_capable = crypto_rsa_encrypt_norm_capable(ctx); + if (!ctx->hw_init) { + ctx->hw_init = (crypto_rsa_init(ctx) == 0) ? 1 : 0; + } + hw_go = hw_encrypt_norm_capable && ctx->hw_init; + if (hw_encrypt_norm_capable && hw_go) { + ret = crypto_rsa_encrypt_norm(ctx, input, output); + if (ret == 0) { + goto cleanup; + } + + /* Fall back to S/W on H/W failure */ + sw_fallback = true; + } +#endif /* NU_CRYPTO_RSA_ENABLE */ + + olen = ctx->len; + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &T, &T, &ctx->E, &ctx->N, &ctx->RN ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &T, output, olen ) ); + +cleanup: +#if defined(MBEDTLS_THREADING_C) + if( mbedtls_mutex_unlock( &ctx->mutex ) != 0 ) + return( MBEDTLS_ERR_THREADING_MUTEX_ERROR ); +#endif + + mbedtls_mpi_free( &T ); + +#if defined(NU_CRYPTO_RSA_ENABLE) + if (hw_go) { + /* Premature return on H/W success, or continue to do other S/W clean-up + * because it is involved as fallback. */ + if (!sw_fallback) { + return ret; + } + } +#endif + + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_PUBLIC_FAILED + ret ); + + return( 0 ); +} + +/* + * Generate or update blinding values, see section 10 of: + * KOCHER, Paul C. Timing attacks on implementations of Diffie-Hellman, RSA, + * DSS, and other systems. In : Advances in Cryptology-CRYPTO'96. Springer + * Berlin Heidelberg, 1996. p. 104-113. + */ +static int rsa_prepare_blinding( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret, count = 0; + mbedtls_mpi R; + + mbedtls_mpi_init( &R ); + + if( ctx->Vf.p != NULL ) + { + /* We already have blinding values, just update them by squaring */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vi, &ctx->Vi, &ctx->Vi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vi, &ctx->Vi, &ctx->N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vf, &ctx->Vf, &ctx->Vf ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vf, &ctx->Vf, &ctx->N ) ); + + goto cleanup; + } + + /* Unblinding value: Vf = random number, invertible mod N */ + do { + if( count++ > 10 ) + { + ret = MBEDTLS_ERR_RSA_RNG_FAILED; + goto cleanup; + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &ctx->Vf, ctx->len - 1, f_rng, p_rng ) ); + + /* Compute Vf^-1 as R * (R Vf)^-1 to avoid leaks from inv_mod. */ + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &R, ctx->len - 1, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vi, &ctx->Vf, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vi, &ctx->Vi, &ctx->N ) ); + + /* At this point, Vi is invertible mod N if and only if both Vf and R + * are invertible mod N. If one of them isn't, we don't need to know + * which one, we just loop and choose new values for both of them. + * (Each iteration succeeds with overwhelming probability.) */ + ret = mbedtls_mpi_inv_mod( &ctx->Vi, &ctx->Vi, &ctx->N ); + if( ret != 0 && ret != MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ) + goto cleanup; + + } while( ret == MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ); + + /* Finish the computation of Vf^-1 = R * (R Vf)^-1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vi, &ctx->Vi, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vi, &ctx->Vi, &ctx->N ) ); + + /* Blinding value: Vi = Vf^(-e) mod N + * (Vi already contains Vf^-1 at this point) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &ctx->Vi, &ctx->Vi, &ctx->E, &ctx->N, &ctx->RN ) ); + + +cleanup: + mbedtls_mpi_free( &R ); + + return( ret ); +} + +/* + * Exponent blinding supposed to prevent side-channel attacks using multiple + * traces of measurements to recover the RSA key. The more collisions are there, + * the more bits of the key can be recovered. See [3]. + * + * Collecting n collisions with m bit long blinding value requires 2^(m-m/n) + * observations on avarage. + * + * For example with 28 byte blinding to achieve 2 collisions the adversary has + * to make 2^112 observations on avarage. + * + * (With the currently (as of 2017 April) known best algorithms breaking 2048 + * bit RSA requires approximately as much time as trying out 2^112 random keys. + * Thus in this sense with 28 byte blinding the security is not reduced by + * side-channel attacks like the one in [3]) + * + * This countermeasure does not help if the key recovery is possible with a + * single trace. + */ +#define RSA_EXPONENT_BLINDING 28 + +/* + * Do an RSA private key operation + */ +int mbedtls_rsa_private( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *input, + unsigned char *output ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; +#if defined(NU_CRYPTO_RSA_ENABLE) + bool hw_go = false; + bool hw_decrypt_norm_capable = false; +#if !defined(MBEDTLS_RSA_NO_CRT) + bool hw_decrypt_crt_capable = false; +#endif + bool sw_fallback = false; +#endif /* NU_CRYPTO_RSA_ENABLE */ + size_t olen; + + /* Temporary holding the result */ + mbedtls_mpi T; + + /* Temporaries holding P-1, Q-1 and the + * exponent blinding factor, respectively. */ + mbedtls_mpi P1, Q1, R; + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* Temporaries holding the results mod p resp. mod q. */ + mbedtls_mpi TP, TQ; + + /* Temporaries holding the blinded exponents for + * the mod p resp. mod q computation (if used). */ + mbedtls_mpi DP_blind, DQ_blind; + + /* Pointers to actual exponents to be used - either the unblinded + * or the blinded ones, depending on the presence of a PRNG. */ + mbedtls_mpi *DP = &ctx->DP; + mbedtls_mpi *DQ = &ctx->DQ; +#else + /* Temporary holding the blinded exponent (if used). */ + mbedtls_mpi D_blind; + + /* Pointer to actual exponent to be used - either the unblinded + * or the blinded one, depending on the presence of a PRNG. */ + mbedtls_mpi *D = &ctx->D; +#endif /* MBEDTLS_RSA_NO_CRT */ + + /* Temporaries holding the initial input and the double + * checked result; should be the same in the end. */ + mbedtls_mpi I, C; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( input != NULL ); + RSA_VALIDATE_RET( output != NULL ); + + if( rsa_check_context( ctx, 1 /* private key checks */, + f_rng != NULL /* blinding y/n */ ) != 0 ) + { + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_THREADING_C) + if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 ) + return( ret ); +#endif + + /* MPI Initialization */ + mbedtls_mpi_init( &T ); + + mbedtls_mpi_init( &P1 ); + mbedtls_mpi_init( &Q1 ); + mbedtls_mpi_init( &R ); + + if( f_rng != NULL ) + { +#if defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_init( &D_blind ); +#else + mbedtls_mpi_init( &DP_blind ); + mbedtls_mpi_init( &DQ_blind ); +#endif + } + +#if !defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_init( &TP ); mbedtls_mpi_init( &TQ ); +#endif + + mbedtls_mpi_init( &I ); + mbedtls_mpi_init( &C ); + + /* End of MPI initialization */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &T, input, ctx->len ) ); + if( mbedtls_mpi_cmp_mpi( &T, &ctx->N ) >= 0 ) + { + ret = MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + goto cleanup; + } + +#if defined(NU_CRYPTO_RSA_ENABLE) + hw_decrypt_norm_capable = crypto_rsa_decrypt_norm_capable(ctx, f_rng != NULL); +#if !defined(MBEDTLS_RSA_NO_CRT) + hw_decrypt_crt_capable = crypto_rsa_decrypt_crt_capable(ctx, f_rng != NULL); +#endif + + if (!ctx->hw_init) { + ctx->hw_init = (crypto_rsa_init(ctx) == 0) ? 1 : 0; + } + + hw_go = (hw_decrypt_norm_capable || +#if !defined(MBEDTLS_RSA_NO_CRT) + hw_decrypt_crt_capable || +#endif + 0) && ctx->hw_init; + +#if !defined(MBEDTLS_RSA_NO_CRT) + /* Go CRT if capable, or normal */ + if (hw_decrypt_crt_capable && hw_go) { + ret = crypto_rsa_decrypt_crt(ctx, f_rng != NULL, input, output); + if (ret == 0) { + goto cleanup; + } + + /* Fall back to H/W normal */ + } +#endif + + if (hw_decrypt_norm_capable && hw_go) { + ret = crypto_rsa_decrypt_norm(ctx, f_rng != NULL, input, output); + if (ret == 0) { + goto cleanup; + } + + /* Fall back to S/W on H/W failure */ + sw_fallback = true; + } +#endif /* NU_CRYPTO_RSA_ENABLE */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &I, &T ) ); + + if( f_rng != NULL ) + { + /* + * Blinding + * T = T * Vi mod N + */ + MBEDTLS_MPI_CHK( rsa_prepare_blinding( ctx, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &T, &ctx->Vi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &T, &T, &ctx->N ) ); + + /* + * Exponent blinding + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &P1, &ctx->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &Q1, &ctx->Q, 1 ) ); + +#if defined(MBEDTLS_RSA_NO_CRT) + /* + * D_blind = ( P - 1 ) * ( Q - 1 ) * R + D + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &R, RSA_EXPONENT_BLINDING, + f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &D_blind, &P1, &Q1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &D_blind, &D_blind, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &D_blind, &D_blind, &ctx->D ) ); + + D = &D_blind; +#else + /* + * DP_blind = ( P - 1 ) * R + DP + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &R, RSA_EXPONENT_BLINDING, + f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &DP_blind, &P1, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &DP_blind, &DP_blind, + &ctx->DP ) ); + + DP = &DP_blind; + + /* + * DQ_blind = ( Q - 1 ) * R + DQ + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &R, RSA_EXPONENT_BLINDING, + f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &DQ_blind, &Q1, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &DQ_blind, &DQ_blind, + &ctx->DQ ) ); + + DQ = &DQ_blind; +#endif /* MBEDTLS_RSA_NO_CRT */ + } + +#if defined(MBEDTLS_RSA_NO_CRT) + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &T, &T, D, &ctx->N, &ctx->RN ) ); +#else + /* + * Faster decryption using the CRT + * + * TP = input ^ dP mod P + * TQ = input ^ dQ mod Q + */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &TP, &T, DP, &ctx->P, &ctx->RP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &TQ, &T, DQ, &ctx->Q, &ctx->RQ ) ); + + /* + * T = (TP - TQ) * (Q^-1 mod P) mod P + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &TP, &TQ ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &TP, &T, &ctx->QP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &T, &TP, &ctx->P ) ); + + /* + * T = TQ + T * Q + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &TP, &T, &ctx->Q ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &T, &TQ, &TP ) ); +#endif /* MBEDTLS_RSA_NO_CRT */ + + if( f_rng != NULL ) + { + /* + * Unblind + * T = T * Vf mod N + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &T, &ctx->Vf ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &T, &T, &ctx->N ) ); + } + + /* Verify the result to prevent glitching attacks. */ + MBEDTLS_MPI_CHK( mbedtls_mpi_exp_mod( &C, &T, &ctx->E, + &ctx->N, &ctx->RN ) ); + if( mbedtls_mpi_cmp_mpi( &C, &I ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_VERIFY_FAILED; + goto cleanup; + } + + olen = ctx->len; + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &T, output, olen ) ); + +cleanup: +#if defined(MBEDTLS_THREADING_C) + if( mbedtls_mutex_unlock( &ctx->mutex ) != 0 ) + return( MBEDTLS_ERR_THREADING_MUTEX_ERROR ); +#endif + + mbedtls_mpi_free( &P1 ); + mbedtls_mpi_free( &Q1 ); + mbedtls_mpi_free( &R ); + + if( f_rng != NULL ) + { +#if defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_free( &D_blind ); +#else + mbedtls_mpi_free( &DP_blind ); + mbedtls_mpi_free( &DQ_blind ); +#endif + } + + mbedtls_mpi_free( &T ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_free( &TP ); mbedtls_mpi_free( &TQ ); +#endif + + mbedtls_mpi_free( &C ); + mbedtls_mpi_free( &I ); + +#if defined(NU_CRYPTO_RSA_ENABLE) + if (hw_go) { + /* Premature return on H/W success, or continue to do other S/W clean-up + * because it is involved as fallback. */ + if (!sw_fallback) { + return ret; + } + } +#endif + + if( ret != 0 ) + return( MBEDTLS_ERR_RSA_PRIVATE_FAILED + ret ); + + return( 0 ); +} + +#if defined(MBEDTLS_PKCS1_V21) +/** + * Generate and apply the MGF1 operation (from PKCS#1 v2.1) to a buffer. + * + * \param dst buffer to mask + * \param dlen length of destination buffer + * \param src source of the mask generation + * \param slen length of the source buffer + * \param md_ctx message digest context to use + */ +static int mgf_mask( unsigned char *dst, size_t dlen, unsigned char *src, + size_t slen, mbedtls_md_context_t *md_ctx ) +{ + unsigned char mask[MBEDTLS_MD_MAX_SIZE]; + unsigned char counter[4]; + unsigned char *p; + unsigned int hlen; + size_t i, use_len; + int ret = 0; + + memset( mask, 0, MBEDTLS_MD_MAX_SIZE ); + memset( counter, 0, 4 ); + + hlen = mbedtls_md_get_size( md_ctx->md_info ); + + /* Generate and apply dbMask */ + p = dst; + + while( dlen > 0 ) + { + use_len = hlen; + if( dlen < hlen ) + use_len = dlen; + + if( ( ret = mbedtls_md_starts( md_ctx ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( md_ctx, src, slen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( md_ctx, counter, 4 ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_finish( md_ctx, mask ) ) != 0 ) + goto exit; + + for( i = 0; i < use_len; ++i ) + *p++ ^= mask[i]; + + counter[3]++; + + dlen -= use_len; + } + +exit: + mbedtls_platform_zeroize( mask, sizeof( mask ) ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSAES-OAEP-ENCRYPT function + */ +int mbedtls_rsa_rsaes_oaep_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + const unsigned char *label, size_t label_len, + size_t ilen, + const unsigned char *input, + unsigned char *output ) +{ + size_t olen; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char *p = output; + unsigned int hlen; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( output != NULL ); + RSA_VALIDATE_RET( ilen == 0 || input != NULL ); + RSA_VALIDATE_RET( label_len == 0 || label != NULL ); + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( f_rng == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + md_info = mbedtls_md_info_from_type( (mbedtls_md_type_t) ctx->hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + olen = ctx->len; + hlen = mbedtls_md_get_size( md_info ); + + /* first comparison checks for overflow */ + if( ilen + 2 * hlen + 2 < ilen || olen < ilen + 2 * hlen + 2 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + memset( output, 0, olen ); + + *p++ = 0; + + /* Generate a random octet string seed */ + if( ( ret = f_rng( p_rng, p, hlen ) ) != 0 ) + return( MBEDTLS_ERR_RSA_RNG_FAILED + ret ); + + p += hlen; + + /* Construct DB */ + if( ( ret = mbedtls_md( md_info, label, label_len, p ) ) != 0 ) + return( ret ); + p += hlen; + p += olen - 2 * hlen - 2 - ilen; + *p++ = 1; + if( ilen != 0 ) + memcpy( p, input, ilen ); + + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + goto exit; + + /* maskedDB: Apply dbMask to DB */ + if( ( ret = mgf_mask( output + hlen + 1, olen - hlen - 1, output + 1, hlen, + &md_ctx ) ) != 0 ) + goto exit; + + /* maskedSeed: Apply seedMask to seed */ + if( ( ret = mgf_mask( output + 1, hlen, output + hlen + 1, olen - hlen - 1, + &md_ctx ) ) != 0 ) + goto exit; + +exit: + mbedtls_md_free( &md_ctx ); + + if( ret != 0 ) + return( ret ); + + return( ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, output, output ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, output, output ) ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/* + * Implementation of the PKCS#1 v2.1 RSAES-PKCS1-V1_5-ENCRYPT function + */ +int mbedtls_rsa_rsaes_pkcs1_v15_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output ) +{ + size_t nb_pad, olen; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char *p = output; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( output != NULL ); + RSA_VALIDATE_RET( ilen == 0 || input != NULL ); + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + olen = ctx->len; + + /* first comparison checks for overflow */ + if( ilen + 11 < ilen || olen < ilen + 11 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + nb_pad = olen - 3 - ilen; + + *p++ = 0; + if( mode == MBEDTLS_RSA_PUBLIC ) + { + if( f_rng == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + *p++ = MBEDTLS_RSA_CRYPT; + + while( nb_pad-- > 0 ) + { + int rng_dl = 100; + + do { + ret = f_rng( p_rng, p, 1 ); + } while( *p == 0 && --rng_dl && ret == 0 ); + + /* Check if RNG failed to generate data */ + if( rng_dl == 0 || ret != 0 ) + return( MBEDTLS_ERR_RSA_RNG_FAILED + ret ); + + p++; + } + } + else + { + *p++ = MBEDTLS_RSA_SIGN; + + while( nb_pad-- > 0 ) + *p++ = 0xFF; + } + + *p++ = 0; + if( ilen != 0 ) + memcpy( p, input, ilen ); + + return( ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, output, output ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, output, output ) ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Add the message padding, then do an RSA operation + */ +int mbedtls_rsa_pkcs1_encrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output ) +{ + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( output != NULL ); + RSA_VALIDATE_RET( ilen == 0 || input != NULL ); + + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsaes_pkcs1_v15_encrypt( ctx, f_rng, p_rng, mode, ilen, + input, output ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsaes_oaep_encrypt( ctx, f_rng, p_rng, mode, NULL, 0, + ilen, input, output ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSAES-OAEP-DECRYPT function + */ +int mbedtls_rsa_rsaes_oaep_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + const unsigned char *label, size_t label_len, + size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t ilen, i, pad_len; + unsigned char *p, bad, pad_done; + unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; + unsigned char lhash[MBEDTLS_MD_MAX_SIZE]; + unsigned int hlen; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( output_max_len == 0 || output != NULL ); + RSA_VALIDATE_RET( label_len == 0 || label != NULL ); + RSA_VALIDATE_RET( input != NULL ); + RSA_VALIDATE_RET( olen != NULL ); + + /* + * Parameters sanity checks + */ + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + ilen = ctx->len; + + if( ilen < 16 || ilen > sizeof( buf ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + md_info = mbedtls_md_info_from_type( (mbedtls_md_type_t) ctx->hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hlen = mbedtls_md_get_size( md_info ); + + // checking for integer underflow + if( 2 * hlen + 2 > ilen ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * RSA operation + */ + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, input, buf ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, input, buf ); + + if( ret != 0 ) + goto cleanup; + + /* + * Unmask data and generate lHash + */ + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + { + mbedtls_md_free( &md_ctx ); + goto cleanup; + } + + /* seed: Apply seedMask to maskedSeed */ + if( ( ret = mgf_mask( buf + 1, hlen, buf + hlen + 1, ilen - hlen - 1, + &md_ctx ) ) != 0 || + /* DB: Apply dbMask to maskedDB */ + ( ret = mgf_mask( buf + hlen + 1, ilen - hlen - 1, buf + 1, hlen, + &md_ctx ) ) != 0 ) + { + mbedtls_md_free( &md_ctx ); + goto cleanup; + } + + mbedtls_md_free( &md_ctx ); + + /* Generate lHash */ + if( ( ret = mbedtls_md( md_info, label, label_len, lhash ) ) != 0 ) + goto cleanup; + + /* + * Check contents, in "constant-time" + */ + p = buf; + bad = 0; + + bad |= *p++; /* First byte must be 0 */ + + p += hlen; /* Skip seed */ + + /* Check lHash */ + for( i = 0; i < hlen; i++ ) + bad |= lhash[i] ^ *p++; + + /* Get zero-padding len, but always read till end of buffer + * (minus one, for the 01 byte) */ + pad_len = 0; + pad_done = 0; + for( i = 0; i < ilen - 2 * hlen - 2; i++ ) + { + pad_done |= p[i]; + pad_len += ((pad_done | (unsigned char)-pad_done) >> 7) ^ 1; + } + + p += pad_len; + bad |= *p++ ^ 0x01; + + /* + * The only information "leaked" is whether the padding was correct or not + * (eg, no data is copied if it was not correct). This meets the + * recommendations in PKCS#1 v2.2: an opponent cannot distinguish between + * the different error conditions. + */ + if( bad != 0 ) + { + ret = MBEDTLS_ERR_RSA_INVALID_PADDING; + goto cleanup; + } + + if( ilen - ( p - buf ) > output_max_len ) + { + ret = MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE; + goto cleanup; + } + + *olen = ilen - (p - buf); + if( *olen != 0 ) + memcpy( output, p, *olen ); + ret = 0; + +cleanup: + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + mbedtls_platform_zeroize( lhash, sizeof( lhash ) ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/** Turn zero-or-nonzero into zero-or-all-bits-one, without branches. + * + * \param value The value to analyze. + * \return Zero if \p value is zero, otherwise all-bits-one. + */ +static unsigned all_or_nothing_int( unsigned value ) +{ + /* MSVC has a warning about unary minus on unsigned, but this is + * well-defined and precisely what we want to do here */ +#if defined(_MSC_VER) +#pragma warning( push ) +#pragma warning( disable : 4146 ) +#endif + return( - ( ( value | - value ) >> ( sizeof( value ) * 8 - 1 ) ) ); +#if defined(_MSC_VER) +#pragma warning( pop ) +#endif +} + +/** Check whether a size is out of bounds, without branches. + * + * This is equivalent to `size > max`, but is likely to be compiled to + * to code using bitwise operation rather than a branch. + * + * \param size Size to check. + * \param max Maximum desired value for \p size. + * \return \c 0 if `size <= max`. + * \return \c 1 if `size > max`. + */ +static unsigned size_greater_than( size_t size, size_t max ) +{ + /* Return the sign bit (1 for negative) of (max - size). */ + return( ( max - size ) >> ( sizeof( size_t ) * 8 - 1 ) ); +} + +/** Choose between two integer values, without branches. + * + * This is equivalent to `cond ? if1 : if0`, but is likely to be compiled + * to code using bitwise operation rather than a branch. + * + * \param cond Condition to test. + * \param if1 Value to use if \p cond is nonzero. + * \param if0 Value to use if \p cond is zero. + * \return \c if1 if \p cond is nonzero, otherwise \c if0. + */ +static unsigned if_int( unsigned cond, unsigned if1, unsigned if0 ) +{ + unsigned mask = all_or_nothing_int( cond ); + return( ( mask & if1 ) | (~mask & if0 ) ); +} + +/** Shift some data towards the left inside a buffer without leaking + * the length of the data through side channels. + * + * `mem_move_to_left(start, total, offset)` is functionally equivalent to + * ``` + * memmove(start, start + offset, total - offset); + * memset(start + offset, 0, total - offset); + * ``` + * but it strives to use a memory access pattern (and thus total timing) + * that does not depend on \p offset. This timing independence comes at + * the expense of performance. + * + * \param start Pointer to the start of the buffer. + * \param total Total size of the buffer. + * \param offset Offset from which to copy \p total - \p offset bytes. + */ +static void mem_move_to_left( void *start, + size_t total, + size_t offset ) +{ + volatile unsigned char *buf = start; + size_t i, n; + if( total == 0 ) + return; + for( i = 0; i < total; i++ ) + { + unsigned no_op = size_greater_than( total - offset, i ); + /* The first `total - offset` passes are a no-op. The last + * `offset` passes shift the data one byte to the left and + * zero out the last byte. */ + for( n = 0; n < total - 1; n++ ) + { + unsigned char current = buf[n]; + unsigned char next = buf[n+1]; + buf[n] = if_int( no_op, current, next ); + } + buf[total-1] = if_int( no_op, buf[total-1], 0 ); + } +} + +/* + * Implementation of the PKCS#1 v2.1 RSAES-PKCS1-V1_5-DECRYPT function + */ +int mbedtls_rsa_rsaes_pkcs1_v15_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t ilen, i, plaintext_max_size; + unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; + /* The following variables take sensitive values: their value must + * not leak into the observable behavior of the function other than + * the designated outputs (output, olen, return value). Otherwise + * this would open the execution of the function to + * side-channel-based variants of the Bleichenbacher padding oracle + * attack. Potential side channels include overall timing, memory + * access patterns (especially visible to an adversary who has access + * to a shared memory cache), and branches (especially visible to + * an adversary who has access to a shared code cache or to a shared + * branch predictor). */ + size_t pad_count = 0; + unsigned bad = 0; + unsigned char pad_done = 0; + size_t plaintext_size = 0; + unsigned output_too_large; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( output_max_len == 0 || output != NULL ); + RSA_VALIDATE_RET( input != NULL ); + RSA_VALIDATE_RET( olen != NULL ); + + ilen = ctx->len; + plaintext_max_size = ( output_max_len > ilen - 11 ? + ilen - 11 : + output_max_len ); + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( ilen < 16 || ilen > sizeof( buf ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, input, buf ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, input, buf ); + + if( ret != 0 ) + goto cleanup; + + /* Check and get padding length in constant time and constant + * memory trace. The first byte must be 0. */ + bad |= buf[0]; + + if( mode == MBEDTLS_RSA_PRIVATE ) + { + /* Decode EME-PKCS1-v1_5 padding: 0x00 || 0x02 || PS || 0x00 + * where PS must be at least 8 nonzero bytes. */ + bad |= buf[1] ^ MBEDTLS_RSA_CRYPT; + + /* Read the whole buffer. Set pad_done to nonzero if we find + * the 0x00 byte and remember the padding length in pad_count. */ + for( i = 2; i < ilen; i++ ) + { + pad_done |= ((buf[i] | (unsigned char)-buf[i]) >> 7) ^ 1; + pad_count += ((pad_done | (unsigned char)-pad_done) >> 7) ^ 1; + } + } + else + { + /* Decode EMSA-PKCS1-v1_5 padding: 0x00 || 0x01 || PS || 0x00 + * where PS must be at least 8 bytes with the value 0xFF. */ + bad |= buf[1] ^ MBEDTLS_RSA_SIGN; + + /* Read the whole buffer. Set pad_done to nonzero if we find + * the 0x00 byte and remember the padding length in pad_count. + * If there's a non-0xff byte in the padding, the padding is bad. */ + for( i = 2; i < ilen; i++ ) + { + pad_done |= if_int( buf[i], 0, 1 ); + pad_count += if_int( pad_done, 0, 1 ); + bad |= if_int( pad_done, 0, buf[i] ^ 0xFF ); + } + } + + /* If pad_done is still zero, there's no data, only unfinished padding. */ + bad |= if_int( pad_done, 0, 1 ); + + /* There must be at least 8 bytes of padding. */ + bad |= size_greater_than( 8, pad_count ); + + /* If the padding is valid, set plaintext_size to the number of + * remaining bytes after stripping the padding. If the padding + * is invalid, avoid leaking this fact through the size of the + * output: use the maximum message size that fits in the output + * buffer. Do it without branches to avoid leaking the padding + * validity through timing. RSA keys are small enough that all the + * size_t values involved fit in unsigned int. */ + plaintext_size = if_int( bad, + (unsigned) plaintext_max_size, + (unsigned) ( ilen - pad_count - 3 ) ); + + /* Set output_too_large to 0 if the plaintext fits in the output + * buffer and to 1 otherwise. */ + output_too_large = size_greater_than( plaintext_size, + plaintext_max_size ); + + /* Set ret without branches to avoid timing attacks. Return: + * - INVALID_PADDING if the padding is bad (bad != 0). + * - OUTPUT_TOO_LARGE if the padding is good but the decrypted + * plaintext does not fit in the output buffer. + * - 0 if the padding is correct. */ + ret = - (int) if_int( bad, - MBEDTLS_ERR_RSA_INVALID_PADDING, + if_int( output_too_large, - MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE, + 0 ) ); + + /* If the padding is bad or the plaintext is too large, zero the + * data that we're about to copy to the output buffer. + * We need to copy the same amount of data + * from the same buffer whether the padding is good or not to + * avoid leaking the padding validity through overall timing or + * through memory or cache access patterns. */ + bad = all_or_nothing_int( bad | output_too_large ); + for( i = 11; i < ilen; i++ ) + buf[i] &= ~bad; + + /* If the plaintext is too large, truncate it to the buffer size. + * Copy anyway to avoid revealing the length through timing, because + * revealing the length is as bad as revealing the padding validity + * for a Bleichenbacher attack. */ + plaintext_size = if_int( output_too_large, + (unsigned) plaintext_max_size, + (unsigned) plaintext_size ); + + /* Move the plaintext to the leftmost position where it can start in + * the working buffer, i.e. make it start plaintext_max_size from + * the end of the buffer. Do this with a memory access trace that + * does not depend on the plaintext size. After this move, the + * starting location of the plaintext is no longer sensitive + * information. */ + mem_move_to_left( buf + ilen - plaintext_max_size, + plaintext_max_size, + plaintext_max_size - plaintext_size ); + + /* Finally copy the decrypted plaintext plus trailing zeros into the output + * buffer. If output_max_len is 0, then output may be an invalid pointer + * and the result of memcpy() would be undefined; prevent undefined + * behavior making sure to depend only on output_max_len (the size of the + * user-provided output buffer), which is independent from plaintext + * length, validity of padding, success of the decryption, and other + * secrets. */ + if( output_max_len != 0 ) + memcpy( output, buf + ilen - plaintext_max_size, plaintext_max_size ); + + /* Report the amount of data we copied to the output buffer. In case + * of errors (bad padding or output too large), the value of *olen + * when this function returns is not specified. Making it equivalent + * to the good case limits the risks of leaking the padding validity. */ + *olen = plaintext_size; + +cleanup: + mbedtls_platform_zeroize( buf, sizeof( buf ) ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Do an RSA operation, then remove the message padding + */ +int mbedtls_rsa_pkcs1_decrypt( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len) +{ + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( output_max_len == 0 || output != NULL ); + RSA_VALIDATE_RET( input != NULL ); + RSA_VALIDATE_RET( olen != NULL ); + + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsaes_pkcs1_v15_decrypt( ctx, f_rng, p_rng, mode, olen, + input, output, output_max_len ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsaes_oaep_decrypt( ctx, f_rng, p_rng, mode, NULL, 0, + olen, input, output, + output_max_len ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PSS-SIGN function + */ +int mbedtls_rsa_rsassa_pss_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ) +{ + size_t olen; + unsigned char *p = sig; + unsigned char salt[MBEDTLS_MD_MAX_SIZE]; + size_t slen, min_slen, hlen, offset = 0; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t msb; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && + hashlen == 0 ) || + hash != NULL ); + RSA_VALIDATE_RET( sig != NULL ); + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( f_rng == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + olen = ctx->len; + + if( md_alg != MBEDTLS_MD_NONE ) + { + /* Gather length of hash to sign */ + md_info = mbedtls_md_info_from_type( md_alg ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hashlen = mbedtls_md_get_size( md_info ); + } + + md_info = mbedtls_md_info_from_type( (mbedtls_md_type_t) ctx->hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hlen = mbedtls_md_get_size( md_info ); + + /* Calculate the largest possible salt length. Normally this is the hash + * length, which is the maximum length the salt can have. If there is not + * enough room, use the maximum salt length that fits. The constraint is + * that the hash length plus the salt length plus 2 bytes must be at most + * the key length. This complies with FIPS 186-4 §5.5 (e) and RFC 8017 + * (PKCS#1 v2.2) §9.1.1 step 3. */ + min_slen = hlen - 2; + if( olen < hlen + min_slen + 2 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + else if( olen >= hlen + hlen + 2 ) + slen = hlen; + else + slen = olen - hlen - 2; + + memset( sig, 0, olen ); + + /* Generate salt of length slen */ + if( ( ret = f_rng( p_rng, salt, slen ) ) != 0 ) + return( MBEDTLS_ERR_RSA_RNG_FAILED + ret ); + + /* Note: EMSA-PSS encoding is over the length of N - 1 bits */ + msb = mbedtls_mpi_bitlen( &ctx->N ) - 1; + p += olen - hlen - slen - 2; + *p++ = 0x01; + memcpy( p, salt, slen ); + p += slen; + + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + goto exit; + + /* Generate H = Hash( M' ) */ + if( ( ret = mbedtls_md_starts( &md_ctx ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( &md_ctx, p, 8 ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( &md_ctx, hash, hashlen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_update( &md_ctx, salt, slen ) ) != 0 ) + goto exit; + if( ( ret = mbedtls_md_finish( &md_ctx, p ) ) != 0 ) + goto exit; + + /* Compensate for boundary condition when applying mask */ + if( msb % 8 == 0 ) + offset = 1; + + /* maskedDB: Apply dbMask to DB */ + if( ( ret = mgf_mask( sig + offset, olen - hlen - 1 - offset, p, hlen, + &md_ctx ) ) != 0 ) + goto exit; + + msb = mbedtls_mpi_bitlen( &ctx->N ) - 1; + sig[0] &= 0xFF >> ( olen * 8 - msb ); + + p += hlen; + *p++ = 0xBC; + + mbedtls_platform_zeroize( salt, sizeof( salt ) ); + +exit: + mbedtls_md_free( &md_ctx ); + + if( ret != 0 ) + return( ret ); + + return( ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, sig, sig ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, sig, sig ) ); +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PKCS1-V1_5-SIGN function + */ + +/* Construct a PKCS v1.5 encoding of a hashed message + * + * This is used both for signature generation and verification. + * + * Parameters: + * - md_alg: Identifies the hash algorithm used to generate the given hash; + * MBEDTLS_MD_NONE if raw data is signed. + * - hashlen: Length of hash in case hashlen is MBEDTLS_MD_NONE. + * - hash: Buffer containing the hashed message or the raw data. + * - dst_len: Length of the encoded message. + * - dst: Buffer to hold the encoded message. + * + * Assumptions: + * - hash has size hashlen if md_alg == MBEDTLS_MD_NONE. + * - hash has size corresponding to md_alg if md_alg != MBEDTLS_MD_NONE. + * - dst points to a buffer of size at least dst_len. + * + */ +static int rsa_rsassa_pkcs1_v15_encode( mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + size_t dst_len, + unsigned char *dst ) +{ + size_t oid_size = 0; + size_t nb_pad = dst_len; + unsigned char *p = dst; + const char *oid = NULL; + + /* Are we signing hashed or raw data? */ + if( md_alg != MBEDTLS_MD_NONE ) + { + const mbedtls_md_info_t *md_info = mbedtls_md_info_from_type( md_alg ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + if( mbedtls_oid_get_oid_by_md( md_alg, &oid, &oid_size ) != 0 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hashlen = mbedtls_md_get_size( md_info ); + + /* Double-check that 8 + hashlen + oid_size can be used as a + * 1-byte ASN.1 length encoding and that there's no overflow. */ + if( 8 + hashlen + oid_size >= 0x80 || + 10 + hashlen < hashlen || + 10 + hashlen + oid_size < 10 + hashlen ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Static bounds check: + * - Need 10 bytes for five tag-length pairs. + * (Insist on 1-byte length encodings to protect against variants of + * Bleichenbacher's forgery attack against lax PKCS#1v1.5 verification) + * - Need hashlen bytes for hash + * - Need oid_size bytes for hash alg OID. + */ + if( nb_pad < 10 + hashlen + oid_size ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + nb_pad -= 10 + hashlen + oid_size; + } + else + { + if( nb_pad < hashlen ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + nb_pad -= hashlen; + } + + /* Need space for signature header and padding delimiter (3 bytes), + * and 8 bytes for the minimal padding */ + if( nb_pad < 3 + 8 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + nb_pad -= 3; + + /* Now nb_pad is the amount of memory to be filled + * with padding, and at least 8 bytes long. */ + + /* Write signature header and padding */ + *p++ = 0; + *p++ = MBEDTLS_RSA_SIGN; + memset( p, 0xFF, nb_pad ); + p += nb_pad; + *p++ = 0; + + /* Are we signing raw data? */ + if( md_alg == MBEDTLS_MD_NONE ) + { + memcpy( p, hash, hashlen ); + return( 0 ); + } + + /* Signing hashed data, add corresponding ASN.1 structure + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm DigestAlgorithmIdentifier, + * digest Digest } + * DigestAlgorithmIdentifier ::= AlgorithmIdentifier + * Digest ::= OCTET STRING + * + * Schematic: + * TAG-SEQ + LEN [ TAG-SEQ + LEN [ TAG-OID + LEN [ OID ] + * TAG-NULL + LEN [ NULL ] ] + * TAG-OCTET + LEN [ HASH ] ] + */ + *p++ = MBEDTLS_ASN1_SEQUENCE | MBEDTLS_ASN1_CONSTRUCTED; + *p++ = (unsigned char)( 0x08 + oid_size + hashlen ); + *p++ = MBEDTLS_ASN1_SEQUENCE | MBEDTLS_ASN1_CONSTRUCTED; + *p++ = (unsigned char)( 0x04 + oid_size ); + *p++ = MBEDTLS_ASN1_OID; + *p++ = (unsigned char) oid_size; + memcpy( p, oid, oid_size ); + p += oid_size; + *p++ = MBEDTLS_ASN1_NULL; + *p++ = 0x00; + *p++ = MBEDTLS_ASN1_OCTET_STRING; + *p++ = (unsigned char) hashlen; + memcpy( p, hash, hashlen ); + p += hashlen; + + /* Just a sanity-check, should be automatic + * after the initial bounds check. */ + if( p != dst + dst_len ) + { + mbedtls_platform_zeroize( dst, dst_len ); + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + } + + return( 0 ); +} + +/* + * Do an RSA operation to sign the message digest + */ +int mbedtls_rsa_rsassa_pkcs1_v15_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char *sig_try = NULL, *verif = NULL; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && + hashlen == 0 ) || + hash != NULL ); + RSA_VALIDATE_RET( sig != NULL ); + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Prepare PKCS1-v1.5 encoding (padding and hash identifier) + */ + + if( ( ret = rsa_rsassa_pkcs1_v15_encode( md_alg, hashlen, hash, + ctx->len, sig ) ) != 0 ) + return( ret ); + + /* + * Call respective RSA primitive + */ + + if( mode == MBEDTLS_RSA_PUBLIC ) + { + /* Skip verification on a public key operation */ + return( mbedtls_rsa_public( ctx, sig, sig ) ); + } + + /* Private key operation + * + * In order to prevent Lenstra's attack, make the signature in a + * temporary buffer and check it before returning it. + */ + + sig_try = mbedtls_calloc( 1, ctx->len ); + if( sig_try == NULL ) + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + + verif = mbedtls_calloc( 1, ctx->len ); + if( verif == NULL ) + { + mbedtls_free( sig_try ); + return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); + } + + MBEDTLS_MPI_CHK( mbedtls_rsa_private( ctx, f_rng, p_rng, sig, sig_try ) ); + MBEDTLS_MPI_CHK( mbedtls_rsa_public( ctx, sig_try, verif ) ); + + if( mbedtls_safer_memcmp( verif, sig, ctx->len ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_PRIVATE_FAILED; + goto cleanup; + } + + memcpy( sig, sig_try, ctx->len ); + +cleanup: + mbedtls_free( sig_try ); + mbedtls_free( verif ); + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Do an RSA operation to sign the message digest + */ +int mbedtls_rsa_pkcs1_sign( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ) +{ + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && + hashlen == 0 ) || + hash != NULL ); + RSA_VALIDATE_RET( sig != NULL ); + + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsassa_pkcs1_v15_sign( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsassa_pss_sign( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +#if defined(MBEDTLS_PKCS1_V21) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PSS-VERIFY function + */ +int mbedtls_rsa_rsassa_pss_verify_ext( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + mbedtls_md_type_t mgf1_hash_id, + int expected_salt_len, + const unsigned char *sig ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t siglen; + unsigned char *p; + unsigned char *hash_start; + unsigned char result[MBEDTLS_MD_MAX_SIZE]; + unsigned char zeros[8]; + unsigned int hlen; + size_t observed_salt_len, msb; + const mbedtls_md_info_t *md_info; + mbedtls_md_context_t md_ctx; + unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( sig != NULL ); + RSA_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && + hashlen == 0 ) || + hash != NULL ); + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V21 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + siglen = ctx->len; + + if( siglen < 16 || siglen > sizeof( buf ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, sig, buf ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, sig, buf ); + + if( ret != 0 ) + return( ret ); + + p = buf; + + if( buf[siglen - 1] != 0xBC ) + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + + if( md_alg != MBEDTLS_MD_NONE ) + { + /* Gather length of hash to sign */ + md_info = mbedtls_md_info_from_type( md_alg ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hashlen = mbedtls_md_get_size( md_info ); + } + + md_info = mbedtls_md_info_from_type( mgf1_hash_id ); + if( md_info == NULL ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + hlen = mbedtls_md_get_size( md_info ); + + memset( zeros, 0, 8 ); + + /* + * Note: EMSA-PSS verification is over the length of N - 1 bits + */ + msb = mbedtls_mpi_bitlen( &ctx->N ) - 1; + + if( buf[0] >> ( 8 - siglen * 8 + msb ) ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* Compensate for boundary condition when applying mask */ + if( msb % 8 == 0 ) + { + p++; + siglen -= 1; + } + + if( siglen < hlen + 2 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + hash_start = p + siglen - hlen - 1; + + mbedtls_md_init( &md_ctx ); + if( ( ret = mbedtls_md_setup( &md_ctx, md_info, 0 ) ) != 0 ) + goto exit; + + ret = mgf_mask( p, siglen - hlen - 1, hash_start, hlen, &md_ctx ); + if( ret != 0 ) + goto exit; + + buf[0] &= 0xFF >> ( siglen * 8 - msb ); + + while( p < hash_start - 1 && *p == 0 ) + p++; + + if( *p++ != 0x01 ) + { + ret = MBEDTLS_ERR_RSA_INVALID_PADDING; + goto exit; + } + + observed_salt_len = hash_start - p; + + if( expected_salt_len != MBEDTLS_RSA_SALT_LEN_ANY && + observed_salt_len != (size_t) expected_salt_len ) + { + ret = MBEDTLS_ERR_RSA_INVALID_PADDING; + goto exit; + } + + /* + * Generate H = Hash( M' ) + */ + ret = mbedtls_md_starts( &md_ctx ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_update( &md_ctx, zeros, 8 ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_update( &md_ctx, hash, hashlen ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_update( &md_ctx, p, observed_salt_len ); + if ( ret != 0 ) + goto exit; + ret = mbedtls_md_finish( &md_ctx, result ); + if ( ret != 0 ) + goto exit; + + if( memcmp( hash_start, result, hlen ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_VERIFY_FAILED; + goto exit; + } + +exit: + mbedtls_md_free( &md_ctx ); + + return( ret ); +} + +/* + * Simplified PKCS#1 v2.1 RSASSA-PSS-VERIFY function + */ +int mbedtls_rsa_rsassa_pss_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ) +{ + mbedtls_md_type_t mgf1_hash_id; + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( sig != NULL ); + RSA_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && + hashlen == 0 ) || + hash != NULL ); + + mgf1_hash_id = ( ctx->hash_id != MBEDTLS_MD_NONE ) + ? (mbedtls_md_type_t) ctx->hash_id + : md_alg; + + return( mbedtls_rsa_rsassa_pss_verify_ext( ctx, f_rng, p_rng, mode, + md_alg, hashlen, hash, + mgf1_hash_id, MBEDTLS_RSA_SALT_LEN_ANY, + sig ) ); + +} +#endif /* MBEDTLS_PKCS1_V21 */ + +#if defined(MBEDTLS_PKCS1_V15) +/* + * Implementation of the PKCS#1 v2.1 RSASSA-PKCS1-v1_5-VERIFY function + */ +int mbedtls_rsa_rsassa_pkcs1_v15_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ) +{ + int ret = 0; + size_t sig_len; + unsigned char *encoded = NULL, *encoded_expected = NULL; + + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( sig != NULL ); + RSA_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && + hashlen == 0 ) || + hash != NULL ); + + sig_len = ctx->len; + + if( mode == MBEDTLS_RSA_PRIVATE && ctx->padding != MBEDTLS_RSA_PKCS_V15 ) + return( MBEDTLS_ERR_RSA_BAD_INPUT_DATA ); + + /* + * Prepare expected PKCS1 v1.5 encoding of hash. + */ + + if( ( encoded = mbedtls_calloc( 1, sig_len ) ) == NULL || + ( encoded_expected = mbedtls_calloc( 1, sig_len ) ) == NULL ) + { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + goto cleanup; + } + + if( ( ret = rsa_rsassa_pkcs1_v15_encode( md_alg, hashlen, hash, sig_len, + encoded_expected ) ) != 0 ) + goto cleanup; + + /* + * Apply RSA primitive to get what should be PKCS1 encoded hash. + */ + + ret = ( mode == MBEDTLS_RSA_PUBLIC ) + ? mbedtls_rsa_public( ctx, sig, encoded ) + : mbedtls_rsa_private( ctx, f_rng, p_rng, sig, encoded ); + if( ret != 0 ) + goto cleanup; + + /* + * Compare + */ + + if( ( ret = mbedtls_safer_memcmp( encoded, encoded_expected, + sig_len ) ) != 0 ) + { + ret = MBEDTLS_ERR_RSA_VERIFY_FAILED; + goto cleanup; + } + +cleanup: + + if( encoded != NULL ) + { + mbedtls_platform_zeroize( encoded, sig_len ); + mbedtls_free( encoded ); + } + + if( encoded_expected != NULL ) + { + mbedtls_platform_zeroize( encoded_expected, sig_len ); + mbedtls_free( encoded_expected ); + } + + return( ret ); +} +#endif /* MBEDTLS_PKCS1_V15 */ + +/* + * Do an RSA operation and check the message digest + */ +int mbedtls_rsa_pkcs1_verify( mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig ) +{ + RSA_VALIDATE_RET( ctx != NULL ); + RSA_VALIDATE_RET( mode == MBEDTLS_RSA_PRIVATE || + mode == MBEDTLS_RSA_PUBLIC ); + RSA_VALIDATE_RET( sig != NULL ); + RSA_VALIDATE_RET( ( md_alg == MBEDTLS_MD_NONE && + hashlen == 0 ) || + hash != NULL ); + + switch( ctx->padding ) + { +#if defined(MBEDTLS_PKCS1_V15) + case MBEDTLS_RSA_PKCS_V15: + return mbedtls_rsa_rsassa_pkcs1_v15_verify( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + +#if defined(MBEDTLS_PKCS1_V21) + case MBEDTLS_RSA_PKCS_V21: + return mbedtls_rsa_rsassa_pss_verify( ctx, f_rng, p_rng, mode, md_alg, + hashlen, hash, sig ); +#endif + + default: + return( MBEDTLS_ERR_RSA_INVALID_PADDING ); + } +} + +/* + * Copy the components of an RSA key + */ +int mbedtls_rsa_copy( mbedtls_rsa_context *dst, const mbedtls_rsa_context *src ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + RSA_VALIDATE_RET( dst != NULL ); + RSA_VALIDATE_RET( src != NULL ); + + dst->ver = src->ver; + dst->len = src->len; + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->N, &src->N ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->E, &src->E ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->D, &src->D ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->P, &src->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->Q, &src->Q ) ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->DP, &src->DP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->DQ, &src->DQ ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->QP, &src->QP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->RP, &src->RP ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->RQ, &src->RQ ) ); +#endif + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->RN, &src->RN ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->Vi, &src->Vi ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &dst->Vf, &src->Vf ) ); + + dst->padding = src->padding; + dst->hash_id = src->hash_id; + +cleanup: + if( ret != 0 ) + mbedtls_rsa_free( dst ); + + return( ret ); +} + +/* + * Free the components of an RSA key + */ +void mbedtls_rsa_free( mbedtls_rsa_context *ctx ) +{ + if( ctx == NULL ) + return; + +#if defined(NU_CRYPTO_RSA_ENABLE) + if (ctx->hw_init) { + crypto_rsa_free(ctx); + ctx->hw_init = 0; + } +#endif + + mbedtls_mpi_free( &ctx->Vi ); + mbedtls_mpi_free( &ctx->Vf ); + mbedtls_mpi_free( &ctx->RN ); + mbedtls_mpi_free( &ctx->D ); + mbedtls_mpi_free( &ctx->Q ); + mbedtls_mpi_free( &ctx->P ); + mbedtls_mpi_free( &ctx->E ); + mbedtls_mpi_free( &ctx->N ); + +#if !defined(MBEDTLS_RSA_NO_CRT) + mbedtls_mpi_free( &ctx->RQ ); + mbedtls_mpi_free( &ctx->RP ); + mbedtls_mpi_free( &ctx->QP ); + mbedtls_mpi_free( &ctx->DQ ); + mbedtls_mpi_free( &ctx->DP ); +#endif /* MBEDTLS_RSA_NO_CRT */ + +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_free( &ctx->mutex ); +#endif +} + +#endif /* MBEDTLS_RSA_ALT */ + +#endif /* MBEDTLS_RSA_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/rsa_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/rsa_alt.h new file mode 100644 index 0000000..86201c5 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/rsa/rsa_alt.h @@ -0,0 +1,109 @@ +/** + * \file rsa_alt.h + * + * \brief This file provides an API for the RSA public-key cryptosystem. + * + * The RSA public-key cryptosystem is defined in Public-Key + * Cryptography Standards (PKCS) #1 v1.5: RSA Encryption + * and Public-Key Cryptography Standards (PKCS) #1 v2.1: + * RSA Cryptography Specifications. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_RSA_ALT_H +#define MBEDTLS_RSA_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "mbedtls/bignum.h" +#include "mbedtls/md.h" + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_RSA_ALT) +// Regular implementation +// + +/* Enable Nuvoton's Crypto RSA H/W */ +#define NU_CRYPTO_RSA_ENABLE + +/** + * \brief The RSA context structure. + * + * \note Direct manipulation of the members of this structure + * is deprecated. All manipulation should instead be done through + * the public interface functions. + */ +typedef struct mbedtls_rsa_context +{ + int ver; /*!< Always 0.*/ + size_t len; /*!< The size of \p N in Bytes. */ + + mbedtls_mpi N; /*!< The public modulus. */ + mbedtls_mpi E; /*!< The public exponent. */ + + mbedtls_mpi D; /*!< The private exponent. */ + mbedtls_mpi P; /*!< The first prime factor. */ + mbedtls_mpi Q; /*!< The second prime factor. */ + + mbedtls_mpi DP; /*!< D % (P - 1). */ + mbedtls_mpi DQ; /*!< D % (Q - 1). */ + mbedtls_mpi QP; /*!< 1 / (Q % P). */ + + mbedtls_mpi RN; /*!< cached R^2 mod N. */ + + mbedtls_mpi RP; /*!< cached R^2 mod P. */ + mbedtls_mpi RQ; /*!< cached R^2 mod Q. */ + + mbedtls_mpi Vi; /*!< The cached blinding value. */ + mbedtls_mpi Vf; /*!< The cached un-blinding value. */ + + int padding; /*!< Selects padding mode: + #MBEDTLS_RSA_PKCS_V15 for 1.5 padding and + #MBEDTLS_RSA_PKCS_V21 for OAEP or PSS. */ + int hash_id; /*!< Hash identifier of mbedtls_md_type_t type, + as specified in md.h for use in the MGF + mask generating function used in the + EME-OAEP and EMSA-PSS encodings. */ +#if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t mutex; /*!< Thread-safety mutex. */ +#endif + +#if defined(NU_CRYPTO_RSA_ENABLE) + int hw_init; /*!< Initialized Crypto RSA H/W or not. */ +#endif +} +mbedtls_rsa_context; + +#endif /* MBEDTLS_RSA_ALT */ + +#ifdef __cplusplus +} +#endif + +#endif /* rsa_alt.h */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha1_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha1_alt.c new file mode 100644 index 0000000..b79130f --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha1_alt.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbedtls/sha1.h" + +#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_SHA1_ALT) + +#include "crypto-misc.h" +#include "nu_bitutil.h" +#include "string.h" + +void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +{ + crypto_sha_init(&ctx->hw_ctx, SHA_MODE_SHA1); +} + +void mbedtls_sha1_free(mbedtls_sha1_context *ctx) +{ + if (ctx == NULL) { + return; + } + + crypto_sha_free(&ctx->hw_ctx); +} + +void mbedtls_sha1_clone(mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src) +{ + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + memcpy(dst, src, sizeof(mbedtls_sha1_context)); +} + +/* + * SHA-1 context setup + */ +int mbedtls_sha1_starts_ret(mbedtls_sha1_context *ctx) +{ + if (ctx == NULL) { + return MBEDTLS_ERR_SHA1_BAD_INPUT_DATA; + } + + return crypto_sha_starts(&ctx->hw_ctx, 0); +} + +/* + * SHA-1 process buffer + */ +int mbedtls_sha1_update_ret(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen) +{ + if (ctx == NULL || (input == NULL && ilen == 0)) { + return MBEDTLS_ERR_SHA1_BAD_INPUT_DATA; + } + + return crypto_sha_update(&ctx->hw_ctx, input, ilen); +} + +/* + * SHA-1 final digest + */ +int mbedtls_sha1_finish_ret(mbedtls_sha1_context *ctx, unsigned char output[20]) +{ + if (ctx == NULL || output == NULL) { + return MBEDTLS_ERR_SHA1_BAD_INPUT_DATA; + } + + return crypto_sha_finish(&ctx->hw_ctx, output, 20); +} + +int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64]) +{ + if (ctx == NULL || data == NULL) { + return MBEDTLS_ERR_SHA1_BAD_INPUT_DATA; + } + + return crypto_sha_update(&ctx->hw_ctx, data, 64); +} + +#endif /* MBEDTLS_SHA1_ALT */ +#endif /* MBEDTLS_SHA1_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha1_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha1_alt.h new file mode 100644 index 0000000..3c4efda --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha1_alt.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SHA1_ALT_H +#define MBEDTLS_SHA1_ALT_H + +#include "mbedtls/sha1.h" + +#if defined(MBEDTLS_SHA1_ALT) + +#include "sha_alt_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct mbedtls_sha1_context_s; + +/** + * \brief SHA-1 context structure + */ +typedef struct mbedtls_sha1_context_s { + crypto_sha_context hw_ctx; +} +mbedtls_sha1_context; + +/** + * \brief Initialize SHA-1 context + * + * \param ctx SHA-1 context to be initialized + */ +void mbedtls_sha1_init( mbedtls_sha1_context *ctx ); + +/** + * \brief Clear SHA-1 context + * + * \param ctx SHA-1 context to be cleared + */ +void mbedtls_sha1_free( mbedtls_sha1_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-1 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void mbedtls_sha1_clone( mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src ); + +/** + * \brief SHA-1 context setup + * + * \param ctx context to be initialized + * + * \returns error code + */ +int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + * + * \returns error code + */ +int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + * + * \returns error code + */ +int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] ); + +/* Internal use */ +int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief SHA-1 context setup + * + * \deprecated Superseded by mbedtls_sha1_starts_ret() in 2.7.0 + * + * \param ctx The SHA-1 context to be initialized. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_sha1_starts( mbedtls_sha1_context *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \deprecated Superseded by mbedtls_sha1_update_ret() in 2.7.0 + * + * \param ctx The SHA-1 context. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_sha1_update( mbedtls_sha1_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief SHA-1 final digest + * + * \deprecated Superseded by mbedtls_sha1_finish_ret() in 2.7.0 + * + * \param ctx The SHA-1 context. + * \param output The SHA-1 checksum result. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, + unsigned char output[20] ); + +/** + * \brief SHA-1 process data block (internal use only) + * + * \deprecated Superseded by mbedtls_internal_sha1_process() in 2.7.0 + * + * \param ctx The SHA-1 context. + * \param data The data block being processed. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +MBEDTLS_DEPRECATED void mbedtls_sha1_process( mbedtls_sha1_context *ctx, + const unsigned char data[64] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SHA1_ALT */ + +#endif /* sha1_alt.h */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha256_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha256_alt.c new file mode 100644 index 0000000..82beab6 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha256_alt.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbedtls/sha256.h" + +#if defined(MBEDTLS_SHA256_C) +#if defined(MBEDTLS_SHA256_ALT) + +#include "crypto-misc.h" +#include "nu_bitutil.h" +#include "string.h" + +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +{ + crypto_sha_init(&ctx->hw_ctx, SHA_MODE_SHA256); +} + +void mbedtls_sha256_free(mbedtls_sha256_context *ctx) +{ + if (ctx == NULL) { + return; + } + + crypto_sha_free(&ctx->hw_ctx); +} + +void mbedtls_sha256_clone(mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src) +{ + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + memcpy(dst, src, sizeof(mbedtls_sha256_context)); +} + +/* + * SHA-256 context setup + */ +int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224) +{ + if (ctx == NULL) { + return MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; + } + + return crypto_sha_starts(&ctx->hw_ctx, is224); +} + +/* + * SHA-256 process buffer + */ +int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen) +{ + if (ctx == NULL || (input == NULL && ilen == 0)) { + return MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; + } + + return crypto_sha_update(&ctx->hw_ctx, input, ilen); +} + +/* + * SHA-256 final digest + */ +int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx, unsigned char output[32]) +{ + if (ctx == NULL || output == NULL) { + return MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; + } + + return crypto_sha_finish(&ctx->hw_ctx, output, ctx->hw_ctx.is224_384 ? 28 : 32); +} + +int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64]) +{ + if (ctx == NULL || data == NULL) { + return MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; + } + + return crypto_sha_update(&ctx->hw_ctx, data, 64); +} + +#endif /* MBEDTLS_SHA256_ALT */ +#endif /* MBEDTLS_SHA256_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha256_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha256_alt.h new file mode 100644 index 0000000..bd8669a --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha256_alt.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SHA256_ALT_H +#define MBEDTLS_SHA256_ALT_H + +#include "mbedtls/sha256.h" + +#if defined(MBEDTLS_SHA256_ALT) + +#include "sha_alt_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct mbedtls_sha256_context_s; + +/** + * \brief SHA-256 context structure + */ +typedef struct mbedtls_sha256_context_s { + crypto_sha_context hw_ctx; +} +mbedtls_sha256_context; + +/** + * \brief Initialize SHA-256 context + * + * \param ctx SHA-256 context to be initialized + */ +void mbedtls_sha256_init( mbedtls_sha256_context *ctx ); + +/** + * \brief Clear SHA-256 context + * + * \param ctx SHA-256 context to be cleared + */ +void mbedtls_sha256_free( mbedtls_sha256_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-256 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void mbedtls_sha256_clone( mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src ); + +/** + * \brief SHA-256 context setup + * + * \param ctx context to be initialized + * \param is224 0 = use SHA256, 1 = use SHA224 + * + * \returns error code + */ +int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224 ); + +/** + * \brief SHA-256 process buffer + * + * \param ctx SHA-256 context + * \param input buffer holding the data + * \param ilen length of the input data + * + * \returns error code + */ +int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char *input, + size_t ilen ); + +/** + * \brief SHA-256 final digest + * + * \param ctx SHA-256 context + * \param output SHA-224/256 checksum result + * + * \returns error code + */ +int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] ); + +/* Internal use */ +int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief This function starts a SHA-256 checksum calculation. + * + * \deprecated Superseded by mbedtls_sha256_starts_ret() in 2.7.0. + * + * \param ctx The SHA-256 context to initialize. + * \param is224 Determines which function to use. + *
  • 0: Use SHA-256.
    • + *
  • 1: Use SHA-224.
+ */ +MBEDTLS_DEPRECATED void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, + int is224 ); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-256 checksum calculation. + * + * \deprecated Superseded by mbedtls_sha256_update_ret() in 2.7.0. + * + * \param ctx The SHA-256 context to initialize. + * \param input The buffer holding the data. + * \param ilen The length of the input data. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256_update( mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief This function finishes the SHA-256 operation, and writes + * the result to the output buffer. + * + * \deprecated Superseded by mbedtls_sha256_finish_ret() in 2.7.0. + * + * \param ctx The SHA-256 context. + * \param output The SHA-224or SHA-256 checksum result. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, + unsigned char output[32] ); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-256 computation. This function is for + * internal use only. + * + * \deprecated Superseded by mbedtls_internal_sha256_process() in 2.7.0. + * + * \param ctx The SHA-256 context. + * \param data The buffer holding one block of data. + */ +MBEDTLS_DEPRECATED void mbedtls_sha256_process( mbedtls_sha256_context *ctx, + const unsigned char data[64] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SHA256_ALT */ + +#endif /* sha256_alt.h */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha512_alt.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha512_alt.c new file mode 100644 index 0000000..c6592d4 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha512_alt.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbedtls/sha512.h" + +#if defined(MBEDTLS_SHA512_C) +#if defined(MBEDTLS_SHA512_ALT) + +#include "crypto-misc.h" +#include "nu_bitutil.h" +#include "string.h" + +void mbedtls_sha512_init(mbedtls_sha512_context *ctx) +{ + crypto_sha_init(&ctx->hw_ctx, SHA_MODE_SHA512); +} + +void mbedtls_sha512_free(mbedtls_sha512_context *ctx) +{ + if (ctx == NULL) { + return; + } + + crypto_sha_free(&ctx->hw_ctx); +} + +void mbedtls_sha512_clone(mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src) +{ + // Corner case: Destination/source contexts are the same + if (dst == src) { + return; + } + + memcpy(dst, src, sizeof(mbedtls_sha512_context)); +} + +/* + * SHA-512 context setup + */ +int mbedtls_sha512_starts_ret(mbedtls_sha512_context *ctx, int is384) +{ + if (ctx == NULL) { + return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; + } + + return crypto_sha_starts(&ctx->hw_ctx, is384); +} + +/* + * SHA-512 process buffer + */ +int mbedtls_sha512_update_ret(mbedtls_sha512_context *ctx, const unsigned char *input, size_t ilen) +{ + if (ctx == NULL || (input == NULL && ilen == 0)) { + return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; + } + + return crypto_sha_update(&ctx->hw_ctx, input, ilen); +} + +/* + * SHA-512 final digest + */ +int mbedtls_sha512_finish_ret(mbedtls_sha512_context *ctx, unsigned char output[64]) +{ + if (ctx == NULL || output == NULL) { + return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; + } + + return crypto_sha_finish(&ctx->hw_ctx, output, ctx->hw_ctx.is224_384 ? 48 : 64); +} + +int mbedtls_internal_sha512_process(mbedtls_sha512_context *ctx, const unsigned char data[128]) +{ + if (ctx == NULL || data == NULL) { + return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; + } + + return crypto_sha_update(&ctx->hw_ctx, data, 128); +} + +#endif /* MBEDTLS_SHA512_ALT */ +#endif /* MBEDTLS_SHA512_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha512_alt.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha512_alt.h new file mode 100644 index 0000000..b6decc2 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha512_alt.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SHA512_ALT_H +#define MBEDTLS_SHA512_ALT_H + +#include "mbedtls/sha512.h" + +#if defined(MBEDTLS_SHA512_ALT) + +#include "sha_alt_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct mbedtls_sha512_context_s; + +/** + * \brief SHA-512 context structure + */ +typedef struct mbedtls_sha512_context_s { + crypto_sha_context hw_ctx; +} +mbedtls_sha512_context; + +/** + * \brief Initialize SHA-512 context + * + * \param ctx SHA-512 context to be initialized + */ +void mbedtls_sha512_init( mbedtls_sha512_context *ctx ); + +/** + * \brief Clear SHA-512 context + * + * \param ctx SHA-512 context to be cleared + */ +void mbedtls_sha512_free( mbedtls_sha512_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-512 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void mbedtls_sha512_clone( mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src ); + +/** + * \brief SHA-512 context setup + * + * \param ctx context to be initialized + * \param is384 0 = use SHA512, 1 = use SHA384 + * + * \returns error code + */ +int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 ); + +/** + * \brief SHA-512 process buffer + * + * \param ctx SHA-512 context + * \param input buffer holding the data + * \param ilen length of the input data + * + * \returns error code + */ +int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, const unsigned char *input, + size_t ilen ); + +/** + * \brief SHA-512 final digest + * + * \param ctx SHA-512 context + * \param output SHA-384/512 checksum result + * + * \returns error code + */ +int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, unsigned char output[64] ); + +/* Internal use */ +int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief This function starts a SHA-384 or SHA-512 checksum + * calculation. + * + * \deprecated Superseded by mbedtls_sha512_starts_ret() in 2.7.0 + * + * \param ctx The SHA-512 context to initialize. + * \param is384 Determines which function to use. + *
  • 0: Use SHA-512.
    • + *
  • 1: Use SHA-384.
+ */ +MBEDTLS_DEPRECATED void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, + int is384 ); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-512 checksum calculation. + * + * \deprecated Superseded by mbedtls_sha512_update_ret() in 2.7.0 + * + * \param ctx The SHA-512 context. + * \param input The buffer holding the data. + * \param ilen The length of the input data. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512_update( mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen ); + +/** + * \brief This function finishes the SHA-512 operation, and writes + * the result to the output buffer. + * + * \deprecated Superseded by mbedtls_sha512_finish_ret() in 2.7.0 + * + * \param ctx The SHA-512 context. + * \param output The SHA-384 or SHA-512 checksum result. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512_finish( mbedtls_sha512_context *ctx, + unsigned char output[64] ); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-512 computation. This function is for + * internal use only. + * + * \deprecated Superseded by mbedtls_internal_sha512_process() in 2.7.0 + * + * \param ctx The SHA-512 context. + * \param data The buffer holding one block of data. + */ +MBEDTLS_DEPRECATED void mbedtls_sha512_process( mbedtls_sha512_context *ctx, + const unsigned char data[128] ); + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SHA512_ALT */ + +#endif /* sha512_alt.h */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha_alt_hw.c b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha_alt_hw.c new file mode 100644 index 0000000..996315a --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha_alt_hw.c @@ -0,0 +1,349 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" + +#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C) +#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) + +#include "nu_bitutil.h" +#include "nu_timer.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "crypto-misc.h" + +#include + +/* SHA context for DMA */ +static struct { + MBED_ALIGN(4) + uint8_t block_imd[NU_CRYPTO_SHA_MAXSIZE_DMABLOCKRUN_BYTES]; // Intermediate data block in DMA mode + uint32_t fbinfo_imd[NU_CRYPTO_SHA_MAXSIZE_FBINFO_WORDS]; // Intermediate feedback information in DMA cascade mode + + const uint8_t *block_act; // Actual of above + uint32_t *fbinfo_act; // Actual of above +} dma_ctx_inst; + +/* Manage SHA H/W + * + * We follow the rules below to manage SHA H/W to share among contexts: + * 1. Go DMA cascade mode to support context save & restore. + * 2. Initialize/un-initialize crypto H/W at first context init/last context free. + * 3. All code involving SHA H/W are in between crypto_sha_acquire()/crypto_sha_release(). + * 4. Interrupt is enabled (SHA_ENABLE_INT()/SHA_DISABLE_INT()) only during real SHA H/W operation. + */ + +void crypto_sha_init(crypto_sha_context *ctx, uint32_t type) +{ + MBED_ASSERT(type == SHA_MODE_SHA1 || + type == SHA_MODE_SHA256 || + type == SHA_MODE_SHA512); + + /* Clean SHA context */ + crypto_zeroize(ctx, sizeof(*ctx)); + + /* SHA operation mode */ + ctx->type = type; + ctx->opmode = type; + + /* Mbed TLS error code for the SHA type */ + switch (type) { + case SHA_MODE_SHA1: + ctx->digestsize = 20; + ctx->err_hw_accel = MBEDTLS_ERR_SHA1_HW_ACCEL_FAILED; + ctx->err_bad_input = MBEDTLS_ERR_SHA1_BAD_INPUT_DATA; + break; + + case SHA_MODE_SHA256: + ctx->digestsize = 32; + ctx->err_hw_accel = MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED; + ctx->err_bad_input = MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; + break; + + case SHA_MODE_SHA512: + ctx->digestsize = 64; + ctx->err_hw_accel = MBEDTLS_ERR_SHA512_HW_ACCEL_FAILED; + ctx->err_bad_input = MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; + break; + + default: + MBED_ASSERT(0); + } + + /* Acquire ownership of SHA H/W */ + crypto_sha_acquire(); + + /* SHA H/W DMA buffer has the following requirements: + * (1) Word-aligned buffer base address + * (2) Word-aligned buffer size + * (3) Located in 0x20000000-0x2FFFFFFF region */ + if ((! crypto_dma_buff_compat(dma_ctx_inst.block_imd, sizeof(dma_ctx_inst.block_imd), 4)) || + (! crypto_dma_buff_compat(dma_ctx_inst.fbinfo_imd, sizeof(dma_ctx_inst.fbinfo_imd), 4))) { + error("Buffer for SHA H/W DMA requires to be word-aligned and located in 0x20000000-0x2FFFFFFF region."); + } + + /* Initialize crypto module */ + crypto_init(); + + /* Release ownership of SHA H/W */ + crypto_sha_release(); +} + +void crypto_sha_free(crypto_sha_context *ctx) +{ + if (ctx == NULL) { + return; + } + + /* Acquire ownership of SHA H/W */ + crypto_sha_acquire(); + + /* Un-initialize crypto module */ + crypto_uninit(); + + /* Release ownership of SHA H/W */ + crypto_sha_release(); + + /* Clean SHA context */ + crypto_zeroize(ctx, sizeof(*ctx)); +} + +int crypto_sha_starts(crypto_sha_context *ctx, int is224_384) +{ + MBED_ASSERT(ctx != NULL); + + /* NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it. */ + /* NOTE: In DMA cascade mode, re-configure SHA H/W instead of at start */ + + ctx->total = 0; + ctx->buffer_left = 0; + + switch (ctx->type) { + case SHA_MODE_SHA1: + ctx->blocksize = 64; + ctx->blocksize_mask = 0x3F; + break; + + case SHA_MODE_SHA256: + ctx->blocksize = 64; + ctx->blocksize_mask = 0x3F; + ctx->opmode = is224_384 ? SHA_MODE_SHA224 : SHA_MODE_SHA256; + ctx->digestsize = is224_384 ? 28 : 32; + break; + + case SHA_MODE_SHA512: + ctx->blocksize = 128; + ctx->blocksize_mask = 0x7F; + ctx->opmode = is224_384 ? SHA_MODE_SHA384 : SHA_MODE_SHA512; + ctx->digestsize = is224_384 ? 48 : 64; + break; + + default: + MBED_ASSERT(0); + } + + ctx->is224_384 = is224_384; + + return 0; +} + +int crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen) +{ + MBED_ASSERT(ctx != NULL); + + if (ilen == 0) { + return 0; + } + + MBED_ASSERT(input != NULL); + + int rc = 0; + + /* One complete block = above left + new input */ + size_t fill = ctx->blocksize - ctx->buffer_left; + if (ctx->buffer_left && ilen >= fill) { + memcpy((void *) (ctx->buffer + ctx->buffer_left), input, fill); + input += fill; + ilen -= fill; + ctx->buffer_left += fill; + MBED_ASSERT(ctx->buffer_left == ctx->blocksize); + rc = crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, (ctx->total == 0), 0); + if (rc != 0) { + return rc; + } + ctx->total += ctx->buffer_left; + ctx->buffer_left = 0; + } + + /* Complete blocks in block runs */ + while (ilen >= NU_CRYPTO_SHA_MAXSIZE_DMABLOCKRUN_BYTES) { + rc = crypto_sha_update_nobuf(ctx, input, NU_CRYPTO_SHA_MAXSIZE_DMABLOCKRUN_BYTES, (ctx->total == 0), 0); + if (rc != 0) { + return rc; + } + ctx->total += NU_CRYPTO_SHA_MAXSIZE_DMABLOCKRUN_BYTES; + input += NU_CRYPTO_SHA_MAXSIZE_DMABLOCKRUN_BYTES; + ilen -= NU_CRYPTO_SHA_MAXSIZE_DMABLOCKRUN_BYTES; + } + + /* Complete blocks modulus block run */ + fill = ilen - (ilen % ctx->blocksize); + MBED_ASSERT((fill % ctx->blocksize) == 0); + if (fill) { + rc = crypto_sha_update_nobuf(ctx, input, fill, (ctx->total == 0), 0); + if (rc != 0) { + return rc; + } + ctx->total += fill; + input += fill; + ilen -= fill; + } + + /* Left incomplete block */ + if (ilen > 0) { + MBED_ASSERT(ilen < ctx->blocksize); + fill = ilen; + memcpy((void *) (ctx->buffer + ctx->buffer_left), input, fill); + input += fill; + ilen -= fill; + ctx->buffer_left += fill; + } + + MBED_ASSERT(ilen == 0); + + return rc; +} + +int crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int isfirst, int islast) +{ + MBED_ASSERT(ctx != NULL); + + /* Accept only: + * 1. Last block which may be incomplete + * 2. Non-last block(s) which must be complete */ + MBED_ASSERT(islast || (ilen % ctx->blocksize) == 0); + + int rc = 0; + + /* Acquire ownership of SHA H/W */ + crypto_sha_acquire(); + + /* Enable SHA interrupt */ + SHA_ENABLE_INT(CRPT); + + /* Use intermediate buffer when incompatible with SHA H/W DMA buffer */ + if (!crypto_dma_buff_compat(input, ilen, 1)) { + memcpy(dma_ctx_inst.block_imd, input, ilen); + dma_ctx_inst.block_act = dma_ctx_inst.block_imd; + } else { + dma_ctx_inst.block_act = input; + } + if (!crypto_dma_buff_compat(ctx->fbinfo, sizeof(ctx->fbinfo), 4)) { + memcpy(dma_ctx_inst.fbinfo_imd, ctx->fbinfo, sizeof(ctx->fbinfo)); + dma_ctx_inst.fbinfo_act = dma_ctx_inst.fbinfo_imd; + } else { + dma_ctx_inst.fbinfo_act = ctx->fbinfo; + } + + SHA_Open(CRPT, ctx->opmode, SHA_IN_SWAP, 0); + SHA_SetDMATransfer(CRPT, (uint32_t) dma_ctx_inst.block_act, ilen); + + /* Address of feedback information input/output */ + CRPT->HMAC_FBADDR = (uint32_t) dma_ctx_inst.fbinfo_act; + + /* Continue above and re-configure further */ + uint32_t hmac_ctl = CRPT->HMAC_CTL | + CRPT_HMAC_CTL_START_Msk | // Start SHA/HMAC engine + (isfirst ? CRPT_HMAC_CTL_DMAFIRST_Msk : 0) | // SHA/HMAC first block in cascade function + (islast ? CRPT_HMAC_CTL_DMALAST_Msk : 0) | // SHA/HMAC last block + CRPT_HMAC_CTL_DMACSCAD_Msk | // Enable SHA/HMAC engine DMA with cascade mode + CRPT_HMAC_CTL_DMAEN_Msk | // Enable SHA/HMAC engine DMA + (isfirst ? 0 : CRPT_HMAC_CTL_FBIN_Msk) | // Feedback input to SHA/HMAC via DMA automatically + // FBIN doesn't make sense for the first block, on which + // SHA H/W isn't fool-proof. Enable FBIN for the first block + // will crash SHA H/W. + (islast ? 0 : CRPT_HMAC_CTL_FBOUT_Msk) | // Feedback output from SHA/HMAC via DMA automatically + // FBOUT is unnecessary for the last block. + 0; + + crypto_sha_prestart(); + CRPT->HMAC_CTL = hmac_ctl; + rc = crypto_sha_wait() ? 0 : ctx->err_hw_accel; + + /* On using intermediate buffer, restore output feedback information */ + if (rc == 0 && + (uint32_t) ctx->fbinfo != (uint32_t) dma_ctx_inst.fbinfo_act) { + memcpy(ctx->fbinfo, dma_ctx_inst.fbinfo_act, sizeof(ctx->fbinfo)); + } + + /* Disable SHA interrupt */ + SHA_DISABLE_INT(CRPT); + + /* Release ownership of SHA H/W */ + crypto_sha_release(); + + return rc; +} + +int crypto_sha_finish(crypto_sha_context *ctx, unsigned char output[], size_t olen) +{ + MBED_ASSERT(ctx != NULL); + MBED_ASSERT(output != NULL); + MBED_ASSERT(olen != 0 && olen == ctx->digestsize); + + int rc = 0; + + /* NOTE: Per real test, SHA H/W can support zero data, so we needn't + * special handling for it. */ + rc = crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, (ctx->total == 0), 1); + if (rc != 0) { + return rc; + } + ctx->total += ctx->buffer_left; + ctx->buffer_left = 0; + rc = crypto_sha_getdigest(output, ctx->digestsize); + if (rc != 0) { + return rc; + } + + return rc; +} + +int crypto_sha_getdigest(unsigned char output[], size_t olen) +{ + MBED_ASSERT(output != NULL); + MBED_ASSERT(olen != 0 && (olen % 4) == 0); + + uint32_t *in_pos = (uint32_t *) &CRPT->HMAC_DGST[0]; + unsigned char *out_pos = output; + uint32_t rmn = olen; + + while (rmn) { + uint32_t val = *in_pos ++; + nu_set32_be(out_pos, val); + out_pos += 4; + rmn -= 4; + } + + return 0; +} + +#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */ +#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */ diff --git a/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha_alt_hw.h b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha_alt_hw.h new file mode 100644 index 0000000..43219d7 --- /dev/null +++ b/connectivity/drivers/mbedtls/TARGET_NUVOTON/TARGET_M460/sha/sha_alt_hw.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SHA_ALT_HW_H +#define MBEDTLS_SHA_ALT_HW_H + +#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT) + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Max size of SHA block in bytes + * + * SHA-160/224/256: 64 bytes + * SHA-384/512: 128 bytes + * + * \note Support SHA1/2 only, no SHA3 + */ +#define NU_CRYPTO_SHA_MAXSIZE_BLOCK_BYTES 128 + +/** + * \brief Max size of SHA DMA block run in bytes + * + * \note DMA cascade mode requires block-aligned except for the last block. + * \note This also defines DMA intermediary buffer size. + */ +#define NU_CRYPTO_SHA_MAXSIZE_DMABLOCKRUN_BYTES \ + (NU_CRYPTO_SHA_MAXSIZE_BLOCK_BYTES * 4) + +/** + * \brief Max size of SHA feedback information in words, used in DMA cascade mode + * + * SHA1/2: 54 words + * SHA3: 88 words + * + * \note Support SHA1/2 only, no SHA3 + * \note According to spec, reserve 54 words for SHA1/2. But per real + * test, SHA H/W will overwrite beyond 54 words. Workaround by + * reserving 88 words anyway. + */ +#define NU_CRYPTO_SHA_MAXSIZE_FBINFO_WORDS 88 + +/** + * \brief SHA context structure + * + * \note SHA type/opmode + * 1. For type, borrow from opmode defines and can only be SHA_MODE_SHA1/SHA256/SHA512. + * 2. Initialize opmode/digestsize dependent on type + * 3. For SHA_MODE_SHA256/512, opmode will change to SHA_MODE_SHA224/384 + * when is224_384 is non-zero in the call to crypto_sha_starts(). + * 4. Following above, for opmode being SHA_MODE_SHA224/384, change digestsize to 28/48 + */ +typedef struct { + /* These fields will initialize at crypto_sha_init() */ + uint32_t type; /*!< SHA type */ + uint32_t opmode; /*!< SHA operation mode */ + uint32_t digestsize; /*!< SHA digest size */ + int err_hw_accel; /*!< Mbed TLS error code for the SHA type */ + int err_bad_input; /*!< Mbed TLS error code for the SHA type */ + + /* These fields will initialize at crypto_sha_starts() */ + uint32_t total; /*!< number of bytes processed */ + union { + uint8_t buffer[NU_CRYPTO_SHA_MAXSIZE_BLOCK_BYTES]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */ + uint32_t buffer_u32[NU_CRYPTO_SHA_MAXSIZE_BLOCK_BYTES/4]; /*!< make buffer word aligned */ + }; + uint16_t buffer_left; + uint16_t blocksize; /*!< block size */ + uint32_t blocksize_mask; /*!< block size mask */ + int is224_384; /*!< 0 => SHA-256/SHA-512, else SHA-224/384 */ + uint32_t fbinfo[NU_CRYPTO_SHA_MAXSIZE_FBINFO_WORDS]; /*!< feedback information in DMA cascade mode */ +} +crypto_sha_context; + +void crypto_sha_init(crypto_sha_context *ctx, uint32_t type); +void crypto_sha_free(crypto_sha_context *ctx); +int crypto_sha_starts(crypto_sha_context *ctx, int is224_384); +int crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen); +int crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int isfirst, int islast); +int crypto_sha_finish(crypto_sha_context *ctx, unsigned char output[], size_t olen); +int crypto_sha_getdigest(unsigned char output[], size_t olen); + +#if defined(MBEDTLS_SHA1_ALT) + +void mbedtls_sha1_hw_init( crypto_sha_context *ctx ); +void mbedtls_sha1_hw_free( crypto_sha_context *ctx ); +int mbedtls_sha1_hw_starts( crypto_sha_context *ctx ); +int mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen ); +int mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] ); +int mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); + +#endif /* MBEDTLS_SHA1_ALT */ + +#if defined(MBEDTLS_SHA256_ALT) + +void mbedtls_sha256_hw_init( crypto_sha_context *ctx ); +void mbedtls_sha256_hw_free( crypto_sha_context *ctx ); +int mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 ); +int mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input, + size_t ilen ); +int mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] ); +int mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] ); + +#endif /* MBEDTLS_SHA256_ALT */ + +#if defined(MBEDTLS_SHA512_ALT) + +void mbedtls_sha512_hw_init( crypto_sha_context *ctx ); +void mbedtls_sha512_hw_free( crypto_sha_context *ctx ); +int mbedtls_sha512_hw_starts( crypto_sha_context *ctx, int is384 ); +int mbedtls_sha512_hw_update( crypto_sha_context *ctx, const unsigned char *input, + size_t ilen ); +int mbedtls_sha512_hw_finish( crypto_sha_context *ctx, unsigned char output[64] ); +int mbedtls_sha512_hw_process( crypto_sha_context *ctx, const unsigned char data[128] ); + +#endif /* MBEDTLS_SHA512_ALT */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */ + +#endif /* sha_alt.h */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c index db8dd42..0b5caa1 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c @@ -442,6 +442,9 @@ msg_len = socket_recvmsg(sckt_data->socket_id, &msghdr, NS_MSG_LEGACY0); + // Buffer to tell additional data for the socket (such as interface ID) + uint8_t ancillary_databuffer[NS_CMSG_SPACE(sizeof(ns_in6_pktinfo_t))]; + tr_debug("dhcp Relay recv msg"); //Parse type @@ -471,6 +474,25 @@ msghdr.msg_iovlen = 1; msg_data.iov_base = relay_msg.relay_options.msg_ptr; msg_data.iov_len = relay_msg.relay_options.len; + + // Append a control message to tell the socket which interface to use if option is activated + if (memcmp(src_address.address, ns_in6addr_any, 16) != 0 && relay_srv->add_interface_id_option) { + ns_cmsghdr_t *cmsg; + ns_in6_pktinfo_t *pktinfo; + + msghdr.msg_control = ancillary_databuffer; + msghdr.msg_controllen = sizeof(ancillary_databuffer); + + cmsg = NS_CMSG_FIRSTHDR(&msghdr); + cmsg->cmsg_type = SOCKET_IPV6_PKTINFO; + cmsg->cmsg_level = SOCKET_IPPROTO_IPV6; + cmsg->cmsg_len = NS_CMSG_LEN(sizeof(ns_in6_pktinfo_t)); + + pktinfo = (ns_in6_pktinfo_t *)NS_CMSG_DATA(cmsg); + pktinfo->ipi6_ifindex = *relay_msg.relay_interface_id.msg_ptr; + memset(pktinfo->ipi6_addr, 0, 16); // Don't specify address (let socket choose appropriate by routing) + } + tr_debug("Forward Original relay msg to client"); } else { diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c index bf20b14..042207e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c @@ -1,5 +1,5 @@ /* **************************************************************************** - * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright(C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files(the "Software"), @@ -31,7 +31,6 @@ * *************************************************************************** */ - #include #include #include @@ -46,7 +45,6 @@ #include "mxc_i2c.h" #include "i2c_reva.h" - /* **** Definitions **** */ #define MXC_I2C_FASTPLUS_SPEED 1000000 @@ -58,334 +56,335 @@ /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr) +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) { - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } MXC_I2C_Shutdown(i2c); // Clear everything out - - if(i2c == MXC_I2C0) { + + if (i2c == MXC_I2C0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_GPIO_Config(&gpio_cfg_i2c0); - } - else if(i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_GPIO_Config(&gpio_cfg_i2c1); - } - else { + } else { return E_NO_DEVICE; } - - return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t*) i2c, masterMode, slaveAddr); + + return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t *)i2c, masterMode, slaveAddr); } -int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx) { - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if(idx != 0) { + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - - if(slaveAddr > MXC_F_I2C_SLADDR_SLA) { + + if (slaveAddr > MXC_F_I2C_SLADDR_SLA) { // Only support addresses up to 10 bits return E_BAD_PARAM; } - + i2c->sladdr = 0; - - if(slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->sladdr = MXC_F_I2C_SLADDR_EA; } - + i2c->sladdr |= slaveAddr; - + return E_NO_ERROR; } -int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c) +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c) { // Configure GPIO for I2C - if(i2c == MXC_I2C0) { + if (i2c == MXC_I2C0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); - } - else if(i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); - } - else { + } else { return E_NO_DEVICE; } - - + int i2cNum = MXC_I2C_GET_IDX(i2c); - + // Reconcile this with MXC_SYS_I2C_Init when we figure out what to do abotu system level things - switch(i2cNum) { + switch (i2cNum) { case 0: MXC_GCR->rst0 |= MXC_F_GCR_RST0_I2C0; break; - + case 1: MXC_GCR->rst1 |= MXC_F_GCR_RST1_I2C1; break; - + default: return E_BAD_PARAM; } - + return E_NO_ERROR; } -int MXC_I2C_SetFrequency(mxc_i2c_regs_t* i2c, unsigned int hz) +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz) { - // ME13 doesn't support high speed more - if(hz > MXC_I2C_FASTPLUS_SPEED) { + if (hz > MXC_I2C_FASTPLUS_SPEED) { return E_NOT_SUPPORTED; } - - return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t*) i2c, hz); + + return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t *)i2c, hz); } -unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t* i2c) +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetClockStretching(mxc_i2c_regs_t* i2c, int enable) +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable) { - return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t*) i2c, enable); + return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t *)i2c, enable); } -int MXC_I2C_GetClockStretching(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t *)i2c); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_Start(mxc_i2c_regs_t* i2c) +int MXC_I2C_Start(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Stop(mxc_i2c_regs_t* i2c) +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteByte(mxc_i2c_regs_t* i2c, unsigned char byte) +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte) { - return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t*) i2c, byte); + return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t *)i2c, byte); } -int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack) { - return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t*) i2c, byte, ack); + return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t *)i2c, byte, ack); } -int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t* i2c, unsigned char* byte, mxc_i2c_getAck_t getAck) +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck) { - return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); + return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t *)i2c, byte, + (mxc_i2c_reva_getAck_t)getAck); } -int MXC_I2C_Write(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len) { - return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_Read(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { - return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t*) i2c, bytes, len, ack); + return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t *)i2c, bytes, len, ack); } -int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; i2cNum = MXC_I2C_GET_IDX(i2c); - - switch(i2cNum) { + + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0RX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1RX; break; } - return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); + return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, + (mxc_i2c_reva_dma_complete_cb_t)callback, config, MXC_DMA); } -int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; i2cNum = MXC_I2C_GET_IDX(i2c); - - switch(i2cNum) { + + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0TX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1TX; break; } - return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); + return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, + (mxc_i2c_reva_dma_complete_cb_t)callback, config, MXC_DMA); } -int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_GetFlags(mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { - return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_ClearFlags(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_DisableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout) +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout) { - MXC_I2C_RevA_SetTimeout ((mxc_i2c_reva_regs_t*) i2c, timeout); + MXC_I2C_RevA_SetTimeout((mxc_i2c_reva_regs_t *)i2c, timeout); } -unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTimeout ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTimeout((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Recover(mxc_i2c_regs_t* i2c, unsigned int retries) +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries) { - return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t*) i2c, retries); + return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t *)i2c, retries); } /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_MasterTransaction(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t*) req, MXC_DMA); + return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t *)req, MXC_DMA); } -int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c, + (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransactionAsync((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransactionAsync( + (mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_AsyncHandler(mxc_i2c_regs_t* i2c) +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t*) i2c, interruptCheck); + MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck); } void MXC_I2C_DMACallback(int ch, int error) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index 56d335f..572ca6f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -1,5 +1,5 @@ /* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -47,99 +47,100 @@ /* **** Variable Declaration **** */ typedef struct { mxc_i2c_reva_req_t *req; - int master; // 1 for Master, 0 for slave - int channelTx; // DMA channel for TX transaction - int channelRx; // DMA channel for RX transaction - int writeDone; // Write done flag - int readDone; // Flag done flag + int master; // 1 for Master, 0 for slave + int channelTx; // DMA channel for TX transaction + int channelRx; // DMA channel for RX transaction + volatile int writeDone; // Write done flag + volatile int readDone; // Flag done flag } mxc_i2c_reva_req_state_t; static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES]; -void* AsyncRequests[MXC_I2C_INSTANCES]; -unsigned int AsyncWritten[MXC_I2C_INSTANCES]; -unsigned int AsyncRead[MXC_I2C_INSTANCES]; +void *AsyncRequests[MXC_I2C_INSTANCES]; +unsigned int AsyncWritten[MXC_I2C_INSTANCES]; +unsigned int AsyncRead[MXC_I2C_INSTANCES]; /* **** Function Prototypes **** */ -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -int MXC_I2C_RevA_DMAHandler (mxc_i2c_reva_req_t* req); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr) -{ +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr) +{ int err; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if ((err = MXC_I2C_Recover ((mxc_i2c_regs_t*) i2c, 16)) != E_NO_ERROR) { + if ((err = MXC_I2C_Recover((mxc_i2c_regs_t *)i2c, 16)) != E_NO_ERROR) { return err; } - + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); // Set the thresholds here and allow the user to change them as needed - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 6); // set RX threshold to 6 bytes - + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 6); // set RX threshold to 6 bytes + if (!masterMode) { - MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t*) i2c, slaveAddr, 0); - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 0; - } - else { + MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0); + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0; + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 1; + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1; } return E_NO_ERROR; } -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx) { if (i2c == NULL) { return E_NULL_PTR; } - + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - + if (slaveAddr > MXC_F_I2C_REVA_SLAVE_ADDR) { // Only support addresses up to 10 bits return E_BAD_PARAM; } - + i2c->slave = 0; - + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->slave = MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN; } - + i2c->slave |= slaveAddr; - + return E_NO_ERROR; } -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c) { return E_NOT_SUPPORTED; } -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz) +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz) { unsigned int ticksTotal, hiClks, lowClks; - + if (i2c == NULL) { return E_NULL_PTR; } @@ -147,161 +148,159 @@ if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) { // We're going to enable high speed int hsLowClks, hsHiClks; - + // Calculate the period of SCL and set up 33% duty cycle ticksTotal = PeripheralClock / hz; hsLowClks = (ticksTotal * 2) / 3 - 1; hsHiClks = ticksTotal / 3 - 1; - + // For rounding errors, adjust by 1 clock tick if (ticksTotal % 1) { hsHiClks++; } - + // If we're too slow for high speed, bail out if ((hsHiClks > 0xF) || (hsLowClks > 0xF)) { return E_BAD_PARAM; } - + hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz } - + // Calculate the period of SCL, 50% duty cycle ticksTotal = PeripheralClock / hz; hiClks = (ticksTotal >> 1) - 1; lowClks = (ticksTotal >> 1) - 1; - + // Adjust for rounding errors if (ticksTotal % 1) { hiClks++; } - + // Check for maximum/minimum supported speeds - if ( (hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { + if ((hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { return E_BAD_PARAM; } - + i2c->clklo = lowClks & MXC_F_I2C_REVA_CLKLO_LO; i2c->clkhi = hiClks & MXC_F_I2C_REVA_CLKHI_HI; - + // Return the actual speed set, since it won't be exactly what's requested - return MXC_I2C_GetFrequency ((mxc_i2c_regs_t*) i2c); + return MXC_I2C_GetFrequency((mxc_i2c_regs_t *)i2c); } -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c) { unsigned int sclCycles = 0; - + // Calculate the speed based on what we've written into registers sclCycles = (i2c->clklo & MXC_F_I2C_REVA_CLKLO_LO) + (i2c->clkhi & MXC_F_I2C_REVA_CLKHI_HI); - + return PeripheralClock / sclCycles; } -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c) { - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - - if (AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] != NULL) { + + if (AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] != NULL) { return E_BUSY; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable) +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable) { if (i2c == NULL) { return E_NULL_PTR; } - + if (enable) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; - } - else { + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - return ! ( (i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); + return !((i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - + // If we have an incomplete transfer, we need to do a restart if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP); - + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP) {} + return E_NO_ERROR; } -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte) +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte) { if (i2c == NULL) { return E_NULL_PTR; } - + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) { return E_OVERFLOW; } - + // I'm depending on an interrupt flag here // This might cause issues with the transaction level functions to come - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); i2c->fifo = byte; - - while (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)); - + + while (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {} + return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR; } -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - if(ack) { + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + + if (ack) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK; } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_IRXM_ACK; @@ -310,290 +309,293 @@ return E_NO_ERROR; } -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck) +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - + + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + if (getAck == NULL) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; + } else { + i2c->ctrl |= (!!getAck((mxc_i2c_reva_regs_t *)i2c, *byte)) + << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; } - else { - i2c->ctrl |= (!!getAck ((mxc_i2c_reva_regs_t*) i2c, *byte)) << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; - } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len) { int notAcked = 0; unsigned written = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - + for (; written < *len; written++) { - int retVal = MXC_I2C_WriteByte ((mxc_i2c_regs_t*) i2c, bytes[written]); - + int retVal = MXC_I2C_WriteByte((mxc_i2c_regs_t *)i2c, bytes[written]); + if (retVal >= 0) { notAcked += retVal; - } - else { + } else { *len = written; return retVal; } } - + *len = written; notAcked = (notAcked > 0) ? 1 : 0; return notAcked; } -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { unsigned read = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - for (; read < *len-1; read++) { - int retVal = MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), 1); - + for (; read < *len - 1; read++) { + int retVal = MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), 1); + if (retVal != E_NO_ERROR) { *len = read; return retVal; } } - + read++; *len = read; - return MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), ack); + return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack); } -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned read = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - - while ( (len > read) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { + + while ((len > read) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { bytes[read++] = i2c->fifo; } - + return read; } -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); - - #if TARGET_NUM == 32665 + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 0; config.dstinc_en = 1; - + srcdst.ch = channel; srcdst.dest = bytes; srcdst.len = len; - + states[i2cNum].channelRx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_RX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) -{ - if(i2c == NULL) { +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) +{ + if (i2c == NULL) { return E_NULL_PTR; } - + return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS; } -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned written = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - while ( (len > written) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { + while ((len > written) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { i2c->fifo = bytes[written++]; } - + return written; } -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)i2c); - + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 1; config.dstinc_en = 0; - + srcdst.ch = channel; srcdst.source = bytes; srcdst.len = len; - + states[i2cNum].channelTx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); // MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_TX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - - int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - return txFIFOlen - ( (i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); + + int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + return txFIFOlen - + ((i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); } -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c) { i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH; - - while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH); + + while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH) {} } -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c) -{ +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c) +{ i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH; - - while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH); + + while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH) {} } -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { if (i2c == NULL) { return E_NULL_PTR; } - + if ((flags0 == NULL) || (flags1 == NULL)) { return E_BAD_PARAM; } - + *flags0 = i2c->intfl0; *flags1 = i2c->intfl1; - + return E_NO_ERROR; } -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->intfl0 = flags0; i2c->intfl1 = flags1; } -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 |= flags0; i2c->inten1 |= flags1; } -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 &= ~flags0; i2c->inten1 &= ~flags1; } -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries) +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries) { int err; unsigned int i; - - if(i2c == NULL) { + + if (i2c == NULL) { return E_NULL_PTR; } @@ -602,91 +604,91 @@ i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; int swBit = i2c->ctrl & MXC_F_I2C_REVA_CTRL_BB_MODE; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } i2c->ctrl |= MXC_F_I2C_REVA_CTRL_BB_MODE; - + // Follow the procedure detailed in the header file // Delay 10uS between each step to give the line/slaves time to react for (i = 0; i < retries; i++) { - MXC_Delay (10); - i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT; - MXC_Delay(10); - + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT; + + MXC_Delay(10); + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); - i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT; + + MXC_Delay(10); + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); - i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - - if (! (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT; + + MXC_Delay(10); + + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); - i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT; - + MXC_Delay(10); - + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT; + + MXC_Delay(10); + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { err = E_NO_ERROR; // We have control break; } } - + if (swBit == 0) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_BB_MODE; } i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_EN; - + return err; } -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout) +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout) { i2c->timeout |= (timeout & 0xFFFF); } -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c) { return (i2c->timeout & 0xFFFF); } @@ -695,24 +697,24 @@ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req) { - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access unsigned int written = 0; unsigned int read = 0; - + if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + // if(!read | write) // Start // send addr w/ write bit @@ -728,288 +730,309 @@ // read rx_len bytes acking all // stop or restart // return good or error - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); i2c->inten0 = 0; i2c->inten1 = 0; - + if ((req->rx_len == 0) || (req->tx_len != 0)) { // Load the slave address with write bit set i2c->fifo = (req->addr << 1) & ~0x1; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; } - + while (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, + MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); + if (req->rx_len != 0) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - + while (req->rx_len > read) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } } - + if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {} + // Wait for Transaction to finish } - - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)); // Wait for Transaction to finish - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)); // Wait for Transaction to finish - + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {} + // Wait for Transaction to finish + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP; - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { return E_COMM_ERR; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)(req->i2c)); - mxc_i2c_reva_regs_t* i2c = req->i2c; - + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)(req->i2c)); + mxc_i2c_reva_regs_t *i2c = req->i2c; + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (AsyncRequests[i2cNum] == NULL) { if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - AsyncRequests[i2cNum] = (void*) req; + + AsyncRequests[i2cNum] = (void *)req; AsyncWritten[i2cNum] = 0; AsyncRead[i2cNum] = 0; - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - if ((req->rx_len == 0) || (req->tx_len != 0)) { - i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set - i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + i2c->inten0 = MXC_I2C_REVA_ERROR; + + if (req->tx_len) { + i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set + } else if (req->rx_len) { + i2c->fifo = (req->addr << 1) | 0x1; // Load the slave address with read bit set + + /* Set the number of bytes to read */ + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read + } + + /* Enable RX Threshold interrupt for when the FIFO is full */ + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + /* Must have tx_len and/or rx_len */ + return E_BAD_PARAM; } - - i2c->inten0 = MXC_I2C_REVA_ERROR | MXC_F_I2C_REVA_INTEN0_TX_THD; + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); + + /* Fill the FIFO as nessary */ + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + return E_NO_ERROR; - } - else { + } else { return E_BUSY; } } -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma) { int i2cNum; - - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { return E_BAD_PARAM; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); + states[i2cNum].req = req; - + states[i2cNum].channelTx = 0xFF; states[i2cNum].channelRx = 0xFF; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 MXC_DMA_Init(dma); - #else +#else MXC_DMA_Init(); - #endif - +#endif + //tx if ((req->tx_buf != NULL) && !(states[i2cNum].writeDone)) { - i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set - - #if TARGET_NUM == 32665 - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL, dma); - #else - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL); - #endif - } - else { + i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL, dma); +#else + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL); +#endif + } else { states[i2cNum].writeDone = 1; } - - if (req->rx_buf != NULL) { - while(states[i2cNum].writeDone != 1); //Ensure DMA transmit has finished before attempting to receive - if ( (states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { + if (req->rx_buf != NULL) { + while (states[i2cNum].writeDone != 1) {} + //Ensure DMA transmit has finished before attempting to receive + + if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed - #if TARGET_NUM == 32665 - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL, dma); - #else - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL); - #endif + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL, dma); +#else + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL); +#endif } - } - else { + } else { states[i2cNum].readDone = 1; } - + return E_NO_ERROR; } void MXC_I2C_RevA_DMACallback(int ch, int error) { mxc_i2c_reva_req_t *temp_req; - - for (int i = 0; i < MXC_I2C_INSTANCES; i ++) { + + for (int i = 0; i < MXC_I2C_INSTANCES; i++) { if (states[i].channelTx == ch) { //save the request temp_req = states[i].req; states[i].writeDone = 1; - + if (states[i].readDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); } } - } - - else if (states[i].channelRx == ch) { + } else if (states[i].channelRx == ch) { //save the request states[i].readDone = 1; temp_req = states[i].req; - + if (states[i].writeDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); - } + } } } } } -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { unsigned int interruptEnables = interruptCheck; int retVal = E_NO_ERROR; - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + // Callback called on // Slave Address Match (distinguish read/write) // RX Threshold @@ -1026,98 +1049,110 @@ // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - + while (interruptEnables > 0) { interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal); } - + return retVal; } -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { - int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t*) i2c); - + int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + if (i2cnum < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - + if (AsyncRequests[i2cnum] != NULL) { return E_BUSY; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set RX threshold to 6 bytes - AsyncRequests[i2cnum] = (void *) callback; - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); // set RX threshold to 6 bytes + AsyncRequests[i2cnum] = (void *)callback; + i2c->inten0 = interruptCheck; - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; - + unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; + if (numBytes > rxFIFOlen) { return E_BAD_PARAM; } - - i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); + + i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS; } -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - + unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + if (numBytes > txFIFOlen) { return E_BAD_PARAM; } - - i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); + + i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS; } -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal) +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)]; - + mxc_i2c_reva_req_t *req = + (mxc_i2c_reva_req_t *)AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)]; + if (req->callback != NULL) { req->callback(req, retVal); } } -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c) { + /* Disable and clear interrupts */ i2c->inten0 = 0; i2c->inten1 = 0; - + + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called @@ -1129,95 +1164,119 @@ { unsigned int written = AsyncWritten[i2cNum]; unsigned int read = AsyncRead[i2cNum]; - mxc_i2c_reva_regs_t* i2c = (mxc_i2c_reva_regs_t*) MXC_I2C_GET_BASE (i2cNum); - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[i2cNum]; - + mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum); + mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum]; + + /* Check for errors */ + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + /* Clear and disable interrupts */ + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + i2c->inten0 = 0; + i2c->inten1 = 0; + + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + MXC_I2C_RevA_AsyncStop(i2c); + + return; + } + + /* Write data to the TX FIFO */ if (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); + + /* Enable the TX Threshold interrupt if we still need to write to the TX FIFO */ + if (written < req->tx_len) { + i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_TX_THD; + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_TX_THD); } - } - - if (req->rx_len > read) { - if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; - } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); - } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { - i2c->rxctrl1 = 0; - } - else { - i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read - } - + + /* Send a restart if we're reading after writing */ + if ((req->tx_len == written) && (req->rx_len)) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_DONE); } } - - if ( (req->tx_len == written) && (read == 0)) { - i2c->inten0 &= ~MXC_F_I2C_REVA_INTEN0_TX_THD; - i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE; - - if ( (req->rx_len) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + /* Read data in the RX FIFO */ + if (req->rx_len > read) { + if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; + } + } + + /* Done writing, still reading */ + if ((req->tx_len == written) && (req->rx_len - read) && + (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) { + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + + /* First done interrupt after completing writes to the TX FIFO */ + if (read == 0) { + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + + /* Set the number of bytes to read */ + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - else { - i2c->rxctrl1 = (req->rx_len); // 0 for 256, otherwise number of bytes to read + + /* Enable RX Threshold interrupt for when the FIFO is full */ + if (read < req->rx_len) { + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - - if ( (req->tx_len == written) && (req->rx_len == read)) { - i2c->inten0 &= ~ (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); - + + /* Done reading and writing */ + if ((req->tx_len == written) && (req->rx_len == read)) { + /* Disable and clear interrupts */ + i2c->inten0 = 0; + i2c->inten1 = 0; + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + + /* Send a restart or stop at the end of the transaction */ if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + + /* Call the callback */ if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - } - else { + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + } else { MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR); } - + + /* Clear the async state */ MXC_I2C_RevA_AsyncStop(i2c); + + } else { + AsyncWritten[i2cNum] = written; + AsyncRead[i2cNum] = read; } - - AsyncWritten[i2cNum] = written; - AsyncRead[i2cNum] = read; } -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal) +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal) { uint32_t tFlags = i2c->intfl0; *retVal = E_NO_ERROR; - + uint32_t readFlag = i2c->ctrl & MXC_F_I2C_REVA_CTRL_READ; // Callback called on // Slave Address Match (distinguish read/write) @@ -1235,114 +1294,161 @@ // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - if (!(interruptEnables & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH| MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { + if (!(interruptEnables & + (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | + MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // (fires anytime a stop/start is detected out of sequence). if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) { - callback (i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV; } } - - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { + + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) { - callback (i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN; } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; - } - - if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } - if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH){ - if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); } - else { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } + + if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { + if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } else { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } } else if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + return interruptEnables; } -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck) +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int slaveRetVal; - + if (i2cNum < 0) { return; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { - MXC_I2C_RevA_MasterAsyncHandler (i2cNum); - } - else { - mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t) AsyncRequests[i2cNum]; - i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler (i2c, callback, i2c->inten0, &slaveRetVal); + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + } else { + mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; + i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h index c32f66e..aa41e2c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h @@ -1,5 +1,5 @@ /* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -31,8 +31,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_H_ -#define _I2C_REVA_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ #include #include @@ -46,33 +46,34 @@ #include "i2c_reva_regs.h" #include "dma.h" - /* **** Definitions **** */ -#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F -#define MXC_I2C_REVA_STD_MODE 100000 -#define MXC_I2C_REVA_FAST_SPEED 400000 -#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 -#define MXC_I2C_REVA_HS_MODE 3400000 +#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F +#define MXC_I2C_REVA_STD_MODE 100000 +#define MXC_I2C_REVA_FAST_SPEED 400000 +#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 +#define MXC_I2C_REVA_HS_MODE 3400000 -#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF -#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 +#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF +#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 -#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 +#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 -#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \ - MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ - MXC_F_I2C_REVA_INTFL0_STOP_ERR) +#define MXC_I2C_REVA_ERROR \ + (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | \ + MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | MXC_F_I2C_REVA_INTFL0_DATA_ERR | \ + MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ + MXC_F_I2C_REVA_INTFL0_STOP_ERR) typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t; -typedef int (*mxc_i2c_reva_getAck_t) (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -typedef void (*mxc_i2c_reva_complete_cb_t) (mxc_i2c_reva_req_t* req, int result); -typedef void (*mxc_i2c_reva_dma_complete_cb_t) (int len, int result); +typedef int (*mxc_i2c_reva_getAck_t)(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +typedef void (*mxc_i2c_reva_complete_cb_t)(mxc_i2c_reva_req_t *req, int result); +typedef void (*mxc_i2c_reva_dma_complete_cb_t)(int len, int result); struct _i2c_reva_req_t { - mxc_i2c_reva_regs_t* i2c; + mxc_i2c_reva_regs_t *i2c; unsigned int addr; - unsigned char* tx_buf; + unsigned char *tx_buf; unsigned int tx_len; - unsigned char* rx_buf; + unsigned char *rx_buf; unsigned int rx_len; int restart; mxc_i2c_reva_complete_cb_t callback; @@ -86,72 +87,86 @@ MXC_I2C_REVA_EVT_UNDERFLOW, MXC_I2C_REVA_EVT_OVERFLOW, } mxc_i2c_reva_slave_event_t; -typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c, - mxc_i2c_reva_slave_event_t event, void* data); +typedef int (*mxc_i2c_reva_slave_handler_t)(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_event_t event, void *data); /* **** Variable Declaration **** */ +extern void *AsyncRequests[MXC_I2C_INSTANCES]; + /* **** Function Prototypes **** */ /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr); -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx); -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz); -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable); -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr); +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx); +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz); +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable); +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c); /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack); -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck); -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len); -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack); -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout); -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries); +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack); +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck); +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len); +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout); +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries); /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck); -void MXC_I2C_RevA_DMACallback (int ch, int error); +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma); +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); +void MXC_I2C_RevA_DMACallback(int ch, int error); -#endif /* _I2C_REVA_H_ */ \ No newline at end of file +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h index d4a3ee2..49a4341 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h @@ -4,7 +4,7 @@ */ /* **************************************************************************** - * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) 2022 Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,8 +37,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_REGS_H_ -#define _I2C_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -115,25 +115,25 @@ * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. * @{ */ - #define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ - #define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ - #define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ - #define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ - #define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ - #define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ - #define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ - #define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ - #define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ - #define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ - #define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ - #define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ - #define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ - #define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ - #define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ - #define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ - #define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ - #define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ - #define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ +#define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ +#define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ +#define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ +#define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ +#define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ +#define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ +#define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ +#define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ +#define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ +#define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ +#define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ +#define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ +#define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ +#define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ +#define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ +#define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ +#define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ +#define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +#define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ /**@} end of group i2c_registers */ /** @@ -142,47 +142,47 @@ * @brief Control Register0. * @{ */ - #define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ - #define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ +#define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ - #define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ +#define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ - #define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ +#define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ +#define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ - #define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ +#define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ /**@} end of group I2C_CTRL_Register */ @@ -192,23 +192,23 @@ * @brief Status Register. * @{ */ - #define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ /**@} end of group I2C_STATUS_Register */ @@ -218,62 +218,62 @@ * @brief Interrupt Status Register. * @{ */ - #define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ - #define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ +#define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ +#define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ - #define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ - #define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ +#define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ - #define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ +#define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTFL0_Register */ @@ -283,62 +283,62 @@ * @brief Interrupt Enable Register. * @{ */ - #define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ - #define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ +#define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ +#define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ - #define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ - #define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ +#define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ - #define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ +#define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTEN0_Register */ @@ -348,14 +348,14 @@ * @brief Interrupt Status Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ - #define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ +#define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ +#define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ /**@} end of group I2C_INTFL1_Register */ @@ -365,14 +365,14 @@ * @brief Interrupt Staus Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ - #define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ +#define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ +#define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ /**@} end of group I2C_INTEN1_Register */ @@ -382,11 +382,11 @@ * @brief FIFO Configuration Register. * @{ */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ /**@} end of group I2C_FIFOLEN_Register */ @@ -396,14 +396,14 @@ * @brief Receive Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ /**@} end of group I2C_RXCTRL0_Register */ @@ -413,11 +413,11 @@ * @brief Receive Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ /**@} end of group I2C_RXCTRL1_Register */ @@ -427,29 +427,29 @@ * @brief Transmit Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ /**@} end of group I2C_TXCTRL0_Register */ @@ -459,11 +459,11 @@ * @brief Transmit Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ /**@} end of group I2C_TXCTRL1_Register */ @@ -473,8 +473,8 @@ * @brief Data Register. * @{ */ - #define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ /**@} end of group I2C_FIFO_Register */ @@ -484,17 +484,17 @@ * @brief Master Control Register. * @{ */ - #define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ - #define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ +#define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ /**@} end of group I2C_MSTCTRL_Register */ @@ -504,8 +504,8 @@ * @brief Clock Low Register. * @{ */ - #define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ - #define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ +#define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ +#define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ /**@} end of group I2C_CLKLO_Register */ @@ -515,8 +515,8 @@ * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ - #define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ +#define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ +#define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ /**@} end of group I2C_CLKHI_Register */ @@ -526,11 +526,11 @@ * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ - #define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ +#define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ +#define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ - #define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ - #define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ +#define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ +#define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ /**@} end of group I2C_HSCLK_Register */ @@ -540,8 +540,8 @@ * @brief Timeout Register * @{ */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ /**@} end of group I2C_TIMEOUT_Register */ @@ -551,11 +551,11 @@ * @brief DMA Register. * @{ */ - #define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ - #define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ +#define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - #define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ - #define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ +#define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ /**@} end of group I2C_DMA_Register */ @@ -565,11 +565,11 @@ * @brief Slave Address Register. * @{ */ - #define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ - #define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ +#define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ +#define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ /**@} end of group I2C_SLAVE_Register */ @@ -577,4 +577,5 @@ } #endif -#endif /* _I2C_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c index d98a03e..8d6fd6a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_me15.c @@ -31,7 +31,6 @@ * *************************************************************************** */ - #include #include #include @@ -46,7 +45,6 @@ #include "mxc_i2c.h" #include "i2c_reva.h" - /* **** Definitions **** */ #define MXC_I2C_FASTPLUS_SPEED 1000000 @@ -58,54 +56,51 @@ /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr) +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) { if (i2c == NULL) { return E_NULL_PTR; } - - MXC_I2C_Shutdown(i2c); // Clear everything out - + + MXC_I2C_Shutdown(i2c); // Clear everything out + if (i2c == MXC_I2C0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_GPIO_Config(&gpio_cfg_i2c0); - } - #if TARGET_NUM != 32675 - else if (i2c == MXC_I2C1) { +#if TARGET_NUM != 32675 + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_GPIO_Config(&gpio_cfg_i2c1); - } - #endif - else if (i2c == MXC_I2C2) { +#endif + } else if (i2c == MXC_I2C2) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2); MXC_GPIO_Config(&gpio_cfg_i2c2); - } - else { + } else { return E_NO_DEVICE; } - - return MXC_I2C_RevA_Init ((mxc_i2c_reva_regs_t*) i2c, masterMode, slaveAddr); + + return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t *)i2c, masterMode, slaveAddr); } -int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx) { - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if(idx != 0) { + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - if(slaveAddr > MXC_F_I2C_SLAVE_ADDR) { + if (slaveAddr > MXC_F_I2C_SLAVE_ADDR) { // Only support addresses up to 10 bits return E_BAD_PARAM; } i2c->slave = 0; - if(slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->slave = MXC_F_I2C_SLAVE_EXT_ADDR_EN; } @@ -115,295 +110,295 @@ return E_NO_ERROR; } -int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c) +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c) { // Configure GPIO for I2C if (i2c == MXC_I2C0) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); - } - else if (i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); - } - else if (i2c == MXC_I2C2) { + } else if (i2c == MXC_I2C2) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2); MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); - } - else { + } else { return E_NO_DEVICE; } - + return E_NO_ERROR; } -int MXC_I2C_Reset (mxc_i2c_regs_t* i2c) +int MXC_I2C_Reset(mxc_i2c_regs_t *i2c) { // Configure GPIO for I2C - if(i2c == MXC_I2C0) { + if (i2c == MXC_I2C0) { MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); - } - else if(i2c == MXC_I2C1) { + } else if (i2c == MXC_I2C1) { MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); - } - else if(i2c == MXC_I2C2) { + } else if (i2c == MXC_I2C2) { MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); - } - else { + } else { return E_NO_DEVICE; } - - return E_NO_ERROR; + + return E_NO_ERROR; } -int MXC_I2C_SetFrequency(mxc_i2c_regs_t* i2c, unsigned int hz) +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz) { // ME13 doesn't support high speed more if (hz > MXC_I2C_FASTPLUS_SPEED) { return E_NOT_SUPPORTED; } - - return MXC_I2C_RevA_SetFrequency ((mxc_i2c_reva_regs_t*) i2c, hz); + + return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t *)i2c, hz); } -unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetFrequency ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t* i2c) +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_ReadyForSleep ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetClockStretching(mxc_i2c_regs_t* i2c, int enable) +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable) { - return MXC_I2C_RevA_SetClockStretching ((mxc_i2c_reva_regs_t*) i2c, enable); + return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t *)i2c, enable); } -int MXC_I2C_GetClockStretching(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetClockStretching ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t *)i2c); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_Start(mxc_i2c_regs_t* i2c) +int MXC_I2C_Start(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Start ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Stop(mxc_i2c_regs_t* i2c) +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_Stop ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteByte(mxc_i2c_regs_t* i2c, unsigned char byte) +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte) { - return MXC_I2C_RevA_WriteByte ((mxc_i2c_reva_regs_t*) i2c, byte); + return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t *)i2c, byte); } -int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack) { - return MXC_I2C_RevA_ReadByte ((mxc_i2c_reva_regs_t*) i2c, byte, ack); + return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t *)i2c, byte, ack); } - // return MXC_I2C_RevA_ReadByteInteractive ((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); +// return MXC_I2C_RevA_ReadByteInteractive ((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); // } -int MXC_I2C_Write(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len) { - return MXC_I2C_RevA_Write ((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_Read(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { - return MXC_I2C_RevA_Read ((mxc_i2c_reva_regs_t*) i2c, bytes, len, ack); + return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t *)i2c, bytes, len, ack); } -int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_ReadRXFIFO ((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; - + i2cNum = MXC_I2C_GET_IDX(i2c); - + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0RX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1RX; break; - + default: return E_BAD_PARAM; } - - return MXC_I2C_RevA_ReadRXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA); + + return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, callback, config, + MXC_DMA); } -int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXFIFOAvailable ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) { - return MXC_I2C_RevA_WriteTXFIFO ((mxc_i2c_reva_regs_t*) i2c, bytes, len); + return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); } -int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) { uint8_t i2cNum; mxc_dma_config_t config; - + i2cNum = MXC_I2C_GET_IDX(i2c); - + switch (i2cNum) { case 0: config.reqsel = MXC_DMA_REQUEST_I2C0TX; break; - + case 1: config.reqsel = MXC_DMA_REQUEST_I2C1TX; break; - + default: return E_BAD_PARAM; } - return MXC_I2C_RevA_WriteTXFIFODMA ((mxc_i2c_reva_regs_t*) i2c, bytes, len, callback, config, MXC_DMA); + return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, callback, config, + MXC_DMA); } -int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t* i2c) +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXFIFOAvailable ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearRXFIFO ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t* i2c) +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_ClearTXFIFO ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_GetFlags(mxc_i2c_regs_t* i2c, unsigned int* flags0, unsigned int* flags1) +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { - return MXC_I2C_RevA_GetFlags ((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_ClearFlags(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_ClearFlags ((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_DisableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) { - MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); + MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); } -void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_EnableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_EnableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c) +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_DisableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); + MXC_I2C_RevA_DisableGeneralCall((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout) +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout) { - MXC_I2C_RevA_SetTimeout ((mxc_i2c_reva_regs_t*) i2c, timeout); + MXC_I2C_RevA_SetTimeout((mxc_i2c_reva_regs_t *)i2c, timeout); } -unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTimeout ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTimeout((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_Recover(mxc_i2c_regs_t* i2c, unsigned int retries) +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries) { - return MXC_I2C_RevA_Recover ((mxc_i2c_reva_regs_t*) i2c, retries); + return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t *)i2c, retries); } /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_MasterTransaction(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransaction ((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionAsync ((mxc_i2c_reva_req_t*) req); + return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t *)req); } -int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req) +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req) { - return MXC_I2C_RevA_MasterTransactionDMA ((mxc_i2c_reva_req_t*) req, MXC_DMA); + return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t *)req, MXC_DMA); } -int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransaction ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c, + (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) { - return MXC_I2C_RevA_SlaveTransactionAsync ((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); + return MXC_I2C_RevA_SlaveTransactionAsync( + (mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); } -int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetRXThreshold ((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetRXThreshold ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t *)i2c); } -int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) { - return MXC_I2C_RevA_SetTXThreshold ((mxc_i2c_reva_regs_t*) i2c, numBytes); + return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); } -unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t* i2c) +unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c) { - return MXC_I2C_RevA_GetTXThreshold ((mxc_i2c_reva_regs_t*) i2c); + return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c); } -void MXC_I2C_AsyncHandler(mxc_i2c_regs_t* i2c) +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c) { - MXC_I2C_RevA_AsyncHandler ((mxc_i2c_reva_regs_t*) i2c, interruptCheck); + MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck); } void MXC_I2C_DMACallback(int ch, int error) diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c index 287027b..572ca6f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -47,99 +47,100 @@ /* **** Variable Declaration **** */ typedef struct { mxc_i2c_reva_req_t *req; - int master; // 1 for Master, 0 for slave - int channelTx; // DMA channel for TX transaction - int channelRx; // DMA channel for RX transaction - volatile int writeDone; // Write done flag - volatile int readDone; // Flag done flag + int master; // 1 for Master, 0 for slave + int channelTx; // DMA channel for TX transaction + int channelRx; // DMA channel for RX transaction + volatile int writeDone; // Write done flag + volatile int readDone; // Flag done flag } mxc_i2c_reva_req_state_t; static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES]; -void* AsyncRequests[MXC_I2C_INSTANCES]; -unsigned int AsyncWritten[MXC_I2C_INSTANCES]; -unsigned int AsyncRead[MXC_I2C_INSTANCES]; +void *AsyncRequests[MXC_I2C_INSTANCES]; +unsigned int AsyncWritten[MXC_I2C_INSTANCES]; +unsigned int AsyncRead[MXC_I2C_INSTANCES]; /* **** Function Prototypes **** */ -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -int MXC_I2C_RevA_DMAHandler (mxc_i2c_reva_req_t* req); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr) -{ +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr) +{ int err; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } - if ((err = MXC_I2C_Recover ((mxc_i2c_regs_t*) i2c, 16)) != E_NO_ERROR) { + if ((err = MXC_I2C_Recover((mxc_i2c_regs_t *)i2c, 16)) != E_NO_ERROR) { return err; } - + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); // Set the thresholds here and allow the user to change them as needed - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 6); // set RX threshold to 6 bytes - + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 6); // set RX threshold to 6 bytes + if (!masterMode) { - MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t*) i2c, slaveAddr, 0); - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 0; - } - else { + MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0); + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0; + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; - states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 1; + states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1; } return E_NO_ERROR; } -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx) +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx) { if (i2c == NULL) { return E_NULL_PTR; } - + if (idx != 0) { // Multiple slaves are not supported yet return E_NOT_SUPPORTED; } - + if (slaveAddr > MXC_F_I2C_REVA_SLAVE_ADDR) { // Only support addresses up to 10 bits return E_BAD_PARAM; } - + i2c->slave = 0; - + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { // Set for 10bit addressing mode i2c->slave = MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN; } - + i2c->slave |= slaveAddr; - + return E_NO_ERROR; } -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c) { return E_NOT_SUPPORTED; } -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz) +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz) { unsigned int ticksTotal, hiClks, lowClks; - + if (i2c == NULL) { return E_NULL_PTR; } @@ -147,161 +148,159 @@ if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) { // We're going to enable high speed int hsLowClks, hsHiClks; - + // Calculate the period of SCL and set up 33% duty cycle ticksTotal = PeripheralClock / hz; hsLowClks = (ticksTotal * 2) / 3 - 1; hsHiClks = ticksTotal / 3 - 1; - + // For rounding errors, adjust by 1 clock tick if (ticksTotal % 1) { hsHiClks++; } - + // If we're too slow for high speed, bail out if ((hsHiClks > 0xF) || (hsLowClks > 0xF)) { return E_BAD_PARAM; } - + hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz } - + // Calculate the period of SCL, 50% duty cycle ticksTotal = PeripheralClock / hz; hiClks = (ticksTotal >> 1) - 1; lowClks = (ticksTotal >> 1) - 1; - + // Adjust for rounding errors if (ticksTotal % 1) { hiClks++; } - + // Check for maximum/minimum supported speeds - if ( (hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { + if ((hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { return E_BAD_PARAM; } - + i2c->clklo = lowClks & MXC_F_I2C_REVA_CLKLO_LO; i2c->clkhi = hiClks & MXC_F_I2C_REVA_CLKHI_HI; - + // Return the actual speed set, since it won't be exactly what's requested - return MXC_I2C_GetFrequency ((mxc_i2c_regs_t*) i2c); + return MXC_I2C_GetFrequency((mxc_i2c_regs_t *)i2c); } -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c) { unsigned int sclCycles = 0; - + // Calculate the speed based on what we've written into registers sclCycles = (i2c->clklo & MXC_F_I2C_REVA_CLKLO_LO) + (i2c->clkhi & MXC_F_I2C_REVA_CLKHI_HI); - + return PeripheralClock / sclCycles; } -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c) { - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - - if (AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] != NULL) { + + if (AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] != NULL) { return E_BUSY; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable) +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable) { if (i2c == NULL) { return E_NULL_PTR; } - + if (enable) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; - } - else { + } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - return ! ( (i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); + return !((i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); } /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - + // If we have an incomplete transfer, we need to do a restart if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP); - + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP) {} + return E_NO_ERROR; } -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte) +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte) { if (i2c == NULL) { return E_NULL_PTR; } - + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) { return E_OVERFLOW; } - + // I'm depending on an interrupt flag here // This might cause issues with the transaction level functions to come - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); i2c->fifo = byte; - - while (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)); - + + while (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {} + return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR; } -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack) +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - if(ack) { + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + + if (ack) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK; } else { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_IRXM_ACK; @@ -310,290 +309,293 @@ return E_NO_ERROR; } -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck) +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck) { if ((i2c == NULL) || (byte == NULL)) { return E_NULL_PTR; } - if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { return E_UNDERFLOW; } - - *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); - + + *byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + if (getAck == NULL) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; + } else { + i2c->ctrl |= (!!getAck((mxc_i2c_reva_regs_t *)i2c, *byte)) + << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; } - else { - i2c->ctrl |= (!!getAck ((mxc_i2c_reva_regs_t*) i2c, *byte)) << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; - } - + return E_NO_ERROR; } -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len) +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len) { int notAcked = 0; unsigned written = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - + for (; written < *len; written++) { - int retVal = MXC_I2C_WriteByte ((mxc_i2c_regs_t*) i2c, bytes[written]); - + int retVal = MXC_I2C_WriteByte((mxc_i2c_regs_t *)i2c, bytes[written]); + if (retVal >= 0) { notAcked += retVal; - } - else { + } else { *len = written; return retVal; } } - + *len = written; notAcked = (notAcked > 0) ? 1 : 0; return notAcked; } -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) { unsigned read = 0; - + if (i2c == NULL) { return E_NULL_PTR; } - + if ((bytes == NULL) || (len == NULL)) { return E_NULL_PTR; } - for (; read < *len-1; read++) { - int retVal = MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), 1); - + for (; read < *len - 1; read++) { + int retVal = MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), 1); + if (retVal != E_NO_ERROR) { *len = read; return retVal; } } - + read++; *len = read; - return MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), ack); + return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack); } -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned read = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - - while ( (len > read) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { + + while ((len > read) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { bytes[read++] = i2c->fifo; } - + return read; } -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); - - #if TARGET_NUM == 32665 + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 0; config.dstinc_en = 1; - + srcdst.ch = channel; srcdst.dest = bytes; srcdst.len = len; - + states[i2cNum].channelRx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_RX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) -{ - if(i2c == NULL) { +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) +{ + if (i2c == NULL) { return E_NULL_PTR; } - + return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS; } -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len) { unsigned written = 0; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - while ( (len > written) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { + while ((len > written) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { i2c->fifo = bytes[written++]; } - + return written; } -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ - mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma) { uint8_t i2cNum; uint8_t channel; mxc_dma_srcdst_t srcdst; - + if ((i2c == NULL) || (bytes == NULL)) { return E_NULL_PTR; } - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)i2c); - + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 channel = MXC_DMA_AcquireChannel(dma); - #else +#else channel = MXC_DMA_AcquireChannel(); - #endif - +#endif + config.ch = channel; - + config.srcwd = MXC_DMA_WIDTH_BYTE; config.dstwd = MXC_DMA_WIDTH_BYTE; - + config.srcinc_en = 1; config.dstinc_en = 0; - + srcdst.ch = channel; srcdst.source = bytes; srcdst.len = len; - + states[i2cNum].channelTx = channel; MXC_DMA_ConfigChannel(config, srcdst); - + if (states[i2cNum].master) { MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); - } - else { + } else { MXC_DMA_SetCallback(channel, NULL); } - - MXC_DMA_EnableInt (channel); - MXC_DMA_Start (channel); + + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); // MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); i2c->dma |= MXC_F_I2C_REVA_DMA_TX_EN; - + return E_NO_ERROR; } -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c) { if (i2c == NULL) { return E_NULL_PTR; } - - int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - return txFIFOlen - ( (i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); + + int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + return txFIFOlen - + ((i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); } -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c) { i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH; - - while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH); + + while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH) {} } -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c) -{ +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c) +{ i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH; - - while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH); + + while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH) {} } -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) { if (i2c == NULL) { return E_NULL_PTR; } - + if ((flags0 == NULL) || (flags1 == NULL)) { return E_BAD_PARAM; } - + *flags0 = i2c->intfl0; *flags1 = i2c->intfl1; - + return E_NO_ERROR; } -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->intfl0 = flags0; i2c->intfl1 = flags1; } -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 |= flags0; i2c->inten1 |= flags1; } -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1) { i2c->inten0 &= ~flags0; i2c->inten1 &= ~flags1; } -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries) +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries) { int err; unsigned int i; - - if(i2c == NULL) { + + if (i2c == NULL) { return E_NULL_PTR; } @@ -602,91 +604,91 @@ i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; int swBit = i2c->ctrl & MXC_F_I2C_REVA_CTRL_BB_MODE; - if(i2c == NULL) { + if (i2c == NULL) { return E_NULL_PTR; } i2c->ctrl |= MXC_F_I2C_REVA_CTRL_BB_MODE; - + // Follow the procedure detailed in the header file // Delay 10uS between each step to give the line/slaves time to react for (i = 0; i < retries; i++) { - MXC_Delay (10); - i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT; - MXC_Delay(10); - + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT; + + MXC_Delay(10); + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); - i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT; + + MXC_Delay(10); + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); - i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT; - + MXC_Delay(10); - - if (! (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT; + + MXC_Delay(10); + + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; continue; // Give up and try again } - - MXC_Delay (10); - i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT; - + MXC_Delay(10); - + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT; + + MXC_Delay(10); + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { err = E_NO_ERROR; // We have control break; } } - + if (swBit == 0) { i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_BB_MODE; } i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_EN; - + return err; } -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c) { i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; } -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c) { - i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_GC_ADDR_EN; } -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout) +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout) { i2c->timeout |= (timeout & 0xFFFF); } -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c) { return (i2c->timeout & 0xFFFF); } @@ -695,24 +697,24 @@ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req) { - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access unsigned int written = 0; unsigned int read = 0; - + if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + // if(!read | write) // Start // send addr w/ write bit @@ -728,288 +730,309 @@ // read rx_len bytes acking all // stop or restart // return good or error - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); i2c->inten0 = 0; i2c->inten1 = 0; - + if ((req->rx_len == 0) || (req->tx_len != 0)) { // Load the slave address with write bit set i2c->fifo = (req->addr << 1) & ~0x1; i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; } - + while (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, + MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); + if (req->rx_len != 0) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - + while (req->rx_len > read) { if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); return E_COMM_ERR; } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } } - + if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {} + // Wait for Transaction to finish } - - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)); // Wait for Transaction to finish - while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)); // Wait for Transaction to finish - + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {} + // Wait for Transaction to finish + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP; - + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { return E_COMM_ERR; } - + return E_NO_ERROR; } -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req) +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)(req->i2c)); - mxc_i2c_reva_regs_t* i2c = req->i2c; - + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)(req->i2c)); + mxc_i2c_reva_regs_t *i2c = req->i2c; + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (AsyncRequests[i2cNum] == NULL) { if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - - AsyncRequests[i2cNum] = (void*) req; + + AsyncRequests[i2cNum] = (void *)req; AsyncWritten[i2cNum] = 0; AsyncRead[i2cNum] = 0; - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - if ((req->rx_len == 0) || (req->tx_len != 0)) { - i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set - i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + i2c->inten0 = MXC_I2C_REVA_ERROR; + + if (req->tx_len) { + i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set + } else if (req->rx_len) { + i2c->fifo = (req->addr << 1) | 0x1; // Load the slave address with read bit set + + /* Set the number of bytes to read */ + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read + } + + /* Enable RX Threshold interrupt for when the FIFO is full */ + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + /* Must have tx_len and/or rx_len */ + return E_BAD_PARAM; } - - i2c->inten0 = MXC_I2C_REVA_ERROR | MXC_F_I2C_REVA_INTEN0_TX_THD; + + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); + + /* Fill the FIFO as nessary */ + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + return E_NO_ERROR; - } - else { + } else { return E_BUSY; } } -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma) +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma) { int i2cNum; - - mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access - i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + + mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { return E_NOT_SUPPORTED; } - + if (i2cNum < 0) { return E_BAD_PARAM; } - + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { return E_BAD_STATE; } - + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { return E_BAD_PARAM; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); + states[i2cNum].req = req; - + states[i2cNum].channelTx = 0xFF; states[i2cNum].channelRx = 0xFF; - - #if TARGET_NUM == 32665 + +#if TARGET_NUM == 32665 MXC_DMA_Init(dma); - #else +#else MXC_DMA_Init(); - #endif - +#endif + //tx if ((req->tx_buf != NULL) && !(states[i2cNum].writeDone)) { - i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set - - #if TARGET_NUM == 32665 - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL, dma); - #else - MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL); - #endif - } - else { + i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL, dma); +#else + MXC_I2C_WriteTXFIFODMA((mxc_i2c_regs_t *)i2c, req->tx_buf, req->tx_len, NULL); +#endif + } else { states[i2cNum].writeDone = 1; } - - if (req->rx_buf != NULL) { - while(states[i2cNum].writeDone != 1); //Ensure DMA transmit has finished before attempting to receive - if ( (states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { + if (req->rx_buf != NULL) { + while (states[i2cNum].writeDone != 1) {} + //Ensure DMA transmit has finished before attempting to receive + + if ((states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; - } - else { + } else { i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read } - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); - - i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set + MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed - #if TARGET_NUM == 32665 - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL, dma); - #else - MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL); - #endif + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {} + + i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set + +#if TARGET_NUM == 32665 + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL, dma); +#else + MXC_I2C_ReadRXFIFODMA((mxc_i2c_regs_t *)i2c, req->rx_buf, req->rx_len, NULL); +#endif } - } - else { + } else { states[i2cNum].readDone = 1; } - + return E_NO_ERROR; } void MXC_I2C_RevA_DMACallback(int ch, int error) { mxc_i2c_reva_req_t *temp_req; - - for (int i = 0; i < MXC_I2C_INSTANCES; i ++) { + + for (int i = 0; i < MXC_I2C_INSTANCES; i++) { if (states[i].channelTx == ch) { //save the request temp_req = states[i].req; states[i].writeDone = 1; - + if (states[i].readDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); } } - } - - else if (states[i].channelRx == ch) { + } else if (states[i].channelRx == ch) { //save the request states[i].readDone = 1; temp_req = states[i].req; - + if (states[i].writeDone) { if (temp_req->restart) { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + MXC_DMA_ReleaseChannel(states[i].channelRx); MXC_DMA_ReleaseChannel(states[i].channelTx); - + // Callback if not NULL if (temp_req->callback != NULL) { temp_req->callback(temp_req, E_NO_ERROR); - } + } } } } } -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { unsigned int interruptEnables = interruptCheck; int retVal = E_NO_ERROR; - - if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + + if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + // Callback called on // Slave Address Match (distinguish read/write) // RX Threshold @@ -1026,98 +1049,110 @@ // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - + while (interruptEnables > 0) { interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal); } - + return retVal; } -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck) { - int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t*) i2c); - + int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + if (i2cnum < 0) { return E_BAD_PARAM; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { return E_BAD_STATE; } - + if (AsyncRequests[i2cnum] != NULL) { return E_BUSY; } - - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set TX threshold to 2 bytes - MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set RX threshold to 6 bytes - AsyncRequests[i2cnum] = (void *) callback; - + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 1); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 1); // set RX threshold to 6 bytes + AsyncRequests[i2cnum] = (void *)callback; + i2c->inten0 = interruptCheck; - + return E_NO_ERROR; } -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; - + unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; + if (numBytes > rxFIFOlen) { return E_BAD_PARAM; } - - i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); + + i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS; } -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes) { - unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; - + unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> + MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + if (numBytes > txFIFOlen) { return E_BAD_PARAM; } - - i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); + + i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | + (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); return E_NO_ERROR; } -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c) +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c) { return (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS; } -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal) +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)]; - + mxc_i2c_reva_req_t *req = + (mxc_i2c_reva_req_t *)AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)]; + if (req->callback != NULL) { req->callback(req, retVal); } } -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c) { + /* Disable and clear interrupts */ i2c->inten0 = 0; i2c->inten1 = 0; - + + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c) +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c) { // Don't need to check for return value as this function is not accessible to user // i2c is already cheked for NULL from where this function is being called @@ -1129,95 +1164,119 @@ { unsigned int written = AsyncWritten[i2cNum]; unsigned int read = AsyncRead[i2cNum]; - mxc_i2c_reva_regs_t* i2c = (mxc_i2c_reva_regs_t*) MXC_I2C_GET_BASE (i2cNum); - mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[i2cNum]; - + mxc_i2c_reva_regs_t *i2c = (mxc_i2c_reva_regs_t *)MXC_I2C_GET_BASE(i2cNum); + mxc_i2c_reva_req_t *req = (mxc_i2c_reva_req_t *)AsyncRequests[i2cNum]; + + /* Check for errors */ + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + /* Clear and disable interrupts */ + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + i2c->inten0 = 0; + i2c->inten1 = 0; + + MXC_I2C_Stop((mxc_i2c_regs_t *)i2c); + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + MXC_I2C_RevA_AsyncStop(i2c); + + return; + } + + /* Write data to the TX FIFO */ if (req->tx_len > written) { if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { - written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written], + req->tx_len - written); i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->tx_len = written; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); + + /* Enable the TX Threshold interrupt if we still need to write to the TX FIFO */ + if (written < req->tx_len) { + i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_TX_THD; + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_TX_THD); } - } - - if (req->rx_len > read) { - if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { - read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; - } - - if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - req->rx_len = read; - MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - MXC_I2C_RevA_AsyncStop (i2c); - } - - if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { - if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { - i2c->rxctrl1 = 0; - } - else { - i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read - } - + + /* Send a restart if we're reading after writing */ + if ((req->tx_len == written) && (req->rx_len)) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_DONE); } } - - if ( (req->tx_len == written) && (read == 0)) { - i2c->inten0 &= ~MXC_F_I2C_REVA_INTEN0_TX_THD; - i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE; - - if ( (req->rx_len) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + + /* Read data in the RX FIFO */ + if (req->rx_len > read) { + if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { + read += + MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; + } + } + + /* Done writing, still reading */ + if ((req->tx_len == written) && (req->rx_len - read) && + (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) { + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + + /* First done interrupt after completing writes to the TX FIFO */ + if (read == 0) { + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + + /* Set the number of bytes to read */ + if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { i2c->rxctrl1 = 0; + } else { + i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read } - else { - i2c->rxctrl1 = (req->rx_len); // 0 for 256, otherwise number of bytes to read + + /* Enable RX Threshold interrupt for when the FIFO is full */ + if (read < req->rx_len) { + i2c->inten0 |= (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + } else { + i2c->inten0 &= ~(MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); } - - MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed - - i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. } - - if ( (req->tx_len == written) && (req->rx_len == read)) { - i2c->inten0 &= ~ (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); - + + /* Done reading and writing */ + if ((req->tx_len == written) && (req->rx_len == read)) { + /* Disable and clear interrupts */ + i2c->inten0 = 0; + i2c->inten1 = 0; + i2c->intfl0 = i2c->intfl0; + i2c->intfl1 = i2c->intfl1; + + /* Send a restart or stop at the end of the transaction */ if (req->restart) { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; - } - else { + } else { i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; } - + + /* Call the callback */ if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { - MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); - } - else { + MXC_I2C_RevA_AsyncCallback(i2c, E_COMM_ERR); + } else { MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR); } - + + /* Clear the async state */ MXC_I2C_RevA_AsyncStop(i2c); + + } else { + AsyncWritten[i2cNum] = written; + AsyncRead[i2cNum] = read; } - - AsyncWritten[i2cNum] = written; - AsyncRead[i2cNum] = read; } -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal) +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal) { uint32_t tFlags = i2c->intfl0; *retVal = E_NO_ERROR; - + uint32_t readFlag = i2c->ctrl & MXC_F_I2C_REVA_CTRL_READ; // Callback called on // Slave Address Match (distinguish read/write) @@ -1235,114 +1294,161 @@ // I2C_EVT_TRANS_COMP // I2C_EVT_UNDERFLOW // I2C_EVT_OVERFLOW - if (!(interruptEnables & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH| MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { + if (!(interruptEnables & + (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH | + MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed // (fires anytime a stop/start is detected out of sequence). if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts - MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); - MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c); + MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) { - callback (i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV; } } - - if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { + + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { - callback (i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; } - + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) { - callback (i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + } + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN; } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } - + if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) { *retVal = E_NO_ERROR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } } if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; - } - - if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } - if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH){ - if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); } - else { - callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } + + if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH) { + if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + } + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; - interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | + MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } else { + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + } + + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | + MXC_I2C_REVA_ERROR; } } else if (tFlags & MXC_I2C_REVA_ERROR) { *retVal = E_COMM_ERR; - callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); - MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts + + if (callback != NULL) { + callback(i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + } + + MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, + MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts MXC_I2C_RevA_ClearTXFIFO(i2c); MXC_I2C_RevA_ClearRXFIFO(i2c); interruptEnables = 0; - AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] = NULL; } - + return interruptEnables; } -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck) +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck) { - int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); int slaveRetVal; - + if (i2cNum < 0) { return; } - + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { - MXC_I2C_RevA_MasterAsyncHandler (i2cNum); - } - else { - mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t) AsyncRequests[i2cNum]; - i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler (i2c, callback, i2c->inten0, &slaveRetVal); + MXC_I2C_RevA_MasterAsyncHandler(i2cNum); + } else { + mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t)AsyncRequests[i2cNum]; + i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, i2c->inten0, &slaveRetVal); } } diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h index df0e5ba..aa41e2c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h @@ -31,8 +31,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_H_ -#define _I2C_REVA_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ #include #include @@ -46,33 +46,34 @@ #include "i2c_reva_regs.h" #include "dma.h" - /* **** Definitions **** */ -#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F -#define MXC_I2C_REVA_STD_MODE 100000 -#define MXC_I2C_REVA_FAST_SPEED 400000 -#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 -#define MXC_I2C_REVA_HS_MODE 3400000 +#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F +#define MXC_I2C_REVA_STD_MODE 100000 +#define MXC_I2C_REVA_FAST_SPEED 400000 +#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 +#define MXC_I2C_REVA_HS_MODE 3400000 -#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF -#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 +#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF +#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 -#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 +#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 -#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \ - MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ - MXC_F_I2C_REVA_INTFL0_STOP_ERR) +#define MXC_I2C_REVA_ERROR \ + (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | \ + MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | MXC_F_I2C_REVA_INTFL0_DATA_ERR | \ + MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ + MXC_F_I2C_REVA_INTFL0_STOP_ERR) typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t; -typedef int (*mxc_i2c_reva_getAck_t) (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -typedef void (*mxc_i2c_reva_complete_cb_t) (mxc_i2c_reva_req_t* req, int result); -typedef void (*mxc_i2c_reva_dma_complete_cb_t) (int len, int result); +typedef int (*mxc_i2c_reva_getAck_t)(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +typedef void (*mxc_i2c_reva_complete_cb_t)(mxc_i2c_reva_req_t *req, int result); +typedef void (*mxc_i2c_reva_dma_complete_cb_t)(int len, int result); struct _i2c_reva_req_t { - mxc_i2c_reva_regs_t* i2c; + mxc_i2c_reva_regs_t *i2c; unsigned int addr; - unsigned char* tx_buf; + unsigned char *tx_buf; unsigned int tx_len; - unsigned char* rx_buf; + unsigned char *rx_buf; unsigned int rx_len; int restart; mxc_i2c_reva_complete_cb_t callback; @@ -86,74 +87,86 @@ MXC_I2C_REVA_EVT_UNDERFLOW, MXC_I2C_REVA_EVT_OVERFLOW, } mxc_i2c_reva_slave_event_t; -typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c, - mxc_i2c_reva_slave_event_t event, void* data); +typedef int (*mxc_i2c_reva_slave_handler_t)(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_event_t event, void *data); /* **** Variable Declaration **** */ -extern void* AsyncRequests[MXC_I2C_INSTANCES]; +extern void *AsyncRequests[MXC_I2C_INSTANCES]; /* **** Function Prototypes **** */ /* ************************************************************************* */ /* Control/Configuration functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr); -int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx); -int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz); -unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable); -int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr); +int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx); +int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz); +unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable); +int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c); /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte); -int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack); -int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck); -int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len); -int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack); -int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); -int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); -void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); -void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout); -unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries); +int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte); +int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack); +int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, + mxc_i2c_reva_getAck_t getAck); +int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len); +int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); +int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes, + unsigned int len); +int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, + mxc_dma_regs_t *dma); +int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); +void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout); +unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries); /* ************************************************************************* */ /* Transaction level functions */ /* ************************************************************************* */ -int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req); -int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma); -int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); -int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c); -int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); -unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); -void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); -void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); -unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); -void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck); -void MXC_I2C_RevA_DMACallback (int ch, int error); +int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req); +int MXC_I2C_RevA_MasterTransactionDMA(mxc_i2c_reva_req_t *req, mxc_dma_regs_t *dma); +int MXC_I2C_RevA_SlaveTransaction(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SlaveTransactionAsync(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + uint32_t interruptCheck); +int MXC_I2C_RevA_SetRXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetRXThreshold(mxc_i2c_reva_regs_t *i2c); +int MXC_I2C_RevA_SetTXThreshold(mxc_i2c_reva_regs_t *i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetTXThreshold(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal); +void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c); +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, + mxc_i2c_reva_slave_handler_t callback, + unsigned int interruptEnables, int *retVal); +void MXC_I2C_RevA_AsyncHandler(mxc_i2c_reva_regs_t *i2c, uint32_t interruptCheck); +void MXC_I2C_RevA_DMACallback(int ch, int error); -#endif /* _I2C_REVA_H_ */ \ No newline at end of file +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_H_ diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h index c15d5b4..49a4341 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h +++ b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h @@ -37,8 +37,8 @@ * *************************************************************************** */ -#ifndef _I2C_REVA_REGS_H_ -#define _I2C_REVA_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ /* **** Includes **** */ #include @@ -46,11 +46,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -115,25 +115,25 @@ * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. * @{ */ - #define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ - #define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ - #define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ - #define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ - #define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ - #define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ - #define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ - #define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ - #define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ - #define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ - #define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ - #define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ - #define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ - #define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ - #define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ - #define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ - #define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ - #define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ - #define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ +#define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ +#define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ +#define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ +#define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ +#define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ +#define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ +#define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ +#define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ +#define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ +#define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ +#define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ +#define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ +#define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ +#define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ +#define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ +#define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ +#define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ +#define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +#define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ /**@} end of group i2c_registers */ /** @@ -142,47 +142,47 @@ * @brief Control Register0. * @{ */ - #define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ - #define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ - #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ +#define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ - #define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ +#define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ - #define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ +#define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ - #define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ - #define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ +#define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ +#define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ - #define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ - #define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ +#define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ +#define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ - #define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ +#define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ +#define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ - #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ +#define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ - #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ +#define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ - #define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ - #define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ +#define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ +#define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ /**@} end of group I2C_CTRL_Register */ @@ -192,23 +192,23 @@ * @brief Status Register. * @{ */ - #define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ - #define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ +#define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ - #define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ +#define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ - #define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ +#define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ /**@} end of group I2C_STATUS_Register */ @@ -218,62 +218,62 @@ * @brief Interrupt Status Register. * @{ */ - #define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ - #define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ +#define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ +#define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ - #define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ - #define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ +#define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ - #define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ +#define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTFL0_Register */ @@ -283,62 +283,62 @@ * @brief Interrupt Enable Register. * @{ */ - #define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ - #define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ +#define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ +#define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ - #define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ - #define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ +#define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ +#define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ - #define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ +#define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ - #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ +#define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ - #define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ - #define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ +#define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ +#define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ - #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ /**@} end of group I2C_INTEN0_Register */ @@ -348,14 +348,14 @@ * @brief Interrupt Status Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ - #define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ +#define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ +#define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ /**@} end of group I2C_INTFL1_Register */ @@ -365,14 +365,14 @@ * @brief Interrupt Staus Register 1. * @{ */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ - #define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ +#define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ - #define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ +#define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ - #define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ - #define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ +#define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ +#define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ /**@} end of group I2C_INTEN1_Register */ @@ -382,11 +382,11 @@ * @brief FIFO Configuration Register. * @{ */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ - #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ +#define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ /**@} end of group I2C_FIFOLEN_Register */ @@ -396,14 +396,14 @@ * @brief Receive Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ - #define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ +#define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ /**@} end of group I2C_RXCTRL0_Register */ @@ -413,11 +413,11 @@ * @brief Receive Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ - #define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ +#define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ /**@} end of group I2C_RXCTRL1_Register */ @@ -427,29 +427,29 @@ * @brief Transmit Control Register 0. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ - #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ +#define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ - #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ +#define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ - #define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ +#define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ /**@} end of group I2C_TXCTRL0_Register */ @@ -459,11 +459,11 @@ * @brief Transmit Control Register 1. * @{ */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ - #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ +#define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ - #define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ +#define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ /**@} end of group I2C_TXCTRL1_Register */ @@ -473,8 +473,8 @@ * @brief Data Register. * @{ */ - #define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ /**@} end of group I2C_FIFO_Register */ @@ -484,17 +484,17 @@ * @brief Master Control Register. * @{ */ - #define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ - #define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ +#define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ - #define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ +#define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ - #define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ +#define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ - #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ +#define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ /**@} end of group I2C_MSTCTRL_Register */ @@ -504,8 +504,8 @@ * @brief Clock Low Register. * @{ */ - #define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ - #define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ +#define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ +#define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ /**@} end of group I2C_CLKLO_Register */ @@ -515,8 +515,8 @@ * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ - #define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ +#define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ +#define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ /**@} end of group I2C_CLKHI_Register */ @@ -526,11 +526,11 @@ * @brief Clock high Register. * @{ */ - #define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ - #define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ +#define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ +#define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ - #define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ - #define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ +#define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ +#define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ /**@} end of group I2C_HSCLK_Register */ @@ -540,8 +540,8 @@ * @brief Timeout Register * @{ */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ - #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ +#define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ /**@} end of group I2C_TIMEOUT_Register */ @@ -551,11 +551,11 @@ * @brief DMA Register. * @{ */ - #define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ - #define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ +#define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - #define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ - #define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ +#define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ /**@} end of group I2C_DMA_Register */ @@ -565,11 +565,11 @@ * @brief Slave Address Register. * @{ */ - #define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ - #define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ +#define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ +#define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ - #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ +#define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ /**@} end of group I2C_SLAVE_Register */ @@ -577,4 +577,5 @@ } #endif -#endif /* _I2C_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I2C_I2C_REVA_REGS_H_ + diff --git a/targets/TARGET_Maxim/USBPhy_Maxim.cpp b/targets/TARGET_Maxim/USBPhy_Maxim.cpp index e2fbd79..687fb98 100644 --- a/targets/TARGET_Maxim/USBPhy_Maxim.cpp +++ b/targets/TARGET_Maxim/USBPhy_Maxim.cpp @@ -16,7 +16,7 @@ */ #if defined(DEVICE_USBDEVICE) && (DEVICE_USBDEVICE) && \ - (defined(TARGET_MAX32620) || defined(TARGET_MAX32625) || defined(TARGET_MAX32630)) + (defined(TARGET_MAX32620C) || defined(TARGET_MAX32625) || defined(TARGET_MAX32630)) #include "mbed.h" #include "USBPhyHw.h" @@ -111,7 +111,7 @@ NVIC_DisableIRQ(USB_IRQn); // Enable the USB clock -#if defined(TARGET_MAX32620) +#if defined(TARGET_MAX32620C) MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE; #elif defined(TARGET_MAX32625) || defined(TARGET_MAX32630) MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED; diff --git a/targets/TARGET_NUVOTON/CMakeLists.txt b/targets/TARGET_NUVOTON/CMakeLists.txt index 2618b54..2119a10 100644 --- a/targets/TARGET_NUVOTON/CMakeLists.txt +++ b/targets/TARGET_NUVOTON/CMakeLists.txt @@ -6,6 +6,7 @@ add_subdirectory(TARGET_M251 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_M261 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_M451 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_M460 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_M480 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_NANO100 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_NUC472 EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin index 80dfd68..316981f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin Binary files differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf index 0bf9982..c623aed 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf Binary files differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin index e8f3b9b..321ac85 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin Binary files differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/i2c_api.c index 65a9553..0009905 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M2354/i2c_api.c @@ -441,13 +441,13 @@ case 0x08: // Start case 0x10: // Master Repeat Start if (i2c_ctl & I2C_CTL0_STA_Msk) { - return 0; + goto cleanup; } else { break; } case 0xF8: // Bus Released if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) { - return 0; + goto cleanup; } else { break; } @@ -458,6 +458,8 @@ } } +cleanup: + i2c_enable_int(obj); return err; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c index b07e088..e0ea415 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c @@ -425,13 +425,13 @@ case 0x08: // Start case 0x10: // Master Repeat Start if (i2c_ctl & I2C_CTL0_STA_Msk) { - return 0; + goto cleanup; } else { break; } case 0xF8: // Bus Released if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) { - return 0; + goto cleanup; } else { break; } @@ -442,6 +442,8 @@ } } +cleanup: + i2c_enable_int(obj); return err; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c index 16b5a44..4e1752f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c @@ -430,13 +430,13 @@ case 0x08: // Start case 0x10: // Master Repeat Start if (i2c_ctl & I2C_CTL0_STA_Msk) { - return 0; + goto cleanup; } else { break; } case 0xF8: // Bus Released if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) { - return 0; + goto cleanup; } else { break; } @@ -447,6 +447,8 @@ } } +cleanup: + i2c_enable_int(obj); return err; diff --git a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c index d9de137..452131c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c @@ -448,14 +448,14 @@ case 0x08: // Start case 0x10: // Master Repeat Start if (i2c_ctl & I2C_CTL_STA_Msk) { - return 0; + goto cleanup; } else { break; } case 0xF8: // Bus Released if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) { - return 0; + goto cleanup; } else { break; @@ -472,8 +472,10 @@ } } +cleanup: + i2c_enable_int(obj); - + return err; } diff --git a/targets/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt new file mode 100644 index 0000000..2714ef9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/CMakeLists.txt @@ -0,0 +1,105 @@ +# Copyright (c) 2022 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/M467.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LINKER_FILE device/TOOLCHAIN_ARM_STD/M467.sct) +endif() + +add_library(mbed-m460 INTERFACE) + +target_sources(mbed-m460 + INTERFACE + analogin_api.c + analogout_api.c + + crypto/crypto-misc.cpp + + device/startup_M460.c + device/system_M460.c + device/StdDriver/src/m460_acmp.c + device/StdDriver/src/m460_bmc.c + device/StdDriver/src/m460_bpwm.c + device/StdDriver/src/m460_canfd.c + device/StdDriver/src/m460_ccap.c + device/StdDriver/src/m460_clk.c + device/StdDriver/src/m460_crc.c + device/StdDriver/src/m460_crypto.c + device/StdDriver/src/m460_dac.c + device/StdDriver/src/m460_eadc.c + device/StdDriver/src/m460_ebi.c + device/StdDriver/src/m460_ecap.c + device/StdDriver/src/m460_epwm.c + device/StdDriver/src/m460_eqei.c + device/StdDriver/src/m460_fmc.c + device/StdDriver/src/m460_gpio.c + device/StdDriver/src/m460_hbi.c + device/StdDriver/src/m460_hsusbd.c + device/StdDriver/src/m460_i2c.c + device/StdDriver/src/m460_i2s.c + device/StdDriver/src/m460_keystore.c + device/StdDriver/src/m460_kpi.c + device/StdDriver/src/m460_pdma.c + device/StdDriver/src/m460_qspi.c + device/StdDriver/src/m460_rng.c + device/StdDriver/src/m460_rtc.c + device/StdDriver/src/m460_sc.c + device/StdDriver/src/m460_scuart.c + device/StdDriver/src/m460_sdh.c + device/StdDriver/src/m460_spi.c + device/StdDriver/src/m460_spim.c + device/StdDriver/src/m460_sys.c + device/StdDriver/src/m460_timer.c + device/StdDriver/src/m460_timer_pwm.c + device/StdDriver/src/m460_trng.c + device/StdDriver/src/m460_uart.c + device/StdDriver/src/m460_usbd.c + device/StdDriver/src/m460_usci_i2c.c + device/StdDriver/src/m460_usci_spi.c + device/StdDriver/src/m460_usci_uart.c + device/StdDriver/src/m460_wdt.c + device/StdDriver/src/m460_wwdt.c + + dma_api.c + flash_api.c + gpio_api.c + gpio_irq_api.c + i2c_api.c + lp_ticker.c + mbed_overrides.c + PeripheralPins.c + pinmap.c + port_api.c + pwmout_api.c + reset_reason.c + rtc_api.c + serial_api.c + sleep.c + spi_api.c + trng_api.cpp + us_ticker.c + watchdog_api.c +) + +target_include_directories(mbed-m460 + INTERFACE + . + crypto + device + device/Reg + device/StdDriver/inc +) + +target_link_libraries(mbed-m460 INTERFACE mbed-nuvoton mbed-flash-cmsis-algo) + +mbed_set_linker_script(mbed-m460 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +add_library(mbed-numaker-iot-m467 INTERFACE) + +target_include_directories(mbed-numaker-iot-m467 + INTERFACE + TARGET_NUMAKER_IOT_M467 +) + +target_link_libraries(mbed-numaker-iot-m467 INTERFACE mbed-m460) diff --git a/targets/TARGET_NUVOTON/TARGET_M460/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M460/PeripheralNames.h new file mode 100644 index 0000000..b528b96 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/PeripheralNames.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name +// which encodes module base address and module index/subindex. +#define NU_MODSUBINDEX_Pos 0 +#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos) +#define NU_MODINDEX_Pos 20 +#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos) + +#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos)) +#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk)) +#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos) +#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos) + +#if 0 +typedef enum { + GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0), + GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0), + GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0), + GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0), + GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0), + GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0), + GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 6, 0), + GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 7, 0), + GPIO_I = (int) NU_MODNAME(GPIOI_BASE, 8, 0), + GPIO_J = (int) NU_MODNAME(GPIOJ_BASE, 9, 0), +} GPIOName; +#endif + +typedef enum { + /* EADC0 */ + ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0, 0), + ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 0, 1), + ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 0, 2), + ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 0, 3), + ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 0, 4), + ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 0, 5), + ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 0, 6), + ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 0, 7), + ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 0, 8), + ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 0, 9), + ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 0, 10), + ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 0, 11), + ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 0, 12), + ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 0, 13), + ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 0, 14), + ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15), + + /* EADC1 */ + ADC_1_0 = (int) NU_MODNAME(EADC1_BASE, 1, 0), + ADC_1_1 = (int) NU_MODNAME(EADC1_BASE, 1, 1), + ADC_1_2 = (int) NU_MODNAME(EADC1_BASE, 1, 2), + ADC_1_3 = (int) NU_MODNAME(EADC1_BASE, 1, 3), + ADC_1_4 = (int) NU_MODNAME(EADC1_BASE, 1, 4), + ADC_1_5 = (int) NU_MODNAME(EADC1_BASE, 1, 5), + ADC_1_6 = (int) NU_MODNAME(EADC1_BASE, 1, 6), + ADC_1_7 = (int) NU_MODNAME(EADC1_BASE, 1, 7), + ADC_1_8 = (int) NU_MODNAME(EADC1_BASE, 1, 8), + ADC_1_9 = (int) NU_MODNAME(EADC1_BASE, 1, 9), + ADC_1_10 = (int) NU_MODNAME(EADC1_BASE, 1, 10), + ADC_1_11 = (int) NU_MODNAME(EADC1_BASE, 1, 11), + ADC_1_12 = (int) NU_MODNAME(EADC1_BASE, 1, 12), + ADC_1_13 = (int) NU_MODNAME(EADC1_BASE, 1, 13), + ADC_1_14 = (int) NU_MODNAME(EADC1_BASE, 1, 14), + ADC_1_15 = (int) NU_MODNAME(EADC1_BASE, 1, 15), + + /* EADC2 */ + ADC_2_0 = (int) NU_MODNAME(EADC2_BASE, 2, 0), + ADC_2_1 = (int) NU_MODNAME(EADC2_BASE, 2, 1), + ADC_2_2 = (int) NU_MODNAME(EADC2_BASE, 2, 2), + ADC_2_3 = (int) NU_MODNAME(EADC2_BASE, 2, 3), + ADC_2_4 = (int) NU_MODNAME(EADC2_BASE, 2, 4), + ADC_2_5 = (int) NU_MODNAME(EADC2_BASE, 2, 5), + ADC_2_6 = (int) NU_MODNAME(EADC2_BASE, 2, 6), + ADC_2_7 = (int) NU_MODNAME(EADC2_BASE, 2, 7), + ADC_2_8 = (int) NU_MODNAME(EADC2_BASE, 2, 8), + ADC_2_9 = (int) NU_MODNAME(EADC2_BASE, 2, 9), + ADC_2_10 = (int) NU_MODNAME(EADC2_BASE, 2, 10), + ADC_2_11 = (int) NU_MODNAME(EADC2_BASE, 2, 11), + ADC_2_12 = (int) NU_MODNAME(EADC2_BASE, 2, 12), + ADC_2_13 = (int) NU_MODNAME(EADC2_BASE, 2, 13), + ADC_2_14 = (int) NU_MODNAME(EADC2_BASE, 2, 14), + ADC_2_15 = (int) NU_MODNAME(EADC2_BASE, 2, 15), +} ADCName; + +typedef enum { + DAC_0_0 = (int) NU_MODNAME(DAC0_BASE, 0, 0), + DAC_1_0 = (int) NU_MODNAME(DAC1_BASE, 1, 0), +} DACName; + +typedef enum { + UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), + UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), + UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0), + UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0), + UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0), + UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0), + UART_6 = (int) NU_MODNAME(UART6_BASE, 6, 0), + UART_7 = (int) NU_MODNAME(UART7_BASE, 7, 0), + UART_8 = (int) NU_MODNAME(UART8_BASE, 8, 0), + UART_9 = (int) NU_MODNAME(UART9_BASE, 9, 0), + // NOTE: board-specific +#if defined(MBED_CONF_TARGET_USB_UART) + USB_UART = MBED_CONF_TARGET_USB_UART, +#else + USB_UART = NC, +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART) + STDIO_UART = MBED_CONF_TARGET_STDIO_UART, +#else + STDIO_UART = USB_UART, +#endif +} UARTName; + +typedef enum { + SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0), + SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0), + SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0), + SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0), + SPI_4 = (int) NU_MODNAME(SPI4_BASE, 4, 0), + SPI_5 = (int) NU_MODNAME(SPI5_BASE, 5, 0), + SPI_6 = (int) NU_MODNAME(SPI6_BASE, 6, 0), + SPI_7 = (int) NU_MODNAME(SPI7_BASE, 7, 0), + SPI_8 = (int) NU_MODNAME(SPI8_BASE, 8, 0), + SPI_9 = (int) NU_MODNAME(SPI9_BASE, 9, 0), + SPI_10 = (int) NU_MODNAME(SPI10_BASE, 10, 0), + + /* No SPI11/12 H/W, degrade QSPI0/1 H/W to SPI_11/12 for standard SPI usage */ + SPI_11 = (int) NU_MODNAME(QSPI0_BASE, 11, 0), + SPI_12 = (int) NU_MODNAME(QSPI1_BASE, 12, 0), +} SPIName; + +typedef enum { + I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0), + I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0), + I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0), + I2C_3 = (int) NU_MODNAME(I2C3_BASE, 3, 0), + I2C_4 = (int) NU_MODNAME(I2C4_BASE, 4, 0), +} I2CName; + +typedef enum { + PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE, 0, 0), + PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE, 0, 1), + PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE, 0, 2), + PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE, 0, 3), + PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE, 0, 4), + PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE, 0, 5), + + PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE, 1, 0), + PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE, 1, 1), + PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE, 1, 2), + PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE, 1, 3), + PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE, 1, 4), + PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE, 1, 5), +} PWMName; + +typedef enum { + TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0, 0), + TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 1, 0), + TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 2, 0), + TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 3, 0), +} TIMERName; + +typedef enum { + RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0), +} RTCName; + +typedef enum { + DMA_0 = (int) NU_MODNAME(PDMA0_BASE, 0, 0), + DMA_1 = (int) NU_MODNAME(PDMA1_BASE, 1, 0), +} DMAName; + +typedef enum { + SD_0 = (int) NU_MODNAME(SDH0_BASE, 0, 0), + SD_1 = (int) NU_MODNAME(SDH1_BASE, 1, 0), +} SDName; + +typedef enum { + CAN_0 = (int) NU_MODNAME(CANFD0_BASE, 0, 0), + CAN_1 = (int) NU_MODNAME(CANFD1_BASE, 1, 0), + CAN_2 = (int) NU_MODNAME(CANFD2_BASE, 2, 0), + CAN_3 = (int) NU_MODNAME(CANFD3_BASE, 3, 0), +} CANName; + +typedef enum { + TRNG_0 = (int) NU_MODNAME(TRNG_BASE, 0, 0), +} TRNGName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M460/PeripheralPins.c new file mode 100644 index 0000000..77d124c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/PeripheralPins.c @@ -0,0 +1,1078 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_8, ADC_1_4, SYS_GPA_MFP2_PA8MFP_EADC1_CH4}, + {NU_PINNAME_BIND(PA_8, ADC_1_4), ADC_1_4, SYS_GPA_MFP2_PA8MFP_EADC1_CH4}, + {PA_8, ADC_2_4, SYS_GPA_MFP2_PA8MFP_EADC2_CH4}, + {NU_PINNAME_BIND(PA_8, ADC_2_4), ADC_2_4, SYS_GPA_MFP2_PA8MFP_EADC2_CH4}, + {PA_9, ADC_1_5, SYS_GPA_MFP2_PA9MFP_EADC1_CH5}, + {NU_PINNAME_BIND(PA_9, ADC_1_5), ADC_1_5, SYS_GPA_MFP2_PA9MFP_EADC1_CH5}, + {PA_9, ADC_2_5, SYS_GPA_MFP2_PA9MFP_EADC2_CH5}, + {NU_PINNAME_BIND(PA_9, ADC_2_5), ADC_2_5, SYS_GPA_MFP2_PA9MFP_EADC2_CH5}, + {PA_10, ADC_1_6, SYS_GPA_MFP2_PA10MFP_EADC1_CH6}, + {NU_PINNAME_BIND(PA_10, ADC_1_6), ADC_1_6, SYS_GPA_MFP2_PA10MFP_EADC1_CH6}, + {PA_10, ADC_2_6, SYS_GPA_MFP2_PA10MFP_EADC2_CH6}, + {NU_PINNAME_BIND(PA_10, ADC_2_6), ADC_2_6, SYS_GPA_MFP2_PA10MFP_EADC2_CH6}, + {PA_11, ADC_1_7, SYS_GPA_MFP2_PA11MFP_EADC1_CH7}, + {NU_PINNAME_BIND(PA_11, ADC_1_7), ADC_1_7, SYS_GPA_MFP2_PA11MFP_EADC1_CH7}, + {PA_11, ADC_2_7, SYS_GPA_MFP2_PA11MFP_EADC2_CH7}, + {NU_PINNAME_BIND(PA_11, ADC_2_7), ADC_2_7, SYS_GPA_MFP2_PA11MFP_EADC2_CH7}, + {PB_0, ADC_0_0, SYS_GPB_MFP0_PB0MFP_EADC0_CH0}, + {NU_PINNAME_BIND(PB_0, ADC_0_0), ADC_0_0, SYS_GPB_MFP0_PB0MFP_EADC0_CH0}, + {PB_0, ADC_1_8, SYS_GPB_MFP0_PB0MFP_EADC1_CH8}, + {NU_PINNAME_BIND(PB_0, ADC_1_8), ADC_1_8, SYS_GPB_MFP0_PB0MFP_EADC1_CH8}, + {PB_0, ADC_2_8, SYS_GPB_MFP0_PB0MFP_EADC2_CH8}, + {NU_PINNAME_BIND(PB_0, ADC_2_8), ADC_2_8, SYS_GPB_MFP0_PB0MFP_EADC2_CH8}, + {PB_1, ADC_0_1, SYS_GPB_MFP0_PB1MFP_EADC0_CH1}, + {NU_PINNAME_BIND(PB_1, ADC_0_1), ADC_0_1, SYS_GPB_MFP0_PB1MFP_EADC0_CH1}, + {PB_1, ADC_1_9, SYS_GPB_MFP0_PB1MFP_EADC1_CH9}, + {NU_PINNAME_BIND(PB_1, ADC_1_9), ADC_1_9, SYS_GPB_MFP0_PB1MFP_EADC1_CH9}, + {PB_1, ADC_2_9, SYS_GPB_MFP0_PB1MFP_EADC2_CH9}, + {NU_PINNAME_BIND(PB_1, ADC_2_9), ADC_2_9, SYS_GPB_MFP0_PB1MFP_EADC2_CH9}, + {PB_2, ADC_0_2, SYS_GPB_MFP0_PB2MFP_EADC0_CH2}, + {NU_PINNAME_BIND(PB_2, ADC_0_2), ADC_0_2, SYS_GPB_MFP0_PB2MFP_EADC0_CH2}, + {PB_2, ADC_1_10, SYS_GPB_MFP0_PB2MFP_EADC1_CH10}, + {NU_PINNAME_BIND(PB_2, ADC_1_10), ADC_1_10, SYS_GPB_MFP0_PB2MFP_EADC1_CH10}, + {PB_3, ADC_0_3, SYS_GPB_MFP0_PB3MFP_EADC0_CH3}, + {NU_PINNAME_BIND(PB_3, ADC_0_3), ADC_0_3, SYS_GPB_MFP0_PB3MFP_EADC0_CH3}, + {PB_3, ADC_1_11, SYS_GPB_MFP0_PB3MFP_EADC1_CH11}, + {NU_PINNAME_BIND(PB_3, ADC_1_11), ADC_1_11, SYS_GPB_MFP0_PB3MFP_EADC1_CH11}, + {PB_4, ADC_0_4, SYS_GPB_MFP1_PB4MFP_EADC0_CH4}, + {PB_5, ADC_0_5, SYS_GPB_MFP1_PB5MFP_EADC0_CH5}, + {PB_6, ADC_0_6, SYS_GPB_MFP1_PB6MFP_EADC0_CH6}, + {NU_PINNAME_BIND(PB_6, ADC_0_6), ADC_0_6, SYS_GPB_MFP1_PB6MFP_EADC0_CH6}, + {PB_6, ADC_2_14, SYS_GPB_MFP1_PB6MFP_EADC2_CH14}, + {NU_PINNAME_BIND(PB_6, ADC_2_14), ADC_2_14, SYS_GPB_MFP1_PB6MFP_EADC2_CH14}, + {PB_7, ADC_0_7, SYS_GPB_MFP1_PB7MFP_EADC0_CH7}, + {NU_PINNAME_BIND(PB_7, ADC_0_7), ADC_0_7, SYS_GPB_MFP1_PB7MFP_EADC0_CH7}, + {PB_7, ADC_2_15, SYS_GPB_MFP1_PB7MFP_EADC2_CH15}, + {NU_PINNAME_BIND(PB_7, ADC_2_15), ADC_2_15, SYS_GPB_MFP1_PB7MFP_EADC2_CH15}, + {PB_8, ADC_0_8, SYS_GPB_MFP2_PB8MFP_EADC0_CH8}, + {PB_9, ADC_0_9, SYS_GPB_MFP2_PB9MFP_EADC0_CH9}, + {PB_10, ADC_0_10, SYS_GPB_MFP2_PB10MFP_EADC0_CH10}, + {PB_11, ADC_0_11, SYS_GPB_MFP2_PB11MFP_EADC0_CH11}, + {PB_12, ADC_0_12, SYS_GPB_MFP3_PB12MFP_EADC0_CH12}, + {NU_PINNAME_BIND(PB_12, ADC_0_12), ADC_0_12, SYS_GPB_MFP3_PB12MFP_EADC0_CH12}, + {PB_12, ADC_1_12, SYS_GPB_MFP3_PB12MFP_EADC1_CH12}, + {NU_PINNAME_BIND(PB_12, ADC_1_12), ADC_1_12, SYS_GPB_MFP3_PB12MFP_EADC1_CH12}, + {PB_13, ADC_0_13, SYS_GPB_MFP3_PB13MFP_EADC0_CH13}, + {NU_PINNAME_BIND(PB_13, ADC_0_13), ADC_0_13, SYS_GPB_MFP3_PB13MFP_EADC0_CH13}, + {PB_13, ADC_1_13, SYS_GPB_MFP3_PB13MFP_EADC1_CH13}, + {NU_PINNAME_BIND(PB_13, ADC_1_13), ADC_1_13, SYS_GPB_MFP3_PB13MFP_EADC1_CH13}, + {PB_14, ADC_0_14, SYS_GPB_MFP3_PB14MFP_EADC0_CH14}, + {NU_PINNAME_BIND(PB_14, ADC_0_14), ADC_0_14, SYS_GPB_MFP3_PB14MFP_EADC0_CH14}, + {PB_14, ADC_1_14, SYS_GPB_MFP3_PB14MFP_EADC1_CH14}, + {NU_PINNAME_BIND(PB_14, ADC_1_14), ADC_1_14, SYS_GPB_MFP3_PB14MFP_EADC1_CH14}, + {PB_15, ADC_0_15, SYS_GPB_MFP3_PB15MFP_EADC0_CH15}, + {NU_PINNAME_BIND(PB_15, ADC_0_15), ADC_0_15, SYS_GPB_MFP3_PB15MFP_EADC0_CH15}, + {PB_15, ADC_1_15, SYS_GPB_MFP3_PB15MFP_EADC1_CH15}, + {NU_PINNAME_BIND(PB_15, ADC_1_15), ADC_1_15, SYS_GPB_MFP3_PB15MFP_EADC1_CH15}, + {PC_9, ADC_2_10, SYS_GPC_MFP2_PC9MFP_EADC2_CH10}, + {PC_10, ADC_2_11, SYS_GPC_MFP2_PC10MFP_EADC2_CH11}, + {PC_11, ADC_2_12, SYS_GPC_MFP2_PC11MFP_EADC2_CH12}, + {PC_12, ADC_2_13, SYS_GPC_MFP3_PC12MFP_EADC2_CH13}, + {PC_13, ADC_1_3, SYS_GPC_MFP3_PC13MFP_EADC1_CH3}, + {NU_PINNAME_BIND(PC_13, ADC_1_3), ADC_1_3, SYS_GPC_MFP3_PC13MFP_EADC1_CH3}, + {PC_13, ADC_2_3, SYS_GPC_MFP3_PC13MFP_EADC2_CH3}, + {NU_PINNAME_BIND(PC_13, ADC_2_3), ADC_2_3, SYS_GPC_MFP3_PC13MFP_EADC2_CH3}, + {PD_10, ADC_1_0, SYS_GPD_MFP2_PD10MFP_EADC1_CH0}, + {NU_PINNAME_BIND(PD_10, ADC_1_0), ADC_1_0, SYS_GPD_MFP2_PD10MFP_EADC1_CH0}, + {PD_10, ADC_2_0, SYS_GPD_MFP2_PD10MFP_EADC2_CH0}, + {NU_PINNAME_BIND(PD_10, ADC_2_0), ADC_2_0, SYS_GPD_MFP2_PD10MFP_EADC2_CH0}, + {PD_11, ADC_1_1, SYS_GPD_MFP2_PD11MFP_EADC1_CH1}, + {NU_PINNAME_BIND(PD_11, ADC_1_1), ADC_1_1, SYS_GPD_MFP2_PD11MFP_EADC1_CH1}, + {PD_11, ADC_2_1, SYS_GPD_MFP2_PD11MFP_EADC2_CH1}, + {NU_PINNAME_BIND(PD_11, ADC_2_1), ADC_2_1, SYS_GPD_MFP2_PD11MFP_EADC2_CH1}, + {PD_12, ADC_1_2, SYS_GPD_MFP3_PD12MFP_EADC1_CH2}, + {NU_PINNAME_BIND(PD_12, ADC_1_2), ADC_1_2, SYS_GPD_MFP3_PD12MFP_EADC1_CH2}, + {PD_12, ADC_2_2, SYS_GPD_MFP3_PD12MFP_EADC2_CH2}, + {NU_PINNAME_BIND(PD_12, ADC_2_2), ADC_2_2, SYS_GPD_MFP3_PD12MFP_EADC2_CH2}, + + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PB_12, DAC_0_0, SYS_GPB_MFP3_PB12MFP_DAC0_OUT}, + {PB_13, DAC_1_0, SYS_GPB_MFP3_PB13MFP_DAC1_OUT}, + + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_0, I2C_2, SYS_GPA_MFP0_PA0MFP_I2C2_SDA}, + {PA_2, I2C_1, SYS_GPA_MFP0_PA2MFP_I2C1_SDA}, + {PA_4, I2C_0, SYS_GPA_MFP1_PA4MFP_I2C0_SDA}, + {PA_6, I2C_1, SYS_GPA_MFP1_PA6MFP_I2C1_SDA}, + {PA_10, I2C_2, SYS_GPA_MFP2_PA10MFP_I2C2_SDA}, + {PA_13, I2C_1, SYS_GPA_MFP3_PA13MFP_I2C1_SDA}, + {PA_15, I2C_0, SYS_GPA_MFP3_PA15MFP_I2C0_SDA}, + {NU_PINNAME_BIND(PA_15, I2C_0), I2C_0, SYS_GPA_MFP3_PA15MFP_I2C0_SDA}, + {PA_15, I2C_2, SYS_GPA_MFP3_PA15MFP_I2C2_SDA}, + {NU_PINNAME_BIND(PA_15, I2C_2), I2C_2, SYS_GPA_MFP3_PA15MFP_I2C2_SDA}, + {PB_0, I2C_1, SYS_GPB_MFP0_PB0MFP_I2C1_SDA}, + {PB_2, I2C_1, SYS_GPB_MFP0_PB2MFP_I2C1_SDA}, + {PB_4, I2C_0, SYS_GPB_MFP1_PB4MFP_I2C0_SDA}, + {PB_8, I2C_0, SYS_GPB_MFP2_PB8MFP_I2C0_SDA}, + {PB_10, I2C_1, SYS_GPB_MFP2_PB10MFP_I2C1_SDA}, + {PB_12, I2C_2, SYS_GPB_MFP3_PB12MFP_I2C2_SDA}, + {PC_0, I2C_0, SYS_GPC_MFP0_PC0MFP_I2C0_SDA}, + {PC_2, I2C_3, SYS_GPC_MFP0_PC2MFP_I2C3_SDA}, + {PC_4, I2C_1, SYS_GPC_MFP1_PC4MFP_I2C1_SDA}, + {PC_8, I2C_0, SYS_GPC_MFP2_PC8MFP_I2C0_SDA}, + {PC_11, I2C_0, SYS_GPC_MFP2_PC11MFP_I2C0_SDA}, + {NU_PINNAME_BIND(PC_11, I2C_0), I2C_0, SYS_GPC_MFP2_PC11MFP_I2C0_SDA}, + {PC_11, I2C_4, SYS_GPC_MFP2_PC11MFP_I2C4_SDA}, + {NU_PINNAME_BIND(PC_11, I2C_4), I2C_4, SYS_GPC_MFP2_PC11MFP_I2C4_SDA}, + {PD_0, I2C_2, SYS_GPD_MFP0_PD0MFP_I2C2_SDA}, + {PD_4, I2C_1, SYS_GPD_MFP1_PD4MFP_I2C1_SDA}, + {PD_6, I2C_0, SYS_GPD_MFP1_PD6MFP_I2C0_SDA}, + {PD_8, I2C_2, SYS_GPD_MFP2_PD8MFP_I2C2_SDA}, + {PE_0, I2C_1, SYS_GPE_MFP0_PE0MFP_I2C1_SDA}, + {PF_1, I2C_0, SYS_GPF_MFP0_PF1MFP_I2C0_SDA}, + {NU_PINNAME_BIND(PF_1, I2C_0), I2C_0, SYS_GPF_MFP0_PF1MFP_I2C0_SDA}, + {PF_1, I2C_1, SYS_GPF_MFP0_PF1MFP_I2C1_SDA}, + {NU_PINNAME_BIND(PF_1, I2C_1), I2C_1, SYS_GPF_MFP0_PF1MFP_I2C1_SDA}, + {PF_2, I2C_0, SYS_GPF_MFP0_PF2MFP_I2C0_SDA}, + {PF_4, I2C_4, SYS_GPF_MFP1_PF4MFP_I2C4_SDA}, + {PG_1, I2C_0, SYS_GPG_MFP0_PG1MFP_I2C0_SDA}, + {NU_PINNAME_BIND(PG_1, I2C_0), I2C_0, SYS_GPG_MFP0_PG1MFP_I2C0_SDA}, + {PG_1, I2C_3, SYS_GPG_MFP0_PG1MFP_I2C3_SDA}, + {NU_PINNAME_BIND(PG_1, I2C_3), I2C_3, SYS_GPG_MFP0_PG1MFP_I2C3_SDA}, + {PG_3, I2C_1, SYS_GPG_MFP0_PG3MFP_I2C1_SDA}, + {PG_8, I2C_3, SYS_GPG_MFP2_PG8MFP_I2C3_SDA}, + {PG_10, I2C_4, SYS_GPG_MFP2_PG10MFP_I2C4_SDA}, + {PH_3, I2C_0, SYS_GPH_MFP0_PH3MFP_I2C0_SDA}, + {PH_9, I2C_2, SYS_GPH_MFP2_PH9MFP_I2C2_SDA}, + {PI_7, I2C_1, SYS_GPI_MFP1_PI7MFP_I2C1_SDA}, + {PI_11, I2C_0, SYS_GPI_MFP2_PI11MFP_I2C0_SDA}, + {PI_15, I2C_3, SYS_GPI_MFP3_PI15MFP_I2C3_SDA}, + {PJ_11, I2C_4, SYS_GPJ_MFP2_PJ11MFP_I2C4_SDA}, + + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_1, I2C_2, SYS_GPA_MFP0_PA1MFP_I2C2_SCL}, + {PA_3, I2C_1, SYS_GPA_MFP0_PA3MFP_I2C1_SCL}, + {PA_5, I2C_0, SYS_GPA_MFP1_PA5MFP_I2C0_SCL}, + {PA_7, I2C_1, SYS_GPA_MFP1_PA7MFP_I2C1_SCL}, + {PA_11, I2C_2, SYS_GPA_MFP2_PA11MFP_I2C2_SCL}, + {PA_12, I2C_1, SYS_GPA_MFP3_PA12MFP_I2C1_SCL}, + {PA_14, I2C_0, SYS_GPA_MFP3_PA14MFP_I2C0_SCL}, + {NU_PINNAME_BIND(PA_14, I2C_0), I2C_0, SYS_GPA_MFP3_PA14MFP_I2C0_SCL}, + {PA_14, I2C_2, SYS_GPA_MFP3_PA14MFP_I2C2_SCL}, + {NU_PINNAME_BIND(PA_14, I2C_2), I2C_2, SYS_GPA_MFP3_PA14MFP_I2C2_SCL}, + {PB_1, I2C_1, SYS_GPB_MFP0_PB1MFP_I2C1_SCL}, + {PB_3, I2C_1, SYS_GPB_MFP0_PB3MFP_I2C1_SCL}, + {PB_5, I2C_0, SYS_GPB_MFP1_PB5MFP_I2C0_SCL}, + {PB_9, I2C_0, SYS_GPB_MFP2_PB9MFP_I2C0_SCL}, + {PB_11, I2C_1, SYS_GPB_MFP2_PB11MFP_I2C1_SCL}, + {PB_13, I2C_2, SYS_GPB_MFP3_PB13MFP_I2C2_SCL}, + {PC_1, I2C_0, SYS_GPC_MFP0_PC1MFP_I2C0_SCL}, + {PC_3, I2C_3, SYS_GPC_MFP0_PC3MFP_I2C3_SCL}, + {PC_5, I2C_1, SYS_GPC_MFP1_PC5MFP_I2C1_SCL}, + {PC_12, I2C_0, SYS_GPC_MFP3_PC12MFP_I2C0_SCL}, + {NU_PINNAME_BIND(PC_12, I2C_0), I2C_0, SYS_GPC_MFP3_PC12MFP_I2C0_SCL}, + {PC_12, I2C_4, SYS_GPC_MFP3_PC12MFP_I2C4_SCL}, + {NU_PINNAME_BIND(PC_12, I2C_4), I2C_4, SYS_GPC_MFP3_PC12MFP_I2C4_SCL}, + {PD_1, I2C_2, SYS_GPD_MFP0_PD1MFP_I2C2_SCL}, + {PD_5, I2C_1, SYS_GPD_MFP1_PD5MFP_I2C1_SCL}, + {PD_7, I2C_0, SYS_GPD_MFP1_PD7MFP_I2C0_SCL}, + {PD_9, I2C_2, SYS_GPD_MFP2_PD9MFP_I2C2_SCL}, + {PE_1, I2C_1, SYS_GPE_MFP0_PE1MFP_I2C1_SCL}, + {PE_13, I2C_0, SYS_GPE_MFP3_PE13MFP_I2C0_SCL}, + {PF_0, I2C_0, SYS_GPF_MFP0_PF0MFP_I2C0_SCL}, + {NU_PINNAME_BIND(PF_0, I2C_0), I2C_0, SYS_GPF_MFP0_PF0MFP_I2C0_SCL}, + {PF_0, I2C_1, SYS_GPF_MFP0_PF0MFP_I2C1_SCL}, + {NU_PINNAME_BIND(PF_0, I2C_1), I2C_1, SYS_GPF_MFP0_PF0MFP_I2C1_SCL}, + {PF_3, I2C_0, SYS_GPF_MFP0_PF3MFP_I2C0_SCL}, + {PF_5, I2C_4, SYS_GPF_MFP1_PF5MFP_I2C4_SCL}, + {PG_0, I2C_0, SYS_GPG_MFP0_PG0MFP_I2C0_SCL}, + {NU_PINNAME_BIND(PG_0, I2C_0), I2C_0, SYS_GPG_MFP0_PG0MFP_I2C0_SCL}, + {PG_0, I2C_3, SYS_GPG_MFP0_PG0MFP_I2C3_SCL}, + {NU_PINNAME_BIND(PG_0, I2C_3), I2C_3, SYS_GPG_MFP0_PG0MFP_I2C3_SCL}, + {PG_2, I2C_1, SYS_GPG_MFP0_PG2MFP_I2C1_SCL}, + {PG_7, I2C_3, SYS_GPG_MFP1_PG7MFP_I2C3_SCL}, + {PG_9, I2C_4, SYS_GPG_MFP2_PG9MFP_I2C4_SCL}, + {PH_2, I2C_0, SYS_GPH_MFP0_PH2MFP_I2C0_SCL}, + {PH_8, I2C_2, SYS_GPH_MFP2_PH8MFP_I2C2_SCL}, + {PI_6, I2C_1, SYS_GPI_MFP1_PI6MFP_I2C1_SCL}, + {PI_10, I2C_0, SYS_GPI_MFP2_PI10MFP_I2C0_SCL}, + {PI_14, I2C_3, SYS_GPI_MFP3_PI14MFP_I2C3_SCL}, + {PJ_10, I2C_4, SYS_GPJ_MFP2_PJ10MFP_I2C4_SCL}, + + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {PA_0, PWM_0_5, SYS_GPA_MFP0_PA0MFP_EPWM0_CH5}, + {PA_1, PWM_0_4, SYS_GPA_MFP0_PA1MFP_EPWM0_CH4}, + {PA_2, PWM_0_3, SYS_GPA_MFP0_PA2MFP_EPWM0_CH3}, + {PA_3, PWM_0_2, SYS_GPA_MFP0_PA3MFP_EPWM0_CH2}, + {PA_4, PWM_0_1, SYS_GPA_MFP1_PA4MFP_EPWM0_CH1}, + {PA_5, PWM_0_0, SYS_GPA_MFP1_PA5MFP_EPWM0_CH0}, + {PA_6, PWM_1_5, SYS_GPA_MFP1_PA6MFP_EPWM1_CH5}, + {PA_7, PWM_1_4, SYS_GPA_MFP1_PA7MFP_EPWM1_CH4}, + {PB_0, PWM_0_5, SYS_GPB_MFP0_PB0MFP_EPWM0_CH5}, + {NU_PINNAME_BIND(PB_0, PWM_0_5), PWM_0_5, SYS_GPB_MFP0_PB0MFP_EPWM0_CH5}, + {PB_0, PWM_1_5, SYS_GPB_MFP0_PB0MFP_EPWM1_CH5}, + {NU_PINNAME_BIND(PB_0, PWM_1_5), PWM_1_5, SYS_GPB_MFP0_PB0MFP_EPWM1_CH5}, + {PB_1, PWM_0_4, SYS_GPB_MFP0_PB1MFP_EPWM0_CH4}, + {NU_PINNAME_BIND(PB_1, PWM_0_4), PWM_0_4, SYS_GPB_MFP0_PB1MFP_EPWM0_CH4}, + {PB_1, PWM_1_4, SYS_GPB_MFP0_PB1MFP_EPWM1_CH4}, + {NU_PINNAME_BIND(PB_1, PWM_1_4), PWM_1_4, SYS_GPB_MFP0_PB1MFP_EPWM1_CH4}, + {PB_2, PWM_0_3, SYS_GPB_MFP0_PB2MFP_EPWM0_CH3}, + {PB_3, PWM_0_2, SYS_GPB_MFP0_PB3MFP_EPWM0_CH2}, + {PB_4, PWM_0_1, SYS_GPB_MFP1_PB4MFP_EPWM0_CH1}, + {PB_5, PWM_0_0, SYS_GPB_MFP1_PB5MFP_EPWM0_CH0}, + {PB_6, PWM_1_5, SYS_GPB_MFP1_PB6MFP_EPWM1_CH5}, + {PB_7, PWM_1_4, SYS_GPB_MFP1_PB7MFP_EPWM1_CH4}, + {PB_12, PWM_1_3, SYS_GPB_MFP3_PB12MFP_EPWM1_CH3}, + {PB_13, PWM_1_2, SYS_GPB_MFP3_PB13MFP_EPWM1_CH2}, + {PB_14, PWM_1_1, SYS_GPB_MFP3_PB14MFP_EPWM1_CH1}, + {PB_15, PWM_1_0, SYS_GPB_MFP3_PB15MFP_EPWM1_CH0}, + {PC_0, PWM_1_5, SYS_GPC_MFP0_PC0MFP_EPWM1_CH5}, + {PC_1, PWM_1_4, SYS_GPC_MFP0_PC1MFP_EPWM1_CH4}, + {PC_2, PWM_1_3, SYS_GPC_MFP0_PC2MFP_EPWM1_CH3}, + {PC_3, PWM_1_2, SYS_GPC_MFP0_PC3MFP_EPWM1_CH2}, + {PC_4, PWM_1_1, SYS_GPC_MFP1_PC4MFP_EPWM1_CH1}, + {PC_5, PWM_1_0, SYS_GPC_MFP1_PC5MFP_EPWM1_CH0}, + {PC_6, PWM_1_3, SYS_GPC_MFP1_PC6MFP_EPWM1_CH3}, + {PC_7, PWM_1_2, SYS_GPC_MFP1_PC7MFP_EPWM1_CH2}, + {PC_8, PWM_1_1, SYS_GPC_MFP2_PC8MFP_EPWM1_CH1}, + {PC_9, PWM_1_3, SYS_GPC_MFP2_PC9MFP_EPWM1_CH3}, + {PC_10, PWM_1_2, SYS_GPC_MFP2_PC10MFP_EPWM1_CH2}, + {PC_11, PWM_1_1, SYS_GPC_MFP2_PC11MFP_EPWM1_CH1}, + {PC_12, PWM_1_0, SYS_GPC_MFP3_PC12MFP_EPWM1_CH0}, + {PD_14, PWM_0_4, SYS_GPD_MFP3_PD14MFP_EPWM0_CH4}, + {PE_2, PWM_0_5, SYS_GPE_MFP0_PE2MFP_EPWM0_CH5}, + {PE_3, PWM_0_4, SYS_GPE_MFP0_PE3MFP_EPWM0_CH4}, + {PE_4, PWM_0_3, SYS_GPE_MFP1_PE4MFP_EPWM0_CH3}, + {PE_5, PWM_0_2, SYS_GPE_MFP1_PE5MFP_EPWM0_CH2}, + {PE_6, PWM_0_1, SYS_GPE_MFP1_PE6MFP_EPWM0_CH1}, + {PE_7, PWM_0_0, SYS_GPE_MFP1_PE7MFP_EPWM0_CH0}, + {PE_8, PWM_0_0, SYS_GPE_MFP2_PE8MFP_EPWM0_CH0}, + {PE_9, PWM_0_1, SYS_GPE_MFP2_PE9MFP_EPWM0_CH1}, + {PE_10, PWM_0_2, SYS_GPE_MFP2_PE10MFP_EPWM0_CH2}, + {PE_11, PWM_0_3, SYS_GPE_MFP2_PE11MFP_EPWM0_CH3}, + {PE_12, PWM_0_4, SYS_GPE_MFP3_PE12MFP_EPWM0_CH4}, + {PE_13, PWM_0_5, SYS_GPE_MFP3_PE13MFP_EPWM0_CH5}, + {NU_PINNAME_BIND(PE_13, PWM_0_5), PWM_0_5, SYS_GPE_MFP3_PE13MFP_EPWM0_CH5}, + {PE_13, PWM_1_0, SYS_GPE_MFP3_PE13MFP_EPWM1_CH0}, + {NU_PINNAME_BIND(PE_13, PWM_1_0), PWM_1_0, SYS_GPE_MFP3_PE13MFP_EPWM1_CH0}, + {PF_0, PWM_1_4, SYS_GPF_MFP0_PF0MFP_EPWM1_CH4}, + {PF_1, PWM_1_5, SYS_GPF_MFP0_PF1MFP_EPWM1_CH5}, + {PF_4, PWM_0_1, SYS_GPF_MFP1_PF4MFP_EPWM0_CH1}, + {PF_5, PWM_0_0, SYS_GPF_MFP1_PF5MFP_EPWM0_CH0}, + {PG_5, PWM_0_3, SYS_GPG_MFP1_PG5MFP_EPWM0_CH3}, + {PG_6, PWM_0_2, SYS_GPG_MFP1_PG6MFP_EPWM0_CH2}, + {PG_7, PWM_0_1, SYS_GPG_MFP1_PG7MFP_EPWM0_CH1}, + {PG_8, PWM_0_0, SYS_GPG_MFP2_PG8MFP_EPWM0_CH0}, + {PH_11, PWM_0_5, SYS_GPH_MFP2_PH11MFP_EPWM0_CH5}, + {PI_12, PWM_1_0, SYS_GPI_MFP3_PI12MFP_EPWM1_CH0}, + {PI_13, PWM_1_1, SYS_GPI_MFP3_PI13MFP_EPWM1_CH1}, + {PI_14, PWM_1_2, SYS_GPI_MFP3_PI14MFP_EPWM1_CH2}, + {PI_15, PWM_1_3, SYS_GPI_MFP3_PI15MFP_EPWM1_CH3}, + {PJ_0, PWM_1_4, SYS_GPJ_MFP0_PJ0MFP_EPWM1_CH4}, + {PJ_1, PWM_1_5, SYS_GPJ_MFP0_PJ1MFP_EPWM1_CH5}, + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_1, UART_0, SYS_GPA_MFP0_PA1MFP_UART0_TXD}, + {PA_3, UART_1, SYS_GPA_MFP0_PA3MFP_UART1_TXD}, + {NU_PINNAME_BIND(PA_3, UART_1), UART_1, SYS_GPA_MFP0_PA3MFP_UART1_TXD}, + {PA_3, UART_4, SYS_GPA_MFP0_PA3MFP_UART4_TXD}, + {NU_PINNAME_BIND(PA_3, UART_4), UART_4, SYS_GPA_MFP0_PA3MFP_UART4_TXD}, +#if COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467 + /* Swap the sequence to pass FPGA CI Test Shield tests */ + {PA_5, UART_5, SYS_GPA_MFP1_PA5MFP_UART5_TXD}, + {NU_PINNAME_BIND(PA_5, UART_5), UART_5, SYS_GPA_MFP1_PA5MFP_UART5_TXD}, + {PA_5, UART_0, SYS_GPA_MFP1_PA5MFP_UART0_TXD}, + {NU_PINNAME_BIND(PA_5, UART_0), UART_0, SYS_GPA_MFP1_PA5MFP_UART0_TXD}, +#else + {PA_5, UART_0, SYS_GPA_MFP1_PA5MFP_UART0_TXD}, + {NU_PINNAME_BIND(PA_5, UART_0), UART_0, SYS_GPA_MFP1_PA5MFP_UART0_TXD}, + {PA_5, UART_5, SYS_GPA_MFP1_PA5MFP_UART5_TXD}, + {NU_PINNAME_BIND(PA_5, UART_5), UART_5, SYS_GPA_MFP1_PA5MFP_UART5_TXD}, +#endif + {PA_7, UART_0, SYS_GPA_MFP1_PA7MFP_UART0_TXD}, + {PA_9, UART_1, SYS_GPA_MFP2_PA9MFP_UART1_TXD}, + {NU_PINNAME_BIND(PA_9, UART_1), UART_1, SYS_GPA_MFP2_PA9MFP_UART1_TXD}, + {PA_9, UART_7, SYS_GPA_MFP2_PA9MFP_UART7_TXD}, + {NU_PINNAME_BIND(PA_9, UART_7), UART_7, SYS_GPA_MFP2_PA9MFP_UART7_TXD}, + {PA_11, UART_6, SYS_GPA_MFP2_PA11MFP_UART6_TXD}, + {PA_12, UART_4, SYS_GPA_MFP3_PA12MFP_UART4_TXD}, + {PA_14, UART_0, SYS_GPA_MFP3_PA14MFP_UART0_TXD}, + {PB_1, UART_2, SYS_GPB_MFP0_PB1MFP_UART2_TXD}, + {PB_3, UART_1, SYS_GPB_MFP0_PB3MFP_UART1_TXD}, +#if COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467 + /* Swap the sequence to pass FPGA CI Test Shield tests */ + {PB_5, UART_5, SYS_GPB_MFP1_PB5MFP_UART5_TXD}, + {NU_PINNAME_BIND(PB_5, UART_5), UART_5, SYS_GPB_MFP1_PB5MFP_UART5_TXD}, + {PB_5, UART_2, SYS_GPB_MFP1_PB5MFP_UART2_TXD}, + {NU_PINNAME_BIND(PB_5, UART_2), UART_2, SYS_GPB_MFP1_PB5MFP_UART2_TXD}, +#else + {PB_5, UART_2, SYS_GPB_MFP1_PB5MFP_UART2_TXD}, + {NU_PINNAME_BIND(PB_5, UART_2), UART_2, SYS_GPB_MFP1_PB5MFP_UART2_TXD}, + {PB_5, UART_5, SYS_GPB_MFP1_PB5MFP_UART5_TXD}, + {NU_PINNAME_BIND(PB_5, UART_5), UART_5, SYS_GPB_MFP1_PB5MFP_UART5_TXD}, +#endif + {PB_7, UART_1, SYS_GPB_MFP1_PB7MFP_UART1_TXD}, + {PB_9, UART_0, SYS_GPB_MFP2_PB9MFP_UART0_TXD}, + {NU_PINNAME_BIND(PB_9, UART_0), UART_0, SYS_GPB_MFP2_PB9MFP_UART0_TXD}, + {PB_9, UART_7, SYS_GPB_MFP2_PB9MFP_UART7_TXD}, + {NU_PINNAME_BIND(PB_9, UART_7), UART_7, SYS_GPB_MFP2_PB9MFP_UART7_TXD}, + {PB_11, UART_4, SYS_GPB_MFP2_PB11MFP_UART4_TXD}, + {PB_13, UART_0, SYS_GPB_MFP3_PB13MFP_UART0_TXD}, + {PB_15, UART_3, SYS_GPB_MFP3_PB15MFP_UART3_TXD}, + {PC_1, UART_2, SYS_GPC_MFP0_PC1MFP_UART2_TXD}, + {PC_3, UART_3, SYS_GPC_MFP0_PC3MFP_UART3_TXD}, + {PC_5, UART_2, SYS_GPC_MFP1_PC5MFP_UART2_TXD}, + {NU_PINNAME_BIND(PC_5, UART_2), UART_2, SYS_GPC_MFP1_PC5MFP_UART2_TXD}, + {PC_5, UART_4, SYS_GPC_MFP1_PC5MFP_UART4_TXD}, + {NU_PINNAME_BIND(PC_5, UART_4), UART_4, SYS_GPC_MFP1_PC5MFP_UART4_TXD}, + {PC_7, UART_4, SYS_GPC_MFP1_PC7MFP_UART4_TXD}, + {NU_PINNAME_BIND(PC_7, UART_4), UART_4, SYS_GPC_MFP1_PC7MFP_UART4_TXD}, + {PC_7, UART_6, SYS_GPC_MFP1_PC7MFP_UART6_TXD}, + {NU_PINNAME_BIND(PC_7, UART_6), UART_6, SYS_GPC_MFP1_PC7MFP_UART6_TXD}, + {PC_10, UART_3, SYS_GPC_MFP2_PC10MFP_UART3_TXD}, +#if COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467 + /* Swap the sequence to pass FPGA CI Test Shield tests */ + {PC_12, UART_6, SYS_GPC_MFP3_PC12MFP_UART6_TXD}, + {NU_PINNAME_BIND(PC_12, UART_6), UART_6, SYS_GPC_MFP3_PC12MFP_UART6_TXD}, + {PC_12, UART_0, SYS_GPC_MFP3_PC12MFP_UART0_TXD}, + {NU_PINNAME_BIND(PC_12, UART_0), UART_0, SYS_GPC_MFP3_PC12MFP_UART0_TXD}, +#else + {PC_12, UART_0, SYS_GPC_MFP3_PC12MFP_UART0_TXD}, + {NU_PINNAME_BIND(PC_12, UART_0), UART_0, SYS_GPC_MFP3_PC12MFP_UART0_TXD}, + {PC_12, UART_6, SYS_GPC_MFP3_PC12MFP_UART6_TXD}, + {NU_PINNAME_BIND(PC_12, UART_6), UART_6, SYS_GPC_MFP3_PC12MFP_UART6_TXD}, +#endif + {PC_13, UART_2, SYS_GPC_MFP3_PC13MFP_UART2_TXD}, + {PD_1, UART_3, SYS_GPD_MFP0_PD1MFP_UART3_TXD}, + {PD_3, UART_0, SYS_GPD_MFP0_PD3MFP_UART0_TXD}, + {PD_7, UART_1, SYS_GPD_MFP1_PD7MFP_UART1_TXD}, + {PD_9, UART_7, SYS_GPD_MFP2_PD9MFP_UART7_TXD}, + {PD_11, UART_1, SYS_GPD_MFP2_PD11MFP_UART1_TXD}, + {NU_PINNAME_BIND(PD_11, UART_1), UART_1, SYS_GPD_MFP2_PD11MFP_UART1_TXD}, + {PD_11, UART_8, SYS_GPD_MFP2_PD11MFP_UART8_TXD}, + {NU_PINNAME_BIND(PD_11, UART_8), UART_8, SYS_GPD_MFP2_PD11MFP_UART8_TXD}, + {PE_1, UART_3, SYS_GPE_MFP0_PE1MFP_UART3_TXD}, + {NU_PINNAME_BIND(PE_1, UART_3), UART_3, SYS_GPE_MFP0_PE1MFP_UART3_TXD}, + {PE_1, UART_8, SYS_GPE_MFP0_PE1MFP_UART8_TXD}, + {NU_PINNAME_BIND(PE_1, UART_8), UART_8, SYS_GPE_MFP0_PE1MFP_UART8_TXD}, + {PE_3, UART_7, SYS_GPE_MFP0_PE3MFP_UART7_TXD}, + {PE_5, UART_6, SYS_GPE_MFP1_PE5MFP_UART6_TXD}, + {NU_PINNAME_BIND(PE_5, UART_6), UART_6, SYS_GPE_MFP1_PE5MFP_UART6_TXD}, + {PE_5, UART_9, SYS_GPE_MFP1_PE5MFP_UART9_TXD}, + {NU_PINNAME_BIND(PE_5, UART_9), UART_9, SYS_GPE_MFP1_PE5MFP_UART9_TXD}, + {PE_7, UART_5, SYS_GPE_MFP1_PE7MFP_UART5_TXD}, + {PE_8, UART_2, SYS_GPE_MFP2_PE8MFP_UART2_TXD}, + {PE_10, UART_3, SYS_GPE_MFP2_PE10MFP_UART3_TXD}, + {PE_13, UART_1, SYS_GPE_MFP3_PE13MFP_UART1_TXD}, + {PE_14, UART_2, SYS_GPE_MFP3_PE14MFP_UART2_TXD}, + {NU_PINNAME_BIND(PE_14, UART_2), UART_2, SYS_GPE_MFP3_PE14MFP_UART2_TXD}, + {PE_14, UART_6, SYS_GPE_MFP3_PE14MFP_UART6_TXD}, + {NU_PINNAME_BIND(PE_14, UART_6), UART_6, SYS_GPE_MFP3_PE14MFP_UART6_TXD}, + {PF_0, UART_0, SYS_GPF_MFP0_PF0MFP_UART0_TXD}, + {NU_PINNAME_BIND(PF_0, UART_0), UART_0, SYS_GPF_MFP0_PF0MFP_UART0_TXD}, + {PF_0, UART_1, SYS_GPF_MFP0_PF0MFP_UART1_TXD}, + {NU_PINNAME_BIND(PF_0, UART_1), UART_1, SYS_GPF_MFP0_PF0MFP_UART1_TXD}, + {PF_0, UART_2, SYS_GPF_MFP0_PF0MFP_UART2_TXD}, + {NU_PINNAME_BIND(PF_0, UART_2), UART_2, SYS_GPF_MFP0_PF0MFP_UART2_TXD}, + {PF_3, UART_0, SYS_GPF_MFP0_PF3MFP_UART0_TXD}, + {NU_PINNAME_BIND(PF_3, UART_0), UART_0, SYS_GPF_MFP0_PF3MFP_UART0_TXD}, + {PF_3, UART_9, SYS_GPF_MFP0_PF3MFP_UART9_TXD}, + {NU_PINNAME_BIND(PF_3, UART_9), UART_9, SYS_GPF_MFP0_PF3MFP_UART9_TXD}, + {PF_4, UART_2, SYS_GPF_MFP1_PF4MFP_UART2_TXD}, + {PF_7, UART_4, SYS_GPF_MFP1_PF7MFP_UART4_TXD}, + {PF_9, UART_9, SYS_GPF_MFP2_PF9MFP_UART9_TXD}, + {PF_11, UART_5, SYS_GPF_MFP2_PF11MFP_UART5_TXD}, + {PG_0, UART_1, SYS_GPG_MFP0_PG0MFP_UART1_TXD}, + {PG_1, UART_2, SYS_GPG_MFP0_PG1MFP_UART2_TXD}, + {PG_11, UART_7, SYS_GPG_MFP2_PG11MFP_UART7_TXD}, + {PG_13, UART_6, SYS_GPG_MFP3_PG13MFP_UART6_TXD}, + {PH_0, UART_5, SYS_GPH_MFP0_PH0MFP_UART5_TXD}, + {PH_2, UART_4, SYS_GPH_MFP0_PH2MFP_UART4_TXD}, + {PH_4, UART_6, SYS_GPH_MFP1_PH4MFP_UART6_TXD}, + {PH_6, UART_7, SYS_GPH_MFP1_PH6MFP_UART7_TXD}, + {PH_8, UART_1, SYS_GPH_MFP2_PH8MFP_UART1_TXD}, + {PH_10, UART_0, SYS_GPH_MFP2_PH10MFP_UART0_TXD}, + {NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFP2_PH10MFP_UART0_TXD}, + {PH_10, UART_4, SYS_GPH_MFP2_PH10MFP_UART4_TXD}, + {NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFP2_PH10MFP_UART4_TXD}, + {PH_10, UART_9, SYS_GPH_MFP2_PH10MFP_UART9_TXD}, + {NU_PINNAME_BIND(PH_10, UART_9), UART_9, SYS_GPH_MFP2_PH10MFP_UART9_TXD}, + {PH_12, UART_9, SYS_GPH_MFP3_PH12MFP_UART9_TXD}, + {PI_6, UART_2, SYS_GPI_MFP1_PI6MFP_UART2_TXD}, + {PI_10, UART_2, SYS_GPI_MFP2_PI10MFP_UART2_TXD}, + {PI_12, UART_4, SYS_GPI_MFP3_PI12MFP_UART4_TXD}, + {PI_14, UART_3, SYS_GPI_MFP3_PI14MFP_UART3_TXD}, + {PJ_0, UART_8, SYS_GPJ_MFP0_PJ0MFP_UART8_TXD}, + {PJ_4, UART_8, SYS_GPJ_MFP1_PJ4MFP_UART8_TXD}, + {PJ_8, UART_7, SYS_GPJ_MFP2_PJ8MFP_UART7_TXD}, + {PJ_10, UART_6, SYS_GPJ_MFP2_PJ10MFP_UART6_TXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_0, UART_0, SYS_GPA_MFP0_PA0MFP_UART0_RXD}, + {PA_2, UART_1, SYS_GPA_MFP0_PA2MFP_UART1_RXD}, + {NU_PINNAME_BIND(PA_2, UART_1), UART_1, SYS_GPA_MFP0_PA2MFP_UART1_RXD}, + {PA_2, UART_4, SYS_GPA_MFP0_PA2MFP_UART4_RXD}, + {NU_PINNAME_BIND(PA_2, UART_4), UART_4, SYS_GPA_MFP0_PA2MFP_UART4_RXD}, +#if COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467 + /* Swap the sequence to pass FPGA CI Test Shield tests */ + {PA_4, UART_5, SYS_GPA_MFP1_PA4MFP_UART5_RXD}, + {NU_PINNAME_BIND(PA_4, UART_5), UART_5, SYS_GPA_MFP1_PA4MFP_UART5_RXD}, + {PA_4, UART_0, SYS_GPA_MFP1_PA4MFP_UART0_RXD}, + {NU_PINNAME_BIND(PA_4, UART_0), UART_0, SYS_GPA_MFP1_PA4MFP_UART0_RXD}, +#else + {PA_4, UART_0, SYS_GPA_MFP1_PA4MFP_UART0_RXD}, + {NU_PINNAME_BIND(PA_4, UART_0), UART_0, SYS_GPA_MFP1_PA4MFP_UART0_RXD}, + {PA_4, UART_5, SYS_GPA_MFP1_PA4MFP_UART5_RXD}, + {NU_PINNAME_BIND(PA_4, UART_5), UART_5, SYS_GPA_MFP1_PA4MFP_UART5_RXD}, +#endif + {PA_6, UART_0, SYS_GPA_MFP1_PA6MFP_UART0_RXD}, + {PA_8, UART_1, SYS_GPA_MFP2_PA8MFP_UART1_RXD}, + {NU_PINNAME_BIND(PA_8, UART_1), UART_1, SYS_GPA_MFP2_PA8MFP_UART1_RXD}, + {PA_8, UART_7, SYS_GPA_MFP2_PA8MFP_UART7_RXD}, + {NU_PINNAME_BIND(PA_8, UART_7), UART_7, SYS_GPA_MFP2_PA8MFP_UART7_RXD}, + {PA_10, UART_6, SYS_GPA_MFP2_PA10MFP_UART6_RXD}, + {PA_13, UART_4, SYS_GPA_MFP3_PA13MFP_UART4_RXD}, + {PA_15, UART_0, SYS_GPA_MFP3_PA15MFP_UART0_RXD}, + {PB_0, UART_2, SYS_GPB_MFP0_PB0MFP_UART2_RXD}, + {PB_2, UART_1, SYS_GPB_MFP0_PB2MFP_UART1_RXD}, +#if COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467 + /* Swap the sequence to pass FPGA CI Test Shield tests */ + {PB_4, UART_5, SYS_GPB_MFP1_PB4MFP_UART5_RXD}, + {NU_PINNAME_BIND(PB_4, UART_5), UART_5, SYS_GPB_MFP1_PB4MFP_UART5_RXD}, + {PB_4, UART_2, SYS_GPB_MFP1_PB4MFP_UART2_RXD}, + {NU_PINNAME_BIND(PB_4, UART_2), UART_2, SYS_GPB_MFP1_PB4MFP_UART2_RXD}, +#else + {PB_4, UART_2, SYS_GPB_MFP1_PB4MFP_UART2_RXD}, + {NU_PINNAME_BIND(PB_4, UART_2), UART_2, SYS_GPB_MFP1_PB4MFP_UART2_RXD}, + {PB_4, UART_5, SYS_GPB_MFP1_PB4MFP_UART5_RXD}, + {NU_PINNAME_BIND(PB_4, UART_5), UART_5, SYS_GPB_MFP1_PB4MFP_UART5_RXD}, +#endif + {PB_6, UART_1, SYS_GPB_MFP1_PB6MFP_UART1_RXD}, + {PB_8, UART_0, SYS_GPB_MFP2_PB8MFP_UART0_RXD}, + {NU_PINNAME_BIND(PB_8, UART_0), UART_0, SYS_GPB_MFP2_PB8MFP_UART0_RXD}, + {PB_8, UART_7, SYS_GPB_MFP2_PB8MFP_UART7_RXD}, + {NU_PINNAME_BIND(PB_8, UART_7), UART_7, SYS_GPB_MFP2_PB8MFP_UART7_RXD}, + {PB_10, UART_4, SYS_GPB_MFP2_PB10MFP_UART4_RXD}, + {PB_12, UART_0, SYS_GPB_MFP3_PB12MFP_UART0_RXD}, + {PB_14, UART_3, SYS_GPB_MFP3_PB14MFP_UART3_RXD}, + {PC_0, UART_2, SYS_GPC_MFP0_PC0MFP_UART2_RXD}, + {PC_2, UART_3, SYS_GPC_MFP0_PC2MFP_UART3_RXD}, + {PC_4, UART_2, SYS_GPC_MFP1_PC4MFP_UART2_RXD}, + {NU_PINNAME_BIND(PC_4, UART_2), UART_2, SYS_GPC_MFP1_PC4MFP_UART2_RXD}, + {PC_4, UART_4, SYS_GPC_MFP1_PC4MFP_UART4_RXD}, + {NU_PINNAME_BIND(PC_4, UART_4), UART_4, SYS_GPC_MFP1_PC4MFP_UART4_RXD}, + {PC_6, UART_4, SYS_GPC_MFP1_PC6MFP_UART4_RXD}, + {NU_PINNAME_BIND(PC_6, UART_4), UART_4, SYS_GPC_MFP1_PC6MFP_UART4_RXD}, + {PC_6, UART_6, SYS_GPC_MFP1_PC6MFP_UART6_RXD}, + {NU_PINNAME_BIND(PC_6, UART_6), UART_6, SYS_GPC_MFP1_PC6MFP_UART6_RXD}, + {PC_8, UART_1, SYS_GPC_MFP2_PC8MFP_UART1_RXD}, + {PC_9, UART_3, SYS_GPC_MFP2_PC9MFP_UART3_RXD}, +#if COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467 + /* Swap the sequence to pass FPGA CI Test Shield tests */ + {PC_11, UART_6, SYS_GPC_MFP2_PC11MFP_UART6_RXD}, + {NU_PINNAME_BIND(PC_11, UART_6), UART_6, SYS_GPC_MFP2_PC11MFP_UART6_RXD}, + {PC_11, UART_0, SYS_GPC_MFP2_PC11MFP_UART0_RXD}, + {NU_PINNAME_BIND(PC_11, UART_0), UART_0, SYS_GPC_MFP2_PC11MFP_UART0_RXD}, +#else + {PC_11, UART_0, SYS_GPC_MFP2_PC11MFP_UART0_RXD}, + {NU_PINNAME_BIND(PC_11, UART_0), UART_0, SYS_GPC_MFP2_PC11MFP_UART0_RXD}, + {PC_11, UART_6, SYS_GPC_MFP2_PC11MFP_UART6_RXD}, + {NU_PINNAME_BIND(PC_11, UART_6), UART_6, SYS_GPC_MFP2_PC11MFP_UART6_RXD}, +#endif + {PD_0, UART_3, SYS_GPD_MFP0_PD0MFP_UART3_RXD}, + {PD_2, UART_0, SYS_GPD_MFP0_PD2MFP_UART0_RXD}, + {PD_6, UART_1, SYS_GPD_MFP1_PD6MFP_UART1_RXD}, + {PD_8, UART_7, SYS_GPD_MFP2_PD8MFP_UART7_RXD}, + {PD_10, UART_1, SYS_GPD_MFP2_PD10MFP_UART1_RXD}, + {NU_PINNAME_BIND(PD_10, UART_1), UART_1, SYS_GPD_MFP2_PD10MFP_UART1_RXD}, + {PD_10, UART_8, SYS_GPD_MFP2_PD10MFP_UART8_RXD}, + {NU_PINNAME_BIND(PD_10, UART_8), UART_8, SYS_GPD_MFP2_PD10MFP_UART8_RXD}, + {PD_12, UART_2, SYS_GPD_MFP3_PD12MFP_UART2_RXD}, + {PD_13, UART_6, SYS_GPD_MFP3_PD13MFP_UART6_RXD}, + {PE_0, UART_3, SYS_GPE_MFP0_PE0MFP_UART3_RXD}, + {NU_PINNAME_BIND(PE_0, UART_3), UART_3, SYS_GPE_MFP0_PE0MFP_UART3_RXD}, + {PE_0, UART_8, SYS_GPE_MFP0_PE0MFP_UART8_RXD}, + {NU_PINNAME_BIND(PE_0, UART_8), UART_8, SYS_GPE_MFP0_PE0MFP_UART8_RXD}, + {PE_2, UART_7, SYS_GPE_MFP0_PE2MFP_UART7_RXD}, + {PE_4, UART_6, SYS_GPE_MFP1_PE4MFP_UART6_RXD}, + {NU_PINNAME_BIND(PE_4, UART_6), UART_6, SYS_GPE_MFP1_PE4MFP_UART6_RXD}, + {PE_4, UART_9, SYS_GPE_MFP1_PE4MFP_UART9_RXD}, + {NU_PINNAME_BIND(PE_4, UART_9), UART_9, SYS_GPE_MFP1_PE4MFP_UART9_RXD}, + {PE_6, UART_5, SYS_GPE_MFP1_PE6MFP_UART5_RXD}, + {PE_9, UART_2, SYS_GPE_MFP2_PE9MFP_UART2_RXD}, + {PE_11, UART_3, SYS_GPE_MFP2_PE11MFP_UART3_RXD}, + {PE_15, UART_2, SYS_GPE_MFP3_PE15MFP_UART2_RXD}, + {NU_PINNAME_BIND(PE_15, UART_2), UART_2, SYS_GPE_MFP3_PE15MFP_UART2_RXD}, + {PE_15, UART_6, SYS_GPE_MFP3_PE15MFP_UART6_RXD}, + {NU_PINNAME_BIND(PE_15, UART_6), UART_6, SYS_GPE_MFP3_PE15MFP_UART6_RXD}, + {PF_1, UART_0, SYS_GPF_MFP0_PF1MFP_UART0_RXD}, + {NU_PINNAME_BIND(PF_1, UART_0), UART_0, SYS_GPF_MFP0_PF1MFP_UART0_RXD}, + {PF_1, UART_1, SYS_GPF_MFP0_PF1MFP_UART1_RXD}, + {NU_PINNAME_BIND(PF_1, UART_1), UART_1, SYS_GPF_MFP0_PF1MFP_UART1_RXD}, + {PF_1, UART_2, SYS_GPF_MFP0_PF1MFP_UART2_RXD}, + {NU_PINNAME_BIND(PF_1, UART_2), UART_2, SYS_GPF_MFP0_PF1MFP_UART2_RXD}, + {PF_2, UART_0, SYS_GPF_MFP0_PF2MFP_UART0_RXD}, + {NU_PINNAME_BIND(PF_2, UART_0), UART_0, SYS_GPF_MFP0_PF2MFP_UART0_RXD}, + {PF_2, UART_9, SYS_GPF_MFP0_PF2MFP_UART9_RXD}, + {NU_PINNAME_BIND(PF_2, UART_9), UART_9, SYS_GPF_MFP0_PF2MFP_UART9_RXD}, + {PF_5, UART_2, SYS_GPF_MFP1_PF5MFP_UART2_RXD}, + {PF_6, UART_4, SYS_GPF_MFP1_PF6MFP_UART4_RXD}, + {PF_8, UART_9, SYS_GPF_MFP2_PF8MFP_UART9_RXD}, + {PF_10, UART_5, SYS_GPF_MFP2_PF10MFP_UART5_RXD}, + {PG_0, UART_2, SYS_GPG_MFP0_PG0MFP_UART2_RXD}, + {PG_1, UART_1, SYS_GPG_MFP0_PG1MFP_UART1_RXD}, + {PG_12, UART_7, SYS_GPG_MFP3_PG12MFP_UART7_RXD}, + {PG_14, UART_6, SYS_GPG_MFP3_PG14MFP_UART6_RXD}, + {PH_1, UART_5, SYS_GPH_MFP0_PH1MFP_UART5_RXD}, + {PH_3, UART_4, SYS_GPH_MFP0_PH3MFP_UART4_RXD}, + {PH_5, UART_6, SYS_GPH_MFP1_PH5MFP_UART6_RXD}, + {PH_7, UART_7, SYS_GPH_MFP1_PH7MFP_UART7_RXD}, + {PH_9, UART_1, SYS_GPH_MFP2_PH9MFP_UART1_RXD}, + {PH_11, UART_0, SYS_GPH_MFP2_PH11MFP_UART0_RXD}, + {NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFP2_PH11MFP_UART0_RXD}, + {PH_11, UART_4, SYS_GPH_MFP2_PH11MFP_UART4_RXD}, + {NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFP2_PH11MFP_UART4_RXD}, + {PH_11, UART_9, SYS_GPH_MFP2_PH11MFP_UART9_RXD}, + {NU_PINNAME_BIND(PH_11, UART_9), UART_9, SYS_GPH_MFP2_PH11MFP_UART9_RXD}, + {PH_13, UART_9, SYS_GPH_MFP3_PH13MFP_UART9_RXD}, + {PI_7, UART_2, SYS_GPI_MFP1_PI7MFP_UART2_RXD}, + {PI_11, UART_2, SYS_GPI_MFP2_PI11MFP_UART2_RXD}, + {PI_13, UART_4, SYS_GPI_MFP3_PI13MFP_UART4_RXD}, + {PI_15, UART_3, SYS_GPI_MFP3_PI15MFP_UART3_RXD}, + {PJ_1, UART_8, SYS_GPJ_MFP0_PJ1MFP_UART8_RXD}, + {PJ_5, UART_8, SYS_GPJ_MFP1_PJ5MFP_UART8_RXD}, + {PJ_9, UART_7, SYS_GPJ_MFP2_PJ9MFP_UART7_RXD}, + {PJ_11, UART_6, SYS_GPJ_MFP2_PJ11MFP_UART6_RXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_0, UART_1, SYS_GPA_MFP0_PA0MFP_UART1_nRTS}, + {PA_4, UART_0, SYS_GPA_MFP1_PA4MFP_UART0_nRTS}, + {PB_3, UART_5, SYS_GPB_MFP0_PB3MFP_UART5_nRTS}, + {PB_8, UART_1, SYS_GPB_MFP2_PB8MFP_UART1_nRTS}, + {PB_10, UART_0, SYS_GPB_MFP2_PB10MFP_UART0_nRTS}, + {PB_13, UART_3, SYS_GPB_MFP3_PB13MFP_UART3_nRTS}, + {PB_14, UART_0, SYS_GPB_MFP3_PB14MFP_UART0_nRTS}, + {PC_3, UART_2, SYS_GPC_MFP0_PC3MFP_UART2_nRTS}, + {PC_6, UART_0, SYS_GPC_MFP1_PC6MFP_UART0_nRTS}, + {PC_10, UART_6, SYS_GPC_MFP2_PC10MFP_UART6_nRTS}, + {PD_3, UART_3, SYS_GPD_MFP0_PD3MFP_UART3_nRTS}, + {PD_8, UART_2, SYS_GPD_MFP2_PD8MFP_UART2_nRTS}, + {PD_12, UART_8, SYS_GPD_MFP3_PD12MFP_UART8_nRTS}, + {PE_0, UART_4, SYS_GPE_MFP0_PE0MFP_UART4_nRTS}, + {PE_2, UART_8, SYS_GPE_MFP0_PE2MFP_UART8_nRTS}, + {PE_3, UART_6, SYS_GPE_MFP0_PE3MFP_UART6_nRTS}, + {PE_5, UART_7, SYS_GPE_MFP1_PE5MFP_UART7_nRTS}, + {PE_6, UART_9, SYS_GPE_MFP1_PE6MFP_UART9_nRTS}, + {PE_12, UART_1, SYS_GPE_MFP3_PE12MFP_UART1_nRTS}, + {PE_13, UART_4, SYS_GPE_MFP3_PE13MFP_UART4_nRTS}, + {PF_4, UART_2, SYS_GPF_MFP1_PF4MFP_UART2_nRTS}, + {PF_9, UART_5, SYS_GPF_MFP2_PF9MFP_UART5_nRTS}, + {PF_10, UART_9, SYS_GPF_MFP2_PF10MFP_UART9_nRTS}, + {PH_2, UART_5, SYS_GPH_MFP0_PH2MFP_UART5_nRTS}, + {PH_4, UART_7, SYS_GPH_MFP1_PH4MFP_UART7_nRTS}, + {PH_7, UART_9, SYS_GPH_MFP1_PH7MFP_UART9_nRTS}, + {PH_8, UART_3, SYS_GPH_MFP2_PH8MFP_UART3_nRTS}, + {PH_9, UART_9, SYS_GPH_MFP2_PH9MFP_UART9_nRTS}, + {PI_8, UART_2, SYS_GPI_MFP2_PI8MFP_UART2_nRTS}, + {PI_15, UART_8, SYS_GPI_MFP3_PI15MFP_UART8_nRTS}, + {PJ_3, UART_8, SYS_GPJ_MFP0_PJ3MFP_UART8_nRTS}, + {PJ_7, UART_9, SYS_GPJ_MFP1_PJ7MFP_UART9_nRTS}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_1, UART_1, SYS_GPA_MFP0_PA1MFP_UART1_nCTS}, + {PA_5, UART_0, SYS_GPA_MFP1_PA5MFP_UART0_nCTS}, + {PB_2, UART_5, SYS_GPB_MFP0_PB2MFP_UART5_nCTS}, + {PB_9, UART_1, SYS_GPB_MFP2_PB9MFP_UART1_nCTS}, + {PB_11, UART_0, SYS_GPB_MFP2_PB11MFP_UART0_nCTS}, + {PB_12, UART_3, SYS_GPB_MFP3_PB12MFP_UART3_nCTS}, + {PB_15, UART_0, SYS_GPB_MFP3_PB15MFP_UART0_nCTS}, + {PC_2, UART_2, SYS_GPC_MFP0_PC2MFP_UART2_nCTS}, + {PC_7, UART_0, SYS_GPC_MFP1_PC7MFP_UART0_nCTS}, + {PC_8, UART_4, SYS_GPC_MFP2_PC8MFP_UART4_nCTS}, + {PC_9, UART_6, SYS_GPC_MFP2_PC9MFP_UART6_nCTS}, + {PC_13, UART_8, SYS_GPC_MFP3_PC13MFP_UART8_nCTS}, + {PD_2, UART_3, SYS_GPD_MFP0_PD2MFP_UART3_nCTS}, + {PD_9, UART_2, SYS_GPD_MFP2_PD9MFP_UART2_nCTS}, + {PE_1, UART_4, SYS_GPE_MFP0_PE1MFP_UART4_nCTS}, + {PE_2, UART_6, SYS_GPE_MFP0_PE2MFP_UART6_nCTS}, + {PE_3, UART_8, SYS_GPE_MFP0_PE3MFP_UART8_nCTS}, + {PE_4, UART_7, SYS_GPE_MFP1_PE4MFP_UART7_nCTS}, + {PE_7, UART_9, SYS_GPE_MFP1_PE7MFP_UART9_nCTS}, + {PE_11, UART_1, SYS_GPE_MFP2_PE11MFP_UART1_nCTS}, + {PF_5, UART_2, SYS_GPF_MFP1_PF5MFP_UART2_nCTS}, + {PF_8, UART_5, SYS_GPF_MFP2_PF8MFP_UART5_nCTS}, + {PF_11, UART_9, SYS_GPF_MFP2_PF11MFP_UART9_nCTS}, + {PH_3, UART_5, SYS_GPH_MFP0_PH3MFP_UART5_nCTS}, + {PH_5, UART_7, SYS_GPH_MFP1_PH5MFP_UART7_nCTS}, + {PH_6, UART_9, SYS_GPH_MFP1_PH6MFP_UART9_nCTS}, + {PH_8, UART_9, SYS_GPH_MFP2_PH8MFP_UART9_nCTS}, + {PH_9, UART_3, SYS_GPH_MFP2_PH9MFP_UART3_nCTS}, + {PI_9, UART_2, SYS_GPI_MFP2_PI9MFP_UART2_nCTS}, + {PI_14, UART_8, SYS_GPI_MFP3_PI14MFP_UART8_nCTS}, + {PJ_2, UART_8, SYS_GPJ_MFP0_PJ2MFP_UART8_nCTS}, + {PJ_6, UART_9, SYS_GPJ_MFP1_PJ6MFP_UART9_nCTS}, + + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_0, SPI_11, SYS_GPA_MFP0_PA0MFP_QSPI0_MOSI0}, + {NU_PINNAME_BIND(PA_0, SPI_11), SPI_11, SYS_GPA_MFP0_PA0MFP_QSPI0_MOSI0}, + {PA_0, SPI_0, SYS_GPA_MFP0_PA0MFP_SPI0_MOSI}, + {NU_PINNAME_BIND(PA_0, SPI_0), SPI_0, SYS_GPA_MFP0_PA0MFP_SPI0_MOSI}, + {PA_8, SPI_2, SYS_GPA_MFP2_PA8MFP_SPI2_MOSI}, + {PA_13, SPI_12, SYS_GPA_MFP3_PA13MFP_QSPI1_MOSI0}, + {PA_15, SPI_0, SYS_GPA_MFP3_PA15MFP_SPI0_MOSI}, + {NU_PINNAME_BIND(PA_15, SPI_0), SPI_0, SYS_GPA_MFP3_PA15MFP_SPI0_MOSI}, + {PA_15, SPI_2, SYS_GPA_MFP3_PA15MFP_SPI2_MOSI}, + {NU_PINNAME_BIND(PA_15, SPI_2), SPI_2, SYS_GPA_MFP3_PA15MFP_SPI2_MOSI}, + {PA_15, SPI_10, SYS_GPA_MFP3_PA15MFP_SPI10_MOSI}, + {NU_PINNAME_BIND(PA_15, SPI_10), SPI_10, SYS_GPA_MFP3_PA15MFP_SPI10_MOSI}, +#if !(COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467) + /* Address SPI among M460HD/M460LD series + * + * SPI4~SPI10 are available in M460LD series, but not in M460HD series. + * + * For the following reasons, we don't address it except for passing FPGA CI Test Shield tests: + * 1. Avoid scattered conditional + * 2. Enable build for both M460HD/M460LD series using the default target name + */ + {PB_0, SPI_4, SYS_GPB_MFP0_PB0MFP_SPI4_MOSI}, +#endif + {PB_4, SPI_1, SYS_GPB_MFP1_PB4MFP_SPI1_MOSI}, + {PB_6, SPI_3, SYS_GPB_MFP1_PB6MFP_SPI3_MOSI}, + {PB_8, SPI_3, SYS_GPB_MFP2_PB8MFP_SPI3_MOSI}, + {PB_12, SPI_0, SYS_GPB_MFP3_PB12MFP_SPI0_MOSI}, + {PC_0, SPI_11, SYS_GPC_MFP0_PC0MFP_QSPI0_MOSI0}, + {NU_PINNAME_BIND(PC_0, SPI_11), SPI_11, SYS_GPC_MFP0_PC0MFP_QSPI0_MOSI0}, + {PC_0, SPI_7, SYS_GPC_MFP0_PC0MFP_SPI7_MOSI}, + {NU_PINNAME_BIND(PC_0, SPI_7), SPI_7, SYS_GPC_MFP0_PC0MFP_SPI7_MOSI}, + {PC_2, SPI_12, SYS_GPC_MFP0_PC2MFP_QSPI1_MOSI0}, + {NU_PINNAME_BIND(PC_2, SPI_12), SPI_12, SYS_GPC_MFP0_PC2MFP_QSPI1_MOSI0}, + {PC_2, SPI_1, SYS_GPC_MFP0_PC2MFP_SPI1_MOSI}, + {NU_PINNAME_BIND(PC_2, SPI_1), SPI_1, SYS_GPC_MFP0_PC2MFP_SPI1_MOSI}, + {PC_6, SPI_1, SYS_GPC_MFP1_PC6MFP_SPI1_MOSI}, + {NU_PINNAME_BIND(PC_6, SPI_1), SPI_1, SYS_GPC_MFP1_PC6MFP_SPI1_MOSI}, + {PC_6, SPI_6, SYS_GPC_MFP1_PC6MFP_SPI6_MOSI}, + {NU_PINNAME_BIND(PC_6, SPI_6), SPI_6, SYS_GPC_MFP1_PC6MFP_SPI6_MOSI}, + {PC_11, SPI_3, SYS_GPC_MFP2_PC11MFP_SPI3_MOSI}, + {PC_14, SPI_9, SYS_GPC_MFP3_PC14MFP_SPI9_MOSI}, + {PD_0, SPI_0, SYS_GPD_MFP0_PD0MFP_SPI0_MOSI}, + {PD_6, SPI_12, SYS_GPD_MFP1_PD6MFP_QSPI1_MOSI0}, + {NU_PINNAME_BIND(PD_6, SPI_12), SPI_12, SYS_GPD_MFP1_PD6MFP_QSPI1_MOSI0}, + {PD_6, SPI_1, SYS_GPD_MFP1_PD6MFP_SPI1_MOSI}, + {NU_PINNAME_BIND(PD_6, SPI_1), SPI_1, SYS_GPD_MFP1_PD6MFP_SPI1_MOSI}, + {PD_10, SPI_9, SYS_GPD_MFP2_PD10MFP_SPI9_MOSI}, + {PD_13, SPI_12, SYS_GPD_MFP3_PD13MFP_QSPI1_MOSI0}, + {PE_0, SPI_11, SYS_GPE_MFP0_PE0MFP_QSPI0_MOSI0}, + {NU_PINNAME_BIND(PE_0, SPI_11), SPI_11, SYS_GPE_MFP0_PE0MFP_QSPI0_MOSI0}, + {PE_0, SPI_1, SYS_GPE_MFP0_PE0MFP_SPI1_MOSI}, + {NU_PINNAME_BIND(PE_0, SPI_1), SPI_1, SYS_GPE_MFP0_PE0MFP_SPI1_MOSI}, + {PE_2, SPI_3, SYS_GPE_MFP0_PE2MFP_SPI3_MOSI}, + {PE_10, SPI_2, SYS_GPE_MFP2_PE10MFP_SPI2_MOSI}, + {PF_1, SPI_12, SYS_GPF_MFP0_PF1MFP_QSPI1_MOSI0}, + {PF_5, SPI_5, SYS_GPF_MFP1_PF5MFP_SPI5_MOSI}, + {PF_6, SPI_0, SYS_GPF_MFP1_PF6MFP_SPI0_MOSI}, + {PF_11, SPI_2, SYS_GPF_MFP2_PF11MFP_SPI2_MOSI}, + {PG_8, SPI_3, SYS_GPG_MFP2_PG8MFP_SPI3_MOSI}, + {PG_11, SPI_8, SYS_GPG_MFP2_PG11MFP_SPI8_MOSI}, + {PG_14, SPI_12, SYS_GPG_MFP3_PG14MFP_QSPI1_MOSI0}, + {PH_5, SPI_1, SYS_GPH_MFP1_PH5MFP_SPI1_MOSI}, + {PI_8, SPI_1, SYS_GPI_MFP2_PI8MFP_SPI1_MOSI}, + {PJ_1, SPI_11, SYS_GPJ_MFP0_PJ1MFP_QSPI0_MOSI0}, + {PJ_5, SPI_12, SYS_GPJ_MFP1_PJ5MFP_QSPI1_MOSI0}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_1, SPI_11, SYS_GPA_MFP0_PA1MFP_QSPI0_MISO0}, + {NU_PINNAME_BIND(PA_1, SPI_11), SPI_11, SYS_GPA_MFP0_PA1MFP_QSPI0_MISO0}, + {PA_1, SPI_0, SYS_GPA_MFP0_PA1MFP_SPI0_MISO}, + {NU_PINNAME_BIND(PA_1, SPI_0), SPI_0, SYS_GPA_MFP0_PA1MFP_SPI0_MISO}, + {PA_9, SPI_2, SYS_GPA_MFP2_PA9MFP_SPI2_MISO}, + {PA_12, SPI_12, SYS_GPA_MFP3_PA12MFP_QSPI1_MISO0}, + {PA_14, SPI_0, SYS_GPA_MFP3_PA14MFP_SPI0_MISO}, + {NU_PINNAME_BIND(PA_14, SPI_0), SPI_0, SYS_GPA_MFP3_PA14MFP_SPI0_MISO}, + {PA_14, SPI_2, SYS_GPA_MFP3_PA14MFP_SPI2_MISO}, + {NU_PINNAME_BIND(PA_14, SPI_2), SPI_2, SYS_GPA_MFP3_PA14MFP_SPI2_MISO}, + {PA_14, SPI_10, SYS_GPA_MFP3_PA14MFP_SPI10_MISO}, + {NU_PINNAME_BIND(PA_14, SPI_10), SPI_10, SYS_GPA_MFP3_PA14MFP_SPI10_MISO}, + {PB_1, SPI_4, SYS_GPB_MFP0_PB1MFP_SPI4_MISO}, + {PB_5, SPI_1, SYS_GPB_MFP1_PB5MFP_SPI1_MISO}, +#if !(COMPONENT_FPGA_CI_TEST_SHIELD && TARGET_NUMAKER_IOT_M467) + /* Address SPI multi-function pin-out difference among M460HD/M460LD series + * + * For PB.7, SPI3_MISO is available in M460LD series, but not in M460HD series. + * + * For the following reasons, we don't address it except for passing FPGA CI Test Shield tests: + * 1. Avoid scattered conditional + * 2. Enable build for both M460HD/M460LD series using the default target name + */ + {PB_7, SPI_3, SYS_GPB_MFP1_PB7MFP_SPI3_MISO}, +#endif + {PB_9, SPI_3, SYS_GPB_MFP2_PB9MFP_SPI3_MISO}, + {PB_13, SPI_0, SYS_GPB_MFP3_PB13MFP_SPI0_MISO}, + {NU_PINNAME_BIND(PB_13, SPI_0), SPI_0, SYS_GPB_MFP3_PB13MFP_SPI0_MISO}, + {PB_13, SPI_9, SYS_GPB_MFP3_PB13MFP_SPI9_MISO}, + {NU_PINNAME_BIND(PB_13, SPI_9), SPI_9, SYS_GPB_MFP3_PB13MFP_SPI9_MISO}, + {PC_1, SPI_11, SYS_GPC_MFP0_PC1MFP_QSPI0_MISO0}, + {NU_PINNAME_BIND(PC_1, SPI_11), SPI_11, SYS_GPC_MFP0_PC1MFP_QSPI0_MISO0}, + {PC_1, SPI_7, SYS_GPC_MFP0_PC1MFP_SPI7_MISO}, + {NU_PINNAME_BIND(PC_1, SPI_7), SPI_7, SYS_GPC_MFP0_PC1MFP_SPI7_MISO}, + {PC_3, SPI_12, SYS_GPC_MFP0_PC3MFP_QSPI1_MISO0}, + {NU_PINNAME_BIND(PC_3, SPI_12), SPI_12, SYS_GPC_MFP0_PC3MFP_QSPI1_MISO0}, + {PC_3, SPI_1, SYS_GPC_MFP0_PC3MFP_SPI1_MISO}, + {NU_PINNAME_BIND(PC_3, SPI_1), SPI_1, SYS_GPC_MFP0_PC3MFP_SPI1_MISO}, + {PC_7, SPI_1, SYS_GPC_MFP1_PC7MFP_SPI1_MISO}, + {NU_PINNAME_BIND(PC_7, SPI_1), SPI_1, SYS_GPC_MFP1_PC7MFP_SPI1_MISO}, + {PC_7, SPI_6, SYS_GPC_MFP1_PC7MFP_SPI6_MISO}, + {NU_PINNAME_BIND(PC_7, SPI_6), SPI_6, SYS_GPC_MFP1_PC7MFP_SPI6_MISO}, + {PC_12, SPI_3, SYS_GPC_MFP3_PC12MFP_SPI3_MISO}, + {PD_1, SPI_0, SYS_GPD_MFP0_PD1MFP_SPI0_MISO}, + {PD_7, SPI_12, SYS_GPD_MFP1_PD7MFP_QSPI1_MISO0}, + {NU_PINNAME_BIND(PD_7, SPI_12), SPI_12, SYS_GPD_MFP1_PD7MFP_QSPI1_MISO0}, + {PD_7, SPI_1, SYS_GPD_MFP1_PD7MFP_SPI1_MISO}, + {NU_PINNAME_BIND(PD_7, SPI_1), SPI_1, SYS_GPD_MFP1_PD7MFP_SPI1_MISO}, + {PD_11, SPI_9, SYS_GPD_MFP2_PD11MFP_SPI9_MISO}, + {PE_1, SPI_11, SYS_GPE_MFP0_PE1MFP_QSPI0_MISO0}, + {NU_PINNAME_BIND(PE_1, SPI_11), SPI_11, SYS_GPE_MFP0_PE1MFP_QSPI0_MISO0}, + {PE_1, SPI_1, SYS_GPE_MFP0_PE1MFP_SPI1_MISO}, + {NU_PINNAME_BIND(PE_1, SPI_1), SPI_1, SYS_GPE_MFP0_PE1MFP_SPI1_MISO}, + {PE_3, SPI_3, SYS_GPE_MFP0_PE3MFP_SPI3_MISO}, + {PE_9, SPI_2, SYS_GPE_MFP2_PE9MFP_SPI2_MISO}, + {PF_0, SPI_12, SYS_GPF_MFP0_PF0MFP_QSPI1_MISO0}, + {PF_4, SPI_5, SYS_GPF_MFP1_PF4MFP_SPI5_MISO}, + {PF_7, SPI_0, SYS_GPF_MFP1_PF7MFP_SPI0_MISO}, + {PG_4, SPI_2, SYS_GPG_MFP1_PG4MFP_SPI2_MISO}, + {PG_7, SPI_3, SYS_GPG_MFP1_PG7MFP_SPI3_MISO}, + {PG_12, SPI_8, SYS_GPG_MFP3_PG12MFP_SPI8_MISO}, + {PG_13, SPI_12, SYS_GPG_MFP3_PG13MFP_QSPI1_MISO0}, + {PH_4, SPI_1, SYS_GPH_MFP1_PH4MFP_SPI1_MISO}, + {PI_7, SPI_1, SYS_GPI_MFP1_PI7MFP_SPI1_MISO}, + {PJ_0, SPI_11, SYS_GPJ_MFP0_PJ0MFP_QSPI0_MISO0}, + {PJ_4, SPI_12, SYS_GPJ_MFP1_PJ4MFP_QSPI1_MISO0}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_2, SPI_11, SYS_GPA_MFP0_PA2MFP_QSPI0_CLK}, + {NU_PINNAME_BIND(PA_2, SPI_11), SPI_11, SYS_GPA_MFP0_PA2MFP_QSPI0_CLK}, + {PA_2, SPI_0, SYS_GPA_MFP0_PA2MFP_SPI0_CLK}, + {NU_PINNAME_BIND(PA_2, SPI_0), SPI_0, SYS_GPA_MFP0_PA2MFP_SPI0_CLK}, + {PA_6, SPI_5, SYS_GPA_MFP1_PA6MFP_SPI5_CLK}, + {NU_PINNAME_BIND(PA_6, SPI_5), SPI_5, SYS_GPA_MFP1_PA6MFP_SPI5_CLK}, + {PA_6, SPI_6, SYS_GPA_MFP1_PA6MFP_SPI6_CLK}, + {NU_PINNAME_BIND(PA_6, SPI_6), SPI_6, SYS_GPA_MFP1_PA6MFP_SPI6_CLK}, + {PA_7, SPI_1, SYS_GPA_MFP1_PA7MFP_SPI1_CLK}, + {PA_10, SPI_2, SYS_GPA_MFP2_PA10MFP_SPI2_CLK}, + {PA_13, SPI_0, SYS_GPA_MFP3_PA13MFP_SPI0_CLK}, + {NU_PINNAME_BIND(PA_13, SPI_0), SPI_0, SYS_GPA_MFP3_PA13MFP_SPI0_CLK}, + {PA_13, SPI_2, SYS_GPA_MFP3_PA13MFP_SPI2_CLK}, + {NU_PINNAME_BIND(PA_13, SPI_2), SPI_2, SYS_GPA_MFP3_PA13MFP_SPI2_CLK}, + {PA_13, SPI_10, SYS_GPA_MFP3_PA13MFP_SPI10_CLK}, + {NU_PINNAME_BIND(PA_13, SPI_10), SPI_10, SYS_GPA_MFP3_PA13MFP_SPI10_CLK}, + {PB_2, SPI_4, SYS_GPB_MFP0_PB2MFP_SPI4_CLK}, + {PB_3, SPI_1, SYS_GPB_MFP0_PB3MFP_SPI1_CLK}, + {PB_7, SPI_1, SYS_GPB_MFP1_PB7MFP_SPI1_CLK}, + {PB_11, SPI_3, SYS_GPB_MFP2_PB11MFP_SPI3_CLK}, + {PB_13, SPI_3, SYS_GPB_MFP3_PB13MFP_SPI3_CLK}, + {PB_14, SPI_0, SYS_GPB_MFP3_PB14MFP_SPI0_CLK}, + {PB_15, SPI_9, SYS_GPB_MFP3_PB15MFP_SPI9_CLK}, + {PC_0, SPI_12, SYS_GPC_MFP0_PC0MFP_QSPI1_CLK}, + {PC_1, SPI_1, SYS_GPC_MFP0_PC1MFP_SPI1_CLK}, + {PC_2, SPI_11, SYS_GPC_MFP0_PC2MFP_QSPI0_CLK}, + {NU_PINNAME_BIND(PC_2, SPI_11), SPI_11, SYS_GPC_MFP0_PC2MFP_QSPI0_CLK}, + {PC_2, SPI_7, SYS_GPC_MFP0_PC2MFP_SPI7_CLK}, + {NU_PINNAME_BIND(PC_2, SPI_7), SPI_7, SYS_GPC_MFP0_PC2MFP_SPI7_CLK}, + {PC_4, SPI_12, SYS_GPC_MFP1_PC4MFP_QSPI1_CLK}, + {PC_10, SPI_3, SYS_GPC_MFP2_PC10MFP_SPI3_CLK}, + {PC_14, SPI_11, SYS_GPC_MFP3_PC14MFP_QSPI0_CLK}, + {PD_2, SPI_0, SYS_GPD_MFP0_PD2MFP_SPI0_CLK}, + {PD_5, SPI_1, SYS_GPD_MFP1_PD5MFP_SPI1_CLK}, + {PD_12, SPI_9, SYS_GPD_MFP3_PD12MFP_SPI9_CLK}, + {PE_4, SPI_3, SYS_GPE_MFP1_PE4MFP_SPI3_CLK}, + {PE_8, SPI_2, SYS_GPE_MFP2_PE8MFP_SPI2_CLK}, + {PF_2, SPI_11, SYS_GPF_MFP0_PF2MFP_QSPI0_CLK}, + {PF_6, SPI_5, SYS_GPF_MFP1_PF6MFP_SPI5_CLK}, + {PF_8, SPI_0, SYS_GPF_MFP2_PF8MFP_SPI0_CLK}, + {PG_3, SPI_2, SYS_GPG_MFP0_PG3MFP_SPI2_CLK}, + {PG_6, SPI_3, SYS_GPG_MFP1_PG6MFP_SPI3_CLK}, + {PG_10, SPI_8, SYS_GPG_MFP2_PG10MFP_SPI8_CLK}, + {PG_12, SPI_12, SYS_GPG_MFP3_PG12MFP_QSPI1_CLK}, + {PH_6, SPI_1, SYS_GPH_MFP1_PH6MFP_SPI1_CLK}, + {PH_8, SPI_11, SYS_GPH_MFP2_PH8MFP_QSPI0_CLK}, + {NU_PINNAME_BIND(PH_8, SPI_11), SPI_11, SYS_GPH_MFP2_PH8MFP_QSPI0_CLK}, + {PH_8, SPI_1, SYS_GPH_MFP2_PH8MFP_SPI1_CLK}, + {NU_PINNAME_BIND(PH_8, SPI_1), SPI_1, SYS_GPH_MFP2_PH8MFP_SPI1_CLK}, + {PH_15, SPI_12, SYS_GPH_MFP3_PH15MFP_QSPI1_CLK}, + {PI_9, SPI_1, SYS_GPI_MFP2_PI9MFP_SPI1_CLK}, + {PI_15, SPI_11, SYS_GPI_MFP3_PI15MFP_QSPI0_CLK}, + {PJ_3, SPI_12, SYS_GPJ_MFP0_PJ3MFP_QSPI1_CLK}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI_11, SYS_GPA_MFP0_PA3MFP_QSPI0_SS}, + {NU_PINNAME_BIND(PA_3, SPI_11), SPI_11, SYS_GPA_MFP0_PA3MFP_QSPI0_SS}, + {PA_3, SPI_0, SYS_GPA_MFP0_PA3MFP_SPI0_SS}, + {NU_PINNAME_BIND(PA_3, SPI_0), SPI_0, SYS_GPA_MFP0_PA3MFP_SPI0_SS}, + {PA_6, SPI_1, SYS_GPA_MFP1_PA6MFP_SPI1_SS}, + {PA_7, SPI_5, SYS_GPA_MFP1_PA7MFP_SPI5_SS}, + {NU_PINNAME_BIND(PA_7, SPI_5), SPI_5, SYS_GPA_MFP1_PA7MFP_SPI5_SS}, + {PA_7, SPI_6, SYS_GPA_MFP1_PA7MFP_SPI6_SS}, + {NU_PINNAME_BIND(PA_7, SPI_6), SPI_6, SYS_GPA_MFP1_PA7MFP_SPI6_SS}, + {PA_11, SPI_2, SYS_GPA_MFP2_PA11MFP_SPI2_SS}, + {PA_12, SPI_0, SYS_GPA_MFP3_PA12MFP_SPI0_SS}, + {NU_PINNAME_BIND(PA_12, SPI_0), SPI_0, SYS_GPA_MFP3_PA12MFP_SPI0_SS}, + {PA_12, SPI_2, SYS_GPA_MFP3_PA12MFP_SPI2_SS}, + {NU_PINNAME_BIND(PA_12, SPI_2), SPI_2, SYS_GPA_MFP3_PA12MFP_SPI2_SS}, + {PA_12, SPI_10, SYS_GPA_MFP3_PA12MFP_SPI10_SS}, + {NU_PINNAME_BIND(PA_12, SPI_10), SPI_10, SYS_GPA_MFP3_PA12MFP_SPI10_SS}, + {PB_2, SPI_1, SYS_GPB_MFP0_PB2MFP_SPI1_SS}, + {PB_3, SPI_4, SYS_GPB_MFP0_PB3MFP_SPI4_SS}, + {PB_6, SPI_1, SYS_GPB_MFP1_PB6MFP_SPI1_SS}, + {PB_10, SPI_3, SYS_GPB_MFP2_PB10MFP_SPI3_SS}, + {PB_12, SPI_3, SYS_GPB_MFP3_PB12MFP_SPI3_SS}, + {PB_14, SPI_9, SYS_GPB_MFP3_PB14MFP_SPI9_SS}, + {PB_15, SPI_0, SYS_GPB_MFP3_PB15MFP_SPI0_SS}, + {PC_0, SPI_1, SYS_GPC_MFP0_PC0MFP_SPI1_SS}, + {PC_1, SPI_12, SYS_GPC_MFP0_PC1MFP_QSPI1_SS}, + {PC_3, SPI_11, SYS_GPC_MFP0_PC3MFP_QSPI0_SS}, + {NU_PINNAME_BIND(PC_3, SPI_11), SPI_11, SYS_GPC_MFP0_PC3MFP_QSPI0_SS}, + {PC_3, SPI_7, SYS_GPC_MFP0_PC3MFP_SPI7_SS}, + {NU_PINNAME_BIND(PC_3, SPI_7), SPI_7, SYS_GPC_MFP0_PC3MFP_SPI7_SS}, + {PC_5, SPI_12, SYS_GPC_MFP1_PC5MFP_QSPI1_SS}, + {PC_9, SPI_3, SYS_GPC_MFP2_PC9MFP_SPI3_SS}, + {PC_13, SPI_9, SYS_GPC_MFP3_PC13MFP_SPI9_SS}, + {PD_3, SPI_0, SYS_GPD_MFP0_PD3MFP_SPI0_SS}, + {PD_4, SPI_1, SYS_GPD_MFP1_PD4MFP_SPI1_SS}, + {PE_5, SPI_3, SYS_GPE_MFP1_PE5MFP_SPI3_SS}, + {PE_11, SPI_2, SYS_GPE_MFP2_PE11MFP_SPI2_SS}, + {PF_7, SPI_5, SYS_GPF_MFP1_PF7MFP_SPI5_SS}, + {PF_9, SPI_0, SYS_GPF_MFP2_PF9MFP_SPI0_SS}, + {PG_2, SPI_2, SYS_GPG_MFP0_PG2MFP_SPI2_SS}, + {PG_5, SPI_3, SYS_GPG_MFP1_PG5MFP_SPI3_SS}, + {PG_9, SPI_8, SYS_GPG_MFP2_PG9MFP_SPI8_SS}, + {PG_11, SPI_12, SYS_GPG_MFP2_PG11MFP_QSPI1_SS}, + {PH_7, SPI_1, SYS_GPH_MFP1_PH7MFP_SPI1_SS}, + {PH_9, SPI_11, SYS_GPH_MFP2_PH9MFP_QSPI0_SS}, + {NU_PINNAME_BIND(PH_9, SPI_11), SPI_11, SYS_GPH_MFP2_PH9MFP_QSPI0_SS}, + {PH_9, SPI_1, SYS_GPH_MFP2_PH9MFP_SPI1_SS}, + {NU_PINNAME_BIND(PH_9, SPI_1), SPI_1, SYS_GPH_MFP2_PH9MFP_SPI1_SS}, + {PH_14, SPI_12, SYS_GPH_MFP3_PH14MFP_QSPI1_SS}, + {PI_10, SPI_1, SYS_GPI_MFP2_PI10MFP_SPI1_SS}, + {PI_14, SPI_11, SYS_GPI_MFP3_PI14MFP_QSPI0_SS}, + {PJ_2, SPI_12, SYS_GPJ_MFP0_PJ2MFP_QSPI1_SS}, + + {NC, NC, 0} +}; + +//*** SD *** + +const PinMap PinMap_SD_DAT0[] = { + {PA_0, SD_1, SYS_GPA_MFP0_PA0MFP_SD1_DAT0}, + {PA_8, SD_1, SYS_GPA_MFP2_PA8MFP_SD1_DAT0}, + {PB_2, SD_0, SYS_GPB_MFP0_PB2MFP_SD0_DAT0}, + {PE_2, SD_0, SYS_GPE_MFP0_PE2MFP_SD0_DAT0}, + {PG_12, SD_1, SYS_GPG_MFP3_PG12MFP_SD1_DAT0}, + {PJ_11, SD_1, SYS_GPJ_MFP2_PJ11MFP_SD1_DAT0}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_DAT1[] = { + {PA_1, SD_1, SYS_GPA_MFP0_PA1MFP_SD1_DAT1}, + {PA_9, SD_1, SYS_GPA_MFP2_PA9MFP_SD1_DAT1}, + {PB_3, SD_0, SYS_GPB_MFP0_PB3MFP_SD0_DAT1}, + {PE_3, SD_0, SYS_GPE_MFP0_PE3MFP_SD0_DAT1}, + {PG_11, SD_1, SYS_GPG_MFP2_PG11MFP_SD1_DAT1}, + {PJ_10, SD_1, SYS_GPJ_MFP2_PJ10MFP_SD1_DAT1}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_DAT2[] = { + {PA_2, SD_1, SYS_GPA_MFP0_PA2MFP_SD1_DAT2}, + {PA_10, SD_1, SYS_GPA_MFP2_PA10MFP_SD1_DAT2}, + {PB_4, SD_0, SYS_GPB_MFP1_PB4MFP_SD0_DAT2}, + {PE_4, SD_0, SYS_GPE_MFP1_PE4MFP_SD0_DAT2}, + {PG_10, SD_1, SYS_GPG_MFP2_PG10MFP_SD1_DAT2}, + {PJ_9, SD_1, SYS_GPJ_MFP2_PJ9MFP_SD1_DAT2}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_DAT3[] = { + {PA_3, SD_1, SYS_GPA_MFP0_PA3MFP_SD1_DAT3}, + {PA_11, SD_1, SYS_GPA_MFP2_PA11MFP_SD1_DAT3}, + {PB_5, SD_0, SYS_GPB_MFP1_PB5MFP_SD0_DAT3}, + {PE_5, SD_0, SYS_GPE_MFP1_PE5MFP_SD0_DAT3}, + {PG_9, SD_1, SYS_GPG_MFP2_PG9MFP_SD1_DAT3}, + {PJ_8, SD_1, SYS_GPJ_MFP2_PJ8MFP_SD1_DAT3}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_CMD[] = { + {PA_5, SD_1, SYS_GPA_MFP1_PA5MFP_SD1_CMD}, + {PB_0, SD_0, SYS_GPB_MFP0_PB0MFP_SD0_CMD}, + {PB_7, SD_1, SYS_GPB_MFP1_PB7MFP_SD1_CMD}, + {PE_7, SD_0, SYS_GPE_MFP1_PE7MFP_SD0_CMD}, + {PG_13, SD_1, SYS_GPG_MFP3_PG13MFP_SD1_CMD}, + {PJ_12, SD_1, SYS_GPJ_MFP3_PJ12MFP_SD1_CMD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_CLK[] = { + {PA_4, SD_1, SYS_GPA_MFP1_PA4MFP_SD1_CLK}, + {PB_1, SD_0, SYS_GPB_MFP0_PB1MFP_SD0_CLK}, + {PB_6, SD_1, SYS_GPB_MFP1_PB6MFP_SD1_CLK}, + {PD_13, SD_1, SYS_GPD_MFP3_PD13MFP_SD1_CLK}, + {PE_6, SD_0, SYS_GPE_MFP1_PE6MFP_SD0_CLK}, + {PG_14, SD_1, SYS_GPG_MFP3_PG14MFP_SD1_CLK}, + {PJ_13, SD_1, SYS_GPJ_MFP3_PJ13MFP_SD1_CLK}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_CD[] = { + {PA_6, SD_1, SYS_GPA_MFP1_PA6MFP_SD1_nCD}, + {PA_12, SD_1, SYS_GPA_MFP3_PA12MFP_SD1_nCD}, + {PB_12, SD_0, SYS_GPB_MFP3_PB12MFP_SD0_nCD}, + {PD_13, SD_0, SYS_GPD_MFP3_PD13MFP_SD0_nCD}, + {PE_14, SD_1, SYS_GPE_MFP3_PE14MFP_SD1_nCD}, + {PG_15, SD_1, SYS_GPG_MFP3_PG15MFP_SD1_nCD}, + + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_TD[] = { + {PA_5, CAN_0, SYS_GPA_MFP1_PA5MFP_CAN0_TXD}, + {PA_12, CAN_0, SYS_GPA_MFP3_PA12MFP_CAN0_TXD}, + {PB_7, CAN_1, SYS_GPB_MFP1_PB7MFP_CAN1_TXD}, + {PB_9, CAN_2, SYS_GPB_MFP2_PB9MFP_CAN2_TXD}, + {PB_11, CAN_0, SYS_GPB_MFP2_PB11MFP_CAN0_TXD}, + {PB_13, CAN_3, SYS_GPB_MFP3_PB13MFP_CAN3_TXD}, + {PC_1, CAN_2, SYS_GPC_MFP0_PC1MFP_CAN2_TXD}, + {PC_3, CAN_1, SYS_GPC_MFP0_PC3MFP_CAN1_TXD}, + {PC_5, CAN_0, SYS_GPC_MFP1_PC5MFP_CAN0_TXD}, + {PC_7, CAN_3, SYS_GPC_MFP1_PC7MFP_CAN3_TXD}, + {PC_10, CAN_1, SYS_GPC_MFP2_PC10MFP_CAN1_TXD}, + {PC_13, CAN_1, SYS_GPC_MFP3_PC13MFP_CAN1_TXD}, + {PD_9, CAN_2, SYS_GPD_MFP2_PD9MFP_CAN2_TXD}, + {PD_11, CAN_0, SYS_GPD_MFP2_PD11MFP_CAN0_TXD}, + {PE_7, CAN_1, SYS_GPE_MFP1_PE7MFP_CAN1_TXD}, + {PE_14, CAN_0, SYS_GPE_MFP3_PE14MFP_CAN0_TXD}, + {PF_0, CAN_2, SYS_GPF_MFP0_PF0MFP_CAN2_TXD}, + {PF_7, CAN_2, SYS_GPF_MFP1_PF7MFP_CAN2_TXD}, + {PF_9, CAN_1, SYS_GPF_MFP2_PF9MFP_CAN1_TXD}, + {PF_11, CAN_3, SYS_GPF_MFP2_PF11MFP_CAN3_TXD}, + {PG_0, CAN_1, SYS_GPG_MFP0_PG0MFP_CAN1_TXD}, + {PH_12, CAN_3, SYS_GPH_MFP3_PH12MFP_CAN3_TXD}, + {PI_6, CAN_3, SYS_GPI_MFP1_PI6MFP_CAN3_TXD}, + {PI_8, CAN_2, SYS_GPI_MFP2_PI8MFP_CAN2_TXD}, + {PI_10, CAN_3, SYS_GPI_MFP2_PI10MFP_CAN3_TXD}, + {PI_12, CAN_0, SYS_GPI_MFP3_PI12MFP_CAN0_TXD}, + {PI_14, CAN_1, SYS_GPI_MFP3_PI14MFP_CAN1_TXD}, + {PJ_0, CAN_2, SYS_GPJ_MFP0_PJ0MFP_CAN2_TXD}, + {PJ_2, CAN_0, SYS_GPJ_MFP0_PJ2MFP_CAN0_TXD}, + {PJ_4, CAN_1, SYS_GPJ_MFP1_PJ4MFP_CAN1_TXD}, + {PJ_6, CAN_2, SYS_GPJ_MFP1_PJ6MFP_CAN2_TXD}, + {PJ_8, CAN_2, SYS_GPJ_MFP2_PJ8MFP_CAN2_TXD}, + {PJ_10, CAN_0, SYS_GPJ_MFP2_PJ10MFP_CAN0_TXD}, + {PJ_12, CAN_1, SYS_GPJ_MFP3_PJ12MFP_CAN1_TXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_RD[] = { + {PA_4, CAN_0, SYS_GPA_MFP1_PA4MFP_CAN0_RXD}, + {PA_13, CAN_0, SYS_GPA_MFP3_PA13MFP_CAN0_RXD}, + {PB_6, CAN_1, SYS_GPB_MFP1_PB6MFP_CAN1_RXD}, + {PB_8, CAN_2, SYS_GPB_MFP2_PB8MFP_CAN2_RXD}, + {PB_10, CAN_0, SYS_GPB_MFP2_PB10MFP_CAN0_RXD}, + {PB_12, CAN_3, SYS_GPB_MFP3_PB12MFP_CAN3_RXD}, + {PC_0, CAN_2, SYS_GPC_MFP0_PC0MFP_CAN2_RXD}, + {PC_2, CAN_1, SYS_GPC_MFP0_PC2MFP_CAN1_RXD}, + {PC_4, CAN_0, SYS_GPC_MFP1_PC4MFP_CAN0_RXD}, + {PC_6, CAN_3, SYS_GPC_MFP1_PC6MFP_CAN3_RXD}, + {PC_9, CAN_1, SYS_GPC_MFP2_PC9MFP_CAN1_RXD}, + {PD_8, CAN_2, SYS_GPD_MFP2_PD8MFP_CAN2_RXD}, + {PD_10, CAN_0, SYS_GPD_MFP2_PD10MFP_CAN0_RXD}, + {PD_12, CAN_1, SYS_GPD_MFP3_PD12MFP_CAN1_RXD}, + {PE_6, CAN_1, SYS_GPE_MFP1_PE6MFP_CAN1_RXD}, + {PE_15, CAN_0, SYS_GPE_MFP3_PE15MFP_CAN0_RXD}, + {PF_1, CAN_2, SYS_GPF_MFP0_PF1MFP_CAN2_RXD}, + {PF_6, CAN_2, SYS_GPF_MFP1_PF6MFP_CAN2_RXD}, + {PF_8, CAN_1, SYS_GPF_MFP2_PF8MFP_CAN1_RXD}, + {PF_10, CAN_3, SYS_GPF_MFP2_PF10MFP_CAN3_RXD}, + {PG_1, CAN_1, SYS_GPG_MFP0_PG1MFP_CAN1_RXD}, + {PH_13, CAN_3, SYS_GPH_MFP3_PH13MFP_CAN3_RXD}, + {PI_7, CAN_3, SYS_GPI_MFP1_PI7MFP_CAN3_RXD}, + {PI_9, CAN_2, SYS_GPI_MFP2_PI9MFP_CAN2_RXD}, + {PI_11, CAN_3, SYS_GPI_MFP2_PI11MFP_CAN3_RXD}, + {PI_13, CAN_0, SYS_GPI_MFP3_PI13MFP_CAN0_RXD}, + {PI_15, CAN_1, SYS_GPI_MFP3_PI15MFP_CAN1_RXD}, + {PJ_1, CAN_2, SYS_GPJ_MFP0_PJ1MFP_CAN2_RXD}, + {PJ_3, CAN_0, SYS_GPJ_MFP0_PJ3MFP_CAN0_RXD}, + {PJ_5, CAN_1, SYS_GPJ_MFP1_PJ5MFP_CAN1_RXD}, + {PJ_7, CAN_2, SYS_GPJ_MFP1_PJ7MFP_CAN2_RXD}, + {PJ_9, CAN_2, SYS_GPJ_MFP2_PJ9MFP_CAN2_RXD}, + {PJ_11, CAN_0, SYS_GPJ_MFP2_PJ11MFP_CAN0_RXD}, + {PJ_13, CAN_1, SYS_GPJ_MFP3_PJ13MFP_CAN1_RXD}, + + {NC, NC, 0} +}; diff --git a/targets/TARGET_NUVOTON/TARGET_M460/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M460/PeripheralPins.h new file mode 100644 index 0000000..92a9561 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/PeripheralPins.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//*** GPIO *** + +extern const PinMap PinMap_GPIO[]; + +//*** ADC *** + +extern const PinMap PinMap_ADC[]; + +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + +//*** I2C *** + +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//*** PWM *** + +extern const PinMap PinMap_PWM[]; + +//*** SERIAL *** + +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; + +//*** SPI *** + +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; + +//*** SD *** + +extern const PinMap PinMap_SD_CD[]; +extern const PinMap PinMap_SD_CMD[]; +extern const PinMap PinMap_SD_CLK[]; +extern const PinMap PinMap_SD_DAT0[]; +extern const PinMap PinMap_SD_DAT1[]; +extern const PinMap PinMap_SD_DAT2[]; +extern const PinMap PinMap_SD_DAT3[]; + +//*** CAN *** + +extern PinMap const PinMap_CAN_TD[]; +extern PinMap const PinMap_CAN_RD[]; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/PinNamesCommon.h b/targets/TARGET_NUVOTON/TARGET_M460/PinNamesCommon.h new file mode 100644 index 0000000..e63115a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/PinNamesCommon.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PIN_NAME_COMMON_H__ +#define __PIN_NAME_COMMON_H__ + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NU_PININDEX_Pos 0 +#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos) +#define NU_PINPORT_Pos 8 +#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos) +#define NU_PIN_MODINDEX_Pos 12 +#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos) +#define NU_PIN_BIND_Pos 16 +#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos) + +#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos) +#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos) +#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos) +#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos) +#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos)) +#define NU_PINNAME_BIND(PINNAME, modname) ((PinName) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)) +#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk) + +#define NU_PORT_BASE(PORT) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * PORT)) +#define NU_MFP_POS(PIN) ((PIN % 4) * 8) +#define NU_MFP_MSK(PIN) (0x1ful << NU_MFP_POS(PIN)) + +// LEGACY +#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME) +#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME) +#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME) +#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN)) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + /* Input pull mode */ + PullNone = 0, + PullDown, + PullUp, + + /* I/O mode */ + InputOnly, + PushPullOutput, + OpenDrain, + QuasiBidirectional, + + /* Default input pull mode */ + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif // __PIN_NAME_COMMON_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/PortNames.h b/targets/TARGET_NUVOTON/TARGET_M460/PortNames.h new file mode 100644 index 0000000..5c8e571 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/PortNames.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7, + PortI = 8, + PortJ = 9 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/README.md b/targets/TARGET_NUVOTON/TARGET_M460/README.md new file mode 100644 index 0000000..f4086d0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/README.md @@ -0,0 +1,67 @@ +# Nuvoton M460 series + +## HyperRAM + +HyperRAM, via Hyper Bus Interface Controller (HBI), is mapped to two regions: `0x0A00_0000`–`0x0BFF_FFFF` and `0x8000_0000`–`0x81FF_FFFF`, through which CPU can direct access. + +### Enable HBI for HyperRAM + +To enable HBI for HyperRAM, create one Mbed OS application configuration file named `mbed_app.json` under root directory of your sample program. +The file should have the following content which will enable HBI and configure its multi-function pins: + +**mbed_app.json**: + +```json +{ + ...... + "target_overrides": { + ...... + "NUMAKER_IOT_M467": { + "target.hbi-enable": true, + "target.hbi-mfp-reg-list": "0x40000534, 0x4000057C, 0x40000590, 0x40000594", + "target.hbi-mfp-reg-msk-list": "0xFFFFFF00, 0xFFFFFFFF, 0xFFFF0000, 0xFFFFFFFF", + "target.hbi-mfp-reg-val-list": "0x10101000, 0x10101010, 0x10100000, 0x10101010" + } + } +} +``` + +Where: + +- `hbi-mfp-reg-list`: Comma-separated list of relevant multi-function pin registers +- `hbi-mfp-reg-msk-list`: Comma-separated list of relevant multi-function pin register masks +- `hbi-mfp-reg-val-list`: Comma-separated list of relevant multi-function pin register values + +> **_NOTE:_** Make sure your HyperRAM hardware is ready. + +> **_NOTE:_** Change the multi-function pins to align with your hardware. + +### Locate data at HyperRAM + +In the port, the region `0x8000_0000`–`0x81FF_FFFF` is chosen for the goal because on Mbed OS, MPU is enabled and the region is configured to be write-able, which naturally fits HyperRAM. +To get to the goal, data must place in specified sections: + +**Locate initialized data** + +Initialized data are just like `RW` sections for ARM, `.data` sectionis for GCC_ARM, and `readwrite` sections for IAR. +To locate them at HyperRAM, place in specified sections named `.data.nu.hyperram`. + +```c++ +__attribute__((section(".data.nu.hyperram"))) +uint32_t my_data = 100; +``` + +**Locate zero-initialized data** + +Zero-initialized data are just like `ZI` sections for ARM, `.bss` sections for GCC_ARM, and `zeroinit` sections for IAR. +To locate them at HyperRAM, place in specified sections named`.bss.nu.hyperram`. + +```c++ +__attribute__((section(".bss.nu.hyperram"))) +uint32_t my_bss; +``` + +> **_NOTE:_** Don't mis-place in sections, +or behavior is undefined because C runtime is not correctly initialized for these sections. + +> **_NOTE:_** Check linker-generated .map file to make sure your data are actually located at HyperRAM. diff --git a/targets/TARGET_NUVOTON/TARGET_M460/TARGET_NUMAKER_IOT_M467/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M460/TARGET_NUMAKER_IOT_M467/PinNames.h new file mode 100644 index 0000000..c0c0eb9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/TARGET_NUMAKER_IOT_M467/PinNames.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* MBED TARGET LIST: NUMAKER_IOT_M467 */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesCommon.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + // Not connected + NC = (int)0xFFFFFFFF, + + // Generic naming + PA_INIT = NU_PINNAME(0, 0), PA_0 = PA_INIT, PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15, + PB_INIT = NU_PINNAME(1, 0), PB_0 = PB_INIT, PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15, + PC_INIT = NU_PINNAME(2, 0), PC_0 = PC_INIT, PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14, + PD_INIT = NU_PINNAME(3, 0), PD_0 = PD_INIT, PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14, + PE_INIT = NU_PINNAME(4, 0), PE_0 = PE_INIT, PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15, + PF_INIT = NU_PINNAME(5, 0), PF_0 = PF_INIT, PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11, + PG_INIT = NU_PINNAME(6, 0), PG_0 = PG_INIT, PG_1, PG_2, PG_3, PG_4, PG_5, PG_6, PG_7, PG_8, PG_9, PG_10, PG_11, PG_12, PG_13, PG_14, PG_15, + PH_INIT = NU_PINNAME(7, 0), PH_0 = PH_INIT, PH_1, PH_2, PH_3, PH_4, PH_5, PH_6, PH_7, PH_8, PH_9, PH_10, PH_11, PH_12, PH_13, PH_14, PH_15, + PI_INIT = NU_PINNAME(8, 0), PI_6 = PI_INIT + 6, PI_7, PI_8, PI_9, PI_10, PI_11, PI_12, PI_13, PI_14, PI_15, + PJ_INIT = NU_PINNAME(9, 0), PJ_0 = PJ_INIT, PJ_1, PJ_2, PJ_3, PJ_4, PJ_5, PJ_6, PJ_7, PJ_8, PJ_9, PJ_10, PJ_11, PJ_12, PJ_13, + + // Arduino UNO naming + ARDUINO_UNO_A0 = PB_6, + ARDUINO_UNO_A1 = PB_7, + ARDUINO_UNO_A2 = PB_8, + ARDUINO_UNO_A3 = PB_9, + ARDUINO_UNO_A4 = PB_0, + ARDUINO_UNO_A5 = PB_1, + + ARDUINO_UNO_D0 = PB_2, + ARDUINO_UNO_D1 = PB_3, + ARDUINO_UNO_D2 = PC_9, + ARDUINO_UNO_D3 = PC_10, + ARDUINO_UNO_D4 = PC_11, + ARDUINO_UNO_D5 = PC_12, + ARDUINO_UNO_D6 = PB_4, + ARDUINO_UNO_D7 = PB_5, + ARDUINO_UNO_D8 = PA_5, + ARDUINO_UNO_D9 = PA_4, + ARDUINO_UNO_D10 = PA_3, + ARDUINO_UNO_D11 = PA_0, + ARDUINO_UNO_D12 = PA_1, + ARDUINO_UNO_D13 = PA_2, + ARDUINO_UNO_D14 = PG_1, + ARDUINO_UNO_D15 = PG_0, + + // Other board-specific naming + + // UART naming + CONSOLE_TX = MBED_CONF_TARGET_USB_UART_TX, + CONSOLE_RX = MBED_CONF_TARGET_USB_UART_RX, + +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = CONSOLE_TX, +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = CONSOLE_RX, +#endif + + // Force PinName to 32-bit required by NU_PINNAME_BIND(...) + FORCE_ENUM_PINNAME_32BIT = 0x7FFFFFFF, + +} PinName; + +// LED naming +#define LED1 PH_4 // LED_RED +#define LED2 PH_5 // LED_YELLOW +#define LED3 PH_6 // LED_GREEN + +// Button naming +#define BUTTON1 PH_0 // BTN0 +#define BUTTON2 PH_1 // BTN1 +#define BTN0 BUTTON1 +#define BTN1 BUTTON2 + +#ifdef __cplusplus +} +#endif + +#endif // MBED_PINNAMES_H diff --git a/targets/TARGET_NUVOTON/TARGET_M460/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M460/analogin_api.c new file mode 100644 index 0000000..bf6aeca --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/analogin_api.c @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" + +static uint32_t eadc_modinit_mask = 0; + +static const struct nu_modinit_s adc_modinit_tab[] = { + /* EADC0 */ + {ADC_0_0, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_1, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_2, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_3, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_4, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_5, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_6, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_7, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_8, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_9, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_10, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_11, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_12, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_13, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_14, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + {ADC_0_15, EADC0_MODULE, CLK_CLKSEL0_EADC0SEL_HCLK, CLK_CLKDIV0_EADC0(8), EADC0_RST, EADC00_IRQn, NULL}, + + /* EADC1 */ + {ADC_1_0, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_1, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_2, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_3, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_4, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_5, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_6, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_7, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_8, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_9, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_10, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_11, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_12, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_13, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_14, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + {ADC_1_15, EADC1_MODULE, CLK_CLKSEL0_EADC1SEL_HCLK, CLK_CLKDIV2_EADC1(8), EADC1_RST, EADC10_IRQn, NULL}, + + /* EADC2 */ + {ADC_2_0, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_1, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_2, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_3, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_4, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_5, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_6, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_7, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_8, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_9, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_10, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_11, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_12, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_13, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_14, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, + {ADC_2_15, EADC2_MODULE, CLK_CLKSEL0_EADC2SEL_HCLK, CLK_CLKDIV5_EADC2(8), EADC2_RST, EADC20_IRQn, NULL}, +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->adc); + + obj->pin = pin; + + // Wire pinout + pinmap_pinout(pin, PinMap_ADC); + + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + + // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module. + if (! eadc_modinit_mask) { + // Unlock protected registers + SYS_UnlockReg(); + + // Select clock source of paired channels + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + // Enable clock of paired channels + CLK_EnableModuleClock(modinit->clkidx); + + // Reset this module if no channel enabled + SYS_ResetModule(modinit->rsetidx); + + // Lock protected registers + SYS_LockReg(); + + // Set the ADC internal sampling time, input mode as single-end and enable the A/D converter + EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END); + } + + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + // Configure the sample module Nmod for analog input channel Nch and software trigger source + EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); + + eadc_modinit_mask |= 1 << chn; +} + +void analogin_free(analogin_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab); + MBED_ASSERT(modinit->modname == (int) obj->adc); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + + /* Channel-level windup from here */ + + /* Mark channel free */ + eadc_modinit_mask &= ~(1 << chn); + + /* Module-level windup from here */ + + /* See analogin_init() for reason */ + if (! eadc_modinit_mask) { + /* Disable EADC module */ + EADC_Close(eadc_base); + + /* Disable IP clock */ + CLK_DisableModuleClock(modinit->clkidx); + } + + /* Free up pins */ + gpio_set(obj->pin); + obj->pin = NC; +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + EADC_START_CONV(eadc_base, 1 << chn); + while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != ((uint32_t) (1 << chn))); + uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn); + // Just 12 bits are effective. Convert to 16 bits. + // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0 + // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8); + + return conv_res_16; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = analogin_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M460/analogout_api.c new file mode 100644 index 0000000..2944bd7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/analogout_api.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" + +/* Maximum DAC modules */ +#define NU_DACMOD_MAXNUM 2 +/* Maximum DAC channels per module */ +#define NU_DACCHN_MAXNUM 1 + +static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM]; + +static const struct nu_modinit_s dac_modinit_tab[] = { + {DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL}, + {DAC_1_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + obj->pin = pin; + + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Module-level setup from here */ + + /* DAC0/DAC1 are designed to share the same RESET/clock/IRQ for group + * function. So we: + * + * 1. Go to setup flow (analogout_init()) only when none of DAC0/DAC1 + * channels are activated. + * 2. Go to windup flow (analogout_free()) only when all DAC0/DAC1 + * channels are deactivated. + */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + /* Select IP clock source and clock divider */ + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock */ + CLK_EnableModuleClock(modinit->clkidx); + + /* Reset IP */ + SYS_ResetModule(modinit->rsetidx); + + /* The conversion settling time is 8us when 12-bit input code transition from + * lowest code (0x000) to highest code (0xFFF). */ + DAC_SetDelayTime(dac_base, 8); + + /* Configure DAT data format to left-aligned + * Effective 12-bits are aligned to left of 16-bit DAC_DAT. */ + DAC_ENABLE_LEFT_ALIGN(dac_base); + } + + /* Channel-level setup from here: */ + + /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ + DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); + + /* Mark channel allocated */ + dac_modinit_mask[modidx] |= 1 << chn; +} + +void analogout_free(dac_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Channel-level windup from here */ + + /* Mark channel free */ + dac_modinit_mask[modidx] &= ~(1 << chn); + + /* Close channel */ + DAC_Close(dac_base, chn); + + /* Module-level windup from here: */ + + /* See analogout_init() for reason */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + + /* Disable IP clock */ + CLK_DisableModuleClock(modinit->clkidx); + } + + /* Free up pin */ + gpio_set(obj->pin); + obj->pin = NC; +} + +void analogout_write(dac_t *obj, float value) +{ + if (value <= 0.0f) { + analogout_write_u16(obj, 0); + } else if (value >= 1.0f) { + analogout_write_u16(obj, 0xFFFF); + } else { + analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF))); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + /* Suppress 'unused variable' warning in case of macro function below expanding to none */ + MBED_UNUSED uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + DAC_WRITE_DATA(dac_base, chn, value); + + /* Clear the DAC conversion complete finish flag for safe */ + DAC_CLR_INT_FLAG(dac_base, chn); + + /* Start A/D conversion */ + DAC_START_CONV(dac_base); + + /* Wait for completed */ + while (DAC_IS_BUSY(dac_base, chn)); +} + +float analogout_read(dac_t *obj) +{ + uint32_t value = analogout_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + /* Suppress 'unused variable' warning in case of macro function below expanding to none */ + MBED_UNUSED uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + uint16_t dat12_4 = DAC_READ_DATA(dac_base, chn); + /* Just 12 bits are effective. Convert to 16 bits. + * + * dat12_4 : b11b10b9b8 b7b6b5b4 b3b2b1b0 0000 + * dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + */ + uint16_t dat16 = (dat12_4 & 0xFFF0) | (dat12_4 >> 12); + + return dat16; +} + +const PinMap *analogout_pinmap() +{ + return PinMap_DAC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/crypto/crypto-misc.cpp b/targets/TARGET_NUVOTON/TARGET_M460/crypto/crypto-misc.cpp new file mode 100644 index 0000000..8d044bb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/crypto/crypto-misc.cpp @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" +#include "mbed_assert.h" +#include "mbed_atomic.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include "nu_timer.h" +#include "crypto-misc.h" +#include "platform/SingletonPtr.h" +#include "platform/PlatformMutex.h" +#include "hal/trng_api.h" + +#if defined(MBEDTLS_CONFIG_HW_SUPPORT) + +/* Consideration for choosing proper synchronization mechanism + * + * We choose mutex to synchronize access to crypto ACC. We can guarantee: + * (1) No deadlock + * We just lock mutex for a short sequence of operations rather than the whole lifetime + * of crypto context. + * (2) No priority inversion + * Mutex supports priority inheritance and it is enabled. + */ + +/* Mutex for crypto PRNG ACC management */ +static SingletonPtr crypto_prng_mutex; + +/* Mutex for crypto AES ACC management */ +static SingletonPtr crypto_aes_mutex; + +/* Mutex for crypto SHA ACC management */ +static SingletonPtr crypto_sha_mutex; + +/* Mutex for crypto ECC ACC management */ +static SingletonPtr crypto_ecc_mutex; + +/* Mutex for crypto RSA ACC management */ +static SingletonPtr crypto_rsa_mutex; + +/* Crypto init counter. Crypto keeps active as it is non-zero. */ +static uint16_t crypto_init_counter = 0U; + +/* Crypto done flags */ +#define NU_CRYPTO_DONE_OK BIT0 // Done with OK +#define NU_CRYPTO_DONE_ERR BIT1 // Done with error + +/* Track if PRNG H/W operation is done */ +static volatile uint16_t crypto_prng_done; +/* Track if AES H/W operation is done */ +static volatile uint16_t crypto_aes_done; +/* Track if SHA H/W operation is done */ +static volatile uint16_t crypto_sha_done; +/* Track if ECC H/W operation is done */ +static volatile uint16_t crypto_ecc_done; +/* Track if RSA H/W operation is done */ +static volatile uint16_t crypto_rsa_done; + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done); +static bool crypto_submodule_wait(volatile uint16_t *submodule_done, int32_t timeout_us); + +/* As crypto init counter changes from 0 to 1: + * + * 1. Enable crypto clock + * 2. Enable crypto interrupt + */ +void crypto_init(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == USHRT_MAX) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would overflow (> USHRT_MAX)"); + } + core_util_atomic_incr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 1) { + SYS_UnlockReg(); // Unlock protected register + CLK_EnableModuleClock(CRPT_MODULE); + SYS_ResetModule(CRPT_RST); + SYS_LockReg(); // Lock protected register + + NVIC_EnableIRQ(CRPT_IRQn); + + /* Seed PRNG with TRNG to enable SCAP + * + * According to TRM, it is suggested PRNG be seeded by TRNG on + * every Crypto H/W reset. + * + * To serialize access to TRNG, we invoke Mbed OS TRNG HAL API whose + * implementations are thread-safe, instead of BSP RNG driver. + */ + trng_t trng_ctx; + trng_init(&trng_ctx); + + /* Wait for PRNG free */ + while (CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk); + + /* Reload seed from TRNG for the first time */ + CRPT->PRNG_CTL = (PRNG_KEY_SIZE_256 << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk | PRNG_CTL_SEEDSRC_TRNG; + + /* Wait for PRNG done */ + while (CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk); + + /* No reload seed for following times */ + CRPT->PRNG_CTL = 0; + + trng_free(&trng_ctx); + } + core_util_critical_section_exit(); +} + +/* As crypto init counter changes from 1 to 0: + * + * 1. Disable crypto interrupt + * 2. Disable crypto clock + */ +void crypto_uninit(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == 0) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would underflow (< 0)"); + } + core_util_atomic_decr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 0) { + NVIC_DisableIRQ(CRPT_IRQn); + + SYS_UnlockReg(); // Unlock protected register + CLK_DisableModuleClock(CRPT_MODULE); + SYS_LockReg(); // Lock protected register + } + core_util_critical_section_exit(); +} + +/* Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = (volatile unsigned char*) v; + while (n--) { + *p++ = 0; + } +} + +/* Implementation that should never be optimized out by the compiler */ +void crypto_zeroize32(uint32_t *v, size_t n) +{ + volatile uint32_t *p = (volatile uint32_t*) v; + while (n--) { + *p++ = 0; + } +} + +void crypto_prng_acquire(void) +{ + /* Don't check return code of Mutex::lock(void) + * + * This function treats RTOS errors as fatal system errors, so it can only return osOK. + * Use of the return value is deprecated, as the return is expected to become void in + * the future. + */ + crypto_prng_mutex->lock(); +} + +void crypto_prng_release(void) +{ + crypto_prng_mutex->unlock(); +} + +void crypto_aes_acquire(void) +{ + /* Don't check return code of Mutex::lock(void) */ + crypto_aes_mutex->lock(); +} + +void crypto_aes_release(void) +{ + crypto_aes_mutex->unlock(); +} + +void crypto_sha_acquire(void) +{ + /* Don't check return code of Mutex::lock(void) */ + crypto_sha_mutex->lock(); +} + +void crypto_sha_release(void) +{ + crypto_sha_mutex->unlock(); +} + +void crypto_ecc_acquire(void) +{ + /* Don't check return code of Mutex::lock(void) */ + crypto_ecc_mutex->lock(); +} + +void crypto_ecc_release(void) +{ + crypto_ecc_mutex->unlock(); +} + +void crypto_rsa_acquire(void) +{ + /* Don't check return code of Mutex::lock(void) */ + crypto_rsa_mutex->lock(); +} + +void crypto_rsa_release(void) +{ + crypto_rsa_mutex->unlock(); +} + +void crypto_prng_prestart(void) +{ + crypto_submodule_prestart(&crypto_prng_done); +} + +bool crypto_prng_wait(void) +{ + return crypto_prng_wait2(-1); +} + +bool crypto_prng_wait2(int32_t timeout_us) +{ + return crypto_submodule_wait(&crypto_prng_done, timeout_us); +} + +void crypto_aes_prestart(void) +{ + crypto_submodule_prestart(&crypto_aes_done); +} + +bool crypto_aes_wait(void) +{ + return crypto_aes_wait2(-1); +} + +bool crypto_aes_wait2(int32_t timeout_us) +{ + return crypto_submodule_wait(&crypto_aes_done, timeout_us); +} + +void crypto_sha_prestart(void) +{ + crypto_submodule_prestart(&crypto_sha_done); +} + +bool crypto_sha_wait(void) +{ + return crypto_sha_wait2(-1); +} + +bool crypto_sha_wait2(int32_t timeout_us) +{ + return crypto_submodule_wait(&crypto_sha_done, timeout_us); +} + +void crypto_ecc_prestart(void) +{ + crypto_submodule_prestart(&crypto_ecc_done); +} + +bool crypto_ecc_wait(void) +{ + return crypto_ecc_wait2(-1); +} + +bool crypto_ecc_wait2(int32_t timeout_us) +{ + return crypto_submodule_wait(&crypto_ecc_done, timeout_us); +} + +void crypto_rsa_prestart(void) +{ + crypto_submodule_prestart(&crypto_rsa_done); +} + +bool crypto_rsa_wait(void) +{ + return crypto_rsa_wait2(-1); +} + +bool crypto_rsa_wait2(int32_t timeout_us) +{ + return crypto_submodule_wait(&crypto_rsa_done, timeout_us); +} + +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */ + ((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */ + (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ +} + +/* Overlap cases + * + * 1. in_buff in front of out_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + * + * 2. out_buff in front of in_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size) +{ + uint32_t in = (uint32_t) in_buff; + uint32_t in_end = in + in_buff_size; + uint32_t out = (uint32_t) out_buff; + uint32_t out_end = out + out_buff_size; + + bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end); + + return overlap; +} + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done) +{ + *submodule_done = 0; + + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); +} + +static bool crypto_submodule_wait(volatile uint16_t *submodule_done, int32_t timeout_us) +{ + /* Translate indefinite to extremely large */ + if (timeout_us < 0) { + timeout_us = 0x7FFFFFFF; + } + + struct nu_countdown_ctx_s ctx; + nu_countdown_init(&ctx, timeout_us); + while (! *submodule_done) { + if (nu_countdown_expired(&ctx)) { + break; + } + } + nu_countdown_free(&ctx); + + /* Ensure while loop above and subsequent code are not reordered */ + __DSB(); + + if ((*submodule_done & NU_CRYPTO_DONE_OK)) { + /* Done with OK */ + return true; + } else if ((*submodule_done & NU_CRYPTO_DONE_ERR)) { + /* Done with error */ + return false; + } + + return false; +} + +/* Crypto interrupt handler */ +extern "C" void CRPT_IRQHandler() +{ + uint32_t intsts; + + /* PRNG */ + if ((intsts = PRNG_GET_INT_FLAG(CRPT)) != 0) { + /* Check interrupt flags */ + if (intsts & CRPT_INTSTS_PRNGIF_Msk) { + /* Done with OK */ + crypto_prng_done |= NU_CRYPTO_DONE_OK; + } else if (intsts & CRPT_INTSTS_PRNGEIF_Msk) { + /* Done with error */ + crypto_prng_done |= NU_CRYPTO_DONE_ERR; + } + /* Clear interrupt flag */ + PRNG_CLR_INT_FLAG(CRPT); + } + + /* AES */ + if ((intsts = AES_GET_INT_FLAG(CRPT)) != 0) { + /* Check interrupt flags */ + if (intsts & CRPT_INTSTS_AESIF_Msk) { + /* Done with OK */ + crypto_aes_done |= NU_CRYPTO_DONE_OK; + } else if (intsts & CRPT_INTSTS_AESEIF_Msk) { + /* Done with error */ + crypto_aes_done |= NU_CRYPTO_DONE_ERR; + } + /* Clear interrupt flag */ + AES_CLR_INT_FLAG(CRPT); + } + + /* SHA */ + if ((intsts = SHA_GET_INT_FLAG(CRPT)) != 0) { + /* Check interrupt flags */ + if (intsts & CRPT_INTSTS_HMACIF_Msk) { + /* Done with OK */ + crypto_sha_done |= NU_CRYPTO_DONE_OK; + } else if (intsts & CRPT_INTSTS_HMACEIF_Msk) { + /* Done with error */ + crypto_sha_done |= NU_CRYPTO_DONE_ERR; + } + /* Clear interrupt flag */ + SHA_CLR_INT_FLAG(CRPT); + } + + /* ECC */ + if ((intsts = ECC_GET_INT_FLAG(CRPT)) != 0) { + /* Check interrupt flags */ + if (intsts & CRPT_INTSTS_ECCIF_Msk) { + /* Done with OK */ + crypto_ecc_done |= NU_CRYPTO_DONE_OK; + } else if (intsts & CRPT_INTSTS_ECCEIF_Msk) { + /* Done with error */ + crypto_ecc_done |= NU_CRYPTO_DONE_ERR; + } + /* Clear interrupt flag */ + ECC_CLR_INT_FLAG(CRPT); + } + + /* RSA */ + if ((intsts = RSA_GET_INT_FLAG(CRPT)) != 0) { + /* Check interrupt flags */ + if (intsts & CRPT_INTSTS_RSAIF_Msk) { + /* Done with OK */ + crypto_rsa_done |= NU_CRYPTO_DONE_OK; + } else if (intsts & CRPT_INTSTS_RSAEIF_Msk) { + /* Done with error */ + crypto_rsa_done |= NU_CRYPTO_DONE_ERR; + } + /* Clear interrupt flag */ + RSA_CLR_INT_FLAG(CRPT); + } +} + +#endif /* #if defined(MBEDTLS_CONFIG_HW_SUPPORT) */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M460/crypto/crypto-misc.h new file mode 100644 index 0000000..4ccf03c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/crypto/crypto-misc.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CRYPTO_MISC_H +#define MBED_CRYPTO_MISC_H + +#include + +#if defined(MBEDTLS_CONFIG_HW_SUPPORT) + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init/Uninit crypto module */ +void crypto_init(void); +void crypto_uninit(void); + +/* Clear buffer to zero + * Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n); +void crypto_zeroize32(uint32_t *v, size_t n); + +/* Acquire/release ownership of crypto sub-module + * + * \note "acquire" is blocking until ownership is acquired + * + * \note "acquire"/"release" must be paired. + * + * \note Recursive "acquire" is allowed because the underlying synchronization + * primitive mutex supports it. + */ +void crypto_prng_acquire(void); +void crypto_prng_release(void); +void crypto_aes_acquire(void); +void crypto_aes_release(void); +void crypto_sha_acquire(void); +void crypto_sha_release(void); +void crypto_ecc_acquire(void); +void crypto_ecc_release(void); +void crypto_rsa_acquire(void); +void crypto_rsa_release(void); + +/* Flow control between crypto/xxx start and crypto/xxx ISR + * + * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. + * + * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction. + * + * On finish, return of crypto_xxx_wait indicates success or not: + * true if successful + * false if failed + * + * Example: Start AES H/W and wait for its finish + * crypto_aes_prestart(); + * AES_Start(); + * crypto_aes_wait(); + */ +void crypto_prng_prestart(void); +bool crypto_prng_wait(void); +bool crypto_prng_wait2(int32_t timeout_us); +void crypto_aes_prestart(void); +bool crypto_aes_wait(void); +bool crypto_aes_wait2(int32_t timeout_us); +void crypto_sha_prestart(void); +bool crypto_sha_wait(void); +bool crypto_sha_wait2(int32_t timeout_us); +void crypto_ecc_prestart(void); +bool crypto_ecc_wait(void); +bool crypto_ecc_wait2(int32_t timeout_us); +void crypto_rsa_prestart(void); +bool crypto_rsa_wait(void); +bool crypto_rsa_wait2(int32_t timeout_us); + + +/* Check if buffer can be used for crypto DMA. It has the following requirements: + * (1) Word-aligned buffer base address + * (2) Crypto submodule (AES, SHA, etc.) dependent buffer size alignment. Must be 2 power. + * (3) Located in 0x20000000-0x2FFFFFFF region + */ +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); + +/* Check if input/output buffers are overlapped */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size); + +#ifdef __cplusplus +} +#endif + +#endif /* #if defined(MBEDTLS_CONFIG_HW_SUPPORT) */ + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device.h b/targets/TARGET_NUVOTON/TARGET_M460/device.h new file mode 100644 index 0000000..d186676 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/M460.h b/targets/TARGET_NUVOTON/TARGET_M460/device/M460.h new file mode 100644 index 0000000..4b49dd9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/M460.h @@ -0,0 +1,815 @@ +/**************************************************************************//** + * @file M460.h + * @version V3.00 + * @brief M460 peripheral access layer header file. + * This file contains all the peripheral register's definitions, + * bits definitions and memory mapping for NuMicro M460 MCU. + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +/** + \mainpage NuMicro M460 Driver Reference Guide + * + * Introduction + * + * This user manual describes the usage of M460 Series MCU device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Important Notice + * + * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, + * any malfunction or failure of which may cause loss of human life, bodily injury or severe + * property damage. Such applications are deemed, "Insecure Usage". + * + * Insecure usage includes, but is not limited to: equipment for surgical implementation, + * atomic energy control instruments, airplane or spaceship instruments, the control or + * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal + * instruments, all types of safety devices, and other applications intended to support or + * sustain life. + * + * All Insecure Usage shall be made at customer's risk, and in the event that third parties + * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify + * the damages and liabilities thus incurred by Nuvoton. + * + * Please note that all data and specifications are subject to change without notice. All the + * trademarks of products and companies mentioned in this datasheet belong to their respective + * owners. + * + * Copyright Notice + * + * Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + */ +#ifndef __M460_H__ +#define __M460_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device Device CMSIS Definitions + Configuration of the Cortex-M4 Processor and Core Peripherals + @{ +*/ + +/** + * @details Interrupt Number Definition. + */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ + + /****** M460 Specific Interrupt Numbers ********************************************************/ + + BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ + IRC_IRQn = 1, /*!< Internal RC Interrupt */ + PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ + RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ + CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ + ISP_IRQn = 5, /*!< FMC ISP Interrupt */ + RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ + TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ + WDT_IRQn = 8, /*!< Watchdog timer Interrupt */ + WWDT_IRQn = 9, /*!< Window Watchdog timer Interrupt */ + EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ + EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ + EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ + GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ + GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ + GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ + GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ + GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ + GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ + QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ + SPI0_IRQn = 23, /*!< SPI0 Interrupt */ + BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ + EPWM0P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ + EPWM0P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ + EPWM0P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ + BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ + EPWM1P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ + EPWM1P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ + EPWM1P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ + TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ + TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ + TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ + TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ + UART0_IRQn = 36, /*!< UART 0 Interrupt */ + UART1_IRQn = 37, /*!< UART 1 Interrupt */ + I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ + PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */ + DAC_IRQn = 41, /*!< DAC Interrupt */ + EADC00_IRQn = 42, /*!< EADC00 Interrupt */ + EADC01_IRQn = 43, /*!< EADC01 Interrupt */ + ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ + ACMP23_IRQn = 45, /*!< Analog Comparator 2 and 3 Interrupt */ + EADC02_IRQn = 46, /*!< EADC02 Interrupt */ + EADC03_IRQn = 47, /*!< EADC03 Interrupt */ + UART2_IRQn = 48, /*!< UART2 Interrupt */ + UART3_IRQn = 49, /*!< UART3 Interrupt */ + QSPI1_IRQn = 50, /*!< QSPI1 Interrupt */ + SPI1_IRQn = 51, /*!< SPI1 Interrupt */ + SPI2_IRQn = 52, /*!< SPI2 Interrupt */ + USBD_IRQn = 53, /*!< USB device Interrupt */ + USBH_IRQn = 54, /*!< USB host Interrupt */ + USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ + BMC_IRQn = 56, /*!< BMC Interrupt */ + SPI5_IRQn = 57, /*!< SPI5 Interrupt */ + SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ + SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ + SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ + GPJ_IRQn = 61, /*!< GPIO Port J Interrupt */ + SPI3_IRQn = 62, /*!< SPI3 Interrupt */ + SPI4_IRQn = 63, /*!< SPI4 Interrupt */ + EMAC0_TXRX_IRQn = 66, /*!< Ethernet MAC 0 Interrupt */ + SDH0_IRQn = 64, /*!< Secure Digital Host Controller 0 Interrupt */ + USBD20_IRQn = 65, /*!< High Speed USB device Interrupt */ + I2S0_IRQn = 68, /*!< I2S0 Interrupt */ + I2S1_IRQn = 69, /*!< I2S1 Interrupt */ + SPI6_IRQn = 70, /*!< SPI6 Interrupt */ + CRPT_IRQn = 71, /*!< CRPT Interrupt */ + GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ + EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ + UART4_IRQn = 74, /*!< UART4 Interrupt */ + UART5_IRQn = 75, /*!< UART5 Interrupt */ + USCI0_IRQn = 76, /*!< USCI0 Interrupt */ + SPI7_IRQn = 77, /*!< SPI7 Interrupt */ + BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ + BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ + SPIM_IRQn = 80, /*!< SPIM Interrupt */ + CCAP_IRQn = 81, /*!< CCAP Interrupt */ + I2C2_IRQn = 82, /*!< I2C2 Interrupt */ + I2C3_IRQn = 83, /*!< I2C3 Interrupt */ + EQEI0_IRQn = 84, /*!< EQEI0 Interrupt */ + EQEI1_IRQn = 85, /*!< EQEI1 Interrupt */ + ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ + ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ + GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ + EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ + SDH1_IRQn = 90, /*!< Secure Digital Host Controller 1 Interrupt */ + PSIO_IRQn = 91, /*!< PSIO Interrupt */ + HSUSBH_IRQn = 92, /*!< High speed USB host Interrupt */ + USBOTG20_IRQn = 93, /*!< High speed USB OTG Interrupt */ + ECAP2_IRQn = 94, /*!< ECAP2 Interrupt */ + ECAP3_IRQn = 95, /*!< ECAP3 Interrupt */ + KPI_IRQn = 96, /*!< Keypad Interface Interrupt */ + HBI_IRQn = 97, /*!< HBI Interrupt */ + PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */ + UART8_IRQn = 99, /*!< UART8 Interrupt */ + UART9_IRQn = 100, /*!< UART9 Interrupt */ + TRNG_IRQn = 101, /*!< TRNG Interrupt */ + UART6_IRQn = 102, /*!< UART6 Interrupt */ + UART7_IRQn = 103, /*!< UART7 Interrupt */ + EADC10_IRQn = 104, /*!< EADC10 Interrupt */ + EADC11_IRQn = 105, /*!< EADC11 Interrupt */ + EADC12_IRQn = 106, /*!< EADC12 Interrupt */ + EADC13_IRQn = 107, /*!< EADC13 Interrupt */ + SPI8_IRQn = 108, /*!< SPI8 Interrupt */ + KS_IRQn = 109, /*!< Keystore Interrupt */ + GPI_IRQn = 110, /*!< GPIO Port I Interrupt */ + SPI9_IRQn = 111, /*!< SPI9 Interrupt */ + CANFD00_IRQn = 112, /*!< CANFD00 Interrupt */ + CANFD01_IRQn = 113, /*!< CANFD01 Interrupt */ + CANFD10_IRQn = 114, /*!< CANFD10 Interrupt */ + CANFD11_IRQn = 115, /*!< CANFD11 Interrupt */ + EQEI2_IRQn = 116, /*!< EQEI2 Interrupt */ + EQEI3_IRQn = 117, /*!< EQEI3 Interrupt */ + I2C4_IRQn = 118, /*!< I2C4 Interrupt */ + SPI10_IRQn = 119, /*!< SPI10 Interrupt */ + CANFD20_IRQn = 120, /*!< CANFD20 Interrupt */ + CANFD21_IRQn = 121, /*!< CANFD21 Interrupt */ + CANFD30_IRQn = 122, /*!< CANFD30 Interrupt */ + CANFD31_IRQn = 123, /*!< CANFD31 Interrupt */ + EADC20_IRQn = 124, /*!< EADC20 Interrupt */ + EADC21_IRQn = 125, /*!< EADC21 Interrupt */ + EADC22_IRQn = 126, /*!< EADC22 Interrupt */ + EADC23_IRQn = 127, /*!< EADC23 Interrupt */ +} +IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0201UL /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 4UL /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0UL /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1UL /*!< MPU present or not */ +#ifdef __FPU_PRESENT +#undef __FPU_PRESENT +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#else +#define __FPU_PRESENT 1UL /*!< FPU present or not */ +#endif + +/*@}*/ /* end of group CMSIS_Device */ + + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_M460.h" /* System include file */ +#include + + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Register definitions */ +/******************************************************************************/ + +#include "sys_reg.h" +#include "clk_reg.h" +#include "fmc_reg.h" +#include "gpio_reg.h" +#include "pdma_reg.h" +#include "timer_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" +#include "rtc_reg.h" +#include "epwm_reg.h" +#include "bpwm_reg.h" +#include "eqei_reg.h" +#include "ecap_reg.h" +#include "uart_reg.h" +#include "emac_reg.h" +#include "sc_reg.h" +#include "i2s_reg.h" +#include "spi_reg.h" +#include "qspi_reg.h" +#include "spim_reg.h" +#include "i2c_reg.h" +#include "uuart_reg.h" +#include "uspi_reg.h" +#include "ui2c_reg.h" +#include "canfd_reg.h" +#include "sdh_reg.h" +#include "ebi_reg.h" +#include "usbd_reg.h" +#include "hsusbd_reg.h" +#include "usbh_reg.h" +#include "hsusbh_reg.h" +#include "otg_reg.h" +#include "hsotg_reg.h" +#include "crc_reg.h" +#include "crypto_reg.h" +#include "trng_reg.h" +#include "eadc_reg.h" +#include "dac_reg.h" +#include "acmp_reg.h" +#include "ccap_reg.h" +#include "keystore_reg.h" +#include "kpi_reg.h" +#include "psio_reg.h" +#include "hbi_reg.h" +#include "bmc_reg.h" + +/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base + Memory Mapped Structure for Peripherals + @{ + */ +/* Peripheral and SRAM base address */ +#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */ + +#define TCM_BASE (PERIPH_BASE + 0xBE000) + +/*!< AHB peripherals */ +//HCLK +// CPU,CRC,EBI,EMC,FMC,PDMA,SD0,SD1,CRPT,SPIM,SRAM,HSUSBD, HSUSBH, USBH +#define SYS_BASE (PERIPH_BASE + 0x00000UL) +#define CLK_BASE (PERIPH_BASE + 0x00200UL) +#define NMI_BASE (PERIPH_BASE + 0x00300UL) +#define GPIOA_BASE (PERIPH_BASE + 0x04000UL) +#define GPIOB_BASE (PERIPH_BASE + 0x04040UL) +#define GPIOC_BASE (PERIPH_BASE + 0x04080UL) +#define GPIOD_BASE (PERIPH_BASE + 0x040C0UL) +#define GPIOE_BASE (PERIPH_BASE + 0x04100UL) +#define GPIOF_BASE (PERIPH_BASE + 0x04140UL) +#define GPIOG_BASE (PERIPH_BASE + 0x04180UL) +#define GPIOH_BASE (PERIPH_BASE + 0x041C0UL) +#define GPIOI_BASE (PERIPH_BASE + 0x04200UL) +#define GPIOJ_BASE (PERIPH_BASE + 0x04240UL) +#define GPIO_INT_BASE (PERIPH_BASE + 0x04450UL) +#define GPIO_PIN_DATA_BASE (PERIPH_BASE + 0x04800UL) +#define SPIM_BASE (PERIPH_BASE + 0x07000UL) +#define PDMA0_BASE (PERIPH_BASE + 0x08000UL) +#define PDMA1_BASE (PERIPH_BASE + 0x18000UL) +#define USBH_BASE (PERIPH_BASE + 0x09000UL) +#define HSUSBH_BASE (PERIPH_BASE + 0x1A000UL) +#define EMAC_BASE (PERIPH_BASE + 0x12000UL) +#define FMC_BASE (PERIPH_BASE + 0x0C000UL) +#define SDH0_BASE (PERIPH_BASE + 0x0D000UL) +#define SDH1_BASE (PERIPH_BASE + 0x0E000UL) +#define EBI_BASE (PERIPH_BASE + 0x10000UL) +#define HSUSBD_BASE (PERIPH_BASE + 0x19000UL) +#define CCAP_BASE (PERIPH_BASE + 0x30000UL) +#define CRC_BASE (PERIPH_BASE + 0x31000UL) +#define CRPT_BASE (PERIPH_BASE + 0x32000UL) +#define KS_BASE (PERIPH_BASE + 0x35000UL) +#define TAMPER_BASE (PERIPH_BASE + 0xE1000UL) +#define HBI_BASE (PERIPH_BASE + 0xCE000UL) +#define BMC_BASE (PERIPH_BASE + 0x1B000UL) + +//PCLK0 +// BPWM0,QSPI0,ECAP2,I2C0/2/4,I2S0,OPA,EPWM0,EQEI0/2,SC0/2,SPI1/3/5/7/9,TMR01,UR0/2/4/6/8,USBD,USCI0,WDT + +/*!< APB0 peripherals */ +#define WDT_BASE (PERIPH_BASE + 0x40000UL) +#define WWDT_BASE (PERIPH_BASE + 0x40100UL) +#define OPA_BASE (PERIPH_BASE + 0x46000UL) +#define I2S0_BASE (PERIPH_BASE + 0x48000UL) +#define EADC1_BASE (PERIPH_BASE + 0x4B000UL) +#define TIMER0_BASE (PERIPH_BASE + 0x50000UL) +#define TIMER1_BASE (PERIPH_BASE + 0x50100UL) +#define EPWM0_BASE (PERIPH_BASE + 0x58000UL) +#define BPWM0_BASE (PERIPH_BASE + 0x5A000UL) +#define QSPI0_BASE (PERIPH_BASE + 0x60000UL) +#define SPI1_BASE (PERIPH_BASE + 0x62000UL) +#define SPI3_BASE (PERIPH_BASE + 0x64000UL) +#define SPI5_BASE (PERIPH_BASE + 0x66000UL) +#define SPI7_BASE (PERIPH_BASE + 0x68000UL) +#define SPI9_BASE (PERIPH_BASE + 0x6C000UL) +#define UART0_BASE (PERIPH_BASE + 0x70000UL) +#define UART2_BASE (PERIPH_BASE + 0x72000UL) +#define UART4_BASE (PERIPH_BASE + 0x74000UL) +#define UART6_BASE (PERIPH_BASE + 0x76000UL) +#define UART8_BASE (PERIPH_BASE + 0x78000UL) +#define I2C0_BASE (PERIPH_BASE + 0x80000UL) +#define I2C2_BASE (PERIPH_BASE + 0x82000UL) +#define CANFD0_BASE (PERIPH_BASE + 0x20000UL) +#define CANFD2_BASE (PERIPH_BASE + 0x28000UL) +#define EQEI0_BASE (PERIPH_BASE + 0xB0000UL) +#define ECAP0_BASE (PERIPH_BASE + 0xB4000UL) +#define USCI0_BASE (PERIPH_BASE + 0xD0000UL) + + + +//PCLK1 +// ACMP01/23,EADC0/1/2,BPWM1,DAC,ECAP1/3,I2C1/3,I2S1,OTG,HSOTG,EPWM1,QEI1/3,RTC,SC1,SPI0/2/4/6/8/10,QSPI1,TMR23,UR1/3/5/7/9,PSIO + +/*!< APB1 peripherals */ +#define RTC_BASE (PERIPH_BASE + 0x41000UL) +#define EADC0_BASE (PERIPH_BASE + 0x43000UL) +#define ACMP01_BASE (PERIPH_BASE + 0x45000UL) +#define I2S1_BASE (PERIPH_BASE + 0x49000UL) +#define USBD_BASE (PERIPH_BASE + 0xC0000UL) +#define EADC1_BASE (PERIPH_BASE + 0x4B000UL) +#define OTG_BASE (PERIPH_BASE + 0x4D000UL) +#define HSOTG_BASE (PERIPH_BASE + 0x4F000UL) +#define TIMER2_BASE (PERIPH_BASE + 0x51000UL) +#define TIMER3_BASE (PERIPH_BASE + 0x51100UL) +#define EADC2_BASE (PERIPH_BASE + 0x97000UL) +#define EPWM1_BASE (PERIPH_BASE + 0x59000UL) +#define BPWM1_BASE (PERIPH_BASE + 0x5B000UL) +#define SPI0_BASE (PERIPH_BASE + 0x61000UL) +#define SPI2_BASE (PERIPH_BASE + 0x63000UL) +#define SPI4_BASE (PERIPH_BASE + 0x65000UL) +#define SPI6_BASE (PERIPH_BASE + 0x67000UL) +#define QSPI1_BASE (PERIPH_BASE + 0x69000UL) +#define SPI8_BASE (PERIPH_BASE + 0x6B000UL) +#define SPI10_BASE (PERIPH_BASE + 0x6D000UL) +#define UART1_BASE (PERIPH_BASE + 0x71000UL) +#define UART3_BASE (PERIPH_BASE + 0x73000UL) +#define UART5_BASE (PERIPH_BASE + 0x75000UL) +#define UART7_BASE (PERIPH_BASE + 0x77000UL) +#define UART9_BASE (PERIPH_BASE + 0x79000UL) +#define I2C1_BASE (PERIPH_BASE + 0x81000UL) +#define CANFD1_BASE (PERIPH_BASE + 0x24000UL) +#define CANFD3_BASE (PERIPH_BASE + 0x2C000UL) +#define EQEI1_BASE (PERIPH_BASE + 0xB1000UL) +#define ECAP1_BASE (PERIPH_BASE + 0xB5000UL) +#define TRNG_BASE (PERIPH_BASE + 0xB9000UL) +#define ECAP2_BASE (PERIPH_BASE + 0xB6000UL) +#define ECAP3_BASE (PERIPH_BASE + 0xB7000UL) +#define EQEI2_BASE (PERIPH_BASE + 0xB2000UL) +#define EQEI3_BASE (PERIPH_BASE + 0xB3000UL) +#define I2C3_BASE (PERIPH_BASE + 0x83000UL) +#define I2C4_BASE (PERIPH_BASE + 0x84000UL) +#define SC0_BASE (PERIPH_BASE + 0x90000UL) +#define SC1_BASE (PERIPH_BASE + 0x91000UL) +#define SC2_BASE (PERIPH_BASE + 0x92000UL) +#define DAC0_BASE (PERIPH_BASE + 0x47000UL) +#define DAC1_BASE (PERIPH_BASE + 0x47040UL) +#define DACDBG_BASE (PERIPH_BASE + 0x47FECUL) +#define OPA0_BASE (PERIPH_BASE + 0x46000UL) + +#define KPI_BASE (PERIPH_BASE + 0x0C2000UL) +#define PSIO_BASE (PERIPH_BASE + 0x0C3000UL) +#define ACMP23_BASE (PERIPH_BASE + 0x0C9000UL) + + + +/*@}*/ /* end of group PERIPHERAL_MEM_MAP */ + + +/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer + The Declaration of Peripherals + @{ + */ + +#define TCM ((TCM_T *) TCM_BASE) +#define SYS ((SYS_T *) SYS_BASE) +#define CLK ((CLK_T *) CLK_BASE) +#define NMI ((NMI_T *) NMI_BASE) +#define PA ((GPIO_T *) GPIOA_BASE) +#define PB ((GPIO_T *) GPIOB_BASE) +#define PC ((GPIO_T *) GPIOC_BASE) +#define PD ((GPIO_T *) GPIOD_BASE) +#define PE ((GPIO_T *) GPIOE_BASE) +#define PF ((GPIO_T *) GPIOF_BASE) +#define PG ((GPIO_T *) GPIOG_BASE) +#define PH ((GPIO_T *) GPIOH_BASE) +#define PI ((GPIO_T *) GPIOI_BASE) +#define PJ ((GPIO_T *) GPIOJ_BASE) +#define GPA ((GPIO_T *) GPIOA_BASE) +#define GPB ((GPIO_T *) GPIOB_BASE) +#define GPC ((GPIO_T *) GPIOC_BASE) +#define GPD ((GPIO_T *) GPIOD_BASE) +#define GPE ((GPIO_T *) GPIOE_BASE) +#define GPF ((GPIO_T *) GPIOF_BASE) +#define GPG ((GPIO_T *) GPIOG_BASE) +#define GPH ((GPIO_T *) GPIOH_BASE) +#define GPI ((GPIO_T *) GPIOI_BASE) +#define GPJ ((GPIO_T *) GPIOJ_BASE) +#define GPIO ((GPIO_INT_T *) GPIO_INT_BASE) +#define PDMA0 ((PDMA_T *) PDMA0_BASE) +#define PDMA1 ((PDMA_T *) PDMA1_BASE) +#define USBH ((USBH_T *) USBH_BASE) +#define HSUSBH ((HSUSBH_T *) HSUSBH_BASE) +#define EMAC ((EMAC_T *) EMAC_BASE) +#define FMC ((FMC_T *) FMC_BASE) +#define SDH0 ((SDH_T *) SDH0_BASE) +#define SDH1 ((SDH_T *) SDH1_BASE) +#define EBI ((EBI_T *) EBI_BASE) +#define CRC ((CRC_T *) CRC_BASE) +#define TAMPER ((TAMPER_T *) TAMPER_BASE) +#define KS ((KS_T *) KS_BASE) +#define HBI ((HBI_T *) HBI_BASE) +#define WDT ((WDT_T *) WDT_BASE) +#define WWDT ((WWDT_T *) WWDT_BASE) +#define RTC ((RTC_T *) RTC_BASE) +#define EADC0 ((EADC_T *) EADC0_BASE) +#define EADC1 ((EADC_T *) EADC1_BASE) +#define EADC2 ((EADC_T *) EADC2_BASE) +#define ACMP01 ((ACMP_T *) ACMP01_BASE) +#define ACMP23 ((ACMP_T *) ACMP23_BASE) +#define KPI ((KPI_T *) KPI_BASE) + +#define I2S0 ((I2S_T *) I2S0_BASE) +#define I2S1 ((I2S_T *) I2S1_BASE) +#define USBD ((USBD_T *) USBD_BASE) +#define OTG ((OTG_T *) OTG_BASE) +#define HSUSBD ((HSUSBD_T *)HSUSBD_BASE) +#define HSOTG ((HSOTG_T *) HSOTG_BASE) +#define TIMER0 ((TIMER_T *) TIMER0_BASE) +#define TIMER1 ((TIMER_T *) TIMER1_BASE) +#define TIMER2 ((TIMER_T *) TIMER2_BASE) +#define TIMER3 ((TIMER_T *) TIMER3_BASE) +#define EPWM0 ((EPWM_T *) EPWM0_BASE) +#define EPWM1 ((EPWM_T *) EPWM1_BASE) +#define BPWM0 ((BPWM_T *) BPWM0_BASE) +#define BPWM1 ((BPWM_T *) BPWM1_BASE) +#define ECAP0 ((ECAP_T *) ECAP0_BASE) +#define ECAP1 ((ECAP_T *) ECAP1_BASE) +#define ECAP2 ((ECAP_T *) ECAP2_BASE) +#define ECAP3 ((ECAP_T *) ECAP3_BASE) +#define EQEI0 ((EQEI_T *) EQEI0_BASE) +#define EQEI1 ((EQEI_T *) EQEI1_BASE) +#define EQEI2 ((EQEI_T *) EQEI2_BASE) +#define EQEI3 ((EQEI_T *) EQEI3_BASE) +#define QSPI0 ((QSPI_T *) QSPI0_BASE) +#define QSPI1 ((QSPI_T *) QSPI1_BASE) +#define SPI0 ((SPI_T *) SPI0_BASE) +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) +#define SPI4 ((SPI_T *) SPI4_BASE) +#define SPI5 ((SPI_T *) SPI5_BASE) +#define SPI6 ((SPI_T *) SPI6_BASE) +#define SPI7 ((SPI_T *) SPI7_BASE) +#define SPI8 ((SPI_T *) SPI8_BASE) +#define SPI9 ((SPI_T *) SPI9_BASE) +#define SPI10 ((SPI_T *) SPI10_BASE) +#define UART0 ((UART_T *) UART0_BASE) +#define UART1 ((UART_T *) UART1_BASE) +#define UART2 ((UART_T *) UART2_BASE) +#define UART3 ((UART_T *) UART3_BASE) +#define UART4 ((UART_T *) UART4_BASE) +#define UART5 ((UART_T *) UART5_BASE) +#define UART6 ((UART_T *) UART6_BASE) +#define UART7 ((UART_T *) UART7_BASE) +#define UART8 ((UART_T *) UART8_BASE) +#define UART9 ((UART_T *) UART9_BASE) +#define I2C0 ((I2C_T *) I2C0_BASE) +#define I2C1 ((I2C_T *) I2C1_BASE) +#define I2C2 ((I2C_T *) I2C2_BASE) +#define I2C3 ((I2C_T *) I2C3_BASE) +#define I2C4 ((I2C_T *) I2C4_BASE) +#define SC0 ((SC_T *) SC0_BASE) +#define SC1 ((SC_T *) SC1_BASE) +#define SC2 ((SC_T *) SC2_BASE) +#define CANFD0 ((CANFD_T *) CANFD0_BASE) +#define CANFD1 ((CANFD_T *) CANFD1_BASE) +#define CANFD2 ((CANFD_T *) CANFD2_BASE) +#define CANFD3 ((CANFD_T *) CANFD3_BASE) +#define CRPT ((CRPT_T *) CRPT_BASE) +#define TRNG ((TRNG_T *) TRNG_BASE) +#define SPIM ((volatile SPIM_T *) SPIM_BASE) +#define DAC0 ((DAC_T *) DAC0_BASE) +#define DAC1 ((DAC_T *) DAC1_BASE) +#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Configuration Struct */ +#define OPA ((OPA_T *) OPA_BASE) +#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Configuration Struct */ +#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Configuration Struct */ +#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Configuration Struct */ +#define CCAP ((CCAP_T *) CCAP_BASE) +#define PSIO ((PSIO_T *) PSIO_BASE) +#define BMC ((BMC_T *) BMC_BASE) + +/*@}*/ /* end of group ERIPHERAL_DECLARATION */ + +/** @addtogroup IO_ROUTINE I/O Routines + The Declaration of I/O Routines + @{ + */ + +typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type +typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type +typedef volatile unsigned int vu32; ///< Define 32-bit unsigned volatile data type + +/** + * @brief Get a 8-bit unsigned value from specified address + * @param[in] addr Address to get 8-bit data from + * @return 8-bit unsigned value stored in specified address + */ +#define M8(addr) (*((vu8 *) (addr))) + +/** + * @brief Get a 16-bit unsigned value from specified address + * @param[in] addr Address to get 16-bit data from + * @return 16-bit unsigned value stored in specified address + * @note The input address must be 16-bit aligned + */ +#define M16(addr) (*((vu16 *) (addr))) + +/** + * @brief Get a 32-bit unsigned value from specified address + * @param[in] addr Address to get 32-bit data from + * @return 32-bit unsigned value stored in specified address + * @note The input address must be 32-bit aligned + */ +#define M32(addr) (*((vu32 *) (addr))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outpw(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inpw(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outps(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inps(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outpb(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inpb(port) (*((volatile unsigned char *)(port))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outp32(port,value) *((volatile unsigned int *)(port)) = (value) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inp32(port) (*((volatile unsigned int *)(port))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outp16(port,value) *((volatile unsigned short *)(port)) = (value) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inp16(port) (*((volatile unsigned short *)(port))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outp8(port,value) *((volatile unsigned char *)(port)) = (value) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inp8(port) (*((volatile unsigned char *)(port))) + + +/*@}*/ /* end of group IO_ROUTINE */ + +/******************************************************************************/ +/* Legacy Constants */ +/******************************************************************************/ +/** @addtogroup Legacy_Constants Legacy Constants + Legacy Constants + @{ +*/ + +#ifndef NULL +#define NULL (0) ///< NULL pointer +#endif + +#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value +#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value + +#define ENABLE (1UL) ///< Enable, define to use in API parameters +#define DISABLE (0UL) ///< Disable, define to use in API parameters + +/* Define one bit mask */ +#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer +#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer +#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer +#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer +#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer +#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer +#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer +#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer +#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer +#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer +#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer +#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer +#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer +#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer +#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer +#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer +#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer +#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer +#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer +#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer +#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer +#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer +#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer +#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer +#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer +#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer +#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer +#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer +#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer +#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer +#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer +#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer +#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer +#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer +#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer + +#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + +/*@}*/ /* end of group Legacy_Constants */ + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "m460_sys.h" +#include "m460_clk.h" + +#include "m460_kpi.h" +#include "m460_rng.h" +#include "m460_keystore.h" +#include "m460_acmp.h" +#include "m460_dac.h" +#include "m460_uart.h" +#include "m460_usci_spi.h" +#include "m460_gpio.h" +#include "m460_ccap.h" +#include "m460_ecap.h" +#include "m460_hbi.h" +#include "m460_eqei.h" +#include "m460_timer.h" +#include "m460_timer_pwm.h" +#include "m460_pdma.h" +#include "m460_crypto.h" +#include "m460_trng.h" +#include "m460_fmc.h" +#include "m460_spim.h" +#include "m460_i2c.h" +#include "m460_i2s.h" +#include "m460_epwm.h" +#include "m460_eadc.h" +#include "m460_bpwm.h" +#include "m460_wdt.h" +#include "m460_wwdt.h" +#include "m460_crc.h" +#include "m460_ebi.h" +#include "m460_usci_i2c.h" +#include "m460_scuart.h" +#include "m460_sc.h" +#include "m460_spi.h" +#include "m460_qspi.h" +#include "m460_canfd.h" +#include "m460_rtc.h" +#include "m460_usci_uart.h" +#include "m460_sdh.h" +#include "m460_usbd.h" +#include "m460_hsusbd.h" +#include "m460_otg.h" +#include "m460_hsotg.h" +#include "m460_psio.h" +#include "m460_bmc.h" + + +#ifdef __cplusplus +} +#endif + +#endif /* __M460_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/M460_mem.h b/targets/TARGET_NUVOTON/TARGET_M460/device/M460_mem.h new file mode 100644 index 0000000..e2c8284 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/M460_mem.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __M460_MEM_H__ +#define __M460_MEM_H__ + +/* About M460_mem.h/M460_mem.icf.h + * + * 1. M460_mem.h is created for centralizing memory configuration. It will be included by C/C++ files + * and linker files (except IAR linker file). + * 2. IAR linker doesn't support preprocessor, so M460_mem.icf.h, duplicate of M460_mem.h + * is created for IAR linker file. + * 3. To continue above, we name M460_mem.icf.h instead of M460_mem.icf because: + * (1) Mbed OS build tool may mis-regard M460_mem.icf as the main linker configuration file. + * (2) *.icf files may not be present in search directories for "include" directive. Per observation, + * the search directories are inconsistent among normal example build and test code build. To address + * it, we name M460_mem.icf.h instead because *.h files are always present in these builds + * (already there or via copy). + */ + +/* Default memory specification + * + * Flash size: 1024KiB + * SRAM size: 512KiB + */ + +/* Resolve ROM start */ +#ifndef MBED_ROM_START +#define MBED_ROM_START (0x0) +#endif + +/* Resolve ROM size */ +#ifndef MBED_ROM_SIZE +#define MBED_ROM_SIZE (0x100000) +#endif + +/* Resolve RAM start */ +#ifndef MBED_RAM_START +#define MBED_RAM_START (0x20000000) +#endif + +/* Resolve RAM size */ +#ifndef MBED_RAM_SIZE +#define MBED_RAM_SIZE (0x80000) +#endif + + +/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just + * MBED_APP_xxx macros to linker files even though they mean the same thing. + * Because this file is to include by both C/C++ files and linker files, we add + * these macros according to the others for consistency when they are missing + * in compile or link stage. */ + +#ifndef APPLICATION_ADDR +#ifdef MBED_APP_START +#define APPLICATION_ADDR MBED_APP_START +#else +#define APPLICATION_ADDR MBED_ROM_START +#endif +#endif + +#ifndef APPLICATION_SIZE +#ifdef MBED_APP_SIZE +#define APPLICATION_SIZE MBED_APP_SIZE +#else +#define APPLICATION_SIZE MBED_ROM_SIZE +#endif +#endif + +#ifndef APPLICATION_RAM_ADDR +#ifdef MBED_RAM_APP_START +#define APPLICATION_RAM_ADDR MBED_RAM_APP_START +#else +#define APPLICATION_RAM_ADDR MBED_RAM_START +#endif +#endif + +#ifndef APPLICATION_RAM_SIZE +#ifdef MBED_RAM_APP_SIZE +#define APPLICATION_RAM_SIZE MBED_RAM_APP_SIZE +#else +#define APPLICATION_RAM_SIZE MBED_RAM_SIZE +#endif +#endif + +#ifndef MBED_APP_START +#define MBED_APP_START APPLICATION_ADDR +#endif + +#ifndef MBED_APP_SIZE +#define MBED_APP_SIZE APPLICATION_SIZE +#endif + +#ifndef MBED_RAM_APP_START +#define MBED_RAM_APP_START APPLICATION_RAM_ADDR +#endif + +#ifndef MBED_RAM_APP_SIZE +#define MBED_RAM_APP_SIZE APPLICATION_RAM_SIZE +#endif + +#if (APPLICATION_ADDR != MBED_APP_START) +#error("APPLICATION_ADDR and MBED_APP_START are not the same!!!") +#endif + +#if (APPLICATION_SIZE != MBED_APP_SIZE) +#error("APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!") +#endif + +#if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START) +#error("APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!") +#endif + +#if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE) +#error("APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!") +#endif + +#endif /* __M460_MEM_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/M460_mem.icf.h b/targets/TARGET_NUVOTON/TARGET_M460/device/M460_mem.icf.h new file mode 100644 index 0000000..35617da --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/M460_mem.icf.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* See M460_mem.h for documentation */ + +/* Default memory specification + * + * Flash size: 1024KiB + * SRAM size: 512KiB + */ + +/* Resolve ROM start */ +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x0; +} + +/* Resolve ROM size */ +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x100000; +} + +/* Resolve RAM start */ +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x20000000; +} + +/* Resolve RAM size */ +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x80000; +} + +/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just + * MBED_APP_xxx macros to linker files even though they mean the same thing. + * Because this file is to include by both C/C++ files and linker files, we add + * these macros according to the others for consistency when they are missing + * in compile or link stage. */ + +if (!isdefinedsymbol(APPLICATION_ADDR)) { + if (isdefinedsymbol(MBED_APP_START)) { + define symbol APPLICATION_ADDR = MBED_APP_START; + } else { + define symbol APPLICATION_ADDR = MBED_ROM_START; + } +} + +if (!isdefinedsymbol(APPLICATION_SIZE)) { + if (isdefinedsymbol(MBED_APP_SIZE)) { + define symbol APPLICATION_SIZE = MBED_APP_SIZE; + } else { + define symbol APPLICATION_SIZE = MBED_ROM_SIZE; + } +} + +if (!isdefinedsymbol(APPLICATION_RAM_ADDR)) { + if (isdefinedsymbol(MBED_RAM_APP_START)) { + define symbol APPLICATION_RAM_ADDR = MBED_RAM_APP_START; + } else { + define symbol APPLICATION_RAM_ADDR = MBED_RAM_START; + } +} + +if (!isdefinedsymbol(APPLICATION_RAM_SIZE)) { + if (isdefinedsymbol(MBED_RAM_APP_SIZE)) { + define symbol APPLICATION_RAM_SIZE = MBED_RAM_APP_SIZE; + } else { + define symbol APPLICATION_RAM_SIZE = MBED_RAM_SIZE; + } +} + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = APPLICATION_ADDR; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = APPLICATION_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_APP_START)) { + define symbol MBED_RAM_APP_START = APPLICATION_RAM_ADDR; +} + +if (!isdefinedsymbol(MBED_RAM_APP_SIZE)) { + define symbol MBED_RAM_APP_SIZE = APPLICATION_RAM_SIZE; +} + +if (APPLICATION_ADDR != MBED_APP_START) { + error "APPLICATION_ADDR and MBED_APP_START are not the same!!!"; +} + +if (APPLICATION_SIZE != MBED_APP_SIZE) { + error "APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!"; +} + +if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START) { + error "APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!"; +} + +if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE) { + error "APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!"; +} diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/NuMicro.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/NuMicro.h new file mode 100644 index 0000000..3bdc351 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/NuMicro.h @@ -0,0 +1,16 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "M460.h" + +#endif /* __NUMICRO_H__ */ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/acmp_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/acmp_reg.h new file mode 100644 index 0000000..daedf48 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/acmp_reg.h @@ -0,0 +1,617 @@ +/**************************************************************************//** + * @file acmp_reg.h + * @version V1.00 + * @brief ACMP register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ACMP_REG_H__ +#define __ACMP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Analog Comparator Controller -------------------------*/ +/** + @addtogroup ACMP Analog Comparator Controller(ACMP) + Memory Mapped Structure for ACMP Controller +@{ */ + +typedef struct +{ + + +/** + * @var ACMP_T::CTL0 + * Offset: 0x00 Analog Comparator 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator 0 Disabled. + * | | |1 = Comparator 0 Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator 0 interrupt Disabled. + * | | |1 = Comparator 0 interrupt Enabled + * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[2] |HYSEN |Comparator Hysteresis Enable Bit + * | | |0 = Comparator 0 hysteresis Disabled. + * | | |1 = Comparator 0 hysteresis Enabled. + * | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL. + * | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysterresis is fixed to 30mV. + * |[3] |ACMPOINV |Comparator Output Inverse + * | | |0 = Comparator 0 output inverse Disabled. + * | | |1 = Comparator 0 output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMP0_N pin. + * | | |01 = Internal comparator reference voltage (CRV0). + * | | |10 = Band-gap voltage. + * | | |11 = DAC0 output. + * | | |Note: NEGSEL must select 2u2019b01 in calibration mode. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMP0_P0. + * | | |01 = Input from ACMP0_P1. + * | | |10 = Input from ACMP0_P2. + * | | |11 = Input from ACMP0_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output. + * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMP0 output is sampled 1 consecutive PCLK. + * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs. + * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs. + * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs. + * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs. + * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs. + * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[21:20] |FCLKDIV |Comparator Output Filter Clock Divider + * | | |00 = cComparator output filter clock = PCLK + * | | |01 = cComparator output filter clock = PCLK/2 + * | | |10 = cComparator output filter clock = PCLK/4 + * | | |11 = Reserved + * | | |Note: uUse FCLKDIV must under the condition fof FILTSEL = 3u2019h7, then set FCLKDIV canto get the effect of filtering 128,256 consecutive PCLKs. + * |[26:24] |HYSSEL |Hysteresis Mode Selection + * | | |000 = Hysteresis is 0mV. + * | | |001 = Hysteresis is 10mV. + * | | |010 = Hysteresis is 20mV. + * | | |011 = Hysteresis is 30mV. + * | | |100 = Hysteresis is 40mV + * | | |101 = Hysteresis is 50mV + * | | |Others = rReserved + * |[29:28] |MODESEL |Comparator Power Mode Selection + * | | |00 = low power mode comparator AVDD current 1uA + * | | |01 = low power mode comparator AVDD current 2uA + * | | |10 = active mode comparator AVDD current 35uA + * | | |11 = active mode comparator AVDD current 70uA + * @var ACMP_T::CTL1 + * Offset: 0x04 Analog Comparator 1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator 1 Disabled. + * | | |1 = Comparator 1 Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator 1 interrupt Disabled. + * | | |1 = Comparator 1 interrupt Enabled + * | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[2] |HYSEN |Comparator Hysteresis Enable Bit + * | | |0 = Comparator 1 hysteresis Disabled. + * | | |1 = Comparator 1 hysteresis Enabled. + * | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL. + * | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysterresis is fixed to 30mV. + * |[3] |ACMPOINV |Comparator Output Inverse Control + * | | |0 = Comparator 1 output inverse Disabled. + * | | |1 = Comparator 1 output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMP1_N pin. + * | | |01 = Internal comparator reference voltage (CRV1). + * | | |10 = Band-gap voltage. + * | | |11 = DAC0 output. + * | | |Note: NEGSEL must select 2u2019b01 in calibration mode. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMP1_P0. + * | | |01 = Input from ACMP1_P1. + * | | |10 = Input from ACMP1_P2. + * | | |11 = Input from ACMP1_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output. + * | | |1 = Comparator 1 output to ACMP1_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMP1 output is sampled 1 consecutive PCLK. + * | | |010 = ACMP1 output is sampled 2 consecutive PCLKs. + * | | |011 = ACMP1 output is sampled 4 consecutive PCLKs. + * | | |100 = ACMP1 output is sampled 8 consecutive PCLKs. + * | | |101 = ACMP1 output is sampled 16 consecutive PCLKs. + * | | |110 = ACMP1 output is sampled 32 consecutive PCLKs. + * | | |111 = ACMP1 output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wakeup Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[21:20] |FCLKDIV |Comparator Output Filter Clock Divider + * | | |00 = comparator output filter clock = PCLK + * | | |01 = comparator output filter clock = PCLK/2 + * | | |10 = comparator output filter clock = PCLK/4 + * | | |11 = Reserved + * |[26:24] |HYSSEL |Hysteresis Mode Selection + * | | |000 = Hysteresis is 0mV. + * | | |001 = Hysteresis is 10mV. + * | | |010 = Hysteresis is 20mV. + * | | |011 = Hysteresis is 30mV. + * | | |100 = Hysteresis is 40mV + * | | |101 = Hysteresis is 50mV + * | | |Others = rReserved00 = Hysteresis is 0mV. + * | | |01 = Hysteresis is 10mV. + * | | |10 = Hysteresis is 20mV. + * | | |11 = Hysteresis is 30mV. + * |[29:28] |MODESEL |Comparator Power Mode Selection + * | | |00 = low power mode comparator AVDD current 1uA + * | | |01 = low power mode comparator AVDD current 2uA + * | | |10 = active mode comparator AVDD current 35uA + * | | |11 = active mode comparator AVDD current 70uA + * @var ACMP_T::STATUS + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output + * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output + * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |ACMPO0 |Comparator 0 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[5] |ACMPO1 |Comparator 1 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |ACMPS0 |Comparator 0 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[13] |ACMPS1 |Comparator 1 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[16] |ACMPWO |Comparator Window Output + * | | |This bit shows the output status of window compare mode + * | | |0 = The positive input voltage is outside the window. + * | | |1 = The positive input voltage is in the window. + * @var ACMP_T::VREF + * Offset: 0x0C Analog Comparator Reference Voltage Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CRV0SEL |Comparator0Comparator 0 Reference Voltage Setting + * | | |CRV0 = CRV0 source voltage * (ACMP_VREF01[5:0] )/ 631/6+CRVCTL/24). + * |[6] |CRV0SSEL |CRV0 Source Voltage Selection + * | | |0 = AVDD is selected as CRV0 source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV0 source voltage. + * |[8] |CRV0EN |CRV0 Enable Bit + * | | |0 = CRV0 is dDisabled. + * | | |1 = CRV0 is eEnabled. + * |[21:16] |CRV1SEL |Comparator1Comparator 1 Reference Voltage Setting + * | | |CRV1 = CRV1 source voltage * (ACMP_VREF01[21:16] )/ 63. + * |[22] |CRV1SSEL |CRV1 Source Voltage Selection + * | | |0 = AVDD is selected as CRV1 source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV1 source voltage. + * |[24] |CRV1EN |CRV1 Enable Bit + * | | |0 = CRV1 is dDisabled. + * | | |1 = CRV1 Eis enabled. + * |[31] |CLAMPEN |Current Level Control Selection under Speed Up Function + * | | |0 = ACMP run on high SPEED mode with high quiescent current + * | | |1 = ACMP run on low SPEED mode with high quiescent current + * | | |Note: Comparator speed up function only support SPEED[1:0]=2bu201911 & 2bu201910 + * @var ACMP_T::CALCTL + * Offset: 0x10 Analog Comparator Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CALTRG0 |Comparator0Comparator 0 Calibration Trigger Bit + * | | |0 = Calibration is stopped. + * | | |1 = Calibration is triggered. + * | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL0[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. + * | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. + * | | |Note 3: If user must trigger calibration twice or more times, the second trigger haves to wait at least 300us after the previous calibration is done. + * |[1] |CALTRG1 |Comparator1Comparator 1 Calibration Trigger Bit + * | | |0 = Calibration is stopped. + * | | |1 = Calibration is triggered. + * | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL1[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. + * | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. + * | | |Note 3: If user must trigger calibration twice or more times, the second trigger haves to wait at least 300us after the previous calibration is done. + * |[5:4] |CALCLK0 |Comparator0Comparator 0 Calibration Clock Rate Selection + * | | |00 = 1.5 kHz. + * | | |01 = 6 kHz. + * | | |10 = 24kHz. + * | | |11 = 95 kHz. + * |[7:6] |CALCLK1 |Comparator1Comparator 1 Calibration Clock Rate Selection + * | | |00 = 1.5 kHz. + * | | |01 = 6 kHz. + * | | |10 = 24kHz. + * | | |11 = 95 kHz. + * |[8] |OFFSETSEL |Comparator Trim Code Selection + * | | |0 = calibration trim code will not minus 1 when calibrated done. + * | | |1 = calibration trim code will not minus 1 when calibrated done. + * |[17:16] |CALRVS |Calibration Reference Voltage Selection + * | | |00 = option0 (N-pair calibration: 5V - 80mV, P-pair calibration: 80mV) + * | | |01 = option1 + * | | |10 = option2 (N-pair calibration: 5V - 160mV, P-pair calibration: 160mV) + * | | |11 = Reserved + * | | |Note: CRV0 and CRV1 must be the same setting in calibration + * | | |Note: The details refer to Analog ACMP SPEC + * @var ACMP_T::CALSTS + * Offset: 0x14 Analog Comparator Calibration Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DONE0 |Comparator 0 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Ddone. + * | | |NOTE: this bit is write 1 clear + * |[4] |DONE1 |Comparator 1 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Ddone. + * | | |NOTE: this bit is write 1 clear + * @var ACMP_T::COFF + * Offset: 0xFF0 Analog Comparator Calibration Offset Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |NCODE0 |Comparator0Comparator 0 Offset of NMOS + * | | |ACMP0 offset canceling trim code of NMOS + * | | |Note: 1. Once ACMP0 is enabled, reading these bits will gets initial value from ROMMAP46[19:16] + * | | |2. write MODESEL ACMP_CTL0[29:28] will decide NCODE0 load from which ROMMAP + * | | | MODESEL = 2u2019b00, NCODE0 load from ROMMAP46[3:0] + * | | | MODESEL = 2u2019b01, NCODE0 load from ROMMAP46[19:16] + * | | | MODESEL = 2u2019b10, NCODE0 load from ROMMAP47[3:0] + * | | | MODESEL = 2u2019b11, NCODE0 load from ROMMAP47[19:16] + * |[7] |NSEL0 |Comparator0Comparator 0 Offset of NMOS + * | | |0 = trim NMOS negative offset + * | | |1 = trim NMOS positive offset + * | | |Note: 1. Once ACMP0 is enabled, reading this bit default will get initial value from ROMMAP46[20] + * | | | 2. write MODESEL ACMP_CTL0[29:28] will decide NSEL0 load from which ROMMAP + * | | | MODESEL = 2u2019b00, NSEL0 load from ROMMAP46[4] + * | | | MODESEL = 2u2019b01, NSEL0 load from ROMMAP46[20] + * | | | MODESEL = 2u2019b10, NSEL0 load from ROMMAP47[4] + * | | | MODESEL = 2u2019b11, NSEL0 load from ROMMAP47[20] + * | | |2 + * | | |If ACMP0 is enabled and CALTRG0 (ACMP_CALCTL01[0]]) is set, after calibration done DONE0(ACMP_CALSRTS01[0]) will get NSEL0 value + * |[11:8] |PCODE0 |Comparator0Comparator 0 Offset of PMOS + * | | |ACMP0 offset canceling trim code of PMOS + * | | |Note: 1. Once ACMP0 is enabled, reading these bits default will get initial value from ROMMAP46[27:24] + * | | |2. write MODESEL ACMP_CTL0[29:28] will decide PCODE0 load from which ROMMAP + * | | | MODESEL = 2u2019b00, PCODE0 load from ROMMAP46[11:8] + * | | | MODESEL = 2u2019b01, PCODE0 load from ROMMAP46[27:24] + * | | | MODESEL = 2u2019b10, PCODE0 load from ROMMAP47[11:8] + * | | | MODESEL = 2u2019b11, PCODE0 load from ROMMAP47[27:24] + * |[15] |PSEL0 |Comparator0Comparator 0 Offset of PMOS + * | | |0 = trim PMOS negative offset + * | | |1 = trim PMOS positive offset + * | | |Note: 1. Once ACMP0 is enabled, reading this bit default will get initial value from ROMMAP46[28]. + * | | |2. write MODESEL ACMP_CTL0[29:28] will decide PSEL0 load from which ROMMAP + * | | | MODESEL = 2u2019b00, PSEL0 load from ROMMAP46[12] + * | | | MODESEL = 2u2019b01, PSEL0 load from ROMMAP48[28] + * | | | MODESEL = 2u2019b10, PSEL0 load from ROMMAP47[12] + * | | | MODESEL = 2u2019b11, PSEL0 load from ROMMAP47[28] + * | | |3 + * | | |If ACMP0 is enabled and CALTRG0 (ACMP_CALCTL01[0]]) is set, after calibration done DONE0(ACMP_CALSACMP_CALSTS01R[0]) will get PSEL0 value + * |[19:16] |NCODE1 |Comparator 1 Offset of NMOS + * | | |ACMP1 offset canceling trim code of PMOS + * | | |Note: 1. Once ACMP1 is enabled, reading these bits default will get initial value from ROMMAP48[19:16] + * | | |2. write MODESEL ACMP_CTL1[29:28] will decide NCODE1 load from which ROMMAP + * | | | MODESEL = 2u2019b00, NCODE1load from ROMMAP48[3:0] + * | | | MODESEL = 2u2019b01, NCODE1 load from ROMMAP48[19:16] + * | | | MODESEL = 2u2019b10, NCODE1 load from ROMMAP49[3:0] + * | | | MODESEL = 2u2019b11, NCODE1 load from ROMMAP49[19:16] + * |[23] |NSEL1 |Comparator 1 Offset of NMOS + * | | |0 = trim NMOS negative offset + * | | |1 = trim NMOS positive offset + * | | |Note: 1. Once ACMP1 is enabled, reading this bit default will get initial value from ROMMAP48[20] + * | | | 2. write MODESEL ACMP_CTL1[29:28] will decide NSEL1 load from which ROMMAP + * | | | MODESEL = 2u2019b00, NSEL1 load from ROMMAP48[4] + * | | | MODESEL = 2u2019b01, NSEL1 load from ROMMAP48[20] + * | | | MODESEL = 2u2019b10, NSEL1 load from ROMMAP49[4] + * | | | MODESEL = 2u2019b11, NSEL1 load from ROMMAP49[20] + * | | |3 + * | | |If ACMP1 is enabled and CALTRG1 (ACMP_CALCTL01[1]]) is set, after calibration done DONE1(ACMP_CALSRTS01[4]) will get NSEL1 value + * |[27:24] |PCODE1 |Comparator 1 Offset of PMOS + * | | |ACMP1 offset canceling trim code of PMOS + * | | |Note: 1. Once ACMP1 is enabled, reading these bits default will get initial value from ROMMAP48[27:24] + * | | |2. write MODESEL ACMP_CTL1[29:28] will decide PCODE1 load from which ROMMAP + * | | | MODESEL = 2u2019b00, PCODE1 load from ROMMAP48[11:8] + * | | | MODESEL = 2u2019b01, PCODE1 load from ROMMAP48[27:24] + * | | | MODESEL = 2u2019b10, PCODE1 load from ROMMAP49[11:8] + * | | | MODESEL = 2u2019b11, PCODE1 load from ROMMAP49[27:24] + * |[31] |PSEL1 |Comparator 1 Offset of PMOS + * | | |0 = trim PMOS negative offset + * | | |1 = trim PMOS positive offset + * | | |Note: 1. Once ACMP1 is enabled, reading this bit default will get initial value from ROMMAP48[28] + * | | | 2. write MODESEL ACMP_CTL1[29:28] will decide PSEL1 load from which ROMMAP + * | | | MODESEL = 2u2019b00, PSEL1 load from ROMMAP48[12] + * | | | MODESEL = 2u2019b01, PSEL1 load from ROMMAP48[28] + * | | | MODESEL = 2u2019b10, PSEL1 load from ROMMAP49[12] + * | | | MODESEL = 2u2019b11, PSEL1 load from ROMMAP49[28] + * | | |3 + * | | |If ACMP1 is enabled and CALTRG1 (ACMP_CALCTL01[1]]) is set, after calibration done DONE1(ACMP_CALSRTS01[4]) will get PSEL1 value + * @var ACMP_T::TEST + * Offset: 0xFF8 Analog Comparator Test Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRV0TEST |CRV0 Test Mode Enable Bit (Write Protect) + * | | |0 = No effect. + * | | |1 = CRV voltage output to ACMP0_N pin for voltage measure. + * | | |This bit is designed for Nuvoton Lab use only. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: NEGSEL (ACMP_CTL0[5:4]) or NEGSEL (ACMP_CTL1[5:4]) must select to 2u2019b01 in CRV test mode + * |[1] |CRV1TEST |CRV1 Test Mode Enable Bit (Write Protect) + * | | |0 = No effect. + * | | |1 = CRV voltage output to ACMP0_N pin for voltage measure. + * | | |This bit is designed for Nuvoton Lab use only. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: NEGSEL (ACMP_CTL0[5:4]) or NEGSEL (ACMP_CTL1[5:4]) must select to 2u2019b01 in CRV test mode + * |[4] |OUTSEL |Comparator CRV Output Source Selection + * | | |0 = CRV output from resistor string + * | | |1 = CRV output from bandgap voltage + * |[8] |HYSBYPASS |Hysteresis Adjust Function Selection + * | | |0 = Enable adjust function + * | | |1 = Bypass adjust function + * @var ACMP_T::VERSION + * Offset: 0xFFC Analog Comparator RTL Design Version Number + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MINOR |Comp RTL Design MINOR Version Number + * | | |Minor version number is dependent on module ECO version control. + * |[23:16] |SUB |Comp RTL Design SUB Version Number + * | | |Major version number is correlated to Product Line. + * |[31:24] |MAJOR |Comp RTL Design MAJOR Version Number + * | | |Major version number is correlated to Product Line. + */ + __IO uint32_t CTL[2]; /*!< [0x0000-0x0004] Analog Comparator 0/1 Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ + __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ + __IO uint32_t CALCTL; /*!< [0x0010] Analog Comparator Calibration Control Register */ + __IO uint32_t CALSTS; /*!< [0x0014] Analog Comparator Calibration Status Register */ + __I uint32_t RESERVE0[1014]; + __IO uint32_t COFF; /*!< [0x0ff0] Analog Comparator Calibration Offset Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t TEST; /*!< [0x0ff8] Analog Comparator Test Control Register */ + __I uint32_t VERSION; /*!< [0x0ffc] Analog Comparator RTL Design Version Number */ + +} ACMP_T; + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller +@{ */ + +#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL0: ACMPEN Position */ +#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL0: ACMPEN Mask */ + +#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL0: ACMPIE Position */ +#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL0: ACMPIE Mask */ + +#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL0: HYSEN Position */ +#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL0: HYSEN Mask */ + +#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL0: ACMPOINV Position */ +#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL0: ACMPOINV Mask */ + +#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL0: NEGSEL Position */ +#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL0: NEGSEL Mask */ + +#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL0: POSSEL Position */ +#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL0: POSSEL Mask */ + +#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL0: INTPOL Position */ +#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL0: INTPOL Mask */ + +#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL0: OUTSEL Position */ +#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL0: OUTSEL Mask */ + +#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL0: FILTSEL Position */ +#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL0: FILTSEL Mask */ + +#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL0: WKEN Position */ +#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL0: WKEN Mask */ + +#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL0: WLATEN Position */ +#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL0: WLATEN Mask */ + +#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL0: WCMPSEL Position */ +#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL0: WCMPSEL Mask */ + +#define ACMP_CTL_FCLKDIV_Pos (20) /*!< ACMP_T::CTL0: FCLKDIV Position */ +#define ACMP_CTL_FCLKDIV_Msk (0x3ul << ACMP_CTL_FCLKDIV_Pos) /*!< ACMP_T::CTL0: FCLKDIV Mask */ + +#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL0: HYSSEL Position */ +#define ACMP_CTL_HYSSEL_Msk (0x7ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL0: HYSSEL Mask */ + +#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL0: MODESEL Position */ +#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL0: MODESEL Mask */ + +#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ +#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ + +#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ +#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ + +#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ +#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ + +#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ +#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ + +#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ +#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ + +#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ +#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ + +#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ +#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ + +#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ +#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ + +#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ +#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ + +#define ACMP_VREF_CRV0SEL_Pos (0) /*!< ACMP_T::VREF: CRV0SEL Position */ +#define ACMP_VREF_CRV0SEL_Msk (0x3ful << ACMP_VREF_CRV0SEL_Pos) /*!< ACMP_T::VREF: CRV0SEL Mask */ + +#define ACMP_VREF_CRV0SSEL_Pos (6) /*!< ACMP_T::VREF: CRV0SSEL Position */ +#define ACMP_VREF_CRV0SSEL_Msk (0x1ul << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_T::VREF: CRV0SSEL Mask */ + +#define ACMP_VREF_CRV0EN_Pos (8) /*!< ACMP_T::VREF: CRV0EN Position */ +#define ACMP_VREF_CRV0EN_Msk (0x1ul << ACMP_VREF_CRV0EN_Pos) /*!< ACMP_T::VREF: CRV0EN Mask */ + +#define ACMP_VREF_CRV1SEL_Pos (16) /*!< ACMP_T::VREF: CRV1SEL Position */ +#define ACMP_VREF_CRV1SEL_Msk (0x3ful << ACMP_VREF_CRV1SEL_Pos) /*!< ACMP_T::VREF: CRV1SEL Mask */ + +#define ACMP_VREF_CRV1SSEL_Pos (22) /*!< ACMP_T::VREF: CRV1SSEL Position */ +#define ACMP_VREF_CRV1SSEL_Msk (0x1ul << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_T::VREF: CRV1SSEL Mask */ + +#define ACMP_VREF_CRV1EN_Pos (24) /*!< ACMP_T::VREF: CRV1EN Position */ +#define ACMP_VREF_CRV1EN_Msk (0x1ul << ACMP_VREF_CRV1EN_Pos) /*!< ACMP_T::VREF: CRV1EN Mask */ + +#define ACMP_VREF_CLAMPEN_Pos (31) /*!< ACMP_T::VREF: CLAMPEN Position */ +#define ACMP_VREF_CLAMPEN_Msk (0x1ul << ACMP_VREF_CLAMPEN_Pos) /*!< ACMP_T::VREF: CLAMPEN Mask */ + +#define ACMP_CALCTL_CALTRG0_Pos (0) /*!< ACMP_T::CALCTL: CALTRG0 Position */ +#define ACMP_CALCTL_CALTRG0_Msk (0x1ul << ACMP_CALCTL_CALTRG0_Pos) /*!< ACMP_T::CALCTL: CALTRG0 Mask */ + +#define ACMP_CALCTL_CALTRG1_Pos (1) /*!< ACMP_T::CALCTL: CALTRG1 Position */ +#define ACMP_CALCTL_CALTRG1_Msk (0x1ul << ACMP_CALCTL_CALTRG1_Pos) /*!< ACMP_T::CALCTL: CALTRG1 Mask */ + +#define ACMP_CALCTL_CALCLK0_Pos (4) /*!< ACMP_T::CALCTL: CALCLK0 Position */ +#define ACMP_CALCTL_CALCLK0_Msk (0x3ul << ACMP_CALCTL_CALCLK0_Pos) /*!< ACMP_T::CALCTL: CALCLK0 Mask */ + +#define ACMP_CALCTL_CALCLK1_Pos (6) /*!< ACMP_T::CALCTL: CALCLK1 Position */ +#define ACMP_CALCTL_CALCLK1_Msk (0x3ul << ACMP_CALCTL_CALCLK1_Pos) /*!< ACMP_T::CALCTL: CALCLK1 Mask */ + +#define ACMP_CALCTL_OFFSETSEL_Pos (8) /*!< ACMP_T::CALCTL: OFFSETSEL Position */ +#define ACMP_CALCTL_OFFSETSEL_Msk (0x1ul << ACMP_CALCTL_OFFSETSEL_Pos) /*!< ACMP_T::CALCTL: OFFSETSEL Mask */ + +#define ACMP_CALCTL_CALRVS_Pos (16) /*!< ACMP_T::CALCTL: CALRVS Position */ +#define ACMP_CALCTL_CALRVS_Msk (0x3ul << ACMP_CALCTL_CALRVS_Pos) /*!< ACMP_T::CALCTL: CALRVS Mask */ + +#define ACMP_CALSTS_DONE0_Pos (0) /*!< ACMP_T::CALSTS: DONE0 Position */ +#define ACMP_CALSTS_DONE0_Msk (0x1ul << ACMP_CALSTS_DONE0_Pos) /*!< ACMP_T::CALSTS: DONE0 Mask */ + +#define ACMP_CALSTS_DONE1_Pos (4) /*!< ACMP_T::CALSTS: DONE1 Position */ +#define ACMP_CALSTS_DONE1_Msk (0x1ul << ACMP_CALSTS_DONE1_Pos) /*!< ACMP_T::CALSTS: DONE1 Mask */ + +#define ACMP_COFF_NCODE0_Pos (0) /*!< ACMP_T::COFF: NCODE0 Position */ +#define ACMP_COFF_NCODE0_Msk (0xful << ACMP_COFF_NCODE0_Pos) /*!< ACMP_T::COFF: NCODE0 Mask */ + +#define ACMP_COFF_NSEL0_Pos (7) /*!< ACMP_T::COFF: NSEL0 Position */ +#define ACMP_COFF_NSEL0_Msk (0x1ul << ACMP_COFF_NSEL0_Pos) /*!< ACMP_T::COFF: NSEL0 Mask */ + +#define ACMP_COFF_PCODE0_Pos (8) /*!< ACMP_T::COFF: PCODE0 Position */ +#define ACMP_COFF_PCODE0_Msk (0xful << ACMP_COFF_PCODE0_Pos) /*!< ACMP_T::COFF: PCODE0 Mask */ + +#define ACMP_COFF_PSEL0_Pos (15) /*!< ACMP_T::COFF: PSEL0 Position */ +#define ACMP_COFF_PSEL0_Msk (0x1ul << ACMP_COFF_PSEL0_Pos) /*!< ACMP_T::COFF: PSEL0 Mask */ + +#define ACMP_COFF_NCODE1_Pos (16) /*!< ACMP_T::COFF: NCODE1 Position */ +#define ACMP_COFF_NCODE1_Msk (0xful << ACMP_COFF_NCODE1_Pos) /*!< ACMP_T::COFF: NCODE1 Mask */ + +#define ACMP_COFF_NSEL1_Pos (23) /*!< ACMP_T::COFF: NSEL1 Position */ +#define ACMP_COFF_NSEL1_Msk (0x1ul << ACMP_COFF_NSEL1_Pos) /*!< ACMP_T::COFF: NSEL1 Mask */ + +#define ACMP_COFF_PCODE1_Pos (24) /*!< ACMP_T::COFF: PCODE1 Position */ +#define ACMP_COFF_PCODE1_Msk (0xful << ACMP_COFF_PCODE1_Pos) /*!< ACMP_T::COFF: PCODE1 Mask */ + +#define ACMP_COFF_PSEL1_Pos (31) /*!< ACMP_T::COFF: PSEL1 Position */ +#define ACMP_COFF_PSEL1_Msk (0x1ul << ACMP_COFF_PSEL1_Pos) /*!< ACMP_T::COFF: PSEL1 Mask */ + +#define ACMP_TEST_CRV0TEST_Pos (0) /*!< ACMP_T::TEST: CRV0TEST Position */ +#define ACMP_TEST_CRV0TEST_Msk (0x1ul << ACMP_TEST_CRV0TEST_Pos) /*!< ACMP_T::TEST: CRV0TEST Mask */ + +#define ACMP_TEST_CRV1TEST_Pos (1) /*!< ACMP_T::TEST: CRV1TEST Position */ +#define ACMP_TEST_CRV1TEST_Msk (0x1ul << ACMP_TEST_CRV1TEST_Pos) /*!< ACMP_T::TEST: CRV1TEST Mask */ + +#define ACMP_TEST_OUTSEL_Pos (4) /*!< ACMP_T::TEST: OUTSEL Position */ +#define ACMP_TEST_OUTSEL_Msk (0x1ul << ACMP_TEST_OUTSEL_Pos) /*!< ACMP_T::TEST: OUTSEL Mask */ + +#define ACMP_TEST_HYSBYPASS_Pos (8) /*!< ACMP_T::TEST: HYSBYPASS Position */ +#define ACMP_TEST_HYSBYPASS_Msk (0x1ul << ACMP_TEST_HYSBYPASS_Pos) /*!< ACMP_T::TEST: HYSBYPASS Mask */ + +#define ACMP_VERSION_MINOR_Pos (0) /*!< ACMP_T::VERSION: MINOR Position */ +#define ACMP_VERSION_MINOR_Msk (0xfffful << ACMP_VERSION_MINOR_Pos) /*!< ACMP_T::VERSION: MINOR Mask */ + +#define ACMP_VERSION_SUB_Pos (16) /*!< ACMP_T::VERSION: SUB Position */ +#define ACMP_VERSION_SUB_Msk (0xfful << ACMP_VERSION_SUB_Pos) /*!< ACMP_T::VERSION: SUB Mask */ + +#define ACMP_VERSION_MAJOR_Pos (24) /*!< ACMP_T::VERSION: MAJOR Position */ +#define ACMP_VERSION_MAJOR_Msk (0xfful << ACMP_VERSION_MAJOR_Pos) /*!< ACMP_T::VERSION: MAJOR Mask */ + +/**@}*/ /* ACMP_CONST */ +/**@}*/ /* end of ACMP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ACMP_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/bmc_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/bmc_reg.h new file mode 100644 index 0000000..11b709c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/bmc_reg.h @@ -0,0 +1,725 @@ +/**************************************************************************//** + * @file bmc_reg.h + * @version V3.00 + * @brief BMC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BMC_REG_H__ +#define __BMC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup BMC Controller + Memory Mapped Structure for BMC Controller +@{ */ + +typedef struct +{ + + +/** + * @var BMC_T::CTL + * Offset: 0x00 Biphase Mask Coding Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BMCEN |Biphase Mask Coding Enable + * | | |0 = Biphase Mask Coding function is Disabled. It is cleared after current frame data transfer done. + * | | |1 = Biphase Mask Coding function is Enabled. + * |[1] |BWADJ |Bit Width Adjustment 1.5 Time + * | | |0 = The bit time period of Logic '0' is same as Logic '1'. + * | | |1 = The bit time period of Logic '0' is 1.5 times as Logic '1'. + * | | |Note: When this bit is set, the PDMA + * |[2] |PREAM32 |Preamble Bit Number 32 + * | | |0 = The bit number of Preamble is 64 bits. + * | | |1 = The bit number of Preamble is 32 bits. + * |[3] |DUMLVL |Dummy Bit Level + * | | |0 = The logic level of dummy bit is LOW. + * | | |1 = The logic level of dummy bit is HIGH. + * |[4] |DMAEN |PDMA Channel Enable + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * |[8] |G0CHEN |BMC Group 0 Channel Enable + * | | |0 = BMC Channel 0~3 Disabled. + * | | |1 = BMC Channel 0~3 Enabled. + * |[9] |G1CHEN |BMC Group 1 Channel Enable + * | | |0 = BMC Channel 4~7 Disabled. + * | | |1 = BMC Channel 4~7 Enabled. + * |[10] |G2CHEN |BMC Group 2 Channel Enable + * | | |0 = BMC Channel 8~11 Disabled. + * | | |1 = BMC Channel 8~11 Enabled. + * |[11] |G3CHEN |BMC Group 3 Channel Enable + * | | |0 = BMC Channel 12~15 Disabled. + * | | |1 = BMC Channel 12~15 Enabled. + * |[12] |G4CHEN |BMC Group 4 Channel Enable + * | | |0 = BMC Channel 16~19 Disabled. + * | | |1 = BMC Channel 16~19 Enabled. + * |[13] |G5CHEN |BMC Group 5 Channel Enable + * | | |0 = BMC Channel 20~23 Disabled. + * | | |1 = BMC Channel 20~23 Enabled. + * |[14] |G6CHEN |BMC Group 6 Channel Enable + * | | |0 = BMC Channel 24~27 Disabled. + * | | |1 = BMC Channel 24~27 Enabled. + * |[15] |G7CHEN |BMC Group 7 Channel Enable + * | | |0 = BMC Channel 28~31 Disabled. + * | | |1 = BMC Channel 28~31 Enabled. + * |[24:16] |BTDIV |Bit Time Divider + * | | |These bit field indicates the half bit time divider for Biphase Mask Coding bit. + * | | |For example, if the HCLK is 200 MHz, the divider can be set as 0x64 + * | | |It will generate 2 MHz reference clock and the Biphase Mask Coding transmitting data is sent according the reference divided clock. + * @var BMC_T::DNUM0 + * Offset: 0x04 Biphase Mask Coding Dummy Bit Number Channel Group 0~3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DNUMG0 |Dummy Number for Channel 0~3 + * | | |These bit field defines the dummy bit number for the group of channel 0~3 + * | | |Each dummy bit equal 8 bit data period. + * |[15:8] |DNUMG1 |Dummy Number for Channel 4~7 + * | | |These bit field defines the dummy bit number for the group of channel 4~7 + * | | |Each dummy bit equal 8 bit data period. + * |[23:16] |DNUMG2 |Dummy Number for Channel 8~11 + * | | |These bit field defines the dummy bit number for the group of channel 8~11 + * | | |Each dummy bit equal 8 bit data period. + * |[31:24] |DNUMG3 |Dummy Number for Channel 12~15 + * | | |These bit field defines the dummy bit number for the group of channel 12~15 + * | | |Each dummy bit equal 8 bit data period. + * @var BMC_T::DNUM1 + * Offset: 0x08 Biphase Mask Coding Dummy Bit Number Channel Group 4~7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DNUMG4 |Dummy Number for Channel 16~19 + * | | |These bit field defines the dummy bit number for the group of channel 16~19 + * | | |Each dummy bit equal 8 bit data period. + * |[15:8] |DNUMG5 |Dummy Number for Channel 20~23 + * | | |These bit field defines the dummy bit number for the group of channel 20~23 + * | | |Each dummy bit equal 8 bit data period. + * |[23:16] |DNUMG6 |Dummy Number for Channel 24~27 + * | | |These bit field defines the dummy bit number for the group of channel 24~27 + * | | |Each dummy bit equal 8 bit data period. + * |[31:24] |DNUMG7 |Dummy Number for Channel 28~31 + * | | |These bit field defines the dummy bit number for the group of channel 28~31 + * | | |Each dummy bit equal 8 bit data period. + * @var BMC_T::INTEN + * Offset: 0x0C Biphase Mask Coding Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTXDIEN |Frame Transmit Done Interrupt Enable Bit + * | | |0 = Frame transmit done interrupt Disabled. + * | | |1 = Frame transmit done interrupt Enabled. + * |[1] |TXUNDIEN |Transmit Data Under Run Interrupt Enable Bit + * | | |0 = Transmit data register under run interrupt Disabled. + * | | |1 = Transmit data register under run interrupt Enabled. + * @var BMC_T::INTSTS + * Offset: 0x10 Biphase Mask Coding Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTXDIF |Frame Transmit Done Interrupt Flag + * | | |0 = No frame transmit done interrupt flag. + * | | |1 = Frame transmit done interrupt flag. Write 1 to clear. + * |[1] |TXUNDIF |Transmit Data Register Under Run Interrupt Flag + * | | |0 = No transmit data register under run interrupt flag. + * | | |1 = Transmit data register under interrupt flag. This bit is the OR function of BMC_INTSTS[15:8]. + * |[8] |G0TXUND |Channel 0~3 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 0~3. + * | | |1 = Transmit data under run active in one of channel 0~3. Write 1 to clear. + + * |[9] |G1TXUND |Channel 4~7 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 4~7. + * | | |1 = Transmit data under run active in one of channel 4~7. Write 1 to clear. + * |[10] |G2TXUND |Channel 8~11 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 8~11. + * | | |1 = Transmit data under run active in one of channel 8~11. Write 1 to clear. + * |[10] |G3TXUND |Channel 12~15 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 12~15. + * | | |1 = Transmit data under run active in one of channel 12~15. Write 1 to clear. + * |[12] |G4TXUND |Channel 16~19 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 16~19. + * | | |1 = Transmit data under run active in one of channel 16~19. Write 1 to clear. + * |[13] |G5TXUND |Channel 20~23 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 20~23. + * | | |1 = Transmit data under run active in one of channel 20~23. Write 1 to clear. + * |[14] |G6TXUND |Channel 24~27 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 24~27. + * | | |1 = Transmit data under run active in one of channel 24~27. Write 1 to clear. + * |[15] |G7TXUND |Channel 28~31 Transmit Data Under Run + * | | |0 = No Transmit data under run active in one of channel 28~31. + * | | |1 = Transmit data under run active in one of channel 28~31. Write 1 to clear. + * @var BMC_T::CHEMPTY + * Offset: 0x14 Biphase Mask Coding Channel Done Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0EPT |BMC Channel 0 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[1] |CH1EPT |BMC Channel 1 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[2] |CH2EPT |BMC Channel 2 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[3] |CH3EPT |BMC Channel 3 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[4] |CH4EPT |BMC Channel 4 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[5] |CH5EPT |BMC Channel 5 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[6] |CH6EPT |BMC Channel 6 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[7] |CH7EPT |BMC Channel 7 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[8] |CH8EPT |BMC Channel 8 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[9] |CH9EPT |BMC Channel 9 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[10] |CH10EPT |BMC Channel 10 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[11] |CH11EPT |BMC Channel 11 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[12] |CH12EPT |BMC Channel 12 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[13] |CH13EPT |BMC Channel 13 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[14] |CH14EPT |BMC Channel 14 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[15] |CH15EPT |BMC Channel 15 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[16] |CH16EPT |BMC Channel 16 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[17] |CH17EPT |BMC Channel 17 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[18] |CH18EPT |BMC Channel 18 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[19] |CH19EPT |BMC Channel 19 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[20] |CH20EPT |BMC Channel 20 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[21] |CH21EPT |BMC Channel 21 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[22] |CH22EPT |BMC Channel 22 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[23] |CH23EPT |BMC Channel 23 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[24] |CH24EPT |BMC Channel 24 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[25] |CH25EPT |BMC Channel 25 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[26] |CH26EPT |BMC Channel 26 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[27] |CH27EPT |BMC Channel 27 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[28] |CH28EPT |BMC Channel 28 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[29] |CH29EPT |BMC Channel 29 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[30] |CH30EPT |BMC Channel 30 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * |[31] |CH31EPT |BMC Channel 31 Current FIFO Empty + * | | |0 = The current transmitted FIFO no empty. + * | | |1 = The current transmitted FIFO empty. + * | | |Note: This bit be clear automatically by writing the relative channel data (byte). + * @var BMC_T::TXDATG0 + * Offset: 0x18 Biphase Mask Coding Transmit Data Group 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH0_TXDAT |Biphase Mask Coding Channel 0 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 0. + * |[12:8] |CH1_TXDAT |Biphase Mask Coding Channel 1 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 1. + * |[20:16] |CH2_TXDAT |Biphase Mask Coding Channel 2 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 2. + * |[28:24] |CH3_TXDAT |Biphase Mask Coding Channel 3 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 3. + * @var BMC_T::TXDATG1 + * Offset: 0x1C Biphase Mask Coding Transmit Data Group 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH4_TXDAT |Biphase Mask Coding Channel 4 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 4. + * |[12:8] |CH5_TXDAT |Biphase Mask Coding Channel 5 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 5. + * |[20:16] |CH6_TXDAT |Biphase Mask Coding Channel 6 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 6. + * |[28:24] |CH7_TXDAT |Biphase Mask Coding Channel 7 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 7. + * @var BMC_T::TXDATG2 + * Offset: 0x20 Biphase Mask Coding Transmit Data Group 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH8_TXDAT |Biphase Mask Coding Channel 8 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 8. + * |[12:8] |CH9_TXDAT |Biphase Mask Coding Channel 9 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 9. + * |[20:16] |CH10_TXDAT|Biphase Mask Coding Channel 10 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 10. + * |[28:24] |CH11_TXDAT|Biphase Mask Coding Channel 11 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 11. + * @var BMC_T::TXDATG3 + * Offset: 0x24 Biphase Mask Coding Transmit Data Group 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH12_TXDAT|Biphase Mask Coding Channel 12 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 12. + * |[12:8] |CH13_TXDAT|Biphase Mask Coding Channel 13 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 13. + * |[20:16] |CH14_TXDAT|Biphase Mask Coding Channel 14 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 14. + * |[28:24] |CH15_TXDAT|Biphase Mask Coding Channel 15 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 15. + * @var BMC_T::TXDATG4 + * Offset: 0x28 Biphase Mask Coding Transmit Data Group 4 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH16_TXDAT|Biphase Mask Coding Channel 16 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 16. + * |[12:8] |CH17_TXDAT|Biphase Mask Coding Channel 17 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 17. + * |[20:16] |CH18_TXDAT|Biphase Mask Coding Channel 18 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 18. + * |[28:24] |CH19_TXDAT|Biphase Mask Coding Channel 19 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 19. + * @var BMC_T::TXDATG5 + * Offset: 0x2C Biphase Mask Coding Transmit Data Group 5 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH20_TXDAT|Biphase Mask Coding Channel 20 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 20. + * |[12:8] |CH21_TXDAT|Biphase Mask Coding Channel 21 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 21. + * |[20:16] |CH22_TXDAT|Biphase Mask Coding Channel 22 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 22. + * |[28:24] |CH23_TXDAT|Biphase Mask Coding Channel 23 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 23. + * @var BMC_T::TXDATG6 + * Offset: 0x30 Biphase Mask Coding Transmit Data Group 6 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH24_TXDAT|Biphase Mask Coding Channel 24 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 24. + * |[12:8] |CH25_TXDAT|Biphase Mask Coding Channel 25 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 25. + * |[20:16] |CH26_TXDAT|Biphase Mask Coding Channel 26 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 26. + * |[28:24] |CH27_TXDAT|Biphase Mask Coding Channel 27 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 27. + * @var BMC_T::TXDATG7 + * Offset: 0x34 Biphase Mask Coding Transmit Data Group 7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CH28_TXDAT|Biphase Mask Coding Channel 28 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 28. + * |[12:8] |CH29_TXDAT|Biphase Mask Coding Channel 29 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 29. + * |[20:16] |CH30_TXDAT|Biphase Mask Coding Channel 30 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 30. + * |[28:24] |CH31_TXDAT|Biphase Mask Coding Channel 31 Transmit Data + * | | |The bits field indicates the transmit data buffer for channel 31. + */ + __IO uint32_t CTL; /*!< [0x0000] Biphase Mask Coding Control Register */ + __IO uint32_t DNUM0; /*!< [0x0004] Biphase Mask Coding Dummy Bit Number Channel Group 0~3 Register */ + __IO uint32_t DNUM1; /*!< [0x0008] Biphase Mask Coding Dummy Bit Number Channel Group 4~7 Register */ + __IO uint32_t INTEN; /*!< [0x000c] Biphase Mask Coding Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0010] Biphase Mask Coding Interrupt Status Register */ + __IO uint32_t CHEMPTY; /*!< [0x0014] Biphase Mask Coding Channel Done Status Register */ + __O uint32_t TXDATG0; /*!< [0x0018] Biphase Mask Coding Transmit Data Group 0 Register */ + __O uint32_t TXDATG1; /*!< [0x001c] Biphase Mask Coding Transmit Data Group 1 Register */ + __O uint32_t TXDATG2; /*!< [0x0020] Biphase Mask Coding Transmit Data Group 2 Register */ + __O uint32_t TXDATG3; /*!< [0x0024] Biphase Mask Coding Transmit Data Group 3 Register */ + __O uint32_t TXDATG4; /*!< [0x0028] Biphase Mask Coding Transmit Data Group 4 Register */ + __O uint32_t TXDATG5; /*!< [0x002c] Biphase Mask Coding Transmit Data Group 5 Register */ + __O uint32_t TXDATG6; /*!< [0x0030] Biphase Mask Coding Transmit Data Group 6 Register */ + __O uint32_t TXDATG7; /*!< [0x0034] Biphase Mask Coding Transmit Data Group 7 Register */ + +} BMC_T; + +/** + @addtogroup BMC_CONST BMC Bit Field Definition + Constant Definitions for BMC Controller +@{ */ + +#define BMC_CTL_BMCEN_Pos (0) /*!< BMC_T::CTL: BMCEN Position */ +#define BMC_CTL_BMCEN_Msk (0x1ul << BMC_CTL_BMCEN_Pos) /*!< BMC_T::CTL: BMCEN Mask */ + +#define BMC_CTL_BWADJ_Pos (1) /*!< BMC_T::CTL: BWADJ Position */ +#define BMC_CTL_BWADJ_Msk (0x1ul << BMC_CTL_BWADJ_Pos) /*!< BMC_T::CTL: BWADJ Mask */ + +#define BMC_CTL_PREAM32_Pos (2) /*!< BMC_T::CTL: PREAM32 Position */ +#define BMC_CTL_PREAM32_Msk (0x1ul << BMC_CTL_PREAM32_Pos) /*!< BMC_T::CTL: PREAM32 Mask */ + +#define BMC_CTL_DUMLVL_Pos (3) /*!< BMC_T::CTL: DUMLVL Position */ +#define BMC_CTL_DUMLVL_Msk (0x1ul << BMC_CTL_DUMLVL_Pos) /*!< BMC_T::CTL: DUMLVL Mask */ + +#define BMC_CTL_DMAEN_Pos (4) /*!< BMC_T::CTL: DMAEN Position */ +#define BMC_CTL_DMAEN_Msk (0x1ul << BMC_CTL_DMAEN_Pos) /*!< BMC_T::CTL: DMAEN Mask */ + +#define BMC_CTL_G0CHEN_Pos (8) /*!< BMC_T::CTL: G0CHEN Position */ +#define BMC_CTL_G0CHEN_Msk (0x1ul << BMC_CTL_G0CHEN_Pos) /*!< BMC_T::CTL: G0CHEN Mask */ + +#define BMC_CTL_G1CHEN_Pos (9) /*!< BMC_T::CTL: G1CHEN Position */ +#define BMC_CTL_G1CHEN_Msk (0x1ul << BMC_CTL_G1CHEN_Pos) /*!< BMC_T::CTL: G1CHEN Mask */ + +#define BMC_CTL_G2CHEN_Pos (10) /*!< BMC_T::CTL: G2CHEN Position */ +#define BMC_CTL_G2CHEN_Msk (0x1ul << BMC_CTL_G2CHEN_Pos) /*!< BMC_T::CTL: G2CHEN Mask */ + +#define BMC_CTL_G3CHEN_Pos (11) /*!< BMC_T::CTL: G3CHEN Position */ +#define BMC_CTL_G3CHEN_Msk (0x1ul << BMC_CTL_G3CHEN_Pos) /*!< BMC_T::CTL: G3CHEN Mask */ + +#define BMC_CTL_G4CHEN_Pos (12) /*!< BMC_T::CTL: G4CHEN Position */ +#define BMC_CTL_G4CHEN_Msk (0x1ul << BMC_CTL_G4CHEN_Pos) /*!< BMC_T::CTL: G4CHEN Mask */ + +#define BMC_CTL_G5CHEN_Pos (13) /*!< BMC_T::CTL: G5CHEN Position */ +#define BMC_CTL_G5CHEN_Msk (0x1ul << BMC_CTL_G5CHEN_Pos) /*!< BMC_T::CTL: G5CHEN Mask */ + +#define BMC_CTL_G6CHEN_Pos (14) /*!< BMC_T::CTL: G6CHEN Position */ +#define BMC_CTL_G6CHEN_Msk (0x1ul << BMC_CTL_G6CHEN_Pos) /*!< BMC_T::CTL: G6CHEN Mask */ + +#define BMC_CTL_G7CHEN_Pos (15) /*!< BMC_T::CTL: G7CHEN Position */ +#define BMC_CTL_G7CHEN_Msk (0x1ul << BMC_CTL_G7CHEN_Pos) /*!< BMC_T::CTL: G7CHEN Mask */ + +#define BMC_CTL_BTDIV_Pos (16) /*!< BMC_T::CTL: BTDIV Position */ +#define BMC_CTL_BTDIV_Msk (0x1fful << BMC_CTL_BTDIV_Pos) /*!< BMC_T::CTL: BTDIV Mask */ + +#define BMC_DNUM0_DNUMG0_Pos (0) /*!< BMC_T::DNUM0: DNUMG0 Position */ +#define BMC_DNUM0_DNUMG0_Msk (0xfful << BMC_DNUM0_DNUMG0_Pos) /*!< BMC_T::DNUM0: DNUMG0 Mask */ + +#define BMC_DNUM0_DNUMG1_Pos (8) /*!< BMC_T::DNUM0: DNUMG1 Position */ +#define BMC_DNUM0_DNUMG1_Msk (0xfful << BMC_DNUM0_DNUMG1_Pos) /*!< BMC_T::DNUM0: DNUMG1 Mask */ + +#define BMC_DNUM0_DNUMG2_Pos (16) /*!< BMC_T::DNUM0: DNUMG2 Position */ +#define BMC_DNUM0_DNUMG2_Msk (0xfful << BMC_DNUM0_DNUMG2_Pos) /*!< BMC_T::DNUM0: DNUMG2 Mask */ + +#define BMC_DNUM0_DNUMG3_Pos (24) /*!< BMC_T::DNUM0: DNUMG3 Position */ +#define BMC_DNUM0_DNUMG3_Msk (0xfful << BMC_DNUM0_DNUMG3_Pos) /*!< BMC_T::DNUM0: DNUMG3 Mask */ + +#define BMC_DNUM1_DNUMG4_Pos (0) /*!< BMC_T::DNUM1: DNUMG4 Position */ +#define BMC_DNUM1_DNUMG4_Msk (0xfful << BMC_DNUM1_DNUMG4_Pos) /*!< BMC_T::DNUM1: DNUMG4 Mask */ + +#define BMC_DNUM1_DNUMG5_Pos (8) /*!< BMC_T::DNUM1: DNUMG5 Position */ +#define BMC_DNUM1_DNUMG5_Msk (0xfful << BMC_DNUM1_DNUMG5_Pos) /*!< BMC_T::DNUM1: DNUMG5 Mask */ + +#define BMC_DNUM1_DNUMG6_Pos (16) /*!< BMC_T::DNUM1: DNUMG6 Position */ +#define BMC_DNUM1_DNUMG6_Msk (0xfful << BMC_DNUM1_DNUMG6_Pos) /*!< BMC_T::DNUM1: DNUMG6 Mask */ + +#define BMC_DNUM1_DNUMG7_Pos (24) /*!< BMC_T::DNUM1: DNUMG7 Position */ +#define BMC_DNUM1_DNUMG7_Msk (0xfful << BMC_DNUM1_DNUMG7_Pos) /*!< BMC_T::DNUM1: DNUMG7 Mask */ + +#define BMC_INTEN_FTXDIEN_Pos (0) /*!< BMC_T::INTEN: FTXDIEN Position */ +#define BMC_INTEN_FTXDIEN_Msk (0x1ul << BMC_INTEN_FTXDIEN_Pos) /*!< BMC_T::INTEN: FTXDIEN Mask */ + +#define BMC_INTEN_TXUNDIEN_Pos (1) /*!< BMC_T::INTEN: TXUNDIEN Position */ +#define BMC_INTEN_TXUNDIEN_Msk (0x1ul << BMC_INTEN_TXUNDIEN_Pos) /*!< BMC_T::INTEN: TXUNDIEN Mask */ + +#define BMC_INTSTS_FTXDIF_Pos (0) /*!< BMC_T::INTSTS: FTXDIF Position */ +#define BMC_INTSTS_FTXDIF_Msk (0x1ul << BMC_INTSTS_FTXDIF_Pos) /*!< BMC_T::INTSTS: FTXDIF Mask */ + +#define BMC_INTSTS_TXUNDIF_Pos (1) /*!< BMC_T::INTSTS: TXUNDIF Position */ +#define BMC_INTSTS_TXUNDIF_Msk (0x1ul << BMC_INTSTS_TXUNDIF_Pos) /*!< BMC_T::INTSTS: TXUNDIF Mask */ + +#define BMC_INTSTS_G0TXUND_Pos (8) /*!< BMC_T::INTSTS: G0TXUND Position */ +#define BMC_INTSTS_G0TXUND_Msk (0x1ul << BMC_INTSTS_G0TXUND_Pos) /*!< BMC_T::INTSTS: G0TXUND Mask */ + +#define BMC_INTSTS_G1TXUND_Pos (9) /*!< BMC_T::INTSTS: G1TXUND Position */ +#define BMC_INTSTS_G1TXUND_Msk (0x1ul << BMC_INTSTS_G1TXUND_Pos) /*!< BMC_T::INTSTS: G1TXUND Mask */ + +#define BMC_INTSTS_G2TXUND_Pos (10) /*!< BMC_T::INTSTS: G2TXUND Position */ +#define BMC_INTSTS_G2TXUND_Msk (0x1ul << BMC_INTSTS_G2TXUND_Pos) /*!< BMC_T::INTSTS: G2TXUND Mask */ + +#define BMC_INTSTS_G3TXUND_Pos (11) /*!< BMC_T::INTSTS: G3TXUND Position */ +#define BMC_INTSTS_G3TXUND_Msk (0x1ul << BMC_INTSTS_G3TXUND_Pos) /*!< BMC_T::INTSTS: G3TXUND Mask */ + +#define BMC_INTSTS_G4TXUND_Pos (12) /*!< BMC_T::INTSTS: G4TXUND Position */ +#define BMC_INTSTS_G4TXUND_Msk (0x1ul << BMC_INTSTS_G4TXUND_Pos) /*!< BMC_T::INTSTS: G4TXUND Mask */ + +#define BMC_INTSTS_G5TXUND_Pos (13) /*!< BMC_T::INTSTS: G5TXUND Position */ +#define BMC_INTSTS_G5TXUND_Msk (0x1ul << BMC_INTSTS_G5TXUND_Pos) /*!< BMC_T::INTSTS: G5TXUND Mask */ + +#define BMC_INTSTS_G6TXUND_Pos (14) /*!< BMC_T::INTSTS: G6TXUND Position */ +#define BMC_INTSTS_G6TXUND_Msk (0x1ul << BMC_INTSTS_G6TXUND_Pos) /*!< BMC_T::INTSTS: G6TXUND Mask */ + +#define BMC_INTSTS_G7TXUND_Pos (15) /*!< BMC_T::INTSTS: G7TXUND Position */ +#define BMC_INTSTS_G7TXUND_Msk (0x1ul << BMC_INTSTS_G7TXUND_Pos) /*!< BMC_T::INTSTS: G7TXUND Mask */ + +#define BMC_CHEMPTY_CH0EPT_Pos (0) /*!< BMC_T::CHEMPTY: CH0EPT Position */ +#define BMC_CHEMPTY_CH0EPT_Msk (0x1ul << BMC_CHEMPTY_CH0EPT_Pos) /*!< BMC_T::CHEMPTY: CH0EPT Mask */ + +#define BMC_CHEMPTY_CH1EPT_Pos (1) /*!< BMC_T::CHEMPTY: CH1EPT Position */ +#define BMC_CHEMPTY_CH1EPT_Msk (0x1ul << BMC_CHEMPTY_CH1EPT_Pos) /*!< BMC_T::CHEMPTY: CH1EPT Mask */ + +#define BMC_CHEMPTY_CH2EPT_Pos (2) /*!< BMC_T::CHEMPTY: CH2EPT Position */ +#define BMC_CHEMPTY_CH2EPT_Msk (0x1ul << BMC_CHEMPTY_CH2EPT_Pos) /*!< BMC_T::CHEMPTY: CH2EPT Mask */ + +#define BMC_CHEMPTY_CH3EPT_Pos (3) /*!< BMC_T::CHEMPTY: CH3EPT Position */ +#define BMC_CHEMPTY_CH3EPT_Msk (0x1ul << BMC_CHEMPTY_CH3EPT_Pos) /*!< BMC_T::CHEMPTY: CH3EPT Mask */ + +#define BMC_CHEMPTY_CH4EPT_Pos (4) /*!< BMC_T::CHEMPTY: CH4EPT Position */ +#define BMC_CHEMPTY_CH4EPT_Msk (0x1ul << BMC_CHEMPTY_CH4EPT_Pos) /*!< BMC_T::CHEMPTY: CH4EPT Mask */ + +#define BMC_CHEMPTY_CH5EPT_Pos (5) /*!< BMC_T::CHEMPTY: CH5EPT Position */ +#define BMC_CHEMPTY_CH5EPT_Msk (0x1ul << BMC_CHEMPTY_CH5EPT_Pos) /*!< BMC_T::CHEMPTY: CH5EPT Mask */ + +#define BMC_CHEMPTY_CH6EPT_Pos (6) /*!< BMC_T::CHEMPTY: CH6EPT Position */ +#define BMC_CHEMPTY_CH6EPT_Msk (0x1ul << BMC_CHEMPTY_CH6EPT_Pos) /*!< BMC_T::CHEMPTY: CH6EPT Mask */ + +#define BMC_CHEMPTY_CH7EPT_Pos (7) /*!< BMC_T::CHEMPTY: CH7EPT Position */ +#define BMC_CHEMPTY_CH7EPT_Msk (0x1ul << BMC_CHEMPTY_CH7EPT_Pos) /*!< BMC_T::CHEMPTY: CH7EPT Mask */ + +#define BMC_CHEMPTY_CH8EPT_Pos (8) /*!< BMC_T::CHEMPTY: CH8EPT Position */ +#define BMC_CHEMPTY_CH8EPT_Msk (0x1ul << BMC_CHEMPTY_CH8EPT_Pos) /*!< BMC_T::CHEMPTY: CH8EPT Mask */ + +#define BMC_CHEMPTY_CH9EPT_Pos (9) /*!< BMC_T::CHEMPTY: CH9EPT Position */ +#define BMC_CHEMPTY_CH9EPT_Msk (0x1ul << BMC_CHEMPTY_CH9EPT_Pos) /*!< BMC_T::CHEMPTY: CH9EPT Mask */ + +#define BMC_CHEMPTY_CH10EPT_Pos (10) /*!< BMC_T::CHEMPTY: CH10EPT Position */ +#define BMC_CHEMPTY_CH10EPT_Msk (0x1ul << BMC_CHEMPTY_CH10EPT_Pos) /*!< BMC_T::CHEMPTY: CH10EPT Mask */ + +#define BMC_CHEMPTY_CH11EPT_Pos (11) /*!< BMC_T::CHEMPTY: CH11EPT Position */ +#define BMC_CHEMPTY_CH11EPT_Msk (0x1ul << BMC_CHEMPTY_CH11EPT_Pos) /*!< BMC_T::CHEMPTY: CH11EPT Mask */ + +#define BMC_CHEMPTY_CH12EPT_Pos (12) /*!< BMC_T::CHEMPTY: CH12EPT Position */ +#define BMC_CHEMPTY_CH12EPT_Msk (0x1ul << BMC_CHEMPTY_CH12EPT_Pos) /*!< BMC_T::CHEMPTY: CH12EPT Mask */ + +#define BMC_CHEMPTY_CH13EPT_Pos (13) /*!< BMC_T::CHEMPTY: CH13EPT Position */ +#define BMC_CHEMPTY_CH13EPT_Msk (0x1ul << BMC_CHEMPTY_CH13EPT_Pos) /*!< BMC_T::CHEMPTY: CH13EPT Mask */ + +#define BMC_CHEMPTY_CH14EPT_Pos (14) /*!< BMC_T::CHEMPTY: CH14EPT Position */ +#define BMC_CHEMPTY_CH14EPT_Msk (0x1ul << BMC_CHEMPTY_CH14EPT_Pos) /*!< BMC_T::CHEMPTY: CH14EPT Mask */ + +#define BMC_CHEMPTY_CH15EPT_Pos (15) /*!< BMC_T::CHEMPTY: CH15EPT Position */ +#define BMC_CHEMPTY_CH15EPT_Msk (0x1ul << BMC_CHEMPTY_CH15EPT_Pos) /*!< BMC_T::CHEMPTY: CH15EPT Mask */ + +#define BMC_CHEMPTY_CH16EPT_Pos (16) /*!< BMC_T::CHEMPTY: CH16EPT Position */ +#define BMC_CHEMPTY_CH16EPT_Msk (0x1ul << BMC_CHEMPTY_CH16EPT_Pos) /*!< BMC_T::CHEMPTY: CH16EPT Mask */ + +#define BMC_CHEMPTY_CH17EPT_Pos (17) /*!< BMC_T::CHEMPTY: CH17EPT Position */ +#define BMC_CHEMPTY_CH17EPT_Msk (0x1ul << BMC_CHEMPTY_CH17EPT_Pos) /*!< BMC_T::CHEMPTY: CH17EPT Mask */ + +#define BMC_CHEMPTY_CH18EPT_Pos (18) /*!< BMC_T::CHEMPTY: CH18EPT Position */ +#define BMC_CHEMPTY_CH18EPT_Msk (0x1ul << BMC_CHEMPTY_CH18EPT_Pos) /*!< BMC_T::CHEMPTY: CH18EPT Mask */ + +#define BMC_CHEMPTY_CH19EPT_Pos (19) /*!< BMC_T::CHEMPTY: CH19EPT Position */ +#define BMC_CHEMPTY_CH19EPT_Msk (0x1ul << BMC_CHEMPTY_CH19EPT_Pos) /*!< BMC_T::CHEMPTY: CH19EPT Mask */ + +#define BMC_CHEMPTY_CH20EPT_Pos (20) /*!< BMC_T::CHEMPTY: CH20EPT Position */ +#define BMC_CHEMPTY_CH20EPT_Msk (0x1ul << BMC_CHEMPTY_CH20EPT_Pos) /*!< BMC_T::CHEMPTY: CH20EPT Mask */ + +#define BMC_CHEMPTY_CH21EPT_Pos (21) /*!< BMC_T::CHEMPTY: CH21EPT Position */ +#define BMC_CHEMPTY_CH21EPT_Msk (0x1ul << BMC_CHEMPTY_CH21EPT_Pos) /*!< BMC_T::CHEMPTY: CH21EPT Mask */ + +#define BMC_CHEMPTY_CH22EPT_Pos (22) /*!< BMC_T::CHEMPTY: CH22EPT Position */ +#define BMC_CHEMPTY_CH22EPT_Msk (0x1ul << BMC_CHEMPTY_CH22EPT_Pos) /*!< BMC_T::CHEMPTY: CH22EPT Mask */ + +#define BMC_CHEMPTY_CH23EPT_Pos (23) /*!< BMC_T::CHEMPTY: CH23EPT Position */ +#define BMC_CHEMPTY_CH23EPT_Msk (0x1ul << BMC_CHEMPTY_CH23EPT_Pos) /*!< BMC_T::CHEMPTY: CH23EPT Mask */ + +#define BMC_CHEMPTY_CH24EPT_Pos (24) /*!< BMC_T::CHEMPTY: CH24EPT Position */ +#define BMC_CHEMPTY_CH24EPT_Msk (0x1ul << BMC_CHEMPTY_CH24EPT_Pos) /*!< BMC_T::CHEMPTY: CH24EPT Mask */ + +#define BMC_CHEMPTY_CH25EPT_Pos (25) /*!< BMC_T::CHEMPTY: CH25EPT Position */ +#define BMC_CHEMPTY_CH25EPT_Msk (0x1ul << BMC_CHEMPTY_CH25EPT_Pos) /*!< BMC_T::CHEMPTY: CH25EPT Mask */ + +#define BMC_CHEMPTY_CH26EPT_Pos (26) /*!< BMC_T::CHEMPTY: CH26EPT Position */ +#define BMC_CHEMPTY_CH26EPT_Msk (0x1ul << BMC_CHEMPTY_CH26EPT_Pos) /*!< BMC_T::CHEMPTY: CH26EPT Mask */ + +#define BMC_CHEMPTY_CH27EPT_Pos (27) /*!< BMC_T::CHEMPTY: CH27EPT Position */ +#define BMC_CHEMPTY_CH27EPT_Msk (0x1ul << BMC_CHEMPTY_CH27EPT_Pos) /*!< BMC_T::CHEMPTY: CH27EPT Mask */ + +#define BMC_CHEMPTY_CH28EPT_Pos (28) /*!< BMC_T::CHEMPTY: CH28EPT Position */ +#define BMC_CHEMPTY_CH28EPT_Msk (0x1ul << BMC_CHEMPTY_CH28EPT_Pos) /*!< BMC_T::CHEMPTY: CH28EPT Mask */ + +#define BMC_CHEMPTY_CH29EPT_Pos (29) /*!< BMC_T::CHEMPTY: CH29EPT Position */ +#define BMC_CHEMPTY_CH29EPT_Msk (0x1ul << BMC_CHEMPTY_CH29EPT_Pos) /*!< BMC_T::CHEMPTY: CH29EPT Mask */ + +#define BMC_CHEMPTY_CH30EPT_Pos (30) /*!< BMC_T::CHEMPTY: CH30EPT Position */ +#define BMC_CHEMPTY_CH30EPT_Msk (0x1ul << BMC_CHEMPTY_CH30EPT_Pos) /*!< BMC_T::CHEMPTY: CH30EPT Mask */ + +#define BMC_CHEMPTY_CH31EPT_Pos (31) /*!< BMC_T::CHEMPTY: CH31EPT Position */ +#define BMC_CHEMPTY_CH31EPT_Msk (0x1ul << BMC_CHEMPTY_CH31EPT_Pos) /*!< BMC_T::CHEMPTY: CH31EPT Mask */ + +#define BMC_TXDATG0_CH0_TXDAT_Pos (0) /*!< BMC_T::TXDATG0: CH0_TXDAT Position */ +#define BMC_TXDATG0_CH0_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH0_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH0_TXDAT Mask */ + +#define BMC_TXDATG0_CH1_TXDAT_Pos (8) /*!< BMC_T::TXDATG0: CH1_TXDAT Position */ +#define BMC_TXDATG0_CH1_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH1_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH1_TXDAT Mask */ + +#define BMC_TXDATG0_CH2_TXDAT_Pos (16) /*!< BMC_T::TXDATG0: CH2_TXDAT Position */ +#define BMC_TXDATG0_CH2_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH2_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH2_TXDAT Mask */ + +#define BMC_TXDATG0_CH3_TXDAT_Pos (24) /*!< BMC_T::TXDATG0: CH3_TXDAT Position */ +#define BMC_TXDATG0_CH3_TXDAT_Msk (0x1ful << BMC_TXDATG0_CH3_TXDAT_Pos) /*!< BMC_T::TXDATG0: CH3_TXDAT Mask */ + +#define BMC_TXDATG1_CH4_TXDAT_Pos (0) /*!< BMC_T::TXDATG1: CH4_TXDAT Position */ +#define BMC_TXDATG1_CH4_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH4_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH4_TXDAT Mask */ + +#define BMC_TXDATG1_CH5_TXDAT_Pos (8) /*!< BMC_T::TXDATG1: CH5_TXDAT Position */ +#define BMC_TXDATG1_CH5_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH5_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH5_TXDAT Mask */ + +#define BMC_TXDATG1_CH6_TXDAT_Pos (16) /*!< BMC_T::TXDATG1: CH6_TXDAT Position */ +#define BMC_TXDATG1_CH6_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH6_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH6_TXDAT Mask */ + +#define BMC_TXDATG1_CH7_TXDAT_Pos (24) /*!< BMC_T::TXDATG1: CH7_TXDAT Position */ +#define BMC_TXDATG1_CH7_TXDAT_Msk (0x1ful << BMC_TXDATG1_CH7_TXDAT_Pos) /*!< BMC_T::TXDATG1: CH7_TXDAT Mask */ + +#define BMC_TXDATG2_CH8_TXDAT_Pos (0) /*!< BMC_T::TXDATG2: CH8_TXDAT Position */ +#define BMC_TXDATG2_CH8_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH8_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH8_TXDAT Mask */ + +#define BMC_TXDATG2_CH9_TXDAT_Pos (8) /*!< BMC_T::TXDATG2: CH9_TXDAT Position */ +#define BMC_TXDATG2_CH9_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH9_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH9_TXDAT Mask */ + +#define BMC_TXDATG2_CH10_TXDAT_Pos (16) /*!< BMC_T::TXDATG2: CH10_TXDAT Position */ +#define BMC_TXDATG2_CH10_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH10_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH10_TXDAT Mask */ + +#define BMC_TXDATG2_CH11_TXDAT_Pos (24) /*!< BMC_T::TXDATG2: CH11_TXDAT Position */ +#define BMC_TXDATG2_CH11_TXDAT_Msk (0x1ful << BMC_TXDATG2_CH11_TXDAT_Pos) /*!< BMC_T::TXDATG2: CH11_TXDAT Mask */ + +#define BMC_TXDATG3_CH12_TXDAT_Pos (0) /*!< BMC_T::TXDATG3: CH12_TXDAT Position */ +#define BMC_TXDATG3_CH12_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH12_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH12_TXDAT Mask */ + +#define BMC_TXDATG3_CH13_TXDAT_Pos (8) /*!< BMC_T::TXDATG3: CH13_TXDAT Position */ +#define BMC_TXDATG3_CH13_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH13_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH13_TXDAT Mask */ + +#define BMC_TXDATG3_CH14_TXDAT_Pos (16) /*!< BMC_T::TXDATG3: CH14_TXDAT Position */ +#define BMC_TXDATG3_CH14_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH14_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH14_TXDAT Mask */ + +#define BMC_TXDATG3_CH15_TXDAT_Pos (24) /*!< BMC_T::TXDATG3: CH15_TXDAT Position */ +#define BMC_TXDATG3_CH15_TXDAT_Msk (0x1ful << BMC_TXDATG3_CH15_TXDAT_Pos) /*!< BMC_T::TXDATG3: CH15_TXDAT Mask */ + +#define BMC_TXDATG4_CH16_TXDAT_Pos (0) /*!< BMC_T::TXDATG4: CH16_TXDAT Position */ +#define BMC_TXDATG4_CH16_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH16_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH16_TXDAT Mask */ + +#define BMC_TXDATG4_CH17_TXDAT_Pos (8) /*!< BMC_T::TXDATG4: CH17_TXDAT Position */ +#define BMC_TXDATG4_CH17_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH17_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH17_TXDAT Mask */ + +#define BMC_TXDATG4_CH18_TXDAT_Pos (16) /*!< BMC_T::TXDATG4: CH18_TXDAT Position */ +#define BMC_TXDATG4_CH18_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH18_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH18_TXDAT Mask */ + +#define BMC_TXDATG4_CH19_TXDAT_Pos (24) /*!< BMC_T::TXDATG4: CH19_TXDAT Position */ +#define BMC_TXDATG4_CH19_TXDAT_Msk (0x1ful << BMC_TXDATG4_CH19_TXDAT_Pos) /*!< BMC_T::TXDATG4: CH19_TXDAT Mask */ + +#define BMC_TXDATG5_CH20_TXDAT_Pos (0) /*!< BMC_T::TXDATG5: CH20_TXDAT Position */ +#define BMC_TXDATG5_CH20_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH20_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH20_TXDAT Mask */ + +#define BMC_TXDATG5_CH21_TXDAT_Pos (8) /*!< BMC_T::TXDATG5: CH21_TXDAT Position */ +#define BMC_TXDATG5_CH21_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH21_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH21_TXDAT Mask */ + +#define BMC_TXDATG5_CH22_TXDAT_Pos (16) /*!< BMC_T::TXDATG5: CH22_TXDAT Position */ +#define BMC_TXDATG5_CH22_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH22_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH22_TXDAT Mask */ + +#define BMC_TXDATG5_CH23_TXDAT_Pos (24) /*!< BMC_T::TXDATG5: CH23_TXDAT Position */ +#define BMC_TXDATG5_CH23_TXDAT_Msk (0x1ful << BMC_TXDATG5_CH23_TXDAT_Pos) /*!< BMC_T::TXDATG5: CH23_TXDAT Mask */ + +#define BMC_TXDATG6_CH24_TXDAT_Pos (0) /*!< BMC_T::TXDATG6: CH24_TXDAT Position */ +#define BMC_TXDATG6_CH24_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH24_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH24_TXDAT Mask */ + +#define BMC_TXDATG6_CH25_TXDAT_Pos (8) /*!< BMC_T::TXDATG6: CH25_TXDAT Position */ +#define BMC_TXDATG6_CH25_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH25_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH25_TXDAT Mask */ + +#define BMC_TXDATG6_CH26_TXDAT_Pos (16) /*!< BMC_T::TXDATG6: CH26_TXDAT Position */ +#define BMC_TXDATG6_CH26_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH26_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH26_TXDAT Mask */ + +#define BMC_TXDATG6_CH27_TXDAT_Pos (24) /*!< BMC_T::TXDATG6: CH27_TXDAT Position */ +#define BMC_TXDATG6_CH27_TXDAT_Msk (0x1ful << BMC_TXDATG6_CH27_TXDAT_Pos) /*!< BMC_T::TXDATG6: CH27_TXDAT Mask */ + +#define BMC_TXDATG7_CH28_TXDAT_Pos (0) /*!< BMC_T::TXDATG7: CH28_TXDAT Position */ +#define BMC_TXDATG7_CH28_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH28_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH28_TXDAT Mask */ + +#define BMC_TXDATG7_CH29_TXDAT_Pos (8) /*!< BMC_T::TXDATG7: CH29_TXDAT Position */ +#define BMC_TXDATG7_CH29_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH29_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH29_TXDAT Mask */ + +#define BMC_TXDATG7_CH30_TXDAT_Pos (16) /*!< BMC_T::TXDATG7: CH30_TXDAT Position */ +#define BMC_TXDATG7_CH30_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH30_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH30_TXDAT Mask */ + +#define BMC_TXDATG7_CH31_TXDAT_Pos (24) /*!< BMC_T::TXDATG7: CH31_TXDAT Position */ +#define BMC_TXDATG7_CH31_TXDAT_Msk (0x1ful << BMC_TXDATG7_CH31_TXDAT_Pos) /*!< BMC_T::TXDATG7: CH31_TXDAT Mask */ + + +/**@}*/ /* BMC_CONST */ +/**@}*/ /* end of BMC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __BMC_REG_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/bpwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/bpwm_reg.h new file mode 100644 index 0000000..a457263 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/bpwm_reg.h @@ -0,0 +1,1835 @@ +/**************************************************************************//** + * @file bpwm_reg.h + * @version V1.00 + * @brief BPWM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_REG_H__ +#define __BPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) + Memory Mapped Structure for BPWM Controller +@{ */ + +typedef struct +{ + /** + * @var BCAPDAT_T::RCAPDAT + * Offset: 0x20C BPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. + * @var BCAPDAT_T::FCAPDAT + * Offset: 0x210 BPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ +} BCAPDAT_T; + +typedef struct +{ + + + /** + * @var BPWM_T::CTL0 + * Offset: 0x00 BPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disabled. + * | | |1 = ICE debug mode counter halt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects BPWM output. + * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var BPWM_T::CTL1 + * Offset: 0x04 BPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 + * | | |Each bit n controls corresponding BPWM channel n. + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * @var BPWM_T::CLKSRC + * Offset: 0x10 BPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select + * | | |000 = BPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var BPWM_T::CLKPSC + * Offset: 0x14 BPWM Clock Prescale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |BPWM Counter Clock Prescale + * | | |The clock of BPWM counter is decided by clock prescaler + * | | |Each BPWM pair share one BPWM counter clock prescaler + * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) + * @var BPWM_T::CNTEN + * Offset: 0x20 BPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit + * | | |0 = BPWM Counter and clock prescaler stop running. + * | | |1 = BPWM Counter and clock prescaler start running. + * @var BPWM_T::CNTCLR + * Offset: 0x24 BPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit BPWM counter to 0000H. + * @var BPWM_T::PERIOD + * Offset: 0x30 BPWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |BPWM Period Register + * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. + * @var BPWM_T::CMPDAT[6] + * Offset: 0x50 BPWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPDAT |BPWM Comparator Register + * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. + * @var BPWM_T::CNT + * Offset: 0x90 BPWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |BPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var BPWM_T::WGCTL0 + * Offset: 0xB0 BPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[3:2] |ZPCTL1 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[5:4] |ZPCTL2 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[7:6] |ZPCTL3 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[9:8] |ZPCTL4 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[11:10] |ZPCTL5 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * @var BPWM_T::WGCTL1 + * Offset: 0xB4 BPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * @var BPWM_T::MSKEN + * Offset: 0xB8 BPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * @var BPWM_T::MSK + * Offset: 0xBC BPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[1] |MSKDAT1 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[2] |MSKDAT2 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[3] |MSKDAT3 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[4] |MSKDAT4 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[5] |MSKDAT5 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * @var BPWM_T::POLCTL + * Offset: 0xD4 BPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[1] |PINV1 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[2] |PINV2 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[3] |PINV3 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[4] |PINV4 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[5] |PINV5 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * @var BPWM_T::POEN + * Offset: 0xD8 BPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[1] |POEN1 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[2] |POEN2 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[3] |POEN3 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[4] |POEN4 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[5] |POEN5 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * @var BPWM_T::INTEN + * Offset: 0xE0 BPWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type period point means center point. + * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var BPWM_T::INTSTS + * Offset: 0xE8 BPWM Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * @var BPWM_T::EADCTS0 + * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit + * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit + * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved + * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit + * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved. + * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit + * @var BPWM_T::EADCTS1 + * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit + * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit + * @var BPWM_T::SSCTL + * Offset: 0x110 BPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit + * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). + * | | |0 = BPWM synchronous start function Disabled. + * | | |1 = BPWM synchronous start function Enabled. + * |[9:8] |SSRC |BPWM Synchronous Start Source Select + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var BPWM_T::SSTRG + * Offset: 0x114 BPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) + * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. + * @var BPWM_T::STATUS + * Offset: 0x120 BPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * @var BPWM_T::CAPINEN + * Offset: 0x200 BPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * @var BPWM_T::CAPCTL + * Offset: 0x204 BPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var BPWM_T::CAPSTS + * Offset: 0x208 BPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * @var BPWM_T::CAPIEN + * Offset: 0x250 BPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var BPWM_T::CAPIF + * Offset: 0x254 BPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * @var BPWM_T::PBUF + * Offset: 0x304 BPWM PERIOD Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |BPWM Period Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var BPWM_T::CMPBUF[6] + * Offset: 0x31C BPWM CMPDAT 0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ + __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] BPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[10]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[55]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ + BCAPDAT_T CAPDAT[6]; /*!< [0x020C] BPWM Rising and Falling Capture Data Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE13[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE14[43]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE15[5]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CMPBUF[6]; /*!< [0x031c] BPWM CMPDAT 0~5 Buffer */ + +} BPWM_T; + +/** + @addtogroup BPWM_CONST BPWM Bit Field Definition + Constant Definitions for BPWM Controller +@{ */ + +#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ +#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ + +#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ +#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ + +#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ +#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ + +#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ +#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ + +#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ +#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ + +#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ +#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ + +#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ +#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ + +#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ +#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ + +#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ +#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ + +#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ +#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ + +#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ +#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ + +#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ +#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ + +#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ +#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ + +#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ +#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ + +#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ +#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ + +#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ +#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ +#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ + +#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ +#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ + +#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ +#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ +#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ + +#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ +#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ + +#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ +#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ + +#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ +#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ + +#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ +#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ + +#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ +#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ + +#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ +#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ + +#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ +#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ + +#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ +#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ + +#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ +#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ +#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ +#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ +#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ +#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ +#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ +#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ + +#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ +#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ +#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ +#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ +#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ +#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ +#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ +#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ + +#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ +#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ +#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ +#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ +#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ +#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ +#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ +#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ + +#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ +#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ +#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ +#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ +#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ +#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ +#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ +#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ + +#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ +#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ + +#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ +#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ + +#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ +#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ + +#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ +#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ + +#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ +#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ + +#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ +#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ + +#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ +#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ + +#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ +#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ + +#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ +#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ + +#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ +#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ + +#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ +#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ + +#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ +#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ + +#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ +#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ + +#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ +#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ + +#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ +#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ + +#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ +#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ + +#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ +#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ + +#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ +#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ + +#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ +#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ + +#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ +#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ + +#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ +#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ + +#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ +#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ + +#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ +#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ + +#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ +#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ + +#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ +#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ + +#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ +#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ + +#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ +#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ + +#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ +#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ + +#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ +#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ + +#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ +#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ +#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ +#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ + +#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ +#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ + +#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ +#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ + +#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ +#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ + +#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ +#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ + +#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ +#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ + +#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ +#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ + +#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ +#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ + +#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ +#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ + +#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ +#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ + +#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ +#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ + +#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ +#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ + +#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ +#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ + +#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ +#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ + +#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ +#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ +#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ +#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ + +#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ +#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ + +#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ +#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ + +#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ +#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ + +#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ +#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ + +#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ +#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ + +#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ +#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ + +#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ +#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ + +#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ +#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ + +#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ +#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ + +#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ +#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ + +#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ +#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ + +#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ +#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ + +#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ +#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ +#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ + +#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ +#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ +#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ + +#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ +#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ +#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ + +#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ +#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ +#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ + +#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ +#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ +#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ + +#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ +#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ +#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ + +#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ +#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ + +#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ +#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ + +#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ +#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ + +#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ +#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ + +#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ +#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ + +#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ +#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ + +#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ +#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ + +#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ +#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ + +#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ +#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ + +#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ +#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ + +#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ +#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ + +#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ +#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ +#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ +#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ +#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ +#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ +#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ +#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ + +#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ +#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ + +#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ +#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ + +#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ +#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ + +#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ +#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ + +#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ +#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ + +#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ +#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ + +#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ +#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ + +#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ +#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ + +#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ +#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ + +#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ +#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ + +#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ +#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ + +#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ +#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ + +#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ +#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ + +#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ +#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ + +#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ +#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ +#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ +#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ +#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ +#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ +#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ +#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ + +#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ +#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ +#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ +#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ +#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ +#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ +#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ +#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ + +#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ +#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ + +#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ +#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ + +#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ +#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ + +#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ +#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ + +#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ +#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ + +#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ +#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ + +#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ +#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ + +#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ +#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ + +#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ +#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ + +#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ +#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ + +#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ +#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ + +#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ +#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ + +#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ +#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ + +#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ +#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ + +#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ +#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ +#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ +#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ +#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ +#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ +#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ +#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ +#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ +#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ +#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ +#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ +#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ +#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ + +#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ +#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ + +#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ +#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ + +#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ +#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ + +#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ +#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ + +#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ +#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ + +#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ +#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ + +#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ +#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ + +#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ +#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ + +#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ +#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ + +#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ +#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ + +#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ +#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ + +#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ +#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ + +#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ +#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ + +#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ +#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ + +#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ +#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ + +#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ +#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ + +#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ +#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ + +#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ +#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ + +#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ +#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ + +#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ +#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ + +#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ +#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* BPWM_CONST */ +/**@}*/ /* end of BPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __BPWM_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/canfd_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/canfd_reg.h new file mode 100644 index 0000000..cf214fd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/canfd_reg.h @@ -0,0 +1,1712 @@ +/**************************************************************************//** + * @file canfd_reg.h + * @version V1.00 + * @brief CAN FD register definition header file + * +* SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef __CANFD_REG_H__ +#define __CANFD_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup Controller Area Network with Feasibility Data Rate (CAN FD) + Memory Mapped Structure for CAN FD Controller +@{ */ + +typedef struct +{ + + /** + * @var CANFD_T::DBTP + * Offset: 0x0C Data Bit Timing & Prescaler Register Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |7[3:0] |DSJW |Data (Re) Synchronization Jump Width + * | | |Valid values are 0 to 15. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[7:4] |DTSEG2 |Data time segment after sample point + * | | |Valid values are 0 to 15. + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + * |[12:8] |DTSEG1 |Data time segment before sample point + * | | |Valid values are 0 to 31. + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used. + * |[20:16] |DBRP |Data Bit Rate Prescaler + * | | |The value by which the oscillator frequency is divided for generating the bit time quanta. + * | | |The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC ='1',the range is limited to 0,1. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[23] |TDC |Transmitter Delay Compensation + * | | |0 = Transmitter Delay Compensation disabled. + * | | |1 = Transmitter Delay Compensation enabled. + * --------------------------------------------------------------------------------------------------- + * @var CANFD_T::TEST + * Offset: 0x10 Test Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |LBCK |Loop Back Mode + * | | |0 = Reset value, Loop Back Mode is disabled. + * | | |1 = Loop Back Mode is enabled (refer to 1.1.5.1 TEST Mode). + * |[6:5] |TX |Control of Transmit Pin + * | | |00 = Reset value, CANx_TXD controlled by the CAN Core, updated at the end of the CAN bit time. + * | | |01 = Sample Point can be monitored at pin CANx_TXD. + * | | |10 = Dominant ('0') level at pin CANx_TXD. + * | | |11 = Recessive ('1') level at pin CANx_TXD. + * |[7] |RX |Receive Pin + * | | |Monitors the actual value of pin CANx_RXD + * | | |0 = The CAN bus is dominant (CANx_RXD = 0). + * | | |1 = The CAN bus is recessive (CANx_RXD = 1). + * @var CANFD_T::RWD + * Offset: 0x14 RAM Watchdog Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |WDC |Watchdog Conguration + * | | |Start value of the Message RAM Watchdog Counter. With the reset value of 00 the counter is disabled. + * |[15:8] |WDV |Watchdog Value + * | | |Actual Message RAM Watchdog Counter Value. + * @var CANFD_T::CCCR + * Offset: 0x18 CC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT |Initialization + * | | |0 = Normal Operation. + * | | |1 = Initialization is started. + * | | |Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. + * | | |Therefore the programmer has to assure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value. + * |[1] |CCE |Conguration Change Enable + * | | |0 = The CPU has no write access to the protected conguration registers. + * | | |1 = The CPU has write access to the protected conguration registers (while CANFD_INIT (CANFD_CCCR[0]) = 1). + * |[2] |ASM |Restricted Operation Mode + * | | |Bit ASM can only be set by the Host when both CCE and INIT are set to 1. + * | | |The bit can be reset by the Host software at any time. + * | | |This bit will be set automatically set to 1 when the Tx handler was not able to read data from the message RAM in time. + * | | |For a description of the Restricted Operation Mode refer to Restricted Operation Mode. + * | | |0 = Normal CAN operation. + * | | |1 = Restricted Operation Mode active. + * |[3] |CSA |Clock Stop Acknowledge + * | | |0 = No clock stop acknowledged. + * | | |1 = The Controller may be set in power down by stopping AHB clock and CAN Core clockcclk. + * |[4] |CSR |Clock Stop Request + * | | |0 = No clock stop is requested. + * | | |1 = Clock stop requested. + * | | |When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. + * |[5] |MON |Bus Monitoring Mode + * | | |Bit MON can only be set by the Host when both CCE and INIT are set to 1. + * | | |The bit can be reset by the Host at any time. + * | | |0 = Bus Monitoring Mode is disabled. + * | | |1 = Bus Monitoring Mode is enabled. + * |[6] |DAR |Disable Automatic Retransmission + * | | |0 = Automatic retransmission of messages not transmitted successfully enabled. + * | | |1 = Automatic retransmission disabled. + * |[7] |TEST |Test Mode Enable + * | | |0 = Normal operation, register TEST holds reset values. + * | | |1 = Test Mode, write access to register TEST enabled. + * |[8] |FDOE |FD Operation Enable + * | | |0 = FD operation disabled. + * | | |1 = FD operation enabled. + * |[9] |BRSE |Bit Rate Switch Enable + * | | |0 = Bit rate switching for transmissions disabled. + * | | |1 = Bit rate switching for transmissions enabled. + * | | |Note: When CAN FD operation is disabled FDOE = 0, BRSE is not evaluated. + * |[12] |PXHD |Protocol Exception Handling Disable + * | | |0 = Protocol exception handling enabled. + * | | |1 = Protocol exception handling disabled. + * | | |Note: When protocol exception handling is disabled, the controller will transmit an error frame when it detects a protocol exception condition. + * |[13] |EFBI |Edge Filtering during Bus Integration + * | | |0 = Edge filtering disabled. + * | | |1 = Two consecutive dominant tq required to detect an edge f or hard synchronization. + * |[14] |TXP |Transmit Pause + * | | |If this bit is set, the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to 1.1.5.5). + * | | |0 = Transmit pause disabled. + * | | |1 = Transmit pause enabled. + * |[15] |NISO |Non ISO Operation + * | | |If this bit is set, the CAN FD controller controller uses the CAN FD frame format as specied by the Bosch CAN FD Specification V1.0. + * | | |0 = CAN FD frame format according to ISO 11898-1:2015. + * | | |1 = CAN FD frame format according to Bosch CAN FD Specification V1.0. + * @var CANFD_T::NBTP + * Offset: 0x1C Nominal Bit Timing & Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |NTSEG2 |Nominal Time segment after sample point + * | | |0x01-0x7F Valid values are 1 to 127. + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used + * | | |tBS2 = (NTSEG2 + 1) x tq. + * | | |Note: With a CAN Core clock (cclk) of 8 MHz, the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s. + * |[15:8] |NTSEG1 |Nominal Time segment before sample point + * | | |Valid values are 1 to 255. + * | | |The actual interpretation by the hardware of this value is such that one more than the programmed value is used + * | | |tBS1 = (NTSEG1 + 1) x tq. + * |[24:16] |NBRP |Nominal Bit Rate Prescaler + * | | |0x000-0x1FF The value by which the oscillator frequency is divided for generating the bit time quanta. + * | | |The bit time is built up from a multiple of this quanta. + * | | |Valid values for the Bit Rate Prescaler are 0 to 511. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[31:25] |NSJW |Nominal Re-Synchronization Jump Width + * | | |Valid values are 0 to 127,Should be smaller than NTSEG2. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * | | |tSJW = (NSJW + 1) x tq. + * @var CANFD_T::TSCC + * Offset: 0x20 Timestamp Counter Conufiguration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TSS |Timestamp Select + * | | |00 = Timestamp counter value always 0x0000. + * | | |01 = Timestamp counter value incremented according to TCP. + * | | |10 = Reserved. + * | | |11 = Same as '00'. + * |[19:16] |TCP |Timestamp Counter Prescaler + * | | |Configures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * @var CANFD_T::TSCV + * Offset: 0x24 Timestamp Counter Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TSC |Timestamp Counter + * | | |The internal Timestamp Counter value is captured on start of frame (both Rx and Tx). + * | | |When CANFD_TSS (TSCC[[1:0]) = 2'b01, the Timestamp Counter is incremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of CANFD_TCP (CANFD_TSCC[19:16]). + * | | |A wrap around sets interrupt ag CANFD_IR (CANFD_IR[16])Write access resets the counter to 0. + * | | |Note: A "wrap around" is a change of the Timestamp Counter value from non-zero to zero not caused by write access to CANFD_TSCV. + * @var CANFD_T::TOCC + * Offset: 0x28 Timeout Counter Conufiguration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ETOC |Enable Timeout Counter + * | | |0 = Timeout Counter disabled. + * | | |1 = Timeout Counter enabled. + * | | |Note: For use of timeout function with CAN FD refer to 1.1.5.3. + * |[2:1] |TOS |Timeout Select + * | | |When operating in Continuous mode, a write to CANFD_TOCV presets the counter to the value configured by CANFD_TOP (TOCC[31:16]) and continues down-counting + * | | |When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by CANFD_TOP (TOCC[31:16]) + * | | |Down-counting is started when the first FIFO element is stored. + * | | |00 = Continuous operation. + * | | |01 = Timeout controlled by Tx Event FIFO. + * | | |10 = Timeout controlled by Rx FIFO 0. + * | | |11 = Timeout controlled by Rx FIFO 1. + * |[31:16] |TOP |Timeout Period + * | | |Start value of the Timeout Counter (down-counter). Configures the Timeout Period. + * @var CANFD_T::TOCV + * Offset: 0x2C Timeout Counter Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC |Timeout Counter + * | | |The filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16]). + * | | |When decremented to 0, interrupt flag TOO (CANFD_IR[18]) is set and the timeout counter is stopped. + * | | |Start and reset/restart conditions are configured via TOS (CANFD_TOCC[1:0]). + * @var CANFD_T::ECR + * Offset: 0x40 Error Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TEC |Transmit Error Counter + * | | |Actual state of the Transmit Error Counter, values between 0 and 255. + * | | |Note: When ASM (CANFD_CCCR[2]) is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. + * |[14:8] |REC |Receive Error Counter + * | | |Actual state of the Receive Error Counter, values between 0 and 127. + * |[15] |RP |Receive Error Passive + * | | |0 = The Receive Error Counter is below the error passive level of 128. + * | | |1 = The Receive Error Counter has reached the error passive level of 128. + * |[23:16] |CEL |CAN Error Logging + * | | |The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. + * | | |The counter is also incremented when the Bus_Off limit is reached. + * | | |It is not incremented when only RP is set without changing REC. + * | | |The increment of CEL follows after the increment of REC or TEC. + * | | |The counter is reset by read access to CEL. + * | | |The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag ELO (CANFD_IR[22]). + * @var CANFD_T::PSR + * Offset: 0x44 Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |LEC |Last Error Code + * | | |The LEC indicates the type of the last error to occur on the CAN bus. + * | | |This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. + * | | |000 = No Error: No error occurred since LEC has been reset by successful reception or transmission. + * | | |001 = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. + * | | |010 = Form Error: A fixed format part of a received frame has the wrong format. + * | | |011 = AckError: The message transmitted by the CANFD CONTROLLER was not acknowledged by another node. + * | | |100 = Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant. + * | | |101 = Bit0Error : During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive + * | | |During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. + * | | |This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). + * | | |110 = CRCError: The CRC check sum of a received message was incorrect. + * | | |The CRC of an incoming message does not match with the CRC calculated from the received data. + * | | |111 = NoChange: Any read access to the Protocol Status Register re-initializes the LEC to 7.When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. + * |[4:3] |ACT |Activity + * | | |Monitors the module's CAN communication state. + * | | |00 = Synchronizing - node is synchronizing on CAN communication. + * | | |01 = Idle - node is neither receiver nor transmitter. + * | | |10 = Receiver - node is operating as receiver. + * | | |11 = Transmitter - node is operating as transmitter. + * |[5] |EP |Error Passive + * | | |0 = The CAN FD controller is in the Error_Active state. + * | | |It normally takes part in bus communication and sends an active error flag when an error has been detected. + * | | |1 = The CAN FD controller is in the Error_Passive state. + * |[6] |EW |Warning Status + * | | |0 = Both error counters are below the Error_Warning limit of 96. + * | | |1 = At least one of error counter has reached the Error_Warning limit of 96. + * |[7] |BO |Bus_Off Status + * | | |0 = The CAN FD controller is not Bus_Off. + * | | |1 = The CAN FD controller is in Bus_Off state. + * |[10:8] |DLEC |Data Phase Last Error Code + * | | |Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. + * | | |Coding is the same as for LEC. + * | | |This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. + * |[11] |RESI |ESI flag of last received CAN FD Message + * | | |This bit is set together with RFDF, independent of acceptance filtering. + * | | |0 = Last received CAN FD message did not have its ESI flag set. + * | | |1 = Last received CAN FD message had its ESI flag set. + * |[12] |RBRS |BRS flag of last received CAN FD Message + * | | |This bit is set together with RFDF, independent of acceptance filtering. + * | | |0 = Last received CAN FD message did not have its BRS flag set. + * | | |1 = Last received CAN FD message had its BRS flag set. + * | | |Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. + * |[13] |RFDF |Received a CAN FD Message + * | | |This bit is set independent of acceptance filtering. + * | | |0 = Since this bit was reset by the CPU, no CAN FD message has been received. + * | | |1 = Message in CAN FD format with FDF flag set has been received. + * | | |Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. + * |[14] |PXE |Protocol Exception Event + * | | |0 = No protocol exception event occurred since last read access. + * | | |1 = Protocol exception event occurred. + * |[22:16] |TDCV |Transmitter Delay Compensation Value + * | | |Position of the secondary sample point, defined by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (TDCR[[14:8]). + * | | |The SSP position is, in the data phase, the number of minimum time quata (mtq) between the start of the transmitted bit and the secondary sample point. + * | | |Valid values are 0 to 127 mtq. + * @var CANFD_T::TDCR + * Offset: 0x48 Transmitter Delay Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TDCF |Transmitter Delay Compensation Filter Window Length + * | | |0x00-0x7F Defines the minimum value for the SSP position, dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement + * | | |The feature is enabled when TDCF is configured to a value greater than TDCO. + * | | |Valid values are 0 to 127 mtq. + * |[14:8] |TDCO |Transmitter Delay Compensation SSP Offset + * | | |0x00-0x7F Offset value defining the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point. + * | | |Valid values are 0 to 127 mtq. + * @var CANFD_T::IR + * Offset: 0x50 Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RF0N |Rx FIFO 0 New Message + * | | |0 = No new message written to Rx FIFO 0. + * | | |1 = New message written to Rx FIFO 0. + * |[1] |RF0W |Rx FIFO 0 Watermark Reached + * | | |0 = Rx FIFO 0 fill level below watermark. + * | | |1 = Rx FIFO 0 fill level reached watermark. + * |[2] |RF0F |Rx FIFO 0 Full + * | | |0 = Rx FIFO 0 not full. + * | | |1 = Rx FIFO 0 full. + * |[3] |RF0L |Rx FIFO 0 Message Lost + * | | |0 = No Rx FIFO 0 message lost. + * | | |1 = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + * |[4] |RF1N |Rx FIFO 1 New Message + * | | |0 = No new message written to Rx FIFO 1. + * | | |1 = New message written to Rx FIFO 1. + * |[5] |RF1W |Rx FIFO 1 Watermark Reached + * | | |0 = Rx FIFO 1 fill level below watermark. + * | | |1 = Rx FIFO 1 fill level reached watermark. + * |[6] |RF1F |Rx FIFO 1 Full + * | | |0 = Rx FIFO 1 not full. + * | | |1 = Rx FIFO 1 full. + * |[7] |RF1L |Rx FIFO 1 Message Lost + * | | |0 = No Rx FIFO 1 message lost. + * | | |1 = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. + * |[8] |HPM |High Priority Message + * | | |0 = No high priority message received. + * | | |1 = High priority message received. + * |[9] |TC |Transmission Completed + * | | |0 = No transmission completed. + * | | |1 = Transmission completed. + * |[10] |TCF |Transmission Cancellation Finished + * | | |0 = No transmission cancellation finished. + * | | |1 = Transmission cancellation finished. + * |[11] |TFE |Tx FIFO Empty + * | | |0 = Tx FIFO non-empty. + * | | |1 = Tx FIFO empty. + * |[12] |TEFN |Tx Event FIFO New Entry + * | | |0 = Tx Event FIFO unchanged. + * | | |1 = Tx Handler wrote Tx Event FIFO element. + * |[13] |TEFW |Tx Event FIFO Watermark Reached + * | | |0 = Tx Event FIFO fill level below watermark. + * | | |1 = Tx Event FIFO fill level reached watermark. + * |[14] |TEFF |Tx Event FIFO Full + * | | |0 = Tx Event FIFO not full. + * | | |1 = Tx Event FIFO full. + * |[15] |TEFL |Tx Event FIFO Element Lost + * | | |0 = No Tx Event FIFO element lost. + * | | |1 = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + * |[16] |TSW |Timestamp Wraparound + * | | |0 = No timestamp counter wrap-around. + * | | |1 = Timestamp counter wrapped around. + * |[17] |MRAF |Message RAM Access Failure + * | | |The flag is set, when the Rx Handler + * | | |Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. + * | | |In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. + * | | |Was not able to write a message to the Message RAM. In this case message storage is aborted. + * | | |In both cases the FIFO put index is not updated resp. + * | | |The New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. + * | | |The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. + * | | |In this case message transmission is aborted. + * | | |In case of a Tx Handler access failure the CAN FD controller is switched into Restricted Operation Mode (refer to Restricted Operation Mode). + * | | |To leave Restricted Operation Mode, the Host CPU has to reset CANFD_ASM (CANFD_CCCR[2]). + * | | |0 = No Message RAM access failure occurred. + * | | |1 = Message RAM access failure occurred. + * |[18] |TOO |Timeout Occurred + * | | |0 = No timeout. + * | | |1 = Timeout reached. + * |[19] |DRX |Message stored to Dedicated Rx Buffer + * | | |The flag is set whenever a received message has been stored into a dedicated Rx Buffer. + * | | |0 = No Rx Buffer updated. + * | | |1 = At least one received message stored into an Rx Buffer. + * |[22] |ELO |Error Logging Overflow + * | | |0= CAN Error Logging Counter did not overflow. + * | | |1= Overflow of CAN Error Logging Counter occurred. + * |[23] |EP |Error Passive + * | | |0 = Error_Passive status unchanged. + * | | |1 = Error_Passive status changed. + * |[24] |EW |Warning Status + * | | |0 = Error_Warning status unchanged. + * | | |1 = Error_Warning status changed. + * |[25] |BO |Bus_Off Status + * | | |0 = Bus_Off status unchanged. + * | | |1 = Bus_Off status changed. + * |[26] |WDI |Watchdog Interrupt + * | | |0 = No Message RAM Watchdog event occurred. + * | | |1 = Message RAM Watchdog event due to missing READY. + * |[27] |PEA |Protocol Error in Arbitration Phase + * | | |0 = No protocol error in arbitration phase. + * | | |1 = Protocol error in arbitration phase detected (CANFD_LEC (CANFD_PSR[2:0]) no equal 0 or 7). + * | | |Note: Nominal bit time is used + * |[28] |PED |Protocol Error in Data Phase + * | | |0 = No protocol error in data phase. + * | | |1= Protocol error in data phase detected (DLEC (CANFD_PSR[10:8]) no equal 0 or 7). + * | | |Note: Data bit time is used. + * |[29] |ARA |Access to Reserved Address + * | | |0 = No access to reserved address occurred. + * | | |1 = Access to reserved address occurred. + * @var CANFD_T::IE + * Offset: 0x54 Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RF0NE |Rx FIFO 0 New Message Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[1] |RF0WE |Rx FIFO 0 Watermark Reached Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |RF0FE |Rx FIFO 0 Full Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[3] |RF0LE |Rx FIFO 0 Message Lost Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[4] |RF1NE |Rx FIFO 1 New Message Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[5] |RF1WE |Rx FIFO 1 Watermark Reached Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[6] |RF1FE |Rx FIFO 1 Full Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[7] |RF1LE |Rx FIFO 1 Message Lost Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[8] |HPME |High Priority Message Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[9] |TCE |Transmission Completed Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[10] |TCFE |Transmission Cancellation Finished Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[11] |TFEE |Tx FIFO Empty Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[12] |TEFNE |Tx Event FIFO New Entry Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[13] |TEFWE |Tx Event FIFO Watermark Reached Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[14] |TEFFE |Tx Event FIFO Full Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[15] |TEFLE |Tx Event FIFO Event Lost Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[16] |TSWE |Timestamp Wraparound Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[17] |MRAFE |Message RAM Access Failure Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[18] |TOOE |Timeout Occurred Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[19] |DRXE |Message stored to Dedicated Rx Buffer Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[20] |BECE |Bit Error Corrected Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[21] |BEUE |Bit Error Uncorrected Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[22] |ELOE |Error Logging Overflow Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[23] |EPE |Error Passive Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[24] |EWE |Warning Status Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[25] |BOE |Bus_Off Status Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[26] |WDIE |Watchdog Interrupt Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[27] |PEAE |Protocol Error in Arbitration Phase Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[28] |PEDE |Protocol Error in Data Phase Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[29] |ARAE |Access to Reserved Address Enable + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * @var CANFD_T::ILS + * Offset: 0x58 Interrupt Line Select + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RF0NL |Rx FIFO 0 New Message Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[1] |RF0WL |Rx FIFO 0 Watermark Reached Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[2] |RF0FL |Rx FIFO 0 Full Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[3] |RF0LL |Rx FIFO 0 Message Lost Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[4] |RF1NL |Rx FIFO 1 New Message Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[5] |RF1WL |Rx FIFO 1 Watermark Reached Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[6] |RF1FL |Rx FIFO 1 Full Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[7] |RF1LL |Rx FIFO 1 Message Lost Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[8] |HPML |High Priority Message Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[9] |TCL |Transmission Completed Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[10] |TCFL |Transmission Cancellation Finished Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[11] |TFEL |Tx FIFO Empty Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[12] |TEFNL |Tx Event FIFO New Entry Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[13] |TEFWL |Tx Event FIFO Watermark Reached Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[14] |TEFFL |Tx Event FIFO Full Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[15] |TEFLL |Tx Event FIFO Event Lost Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[16] |TSWL |Timestamp Wraparound Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[17] |MRAFL |Message RAM Access Failure Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[18] |TOOL |Timeout Occurred Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[19] |DRXL |Message stored to Dedicated Rx Buffer Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[22] |ELOL |Error Logging Overflow Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[23] |EPL |Error Passive Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[24] |EWL |Warning Status Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[25] |BOL |Bus_Off Status Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[26] |WDIL |Watchdog Interrupt Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[27] |PEAL |Protocol Error in Arbitration Phase Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[28] |PEDL |Protocol Error in Data Phase Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * |[29] |ARAL |Access to Reserved Address Line + * | | |0 = Interrupt assigned to CAN interrupt line 0. + * | | |1 = Interrupt assigned to CAN interrupt line 1. + * @var CANFD_T::ILE + * Offset: 0x5C Interrupt Line Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ENT0 |Enable Interrupt Line 0 + * | | |0 = Interrupt line canfd_int0 disabled. + * | | |1 = Interrupt line canfd_int0 enabled. + * |[1] |ENT1 |Enable Interrupt Line 1 + * | | |0 = Interrupt line canfd_int1 disabled. + * | | |1 = Interrupt line canfd_int1 enabled. + * @var CANFD_T::GFC + * Offset: 0x80 Global Filter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RRFE |Reject Remote Frames Extended + * | | |0= Filter remote frames with 29-bit extended IDs. + * | | |1= Reject all remote frames with 29-bit extended IDs. + * |[1] |RRFS |Reject Remote Frames Standard + * | | |0= Filter remote frames with 11-bit standard IDs. + * | | |1= Reject all remote frames with 11-bit standard IDs. + * |[3:2] |ANFE |Accept Non-matching Frames Extended + * | | |Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. + * | | |00 = Accept in Rx FIFO 0. + * | | |01 = Accept in Rx FIFO 1. + * | | |10 = Reject. + * | | |11 = Reject. + * |[5:4] |ANFS |Accept Non-matching Frames Standard + * | | |Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. + * | | |00 = Accept in Rx FIFO 0. + * | | |01 = Accept in Rx FIFO 1. + * | | |10 = Reject. + * | | |11 = Reject. + * @var CANFD_T::SIDFC + * Offset: 0x84 Standard ID Filter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |FLSSA |Filter List Standard Start Address + * | | |Start address of standard Message ID filter list (32-bit word address, refer to Figure 1.1-11). + * |[23:16] |LSS |List Size Standard + * | | |0= No standard Message ID filter. + * | | |1-128 = Number of standard Message ID filter elements. + * | | |>128= Values greater than 128 are interpreted as 128. + * @var CANFD_T::XIDFC + * Offset: 0x88 Extended ID Filter Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |FLESA |Filter List Extended Start Address + * | | |Start address of extended Message ID filter list (32-bit word address, refer to Figure 1.1-11). + * |[22:16] |LSE |List Size Extended + * | | |0= No extended Message ID filter. + * | | |1-64= Number of extended Message ID filter elements. + * | | |>64= Values greater than 64 are interpreted as 64. + * @var CANFD_T::XIDAM + * Offset: 0x90 Extended ID AND Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |EIDM |Extended ID Mask + * | | |For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. + * | | |Intended for masking of 29-bit IDs in SAE J1939. + * | | |With the reset value of all bits set to one the mask is not active. + * | | |Note: These are protected write bits, write access is possible only when bit CCE and bit INIT of CANFD_CCCR register are set to 1. + * @var CANFD_T::HPMS + * Offset: 0x94 High Priority Message Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BIDX |Buffer Index + * | | |Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = 1. + * |[7:6] |MSI |Message Storage Indicator + * | | |00 = No FIFO selected. + * | | |01 = FIFO message lost. + * | | |10 = Message stored in FIFO 0. + * | | |11 = Message stored in FIFO 1. + * |[14:8] |FIDX |Filter Index + * | | |Index of matching filter element. Range is 0 to CANFD_SIDFC.LSS - 1 respor. CANFD_XIDFC.LSE - 1. + * |[15] |FLST |Filter List + * | | |Indicates the filter list of the matching filter element. + * | | |0 = Standard Filter List. + * | | |1 = Extended Filter List. + * @var CANFD_T::NDAT1 + * Offset: 0x98 New Data 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NDn |New Data + * | | |The register holds the New Data flags of Rx Buffers 0 to 31. + * | | |The flags are set when the respective Rx Buffer has been updated from a received frame. + * | | |The flags remain set until the Host clears them. + * | | |A flag is cleared by writing a 1 to the corresponding bit position. + * | | |Writing a 0 has no effect.A hard reset will clear the register. + * | | |0 = Rx Buffer not updated. + * | | |1 = Rx Buffer updated from new message. + * @var CANFD_T::NDAT2 + * Offset: 0x9C New Data 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |NDn |New Data + * | | |The register holds the New Data flags of Rx Buffers 32 to 63. + * | | |The flags are set when the respective Rx Buffer has been updated from a received frame. + * | | |The flags remain set until the Host clears them. + * | | |A flag is cleared by writing a 1 to the corresponding bit position. + * | | |Writing a 0 has no effect.A hard reset will clear the register. + * | | |0 = Rx Buffer not updated. + * | | |1 = Rx Buffer updated from new message. + * @var CANFD_T::RXF0C + * Offset: 0xA0 Rx FIFO 0 Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |F0SA |Rx FIFO 0 Start Address + * | | |Start address of Rx FIFO 0 in Message RAM (32-bit word address). + * |[22:16] |F0S |Rx FIFO 0 Size + * | | |0= No Rx FIFO 0. + * | | |1-64= Number of Rx FIFO 0 elements. + * | | |>64= Values greater than 64 are interpreted as 64. + * | | |The Rx FIFO 0 elements are indexed from 0 to F0S-1. + * |[30:24] |F0WM |Rx FIFO 0 Watermark + * | | |0= Watermark interrupt disabled + * | | |1-64 = Level for Rx FIFO 0 watermark interrupt (CANFD_IR.RF0W). + * | | |>64 = Watermark interrupt disabled. + * |[31] |F0OM |FIFO 0 Operation Mode + * | | |FIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs). + * | | |0 = FIFO 0 blocking mode. + * | | |1 = FIFO 0 overwrite mode. + * @var CANFD_T::RXF0S + * Offset: 0xA4 Rx FIFO 0 Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |F0FL |Rx FIFO 0 Fill Level + * | | |Number of elements stored in Rx FIFO 0, range 0 to 64. + * |[13:8] |F0GI |Rx FIFO 0 Get Index + * | | |Rx FIFO 0 read index pointer, range 0 to 63. + * |[21:16] |F0PI |Rx FIFO 0 Put Index + * | | |Rx FIFO 0 write index pointer, range 0 to 63. + * |[24] |F0F |Rx FIFO 0 Full + * | | |0= Rx FIFO 0 not full. + * | | |1= Rx FIFO 0 full. + * |[25] |RF0L |Rx FIFO 0 Message Lost + * | | |This bit is a copy of interrupt flag CANFD_IR.RF0L. + * | | |When CANFD_IR.RF0L is reset, this bit is also reset. + * | | |0 = No Rx FIFO 0 message lost. + * | | |1 = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero. + * | | |Note: Overwriting the oldest message when F0OM (CANFD_RXF0C[31]) = 1 will not set this flag. + * @var CANFD_T::RXF0A + * Offset: 0xA8 Rx FIFO 0 Acknowledge + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |F0A |Rx FIFO 0 Acknowledge Index + * | | |After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. + * | | |This will set the Rx FIFO 0 Get Index F0GI (CANFD_RXF0S[13:8]) to F0AI (CANFD_RXF0A[5:0]) + 1 and update the FIFO 0 Fill Level CANFD_RXF0S.F0FL. + * @var CANFD_T::RXBC + * Offset: 0xAC Rx Buffer Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |RBSA |Rx Buffer Start Address + * | | |Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address). + * @var CANFD_T::RXF1C + * Offset: 0xB0 Rx FIFO 1 Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |F1SA |Rx FIFO 1 Start Address + * | | |Start address of Rx FIFO 1 in Message RAM (32-bit word address, refer to Figure 1.1-11). + * |[22:16] |F1S |Rx FIFO 1 Size. + * | | |0= No Rx FIFO 1. + * | | |1-64 = Number of Rx FIFO 1 elements. + * | | |>64 = Values greater than 64 are interpreted as 64. + * | | |The Rx FIFO 1 elements are indexed from 0 to F1S - 1. + * |[30:24] |F1WM |Rx FIFO 1 Watermark + * | | |0= Watermark interrupt disabled. + * | | |1-64 = Level for Rx FIFO 1 watermark interrupt (CANFD_IR.RF1W). + * | | |>64 = Watermark interrupt disabled. + * |[31] |F1OM |FIFO 1 Operation Mode. + * | | |FIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs). + * | | |0= FIFO 1 blocking mode. + * | | |1= FIFO 1 overwrite mode. + * @var CANFD_T::RXF1S + * Offset: 0xB4 Rx FIFO 1 Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |F1FL |Rx FIFO 1 Fill Level + * | | |Number of elements stored in Rx FIFO 1, range 0 to 64. + * |[13:8] |F1G |Rx FIFO 1 Get Index + * | | |Rx FIFO 1 read index pointer, range 0 to 63. + * |[21:16] |F1P |Rx FIFO 1 Fill Level + * | | |Number of elements stored in Rx FIFO 1, range 0 to 64. + * |[24] |F1F |Rx FIFO 1 Full + * | | |0 = Rx FIFO 1 not full. + * | | |1 = Rx FIFO 1 full. + * |[25] |RF1L |Rx FIFO 1 Message Lost + * | | |This bit is a copy of interrupt flag CANFD_IR.RF1L. + * | | |When CANFD_IR.RF1L is reset, this bit is also reset. + * | | |0= No Rx FIFO 1 message lost. + * | | |1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero. + * | | |Note: Overwriting the oldest message when F1OM (CANFD_RXF1C[31]) = 1 will not set this flag. + * @var CANFD_T::RXF1A + * Offset: 0xB8 Rx FIFO 1 Acknowledge + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |F1A |Rx FIFO 1 Acknowledge Index + * | | |After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. + * | | |This will set the Rx FIFO 1 Get Index F1GI (CANFD_RXF1S[13:8]) to F1AI (CANFD_RXF1A[5:0]) + 1 and update the FIFO 1 Fill Level F1FL (CANFD_RXF1S[6:0]). + * @var CANFD_T::RXESC + * Offset: 0xBC Rx Buffer / FIFO Element Size Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |F0DS |Rx FIFO 0 Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * | | |Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer resp Rx FIFO element. + * | | |The rest of the frame data field is ignored. + * |[6:4] |F1DS |Rx FIFO 1 Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * |[10:8] |RBDS |Rx Buffer Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * @var CANFD_T::TXBC + * Offset: 0xC0 Tx Buffer Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |TBSA |Tx Buffers Start Address + * | | |Start address of Tx Buffers section in Message RAM (32-bit word address, refer to Figure 1.1-11). + * | | |Note: Be aware that tThe sum of TFQS and NDTB may be not greater than 32. + * | | |There is no check for erroneous configurations. + * | | |The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. + * |[21:16] |NDTB |Number of Dedicated Transmit Buffers + * | | |0= No Dedicated Tx Buffers. + * | | |1-32= Number of Dedicated Tx Buffers. + * | | |>32= Values greater than 32 are interpreted as 32. + * |[29:24] |TFQS |Transmit FIFO/Queue Size + * | | |0= No Tx FIFO/Queue. + * | | |1-32= Number of Tx Buffers used for Tx FIFO/Queue. + * | | |>32= Values greater than 32 are interpreted as 32. + * |[30] |TFQM |Tx FIFO/Queue Mode + * | | |0= Tx FIFO operation. + * | | |1= Tx Queue operation. + * @var CANFD_T::TXFQS + * Offset: 0xC4 Tx FIFO/Queue Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |TFFL |Tx FIFO Free Level + * | | |Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32 + * | | |Read as zero when Tx Queue operation is configured (TFQM (CANFD_TXBC[3]) = 1). + * | | |Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. + * | | |Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. + * |[12:8] |TFG |Tx FIFO Get Index. + * | | |Tx FIFO read index pointer, range 0 to 31. + * | | |Read as zero when Tx Queue operation is configured (TFQM (CANFD_TXBC[30]) = 1). + * |[20:16] |TFQP |Tx FIFO/Queue Put Index + * | | |Tx FIFO/Queue write index pointer, range 0 to 31. + * |[21] |TFQF |Tx FIFO/Queue Full + * | | |0= Tx FIFO/Queue not full. + * | | |1= Tx FIFO/Queue full. + * @var CANFD_T::TXESC + * Offset: 0xC8 Tx Buffer Element Size Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TBDS |Tx Buffer Data Field Size + * | | |000 = 8 byte data field. + * | | |001 = 12 byte data field. + * | | |010 = 16 byte data field. + * | | |011 = 20 byte data field. + * | | |100 = 24 byte data field. + * | | |101 = 32 byte data field. + * | | |110 = 48 byte data field. + * | | |111 = 64 byte data field. + * | | |Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size CANFD_TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding bytes). + * @var CANFD_T::TXBRP + * Offset: 0xCC Tx Buffer Request Pending + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TRPn |Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register CANFD_TXBAR. The bits are reset after a requested transmission has completed or has been cancelled via register CANFD_TXBCR. + * | | |CANFD_TXBRP bits are set only for those Tx Buffers configured via CANFD_TXBC. + * | | |After a CANFD_TXBRP bit has been set, a Tx scan (refer to 1.1.5.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). + * | | |A cancellation request resets the corresponding transmission request pending bit of register CANFD_TXBRP. + * | | |In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. + * | | |The cancellation request bits are reset directly after the corresponding CANFD_TXBRP bit has been reset. + * | | |After a cancellation has been requested, a finished cancellation is signaled via CANFD_TXBCF. + * | | |- after successful transmission together with the corresponding CANFD_TXBTO bit. + * | | |- when the transmission has not yet been started at the point of cancellation. + * | | |- when the transmission has been aborted due to lost arbitration. + * | | |- when an error occurred during frame transmission. + * | | |In DAR mode all transmissions are automatically cancelled if they are not successful. + * | | |The corresponding CANFD_TXBCF bit is set for all unsuccessful transmissions. + * | | |0 = No transmission request pending. + * | | |1 = Transmission request pending. + * | | |Note: CANFD_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. + * | | |In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding CANFD_TXBRP bit is reset. + * @var CANFD_T::TXBAR + * Offset: 0xD0 Tx Buffer Add Request + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARn |Add Request Each Tx Buffer has its own Add Request bit. Writing a 1 will set the corresponding Add Request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR. CANFD_TXBAR bits are set only for those Tx Buffers configured via CANFD_TXBC. + * | | |When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. + * | | |0 = No transmission request added. + * | | |1 = Transmission requested added. + * | | |Note: If an add request is applied for a Tx Buffer with pending transmission request (corre- sponding CANFD_TXBRP bit already set), this add request is ignored. + * @var CANFD_T::TXBCR + * Offset: 0xD4 Tx Buffer Cancellation Request + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRn |Cancellation Request + * | | |Each Tx Buffer has its own Cancellation Request bit. + * | | |Writing a 1 will set the corresponding Cancellation Request bit; writing a 0 has no impact. + * | | |This enables the Host to set cancellation requests for multiple Tx Buffers with one write to CANFD_TXBCR. + * | | |CANFD_TXBCR bits are set only for those Tx Buffers configured via CANFD_TXBC. + * | | |The bits remain set until the corresponding bit of CANFD_TXBRP is reset. + * | | |0 = No cancellation pending. + * | | |1 = Cancellation pending. + * @var CANFD_T::TXBTO + * Offset: 0xD8 Tx Buffer Transmission Occurred + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TOn |Transmission Occurred + * | | |Each Tx Buffer has its own Transmission Occurred bit. + * | | |The bits are set when the corresponding CANFD_TXBRP bit is cleared after a successful transmission. + * | | |The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR. + * | | |0 = No transmission occurred. + * | | |1 = Transmission occurred. + * @var CANFD_T::TXBCF + * Offset: 0xDC Tx Buffer Cancellation Finished + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CFn |Cancellation Finished + * | | |Each Tx Buffer has its own Cancellation Finished bit. + * | | |The bits are set when the corresponding CANFD_TXBRP bit is cleared after a cancellation was requested via CANFD_TXBCR. + * | | |In case the corresponding CANFD_TXBRP bit was not set at the point of cancellation, CF is set immediately. + * | | |The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register CANFD_TXBAR. + * | | |0 = No transmit buffer cancellation. + * | | |1 = Transmit buffer cancellation finished. + * @var CANFD_T::TXBTIE + * Offset: 0xE0 Tx Buffer Transmission Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TIEn |Transmission Interrupt Enable + * | | |Each Tx Buffer has its own Transmission Interrupt Enable bit. + * | | |0 = Transmission interrupt disabled. + * | | |1 = Transmission interrupt enable. + * @var CANFD_T::TXBCIE + * Offset: 0xE4 Tx Buffer Cancellation Finished Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CFIEn |Cancellation Finished Interrupt Enable + * | | |Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. + * | | |0 = Cancellation finished interrupt disabled. + * | | |1 = Cancellation finished interrupt enabled. + * @var CANFD_T::TXEFC + * Offset: 0xF0 Tx Event FIFO Configuration + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:2] |EFSA |Event FIFO Start Address + * | | |Start address of Tx Event FIFO in Message RAM (32-bit word address, refer to Figure 1.1-11). + * |[21:16] |EFS |Event FIFO Size + * | | |0= Tx Event FIFO disabled. + * | | |1-32= Number of Tx Event FIFO elements. + * | | |>32= Values greater than 32 are interpreted as 32. + * | | |The Tx Event FIFO elements are indexed from 0 to EFS - 1. + * |[29:24] |EFWN |Event FIFO Watermark + * | | |0 = Watermark interrupt disabled. + * | | |1-32= Level for Tx Event FIFO watermark interrupt (TEFW (CANFD_IR[13])). + * | | |>32= Watermark interrupt disabled. + * @var CANFD_T::TXEFS + * Offset: 0xF4 Tx Event FIFO Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |EFFL |Event FIFO Fill Level + * | | |Number of elements stored in Tx Event FIFO, range 0 to 32. + * |[12:8] |EFG |Event FIFO Get Index + * | | |Tx Event FIFO read index pointer, range 0 to 31. + * |[20:16] |EFP |Event FIFO Put Index + * | | |Tx Event FIFO write index pointer, range 0 to 31. + * |[24] |EFF |Event FIFO Full + * | | |0= Tx Event FIFO not full. + * | | |1= Tx Event FIFO full. + * |[25] |TEFL |Tx Event FIFO Element Lost + * | | |This bit is a copy of interrupt flag TEFL (CANFD_IR[15]). + * | | |When TEFL is reset, this bit is also reset. + * | | |0= No Tx Event FIFO element lost. + * | | |1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. + * @var CANFD_T::TXEFA + * Offset: 0xF8 Tx Event FIFO Acknowledge + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |EFA |Event FIFO Acknowledge Index + * | | |After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. + * | | |This will set the Tx Event FIFO Get Index EFGI (CANFD_TXEFS[12:8]) to EFAI + 1 and update the Event FIFO Fill Level EFFL (CANFD_TXEFS[5:0]). + */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DBTP; /*!< [0x000c] Data Bit Timing & Prescaler Register */ + __IO uint32_t TEST; /*!< [0x0010] Test Register */ + __IO uint32_t RWD; /*!< [0x0014] RAM Watchdog */ + __IO uint32_t CCCR; /*!< [0x0018] CC Control Register */ + __IO uint32_t NBTP; /*!< [0x001c] Nominal Bit Timing & Prescaler Register */ + __IO uint32_t TSCC; /*!< [0x0020] Timestamp Counter Configuration */ + __IO uint32_t TSCV; /*!< [0x0024] Timestamp Counter Value */ + __IO uint32_t TOCC; /*!< [0x0028] Timeout Counter Configuration */ + __IO uint32_t TOCV; /*!< [0x002c] Timeout Counter Value */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[4]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t ECR; /*!< [0x0040] Error Counter Register */ + __I uint32_t PSR; /*!< [0x0044] Protocol Status Register */ + __IO uint32_t TDCR; /*!< [0x0048] Transmitter Delay Compensation Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t IR; /*!< [0x0050] Interrupt Register */ + __IO uint32_t IE; /*!< [0x0054] Interrupt Enable */ + __IO uint32_t ILS; /*!< [0x0058] Interrupt Line Select */ + __IO uint32_t ILE; /*!< [0x005c] Interrupt Line Enable */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GFC; /*!< [0x0080] Global Filter Configuration */ + __IO uint32_t SIDFC; /*!< [0x0084] Standard ID Filter Configuration */ + __IO uint32_t XIDFC; /*!< [0x0088] Extended ID Filter Configuration */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t XIDAM; /*!< [0x0090] Extended ID AND Mask */ + __I uint32_t HPMS; /*!< [0x0094] High Priority Message Status */ + __IO uint32_t NDAT1; /*!< [0x0098] New Data 1 */ + __IO uint32_t NDAT2; /*!< [0x009c] New Data 2 */ + __IO uint32_t RXF0C; /*!< [0x00a0] Rx FIFO 0 Configuration */ + __IO uint32_t RXF0S; /*!< [0x00a4] Rx FIFO 0 Status */ + __IO uint32_t RXF0A; /*!< [0x00a8] Rx FIFO 0 Acknowledge */ + __IO uint32_t RXBC; /*!< [0x00ac] Rx Buffer Configuration */ + __IO uint32_t RXF1C; /*!< [0x00b0] Rx FIFO 1 Configuration */ + __IO uint32_t RXF1S; /*!< [0x00b4] Rx FIFO 1 Status */ + __IO uint32_t RXF1A; /*!< [0x00b8] Rx FIFO 1 Acknowledge */ + __IO uint32_t RXESC; /*!< [0x00bc] Rx Buffer / FIFO Element Size Configuration */ + __IO uint32_t TXBC; /*!< [0x00c0] Tx Buffer Configuration */ + __IO uint32_t TXFQS; /*!< [0x00c4] Tx FIFO/Queue Status */ + __IO uint32_t TXESC; /*!< [0x00c8] Tx Buffer Element Size Configuration */ + __IO uint32_t TXBRP; /*!< [0x00cc] Tx Buffer Request Pending */ + __IO uint32_t TXBAR; /*!< [0x00d0] Tx Buffer Add Request */ + __IO uint32_t TXBCR; /*!< [0x00d4] Tx Buffer Cancellation Request */ + __IO uint32_t TXBTO; /*!< [0x00d8] Tx Buffer Transmission Occurred */ + __IO uint32_t TXBCF; /*!< [0x00dc] Tx Buffer Cancellation Finished */ + __IO uint32_t TXBTIE; /*!< [0x00e0] Tx Buffer Transmission Interrupt Enable */ + __IO uint32_t TXBCIE; /*!< [0x00e4] Tx Buffer Cancellation Finished Interrupt Enable */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TXEFC; /*!< [0x00f0] Tx Event FIFO Configuration */ + __IO uint32_t TXEFS; /*!< [0x00f4] Tx Event FIFO Status */ + __IO uint32_t TXEFA; /*!< [0x00f8] Tx Event FIFO Acknowledge */ + +} CANFD_T; + +/** + @addtogroup CANFD_CONST CAN FD Bit Field Definition + Constant Definitions for CAN FD Controller +@{ */ + +#define CANFD_DBTP_DSJW_Pos (0) /*!< CANFD_T::DBTP: DSJW Position */ +#define CANFD_DBTP_DSJW_Msk (0xful << CANFD_DBTP_DSJW_Pos) /*!< CANFD_T::DBTP: DSJW Mask */ + +#define CANFD_DBTP_DTSEG2_Pos (4) /*!< CANFD_T::DBTP: DTSEG2 Position */ +#define CANFD_DBTP_DTSEG2_Msk (0xful << CANFD_DBTP_DTSEG2_Pos) /*!< CANFD_T::DBTP: DTSEG2 Mask */ + +#define CANFD_DBTP_DTSEG1_Pos (8) /*!< CANFD_T::DBTP: DTSEG1 Position */ +#define CANFD_DBTP_DTSEG1_Msk (0x1ful << CANFD_DBTP_DTSEG1_Pos) /*!< CANFD_T::DBTP: DTSEG1 Mask */ + +#define CANFD_DBTP_DBRP_Pos (16) /*!< CANFD_T::DBTP: DBRP Position */ +#define CANFD_DBTP_DBRP_Msk (0x1ful << CANFD_DBTP_DBRP_Pos) /*!< CANFD_T::DBTP: DBRP Mask */ + +#define CANFD_DBTP_TDC_Pos (23) /*!< CANFD_T::DBTP: TDC Position */ +#define CANFD_DBTP_TDC_Msk (0x1ul << CANFD_DBTP_TDC_Pos) /*!< CANFD_T::DBTP: TDC Mask */ + +#define CANFD_TEST_LBCK_Pos (4) /*!< CANFD_T::TEST: LBCK Position */ +#define CANFD_TEST_LBCK_Msk (0x1ul << CANFD_TEST_LBCK_Pos) /*!< CANFD_T::TEST: LBCK Mask */ + +#define CANFD_TEST_TX_Pos (5) /*!< CANFD_T::TEST: TX Position */ +#define CANFD_TEST_TX_Msk (0x3ul << CANFD_TEST_TX_Pos) /*!< CANFD_T::TEST: TX Mask */ + +#define CANFD_TEST_RX_Pos (7) /*!< CANFD_T::TEST: RX Position */ +#define CANFD_TEST_RX_Msk (0x1ul << CANFD_TEST_RX_Pos) /*!< CANFD_T::TEST: RX Mask */ + +#define CANFD_RWD_WDC_Pos (0) /*!< CANFD_T::RWD: WDC Position */ +#define CANFD_RWD_WDC_Msk (0xfful << CANFD_RWD_WDC_Pos) /*!< CANFD_T::RWD: WDC Mask */ + +#define CANFD_RWD_WDV_Pos (8) /*!< CANFD_T::RWD: WDV Position */ +#define CANFD_RWD_WDV_Msk (0xfful << CANFD_RWD_WDV_Pos) /*!< CANFD_T::RWD: WDV Mask */ + +#define CANFD_CCCR_INIT_Pos (0) /*!< CANFD_T::CCCR: INIT Position */ +#define CANFD_CCCR_INIT_Msk (0x1ul << CANFD_CCCR_INIT_Pos) /*!< CANFD_T::CCCR: INIT Mask */ + +#define CANFD_CCCR_CCE_Pos (1) /*!< CANFD_T::CCCR: CCE Position */ +#define CANFD_CCCR_CCE_Msk (0x1ul << CANFD_CCCR_CCE_Pos) /*!< CANFD_T::CCCR: CCE Mask */ + +#define CANFD_CCCR_ASM_Pos (2) /*!< CANFD_T::CCCR: ASM Position */ +#define CANFD_CCCR_ASM_Msk (0x1ul << CANFD_CCCR_ASM_Pos) /*!< CANFD_T::CCCR: ASM Mask */ + +#define CANFD_CCCR_CSA_Pos (3) /*!< CANFD_T::CCCR: CSA Position */ +#define CANFD_CCCR_CSA_Msk (0x1ul << CANFD_CCCR_CSA_Pos) /*!< CANFD_T::CCCR: CSA Mask */ + +#define CANFD_CCCR_CSR_Pos (4) /*!< CANFD_T::CCCR: CSR Position */ +#define CANFD_CCCR_CSR_Msk (0x1ul << CANFD_CCCR_CSR_Pos) /*!< CANFD_T::CCCR: CSR Mask */ + +#define CANFD_CCCR_MON_Pos (5) /*!< CANFD_T::CCCR: MON Position */ +#define CANFD_CCCR_MON_Msk (0x1ul << CANFD_CCCR_MON_Pos) /*!< CANFD_T::CCCR: MON Mask */ + +#define CANFD_CCCR_DAR_Pos (6) /*!< CANFD_T::CCCR: DAR Position */ +#define CANFD_CCCR_DAR_Msk (0x1ul << CANFD_CCCR_DAR_Pos) /*!< CANFD_T::CCCR: DAR Mask */ + +#define CANFD_CCCR_TEST_Pos (7) /*!< CANFD_T::CCCR: TEST Position */ +#define CANFD_CCCR_TEST_Msk (0x1ul << CANFD_CCCR_TEST_Pos) /*!< CANFD_T::CCCR: TEST Mask */ + +#define CANFD_CCCR_FDOE_Pos (8) /*!< CANFD_T::CCCR: FDOE Position */ +#define CANFD_CCCR_FDOE_Msk (0x1ul << CANFD_CCCR_FDOE_Pos) /*!< CANFD_T::CCCR: FDOE Mask */ + +#define CANFD_CCCR_BRSE_Pos (9) /*!< CANFD_T::CCCR: BRSE Position */ +#define CANFD_CCCR_BRSE_Msk (0x1ul << CANFD_CCCR_BRSE_Pos) /*!< CANFD_T::CCCR: BRSE Mask */ + +#define CANFD_CCCR_PXHD_Pos (12) /*!< CANFD_T::CCCR: PXHD Position */ +#define CANFD_CCCR_PXHD_Msk (0x1ul << CANFD_CCCR_PXHD_Pos) /*!< CANFD_T::CCCR: PXHD Mask */ + +#define CANFD_CCCR_EFBI_Pos (13) /*!< CANFD_T::CCCR: EFBI Position */ +#define CANFD_CCCR_EFBI_Msk (0x1ul << CANFD_CCCR_EFBI_Pos) /*!< CANFD_T::CCCR: EFBI Mask */ + +#define CANFD_CCCR_TXP_Pos (14) /*!< CANFD_T::CCCR: TXP Position */ +#define CANFD_CCCR_TXP_Msk (0x1ul << CANFD_CCCR_TXP_Pos) /*!< CANFD_T::CCCR: TXP Mask */ + +#define CANFD_CCCR_NISO_Pos (15) /*!< CANFD_T::CCCR: NISO Position */ +#define CANFD_CCCR_NISO_Msk (0x1ul << CANFD_CCCR_NISO_Pos) /*!< CANFD_T::CCCR: NISO Mask */ + +#define CANFD_NBTP_NTSEG2_Pos (0) /*!< CANFD_T::NBTP: NTSEG2 Position */ +#define CANFD_NBTP_NTSEG2_Msk (0x7ful << CANFD_NBTP_NTSEG2_Pos) /*!< CANFD_T::NBTP: NTSEG2 Mask */ + +#define CANFD_NBTP_NTSEG1_Pos (8) /*!< CANFD_T::NBTP: NTSEG1 Position */ +#define CANFD_NBTP_NTSEG1_Msk (0xfful << CANFD_NBTP_NTSEG1_Pos) /*!< CANFD_T::NBTP: NTSEG1 Mask */ + +#define CANFD_NBTP_NBRP_Pos (16) /*!< CANFD_T::NBTP: NBRP Position */ +#define CANFD_NBTP_NBRP_Msk (0x1fful << CANFD_NBTP_NBRP_Pos) /*!< CANFD_T::NBTP: NBRP Mask */ + +#define CANFD_NBTP_NSJW_Pos (25) /*!< CANFD_T::NBTP: NSJW Position */ +#define CANFD_NBTP_NSJW_Msk (0x7ful << CANFD_NBTP_NSJW_Pos) /*!< CANFD_T::NBTP: NSJW Mask */ + +#define CANFD_TSCC_TSS_Pos (0) /*!< CANFD_T::TSCC: TSS Position */ +#define CANFD_TSCC_TSS_Msk (0x3ul << CANFD_TSCC_TSS_Pos) /*!< CANFD_T::TSCC: TSS Mask */ + +#define CANFD_TSCC_TCP_Pos (16) /*!< CANFD_T::TSCC: TCP Position */ +#define CANFD_TSCC_TCP_Msk (0xful << CANFD_TSCC_TCP_Pos) /*!< CANFD_T::TSCC: TCP Mask */ + +#define CANFD_TSCV_TSC_Pos (0) /*!< CANFD_T::TSCV: TSC Position */ +#define CANFD_TSCV_TSC_Msk (0xfffful << CANFD_TSCV_TSC_Pos) /*!< CANFD_T::TSCV: TSC Mask */ + +#define CANFD_TOCC_ETOC_Pos (0) /*!< CANFD_T::TOCC: ETOC Position */ +#define CANFD_TOCC_ETOC_Msk (0x1ul << CANFD_TOCC_ETOC_Pos) /*!< CANFD_T::TOCC: ETOC Mask */ + +#define CANFD_TOCC_TOS_Pos (1) /*!< CANFD_T::TOCC: TOS Position */ +#define CANFD_TOCC_TOS_Msk (0x3ul << CANFD_TOCC_TOS_Pos) /*!< CANFD_T::TOCC: TOS Mask */ + +#define CANFD_TOCC_TOP_Pos (16) /*!< CANFD_T::TOCC: TOP Position */ +#define CANFD_TOCC_TOP_Msk (0xfffful << CANFD_TOCC_TOP_Pos) /*!< CANFD_T::TOCC: TOP Mask */ + +#define CANFD_TOCV_TOC_Pos (0) /*!< CANFD_T::TOCV: TOC Position */ +#define CANFD_TOCV_TOC_Msk (0xfffful << CANFD_TOCV_TOC_Pos) /*!< CANFD_T::TOCV: TOC Mask */ + +#define CANFD_ECR_TEC_Pos (0) /*!< CANFD_T::ECR: TEC Position */ +#define CANFD_ECR_TEC_Msk (0xfful << CANFD_ECR_TEC_Pos) /*!< CANFD_T::ECR: TEC Mask */ + +#define CANFD_ECR_REC_Pos (8) /*!< CANFD_T::ECR: REC Position */ +#define CANFD_ECR_REC_Msk (0x7ful << CANFD_ECR_REC_Pos) /*!< CANFD_T::ECR: REC Mask */ + +#define CANFD_ECR_RP_Pos (15) /*!< CANFD_T::ECR: RP Position */ +#define CANFD_ECR_RP_Msk (0x1ul << CANFD_ECR_RP_Pos) /*!< CANFD_T::ECR: RP Mask */ + +#define CANFD_ECR_CEL_Pos (16) /*!< CANFD_T::ECR: CEL Position */ +#define CANFD_ECR_CEL_Msk (0xfful << CANFD_ECR_CEL_Pos) /*!< CANFD_T::ECR: CEL Mask */ + +#define CANFD_PSR_LEC_Pos (0) /*!< CANFD_T::PSR: LEC Position */ +#define CANFD_PSR_LEC_Msk (0x7ul << CANFD_PSR_LEC_Pos) /*!< CANFD_T::PSR: LEC Mask */ + +#define CANFD_PSR_ACT_Pos (3) /*!< CANFD_T::PSR: ACT Position */ +#define CANFD_PSR_ACT_Msk (0x3ul << CANFD_PSR_ACT_Pos) /*!< CANFD_T::PSR: ACT Mask */ + +#define CANFD_PSR_EP_Pos (5) /*!< CANFD_T::PSR: EP Position */ +#define CANFD_PSR_EP_Msk (0x1ul << CANFD_PSR_EP_Pos) /*!< CANFD_T::PSR: EP Mask */ + +#define CANFD_PSR_EW_Pos (6) /*!< CANFD_T::PSR: EW Position */ +#define CANFD_PSR_EW_Msk (0x1ul << CANFD_PSR_EW_Pos) /*!< CANFD_T::PSR: EW Mask */ + +#define CANFD_PSR_BO_Pos (7) /*!< CANFD_T::PSR: BO Position */ +#define CANFD_PSR_BO_Msk (0x1ul << CANFD_PSR_BO_Pos) /*!< CANFD_T::PSR: BO Mask */ + +#define CANFD_PSR_DLEC_Pos (8) /*!< CANFD_T::PSR: DLEC Position */ +#define CANFD_PSR_DLEC_Msk (0x7ul << CANFD_PSR_DLEC_Pos) /*!< CANFD_T::PSR: DLEC Mask */ + +#define CANFD_PSR_RESI_Pos (11) /*!< CANFD_T::PSR: RESI Position */ +#define CANFD_PSR_RESI_Msk (0x1ul << CANFD_PSR_RESI_Pos) /*!< CANFD_T::PSR: RESI Mask */ + +#define CANFD_PSR_RBRS_Pos (12) /*!< CANFD_T::PSR: RBRS Position */ +#define CANFD_PSR_RBRS_Msk (0x1ul << CANFD_PSR_RBRS_Pos) /*!< CANFD_T::PSR: RBRS Mask */ + +#define CANFD_PSR_RFDF_Pos (13) /*!< CANFD_T::PSR: RFDF Position */ +#define CANFD_PSR_RFDF_Msk (0x1ul << CANFD_PSR_RFDF_Pos) /*!< CANFD_T::PSR: RFDF Mask */ + +#define CANFD_PSR_PXE_Pos (14) /*!< CANFD_T::PSR: PXE Position */ +#define CANFD_PSR_PXE_Msk (0x1ul << CANFD_PSR_PXE_Pos) /*!< CANFD_T::PSR: PXE Mask */ + +#define CANFD_PSR_TDCV_Pos (16) /*!< CANFD_T::PSR: TDCV Position */ +#define CANFD_PSR_TDCV_Msk (0x7ful << CANFD_PSR_TDCV_Pos) /*!< CANFD_T::PSR: TDCV Mask */ + +#define CANFD_TDCR_TDCF_Pos (0) /*!< CANFD_T::TDCR: TDCF Position */ +#define CANFD_TDCR_TDCF_Msk (0x7ful << CANFD_TDCR_TDCF_Pos) /*!< CANFD_T::TDCR: TDCF Mask */ + +#define CANFD_TDCR_TDCO_Pos (8) /*!< CANFD_T::TDCR: TDCO Position */ +#define CANFD_TDCR_TDCO_Msk (0x7ful << CANFD_TDCR_TDCO_Pos) /*!< CANFD_T::TDCR: TDCO Mask */ + +#define CANFD_IR_RF0N_Pos (0) /*!< CANFD_T::IR: RF0N Position */ +#define CANFD_IR_RF0N_Msk (0x1ul << CANFD_IR_RF0N_Pos) /*!< CANFD_T::IR: RF0N Mask */ + +#define CANFD_IR_RF0W_Pos (1) /*!< CANFD_T::IR: RF0W Position */ +#define CANFD_IR_RF0W_Msk (0x1ul << CANFD_IR_RF0W_Pos) /*!< CANFD_T::IR: RF0W Mask */ + +#define CANFD_IR_RF0F_Pos (2) /*!< CANFD_T::IR: RF0F Position */ +#define CANFD_IR_RF0F_Msk (0x1ul << CANFD_IR_RF0F_Pos) /*!< CANFD_T::IR: RF0F Mask */ + +#define CANFD_IR_RF0L_Pos (3) /*!< CANFD_T::IR: RF0L Position */ +#define CANFD_IR_RF0L_Msk (0x1ul << CANFD_IR_RF0L_Pos) /*!< CANFD_T::IR: RF0L Mask */ + +#define CANFD_IR_RF1N_Pos (4) /*!< CANFD_T::IR: RF1N Position */ +#define CANFD_IR_RF1N_Msk (0x1ul << CANFD_IR_RF1N_Pos) /*!< CANFD_T::IR: RF1N Mask */ + +#define CANFD_IR_RF1W_Pos (5) /*!< CANFD_T::IR: RF1W Position */ +#define CANFD_IR_RF1W_Msk (0x1ul << CANFD_IR_RF1W_Pos) /*!< CANFD_T::IR: RF1W Mask */ + +#define CANFD_IR_RF1F_Pos (6) /*!< CANFD_T::IR: RF1F Position */ +#define CANFD_IR_RF1F_Msk (0x1ul << CANFD_IR_RF1F_Pos) /*!< CANFD_T::IR: RF1F Mask */ + +#define CANFD_IR_RF1L_Pos (7) /*!< CANFD_T::IR: RF1L Position */ +#define CANFD_IR_RF1L_Msk (0x1ul << CANFD_IR_RF1L_Pos) /*!< CANFD_T::IR: RF1L Mask */ + +#define CANFD_IR_HPM_Pos (8) /*!< CANFD_T::IR: HPM Position */ +#define CANFD_IR_HPM_Msk (0x1ul << CANFD_IR_HPM_Pos) /*!< CANFD_T::IR: HPM Mask */ + +#define CANFD_IR_TC_Pos (9) /*!< CANFD_T::IR: TC Position */ +#define CANFD_IR_TC_Msk (0x1ul << CANFD_IR_TC_Pos) /*!< CANFD_T::IR: TC Mask */ + +#define CANFD_IR_TCF_Pos (10) /*!< CANFD_T::IR: TCF Position */ +#define CANFD_IR_TCF_Msk (0x1ul << CANFD_IR_TCF_Pos) /*!< CANFD_T::IR: TCF Mask */ + +#define CANFD_IR_TFE_Pos (11) /*!< CANFD_T::IR: TFE Position */ +#define CANFD_IR_TFE_Msk (0x1ul << CANFD_IR_TFE_Pos) /*!< CANFD_T::IR: TFE Mask */ + +#define CANFD_IR_TEFN_Pos (12) /*!< CANFD_T::IR: TEFN Position */ +#define CANFD_IR_TEFN_Msk (0x1ul << CANFD_IR_TEFN_Pos) /*!< CANFD_T::IR: TEFN Mask */ + +#define CANFD_IR_TEFW_Pos (13) /*!< CANFD_T::IR: TEFW Position */ +#define CANFD_IR_TEFW_Msk (0x1ul << CANFD_IR_TEFW_Pos) /*!< CANFD_T::IR: TEFW Mask */ + +#define CANFD_IR_TEFF_Pos (14) /*!< CANFD_T::IR: TEFF Position */ +#define CANFD_IR_TEFF_Msk (0x1ul << CANFD_IR_TEFF_Pos) /*!< CANFD_T::IR: TEFF Mask */ + +#define CANFD_IR_TEFL_Pos (15) /*!< CANFD_T::IR: TEFL Position */ +#define CANFD_IR_TEFL_Msk (0x1ul << CANFD_IR_TEFL_Pos) /*!< CANFD_T::IR: TEFL Mask */ + +#define CANFD_IR_TSW_Pos (16) /*!< CANFD_T::IR: TSW Position */ +#define CANFD_IR_TSW_Msk (0x1ul << CANFD_IR_TSW_Pos) /*!< CANFD_T::IR: TSW Mask */ + +#define CANFD_IR_MRAF_Pos (17) /*!< CANFD_T::IR: MRAF Position */ +#define CANFD_IR_MRAF_Msk (0x1ul << CANFD_IR_MRAF_Pos) /*!< CANFD_T::IR: MRAF Mask */ + +#define CANFD_IR_TOO_Pos (18) /*!< CANFD_T::IR: TOO Position */ +#define CANFD_IR_TOO_Msk (0x1ul << CANFD_IR_TOO_Pos) /*!< CANFD_T::IR: TOO Mask */ + +#define CANFD_IR_DRX_Pos (19) /*!< CANFD_T::IR: DRX Position */ +#define CANFD_IR_DRX_Msk (0x1ul << CANFD_IR_DRX_Pos) /*!< CANFD_T::IR: DRX Mask */ + +#define CANFD_IR_ELO_Pos (22) /*!< CANFD_T::IR: ELO Position */ +#define CANFD_IR_ELO_Msk (0x1ul << CANFD_IR_ELO_Pos) /*!< CANFD_T::IR: ELO Mask */ + +#define CANFD_IR_EP_Pos (23) /*!< CANFD_T::IR: EP Position */ +#define CANFD_IR_EP_Msk (0x1ul << CANFD_IR_EP_Pos) /*!< CANFD_T::IR: EP Mask */ + +#define CANFD_IR_EW_Pos (24) /*!< CANFD_T::IR: EW Position */ +#define CANFD_IR_EW_Msk (0x1ul << CANFD_IR_EW_Pos) /*!< CANFD_T::IR: EW Mask */ + +#define CANFD_IR_BO_Pos (25) /*!< CANFD_T::IR: BO Position */ +#define CANFD_IR_BO_Msk (0x1ul << CANFD_IR_BO_Pos) /*!< CANFD_T::IR: BO Mask */ + +#define CANFD_IR_WDI_Pos (26) /*!< CANFD_T::IR: WDI Position */ +#define CANFD_IR_WDI_Msk (0x1ul << CANFD_IR_WDI_Pos) /*!< CANFD_T::IR: WDI Mask */ + +#define CANFD_IR_PEA_Pos (27) /*!< CANFD_T::IR: PEA Position */ +#define CANFD_IR_PEA_Msk (0x1ul << CANFD_IR_PEA_Pos) /*!< CANFD_T::IR: PEA Mask */ + +#define CANFD_IR_PED_Pos (28) /*!< CANFD_T::IR: PED Position */ +#define CANFD_IR_PED_Msk (0x1ul << CANFD_IR_PED_Pos) /*!< CANFD_T::IR: PED Mask */ + +#define CANFD_IR_ARA_Pos (29) /*!< CANFD_T::IR: ARA Position */ +#define CANFD_IR_ARA_Msk (0x1ul << CANFD_IR_ARA_Pos) /*!< CANFD_T::IR: ARA Mask */ + +#define CANFD_IE_RF0NE_Pos (0) /*!< CANFD_T::IE: RF0NE Position */ +#define CANFD_IE_RF0NE_Msk (0x1ul << CANFD_IE_RF0NE_Pos) /*!< CANFD_T::IE: RF0NE Mask */ + +#define CANFD_IE_RF0WE_Pos (1) /*!< CANFD_T::IE: RF0WE Position */ +#define CANFD_IE_RF0WE_Msk (0x1ul << CANFD_IE_RF0WE_Pos) /*!< CANFD_T::IE: RF0WE Mask */ + +#define CANFD_IE_RF0FE_Pos (2) /*!< CANFD_T::IE: RF0FE Position */ +#define CANFD_IE_RF0FE_Msk (0x1ul << CANFD_IE_RF0FE_Pos) /*!< CANFD_T::IE: RF0FE Mask */ + +#define CANFD_IE_RF0LE_Pos (3) /*!< CANFD_T::IE: RF0LE Position */ +#define CANFD_IE_RF0LE_Msk (0x1ul << CANFD_IE_RF0LE_Pos) /*!< CANFD_T::IE: RF0LE Mask */ + +#define CANFD_IE_RF1NE_Pos (4) /*!< CANFD_T::IE: RF1NE Position */ +#define CANFD_IE_RF1NE_Msk (0x1ul << CANFD_IE_RF1NE_Pos) /*!< CANFD_T::IE: RF1NE Mask */ + +#define CANFD_IE_RF1WE_Pos (5) /*!< CANFD_T::IE: RF1WE Position */ +#define CANFD_IE_RF1WE_Msk (0x1ul << CANFD_IE_RF1WE_Pos) /*!< CANFD_T::IE: RF1WE Mask */ + +#define CANFD_IE_RF1FE_Pos (6) /*!< CANFD_T::IE: RF1FE Position */ +#define CANFD_IE_RF1FE_Msk (0x1ul << CANFD_IE_RF1FE_Pos) /*!< CANFD_T::IE: RF1FE Mask */ + +#define CANFD_IE_RF1LE_Pos (7) /*!< CANFD_T::IE: RF1LE Position */ +#define CANFD_IE_RF1LE_Msk (0x1ul << CANFD_IE_RF1LE_Pos) /*!< CANFD_T::IE: RF1LE Mask */ + +#define CANFD_IE_HPME_Pos (8) /*!< CANFD_T::IE: HPME Position */ +#define CANFD_IE_HPME_Msk (0x1ul << CANFD_IE_HPME_Pos) /*!< CANFD_T::IE: HPME Mask */ + +#define CANFD_IE_TCE_Pos (9) /*!< CANFD_T::IE: TCE Position */ +#define CANFD_IE_TCE_Msk (0x1ul << CANFD_IE_TCE_Pos) /*!< CANFD_T::IE: TCE Mask */ + +#define CANFD_IE_TCFE_Pos (10) /*!< CANFD_T::IE: TCFE Position */ +#define CANFD_IE_TCFE_Msk (0x1ul << CANFD_IE_TCFE_Pos) /*!< CANFD_T::IE: TCFE Mask */ + +#define CANFD_IE_TFEE_Pos (11) /*!< CANFD_T::IE: TFEE Position */ +#define CANFD_IE_TFEE_Msk (0x1ul << CANFD_IE_TFEE_Pos) /*!< CANFD_T::IE: TFEE Mask */ + +#define CANFD_IE_TEFNE_Pos (12) /*!< CANFD_T::IE: TEFNE Position */ +#define CANFD_IE_TEFNE_Msk (0x1ul << CANFD_IE_TEFNE_Pos) /*!< CANFD_T::IE: TEFNE Mask */ + +#define CANFD_IE_TEFWE_Pos (13) /*!< CANFD_T::IE: TEFWE Position */ +#define CANFD_IE_TEFWE_Msk (0x1ul << CANFD_IE_TEFWE_Pos) /*!< CANFD_T::IE: TEFWE Mask */ + +#define CANFD_IE_TEFFE_Pos (14) /*!< CANFD_T::IE: TEFFE Position */ +#define CANFD_IE_TEFFE_Msk (0x1ul << CANFD_IE_TEFFE_Pos) /*!< CANFD_T::IE: TEFFE Mask */ + +#define CANFD_IE_TEFLE_Pos (15) /*!< CANFD_T::IE: TEFLE Position */ +#define CANFD_IE_TEFLE_Msk (0x1ul << CANFD_IE_TEFLE_Pos) /*!< CANFD_T::IE: TEFLE Mask */ + +#define CANFD_IE_TSWE_Pos (16) /*!< CANFD_T::IE: TSWE Position */ +#define CANFD_IE_TSWE_Msk (0x1ul << CANFD_IE_TSWE_Pos) /*!< CANFD_T::IE: TSWE Mask */ + +#define CANFD_IE_MRAFE_Pos (17) /*!< CANFD_T::IE: MRAFE Position */ +#define CANFD_IE_MRAFE_Msk (0x1ul << CANFD_IE_MRAFE_Pos) /*!< CANFD_T::IE: MRAFE Mask */ + +#define CANFD_IE_TOOE_Pos (18) /*!< CANFD_T::IE: TOOE Position */ +#define CANFD_IE_TOOE_Msk (0x1ul << CANFD_IE_TOOE_Pos) /*!< CANFD_T::IE: TOOE Mask */ + +#define CANFD_IE_DRXE_Pos (19) /*!< CANFD_T::IE: DRXE Position */ +#define CANFD_IE_DRXE_Msk (0x1ul << CANFD_IE_DRXE_Pos) /*!< CANFD_T::IE: DRXE Mask */ + +#define CANFD_IE_BECE_Pos (20) /*!< CANFD_T::IE: BECE Position */ +#define CANFD_IE_BECE_Msk (0x1ul << CANFD_IE_BECE_Pos) /*!< CANFD_T::IE: BECE Mask */ + +#define CANFD_IE_BEUE_Pos (21) /*!< CANFD_T::IE: BEUE Position */ +#define CANFD_IE_BEUE_Msk (0x1ul << CANFD_IE_BEUE_Pos) /*!< CANFD_T::IE: BEUE Mask */ + +#define CANFD_IE_ELOE_Pos (22) /*!< CANFD_T::IE: ELOE Position */ +#define CANFD_IE_ELOE_Msk (0x1ul << CANFD_IE_ELOE_Pos) /*!< CANFD_T::IE: ELOE Mask */ + +#define CANFD_IE_EPE_Pos (23) /*!< CANFD_T::IE: EPE Position */ +#define CANFD_IE_EPE_Msk (0x1ul << CANFD_IE_EPE_Pos) /*!< CANFD_T::IE: EPE Mask */ + +#define CANFD_IE_EWE_Pos (24) /*!< CANFD_T::IE: EWE Position */ +#define CANFD_IE_EWE_Msk (0x1ul << CANFD_IE_EWE_Pos) /*!< CANFD_T::IE: EWE Mask */ + +#define CANFD_IE_BOE_Pos (25) /*!< CANFD_T::IE: BOE Position */ +#define CANFD_IE_BOE_Msk (0x1ul << CANFD_IE_BOE_Pos) /*!< CANFD_T::IE: BOE Mask */ + +#define CANFD_IE_WDIE_Pos (26) /*!< CANFD_T::IE: WDIE Position */ +#define CANFD_IE_WDIE_Msk (0x1ul << CANFD_IE_WDIE_Pos) /*!< CANFD_T::IE: WDIE Mask */ + +#define CANFD_IE_PEAE_Pos (27) /*!< CANFD_T::IE: PEAE Position */ +#define CANFD_IE_PEAE_Msk (0x1ul << CANFD_IE_PEAE_Pos) /*!< CANFD_T::IE: PEAE Mask */ + +#define CANFD_IE_PEDE_Pos (28) /*!< CANFD_T::IE: PEDE Position */ +#define CANFD_IE_PEDE_Msk (0x1ul << CANFD_IE_PEDE_Pos) /*!< CANFD_T::IE: PEDE Mask */ + +#define CANFD_IE_ARAE_Pos (29) /*!< CANFD_T::IE: ARAE Position */ +#define CANFD_IE_ARAE_Msk (0x1ul << CANFD_IE_ARAE_Pos) /*!< CANFD_T::IE: ARAE Mask */ + +#define CANFD_ILS_RF0NL_Pos (0) /*!< CANFD_T::ILS: RF0NL Position */ +#define CANFD_ILS_RF0NL_Msk (0x1ul << CANFD_ILS_RF0NL_Pos) /*!< CANFD_T::ILS: RF0NL Mask */ + +#define CANFD_ILS_RF0WL_Pos (1) /*!< CANFD_T::ILS: RF0WL Position */ +#define CANFD_ILS_RF0WL_Msk (0x1ul << CANFD_ILS_RF0WL_Pos) /*!< CANFD_T::ILS: RF0WL Mask */ + +#define CANFD_ILS_RF0FL_Pos (2) /*!< CANFD_T::ILS: RF0FL Position */ +#define CANFD_ILS_RF0FL_Msk (0x1ul << CANFD_ILS_RF0FL_Pos) /*!< CANFD_T::ILS: RF0FL Mask */ + +#define CANFD_ILS_RF0LL_Pos (3) /*!< CANFD_T::ILS: RF0LL Position */ +#define CANFD_ILS_RF0LL_Msk (0x1ul << CANFD_ILS_RF0LL_Pos) /*!< CANFD_T::ILS: RF0LL Mask */ + +#define CANFD_ILS_RF1NL_Pos (4) /*!< CANFD_T::ILS: RF1NL Position */ +#define CANFD_ILS_RF1NL_Msk (0x1ul << CANFD_ILS_RF1NL_Pos) /*!< CANFD_T::ILS: RF1NL Mask */ + +#define CANFD_ILS_RF1WL_Pos (5) /*!< CANFD_T::ILS: RF1WL Position */ +#define CANFD_ILS_RF1WL_Msk (0x1ul << CANFD_ILS_RF1WL_Pos) /*!< CANFD_T::ILS: RF1WL Mask */ + +#define CANFD_ILS_RF1FL_Pos (6) /*!< CANFD_T::ILS: RF1FL Position */ +#define CANFD_ILS_RF1FL_Msk (0x1ul << CANFD_ILS_RF1FL_Pos) /*!< CANFD_T::ILS: RF1FL Mask */ + +#define CANFD_ILS_RF1LL_Pos (7) /*!< CANFD_T::ILS: RF1LL Position */ +#define CANFD_ILS_RF1LL_Msk (0x1ul << CANFD_ILS_RF1LL_Pos) /*!< CANFD_T::ILS: RF1LL Mask */ + +#define CANFD_ILS_HPML_Pos (8) /*!< CANFD_T::ILS: HPML Position */ +#define CANFD_ILS_HPML_Msk (0x1ul << CANFD_ILS_HPML_Pos) /*!< CANFD_T::ILS: HPML Mask */ + +#define CANFD_ILS_TCL_Pos (9) /*!< CANFD_T::ILS: TCL Position */ +#define CANFD_ILS_TCL_Msk (0x1ul << CANFD_ILS_TCL_Pos) /*!< CANFD_T::ILS: TCL Mask */ + +#define CANFD_ILS_TCFL_Pos (10) /*!< CANFD_T::ILS: TCFL Position */ +#define CANFD_ILS_TCFL_Msk (0x1ul << CANFD_ILS_TCFL_Pos) /*!< CANFD_T::ILS: TCFL Mask */ + +#define CANFD_ILS_TFEL_Pos (11) /*!< CANFD_T::ILS: TFEL Position */ +#define CANFD_ILS_TFEL_Msk (0x1ul << CANFD_ILS_TFEL_Pos) /*!< CANFD_T::ILS: TFEL Mask */ + +#define CANFD_ILS_TEFNL_Pos (12) /*!< CANFD_T::ILS: TEFNL Position */ +#define CANFD_ILS_TEFNL_Msk (0x1ul << CANFD_ILS_TEFNL_Pos) /*!< CANFD_T::ILS: TEFNL Mask */ + +#define CANFD_ILS_TEFWL_Pos (13) /*!< CANFD_T::ILS: TEFWL Position */ +#define CANFD_ILS_TEFWL_Msk (0x1ul << CANFD_ILS_TEFWL_Pos) /*!< CANFD_T::ILS: TEFWL Mask */ + +#define CANFD_ILS_TEFFL_Pos (14) /*!< CANFD_T::ILS: TEFFL Position */ +#define CANFD_ILS_TEFFL_Msk (0x1ul << CANFD_ILS_TEFFL_Pos) /*!< CANFD_T::ILS: TEFFL Mask */ + +#define CANFD_ILS_TEFLL_Pos (15) /*!< CANFD_T::ILS: TEFLL Position */ +#define CANFD_ILS_TEFLL_Msk (0x1ul << CANFD_ILS_TEFLL_Pos) /*!< CANFD_T::ILS: TEFLL Mask */ + +#define CANFD_ILS_TSWL_Pos (16) /*!< CANFD_T::ILS: TSWL Position */ +#define CANFD_ILS_TSWL_Msk (0x1ul << CANFD_ILS_TSWL_Pos) /*!< CANFD_T::ILS: TSWL Mask */ + +#define CANFD_ILS_MRAFL_Pos (17) /*!< CANFD_T::ILS: MRAFL Position */ +#define CANFD_ILS_MRAFL_Msk (0x1ul << CANFD_ILS_MRAFL_Pos) /*!< CANFD_T::ILS: MRAFL Mask */ + +#define CANFD_ILS_TOOL_Pos (18) /*!< CANFD_T::ILS: TOOL Position */ +#define CANFD_ILS_TOOL_Msk (0x1ul << CANFD_ILS_TOOL_Pos) /*!< CANFD_T::ILS: TOOL Mask */ + +#define CANFD_ILS_DRXL_Pos (19) /*!< CANFD_T::ILS: DRXL Position */ +#define CANFD_ILS_DRXL_Msk (0x1ul << CANFD_ILS_DRXL_Pos) /*!< CANFD_T::ILS: DRXL Mask */ + +#define CANFD_ILS_ELOL_Pos (22) /*!< CANFD_T::ILS: ELOL Position */ +#define CANFD_ILS_ELOL_Msk (0x1ul << CANFD_ILS_ELOL_Pos) /*!< CANFD_T::ILS: ELOL Mask */ + +#define CANFD_ILS_EPL_Pos (23) /*!< CANFD_T::ILS: EPL Position */ +#define CANFD_ILS_EPL_Msk (0x1ul << CANFD_ILS_EPL_Pos) /*!< CANFD_T::ILS: EPL Mask */ + +#define CANFD_ILS_EWL_Pos (24) /*!< CANFD_T::ILS: EWL Position */ +#define CANFD_ILS_EWL_Msk (0x1ul << CANFD_ILS_EWL_Pos) /*!< CANFD_T::ILS: EWL Mask */ + +#define CANFD_ILS_BOL_Pos (25) /*!< CANFD_T::ILS: BOL Position */ +#define CANFD_ILS_BOL_Msk (0x1ul << CANFD_ILS_BOL_Pos) /*!< CANFD_T::ILS: BOL Mask */ + +#define CANFD_ILS_WDIL_Pos (26) /*!< CANFD_T::ILS: WDIL Position */ +#define CANFD_ILS_WDIL_Msk (0x1ul << CANFD_ILS_WDIL_Pos) /*!< CANFD_T::ILS: WDIL Mask */ + +#define CANFD_ILS_PEAL_Pos (27) /*!< CANFD_T::ILS: PEAL Position */ +#define CANFD_ILS_PEAL_Msk (0x1ul << CANFD_ILS_PEAL_Pos) /*!< CANFD_T::ILS: PEAL Mask */ + +#define CANFD_ILS_PEDL_Pos (28) /*!< CANFD_T::ILS: PEDL Position */ +#define CANFD_ILS_PEDL_Msk (0x1ul << CANFD_ILS_PEDL_Pos) /*!< CANFD_T::ILS: PEDL Mask */ + +#define CANFD_ILS_ARAL_Pos (29) /*!< CANFD_T::ILS: ARAL Position */ +#define CANFD_ILS_ARAL_Msk (0x1ul << CANFD_ILS_ARAL_Pos) /*!< CANFD_T::ILS: ARAL Mask */ + +#define CANFD_ILE_ENT0_Pos (0) /*!< CANFD_T::ILE: ENT0 Position */ +#define CANFD_ILE_ENT0_Msk (0x1ul << CANFD_ILE_ENT0_Pos) /*!< CANFD_T::ILE: ENT0 Mask */ + +#define CANFD_ILE_ENT1_Pos (1) /*!< CANFD_T::ILE: ENT1 Position */ +#define CANFD_ILE_ENT1_Msk (0x1ul << CANFD_ILE_ENT1_Pos) /*!< CANFD_T::ILE: ENT1 Mask */ + +#define CANFD_GFC_RRFE_Pos (0) /*!< CANFD_T::GFC: RRFE Position */ +#define CANFD_GFC_RRFE_Msk (0x1ul << CANFD_GFC_RRFE_Pos) /*!< CANFD_T::GFC: RRFE Mask */ + +#define CANFD_GFC_RRFS_Pos (1) /*!< CANFD_T::GFC: RRFS Position */ +#define CANFD_GFC_RRFS_Msk (0x1ul << CANFD_GFC_RRFS_Pos) /*!< CANFD_T::GFC: RRFS Mask */ + +#define CANFD_GFC_ANFE_Pos (2) /*!< CANFD_T::GFC: ANFE Position */ +#define CANFD_GFC_ANFE_Msk (0x3ul << CANFD_GFC_ANFE_Pos) /*!< CANFD_T::GFC: ANFE Mask */ + +#define CANFD_GFC_ANFS_Pos (4) /*!< CANFD_T::GFC: ANFS Position */ +#define CANFD_GFC_ANFS_Msk (0x3ul << CANFD_GFC_ANFS_Pos) /*!< CANFD_T::GFC: ANFS Mask */ + +#define CANFD_SIDFC_FLSSA_Pos (2) /*!< CANFD_T::SIDFC: FLSSA Position */ +#define CANFD_SIDFC_FLSSA_Msk (0x3ffful << CANFD_SIDFC_FLSSA_Pos) /*!< CANFD_T::SIDFC: FLSSA Mask */ + +#define CANFD_SIDFC_LSS_Pos (16) /*!< CANFD_T::SIDFC: LSS Position */ +#define CANFD_SIDFC_LSS_Msk (0xfful << CANFD_SIDFC_LSS_Pos) /*!< CANFD_T::SIDFC: LSS Mask */ + +#define CANFD_XIDFC_FLESA_Pos (2) /*!< CANFD_T::XIDFC: FLESA Position */ +#define CANFD_XIDFC_FLESA_Msk (0x3ffful << CANFD_XIDFC_FLESA_Pos) /*!< CANFD_T::XIDFC: FLESA Mask */ + +#define CANFD_XIDFC_LSE_Pos (16) /*!< CANFD_T::XIDFC: LSE Position */ +#define CANFD_XIDFC_LSE_Msk (0x7ful << CANFD_XIDFC_LSE_Pos) /*!< CANFD_T::XIDFC: LSE Mask */ + +#define CANFD_XIDAM_EIDM_Pos (0) /*!< CANFD_T::XIDAM: EIDM Position */ +#define CANFD_XIDAM_EIDM_Msk (0x1ffffffful << CANFD_XIDAM_EIDM_Pos) /*!< CANFD_T::XIDAM: EIDM Mask */ + +#define CANFD_HPMS_BIDX_Pos (0) /*!< CANFD_T::HPMS: BIDX Position */ +#define CANFD_HPMS_BIDX_Msk (0x3ful << CANFD_HPMS_BIDX_Pos) /*!< CANFD_T::HPMS: BIDX Mask */ + +#define CANFD_HPMS_MSI_Pos (6) /*!< CANFD_T::HPMS: MSI Position */ +#define CANFD_HPMS_MSI_Msk (0x3ul << CANFD_HPMS_MSI_Pos) /*!< CANFD_T::HPMS: MSI Mask */ + +#define CANFD_HPMS_FIDX_Pos (8) /*!< CANFD_T::HPMS: FIDX Position */ +#define CANFD_HPMS_FIDX_Msk (0x7ful << CANFD_HPMS_FIDX_Pos) /*!< CANFD_T::HPMS: FIDX Mask */ + +#define CANFD_HPMS_FLST_Pos (15) /*!< CANFD_T::HPMS: FLST Position */ +#define CANFD_HPMS_FLST_Msk (0x1ul << CANFD_HPMS_FLST_Pos) /*!< CANFD_T::HPMS: FLST Mask */ + +#define CANFD_NDAT1_NDn_Pos (0) /*!< CANFD_T::NDAT1: NDn Position */ +#define CANFD_NDAT1_NDn_Msk (0xfffffffful << CANFD_NDAT1_NDn_Pos) /*!< CANFD_T::NDAT1: NDn Mask */ + +#define CANFD_NDAT2_NDn_Pos (0) /*!< CANFD_T::NDAT2: NDn Position */ +#define CANFD_NDAT2_NDn_Msk (0xfffffffful << CANFD_NDAT2_NDn_Pos) /*!< CANFD_T::NDAT2: NDn Mask */ + +#define CANFD_RXF0C_F0SA_Pos (2) /*!< CANFD_T::RXF0C: F0SA Position */ +#define CANFD_RXF0C_F0SA_Msk (0x3ffful << CANFD_RXF0C_F0SA_Pos) /*!< CANFD_T::RXF0C: F0SA Mask */ + +#define CANFD_RXF0C_F0S_Pos (16) /*!< CANFD_T::RXF0C: F0S Position */ +#define CANFD_RXF0C_F0S_Msk (0x7ful << CANFD_RXF0C_F0S_Pos) /*!< CANFD_T::RXF0C: F0S Mask */ + +#define CANFD_RXF0C_F0WM_Pos (24) /*!< CANFD_T::RXF0C: F0WM Position */ +#define CANFD_RXF0C_F0WM_Msk (0x7ful << CANFD_RXF0C_F0WM_Pos) /*!< CANFD_T::RXF0C: F0WM Mask */ + +#define CANFD_RXF0C_F0OM_Pos (31) /*!< CANFD_T::RXF0C: F0OM Position */ +#define CANFD_RXF0C_F0OM_Msk (0x1ul << CANFD_RXF0C_F0OM_Pos) /*!< CANFD_T::RXF0C: F0OM Mask */ + +#define CANFD_RXF0S_F0FL_Pos (0) /*!< CANFD_T::RXF0S: F0FL Position */ +#define CANFD_RXF0S_F0FL_Msk (0x7ful << CANFD_RXF0S_F0FL_Pos) /*!< CANFD_T::RXF0S: F0FL Mask */ + +#define CANFD_RXF0S_F0GI_Pos (8) /*!< CANFD_T::RXF0S: F0GI Position */ +#define CANFD_RXF0S_F0GI_Msk (0x3ful << CANFD_RXF0S_F0GI_Pos) /*!< CANFD_T::RXF0S: F0GI Mask */ + +#define CANFD_RXF0S_F0PI_Pos (16) /*!< CANFD_T::RXF0S: F0PI Position */ +#define CANFD_RXF0S_F0PI_Msk (0x3ful << CANFD_RXF0S_F0PI_Pos) /*!< CANFD_T::RXF0S: F0PI Mask */ + +#define CANFD_RXF0S_F0F_Pos (24) /*!< CANFD_T::RXF0S: F0F Position */ +#define CANFD_RXF0S_F0F_Msk (0x1ul << CANFD_RXF0S_F0F_Pos) /*!< CANFD_T::RXF0S: F0F Mask */ + +#define CANFD_RXF0S_RF0L_Pos (25) /*!< CANFD_T::RXF0S: RF0L Position */ +#define CANFD_RXF0S_RF0L_Msk (0x1ul << CANFD_RXF0S_RF0L_Pos) /*!< CANFD_T::RXF0S: RF0L Mask */ + +#define CANFD_RXF0A_F0A_Pos (0) /*!< CANFD_T::RXF0A: F0A Position */ +#define CANFD_RXF0A_F0A_Msk (0x3ful << CANFD_RXF0A_F0A_Pos) /*!< CANFD_T::RXF0A: F0A Mask */ + +#define CANFD_RXBC_RBSA_Pos (2) /*!< CANFD_T::RXBC: RBSA Position */ +#define CANFD_RXBC_RBSA_Msk (0x3ffful << CANFD_RXBC_RBSA_Pos) /*!< CANFD_T::RXBC: RBSA Mask */ + +#define CANFD_RXF1C_F1SA_Pos (2) /*!< CANFD_T::RXF1C: F1SA Position */ +#define CANFD_RXF1C_F1SA_Msk (0x3ffful << CANFD_RXF1C_F1SA_Pos) /*!< CANFD_T::RXF1C: F1SA Mask */ + +#define CANFD_RXF1C_F1S_Pos (16) /*!< CANFD_T::RXF1C: F1S Position */ +#define CANFD_RXF1C_F1S_Msk (0x7ful << CANFD_RXF1C_F1S_Pos) /*!< CANFD_T::RXF1C: F1S Mask */ + +#define CANFD_RXF1C_F1WM_Pos (24) /*!< CANFD_T::RXF1C: F1WM Position */ +#define CANFD_RXF1C_F1WM_Msk (0x7ful << CANFD_RXF1C_F1WM_Pos) /*!< CANFD_T::RXF1C: F1WM Mask */ + +#define CANFD_RXF1C_F1OM_Pos (31) /*!< CANFD_T::RXF1C: F1OM Position */ +#define CANFD_RXF1C_F1OM_Msk (0x1ul << CANFD_RXF1C_F1OM_Pos) /*!< CANFD_T::RXF1C: F1OM Mask */ + +#define CANFD_RXF1S_F1FL_Pos (0) /*!< CANFD_T::RXF1S: F1FL Position */ +#define CANFD_RXF1S_F1FL_Msk (0x7ful << CANFD_RXF1S_F1FL_Pos) /*!< CANFD_T::RXF1S: F1FL Mask */ + +#define CANFD_RXF1S_F1GI_Pos (8) /*!< CANFD_T::RXF1S: F1GI Position */ +#define CANFD_RXF1S_F1GI_Msk (0x3ful << CANFD_RXF1S_F1GI_Pos) /*!< CANFD_T::RXF1S: F1GI Mask */ + +#define CANFD_RXF1S_F1PI_Pos (16) /*!< CANFD_T::RXF1S: F1PI Position */ +#define CANFD_RXF1S_F1PI_Msk (0x3ful << CANFD_RXF1S_F1PI_Pos) /*!< CANFD_T::RXF1S: F1PI Mask */ + +#define CANFD_RXF1S_F1F_Pos (24) /*!< CANFD_T::RXF1S: F1F Position */ +#define CANFD_RXF1S_F1F_Msk (0x1ul << CANFD_RXF1S_F1F_Pos) /*!< CANFD_T::RXF1S: F1F Mask */ + +#define CANFD_RXF1S_RF1L_Pos (25) /*!< CANFD_T::RXF1S: RF1L Position */ +#define CANFD_RXF1S_RF1L_Msk (0x1ul << CANFD_RXF1S_RF1L_Pos) /*!< CANFD_T::RXF1S: RF1L Mask */ + +#define CANFD_RXF1A_F1AI_Pos (0) /*!< CANFD_T::RXF1A: F1AI Position */ +#define CANFD_RXF1A_F1AI_Msk (0x3ful << CANFD_RXF1A_F1AI_Pos) /*!< CANFD_T::RXF1A: F1AI Mask */ + +#define CANFD_RXESC_F0DS_Pos (0) /*!< CANFD_T::RXESC: F0DS Position */ +#define CANFD_RXESC_F0DS_Msk (0x7ul << CANFD_RXESC_F0DS_Pos) /*!< CANFD_T::RXESC: F0DS Mask */ + +#define CANFD_RXESC_F1DS_Pos (4) /*!< CANFD_T::RXESC: F1DS Position */ +#define CANFD_RXESC_F1DS_Msk (0x7ul << CANFD_RXESC_F1DS_Pos) /*!< CANFD_T::RXESC: F1DS Mask */ + +#define CANFD_RXESC_RBDS_Pos (8) /*!< CANFD_T::RXESC: RBDS Position */ +#define CANFD_RXESC_RBDS_Msk (0x7ul << CANFD_RXESC_RBDS_Pos) /*!< CANFD_T::RXESC: RBDS Mask */ + +#define CANFD_TXBC_TBSA_Pos (2) /*!< CANFD_T::TXBC: TBSA Position */ +#define CANFD_TXBC_TBSA_Msk (0x3ffful << CANFD_TXBC_TBSA_Pos) /*!< CANFD_T::TXBC: TBSA Mask */ + +#define CANFD_TXBC_NDTB_Pos (16) /*!< CANFD_T::TXBC: NDTB Position */ +#define CANFD_TXBC_NDTB_Msk (0x3ful << CANFD_TXBC_NDTB_Pos) /*!< CANFD_T::TXBC: NDTB Mask */ + +#define CANFD_TXBC_TFQS_Pos (24) /*!< CANFD_T::TXBC: TFQS Position */ +#define CANFD_TXBC_TFQS_Msk (0x3ful << CANFD_TXBC_TFQS_Pos) /*!< CANFD_T::TXBC: TFQS Mask */ + +#define CANFD_TXBC_TFQM_Pos (30) /*!< CANFD_T::TXBC: TFQM Position */ +#define CANFD_TXBC_TFQM_Msk (0x1ul << CANFD_TXBC_TFQM_Pos) /*!< CANFD_T::TXBC: TFQM Mask */ + +#define CANFD_TXFQS_TFFL_Pos (0) /*!< CANFD_T::TXFQS: TFFL Position */ +#define CANFD_TXFQS_TFFL_Msk (0x3ful << CANFD_TXFQS_TFFL_Pos) /*!< CANFD_T::TXFQS: TFFL Mask */ + +#define CANFD_TXFQS_TFGI_Pos (8) /*!< CANFD_T::TXFQS: TFGI Position */ +#define CANFD_TXFQS_TFGI_Msk (0x1ful << CANFD_TXFQS_TFGI_Pos) /*!< CANFD_T::TXFQS: TFGI Mask */ + +#define CANFD_TXFQS_TFQPI_Pos (16) /*!< CANFD_T::TXFQS: TFQPI Position */ +#define CANFD_TXFQS_TFQPI_Msk (0x1ful << CANFD_TXFQS_TFQPI_Pos) /*!< CANFD_T::TXFQS: TFQPI Mask */ + +#define CANFD_TXFQS_TFQF_Pos (21) /*!< CANFD_T::TXFQS: TFQF Position */ +#define CANFD_TXFQS_TFQF_Msk (0x1ul << CANFD_TXFQS_TFQF_Pos) /*!< CANFD_T::TXFQS: TFQF Mask */ + +#define CANFD_TXESC_TBDS_Pos (0) /*!< CANFD_T::TXESC: TBDS Position */ +#define CANFD_TXESC_TBDS_Msk (0x7ul << CANFD_TXESC_TBDS_Pos) /*!< CANFD_T::TXESC: TBDS Mask */ + +#define CANFD_TXBRP_TRPn_Pos (0) /*!< CANFD_T::TXBRP: TRPn Position */ +#define CANFD_TXBRP_TRPn_Msk (0xfffffffful << CANFD_TXBRP_TRPn_Pos) /*!< CANFD_T::TXBRP: TRPn Mask */ + +#define CANFD_TXBAR_ARn_Pos (0) /*!< CANFD_T::TXBAR: ARn Position */ +#define CANFD_TXBAR_ARn_Msk (0xfffffffful << CANFD_TXBAR_ARn_Pos) /*!< CANFD_T::TXBAR: ARn Mask */ + +#define CANFD_TXBCR_CRn_Pos (0) /*!< CANFD_T::TXBCR: CRn Position */ +#define CANFD_TXBCR_CRn_Msk (0xfffffffful << CANFD_TXBCR_CRn_Pos) /*!< CANFD_T::TXBCR: CRn Mask */ + +#define CANFD_TXBTO_TOn_Pos (0) /*!< CANFD_T::TXBTO: TOn Position */ +#define CANFD_TXBTO_TOn_Msk (0xfffffffful << CANFD_TXBTO_TOn_Pos) /*!< CANFD_T::TXBTO: TOn Mask */ + +#define CANFD_TXBCF_CFn_Pos (0) /*!< CANFD_T::TXBCF: CFn Position */ +#define CANFD_TXBCF_CFn_Msk (0xfffffffful << CANFD_TXBCF_CFn_Pos) /*!< CANFD_T::TXBCF: CFn Mask */ + +#define CANFD_TXBTIE_TIEn_Pos (0) /*!< CANFD_T::TXBTIE: TIEn Position */ +#define CANFD_TXBTIE_TIEn_Msk (0xfffffffful << CANFD_TXBTIE_TIEn_Pos) /*!< CANFD_T::TXBTIE: TIEn Mask */ + +#define CANFD_TXBCIE_CFIEn_Pos (0) /*!< CANFD_T::TXBCIE: CFIEn Position */ +#define CANFD_TXBCIE_CFIEn_Msk (0xfffffffful << CANFD_TXBCIE_CFIEn_Pos) /*!< CANFD_T::TXBCIE: CFIEn Mask */ + +#define CANFD_TXEFC_EFSA_Pos (2) /*!< CANFD_T::TXEFC: EFSA Position */ +#define CANFD_TXEFC_EFSA_Msk (0x3ffful << CANFD_TXEFC_EFSA_Pos) /*!< CANFD_T::TXEFC: EFSA Mask */ + +#define CANFD_TXEFC_EFS_Pos (16) /*!< CANFD_T::TXEFC: EFS Position */ +#define CANFD_TXEFC_EFS_Msk (0x3ful << CANFD_TXEFC_EFS_Pos) /*!< CANFD_T::TXEFC: EFS Mask */ + +#define CANFD_TXEFC_EFWN_Pos (24) /*!< CANFD_T::TXEFC: EFWN Position */ +#define CANFD_TXEFC_EFWN_Msk (0x3ful << CANFD_TXEFC_EFWN_Pos) /*!< CANFD_T::TXEFC: EFWN Mask */ + +#define CANFD_TXEFS_EFFL_Pos (0) /*!< CANFD_T::TXEFS: EFFL Position */ +#define CANFD_TXEFS_EFFL_Msk (0x3ful << CANFD_TXEFS_EFFL_Pos) /*!< CANFD_T::TXEFS: EFFL Mask */ + +#define CANFD_TXEFS_EFGI_Pos (8) /*!< CANFD_T::TXEFS: EFGI Position */ +#define CANFD_TXEFS_EFGI_Msk (0x1ful << CANFD_TXEFS_EFGI_Pos) /*!< CANFD_T::TXEFS: EFGI Mask */ + +#define CANFD_TXEFS_EFPI_Pos (16) /*!< CANFD_T::TXEFS: EFPI Position */ +#define CANFD_TXEFS_EFPI_Msk (0x1ful << CANFD_TXEFS_EFPI_Pos) /*!< CANFD_T::TXEFS: EFPI Mask */ + +#define CANFD_TXEFS_EFF_Pos (24) /*!< CANFD_T::TXEFS: EFF Position */ +#define CANFD_TXEFS_EFF_Msk (0x1ul << CANFD_TXEFS_EFF_Pos) /*!< CANFD_T::TXEFS: EFF Mask */ + +#define CANFD_TXEFS_TEFL_Pos (25) /*!< CANFD_T::TXEFS: TEFL Position */ +#define CANFD_TXEFS_TEFL_Msk (0x1ul << CANFD_TXEFS_TEFL_Pos) /*!< CANFD_T::TXEFS: TEFL Mask */ + +#define CANFD_TXEFA_EFAI_Pos (0) /*!< CANFD_T::TXEFA: EFAI Position */ +#define CANFD_TXEFA_EFAI_Msk (0x1ful << CANFD_TXEFA_EFAI_Pos) /*!< CANFD_T::TXEFA: EFAI Mask */ + +/**@}*/ /* CANFD_CONST */ +/**@}*/ /* end of CANFD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __CANFD_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ccap_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ccap_reg.h new file mode 100644 index 0000000..95e0ca9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ccap_reg.h @@ -0,0 +1,413 @@ +/**************************************************************************//** + * @file ccap_reg.h + * @version V3.00 + * @brief CCAP register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CCAP_REG_H__ +#define __CCAP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CCAP Camera Capture Interface Controller (CCAP) + Memory Mapped Structure for CCAP Controller +@{ */ + + +typedef struct { + + + /** + * @var CCAP_T::CTL + * Offset: 0x00 Camera Capture Interface Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCAPEN |Camera Capture Interface Enable Bit + * | | |0 = Camera Capture Interface Disabled. + * | | |1 = Camera Capture Interface Enabled. + * |[6] |PKTEN |Packet Output Enable Bit + * | | |0 = Packet output Disabled. + * | | |1 = Packet output Enabled. + * |[7] |MONO |Monochrome CMOS Sensor Select + * | | |0 = Color CMOS Sensor. + * | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled. + * |[16] |SHUTTER |Camera Capture Interface Automatically Disable the Capture Interface After a Frame Had Been Captured + * | | |0 = Shutter Disabled. + * | | |1 = Shutter Enabled. + * |[17] |MY4_SWAP |Monochrome CMOS Sensor 4-bit Data Nibble Swap + * | | |0 = The 4-bit data input sequence: 1st Pixel is for 1st Nibble (1st pixel at MSB). + * | | |1 = The 4-bit data input sequence: 1st Pixel is for 2nd Nibble (1st pixel at LSB). + * |[18] |MY8_MY4 |Monochrome CMOS Sensor Data I/O Interface + * | | |0 = Monochrome CMOS sensor is by the 4-bit data I/O interface. + * | | |1 = Monochrome CMOS sensor is by the 8-bit data I/O interface. + * |[19] |Luma_Y_One|Color/Monochrome CMOS Sensor Luminance 8-bit Y to 1-bit Y Conversion + * | | |0 = Color/Monochrome CMOS sensor Luma-Y-One bit Disabled. + * | | |1 = Color/Monochrome CMOS sensor Luma-Y-One bit Enabled. + * | | |Note: Color CMOS sensor U/V components are ignored when the Luma_Y_One is enabled. + * |[20] |UPDATE |Update Register at New Frame + * | | |0 = Update register at new frame Disabled. + * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated). + * |[24] |VPRST |Capture Interface Reset + * | | |0 = Capture interface reset Disabled. + * | | |1 = Capture interface reset Enabled. + * @var CCAP_T::PAR + * Offset: 0x04 Camera Capture Interface Parameter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INFMT |Sensor Input Data Format + * | | |0 = YCbCr422. + * | | |1 = RGB565. + * |[1] |SENTYPE |Sensor Input Type + * | | |0 = CCIR601. + * | | |1 = CCIR656, VSync & Hsync embedded in the data signal. + * |[3:2] |INDATORD |Sensor Input Data Order + * | | |If INFMT (CCAP_PAR[0]) = 0 (YCbCr): + * | | |00 = Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1 V0. + * | | |01 = Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1 U0. + * | | |10 = Sensor input data (Byte 0 1 2 3) is U0 Y0 V0 Y1. + * | | |11 = Sensor input data (Byte 0 1 2 3) is V0 Y0 U0 Y1. + * | | |If INFMT (CCAP_PAR[0]) = 1 (RGB565): + * | | |00 = Sensor input data (Byte 0) is {R[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], B[4:0]}. + * | | |01 = Sensor input data (Byte 0) is {B[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], R[4:0]}. + * | | |10 = Sensor input data (Byte 0) is {G[2:0],B[4:0]}. Sensor input data (Byte 1) is {R[4:0], G[5:3]}. + * | | |11 = Sensor input data (Byte 0) is {G[2:0],R[4:0]}. Sensor input data (Byte 1) is {B[4:0], G[5:3]}. + * |[5:4] |OUTFMT |Image Data Format Output to System Memory + * | | |00 = YCbCr422. + * | | |01 = Only output Y. (Select this format when CCAP_CTL "Luma_Y_One" or "MONO" enabled). + * | | |10 = RGB555. + * | | |11 = RGB565. + * |[6] |RANGE |Scale Input YUV CCIR601 Color Range to Full Range + * | | |0 = Default. + * | | |1 = Scale to full range. + * |[8] |PCLKP |Sensor Pixel Clock Polarity + * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock. + * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock. + * |[9] |HSP |Sensor Hsync Polarity + * | | |0 = Sync Low. + * | | |1 = Sync High. + * |[10] |VSP |Sensor Vsync Polarity + * | | |0 = Sync Low. + * | | |1 = Sync High. + * |[18] |FBB |Field by Blank + * | | |Field by Blank (only in ccir-656 mode) means blanking pixel data(0x80108010) have to transfer to system memory or not. + * | | |0 = Field by blank Disabled. (blank pixel data will transfer to system memory). + * | | |1 = Field by blank Enabled. (only active data will transfer to system memory). + * @var CCAP_T::INT + * Offset: 0x08 Camera Capture Interface Interrupt Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VINTF |Video Frame End Interrupt + * | | |0 = Did not receive a frame completely. + * | | |1 = Received a frame completely. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |MEINTF |Bus Master Transfer Error Interrupt + * | | |0 = Transfer Error did not occur. + * | | |1 = Transfer Error occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |ADDRMINTF |Memory Address Match Interrupt + * | | |0 = Memory Address Match Interrupt did not occur. + * | | |1 = Memory Address Match Interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |VIEN |Video Frame End Interrupt Enable Bit + * | | |0 = Video frame end interrupt Disabled. + * | | |1 = Video frame end interrupt Enabled. + * |[17] |MEIEN |Bus Master Transfer Error Interrupt Enable Bit + * | | |0 = Bus Master Transfer error interrupt Disabled. + * | | |1 = Bus Master Transfer error interrupt Enabled. + * |[19] |ADDRMIEN |Memory Address Match Interrupt Enable Bit + * | | |0 = Memory address match interrupt Disabled. + * | | |1 = Memory address match interrupt Enabled. + * @var CCAP_T::CWSP + * Offset: 0x20 Cropping Window Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CWSADDRH |Cropping Window Horizontal Starting Address + * | | |Specify the value of the cropping window horizontal start address. + * |[26:16] |CWSADDRV |Cropping Window Vertical Starting Address + * | | |Specify the value of the cropping window vertical start address. + * @var CCAP_T::CWS + * Offset: 0x24 Cropping Window Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CWW |Cropping Window Width + * | | |Specify the size of the cropping window width. + * |[26:16] |CWH |Cropping Window Height + * | | |Specify the size of the cropping window height. + * @var CCAP_T::PKTSL + * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PKTSHML |Packet Scaling Horizontal Factor M + * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image width * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[15:8] |PKTSHNL |Packet Scaling Horizontal Factor N + * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor. + * |[23:16] |PKTSVML |Packet Scaling Vertical Factor M + * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor. + * | | |The output image width will be equal to the image height * N/M. + * | | |Note: The value of N must be equal to or less than M. + * |[31:24] |PKTSVNL |Packet Scaling Vertical Factor N + * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor. + * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor. + * @var CCAP_T::FRCTL + * Offset: 0x30 Scaling Frame Rate Factor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FRM |Scaling Frame Rate Factor M + * | | |Specify the denominator part (M) of the frame rate scaling factor. + * | | |The output image frame rate will be equal to input image frame rate * (N/M). + * | | |Note: The value of N must be equal to or less than M. + * |[13:8] |FRN |Scaling Frame Rate Factor N + * | | |Specify the numerator part (N) of the frame rate scaling factor. + * @var CCAP_T::STRIDE + * Offset: 0x34 Frame Output Pixel Stride Width Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PKTSTRIDE |Packet Frame Output Pixel Stride Width + * | | |The output pixel stride size of packet pipe. + * | | |It is a 32-pixel aligned stride width for the Luma-Y-One bit format or a 4-pixel aligned stride with for the Luma-Y-Eight bit format when color or monochrome CMOS sensors used. + * | | |This means that every new captured line is by word alignment address when color or monochrome CMOS sensors used. + * @var CCAP_T::FIFOTH + * Offset: 0x3C FIFO Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:24] |PKTFTH |Packet FIFO Threshold + * | | |Specify the 5-bit value of the packet FIFO threshold. + * |[31] |OVF |FIFO Overflow Flag + * | | |Indicate the FIFO overflow flag. + * @var CCAP_T::CMPADDR + * Offset: 0x40 Compare Memory Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CMPADDR |Compare Memory Base Address + * | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0]. + * @var CCAP_T::LUMA_Y1_THD + * Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :-----------: | :---- | + * |[7:0] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value + * | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion. + * @var CCAP_T::PKTSM + * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PKTSHMH |Packet Scaling Horizontal Factor M + * | | |Specify the higher 8-bit of denominator part (M) of the horizontal scaling factor. + * | | |Please refer to the register CCAP_PKTSL for the detailed operation. + * |[15:8] |PKTSHNH |Packet Scaling Horizontal Factor N + * | | |Specify the higher 8-bit of numerator part (N) of the horizontal scaling factor. + * | | |Please refer to the register CCAP_PKTSL for the detailed operation. + * |[23:16] |PKTSVMH |Packet Scaling Vertical Factor M + * | | |Specify the higher 8-bit of denominator part (M) of the vertical scaling factor. + * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. + * |[31:24] |PKTSVNH |Packet Scaling Vertical Factor N + * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor. + * | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers. + * @var CCAP_T::CURADDRP + * Offset: 0x50 Current Packet System Memory Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |Current Packet Output Memory Address + * | | |Specify the 32-bit value of the current packet output memory address. + * @var CCAP_T::PKTBA0 + * Offset: 0x60 System Memory Packet Base Address 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BASEADDR |System Memory Packet Base Address 0 + * | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0]. + */ + __IO uint32_t CTL; /*!< [0x0000] Camera Capture Interface Control Register */ + __IO uint32_t PAR; /*!< [0x0004] Camera Capture Interface Parameter Register */ + __IO uint32_t INT; /*!< [0x0008] Camera Capture Interface Interrupt Register */ + __I uint32_t RESERVE0[5]; + __IO uint32_t CWSP; /*!< [0x0020] Cropping Window Starting Address Register */ + __IO uint32_t CWS; /*!< [0x0024] Cropping Window Size Register */ + __IO uint32_t PKTSL; /*!< [0x0028] Packet Scaling Vertical/Horizontal Factor Register (LSB) */ + __IO uint32_t PLNSL; + __IO uint32_t FRCTL; /*!< [0x0030] Scaling Frame Rate Factor Register */ + __IO uint32_t STRIDE; /*!< [0x0034] Frame Output Pixel Stride Width Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t FIFOTH; /*!< [0x003C] FIFO Threshold Register */ + __IO uint32_t CMPADDR; /*!< [0x0040] Compare Memory Base Address Register */ + __IO uint32_t LUMA_Y1_THD; /*!< [0x0044] Luminance Y8 to Y1 Threshold Value Register */ + __IO uint32_t PKTSM; /*!< [0x0048] Packet Scaling Vertical/Horizontal Factor Register (MSB) */ + __I uint32_t RESERVE2[1]; + __IO uint32_t CURADDRP; /*!< [0x0050] Current Packet System Memory Address Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t PKTBA0; /*!< [0x0060] System Memory Packet Base Address 0 Register */ +} CCAP_T; + +/** + @addtogroup CCAP_CONST CCAP Bit Field Definition + Constant Definitions for CCAP Controller +@{ */ + +#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */ +#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */ + +#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */ +#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */ + +#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */ +#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */ + +#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */ +#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */ + +#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */ +#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */ + +#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */ +#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */ + +#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */ +#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */ + +#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */ +#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */ + +#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */ +#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */ + +#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */ +#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */ + +#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */ +#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */ + +#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */ +#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */ + +#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */ +#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */ + +#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */ +#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */ + +#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */ +#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */ + +#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */ +#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */ + +#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */ +#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */ + +#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */ +#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */ + +#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */ +#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */ + +#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */ +#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */ + +#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */ +#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */ + +#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */ +#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */ + +#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */ +#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */ + +#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */ +#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */ + +#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */ +#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */ + +#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */ +#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */ + +#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */ +#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */ + +#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */ +#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */ + +#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */ +#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */ + +#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */ +#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */ + +#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */ +#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */ + +#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */ +#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */ + +#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */ +#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */ + +#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */ +#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */ + +#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */ +#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */ + +#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */ +#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */ + +#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */ +#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */ + +#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */ +#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */ + +#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */ +#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */ + +#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */ +#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */ + +#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */ +#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */ + +#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */ +#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */ + +#define CCAP_CURADDRP_CURADDR_Pos (0) /*!< CCAP_T::CURADDRP: CURADDR Position */ +#define CCAP_CURADDRP_CURADDR_Msk (0xfffffffful << CCAP_CURADDRP_CURADDR_Pos) /*!< CCAP_T::CURADDRP: CURADDR Mask */ + +#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */ +#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */ + +/**@}*/ /* CCAP_CONST */ +/**@}*/ /* end of CCAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CCAP_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/clk_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/clk_reg.h new file mode 100644 index 0000000..8326f1d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/clk_reg.h @@ -0,0 +1,2452 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V3.00 + * @brief CLK register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + + +/*---------------------- System Clock Controller -------------------------*/ +/** + @addtogroup CLK System Clock Controller(CLK) + Memory Mapped Structure for CLK Controller +@{ */ + +typedef struct +{ + + +/** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) + * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. + * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 64 or 24 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). + * | | |0 = Clock cycles delay Disabled. + * | | |1 = Clock cycles delay Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. + * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status + * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode. + * | | |The flag is set if any wake-up source ccurred. + * | | |Note 1: Write 1 to clear the bit to 0. + * | | |Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. + * |[7] |PDEN |System Power-down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared + * | | |Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. + * | | |In Power-down mode, the PLL, PLLFN and system clock are disabled, and ignored the clock source selection. + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. + * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. + * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) + * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. + * | | |00 = HXT frequency is lower than from 8 MHz. + * | | |01 = HXT frequency is from 8 MHz to 12 MHz. + * | | |10 = HXT frequency is from 12 MHz to 16 MHz. + * | | |11 = HXT frequency is higher than 16 MHz. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) + * | | |0 = Select INV type. + * | | |1 = Select GM type. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) + * | | |00 = HIRC stable count is 64 clocks. + * | | |01 = HIRC stable count is 24 clocks. + * | | |Others = Reserved + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[18] |HIRC48MEN |HIRC48M Enable Bit (Write Protect) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) Disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[31] |HXTMD |HXT Bypass Mode (Write Protect) + * | | |0 = HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins. + * | | |1 = HXT works as external clock mode. PF.3 is configured as external clock input pin. + * | | |Note: This bit is write protected. Refer to the SYS_REGCTL register. + * @var CLK_T::AHBCLK0 + * Offset: 0x04 AHB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit + * | | |0 = PDMA0 peripheral clock Disabled. + * | | |1 = PDMA0 peripheral clock Enabled. + * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * |[3] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[4] |STCKEN |System Tick Clock Enable Bit + * | | |0 = System tick clock Disabled. + * | | |1 = System tick clock Enabled. + * |[5] |EMAC0CKEN |EMAC0 Controller Clock Enable Bit + * | | |0 = EMAC0 controller clock Disabled. + * | | |1 = EMAC0 controller clock Enabled. + * |[6] |SDH0CKEN |SDH0 Controller Clock Enable Bit + * | | |0 = SDH0 clock Disabled. + * | | |1 = SDH0 clock Enabled. + * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit + * | | |0 = CRC peripheral clock Disabled. + * | | |1 = CRC peripheral clock Enabled. + * |[8] |CCAPCKEN |Camera Capture Interface Controller Clock Enable Bit + * | | |0 = CCAP controller clock Disabled. + * | | |1 = CCAP controller clock Enabled. + * |[9] |SENCKEN |CCAP Sensor Clock Enable Bit + * | | |0 = CCAP Sensor clock Disabled. + * | | |1 = CCAP Sensor clock Enabled. + * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit + * | | |0 = HSUSB device controller clock Disabled. + * | | |1 = HSUSB device controller clock Enabled. + * |[11] |HBICKEN |Hyper Bus Interface Clock Enable Bit + * | | |0 = HBI clock Disabled. + * | | |1 = HBI clock Enabled. + * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit + * | | |0 = Cryptographic Accelerator clock Disabled. + * | | |1 = Cryptographic Accelerator clock Enabled. + * |[13] |KSCKEN |Key Stroe Clock Enable Bit + * | | |0 = Key Store clock Disabled. + * | | |1 = Key Store clock Enabled. + * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit + * | | |0 = SPIM controller clock Disabled. + * | | |1 = SPIM controller clock Enabled. + * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode + * | | |0 = FMC clock Disabled when chip is under IDLE mode. + * | | |1 = FMC clock Enabled when chip is under IDLE mode. + * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit + * | | |0 = USB HOST peripheral clock Disabled. + * | | |1 = USB HOST peripheral clock Enabled. + * |[17] |SDH1CKEN |SDH1 Controller Clock Enable Bit + * | | |0 = SDH1 clock Disabled. + * | | |1 = SDH1 clock Enabled. + * |[18] |PDMA1CKEN |PDMA1 Clock Enable Bit + * | | |0 = PDMA1 clock Disabled. + * | | |1 = PDMA1 clock Enabled. + * |[19] |TRACECKEN |TRACE Clock Enable Bit + * | | |0 = TRACE clock Disabled. + * | | |1 = TRACE clock Enabled. + * |[24] |GPACKEN |GPIOA Clock Enable Bit + * | | |0 = GPIOA clock Disabled. + * | | |1 = GPIOA clock Enabled. + * |[25] |GPBCKEN |GPIOB Clock Enable Bit + * | | |0 = GPIOB clock Disabled. + * | | |1 = GPIOB clock Enabled. + * |[26] |GPCCKEN |GPIOC Clock Enable Bit + * | | |0 = GPIOC clock Disabled. + * | | |1 = GPIOC clock Enabled. + * |[27] |GPDCKEN |GPIOD Clock Enable Bit + * | | |0 = GPIOD clock Disabled. + * | | |1 = GPIOD clock Enabled. + * |[28] |GPECKEN |GPIOE Clock Enable Bit + * | | |0 = GPIOE clock Disabled. + * | | |1 = GPIOE clock Enabled. + * |[29] |GPFCKEN |GPIOF Clock Enable Bit + * | | |0 = GPIOF clock Disabled. + * | | |1 = GPIOF clock Enabled. + * |[30] |GPGCKEN |GPIOG Clock Enable Bit + * | | |0 = GPIOG clock Disabled. + * | | |1 = GPIOG clock Enabled. + * |[31] |GPHCKEN |GPIOH Clock Enable Bit + * | | |0 = GPIOH clock Disabled. + * | | |1 = GPIOH clock Enabled. + * @var CLK_T::APBCLK0 + * Offset: 0x08 APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer clock Disabled. + * | | |1 = Watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit + * | | |This bit is used to control the RTC APB clock only. + * | | |The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]). + * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |CLKOCKEN |CLKO Clock Enable Bit + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit + * | | |0 = Analog comparator 0/1 clock Disabled. + * | | |1 = Analog comparator 0/1 clock Enabled. + * |[8] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[10] |I2C2CKEN |I2C2 Clock Enable Bit + * | | |0 = I2C2 clock Disabled. + * | | |1 = I2C2 clock Enabled. + * |[11] |I2C3CKEN |I2C3 Clock Enable Bit + * | | |0 = I2C3 clock Disabled. + * | | |1 = I2C3 clock Enabled. + * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[13] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[14] |SPI1CKEN |SPI1 Clock Enable Bit + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[15] |SPI2CKEN |SPI2 Clock Enable Bit + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[16] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[19] |UART3CKEN |UART3 Clock Enable Bit + * | | |0 = UART3 clock Disabled. + * | | |1 = UART3 clock Enabled. + * |[20] |UART4CKEN |UART4 Clock Enable Bit + * | | |0 = UART4 clock Disabled. + * | | |1 = UART4 clock Enabled. + * |[21] |UART5CKEN |UART5 Clock Enable Bit + * | | |0 = UART5 clock Disabled. + * | | |1 = UART5 clock Enabled. + * |[22] |UART6CKEN |UART6 Clock Enable Bit + * | | |0 = UART6 clock Disabled. + * | | |1 = UART6 clock Enabled. + * |[23] |UART7CKEN |UART7 Clock Enable Bit + * | | |0 = UART7 clock Disabled. + * | | |1 = UART7 clock Enabled. + * |[26] |OTGCKEN |USB OTG Clock Enable Bit + * | | |0 = USB OTG clock Disabled. + * | | |1 = USB OTG clock Enabled. + * |[27] |USBDCKEN |USB Device Clock Enable Bit + * | | |0 = USB device clock Disabled. + * | | |1 = USB device clock Enabled. + * |[28] |EADC0CKEN |EADC0 Clock Enable Bit + * | | |0 = EADC0 clock Disabled. + * | | |1 = EADC0 clock Enabled. + * |[29] |I2S0CKEN |I2S0 Clock Enable Bit + * | | |0 = I2S0 clock Disabled. + * | | |1 = I2S0 clock Enabled. + * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit + * | | |0 = HSUSB OTG clock Disabled. + * | | |1 = HSUSB OTG clock Enabled. + * @var CLK_T::APBCLK1 + * Offset: 0x0C APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0CKEN |SC0 Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[1] |SC1CKEN |SC1 Clock Enable Bit + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[2] |SC2CKEN |SC2 Clock Enable Bit + * | | |0 = SC2 clock Disabled. + * | | |1 = SC2 clock Enabled. + * |[3] |I2C4CKEN |I2C4 Clock Enable Bit + * | | |0 = I2C4 clock Disabled. + * | | |1 = I2C4 clock Enabled. + * |[4] |QSPI1CKEN |QSPI1 Clock Enable Bit + * | | |0 = QSPI1 clock Disabled. + * | | |1 = QSPI1 clock Enabled. + * |[6] |SPI3CKEN |SPI3 Clock Enable Bit + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[7] |SPI4CKEN |SPI4 Clock Enable Bit + * | | |0 = SPI4 clock Disabled. + * | | |1 = SPI4 clock Enabled. + * |[8] |USCI0CKEN |USCI0 Clock Enable Bit + * | | |0 = USCI0 clock Disabled. + * | | |1 = USCI0 clock Enabled. + * |[10] |PSIOCKEN |PSIO Clock Enable Bit + * | | |0 = PSIO clock Disabled. + * | | |1 = PSIO clock Enabled. + * |[12] |DACCKEN |DAC Clock Enable Bit + * | | |0 = DAC clock Disabled. + * | | |1 = DAC clock Enabled. + * |[13] |ECAP2CKEN |ECAP2 Clock Enable Bit + * | | |0 = ECAP2 clock Disabled. + * | | |1 = ECAP2 clock Enabled. + * |[14] |ECAP3CKEN |ECAP3 Clock Enable Bit + * | | |0 = ECAP3 clock Disabled. + * | | |1 = ECAP3 clock Enabled. + * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit + * | | |0 = EPWM0 clock Disabled. + * | | |1 = EPWM0 clock Enabled. + * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit + * | | |0 = EPWM1 clock Disabled. + * | | |1 = EPWM1 clock Enabled. + * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit + * | | |0 = BPWM0 clock Disabled. + * | | |1 = BPWM0 clock Enabled. + * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit + * | | |0 = BPWM1 clock Disabled. + * | | |1 = BPWM1 clock Enabled. + * |[20] |EQEI2CKEN |EQEI2 Clock Enable Bit + * | | |0 = EQEI2 clock Disabled. + * | | |1 = EQEI2 clock Enabled. + * |[21] |EQEI3CKEN |EQEI3 Clock Enable Bit + * | | |0 = EQEI3 clock Disabled. + * | | |1 = EQEI3 clock Enabled. + * |[22] |EQEI0CKEN |EQEI0 Clock Enable Bit + * | | |0 = EQEI0 clock Disabled. + * | | |1 = EQEI0 clock Enabled. + * |[23] |EQEI1CKEN |EQEI1 Clock Enable Bit + * | | |0 = EQEI1 clock Disabled. + * | | |1 = EQEI1 clock Enabled. + * |[25] |TRNGCKEN |TRNG Clock Enable Bit + * | | |0 = TRNG clock Disabled. + * | | |1 = TRNG clock Enabled. + * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit + * | | |0 = ECAP0 clock Disabled. + * | | |1 = ECAP0 clock Enabled. + * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit + * | | |0 = ECAP1 clock Disabled. + * | | |1 = ECAP1 clock Enabled. + * |[29] |I2S1CKEN |I2S1 Clock Enable Bit + * | | |0 = I2S1 clock Disabled. + * | | |1 = I2S1 clock Enabled. + * |[31] |EADC1CKEN |EADC1 Clock Enable Bit + * | | |0 = EADC1 clock Disabled. + * | | |1 = EADC1 clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PLL + * | | |011 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * | | |Note: Theses bits are write protected. Refer to the SYS_REGLCTL register. + * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from HIRC/2. + * | | |Note 1: If SysTick clock source is not from HCLK (i.e. SYST_CTRL[2] = 0), SysTick needs to enable STCKEN(CLK_AHBCLK0[4]). + * | | |SysTick clock source must less than or equal to HCLK/2. + * | | |Note 2: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[8] |USBSEL |USB Clock Source Selection (Write Protect) + * | | |0 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). + * | | |1 = Clock source from PLL/2. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:10] |EADC0SEL |EADC0 Clock Source Selection (Write Protect) + * | | |00 = Clock source from PLLFN/2. + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from HCLK. + * | | |11 = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[13:12] |EADC1SEL |EADC1 Clock Source Selection (Write Protect) + * | | |00 = Clock source from PLLFN/2. + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from HCLK. + * | | |11 = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |EADC2SEL |EADC2 Clock Source Selection (Write Protect) + * | | |00 = Clock source from PLLFN/2. + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from HCLK. + * | | |11 = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[17:16] |CCAPSEL |CCAP Sensor Clock Source Selection (Write Protect) + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[21:20] |SDH0SEL |SDH0 Clock Source Selection (Write Protect) + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2 clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[23:22] |SDH1SEL |SDH1 Clock Source Selection (Write Protect) + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2 clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[25:24] |CANFD0SEL |CANFD0 Clock Source Selection (Write Protect) + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2 clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[27:26] |CANFD1SEL |CANFD1 Clock Source Selection (Write Protect) + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2 clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[29:28] |CANFD2SEL |CANFD2 Clock Source Selection (Write Protect) + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2 clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31:30] |CANFD3SEL |CANFD3 Clock Source Selection (Write Protect) + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2 clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[6:4] |CLKOSEL |Clock Output Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from HCLK. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |101 = Clock source from PLLFN/2. + * | | |110 = Clock source from PLL/2. + * | | |111 = Reserved. + * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM0 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM1 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM2 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM3 pin. + * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[25:24] |UART0SEL |UART0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART1SEL |UART1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKSEL2 + * Offset: 0x18 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPWM0SEL |EPWM0 Clock Source Selection + * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. + * | | |0 = Clock source from HCLK. + * | | |1 = Clock source from PCLK0. + * |[1] |EPWM1SEL |EPWM1 Clock Source Selection + * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. + * | | |0 = Clock source from HCLK. + * | | |1 = Clock source from PCLK1. + * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[6:4] |SPI0SEL |SPI0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). + * | | |101 = Clock source from PLLFN/2. + * | | |Others = Reserved. + * |[8] |BPWM0SEL |BPWM0 Clock Source Selection + * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. + * | | |0 = Clock source from HCLK. + * | | |1 = Clock source from PCLK0. + * |[9] |BPWM1SEL |BPWM1 Clock Source Selection + * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. + * | | |0 = Clock source from HCLK. + * | | |1 = Clock source from PCLK1. + * |[11:10] |QSPI1SEL |QSPI1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[14:12] |SPI1SEL |SPI1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). + * | | |101 = Clock source from PLLFN/2. + * | | |Others = Reserved. + * |[18:16] |I2S1SEL |I2S1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). + * | | |101 = Clock source from PLLFN/2. + * | | |Others = Reserved. + * |[21:20] |UART8SEL |UART8 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[23:22] |UART9SEL |UART9 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27] |TRNGSEL |TRNG Clock Source Selection + * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * |[30:28] |PSIOSEL |PSIO Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from PLL/2. + * | | |100 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |101 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKSEL3 + * Offset: 0x1C Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |SC1SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SC2SEL |SC2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |KPISEL |KPI Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |10 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |11 = Reserved. + * |[11:9] |SPI2SEL |SPI2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). + * | | |101 = Clock source from PLLFN/2. + * | | |Others = Reserved. + * |[14:12] |SPI3SEL |SPI3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). + * | | |101 = Clock source from PLLFN/2. + * | | |Others = Reserved. + * |[18:16] |I2S0SEL |I2S0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). + * | | |101 = Clock source from PLLFN/2. + * | | |Others = Reserved. + * |[21:20] |UART6SEL |UART6 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[23:22] |UART7SEL |UART7 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[25:24] |UART2SEL |UART2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[27:26] |UART3SEL |UART3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[29:28] |UART4SEL |UART4 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |UART5SEL |UART5 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL/2. + * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * @var CLK_T::CLKDIV0 + * Offset: 0x20 Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). + * |[7:4] |USBDIV |USB Clock Divide Number from PLL/2 Clock + * | | |USB clock frequency = ((PLL frequency)/2) / (USBDIV + 1). + * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[23:16] |EADC0DIV |EADC0 Clock Divide Number from EADC0 Clock Source + * | | |EADC0 clock frequency = (EADC0 clock source frequency) / (EADC0DIV + 1). + * |[31:24] |SDH0DIV |SDH0 Clock Divide Number from SDH0 Clock Source + * | | |SDH0 clock frequency = (SDH0 clock source frequency) / (SDH0DIV + 1). + * @var CLK_T::CLKDIV1 + * Offset: 0x24 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0DIV |SC0 Clock Divide Number from SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). + * |[15:8] |SC1DIV |SC1 Clock Divide Number from SC1 Clock Source + * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). + * |[23:16] |SC2DIV |SC2 Clock Divide Number from SC2 Clock Source + * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). + * |[31:24] |PSIODIV |PSIO Clock Divide Number from PSIO Clock Source + * | | |PSIO clock frequency = (PSIO clock source frequency) / (PSIODIV + 1). + * @var CLK_T::CLKDIV2 + * Offset: 0x28 Clock Divider Number Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |I2S0DIV |I2S0 Clock Divide Number from I2S0 Clock Source + * | | |I2S0 clock frequency = (I2S0 clock source frequency) / (I2S0DIV + 1). + * |[7:4] |I2S1DIV |I2S1 Clock Divide Number from I2S1 Clock Source + * | | |I2S1 clock frequency = (I2S1 clock source frequency) / (I2S1DIV + 1). + * |[15:8] |KPIDIV |KPI Clock Divide Number from KPI Clock Source + * | | |KPI clock frequency = (KPI clock source frequency) / (KPIDIV + 1). + * |[31:24] |EADC1DIV |EADC1 Clock Divide Number from EADC1 Clock Source + * | | |EADC1 clock frequency = (EADC1 clock source frequency) / (EADC1DIV + 1). + * @var CLK_T::CLKDIV3 + * Offset: 0x2C Clock Divider Number Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:8] |VSENSEDIV |Video Pixel Clock Divide Number from CCAP Sensor Clock Source + * | | |Video pixel clock frequency = (CCAP sensor clock source frequency) / (VSENSEDIV + 1). + * |[23:16] |EMAC0DIV |EMAC0 Clock Divide Number form HCLK + * | | |EMAC0 MDCLK clock frequency = (HCLK) / (EMAC0DIV + 1). + * |[31:24] |SDH1DIV |SDH1 Clock Divide Number from SDH1 Clock Source + * | | |SDH1 clock frequency = (SDH1 clock source frequency) / (SDH1DIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x30 Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source + * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). + * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source + * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). + * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source + * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). + * |[19:16] |UART6DIV |UART6 Clock Divide Number from UART6 Clock Source + * | | |UART6 clock frequency = (UART6 clock source frequency) / (UART6DIV + 1). + * |[23:20] |UART7DIV |UART7 Clock Divide Number from UART7 Clock Source + * | | |UART7 clock frequency = (UART7 clock source frequency) / (UART7DIV + 1). + * @var CLK_T::PCLKDIV + * Offset: 0x34 APB Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |APB0DIV |APB0 Clock Divider + * | | |APB0 clock can be divided from HCLK. + * | | |000 = PCLK0 frequency is HCLK. + * | | |001 = PCLK0 frequency is HCLK/2. + * | | |010 = PCLK0 frequency is HCLK/4. + * | | |011 = PCLK0 frequency is HCLK/8. + * | | |100 = PCLK0 frequency is HCLK/16. + * | | |Others = Reserved. + * |[6:4] |APB1DIV |APB1 Clock Divider + * | | |APB1 clock can be divided from HCLK. + * | | |000 = PCLK1 frequency is HCLK. + * | | |001 = PCLK1 frequency is HCLK/2. + * | | |010 = PCLK1 frequency is HCLK/4. + * | | |011 = PCLK1 frequency is HCLK/8. + * | | |100 = PCLK1 frequency is HCLK/16. + * | | |Others = Reserved. + * @var CLK_T::APBCLK2 + * Offset: 0x38 APB Devices Clock Enable Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KPICKEN |KPI Clock Enable Bit + * | | |0 = KPI clock Disabled. + * | | |1 = KPI clock Enabled. + * |[6] |EADC2CKEN |EADC2 Clock Enable Bit + * | | |0 = EADC2 clock Disabled. + * | | |1 = EADC2 clock Enabled. + * |[7] |ACMP23CKEN|Analog Comparator 2/3 Clock Enable Bit + * | | |0 = Analog Comparator 2/3 clock Disabled. + * | | |1 = Analog Comparator 2/3 clock Enabled. + * |[8] |SPI5CKEN |SPI5 Clock Enable Bit + * | | |0 = SPI5 clock Disabled. + * | | |1 = SPI5 clock Enabled. + * |[9] |SPI6CKEN |SPI6 Clock Enable Bit + * | | |0 = SPI6 clock Disabled. + * | | |1 = SPI6 clock Enabled. + * |[10] |SPI7CKEN |SPI7 Clock Enable Bit + * | | |0 = SPI7 clock Disabled. + * | | |1 = SPI7 clock Enabled. + * |[11] |SPI8CKEN |SPI8 Clock Enable Bit + * | | |0 = SPI8 clock Disabled. + * | | |1 = SPI8 clock Enabled. + * |[12] |SPI9CKEN |SPI9 Clock Enable Bit + * | | |0 = SPI9 clock Disabled. + * | | |1 = SPI9 clock Enabled. + * |[13] |SPI10CKEN |SPI10 Clock Enable Bit + * | | |0 = SPI10 clock Disabled. + * | | |1 = SPI10 clock Enabled. + * |[16] |UART8CKEN |UART8 Clock Enable Bit + * | | |0 = UART8 clock Disabled. + * | | |1 = UART8 clock Enabled. + * |[17] |UART9CKEN |UART9 Clock Enable Bit + * | | |0 = UART9 clock Disabled. + * | | |1 = UART9 clock Enabled. + * @var CLK_T::CLKDIV5 + * Offset: 0x3C Clock Divider Number Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CANFD0DIV |CANFD0 Clock Divide Number from CANFD0 Clock Source + * | | |CANFD0 clock frequency = (CANFD0 clock source frequency) / (CANFD0DIV + 1). + * |[7:4] |CANFD1DIV |CANFD1 Clock Divide Number from CANFD1 Clock Source + * | | |CANFD1 clock frequency = (CANFD1 clock source frequency) / (CANFD1DIV + 1). + * |[11:8] |CANFD2DIV |CANFD2 Clock Divide Number from CANFD2 Clock Source + * | | |CANFD2 clock frequency = (CANFD2 clock source frequency) / (CANFD2DIV + 1). + * |[15:12] |CANFD3DIV |CANFD3 Clock Divide Number from CANFD3 Clock Source + * | | |CANFD3 clock frequency = (CANFD3 clock source frequency) / (CANFD3DIV + 1). + * |[19:16] |UART8DIV |UART6 Clock Divide Number from UART8 Clock Source + * | | |UART6 clock frequency = (UART8 clock source frequency) / (UART8DIV + 1). + * |[23:20] |UART9DIV |UART7 Clock Divide Number from UART9 Clock Source + * | | |UART7 clock frequency = (UART9 clock source frequency) / (UART9DIV + 1). + * |[31:24] |EADC2DIV |EADC2 Clock Divide Number from EADC2 Clock Source + * | | |EADC2 clock frequency = (EADC2 clock source frequency) / (EADC2DIV + 1). + * @var CLK_T::PLLCTL + * Offset: 0x40 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[16] |PD |Power-down Mode (Write Protect) + * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |0 = PLL is in normal mode. + * | | |1 = PLL is in Power-down mode (default). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |OE |PLL FOUT Enable Control (Write Protect) + * | | |0 = PLL FOUT Enabled. + * | | |1 = PLL FOUT is fixed low. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). + * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 1200 PLL source clock (suitable for source clock equal to or less than 12 MHz). + * | | |1 = PLL stable time is 2400 PLL source clock (suitable for source clock larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PLLFNCTL0 + * Offset: 0x48 PLLFN Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[27:16] |FRDIV |PLL Fractional Divider Control (Write Protect) + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PLLFNCTL1 + * Offset: 0x4C PLLFN Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 1200 PLL source clock (suitable for source clock equal to or less than 12 MHz). + * | | |1 = PLL stable time is 2400 PLL source clock (suitable for source clock larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[28] |PD |Power-down Mode (Write Protect) + * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |0 = PLL is in normal mode. + * | | |1 = PLL is in Power-down mode (default). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[29] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |OE |PLL FOUT Enable Control (Write Protect) + * | | |0 = PLL FOUT Enabled. + * | | |1 = PLL FOUT is fixed low. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[31] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |0 = PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT). + * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * |[6] |HIRC48MSTB|HIRC48M Clock Source Stable Flag (Read Only) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is not stable or disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is stable and enabled. + * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) + * | | |This bit is updated when software switches system clock source + * | | |If switch target clock is stable, this bit will be set to 0 + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |0 = Clock switching success. + * | | |1 = Clock switching failure. + * | | |Note: This bit is read only. + * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. + * |[10] |PLLFNSTB |Internal PLLFN Clock Source Stable Flag + * | | |0 = Internal PLLFN clock is not stable or disabled. + * | | |1 = Internal PLLFN clock is stable. + * | | |Note: This bit is read only. + * @var CLK_T::AHBCLK1 + * Offset: 0x58 AHB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[20] |CANFD0CKEN|CANFD0 Clock Enable Bit + * | | |0 = CANFD0 clock Disabled. + * | | |1 = CANFD0 clock Enabled. + * |[21] |CANFD1CKEN|CANFD1 Clock Enable Bit + * | | |0 = CANFD1 clock Disabled. + * | | |1 = CANFD1 clock Enabled. + * |[22] |CANFD2CKEN|CANFD2 Clock Enable Bit + * | | |0 = CANFD2 clock Disabled. + * | | |1 = CANFD2 clock Enabled. + * |[23] |CANFD3CKEN|CANFD3 Clock Enable Bit + * | | |0 = CANFD3 clock Disabled. + * | | |1 = CANFD3 clock Enabled. + * |[24] |GPICKEN |GPIOI Clock Enable Bit + * | | |0 = GPIOI clock Disabled. + * | | |1 = GPIOI clock Enabled. + * |[25] |GPJCKEN |GPIOJ Clock Enable Bit + * | | |0 = GPIOJ clock Disabled. + * | | |1 = GPIOJ clock Enabled. + * |[28] |BMCCKEN |BMC Clock Enable Bit + * | | |0 = BMC clock Disabled. + * | | |1 = BMC clock Enabled. + * @var CLK_T::CLKSEL4 + * Offset: 0x5C Clock Source Select Control Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |SPI4SEL |SPI4 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[6:4] |SPI5SEL |SPI5 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[10:8] |SPI6SEL |SPI6 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |SPI7SEL |SPI7 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |SPI8SEL |SPI8 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |SPI9SEL |SPI9 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[26:24] |SPI10SEL |SPI10 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL/2. + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKOCTL + * Offset: 0x60 Clock Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is Fout = Fin/2^(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL[3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit + * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. + * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. + * @var CLK_T::CLKDCTL + * Offset: 0x70 Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. + * |[18] |HXTFQASW |HXT Clock Frequency Range Detector Event Auto Switch Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail event happened and HCLK will not switch to HIRC automatically. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail event happened and HCLK will switch to HIRC automatically. + * | | |Note: This bit should be set before HXTFQDEN(CLK_CLKDCTL[16]). + * @var CLK_T::CLKDSTS + * Offset: 0x74 Clock Fail Detector Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note 1: Write 1 to clear the bit to 0. + * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note 1: Write 1 to clear the bit to 0. + * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note 1: Write 1 to clear the bit to 0. + * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CDUPB + * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value + * | | |The bits define the maximum value of frequency range detector window. + * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value + * | | |The bits define the minimum value of frequency range detector window. + * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::STOPREQ + * Offset: 0x80 Clock Stop Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CANFD0STR |CANFD0 Clock Stop Request + * | | |This bit is used to stop CANFD0 clock. + * | | |0 = CANFD0 clock is not stoped by this bit. (default) + * | | |1 = Set this bit and check the CANFD0STA(CLK_STOPACK[0]) is 1, then CANFD0 clock stop. + * |[1] |CANFD1STR |CANFD1 Clock Stop Request + * | | |This bit is used to stop CANFD1 clock. + * | | |0 = CANFD1 clock is not stoped by this bit. (default) + * | | |1 = Set this bit and check the CANFD1STA(CLK_STOPACK[1]) is 1, then CANFD1 clock stop. + * |[2] |CANFD2STR |CANFD2 Clock Stop Request + * | | |This bit is used to stop CANFD2 clock. + * | | |0 = CANFD2 clock is not stoped by this bit. (default) + * | | |1 = Set this bit and check the CANFD2STA(CLK_STOPACK[2]) is 1, then CANFD2 clock stop. + * |[3] |CANFD3STR |CANFD3 Clock Stop Request + * | | |This bit is used to stop CANFD3 clock. + * | | |0 = CANFD3 clock is not stoped by this bit. (default) + * | | |1 = Set this bit and check the CANFD3STA(CLK_STOPACK[3]) is 1, then CANFD3 clock stop. + * @var CLK_T::STOPACK + * Offset: 0x84 Clock Stop Acknowledge Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CANFD0STA |CANFD0 Clock Stop Acknowledge (Read Only) + * | | |This bit is used to check CANFD0 clock stop by setting CANFD0STR(CLK_STOPREQ[0]). + * | | |0 = CANFD0 clock not stoped. + * | | |1 = CANFD0 clock stoped. + * |[1] |CANFD1STA |CANFD1 Clock Stop Acknowledge (Read Only) + * | | |This bit is used to check CANFD1 clock stop by setting CANFD1STR(CLK_STOPREQ[1]). + * | | |0 = CANFD1 clock not stoped. + * | | |1 = CANFD1 clock stoped. + * |[2] |CANFD2STA |CANFD2 Clock Stop Acknowledge (Read Only) + * | | |This bit is used to check CANFD2 clock stop by setting CANFD2STR(CLK_STOPREQ[2]). + * | | |0 = CANFD2 clock not stoped. + * | | |1 = CANFD2 clock stoped. + * |[3] |CAN3STACK |CANFD3 Clock Stop Acknowledge (Read Only) + * | | |This bit is used to check CANFD3 clock stop by setting CANFD3STR(CLK_STOPREQ[3]). + * | | |0 = CANFD3 clock not stoped. + * | | |1 = CANFD3 clock stoped. + * @var CLK_T::PMUCTL + * Offset: 0x90 Power Manager Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) + * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. + * | | |000 = Normal Power-down mode is selected (NPD). + * | | |001 = Low leakage Power-down mode is selected (LLPD). + * | | |010 = Fast wake-up Power-down mode is selected (FWPD). + * | | |011 = Reserved. + * | | |100 = Standby Power-down mode is selected (SPD). + * | | |101 = Reserved. + * | | |110 = Deep Power-down mode is selected (DPD). + * | | |111 = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[3] |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable Bit (Write Protect) + * | | |0= When GPIO enters deep power-down mode, all I/O status are tri-state. + * | | |1= When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status. + * | | |After chip was woken up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0] to release I/O hold status. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6:4] |SRETSEL |SRAM Retention Range Select Bit (Write Protect) + * | | |Select SRAM retention range when chip enter SPD mode. + * | | |000 = No SRAM retention. + * | | |001 = 16K SRAM retention when chip enter SPD mode. + * | | |010 = 32K SRAM retention when chip enter SPD mode. + * | | |011 = 64K SRAM retention when chip enter SPD mode. + * | | |100 = 128K SRAM retention when chip enter SPD mode. (default) + * | | |101 = 256K SRAM retention when chip enter SPD mode. + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) + * | | |0 = Wake-up timer disabled at DPD/SPD mode. + * | | |1 = Wake-up timer enabled at DPD/SPD mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) + * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. + * | | |0000 = Time-out interval is 128 LIRC clocks (12.8 ms). + * | | |0001 = Time-out interval is 256 LIRC clocks (25.6 ms). + * | | |0010 = Time-out interval is 512 LIRC clocks (51.2 ms). + * | | |0011 = Time-out interval is 1024 LIRC clocks (102.4ms). + * | | |0100 = Time-out interval is 4096 LIRC clocks (409.6ms). + * | | |0101 = Time-out interval is 8192 LIRC clocks (819.2ms). + * | | |0110 = Time-out interval is 16384 LIRC clocks (1638.4ms). + * | | |0111 = Time-out interval is 65536 LIRC clocks (6553.6ms). + * | | |1000 = Time-out interval is 131072 LIRC clocks (13107.2ms). + * | | |1001 = Time-out interval is 262144 LIRC clocks (26214.4ms). + * | | |1010 = Time-out interval is 524288 LIRC clocks (52428.8ms). + * | | |1011 = Time-out interval is 1048576 LIRC clocks (104857.6ms). + * | | |Others = Time-out interval is 128 LIRC clocks (12.8ms). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[17:16] |WKPINEN0 |Wake-up Pin0 Enable Bit (Write Protect) + * | | |This is control register for GPC.0 to wake-up pin. + * | | |00 = Wake-up pin disabled at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable Bit (Write Protect) + * | | |0 = ACMP wake-up disabled at Standby Power-down mode. + * | | |1 = ACMP wake-up enabled at Standby Power-down mode. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Set FILTSEL(ACMP_CTLx[15:13]) for comparator output filter count selection, the filter clock is LIRC in ACMP SPD mode wakeup function. + * |[22] |VBUSWKEN |VBUS Wake-up Enable Bit (Write Protect) + * | | |0 = VBUS transition wake-up disabled at Deep Power-down mode. + * | | |1 = VBUS transition wake-up enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |RTCWKEN |RTC Wake-up Enable Bit (Write Protect) + * | | |0 = RTC wake-up disabled at Deep Power-down mode or Standby Power-down mode. + * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[25:24] |WKPINEN1 |Wake-up Pin1 Enable Bit (Write Protect) + * | | |This is control register for GPB.0 to wake-up pin. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[27:26] |WKPINEN2 |Wake-up Pin2 Enable Bit (Write Protect) + * | | |This is control register for GPB.2 to wake-up pin. + * | | |00 = Wake-up pin disabled at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[29:28] |WKPINEN3 |Wake-up Pin3 Enable Bit (Write Protect) + * | | |This is control register for GPB.12 to wake-up pin. + * | | |00 = Wake-up pin disabled at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31:30] |WKPINEN4 |Wake-up Pin4 Enable Bit (Write Protect) + * | | |This is control register for GPF.6 to wake-up pin. + * | | |00 = Wake-up pin disabled at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Setting IOCTLSEL(RTC_LXTCTL[8]) to avoid GPF.6 unexpected falling edge. + * @var CLK_T::PMUSTS + * Offset: 0x94 Power Manager Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINWK0 |Pin0 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. + * |[1] |TMRWK |Timer Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. + * |[2] |RTCWK |RTC Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. + * |[3] |PINWK1 |Pin1 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.0). + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. + * |[4] |PINWK2 |Pin2 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.2). + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. + * |[5] |PINWK3 |Pin3 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.12). + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. + * |[6] |PINWK4 |Pin4 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PF.6). + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. + * |[7] |VBUSWK |VBUS Wake-up Flag( Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.12). + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. + * |[8] |GPAWK |GPA Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[9] |GPBWK |GPB Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[10] |GPCWK |GPC Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[11] |GPDWK |GPD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[12] |LVRWK |LVR Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[13] |BODWK |BOD Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[15] |RSTWK |RST pin Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RST pin trigger happened. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. + * |[16] |ACMPWK0 |ACMP0 Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP0 transition. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[17] |ACMPWK1 |ACMP1 Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP1 transition. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[18] |ACMPWK2 |ACMP2 Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP2 transition. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[19] |ACMPWK3 |ACMP3 Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP3 transition. + * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. + * |[31] |CLRWK |Clear Wake-up Flag + * | | |0 = No clear. + * | | |1= Clear all wake-up flag. + * | | |Note: This bit is auto cleared by hardware. + * @var CLK_T::SWKDBCTL + * Offset: 0x9C GPIO Standby Power-down Wake-up De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection + * | | |0000 = Sample wake-up input once per 1 clock. + * | | |0001 = Sample wake-up input once per 2 clocks. + * | | |0010 = Sample wake-up input once per 4 clocks. + * | | |0011 = Sample wake-up input once per 8 clocks. + * | | |0100 = Sample wake-up input once per 16 clocks. + * | | |0101 = Sample wake-up input once per 32 clocks. + * | | |0110 = Sample wake-up input once per 64 clocks. + * | | |0111 = Sample wake-up input once per 128 clocks. + * | | |1000 = Sample wake-up input once per 256 clocks. + * | | |1001 = Sample wake-up input once per 2*256 clocks. + * | | |1010 = Sample wake-up input once per 4*256 clocks. + * | | |1011 = Sample wake-up input once per 8*256 clocks. + * | | |1100 = Sample wake-up input once per 16*256 clocks. + * | | |1101 = Sample wake-up input once per 32*256 clocks. + * | | |1110 = Sample wake-up input once per 64*256 clocks. + * | | |1111 = Sample wake-up input once per 128*256 clocks.. + * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * @var CLK_T::PASWKCTL + * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPA group pin wake-up function Disabled. + * | | |1 = GPA group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPA group pin rising edge wake-up function Disabled. + * | | |1 = GPA group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPA group pin falling edge wake-up function Disabled. + * | | |1 = GPA group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select + * | | |0000 = GPA.0 wake-up function Enabled. + * | | |0001 = GPA.1 wake-up function Enabled. + * | | |0010 = GPA.2 wake-up function Enabled. + * | | |0011 = GPA.3 wake-up function Enabled. + * | | |0100 = GPA.4 wake-up function Enabled. + * | | |0101 = GPA.5 wake-up function Enabled. + * | | |0110 = GPA.6 wake-up function Enabled. + * | | |0111 = GPA.7 wake-up function Enabled. + * | | |1000 = GPA.8 wake-up function Enabled. + * | | |1001 = GPA.9 wake-up function Enabled. + * | | |1010 = GPA.10 wake-up function Enabled. + * | | |1011 = GPA.11 wake-up function Enabled. + * | | |1100 = GPA.12 wake-up function Enabled. + * | | |1101 = GPA.13 wake-up function Enabled. + * | | |1110 = GPA.14 wake-up function Enabled. + * | | |1111 = GPA.15 wake-up function Enabled. + * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. + * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PBSWKCTL + * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPB group pin wake-up function Disabled. + * | | |1 = GPB group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPB group pin rising edge wake-up function Disabled. + * | | |1 = GPB group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPB group pin falling edge wake-up function Disabled. + * | | |1 = GPB group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select + * | | |0000 = GPB.0 wake-up function Enabled. + * | | |0001 = GPB.1 wake-up function Enabled. + * | | |0010 = GPB.2 wake-up function Enabled. + * | | |0011 = GPB.3 wake-up function Enabled. + * | | |0100 = GPB.4 wake-up function Enabled. + * | | |0101 = GPB.5 wake-up function Enabled. + * | | |0110 = GPB.6 wake-up function Enabled. + * | | |0111 = GPB.7 wake-up function Enabled. + * | | |1000 = GPB.8 wake-up function Enabled. + * | | |1001 = GPB.9 wake-up function Enabled. + * | | |1010 = GPB.10 wake-up function Enabled. + * | | |1011 = GPB.11 wake-up function Enabled. + * | | |1100 = GPB.12 wake-up function Enabled. + * | | |1101 = GPB.13 wake-up function Enabled. + * | | |1110 = GPB.14 wake-up function Enabled. + * | | |1111 = GPB.15 wake-up function Enabled. + * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. (LIRC) + * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. + * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PCSWKCTL + * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPC group pin wake-up function Disabled. + * | | |1 = GPC group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPC group pin rising edge wake-up function Disabled. + * | | |1 = GPC group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPC group pin falling edge wake-up function Disabled. + * | | |1 = GPC group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select + * | | |0000 = GPC.0 wake-up function Enabled. + * | | |0001 = GPC.1 wake-up function Enabled. + * | | |0010 = GPC.2 wake-up function Enabled. + * | | |0011 = GPC.3 wake-up function Enabled. + * | | |0100 = GPC.4 wake-up function Enabled. + * | | |0101 = GPC.5 wake-up function Enabled. + * | | |0110 = GPC.6 wake-up function Enabled. + * | | |0111 = GPC.7 wake-up function Enabled. + * | | |1000 = GPC.8 wake-up function Enabled. + * | | |1001 = GPC.9 wake-up function Enabled. + * | | |1010 = GPC.10 wake-up function Enabled. + * | | |1011 = GPC.11 wake-up function Enabled. + * | | |1100 = GPC.12 wake-up function Enabled. + * | | |1101 = GPC.13 wake-up function Enabled. + * | | |1110 = GPC.14 wake-up function Enabled. + * | | |1111 = GPC.15 wake-up function Enabled. + * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. + * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. + * | | |Note: The de-bounce function is valid only for edge triggered. + * @var CLK_T::PDSWKCTL + * Offset: 0xAC GPD Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPD group pin wake-up function Disabled. + * | | |1 = GPD group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPD group pin rising edge wake-up function Disabled. + * | | |1 = GPD group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPD group pin falling edge wake-up function Disabled. + * | | |1 = GPD group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select + * | | |0000 = GPD.0 wake-up function Enabled. + * | | |0001 = GPD.1 wake-up function Enabled. + * | | |0010 = GPD.2 wake-up function Enabled. + * | | |0011 = GPD.3 wake-up function Enabled. + * | | |0100 = GPD.4 wake-up function Enabled. + * | | |0101 = GPD.5 wake-up function Enabled. + * | | |0110 = GPD.6 wake-up function Enabled. + * | | |0111 = GPD.7 wake-up function Enabled. + * | | |1000 = GPD.8 wake-up function Enabled. + * | | |1001 = GPD.9 wake-up function Enabled. + * | | |1010 = GPD.10 wake-up function Enabled. + * | | |1011 = GPD.11 wake-up function Enabled. + * | | |1100 = GPD.12 wake-up function Enabled. + * | | |1101 = GPD.13 wake-up function Enabled. + * | | |1110 = GPD.14 wake-up function Enabled. + * | | |1111 = GPD.15 wake-up function Enabled. + * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. + * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. + * | | |Note: The de-bounce function is valid only for edge triggered. + * @var CLK_T::IOPDCTL + * Offset: 0xB0 GPIO Standby Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IOHR |GPIO Hold Release + * | | |When GPIO enters deep power-down mode or standby power-down mode, all I/O status are hold to keep normal operating status. + * | | |After chip is woken up from deep power-down mode or standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. + * | | |Note: This bit is auto cleared by hardware. + */ + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t AHBCLK0; /*!< [0x0004] AHB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ + __IO uint32_t CLKDIV2; /*!< [0x0028] Clock Divider Number Register 2 */ + __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ + __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ + __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ + __IO uint32_t APBCLK2; /*!< [0x0038] APB Devices Clock Enable Control Register 2 */ + __IO uint32_t CLKDIV5; /*!< [0x003c] Clock Divider Number Register 5 */ + __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t PLLFNCTL0; /*!< [0x0048] PLLFN Control Register 0 */ + __IO uint32_t PLLFNCTL1; /*!< [0x004c] PLLFN Control Register 1 */ + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t AHBCLK1; /*!< [0x0058] AHB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL4; /*!< [0x005c] Clock Source Select Control Register 4 */ + __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ + __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ + __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ + __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ + __IO uint32_t STOPREQ; /*!< [0x0080] Clock Stop Request Register */ + __I uint32_t STOPACK; /*!< [0x0084] Clock Stop Acknowledge Register */ + __I uint32_t RESERVE4[2]; + __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ + __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ + __I uint32_t RESERVE5[1]; + __IO uint32_t SWKDBCTL; /*!< [0x009c] GPIO Standby Power-down Wake-up De-bounce Control Register */ + __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ + __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ + __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ + __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ + __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ +#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ + +#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ +#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ + +#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ +#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ + +#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ +#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ + +#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ +#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ + +#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ +#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ + +#define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ +#define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ + +#define CLK_PWRCTL_HIRC48MEN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48MEN Position */ +#define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) /*!< CLK_T::PWRCTL: HIRC48MEN Mask */ + +#define CLK_PWRCTL_HXTMD_Pos (31) /*!< CLK_T::PWRCTL: HXTMD Position */ +#define CLK_PWRCTL_HXTMD_Msk (0x1ul << CLK_PWRCTL_HXTMD_Pos) /*!< CLK_T::PWRCTL: HXTMD Mask */ + +#define CLK_AHBCLK0_PDMA0CKEN_Pos (1) /*!< CLK_T::AHBCLK0: PDMA0CKEN Position */ +#define CLK_AHBCLK0_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK0_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK0: PDMA0CKEN Mask */ + +#define CLK_AHBCLK0_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK0: ISPCKEN Position */ +#define CLK_AHBCLK0_ISPCKEN_Msk (0x1ul << CLK_AHBCLK0_ISPCKEN_Pos) /*!< CLK_T::AHBCLK0: ISPCKEN Mask */ + +#define CLK_AHBCLK0_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK0: EBICKEN Position */ +#define CLK_AHBCLK0_EBICKEN_Msk (0x1ul << CLK_AHBCLK0_EBICKEN_Pos) /*!< CLK_T::AHBCLK0: EBICKEN Mask */ + +#define CLK_AHBCLK0_STCKEN_Pos (4) /*!< CLK_T::AHBCLK0: STCKEN Position */ +#define CLK_AHBCLK0_STCKEN_Msk (0x1ul << CLK_AHBCLK0_STCKEN_Pos) /*!< CLK_T::AHBCLK0: STCKEN Mask */ + +#define CLK_AHBCLK0_EMAC0CKEN_Pos (5) /*!< CLK_T::AHBCLK0: EMAC0CKEN Position */ +#define CLK_AHBCLK0_EMAC0CKEN_Msk (0x1ul << CLK_AHBCLK0_EMAC0CKEN_Pos) /*!< CLK_T::AHBCLK0: EMAC0CKEN Mask */ + +#define CLK_AHBCLK0_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK0: SDH0CKEN Position */ +#define CLK_AHBCLK0_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK0_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK0: SDH0CKEN Mask */ + +#define CLK_AHBCLK0_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK0: CRCCKEN Position */ +#define CLK_AHBCLK0_CRCCKEN_Msk (0x1ul << CLK_AHBCLK0_CRCCKEN_Pos) /*!< CLK_T::AHBCLK0: CRCCKEN Mask */ + +#define CLK_AHBCLK0_CCAPCKEN_Pos (8) /*!< CLK_T::AHBCLK0: CCAPCKEN Position */ +#define CLK_AHBCLK0_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK0_CCAPCKEN_Pos) /*!< CLK_T::AHBCLK0: CCAPCKEN Mask */ + +#define CLK_AHBCLK0_SENCKEN_Pos (9) /*!< CLK_T::AHBCLK0: SENCKEN Position */ +#define CLK_AHBCLK0_SENCKEN_Msk (0x1ul << CLK_AHBCLK0_SENCKEN_Pos) /*!< CLK_T::AHBCLK0: SENCKEN Mask */ + +#define CLK_AHBCLK0_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK0: HSUSBDCKEN Position */ +#define CLK_AHBCLK0_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK0_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK0: HSUSBDCKEN Mask */ + +#define CLK_AHBCLK0_HBICKEN_Pos (11) /*!< CLK_T::AHBCLK0: HBICKEN Position */ +#define CLK_AHBCLK0_HBICKEN_Msk (0x1ul << CLK_AHBCLK0_HBICKEN_Pos) /*!< CLK_T::AHBCLK0: HBICKEN Mask */ + +#define CLK_AHBCLK0_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK0: CRPTCKEN Position */ +#define CLK_AHBCLK0_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK0_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK0: CRPTCKEN Mask */ + +#define CLK_AHBCLK0_KSCKEN_Pos (13) /*!< CLK_T::AHBCLK0: KSCKEN Position */ +#define CLK_AHBCLK0_KSCKEN_Msk (0x1ul << CLK_AHBCLK0_KSCKEN_Pos) /*!< CLK_T::AHBCLK0: KSCKEN Mask */ + +#define CLK_AHBCLK0_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK0: SPIMCKEN Position */ +#define CLK_AHBCLK0_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK0_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK0: SPIMCKEN Mask */ + +#define CLK_AHBCLK0_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK0: FMCIDLE Position */ +#define CLK_AHBCLK0_FMCIDLE_Msk (0x1ul << CLK_AHBCLK0_FMCIDLE_Pos) /*!< CLK_T::AHBCLK0: FMCIDLE Mask */ + +#define CLK_AHBCLK0_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK0: USBHCKEN Position */ +#define CLK_AHBCLK0_USBHCKEN_Msk (0x1ul << CLK_AHBCLK0_USBHCKEN_Pos) /*!< CLK_T::AHBCLK0: USBHCKEN Mask */ + +#define CLK_AHBCLK0_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK0: SDH1CKEN Position */ +#define CLK_AHBCLK0_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK0_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK0: SDH1CKEN Mask */ + +#define CLK_AHBCLK0_PDMA1CKEN_Pos (18) /*!< CLK_T::AHBCLK0: PDMA1CKEN Position */ +#define CLK_AHBCLK0_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK0_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK0: PDMA1CKEN Mask */ + +#define CLK_AHBCLK0_TRACECKEN_Pos (19) /*!< CLK_T::AHBCLK0: TRACECKEN Position */ +#define CLK_AHBCLK0_TRACECKEN_Msk (0x1ul << CLK_AHBCLK0_TRACECKEN_Pos) /*!< CLK_T::AHBCLK0: TRACECKEN Mask */ + +#define CLK_AHBCLK0_GPACKEN_Pos (24) /*!< CLK_T::AHBCLK0: GPACKEN Position */ +#define CLK_AHBCLK0_GPACKEN_Msk (0x1ul << CLK_AHBCLK0_GPACKEN_Pos) /*!< CLK_T::AHBCLK0: GPACKEN Mask */ + +#define CLK_AHBCLK0_GPBCKEN_Pos (25) /*!< CLK_T::AHBCLK0: GPBCKEN Position */ +#define CLK_AHBCLK0_GPBCKEN_Msk (0x1ul << CLK_AHBCLK0_GPBCKEN_Pos) /*!< CLK_T::AHBCLK0: GPBCKEN Mask */ + +#define CLK_AHBCLK0_GPCCKEN_Pos (26) /*!< CLK_T::AHBCLK0: GPCCKEN Position */ +#define CLK_AHBCLK0_GPCCKEN_Msk (0x1ul << CLK_AHBCLK0_GPCCKEN_Pos) /*!< CLK_T::AHBCLK0: GPCCKEN Mask */ + +#define CLK_AHBCLK0_GPDCKEN_Pos (27) /*!< CLK_T::AHBCLK0: GPDCKEN Position */ +#define CLK_AHBCLK0_GPDCKEN_Msk (0x1ul << CLK_AHBCLK0_GPDCKEN_Pos) /*!< CLK_T::AHBCLK0: GPDCKEN Mask */ + +#define CLK_AHBCLK0_GPECKEN_Pos (28) /*!< CLK_T::AHBCLK0: GPECKEN Position */ +#define CLK_AHBCLK0_GPECKEN_Msk (0x1ul << CLK_AHBCLK0_GPECKEN_Pos) /*!< CLK_T::AHBCLK0: GPECKEN Mask */ + +#define CLK_AHBCLK0_GPFCKEN_Pos (29) /*!< CLK_T::AHBCLK0: GPFCKEN Position */ +#define CLK_AHBCLK0_GPFCKEN_Msk (0x1ul << CLK_AHBCLK0_GPFCKEN_Pos) /*!< CLK_T::AHBCLK0: GPFCKEN Mask */ + +#define CLK_AHBCLK0_GPGCKEN_Pos (30) /*!< CLK_T::AHBCLK0: GPGCKEN Position */ +#define CLK_AHBCLK0_GPGCKEN_Msk (0x1ul << CLK_AHBCLK0_GPGCKEN_Pos) /*!< CLK_T::AHBCLK0: GPGCKEN Mask */ + +#define CLK_AHBCLK0_GPHCKEN_Pos (31) /*!< CLK_T::AHBCLK0: GPHCKEN Position */ +#define CLK_AHBCLK0_GPHCKEN_Msk (0x1ul << CLK_AHBCLK0_GPHCKEN_Pos) /*!< CLK_T::AHBCLK0: GPHCKEN Mask */ + +#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ +#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ +#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ + +#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ +#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ + +#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ +#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ + +#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ +#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ + +#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ +#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ + +#define CLK_APBCLK0_I2C3CKEN_Pos (11) /*!< CLK_T::APBCLK0: I2C3CKEN Position */ +#define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) /*!< CLK_T::APBCLK0: I2C3CKEN Mask */ + +#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ +#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ +#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ +#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ + +#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ +#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ +#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ + +#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ +#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ + +#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ +#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ + +#define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */ +#define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */ + +#define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */ +#define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */ + +#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ +#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_EADC0CKEN_Pos (28) /*!< CLK_T::APBCLK0: EADC0CKEN Position */ +#define CLK_APBCLK0_EADC0CKEN_Msk (0x1ul << CLK_APBCLK0_EADC0CKEN_Pos) /*!< CLK_T::APBCLK0: EADC0CKEN Mask */ + +#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ +#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ + +#define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ +#define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ +#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ + +#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ +#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ + +#define CLK_APBCLK1_I2C4CKEN_Pos (3) /*!< CLK_T::APBCLK1: I2C4CKEN Position */ +#define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) /*!< CLK_T::APBCLK1: I2C4CKEN Mask */ + +#define CLK_APBCLK1_QSPI1CKEN_Pos (4) /*!< CLK_T::APBCLK1: QSPI1CKEN Position */ +#define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI1CKEN Mask */ + +#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ +#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ + +#define CLK_APBCLK1_SPI4CKEN_Pos (7) /*!< CLK_T::APBCLK1: SPI4CKEN Position */ +#define CLK_APBCLK1_SPI4CKEN_Msk (0x1ul << CLK_APBCLK1_SPI4CKEN_Pos) /*!< CLK_T::APBCLK1: SPI4CKEN Mask */ + +#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ +#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ + +#define CLK_APBCLK1_PSIOCKEN_Pos (10) /*!< CLK_T::APBCLK1: PSIOCKEN Position */ +#define CLK_APBCLK1_PSIOCKEN_Msk (0x1ul << CLK_APBCLK1_PSIOCKEN_Pos) /*!< CLK_T::APBCLK1: PSIOCKEN Mask */ + +#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ +#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ + +#define CLK_APBCLK1_ECAP2CKEN_Pos (13) /*!< CLK_T::APBCLK1: ECAP2CKEN Position */ +#define CLK_APBCLK1_ECAP2CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP2CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP2CKEN Mask */ + +#define CLK_APBCLK1_ECAP3CKEN_Pos (14) /*!< CLK_T::APBCLK1: ECAP3CKEN Position */ +#define CLK_APBCLK1_ECAP3CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP3CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP3CKEN Mask */ + +#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ +#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ + +#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ +#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ + +#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ +#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ + +#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ +#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ + +#define CLK_APBCLK1_EQEI2CKEN_Pos (20) /*!< CLK_T::APBCLK1: EQEI2CKEN Position */ +#define CLK_APBCLK1_EQEI2CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI2CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI2CKEN Mask */ + +#define CLK_APBCLK1_EQEI3CKEN_Pos (21) /*!< CLK_T::APBCLK1: EQEI3CKEN Position */ +#define CLK_APBCLK1_EQEI3CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI3CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI3CKEN Mask */ + +#define CLK_APBCLK1_EQEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: EQEI0CKEN Position */ +#define CLK_APBCLK1_EQEI0CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI0CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI0CKEN Mask */ + +#define CLK_APBCLK1_EQEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: EQEI1CKEN Position */ +#define CLK_APBCLK1_EQEI1CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI1CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI1CKEN Mask */ + +#define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ +#define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ + +#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ +#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ + +#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ +#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ + +#define CLK_APBCLK1_I2S1CKEN_Pos (29) /*!< CLK_T::APBCLK1: I2S1CKEN Position */ +#define CLK_APBCLK1_I2S1CKEN_Msk (0x1ul << CLK_APBCLK1_I2S1CKEN_Pos) /*!< CLK_T::APBCLK1: I2S1CKEN Mask */ + +#define CLK_APBCLK1_EADC1CKEN_Pos (31) /*!< CLK_T::APBCLK1: EADC1CKEN Position */ +#define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos) /*!< CLK_T::APBCLK1: EADC1CKEN Mask */ + +#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ +#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ + +#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ +#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ + +#define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ +#define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ + +#define CLK_CLKSEL0_EADC0SEL_Pos (10) /*!< CLK_T::CLKSEL0: EADC0SEL Position */ +#define CLK_CLKSEL0_EADC0SEL_Msk (0x3ul << CLK_CLKSEL0_EADC0SEL_Pos) /*!< CLK_T::CLKSEL0: EADC0SEL Mask */ + +#define CLK_CLKSEL0_EADC1SEL_Pos (12) /*!< CLK_T::CLKSEL0: EADC1SEL Position */ +#define CLK_CLKSEL0_EADC1SEL_Msk (0x3ul << CLK_CLKSEL0_EADC1SEL_Pos) /*!< CLK_T::CLKSEL0: EADC1SEL Mask */ + +#define CLK_CLKSEL0_EADC2SEL_Pos (14) /*!< CLK_T::CLKSEL0: EADC2SEL Position */ +#define CLK_CLKSEL0_EADC2SEL_Msk (0x3ul << CLK_CLKSEL0_EADC2SEL_Pos) /*!< CLK_T::CLKSEL0: EADC2SEL Mask */ + +#define CLK_CLKSEL0_CCAPSEL_Pos (16) /*!< CLK_T::CLKSEL0: CCAPSEL Position */ +#define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos) /*!< CLK_T::CLKSEL0: CCAPSEL Mask */ + +#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ +#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ + +#define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ +#define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ + +#define CLK_CLKSEL0_CANFD0SEL_Pos (24) /*!< CLK_T::CLKSEL0: CANFD0SEL Position */ +#define CLK_CLKSEL0_CANFD0SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD0SEL Mask */ + +#define CLK_CLKSEL0_CANFD1SEL_Pos (26) /*!< CLK_T::CLKSEL0: CANFD1SEL Position */ +#define CLK_CLKSEL0_CANFD1SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD1SEL Mask */ + +#define CLK_CLKSEL0_CANFD2SEL_Pos (28) /*!< CLK_T::CLKSEL0: CANFD2SEL Position */ +#define CLK_CLKSEL0_CANFD2SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD2SEL Mask */ + +#define CLK_CLKSEL0_CANFD3SEL_Pos (30) /*!< CLK_T::CLKSEL0: CANFD3SEL Position */ +#define CLK_CLKSEL0_CANFD3SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD3SEL Mask */ + +#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ +#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ + +#define CLK_CLKSEL1_CLKOSEL_Pos (4) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ +#define CLK_CLKSEL1_CLKOSEL_Msk (0x7ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ +#define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ + +#define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ +#define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ + +#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ +#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ + +#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ +#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ + +#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ +#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ +#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ +#define CLK_CLKSEL2_SPI0SEL_Msk (0x7ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ + +#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ +#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ + +#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ +#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI1SEL_Pos (10) /*!< CLK_T::CLKSEL2: QSPI1SEL Position */ +#define CLK_CLKSEL2_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI1SEL Mask */ + +#define CLK_CLKSEL2_SPI1SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ +#define CLK_CLKSEL2_SPI1SEL_Msk (0x7ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ + +#define CLK_CLKSEL2_I2S1SEL_Pos (16) /*!< CLK_T::CLKSEL2: I2S1SEL Position */ +#define CLK_CLKSEL2_I2S1SEL_Msk (0x7ul << CLK_CLKSEL2_I2S1SEL_Pos) /*!< CLK_T::CLKSEL2: I2S1SEL Mask */ + +#define CLK_CLKSEL2_UART8SEL_Pos (20) /*!< CLK_T::CLKSEL2: UART8SEL Position */ +#define CLK_CLKSEL2_UART8SEL_Msk (0x3ul << CLK_CLKSEL2_UART8SEL_Pos) /*!< CLK_T::CLKSEL2: UART8SEL Mask */ + +#define CLK_CLKSEL2_UART9SEL_Pos (22) /*!< CLK_T::CLKSEL2: UART9SEL Position */ +#define CLK_CLKSEL2_UART9SEL_Msk (0x3ul << CLK_CLKSEL2_UART9SEL_Pos) /*!< CLK_T::CLKSEL2: UART9SEL Mask */ + +#define CLK_CLKSEL2_TRNGSEL_Pos (27) /*!< CLK_T::CLKSEL2: TRNGSEL Position */ +#define CLK_CLKSEL2_TRNGSEL_Msk (0x1ul << CLK_CLKSEL2_TRNGSEL_Pos) /*!< CLK_T::CLKSEL2: TRNGSEL Mask */ + +#define CLK_CLKSEL2_PSIOSEL_Pos (28) /*!< CLK_T::CLKSEL2: PSIOSEL Position */ +#define CLK_CLKSEL2_PSIOSEL_Msk (0x7ul << CLK_CLKSEL2_PSIOSEL_Pos) /*!< CLK_T::CLKSEL2: PSIOSEL Mask */ + +#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ +#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ + +#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ +#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ + +#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ +#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ + +#define CLK_CLKSEL3_KPISEL_Pos (6) /*!< CLK_T::CLKSEL3: KPISEL Position */ +#define CLK_CLKSEL3_KPISEL_Msk (0x3ul << CLK_CLKSEL3_KPISEL_Pos) /*!< CLK_T::CLKSEL3: KPISEL Mask */ + +#define CLK_CLKSEL3_SPI2SEL_Pos (9) /*!< CLK_T::CLKSEL3: SPI2SEL Position */ +#define CLK_CLKSEL3_SPI2SEL_Msk (0x7ul << CLK_CLKSEL3_SPI2SEL_Pos) /*!< CLK_T::CLKSEL3: SPI2SEL Mask */ + +#define CLK_CLKSEL3_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL3: SPI3SEL Position */ +#define CLK_CLKSEL3_SPI3SEL_Msk (0x7ul << CLK_CLKSEL3_SPI3SEL_Pos) /*!< CLK_T::CLKSEL3: SPI3SEL Mask */ + +#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ +#define CLK_CLKSEL3_I2S0SEL_Msk (0x7ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ + +#define CLK_CLKSEL3_UART6SEL_Pos (20) /*!< CLK_T::CLKSEL3: UART6SEL Position */ +#define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos) /*!< CLK_T::CLKSEL3: UART6SEL Mask */ + +#define CLK_CLKSEL3_UART7SEL_Pos (22) /*!< CLK_T::CLKSEL3: UART7SEL Position */ +#define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos) /*!< CLK_T::CLKSEL3: UART7SEL Mask */ + +#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ +#define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ + +#define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ +#define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ + +#define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ +#define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ + +#define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ +#define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ + +#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ +#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ + +#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ +#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ + +#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ +#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ + +#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ +#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ + +#define CLK_CLKDIV0_EADC0DIV_Pos (16) /*!< CLK_T::CLKDIV0: EADC0DIV Position */ +#define CLK_CLKDIV0_EADC0DIV_Msk (0xfful << CLK_CLKDIV0_EADC0DIV_Pos) /*!< CLK_T::CLKDIV0: EADC0DIV Mask */ + +#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ +#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ +#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ + +#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ +#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ + +#define CLK_CLKDIV1_PSIODIV_Pos (24) /*!< CLK_T::CLKDIV1: PSIODIV Position */ +#define CLK_CLKDIV1_PSIODIV_Msk (0xfful << CLK_CLKDIV1_PSIODIV_Pos) /*!< CLK_T::CLKDIV1: PSIODIV Mask */ + +#define CLK_CLKDIV2_I2S0DIV_Pos (0) /*!< CLK_T::CLKDIV2: I2S0DIV Position */ +#define CLK_CLKDIV2_I2S0DIV_Msk (0xful << CLK_CLKDIV2_I2S0DIV_Pos) /*!< CLK_T::CLKDIV2: I2S0DIV Mask */ + +#define CLK_CLKDIV2_I2S1DIV_Pos (4) /*!< CLK_T::CLKDIV2: I2S1DIV Position */ +#define CLK_CLKDIV2_I2S1DIV_Msk (0xful << CLK_CLKDIV2_I2S1DIV_Pos) /*!< CLK_T::CLKDIV2: I2S1DIV Mask */ + +#define CLK_CLKDIV2_KPIDIV_Pos (8) /*!< CLK_T::CLKDIV2: KPIDIV Position */ +#define CLK_CLKDIV2_KPIDIV_Msk (0xfful << CLK_CLKDIV2_KPIDIV_Pos) /*!< CLK_T::CLKDIV2: KPIDIV Mask */ + +#define CLK_CLKDIV2_EADC1DIV_Pos (24) /*!< CLK_T::CLKDIV2: EADC1DIV Position */ +#define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLK_T::CLKDIV2: EADC1DIV Mask */ + +#define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK_T::CLKDIV3: VSENSEDIV Position */ +#define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK_T::CLKDIV3: VSENSEDIV Mask */ + +#define CLK_CLKDIV3_EMAC0DIV_Pos (16) /*!< CLK_T::CLKDIV3: EMAC0DIV Position */ +#define CLK_CLKDIV3_EMAC0DIV_Msk (0xfful << CLK_CLKDIV3_EMAC0DIV_Pos) /*!< CLK_T::CLKDIV3: EMAC0DIV Mask */ + +#define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ +#define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ + +#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ +#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ + +#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ +#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ + +#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ +#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ + +#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ +#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ + +#define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */ +#define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */ + +#define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */ +#define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */ + +#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ +#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ + +#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ +#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ + +#define CLK_APBCLK2_KPICKEN_Pos (0) /*!< CLK_T::APBCLK2: KPICKEN Position */ +#define CLK_APBCLK2_KPICKEN_Msk (0x1ul << CLK_APBCLK2_KPICKEN_Pos) /*!< CLK_T::APBCLK2: KPICKEN Mask */ + +#define CLK_APBCLK2_EADC2CKEN_Pos (6) /*!< CLK_T::APBCLK2: EADC2CKEN Position */ +#define CLK_APBCLK2_EADC2CKEN_Msk (0x1ul << CLK_APBCLK2_EADC2CKEN_Pos) /*!< CLK_T::APBCLK2: EADC2CKEN Mask */ + +#define CLK_APBCLK2_ACMP23CKEN_Pos (7) /*!< CLK_T::APBCLK2: ACMP23CKEN Position */ +#define CLK_APBCLK2_ACMP23CKEN_Msk (0x1ul << CLK_APBCLK2_ACMP23CKEN_Pos) /*!< CLK_T::APBCLK2: ACMP23CKEN Mask */ + +#define CLK_APBCLK2_SPI5CKEN_Pos (8) /*!< CLK_T::APBCLK2: SPI5CKEN Position */ +#define CLK_APBCLK2_SPI5CKEN_Msk (0x1ul << CLK_APBCLK2_SPI5CKEN_Pos) /*!< CLK_T::APBCLK2: SPI5CKEN Mask */ + +#define CLK_APBCLK2_SPI6CKEN_Pos (9) /*!< CLK_T::APBCLK2: SPI6CKEN Position */ +#define CLK_APBCLK2_SPI6CKEN_Msk (0x1ul << CLK_APBCLK2_SPI6CKEN_Pos) /*!< CLK_T::APBCLK2: SPI6CKEN Mask */ + +#define CLK_APBCLK2_SPI7CKEN_Pos (10) /*!< CLK_T::APBCLK2: SPI7CKEN Position */ +#define CLK_APBCLK2_SPI7CKEN_Msk (0x1ul << CLK_APBCLK2_SPI7CKEN_Pos) /*!< CLK_T::APBCLK2: SPI7CKEN Mask */ + +#define CLK_APBCLK2_SPI8CKEN_Pos (11) /*!< CLK_T::APBCLK2: SPI8CKEN Position */ +#define CLK_APBCLK2_SPI8CKEN_Msk (0x1ul << CLK_APBCLK2_SPI8CKEN_Pos) /*!< CLK_T::APBCLK2: SPI8CKEN Mask */ + +#define CLK_APBCLK2_SPI9CKEN_Pos (12) /*!< CLK_T::APBCLK2: SPI9CKEN Position */ +#define CLK_APBCLK2_SPI9CKEN_Msk (0x1ul << CLK_APBCLK2_SPI9CKEN_Pos) /*!< CLK_T::APBCLK2: SPI9CKEN Mask */ + +#define CLK_APBCLK2_SPI10CKEN_Pos (13) /*!< CLK_T::APBCLK2: SPI10CKEN Position */ +#define CLK_APBCLK2_SPI10CKEN_Msk (0x1ul << CLK_APBCLK2_SPI10CKEN_Pos) /*!< CLK_T::APBCLK2: SPI10CKEN Mask */ + +#define CLK_APBCLK2_UART8CKEN_Pos (16) /*!< CLK_T::APBCLK2: UART8CKEN Position */ +#define CLK_APBCLK2_UART8CKEN_Msk (0x1ul << CLK_APBCLK2_UART8CKEN_Pos) /*!< CLK_T::APBCLK2: UART8CKEN Mask */ + +#define CLK_APBCLK2_UART9CKEN_Pos (17) /*!< CLK_T::APBCLK2: UART9CKEN Position */ +#define CLK_APBCLK2_UART9CKEN_Msk (0x1ul << CLK_APBCLK2_UART9CKEN_Pos) /*!< CLK_T::APBCLK2: UART9CKEN Mask */ + +#define CLK_CLKDIV5_CANFD0DIV_Pos (0) /*!< CLK_T::CLKDIV5: CANFD0DIV Position */ +#define CLK_CLKDIV5_CANFD0DIV_Msk (0xful << CLK_CLKDIV5_CANFD0DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD0DIV Mask */ + +#define CLK_CLKDIV5_CANFD1DIV_Pos (4) /*!< CLK_T::CLKDIV5: CANFD1DIV Position */ +#define CLK_CLKDIV5_CANFD1DIV_Msk (0xful << CLK_CLKDIV5_CANFD1DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD1DIV Mask */ + +#define CLK_CLKDIV5_CANFD2DIV_Pos (8) /*!< CLK_T::CLKDIV5: CANFD2DIV Position */ +#define CLK_CLKDIV5_CANFD2DIV_Msk (0xful << CLK_CLKDIV5_CANFD2DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD2DIV Mask */ + +#define CLK_CLKDIV5_CANFD3DIV_Pos (12) /*!< CLK_T::CLKDIV5: CANFD3DIV Position */ +#define CLK_CLKDIV5_CANFD3DIV_Msk (0xful << CLK_CLKDIV5_CANFD3DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD3DIV Mask */ + +#define CLK_CLKDIV5_UART8DIV_Pos (16) /*!< CLK_T::CLKDIV5: UART8DIV Position */ +#define CLK_CLKDIV5_UART8DIV_Msk (0xful << CLK_CLKDIV5_UART8DIV_Pos) /*!< CLK_T::CLKDIV5: UART8DIV Mask */ + +#define CLK_CLKDIV5_UART9DIV_Pos (20) /*!< CLK_T::CLKDIV5: UART9DIV Position */ +#define CLK_CLKDIV5_UART9DIV_Msk (0xful << CLK_CLKDIV5_UART9DIV_Pos) /*!< CLK_T::CLKDIV5: UART9DIV Mask */ + +#define CLK_CLKDIV5_EADC2DIV_Pos (24) /*!< CLK_T::CLKDIV5: EADC2DIV Position */ +#define CLK_CLKDIV5_EADC2DIV_Msk (0xfful << CLK_CLKDIV5_EADC2DIV_Pos) /*!< CLK_T::CLKDIV5: EADC2DIV Mask */ + +#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ +#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ + +#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ +#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ + +#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ +#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ + +#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ +#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ + +#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ +#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ + +#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ +#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ + +#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ +#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ + +#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ +#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ + +#define CLK_PLLFNCTL0_FBDIV_Pos (0) /*!< CLK_T::PLLFNCTL0: FBDIV Position */ +#define CLK_PLLFNCTL0_FBDIV_Msk (0x1fful << CLK_PLLFNCTL0_FBDIV_Pos) /*!< CLK_T::PLLFNCTL0: FBDIV Mask */ + +#define CLK_PLLFNCTL0_INDIV_Pos (9) /*!< CLK_T::PLLFNCTL0: INDIV Position */ +#define CLK_PLLFNCTL0_INDIV_Msk (0x1ful << CLK_PLLFNCTL0_INDIV_Pos) /*!< CLK_T::PLLFNCTL0: INDIV Mask */ + +#define CLK_PLLFNCTL0_OUTDIV_Pos (14) /*!< CLK_T::PLLFNCTL0: OUTDIV Position */ +#define CLK_PLLFNCTL0_OUTDIV_Msk (0x3ul << CLK_PLLFNCTL0_OUTDIV_Pos) /*!< CLK_T::PLLFNCTL0: OUTDIV Mask */ + +#define CLK_PLLFNCTL0_FRDIV_Pos (16) /*!< CLK_T::PLLFNCTL0: FRDIV Position */ +#define CLK_PLLFNCTL0_FRDIV_Msk (0xffful << CLK_PLLFNCTL0_FRDIV_Pos) /*!< CLK_T::PLLFNCTL0: FRDIV Mask */ + +#define CLK_PLLFNCTL1_STBSEL_Pos (27) /*!< CLK_T::PLLFNCTL1: STBSEL Position */ +#define CLK_PLLFNCTL1_STBSEL_Msk (0x1ul << CLK_PLLFNCTL1_STBSEL_Pos) /*!< CLK_T::PLLFNCTL1: STBSEL Mask */ + +#define CLK_PLLFNCTL1_PD_Pos (28) /*!< CLK_T::PLLFNCTL1: PD Position */ +#define CLK_PLLFNCTL1_PD_Msk (0x1ul << CLK_PLLFNCTL1_PD_Pos) /*!< CLK_T::PLLFNCTL1: PD Mask */ + +#define CLK_PLLFNCTL1_BP_Pos (29) /*!< CLK_T::PLLFNCTL1: BP Position */ +#define CLK_PLLFNCTL1_BP_Msk (0x1ul << CLK_PLLFNCTL1_BP_Pos) /*!< CLK_T::PLLFNCTL1: BP Mask */ + +#define CLK_PLLFNCTL1_OE_Pos (30) /*!< CLK_T::PLLFNCTL1: OE Position */ +#define CLK_PLLFNCTL1_OE_Msk (0x1ul << CLK_PLLFNCTL1_OE_Pos) /*!< CLK_T::PLLFNCTL1: OE Mask */ + +#define CLK_PLLFNCTL1_PLLSRC_Pos (31) /*!< CLK_T::PLLFNCTL1: PLLSRC Position */ +#define CLK_PLLFNCTL1_PLLSRC_Msk (0x1ul << CLK_PLLFNCTL1_PLLSRC_Pos) /*!< CLK_T::PLLFNCTL1: PLLSRC Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ +#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_HIRC48MSTB_Pos (6) /*!< CLK_T::STATUS: HIRC48MSTB Position */ +#define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos) /*!< CLK_T::STATUS: HIRC48MSTB Mask */ + +#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ +#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ + +#define CLK_STATUS_PLLFNSTB_Pos (10) /*!< CLK_T::STATUS: PLLFNSTB Position */ +#define CLK_STATUS_PLLFNSTB_Msk (0x1ul << CLK_STATUS_PLLFNSTB_Pos) /*!< CLK_T::STATUS: PLLFNSTB Mask */ + +#define CLK_AHBCLK1_CANFD0CKEN_Pos (20) /*!< CLK_T::AHBCLK1: CANFD0CKEN Position */ +#define CLK_AHBCLK1_CANFD0CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD0CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD0CKEN Mask */ + +#define CLK_AHBCLK1_CANFD1CKEN_Pos (21) /*!< CLK_T::AHBCLK1: CANFD1CKEN Position */ +#define CLK_AHBCLK1_CANFD1CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD1CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD1CKEN Mask */ + +#define CLK_AHBCLK1_CANFD2CKEN_Pos (22) /*!< CLK_T::AHBCLK1: CANFD2CKEN Position */ +#define CLK_AHBCLK1_CANFD2CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD2CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD2CKEN Mask */ + +#define CLK_AHBCLK1_CANFD3CKEN_Pos (23) /*!< CLK_T::AHBCLK1: CANFD3CKEN Position */ +#define CLK_AHBCLK1_CANFD3CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD3CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD3CKEN Mask */ + +#define CLK_AHBCLK1_GPICKEN_Pos (24) /*!< CLK_T::AHBCLK1: GPICKEN Position */ +#define CLK_AHBCLK1_GPICKEN_Msk (0x1ul << CLK_AHBCLK1_GPICKEN_Pos) /*!< CLK_T::AHBCLK1: GPICKEN Mask */ + +#define CLK_AHBCLK1_GPJCKEN_Pos (25) /*!< CLK_T::AHBCLK1: GPJCKEN Position */ +#define CLK_AHBCLK1_GPJCKEN_Msk (0x1ul << CLK_AHBCLK1_GPJCKEN_Pos) /*!< CLK_T::AHBCLK1: GPJCKEN Mask */ + +#define CLK_AHBCLK1_BMCCKEN_Pos (28) /*!< CLK_T::AHBCLK1: BMCCKEN Position */ +#define CLK_AHBCLK1_BMCCKEN_Msk (0x1ul << CLK_AHBCLK1_BMCCKEN_Pos) /*!< CLK_T::AHBCLK1: BMCCKEN Mask */ + +#define CLK_CLKSEL4_SPI4SEL_Pos (0) /*!< CLK_T::CLKSEL4: SPI4SEL Position */ +#define CLK_CLKSEL4_SPI4SEL_Msk (0x7ul << CLK_CLKSEL4_SPI4SEL_Pos) /*!< CLK_T::CLKSEL4: SPI4SEL Mask */ + +#define CLK_CLKSEL4_SPI5SEL_Pos (4) /*!< CLK_T::CLKSEL4: SPI5SEL Position */ +#define CLK_CLKSEL4_SPI5SEL_Msk (0x7ul << CLK_CLKSEL4_SPI5SEL_Pos) /*!< CLK_T::CLKSEL4: SPI5SEL Mask */ + +#define CLK_CLKSEL4_SPI6SEL_Pos (8) /*!< CLK_T::CLKSEL4: SPI6SEL Position */ +#define CLK_CLKSEL4_SPI6SEL_Msk (0x7ul << CLK_CLKSEL4_SPI6SEL_Pos) /*!< CLK_T::CLKSEL4: SPI6SEL Mask */ + +#define CLK_CLKSEL4_SPI7SEL_Pos (12) /*!< CLK_T::CLKSEL4: SPI7SEL Position */ +#define CLK_CLKSEL4_SPI7SEL_Msk (0x7ul << CLK_CLKSEL4_SPI7SEL_Pos) /*!< CLK_T::CLKSEL4: SPI7SEL Mask */ + +#define CLK_CLKSEL4_SPI8SEL_Pos (16) /*!< CLK_T::CLKSEL4: SPI8SEL Position */ +#define CLK_CLKSEL4_SPI8SEL_Msk (0x7ul << CLK_CLKSEL4_SPI8SEL_Pos) /*!< CLK_T::CLKSEL4: SPI8SEL Mask */ + +#define CLK_CLKSEL4_SPI9SEL_Pos (20) /*!< CLK_T::CLKSEL4: SPI9SEL Position */ +#define CLK_CLKSEL4_SPI9SEL_Msk (0x7ul << CLK_CLKSEL4_SPI9SEL_Pos) /*!< CLK_T::CLKSEL4: SPI9SEL Mask */ + +#define CLK_CLKSEL4_SPI10SEL_Pos (24) /*!< CLK_T::CLKSEL4: SPI10SEL Position */ +#define CLK_CLKSEL4_SPI10SEL_Msk (0x7ul << CLK_CLKSEL4_SPI10SEL_Pos) /*!< CLK_T::CLKSEL4: SPI10SEL Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ +#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDCTL_HXTFQASW_Pos (18) /*!< CLK_T::CLKDCTL: HXTFQASW Position */ +#define CLK_CLKDCTL_HXTFQASW_Msk (0x1ul << CLK_CLKDCTL_HXTFQASW_Pos) /*!< CLK_T::CLKDCTL: HXTFQASW Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_STOPREQ_CANFD0STR_Pos (0) /*!< CLK_T::STOPREQ: CANFD0STR Position */ +#define CLK_STOPREQ_CANFD0STR_Msk (0x1ul << CLK_STOPREQ_CANFD0STR_Pos) /*!< CLK_T::STOPREQ: CANFD0STR Mask */ + +#define CLK_STOPREQ_CANFD1STR_Pos (1) /*!< CLK_T::STOPREQ: CANFD1STR Position */ +#define CLK_STOPREQ_CANFD1STR_Msk (0x1ul << CLK_STOPREQ_CANFD1STR_Pos) /*!< CLK_T::STOPREQ: CANFD1STR Mask */ + +#define CLK_STOPREQ_CANFD2STR_Pos (2) /*!< CLK_T::STOPREQ: CANFD2STR Position */ +#define CLK_STOPREQ_CANFD2STR_Msk (0x1ul << CLK_STOPREQ_CANFD2STR_Pos) /*!< CLK_T::STOPREQ: CANFD2STR Mask */ + +#define CLK_STOPREQ_CANFD3STR_Pos (3) /*!< CLK_T::STOPREQ: CANFD3STR Position */ +#define CLK_STOPREQ_CANFD3STR_Msk (0x1ul << CLK_STOPREQ_CANFD3STR_Pos) /*!< CLK_T::STOPREQ: CANFD3STR Mask */ + +#define CLK_STOPACK_CANFD0STA_Pos (0) /*!< CLK_T::STOPACK: CANFD0STA Position */ +#define CLK_STOPACK_CANFD0STA_Msk (0x1ul << CLK_STOPACK_CANFD0STA_Pos) /*!< CLK_T::STOPACK: CANFD0STA Mask */ + +#define CLK_STOPACK_CANFD1STA_Pos (1) /*!< CLK_T::STOPACK: CANFD1STA Position */ +#define CLK_STOPACK_CANFD1STA_Msk (0x1ul << CLK_STOPACK_CANFD1STA_Pos) /*!< CLK_T::STOPACK: CANFD1STA Mask */ + +#define CLK_STOPACK_CANFD2STA_Pos (2) /*!< CLK_T::STOPACK: CANFD2STA Position */ +#define CLK_STOPACK_CANFD2STA_Msk (0x1ul << CLK_STOPACK_CANFD2STA_Pos) /*!< CLK_T::STOPACK: CANFD2STA Mask */ + +#define CLK_STOPACK_CANFD3STA_Pos (3) /*!< CLK_T::STOPACK: CANFD3STA Position */ +#define CLK_STOPACK_CANFD3STA_Msk (0x1ul << CLK_STOPACK_CANFD3STA_Pos) /*!< CLK_T::STOPACK: CANFD3STA Mask */ + +#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ +#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ + +#define CLK_PMUCTL_DPDHOLDEN_Pos (3) /*!< CLK_T::PMUCTL: DPDHOLDEN Position */ +#define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos) /*!< CLK_T::PMUCTL: DPDHOLDEN Mask */ + +#define CLK_PMUCTL_SRETSEL_Pos (4) /*!< CLK_T::PMUCTL: SRETSEL Position */ +#define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) /*!< CLK_T::PMUCTL: SRETSEL Mask */ + +#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ +#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ + +#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ +#define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ + +#define CLK_PMUCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN0 Position */ +#define CLK_PMUCTL_WKPINEN0_Msk (0x3ul << CLK_PMUCTL_WKPINEN0_Pos) /*!< CLK_T::PMUCTL: WKPINEN0 Mask */ + +#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ +#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ + +#define CLK_PMUCTL_VBUSWKEN_Pos (22) /*!< CLK_T::PMUCTL: VBUSWKEN Position */ +#define CLK_PMUCTL_VBUSWKEN_Msk (0x1ul << CLK_PMUCTL_VBUSWKEN_Pos) /*!< CLK_T::PMUCTL: VBUSWKEN Mask */ + +#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ +#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ + +#define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ +#define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ + +#define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ +#define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ + +#define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ +#define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ + +#define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ +#define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ + +#define CLK_PMUSTS_PINWK0_Pos (0) /*!< CLK_T::PMUSTS: PINWK0 Position */ +#define CLK_PMUSTS_PINWK0_Msk (0x1ul << CLK_PMUSTS_PINWK0_Pos) /*!< CLK_T::PMUSTS: PINWK0 Mask */ + +#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ +#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ + +#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ +#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ + +#define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ +#define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ + +#define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ +#define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ + +#define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ +#define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ + +#define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ +#define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ + +#define CLK_PMUSTS_VBUSWK_Pos (7) /*!< CLK_T::PMUSTS: VBUSWK Position */ +#define CLK_PMUSTS_VBUSWK_Msk (0x1ul << CLK_PMUSTS_VBUSWK_Pos) /*!< CLK_T::PMUSTS: VBUSWK Mask */ + +#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ +#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ + +#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ +#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ + +#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ +#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ + +#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ +#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ + +#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ +#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ + +#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ +#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ + +#define CLK_PMUSTS_RSTWK_Pos (15) /*!< CLK_T::PMUSTS: RSTWK Position */ +#define CLK_PMUSTS_RSTWK_Msk (0x1ul << CLK_PMUSTS_RSTWK_Pos) /*!< CLK_T::PMUSTS: RSTWK Mask */ + +#define CLK_PMUSTS_ACMPWK0_Pos (16) /*!< CLK_T::PMUSTS: ACMPWK0 Position */ +#define CLK_PMUSTS_ACMPWK0_Msk (0x1ul << CLK_PMUSTS_ACMPWK0_Pos) /*!< CLK_T::PMUSTS: ACMPWK0 Mask */ + +#define CLK_PMUSTS_ACMPWK1_Pos (17) /*!< CLK_T::PMUSTS: ACMPWK1 Position */ +#define CLK_PMUSTS_ACMPWK1_Msk (0x1ul << CLK_PMUSTS_ACMPWK1_Pos) /*!< CLK_T::PMUSTS: ACMPWK1 Mask */ + +#define CLK_PMUSTS_ACMPWK2_Pos (18) /*!< CLK_T::PMUSTS: ACMPWK2 Position */ +#define CLK_PMUSTS_ACMPWK2_Msk (0x1ul << CLK_PMUSTS_ACMPWK2_Pos) /*!< CLK_T::PMUSTS: ACMPWK2 Mask */ + +#define CLK_PMUSTS_ACMPWK3_Pos (19) /*!< CLK_T::PMUSTS: ACMPWK3 Position */ +#define CLK_PMUSTS_ACMPWK3_Msk (0x1ul << CLK_PMUSTS_ACMPWK3_Pos) /*!< CLK_T::PMUSTS: ACMPWK3 Mask */ + +#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ +#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ + +#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ + +#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ +#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ + +#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ +#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ + +#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ +#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ + +#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ +#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ + +#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ +#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ + +#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ +#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ + +#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ +#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ + +#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ +#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ + +#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ +#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ + +#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ +#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ + +#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ +#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ + +#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ +#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ + +#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ +#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ + +#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ +#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ + +#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ +#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ + +#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ +#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ + +#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ +#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ + +#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ +#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ + +#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ +#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ + +#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ +#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ + +#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ +#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ + + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CLK_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/crc_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/crc_reg.h new file mode 100644 index 0000000..a31c304 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/crc_reg.h @@ -0,0 +1,166 @@ +/**************************************************************************//** + * @file crc_reg.h + * @version V3.00 + * @brief CRC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_REG_H__ +#define __CRC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Cyclic Redundancy Check Controller -------------------------*/ +/** + @addtogroup CRC Cyclic Redundancy Check Controller(CRC) + Memory Mapped Structure for CRC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCEN |CRC Channel Enable Bit + * | | |0 = No effect. + * | | |1 = CRC operation Enabled. + * |[1] |CHKSINIT |Checksum Initialization + * | | |0 = No effect. + * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value. + * | | |Note: This bit will be cleared automatically and written only. + * |[24] |DATREV |Write Data Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. + * | | |0 = Bit order reversed for CRC write data in Disabled. + * | | |1 = Bit order reversed for CRC write data in Enabled (per byte). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. + * |[25] |CHKSREV |Checksum Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. + * | | |0 = Bit order reverse for CRC checksum Disabled. + * | | |1 = Bit order reverse for CRC checksum Enabled. + * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. + * |[26] |DATFMT |Write Data 1's Complement + * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register. + * | | |0 = 1's complement for CRC writes data in Disabled. + * | | |1 = 1's complement for CRC writes data in Enabled. + * |[27] |CHKSFMT |Checksum 1's Complement + * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. + * | | |0 = 1's complement for CRC checksum Disabled. + * | | |0 = 1's complement for CRC checksum Enabled. + * |[29:28] |DATLEN |CPU Write Data Length + * | | |This field indicates the write data length. + * | | |00 = Data length is 8-bit mode. + * | | |01 = Data length is 16-bit mode. + * | | |1x = Data length is 32-bit mode. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * |[31:30] |CRCMODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |01 = CRC-8 Polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |11 = CRC-32 Polynomial mode. + * | | |Note: User must program the polynomial value in CRC_POLYNOMIAL register to specify the polynomial used for CRC calculation. + * @var CRC_T::DAT + * Offset: 0x04 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |CRC Write Data Bits + * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * @var CRC_T::SEED + * Offset: 0x08 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |CRC Seed Value + * | | |This field indicates the CRC seed value. + * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). + * @var CRC_T::CHECKSUM + * Offset: 0x0C CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CHECKSUM |CRC Checksum Results + * | | |This field indicates the CRC checksum result. + * | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). + * @var CRC_T::POLYNOMIAL + * Offset: 0x10 CRC Polynomial Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POLYNOMIAL |CRC Polynomial Register + * | | |This field indicates the value of CRC polynomial. + */ + __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ + __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ + __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ + __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ + __IO uint32_t POLYNOMIAL; /*!< [0x0010] CRC Polynomial Register */ + +} CRC_T; + +/** + @addtogroup CRC_CONST CRC Bit Field Definition + Constant Definitions for CRC Controller + @{ +*/ + +#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ +#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ + +#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ +#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ + +#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ +#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ + +#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ +#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ + +#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ +#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ + +#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ +#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ + +#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ +#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ + +#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ +#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ + +#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ +#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ + +#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ +#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ + +#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ +#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ + +#define CRC_POLYNOMIAL_POLYNOMIAL_Pos (0) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Position */ +#define CRC_POLYNOMIAL_POLYNOMIAL_Msk (0xfffffffful << CRC_POLYNOMIAL_POLYNOMIAL_Pos) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Mask */ + + +/**@}*/ /* CRC_CONST */ +/**@}*/ /* end of CRC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/crypto_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/crypto_reg.h new file mode 100644 index 0000000..6a9e2ef --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/crypto_reg.h @@ -0,0 +1,6827 @@ +/**************************************************************************//** + * @file crypto_reg.h + * @version V1.00 + * @brief CRYPTO register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRYPTO_REG_H__ +#define __CRYPTO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + + +/*---------------------- Cryptographic Accelerator -------------------------*/ +/** + @addtogroup CRPT Cryptographic Accelerator(CRPT) + Memory Mapped Structure for CRPT Controller +@{ */ + +typedef struct +{ + + +/** + * @var CRPT_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Bit + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when an amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Bit + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Bit + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * |[17] |PRNGEIEN |PRNG Error Flag Enable Bit + * | | |0 = PRNG error interrupt flag Disabled. + * | | |1 = PRNG error interrupt flag Enabled. + * |[22] |ECCIEN |ECC Interrupt Enable Bit + * | | |0 = ECC interrupt Disabled. + * | | |1 = ECC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when an amount of data set in ECC_DMA_CNT is fed into the ECC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. + * |[23] |ECCEIEN |ECC Error Interrupt Enable Bit + * | | |0 = ECC error interrupt flag Disabled. + * | | |1 = ECC error interrupt flag Enabled. + * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Bit + * | | |0 = SHA/HMAC interrupt Disabled. + * | | |1 = SHA/HMAC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when an amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. + * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Bit + * | | |0 = SHA/HMAC error interrupt flag Disabled. + * | | |1 = HMAC error interrupt flag Enabled. + * |[30] |RSAIEN |RSA Interrupt Enable Bit + * | | |0 = RSA interrupt Disabled. + * | | |1 = RSA interrupt Enabled. + * |[31] |RSAEIEN |RSA Error Interrupt Enable Bit + * | | |0 = RSA error interrupt flag Disabled. + * | | |1 = RSA error interrupt flag Enabled. + * @var CRPT_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |0 = No AES interrupt. + * | | |1 = AES encryption/decryption done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[1] |AESEIF |AES Error Flag + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[17] |PRNGEIF |PRNG Error Flag + * | | |0 = No PRNG error. + * | | |1 = PRNG key generation error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[22] |ECCIF |ECC Finish Interrupt Flag + * | | |0 = No ECC interrupt. + * | | |1 = ECC operation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[23] |ECCEIF |ECC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register. + * | | |0 = No ECC error. + * | | |1 = ECC error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag + * | | |0 = No SHA/HMAC interrupt. + * | | |1 = SHA/HMAC operation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[25] |HMACEIF |SHA/HMAC Error Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register. + * | | |0 = No SHA/HMAC error. + * | | |1 = SHA/HMAC error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[30] |RSAIF |RSA Finish Interrupt Flag + * | | |0 = No RSA interrupt. + * | | |1 = RSA operation done interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * |[31] |RSAEIF |RSA Error Interrupt Flag + * | | |This register includes operating and setting error. The detail flag is shown in CRPT_RSA_STS register. + * | | |0 = No RSA error. + * | | |1 = RSA error interrupt. + * | | |Note: This bit is cleared by writing 1, and it has no effect by writing 0. + * @var CRPT_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[5:2] |KEYSZ |PRNG Generate Key Size + * | | |0000 = 128 bits. + * | | |0001 = 163 bits. + * | | |0010 = 192 bits. + * | | |0011 = 224 bits. + * | | |0100 = 233 bits. + * | | |0101 = 255 bits. + * | | |0110 = 256 bits. + * | | |0111 = 283 bits (only for KS). + * | | |1000 = 384 bits (only for KS). + * | | |1001 = 409 bits (only for KS). + * | | |1010 = 512 bits (only for KS). + * | | |1011 = 521 bits (only for KS). + * | | |1100 = 571 bits (only for KS). + * | | |1101 = Reserved. + * | | |1110 = Reserved. + * | | |1111 = Reserved. + * | | |Note: 283~571 bits are only generated for key store. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = PRNG engine is generating CRPT_PRNG_KEYx. + * |[16] |SEEDSRC |Seed Source + * | | |0 = Seed is from TRNG. + * | | |1 = Seed is from PRNG seed register. + * | | |Note: When SEEDRLD is set to 0, this bit (SEEDSRC) is meaningless. + * @var CRPT_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * | | |Note: In TRNG+PRNG mode, the seed is from TRNG engine, and it will not be stored in this register. + * @var CRPT_T::PRNG_KEY0 + * Offset: 0x10 PRNG Generated Key0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_KEY1 + * Offset: 0x14 PRNG Generated Key1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_KEY2 + * Offset: 0x18 PRNG Generated Key2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_KEY3 + * Offset: 0x1C PRNG Generated Key3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_KEY4 + * Offset: 0x20 PRNG Generated Key4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_KEY5 + * Offset: 0x24 PRNG Generated Key5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_KEY6 + * Offset: 0x28 PRNG Generated Key6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_KEY7 + * Offset: 0x2C PRNG Generated Key7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_STS + * Offset: 0x30 PRNG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |PRNG Busy Flag + * | | |0 = PRNG engine is idle. + * | | |1 = PRNG engine is generating CRPT_PRNG_KEYx. + * |[16] |KCTLERR |PRNG Key Control Register Error Flag + * | | |0 = No error. + * | | |1 = PRNG key control error + * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). + * |[17] |KSERR |PRNG Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access key store failed. + * @var CRPT_T::AES_FDBCK0 + * Offset: 0x50 AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next blocku2019s operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::AES_FDBCK1 + * Offset: 0x54 AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next blocku2019s operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::AES_FDBCK2 + * Offset: 0x58 AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next blocku2019s operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::AES_FDBCK3 + * Offset: 0x5C AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next blocku2019s operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::AES_GCM_IVCNT0 + * Offset: 0x80 AES GCM IV Byte Count Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM IV Byte Count + * | | |The bit length of IV is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_IVCNT0 keeps the low weight byte count of initial vector (i.e., len(IV)[34:3]) of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_IVCNT1 + * Offset: 0x84 AES GCM IV Byte Count Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |CNT |AES GCM IV Byte Count + * | | |The bit length of IV is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_IVCNT1 keeps the high weight byte count of initial vector (i.e., len(IV)[64:35]) of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_ACNT0 + * Offset: 0x88 AES GCM A Byte Count Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM a Byte Count + * | | |The bit length of A is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_ACNT0 keeps the low weight byte count of the additional authenticated data (i.e., len(A)[34:3]) of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_ACNT1 + * Offset: 0x8C AES GCM A Byte Count Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |CNT |AES GCM a Byte Count + * | | |The bit length of A is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_ACNT0 keeps the high weight byte count of the additional authenticated data (i.e., len(A)[63:35]) of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_PCNT0 + * Offset: 0x90 AES GCM P Byte Count Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM P Byte Count + * | | |The bit length of Por C is 39 bits for AES GCM mode + * | | |The CRPT_AES_GCM_PCNT0 keeps the low weight byte count of the plaintext or ciphertext (i.e., len(P)[34:3] or len(C)[34:3]) of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_PCNT1 + * Offset: 0x94 AES GCM P Byte Count Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[28:0] |CNT |AES GCM P Byte Count + * | | |The bit length of Por C is 39 bits for AES GCM mode + * | | |The CRPT_AES_GCM_PCNT1 keeps the high weight byte count of the plaintext or ciphertext (i.e., len(P)[38:35] or len(C)[38:35]) of AES GCM mode and can be read and written. + * | | |The bit length of Por C is 64 bits for AES CCM mode + * | | |The CRPT_AES_GCM_PCNT1 keeps the high weight byte count of the plaintext or ciphertext (i.e., len(P)[63:35] or len(C)[63:35]) of AES CCM mode and can be read and written. + * @var CRPT_T::AES_FBADDR + * Offset: 0xA0 AES DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |AES DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedback address register for automatically reading and writing feedback values via DMA + * | | |The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the AES accelerator can read the feedback data of the last cascade operation from SRAM memory space and write the feedback data of the current cascade operation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRPT_AES_FBADDR before triggering START. + * @var CRPT_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it is read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it is read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2u2019b00 = 128 bits key. + * | | |2u2019b01 = 192 bits key. + * | | |2u2019b10 = 256 bits key. + * | | |2u2019b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it is read back, and must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * | | |Note: The last two blocks of AES-CBC-CS1/2/3 must be in the last cascade operation. + * |[7] |DMAEN |AES Engine DMA Enable Bit + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * | | |0x20 = GCM (Galois/Counter Mode). + * | | |0x21 = GHASH (Galois Hash Function). + * | | |0x22 = CCM (Counter with CBC-MAC Mode). + * |[16] |ENCRYPTO |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[20] |FBIN |Feedback Input to AES Via DMA Automatically + * | | |0 = DMA automatic feedback input function Disabled. + * | | |1 = DMA automatic feedback input function Enabled when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From AES Via DMA Automatically + * | | |0 = DMA automatic feedback output function Disabled. + * | | |1 = DMA automatic feedback output function Enabled when DMAEN = 1. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU reads data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[24] |KOUTSWAP |AES Engine Output Key, Initial Vector and Feedback Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU reads key, initial vector and feedback from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25] |KINSWAP |AES Engine Input Key and Initial Vector Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds key and initial vector to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_AES_CTL[31] and u201C10110u201D to CRPT_AES_CTL[30:26] is to unprotect the AES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |The key content would be cleared as well. + * @var CRPT_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happened during feeding data to the AES engine. + * |[12] |CNTERR |CRPT_AES_CNT Setting Error + * | | |0 = No error in CRPT_AES_CNT setting. + * | | |1 = CRPT_AES_CNT is 0 if DMAEN (CRPT_AES_CTL[7]) is enabled. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRPT_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happened during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * |[21] |KSERR |AES Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Key store access error will stop AES engine. + * @var CRPT_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. + * @var CRPT_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::AES_KEY0 + * Offset: 0x110 AES Key Word 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_KEY1 + * Offset: 0x114 AES Key Word 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_KEY2 + * Offset: 0x118 AES Key Word 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_KEY3 + * Offset: 0x11C AES Key Word 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_KEY4 + * Offset: 0x120 AES Key Word 4 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_KEY5 + * Offset: 0x124 AES Key Word 5 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_KEY6 + * Offset: 0x128 AES Key Word 6 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_KEY7 + * Offset: 0x12C AES Key Word 7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_IV0 + * Offset: 0x130 AES Initial Vector Word 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES_IV1 + * Offset: 0x134 AES Initial Vector Word 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES_IV2 + * Offset: 0x138 AES Initial Vector Word 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES_IV3 + * Offset: 0x13C AES Initial Vector Word 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES_SADDR + * Offset: 0x140 AES DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (decryption) from SRAM memory space and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_DADDR + * Offset: 0x144 AES DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine outputu2019s text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_CNT + * Offset: 0x148 AES Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AES_CNT can be read and written + * | | |Writing to CRPT_AES_CNT while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of CRPT_AES_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes + * | | |Operations that are qual or less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, CTR, CCM and GCM mode, CRPT_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * | | |In AES GCM mode without DMA cascade function, the value of CRPT_AES_CNT is equal to the total value of {CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. + * | | |In AES GCM mode with DMA cascade function, the value of CRPT_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment. + * | | |In AES CCM mode without DMA cascade function, the value of CRPT_AES_CNT is equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. + * | | |In AES CCM mode with DMA cascade function, the value of CRPT_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment, except for the last block of plaintext or ciphertext. + * @var CRPT_T::HMAC_CTL + * Offset: 0x300 SHA/HMAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |SHA/HMAC Engine Start + * | | |0 = No effect. + * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it is read back. + * |[1] |STOP |SHA/HMAC Engine Stop + * | | |0 = No effect. + * | | |1 = Stop SHA/HMAC engine. + * | | |Note: This bit is always 0 when it is read back. + * |[4] |DMAFIRST |SHA/HMAC First Block in Cascade function + * | | |This bit must be set as feeding in first byte of data. + * |[5] |DMALAST |SHA/HMAC Last Block + * | | |This bit must be set as feeding in last byte of data. + * |[6] |DMACSCAD |SHA/HMAC Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Bit + * | | |0 = SHA/HMAC DMA engine Disabled. + * | | |SHA/HMAC engine operates in Non-DMA mode. The data need to be written in CRPT_HMAC_DATIN. + * | | |1 = SHA/HMAC DMA engine Enabled. + * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes + * | | |When SHA3EN=0,. + * | | |0x0xx: SHA1-160 + * | | |0x100: SHA2-256 + * | | |0x101: SHA2-224 + * | | |0x110: SHA2-512 + * | | |0x111: SHA2-384 + * | | |When SHA3EN=1,. + * | | |0x100: SHA3-256 + * | | |0x101: SHA3-224 + * | | |0x110: SHA3-512 + * | | |0x111: SHA3-384 + * | | |0x000: SHAKE128 + * | | |0x001: SHAKE256 + * | | |Note: These bits can be read and written. But writing to them wouldnu2019t take effect as BUSY is 1. + * |[11] |HMACEN |HMAC_SHA Engine Operating Mode + * | | |0 = Execute SHA function. + * | | |1 = Execute HMAC function. + * |[12] |SHA3EN |SHA3 Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute SHA3 function. + * |[20] |FBIN |Feedback Input to SHA/HMAC Via DMA Automatically + * | | |0 = DMA automatic feedback input function Disabled. + * | | |1 = DMA automatic feedback input function Enabled when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From SHA/HMAC Via DMA Automatically + * | | |0 = DMA automatic feedback output function Disabled. + * | | |1 = DMA automatic feedback output function Enabled when DMAEN = 1. + * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[24] |NEXTDGST |SHAKE128/256 Next Digest Start + * | | |0 = No effect. + * | | |1 = Start SHAKE engine to generate the next digest only when SHAKEBUSY is 0 + * | | |BUSY and SHAKEBUSY flag will be set. + * |[25] |FINISHDGST|SHAKE128/256 Next Digest Finish + * | | |0 = No effect. + * | | |1 = finish generating the next digest. + * @var CRPT_T::HMAC_STS + * Offset: 0x304 SHA/HMAC Status Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |SHA/HMAC Engine Busy + * | | |0 = SHA/HMAC engine is idle or finished. + * | | |1 = SHA/HMAC engine is busy. + * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag + * | | |0 = SHA/HMAC DMA engine is idle or finished. + * | | |1 = SHA/HMAC DMA engine is busy. + * |[2] |SHAKEBUSY |SHAKE Engine Busy Flag + * | | |0 = SHAKE engine is idle or finished. + * | | |1 = SHAKE engine is busy. + * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag + * | | |0 = Show the SHA/HMAC engine access normal. + * | | |1 = Show the SHA/HMAC engine access error. + * |[9] |KSERR |HMAC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop HMAC engine. + * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request + * | | |0 = No effect. + * | | |1 = Request SHA/HMAC Non-DMA mode data input. + * @var CRPT_T::HMAC_DGST0 + * Offset: 0x308 SHA/HMAC Output Feedback Data 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST1 + * Offset: 0x30C SHA/HMAC Output Feedback Data 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST2 + * Offset: 0x310 SHA/HMAC Output Feedback Data 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST3 + * Offset: 0x314 SHA/HMAC Output Feedback Data 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST4 + * Offset: 0x318 SHA/HMAC Output Feedback Data 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST5 + * Offset: 0x31C SHA/HMAC Output Feedback Data 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST6 + * Offset: 0x320 SHA/HMAC Output Feedback Data 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST7 + * Offset: 0x324 SHA/HMAC Output Feedback Data 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST8 + * Offset: 0x328 SHA/HMAC Output Feedback Data 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST9 + * Offset: 0x32C SHA/HMAC Output Feedback Data 9 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST10 + * Offset: 0x330 SHA/HMAC Output Feedback Data 10 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST11 + * Offset: 0x334 SHA/HMAC Output Feedback Data 11 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST12 + * Offset: 0x338 SHA/HMAC Output Feedback Data 12 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST13 + * Offset: 0x33C SHA/HMAC Output Feedback Data 13 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST14 + * Offset: 0x340 SHA/HMAC Output Feedback Data 14 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_DGST15 + * Offset: 0x344 SHA/HMAC Output Feedback Data 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC Output Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_KEYCNT + * Offset: 0x348 SHA/HMAC Key Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count + * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates + * | | |The register is 32-bit and the maximum byte count is 4G bytes + * | | |It can be read and written. + * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_KEYCNT will be updated later on + * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. + * @var CRPT_T::HMAC_SADDR + * Offset: 0x34C SHA/HMAC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |SHA/HMAC DMA Source Address + * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. + * | | |CRPT_HMAC_SADDR can be read and written + * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. + * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. + * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. + * @var CRPT_T::HMAC_DMACNT + * Offset: 0x350 SHA/HMAC Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count + * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode + * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_HMAC_DMACNT can be read and written + * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_DMACNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. + * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. + * @var CRPT_T::HMAC_DATIN + * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |SHA/HMAC Engine Input Port + * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS + * | | |Feed data as DATINREQ is 1. + * @var CRPT_T::HMAC_FDBCK0 + * Offset: 0x358 SHA/HMAC Output Feedback Data 0 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK1 + * Offset: 0x35C SHA/HMAC Output Feedback Data 1 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK2 + * Offset: 0x360 SHA/HMAC Output Feedback Data 2 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK3 + * Offset: 0x364 SHA/HMAC Output Feedback Data 3 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK4 + * Offset: 0x368 SHA/HMAC Output Feedback Data 4 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK5 + * Offset: 0x36C SHA/HMAC Output Feedback Data 5 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK6 + * Offset: 0x370 SHA/HMAC Output Feedback Data 6 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK7 + * Offset: 0x374 SHA/HMAC Output Feedback Data 7 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK8 + * Offset: 0x378 SHA/HMAC Output Feedback Data 8 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK9 + * Offset: 0x37C SHA/HMAC Output Feedback Data 9 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK10 + * Offset: 0x380 SHA/HMAC Output Feedback Data 10 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK11 + * Offset: 0x384 SHA/HMAC Output Feedback Data 11 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK12 + * Offset: 0x388 SHA/HMAC Output Feedback Data 12 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK13 + * Offset: 0x38C SHA/HMAC Output Feedback Data 13 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK14 + * Offset: 0x390 SHA/HMAC Output Feedback Data 14 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK15 + * Offset: 0x394 SHA/HMAC Output Feedback Data 15 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK16 + * Offset: 0x398 SHA/HMAC Output Feedback Data 16 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK17 + * Offset: 0x39C SHA/HMAC Output Feedback Data 17 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK18 + * Offset: 0x3A0 SHA/HMAC Output Feedback Data 18 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK19 + * Offset: 0x3A4 SHA/HMAC Output Feedback Data 19 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK20 + * Offset: 0x3A8 SHA/HMAC Output Feedback Data 20 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK21 + * Offset: 0x3AC SHA/HMAC Output Feedback Data 21 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK22 + * Offset: 0x3B0 SHA/HMAC Output Feedback Data 22 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK23 + * Offset: 0x3B4 SHA/HMAC Output Feedback Data 23 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK24 + * Offset: 0x3B8 SHA/HMAC Output Feedback Data 24 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK25 + * Offset: 0x3BC SHA/HMAC Output Feedback Data 25 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK26 + * Offset: 0x3C0 SHA/HMAC Output Feedback Data 26 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK27 + * Offset: 0x3C4 SHA/HMAC Output Feedback Data 27 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK28 + * Offset: 0x3C8 SHA/HMAC Output Feedback Data 28 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK29 + * Offset: 0x3CC SHA/HMAC Output Feedback Data 29 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK30 + * Offset: 0x3D0 SHA/HMAC Output Feedback Data 30 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK31 + * Offset: 0x3D4 SHA/HMAC Output Feedback Data 31 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK32 + * Offset: 0x3D8 SHA/HMAC Output Feedback Data 32 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK33 + * Offset: 0x3DC SHA/HMAC Output Feedback Data 33 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK34 + * Offset: 0x3E0 SHA/HMAC Output Feedback Data 34 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK35 + * Offset: 0x3E4 SHA/HMAC Output Feedback Data 35 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK36 + * Offset: 0x3E8 SHA/HMAC Output Feedback Data 36 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK37 + * Offset: 0x3EC SHA/HMAC Output Feedback Data 37 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK38 + * Offset: 0x3F0 SHA/HMAC Output Feedback Data 38 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK39 + * Offset: 0x3F4 SHA/HMAC Output Feedback Data 39 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK40 + * Offset: 0x3F8 SHA/HMAC Output Feedback Data 40 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK41 + * Offset: 0x3FC SHA/HMAC Output Feedback Data 41 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK42 + * Offset: 0x400 SHA/HMAC Output Feedback Data 42 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK43 + * Offset: 0x404 SHA/HMAC Output Feedback Data 43 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK44 + * Offset: 0x408 SHA/HMAC Output Feedback Data 44 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK45 + * Offset: 0x40C SHA/HMAC Output Feedback Data 45 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK46 + * Offset: 0x410 SHA/HMAC Output Feedback Data 46 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK47 + * Offset: 0x414 SHA/HMAC Output Feedback Data 47 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK48 + * Offset: 0x418 SHA/HMAC Output Feedback Data 48 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK49 + * Offset: 0x41C SHA/HMAC Output Feedback Data 49 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK50 + * Offset: 0x420 SHA/HMAC Output Feedback Data 50 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK51 + * Offset: 0x424 SHA/HMAC Output Feedback Data 51 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK52 + * Offset: 0x428 SHA/HMAC Output Feedback Data 52 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK53 + * Offset: 0x42C SHA/HMAC Output Feedback Data 53 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK54 + * Offset: 0x430 SHA/HMAC Output Feedback Data 54 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK55 + * Offset: 0x434 SHA/HMAC Output Feedback Data 55 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK56 + * Offset: 0x438 SHA/HMAC Output Feedback Data 56 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK57 + * Offset: 0x43C SHA/HMAC Output Feedback Data 57 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK58 + * Offset: 0x440 SHA/HMAC Output Feedback Data 58 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK59 + * Offset: 0x444 SHA/HMAC Output Feedback Data 59 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK60 + * Offset: 0x448 SHA/HMAC Output Feedback Data 60 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK61 + * Offset: 0x44C SHA/HMAC Output Feedback Data 61 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK62 + * Offset: 0x450 SHA/HMAC Output Feedback Data 62 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK63 + * Offset: 0x454 SHA/HMAC Output Feedback Data 63 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK64 + * Offset: 0x458 SHA/HMAC Output Feedback Data 64 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK65 + * Offset: 0x45C SHA/HMAC Output Feedback Data 65 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK66 + * Offset: 0x460 SHA/HMAC Output Feedback Data 66 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK67 + * Offset: 0x464 SHA/HMAC Output Feedback Data 67 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK68 + * Offset: 0x468 SHA/HMAC Output Feedback Data 68 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK69 + * Offset: 0x46C SHA/HMAC Output Feedback Data 69 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK70 + * Offset: 0x470 SHA/HMAC Output Feedback Data 70 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK71 + * Offset: 0x474 SHA/HMAC Output Feedback Data 71 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK72 + * Offset: 0x478 SHA/HMAC Output Feedback Data 72 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK73 + * Offset: 0x47C SHA/HMAC Output Feedback Data 73 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK74 + * Offset: 0x480 SHA/HMAC Output Feedback Data 74 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK75 + * Offset: 0x484 SHA/HMAC Output Feedback Data 75 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK76 + * Offset: 0x488 SHA/HMAC Output Feedback Data 76 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK77 + * Offset: 0x48C SHA/HMAC Output Feedback Data 77 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK78 + * Offset: 0x490 SHA/HMAC Output Feedback Data 78 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK79 + * Offset: 0x494 SHA/HMAC Output Feedback Data 79 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK80 + * Offset: 0x498 SHA/HMAC Output Feedback Data 80 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK81 + * Offset: 0x49C SHA/HMAC Output Feedback Data 81 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK82 + * Offset: 0x4A0 SHA/HMAC Output Feedback Data 82 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK83 + * Offset: 0x4A4 SHA/HMAC Output Feedback Data 83 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK84 + * Offset: 0x4A8 SHA/HMAC Output Feedback Data 84 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK85 + * Offset: 0x4AC SHA/HMAC Output Feedback Data 85 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK86 + * Offset: 0x4B0 SHA/HMAC Output Feedback Data 86 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FDBCK87 + * Offset: 0x4B4 SHA/HMAC Output Feedback Data 87 After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2 and 2784 bits in size for SHA3. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next blocku2019s operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_SHA512T + * Offset: 0x4F8 SHA/HMAC SHA512/t Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SHA512TEN |SHA512/t Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute SHA512/t function if SHA3EN=0. + * | | |Note: When SHA512TEN=1, SHA/HMAC only execute SHA2-512. + * |[16:8] |TLEN |SHA512/t output digest length + * | | |The TLEN is equal to value t of SHA512/t. It also means the output digest length of SHA512 /t. + * | | |Note: TLEN < 512, and TLEN is not 384 + * @var CRPT_T::HMAC_FBADDR + * Offset: 0x4FC SHA/HMAC DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |SHA/HMAC DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedback address register for automatically reading and writing feedback values via DMA + * | | |The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the SHA/HMAC accelerator can read the feedback data of the last cascade operation from SRAM memory space and write the feedback data of the current cascade operation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRPT_HMAC_FBADDR before triggering START. + * @var CRPT_T::HMAC_SHAKEDGST0 + * Offset: 0x500 SHA/HMAC SHAKE Digest Message 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST1 + * Offset: 0x504 SHA/HMAC SHAKE Digest Message 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST2 + * Offset: 0x508 SHA/HMAC SHAKE Digest Message 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST3 + * Offset: 0x50C SHA/HMAC SHAKE Digest Message 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST4 + * Offset: 0x510 SHA/HMAC SHAKE Digest Message 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST5 + * Offset: 0x514 SHA/HMAC SHAKE Digest Message 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST6 + * Offset: 0x518 SHA/HMAC SHAKE Digest Message 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST7 + * Offset: 0x51C SHA/HMAC SHAKE Digest Message 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST8 + * Offset: 0x520 SHA/HMAC SHAKE Digest Message 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST9 + * Offset: 0x524 SHA/HMAC SHAKE Digest Message 9 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST10 + * Offset: 0x528 SHA/HMAC SHAKE Digest Message 10 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST11 + * Offset: 0x52C SHA/HMAC SHAKE Digest Message 11 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST12 + * Offset: 0x530 SHA/HMAC SHAKE Digest Message 12 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST13 + * Offset: 0x534 SHA/HMAC SHAKE Digest Message 13 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST14 + * Offset: 0x538 SHA/HMAC SHAKE Digest Message 14 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST15 + * Offset: 0x53C SHA/HMAC SHAKE Digest Message 15 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST16 + * Offset: 0x540 SHA/HMAC SHAKE Digest Message 16 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST17 + * Offset: 0x544 SHA/HMAC SHAKE Digest Message 17 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST18 + * Offset: 0x548 SHA/HMAC SHAKE Digest Message 18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST19 + * Offset: 0x54C SHA/HMAC SHAKE Digest Message 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST20 + * Offset: 0x550 SHA/HMAC SHAKE Digest Message 20 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST21 + * Offset: 0x554 SHA/HMAC SHAKE Digest Message 21 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST22 + * Offset: 0x558 SHA/HMAC SHAKE Digest Message 22 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST23 + * Offset: 0x55C SHA/HMAC SHAKE Digest Message 23 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST24 + * Offset: 0x560 SHA/HMAC SHAKE Digest Message 24 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST25 + * Offset: 0x564 SHA/HMAC SHAKE Digest Message 25 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST26 + * Offset: 0x568 SHA/HMAC SHAKE Digest Message 26 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST27 + * Offset: 0x56C SHA/HMAC SHAKE Digest Message 27 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST28 + * Offset: 0x570 SHA/HMAC SHAKE Digest Message 28 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST29 + * Offset: 0x574 SHA/HMAC SHAKE Digest Message 29 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST30 + * Offset: 0x578 SHA/HMAC SHAKE Digest Message 30 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST31 + * Offset: 0x57C SHA/HMAC SHAKE Digest Message 31 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST32 + * Offset: 0x580 SHA/HMAC SHAKE Digest Message 32 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST33 + * Offset: 0x584 SHA/HMAC SHAKE Digest Message 33 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST34 + * Offset: 0x588 SHA/HMAC SHAKE Digest Message 34 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST35 + * Offset: 0x58C SHA/HMAC SHAKE Digest Message 35 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST36 + * Offset: 0x590 SHA/HMAC SHAKE Digest Message 36 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST37 + * Offset: 0x594 SHA/HMAC SHAKE Digest Message 37 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST38 + * Offset: 0x598 SHA/HMAC SHAKE Digest Message 38 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST39 + * Offset: 0x59C SHA/HMAC SHAKE Digest Message 39 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST40 + * Offset: 0x5A0 SHA/HMAC SHAKE Digest Message 40 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::HMAC_SHAKEDGST41 + * Offset: 0x5A4 SHA/HMAC SHAKE Digest Message 41 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMAC SHAKE Digest Message Register + * | | |For SHAKE-128, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 41. + * | | |For SHAKE-256, the digest is stored in CRPT_HMAC_SHAKEDGST0 0 ~ CRPT_HMAC_ SHAKEDGST0 33. + * @var CRPT_T::ECC_CTL + * Offset: 0x800 ECC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |ECC Accelerator Start + * | | |0 = No effect. + * | | |1 = Start ECC accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it is read back. + * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |ECC Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort ECC accelerator and make it into idle state. + * | | |This bit is always 0 when it is read back. + * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. + * |[3] |PFA2C |Prime Field Adder with 2 Cycles + * | | |0 = cost 1 cycle . + * | | |1 = cost 2 cycles. + * |[4] |ECDSAS |Generate S in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating S. + * | | |POINTX1 = ((POINTX2 * POINTY1 + POINTY2 ) / POINTX1) % CURVEN. + * |[5] |ECDSAR |Generate R in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating R. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * |[6] |DFAP |Differential Fault Attack Protection + * | | |0 = Differential fault attack protection Disabled. + * | | |1 = Differential fault attack protection Enabled. + * |[7] |DMAEN |ECC Accelerator DMA Enable Bit + * | | |0 = ECC DMA engine Disabled. + * | | |1 = ECC DMA engine Enabled. + * | | |Only when START and DMAEN are 1, ECC DMA engine will be active. + * |[8] |FSEL |Field Selection + * | | |0 = Binary Field (GF(2m )). + * | | |1 = Prime Field (GF(p)). + * |[10:9] |ECCOP |Point Operation for BF and PF + * | | |00 = Point multiplication:. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * | | |01 = Modulus operation: choose by MODOP (CRPT_ECC_CTL[12:11]). + * | | |10 = Point addition:. + * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. + * | | |(POINTX2, POINTY2) + * | | |11 = Point doubling:. + * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). + * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 + * |[12:11] |MODOP |Modulus Operation for PF + * | | |00 = Division:. + * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. + * | | |01 = Multiplication:. + * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. + * | | |10 = Addition:. + * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. + * | | |11 = Subtraction:. + * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. + * | | |MODOP is active only when ECCOP = 01. + * |[13] |CSEL |Curve Selection + * | | |0 = NIST suggested curve. + * | | |1 = Montgomery curve. + * |[14] |SCAP |Side-channel Attack Protection + * | | |0 = Full speed without side-channel protection. + * | | |1 = Less speed with side-channel protection. + * |[16] |LDP1 |The Control Signal of Register POINTX1 and POINTY1 for the x and Y Coordinate of the First Point + * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. + * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. + * |[17] |LDP2 |The Control Signal of Register POINTX2 and POINTY2 for the x and Y Coordinate of the Second Point + * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. + * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. + * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve + * | | |0 = The register for CURVEA is not modified by DMA or user. + * | | |1 = The register for CURVEA is modified by DMA or user. + * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve + * | | |0 = The register for CURVEB is not modified by DMA or user. + * | | |1 = The register for CURVEB is modified by DMA or user. + * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve + * | | |0 = The register for CURVEN is not modified by DMA or user. + * | | |1 = The register for CURVEN is modified by DMA or user. + * |[21] |LDK |The Control Signal of Register for SCALARK + * | | |0 = The register for SCALARK is not modified by DMA or user. + * | | |1 = The register for SCALARK is modified by DMA or user. + * |[31:22] |CURVEM |The key length of elliptic curve. + * @var CRPT_T::ECC_STS + * Offset: 0x804 ECC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |ECC Accelerator Busy Flag + * | | |0 = The ECC accelerator is idle or finished. + * | | |1 = The ECC accelerator is under processing and protects all registers. + * | | |Note: Remember to clear ECC interrupt flag after ECC accelerator is finished + * |[1] |DMABUSY |ECC DMA Busy Flag + * | | |0 = ECC DMA is idle or finished. + * | | |1 = ECC DMA is busy. + * |[16] |BUSERR |ECC DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and ECC accelerator. + * |[17] |KSERR |ECC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop ECC engine. + * |[18] |DFAERR |ECC Engine Differential Fault Attack Error Flag + * | | |0 = No error. + * | | |1 = Differential Fault Attack happened in ECC engine. The results from ECC engine are wrong. + * @var CRPT_T::ECC_X1_00 + * Offset: 0x808 ECC the X-coordinate Word0 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_01 + * Offset: 0x80C ECC the X-coordinate Word1 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_02 + * Offset: 0x810 ECC the X-coordinate Word2 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_03 + * Offset: 0x814 ECC the X-coordinate Word3 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_04 + * Offset: 0x818 ECC the X-coordinate Word4 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_05 + * Offset: 0x81C ECC the X-coordinate Word5 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_06 + * Offset: 0x820 ECC the X-coordinate Word6 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_07 + * Offset: 0x824 ECC the X-coordinate Word7 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_08 + * Offset: 0x828 ECC the X-coordinate Word8 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_09 + * Offset: 0x82C ECC the X-coordinate Word9 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_10 + * Offset: 0x830 ECC the X-coordinate Word10 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_11 + * Offset: 0x834 ECC the X-coordinate Word11 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_12 + * Offset: 0x838 ECC the X-coordinate Word12 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_13 + * Offset: 0x83C ECC the X-coordinate Word13 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_14 + * Offset: 0x840 ECC the X-coordinate Word14 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_15 + * Offset: 0x844 ECC the X-coordinate Word15 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_16 + * Offset: 0x848 ECC the X-coordinate Word16 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_X1_17 + * Offset: 0x84C ECC the X-coordinate Word17 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_Y1_00 + * Offset: 0x850 ECC the Y-coordinate Word0 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_01 + * Offset: 0x854 ECC the Y-coordinate Word1 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_02 + * Offset: 0x858 ECC the Y-coordinate Word2 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_03 + * Offset: 0x85C ECC the Y-coordinate Word3 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_04 + * Offset: 0x860 ECC the Y-coordinate Word4 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_05 + * Offset: 0x864 ECC the Y-coordinate Word5 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_06 + * Offset: 0x868 ECC the Y-coordinate Word6 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_07 + * Offset: 0x86C ECC the Y-coordinate Word7 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_08 + * Offset: 0x870 ECC the Y-coordinate Word8 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_09 + * Offset: 0x874 ECC the Y-coordinate Word9 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_10 + * Offset: 0x878 ECC the Y-coordinate Word10 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_11 + * Offset: 0x87C ECC the Y-coordinate Word11 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_12 + * Offset: 0x880 ECC the Y-coordinate Word12 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_13 + * Offset: 0x884 ECC the Y-coordinate Word13 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_14 + * Offset: 0x888 ECC the Y-coordinate Word14 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_15 + * Offset: 0x88C ECC the Y-coordinate Word15 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_16 + * Offset: 0x890 ECC the Y-coordinate Word16 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_Y1_17 + * Offset: 0x894 ECC the Y-coordinate Word17 of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_X2_00 + * Offset: 0x898 ECC the X-coordinate Word0 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_01 + * Offset: 0x89C ECC the X-coordinate Word1 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_02 + * Offset: 0x8A0 ECC the X-coordinate Word2 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_03 + * Offset: 0x8A4 ECC the X-coordinate Word3 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_04 + * Offset: 0x8A8 ECC the X-coordinate Word4 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_05 + * Offset: 0x8AC ECC the X-coordinate Word5 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_06 + * Offset: 0x8B0 ECC the X-coordinate Word6 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_07 + * Offset: 0x8B4 ECC the X-coordinate Word7 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_08 + * Offset: 0x8B8 ECC the X-coordinate Word8 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_09 + * Offset: 0x8BC ECC the X-coordinate Word9 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_10 + * Offset: 0x8C0 ECC the X-coordinate Word10 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_11 + * Offset: 0x8C4 ECC the X-coordinate Word11 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_12 + * Offset: 0x8C8 ECC the X-coordinate Word12 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_13 + * Offset: 0x8CC ECC the X-coordinate Word13 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_14 + * Offset: 0x8D0 ECC the X-coordinate Word14 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_15 + * Offset: 0x8D4 ECC the X-coordinate Word15 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_16 + * Offset: 0x8D8 ECC the X-coordinate Word16 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_X2_17 + * Offset: 0x8DC ECC the X-coordinate Word17 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_Y2_00 + * Offset: 0x8E0 ECC the Y-coordinate Word0 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_01 + * Offset: 0x8E4 ECC the Y-coordinate Word1 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_02 + * Offset: 0x8E8 ECC the Y-coordinate Word2 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_03 + * Offset: 0x8EC ECC the Y-coordinate Word3 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_04 + * Offset: 0x8F0 ECC the Y-coordinate Word4 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_05 + * Offset: 0x8F4 ECC the Y-coordinate Word5 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_06 + * Offset: 0x8F8 ECC the Y-coordinate Word6 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_07 + * Offset: 0x8FC ECC the Y-coordinate Word7 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_08 + * Offset: 0x900 ECC the Y-coordinate Word8 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_09 + * Offset: 0x904 ECC the Y-coordinate Word9 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_10 + * Offset: 0x908 ECC the Y-coordinate Word10 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_11 + * Offset: 0x90C ECC the Y-coordinate Word11 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_12 + * Offset: 0x910 ECC the Y-coordinate Word12 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_13 + * Offset: 0x914 ECC the Y-coordinate Word13 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_14 + * Offset: 0x918 ECC the Y-coordinate Word14 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_15 + * Offset: 0x91C ECC the Y-coordinate Word15 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_16 + * Offset: 0x920 ECC the Y-coordinate Word16 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_Y2_17 + * Offset: 0x924 ECC the Y-coordinate Word17 of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_A_00 + * Offset: 0x928 ECC the Parameter CURVEA Word0 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_01 + * Offset: 0x92C ECC the Parameter CURVEA Word1 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_02 + * Offset: 0x930 ECC the Parameter CURVEA Word2 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_03 + * Offset: 0x934 ECC the Parameter CURVEA Word3 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_04 + * Offset: 0x938 ECC the Parameter CURVEA Word4 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_05 + * Offset: 0x93C ECC the Parameter CURVEA Word5 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_06 + * Offset: 0x940 ECC the Parameter CURVEA Word6 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_07 + * Offset: 0x944 ECC the Parameter CURVEA Word7 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_08 + * Offset: 0x948 ECC the Parameter CURVEA Word8 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_09 + * Offset: 0x94C ECC the Parameter CURVEA Word9 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_10 + * Offset: 0x950 ECC the Parameter CURVEA Word10 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_11 + * Offset: 0x954 ECC the Parameter CURVEA Word11 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_12 + * Offset: 0x958 ECC the Parameter CURVEA Word12 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_13 + * Offset: 0x95C ECC the Parameter CURVEA Word13 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_14 + * Offset: 0x960 ECC the Parameter CURVEA Word14 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_15 + * Offset: 0x964 ECC the Parameter CURVEA Word15 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_16 + * Offset: 0x968 ECC the Parameter CURVEA Word16 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_A_17 + * Offset: 0x96C ECC the Parameter CURVEA Word17 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_B_00 + * Offset: 0x970 ECC the Parameter CURVEB Word0 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_01 + * Offset: 0x974 ECC the Parameter CURVEB Word1 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_02 + * Offset: 0x978 ECC the Parameter CURVEB Word2 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_03 + * Offset: 0x97C ECC the Parameter CURVEB Word3 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_04 + * Offset: 0x980 ECC the Parameter CURVEB Word4 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_05 + * Offset: 0x984 ECC the Parameter CURVEB Word5 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_06 + * Offset: 0x988 ECC the Parameter CURVEB Word6 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_07 + * Offset: 0x98C ECC the Parameter CURVEB Word7 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_08 + * Offset: 0x990 ECC the Parameter CURVEB Word8 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_09 + * Offset: 0x994 ECC the Parameter CURVEB Word9 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_10 + * Offset: 0x998 ECC the Parameter CURVEB Word10 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_11 + * Offset: 0x99C ECC the Parameter CURVEB Word11 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_12 + * Offset: 0x9A0 ECC the Parameter CURVEB Word12 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_13 + * Offset: 0x9A4 ECC the Parameter CURVEB Word13 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_14 + * Offset: 0x9A8 ECC the Parameter CURVEB Word14 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_15 + * Offset: 0x9AC ECC the Parameter CURVEB Word15 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_16 + * Offset: 0x9B0 ECC the Parameter CURVEB Word16 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_B_17 + * Offset: 0x9B4 ECC the Parameter CURVEB Word17 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_N_00 + * Offset: 0x9B8 ECC the Parameter CURVEN Word0 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_01 + * Offset: 0x9BC ECC the Parameter CURVEN Word1 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_02 + * Offset: 0x9C0 ECC the Parameter CURVEN Word2 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_03 + * Offset: 0x9C4 ECC the Parameter CURVEN Word3 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_04 + * Offset: 0x9C8 ECC the Parameter CURVEN Word4 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_05 + * Offset: 0x9CC ECC the Parameter CURVEN Word5 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_06 + * Offset: 0x9D0 ECC the Parameter CURVEN Word6 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_07 + * Offset: 0x9D4 ECC the Parameter CURVEN Word7 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_08 + * Offset: 0x9D8 ECC the Parameter CURVEN Word8 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_09 + * Offset: 0x9DC ECC the Parameter CURVEN Word9 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_10 + * Offset: 0x9E0 ECC the Parameter CURVEN Word10 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_11 + * Offset: 0x9E4 ECC the Parameter CURVEN Word11 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_12 + * Offset: 0x9E8 ECC the Parameter CURVEN Word12 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_13 + * Offset: 0x9EC ECC the Parameter CURVEN Word13 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_14 + * Offset: 0x9F0 ECC the Parameter CURVEN Word14 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_15 + * Offset: 0x9F4 ECC the Parameter CURVEN Word15 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_16 + * Offset: 0x9F8 ECC the Parameter CURVEN Word16 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_N_17 + * Offset: 0x9FC ECC the Parameter CURVEN Word17 of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 + * @var CRPT_T::ECC_K_00 + * Offset: 0xA00 ECC the Scalar SCALARK Word0 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_01 + * Offset: 0xA04 ECC the Scalar SCALARK Word1 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_02 + * Offset: 0xA08 ECC the Scalar SCALARK Word2 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_03 + * Offset: 0xA0C ECC the Scalar SCALARK Word3 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_04 + * Offset: 0xA10 ECC the Scalar SCALARK Word4 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_05 + * Offset: 0xA14 ECC the Scalar SCALARK Word5 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_06 + * Offset: 0xA18 ECC the Scalar SCALARK Word6 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_07 + * Offset: 0xA1C ECC the Scalar SCALARK Word7 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_08 + * Offset: 0xA20 ECC the Scalar SCALARK Word8 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_09 + * Offset: 0xA24 ECC the Scalar SCALARK Word9 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_10 + * Offset: 0xA28 ECC the Scalar SCALARK Word10 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_11 + * Offset: 0xA2C ECC the Scalar SCALARK Word11 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_12 + * Offset: 0xA30 ECC the Scalar SCALARK Word12 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_13 + * Offset: 0xA34 ECC the Scalar SCALARK Word13 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_14 + * Offset: 0xA38 ECC the Scalar SCALARK Word14 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_15 + * Offset: 0xA3C ECC the Scalar SCALARK Word15 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_16 + * Offset: 0xA40 ECC the Scalar SCALARK Word16 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_K_17 + * Offset: 0xA44 ECC the Scalar SCALARK Word17 of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 + * @var CRPT_T::ECC_SADDR + * Offset: 0xA48 ECC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * @var CRPT_T::ECC_DADDR + * Offset: 0xA4C ECC DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |ECC DMA Destination Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator + * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored + * | | |Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished + * | | |The start of destination address should be located at word boundary + * | | |That is, bit 1 and 0 of DADDR are ignored + * | | |DADDR can be read and written + * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START + * @var CRPT_T::ECC_STARTREG + * Offset: 0xA50 ECC Starting Address of Updated Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |STARTREG |ECC Starting Address of Updated Registers + * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine + * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTRE.G + * | | |For example, to update input data from register CRPT_ECC POINTX1 + * | | |Thus, the value of STARTREG is 0x808. + * @var CRPT_T::ECC_WORDCNT + * Offset: 0xA54 ECC DMA Word Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WORDCNT |ECC DMA Word Count + * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode + * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words + * | | |CRPT_ECC_WORDCNT can be read and written + * @var CRPT_T::RSA_CTL + * Offset: 0xB00 RSA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |RSA Accelerator Start + * | | |0 = No effect. + * | | |1 = Start RSA accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it is read back. + * | | |RSA accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |RSA Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort RSA accelerator and make it into initial state. + * | | |This bit is always 0 when it is read back. + * | | |Remember to clear RSA interrupt flag after stopping RSA accelerator. + * |[2] |CRT |CRT Enable Control + * | | |0 = CRT Disabled. + * | | |1 = CRT Enabled. + * | | |CRT is only used in decryption with key length 2048, 3072,4096 bits. + * |[3] |CRTBYP |CRT Bypass Enable Control + * | | |0 = CRT Bypass Disabled. + * | | |1 = CRT Bypass Enabled. + * | | |CRT bypass is only used in CRT decryption with the same key. + * | | |Note: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption (means the second time to the latest time), but they cannot set CRTBYP to 1 in non-CRT mode. + * |[5:4] |KEYLENG |The Key Length of RSA Operation + * | | |00 = 1024-bits. + * | | |01 = 2048-bits. + * | | |10 = 3072-bits. + * | | |11 = 4096-bits. + * |[8] |SCAP |Side Channel Attack Protection Enable Control + * | | |0 = Side Channel Attack Protection Disabled. + * | | |1 = Side Channel Attack Protection Enabled. + * @var CRPT_T::RSA_STS + * Offset: 0xB04 RSA Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |RSA Accelerator Busy Flag + * | | |0 = The RSA accelerator is idle or finished. + * | | |1 = The RSA accelerator is under processing and protects all registers. + * | | |Remember to clear RSA interrupt flag after RSA accelerator finished. + * |[1] |DMABUSY |RSA DMA Busy Flag + * | | |0 = RSA DMA is idle or finished. + * | | |1 = RSA DMA is busy. + * |[16] |BUSERR |RSA DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and RSA accelerator. + * |[17] |CTLERR |RSA Control Register Error Flag + * | | |0 = No error. + * | | |1 = RSA control error. RSA will not start in the unsupported situation. + * | | |Note: If users use the error combination of control, even though they donu2019t set START(CRPT_RSA_CTL[0]) to 1, CTLERR still be set to 1. + * |[18] |KSERR |RSA Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop RSA engine. + * @var CRPT_T::RSA_SADDR0 + * Offset: 0xB08 RSA DMA Source Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR0 |RSA DMA Source Address Register0 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Base of Exponentiation (M). + * @var CRPT_T::RSA_SADDR1 + * Offset: 0xB0C RSA DMA Source Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR1 |RSA DMA Source Address Register1 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Base of Modulus Operation (N). + * @var CRPT_T::RSA_SADDR2 + * Offset: 0xB10 RSA DMA Source Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR2 |RSA DMA Source Address Register2 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Exponent of Exponentiation (E). + * @var CRPT_T::RSA_SADDR3 + * Offset: 0xB14 RSA DMA Source Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR3 |RSA DMA Source Address Register3 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Factor of Modulus Operation (p). + * @var CRPT_T::RSA_SADDR4 + * Offset: 0xB18 RSA DMA Source Address Register4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR4 |RSA DMA Source Address Register4 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA the Factor of Modulus Operation (q). + * @var CRPT_T::RSA_DADDR + * Offset: 0xB1C RSA DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |RSA DMA Destination Address Register + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA DMA Destination Address Register (Ans). + * @var CRPT_T::RSA_MADDR0 + * Offset: 0xB20 RSA DMA Middle Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR0 |RSA DMA Middle Address Register0 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Cp -> Mp -> Sp). + * @var CRPT_T::RSA_MADDR1 + * Offset: 0xB24 RSA DMA Middle Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR1 |RSA DMA Middle Address Register1 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Cq -> Mq -> Sq). + * @var CRPT_T::RSA_MADDR2 + * Offset: 0xB28 RSA DMA Middle Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR2 |RSA DMA Middle Address Register2 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Dp). + * @var CRPT_T::RSA_MADDR3 + * Offset: 0xB2C RSA DMA Middle Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR3 |RSA DMA Middle Address Register3 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Dq). + * @var CRPT_T::RSA_MADDR4 + * Offset: 0xB30 RSA DMA Middle Address Register4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR4 |RSA DMA Middle Address Register4 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Rp). + * @var CRPT_T::RSA_MADDR5 + * Offset: 0xB34 RSA DMA Middle Address Register5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR5 |RSA DMA Middle Address Register5 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Rq). + * @var CRPT_T::RSA_MADDR6 + * Offset: 0xB38 RSA DMA Middle Address Register6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR6 |RSA DMA Middle Address Register6 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelerator. + * | | |This register is stored the address of RSA SCA Protection the Temporary Value (Eu2019). + * @var CRPT_T::PRNG_KSCTL + * Offset: 0xF00 PRNG Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Write Key Number + * | | |The key number is sent to key store + * | | |Note: Only for destination Is OTP of key store. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set written key as the non-secure key. + * | | |1 = Set written key as the secure key. + * |[19] |ECDH |ECDH Control Bit + * | | |0 = reserved. + * | | |1 = key is written to key store and used in ECDH. + * | | |Note: When ECDH was set to u20181u2019, 1 + * | | |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) + * | | |Otherwise, KCTLERR will become u20181u2019(CRPT_PRNG_KSSTS[16]) + * | | |2 + * | | |Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n cannot be 0 or 1, otherwise, PRNG will always keep busy. + * |[20] |ECDSA |ECDSA Control Bit + * | | |0 = reserved. + * | | |1 = key is written to key store and used in ECDSA. + * | | |Note: When ECDSA was set to u20181u2019, 1 + * | | |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) + * | | |Otherwise, KCTLERR will become u20181u2019(CRPT_PRNG_KSSTS[16]) + * | | |2 + * | | |Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n cannot be 0 or 1, otherwise, PRNG will always keep busy. + * |[21] |WDST |Write Key Destination + * | | |0 = key is written to registers CRPT_PRNG_KEYx. + * | | |1 = key is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = key is written to the SRAM of key store. + * | | |01 = key is written to the flash of key store. + * | | |10 = key is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = Only for AES used. + * | | |001 = Only for HMAC engine used. + * | | |100 = Only for ECC engine used. + * | | |101 = Only for CPU engine use. + * | | |Others = reserved. + * @var CRPT_T::PRNG_KSSTS + * Offset: 0xF04 PRNG Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store + * |[16] |KCTLERR |PRNG Key Control Register Error Flag + * | | |0 = No error. + * | | |1 = PRNG key control error + * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). + * @var CRPT_T::AES_KSCTL + * Offset: 0xF10 AES Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Source + * | | |0 = key is read from registers CRPT_AESx_KEYx. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Source + * | | |00 = key is read from the SRAM of key store. + * | | |01 = key is read from the flash of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::HMAC_KSCTL + * Offset: 0xF30 HMAC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Source + * | | |0 = key is read from HMAC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Source + * | | |00 = key is read from the SRAM of key store. + * | | |01 = key is read from the flash of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::ECC_KSCTL + * Offset: 0xF40 ECC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMK |Read Key Number K + * | | |The key number of CRPT_ECC_K is sent to key store when RSRCK =1. + * |[5] |RSRCK |Read Key Source for Key Number K + * | | |0 = key is read from ECC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRCK |Read Key Store Source for Key Number K + * | | |00 = key is read from the SRAM of key store. + * | | |01 = key is read from the flash of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[14] |ECDH |ECDH Control Bit + * | | |0 = reserved. + * | | |1 = Set ECC operation is in ECDH + * | | |When this bit and RSRCK are equal to 0x1, ECC will read ECDH private key to CRPT_ECC_K from key store. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set ECDH written key as the non-secure key. + * | | |1 = Set ECDH written key as the secure key. + * |[20] |XY |ECDH Output Select Bit + * | | |0 = The ECDH written key is from X-coordinate Value. + * | | |1 = The ECDH written key is from Y-coordinate Value. + * |[21] |WDST |Write Key Destination + * | | |0 = The ECDH written key is in registers CRPT_ECC_X1 and CRPT_ECC_Y. + * | | |1 = The ECDH written key is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = The ECDH written key is written to the SRAM of key store. + * | | |01 = The ECDH written key is written to the flash of key store. + * | | |10 = The ECDH written key is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = The ECDH written key is only for AES used. + * | | |001 = The ECDH written key is only for HMAC engine used. + * | | |100 = The ECDH written key is only for ECC engine used. + * | | |101 = The ECDH written key is only for CPU engine use. + * | | |Others = reserved. + * @var CRPT_T::ECC_KSSTS + * Offset: 0xF44 ECC Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store after ECDH. + * @var CRPT_T::ECC_KSXY + * Offset: 0xF48 ECC XY Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMX |Read Key Number X + * | | |The key number of CRPT_ECC_X1 is sent to key store when RSRCXY =1. + * |[5] |RSRCXY |Read Key Source for Key Number x and Y + * | | |0 = Key is read from ECC registers. + * | | |1 = Key is read from key store. + * |[7:6] |RSSRCX |Read Key Store Source for Key Number X + * | | |00 = Key is read from the SRAM of key store. + * | | |01 = Key is read from the flash of key store. + * | | |10 = Key is read from the OTP of key store. + * | | |Others = reserved. + * |[12:8] |NUMY |Read Key Number Y + * | | |The key number of CRPT_ECC_Y1 is sent to key store when RSRCXY =1. + * |[15:14] |RSSRCY |Read Key Store Source for Key Number Y + * | | |00 = Key is read from the SRAM of key store. + * | | |01 = Key is read from the flash of key store. + * | | |10 = Key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::RSA_KSCTL + * Offset: 0xF50 RSA Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Source + * | | |0 = Key is read from RSA engine. + * | | |1 = Key is read from key store. + * |[7:6] |RSSRC |Read Key Store Source + * | | |00 = Key is read from the SRAM of key store. + * | | |Others = Reserved. + * |[12:8] |BKNUM |Read Exponent Blind Key Number + * | | |The key number is sent to key store, and its destination always be the SRAM of key store + * | | |CPU cannot read the exponent blind key. + * | | |Note: Use this key number, only when executing SCA protection but no-CRT mode + * | | |When allocate space of key store, key owner selection bits(KS_METADATA[18:16]) should be u2018010u2019. + * @var CRPT_T::RSA_KSSTS0 + * Offset: 0xF54 RSA Key Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM0 |Key Number0 + * | | |The key number is generated by key store, RSA can get complete p by key number in key store while operating. + * | | |Note: The size of this key as half key length. + * |[12:8] |NUM1 |Key Number1 + * | | |The key number is generated by key store, RSA can get complete q by key number in Key Store while operating. + * | | |Note: The size of this key as half key length. + * |[20:16] |NUM2 |Key Number2 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value(Cp) by key number in the key store while operating. + * | | |Note: The size of this key as key length. + * |[28:24] |NUM3 |Key Number3 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value(Cq) by key number in the key store while operating. + * | | |Note: The size of this key as key length. + * @var CRPT_T::RSA_KSSTS1 + * Offset: 0xF58 RSA Key Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM4 |Key Number4 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value(Dp) by key number in key store while operating. + * | | |Note: The size of this key as half key length. + * |[12:8] |NUM5 |Key Number5 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value(Dq) by key number in key store while operating. + * | | |Note: The size of this key as half key length. + * |[20:16] |NUM6 |Key Number6 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value(Rp) by key number in key store while operating. + * | | |Note: The size of this key as key length. + * |[28:24] |NUM7 |Key Number7 + * | | |The key number is generated by key store, RSA can get or store the intermediate temporary value(Rq) by key number in key store while operating. + * | | |Note: The size of this key as key length. + * @var CRPT_T::VERSION + * Offset: 0xFFC Crypto RTL Design Version Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MINOR |RTL Design Minor Version Number + * | | |Minor version number is dependent on moduleu2019s ECO version control. + * | | |0x1000:(Current Minor Version Number) + * |[23:16] |SUB |RTL Design Sub Version Number + * | | |Sub version number is correlated to moduleu2019s key feature. + * | | |0x01:(Current Sub Version Number) + * |[31:24] |MAJOR |RTL Design Major Version Number + * | | |Major version number is correlated to Product Line. + * | | |0x02:(Current Major Version Number) + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY[8]; /*!< [0x0010 - 0x002c] PRNG Generated Key0 */ + __I uint32_t PRNG_STS; /*!< [0x0030] PRNG Status Register */ + __I uint32_t RESERVE0[7]; + __I uint32_t AES_FDBCK[4]; /*!< [0x0050 - 0x005c] AES Engine Output Feedback Data After Cryptographic Operation */ + __I uint32_t RESERVE1[8]; + __IO uint32_t AES_GCM_IVCNT[2]; /*!< [0x0080 - 0x0084] AES GCM IV Byte Count Register 0 */ + __IO uint32_t AES_GCM_ACNT[2]; /*!< [0x0088 - 0x008c] AES GCM A Byte Count Register 0 */ + __IO uint32_t AES_GCM_PCNT[2]; /*!< [0x0090 - 0x0094] AES GCM P Byte Count Register 0 */ + __I uint32_t RESERVE2[2]; + __IO uint32_t AES_FBADDR; /*!< [0x00a0] AES DMA Feedback Address Register */ + __I uint32_t RESERVE3[23]; + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES_KEY[8]; /*!< [0x0110 - 0x012c] AES Key Word 0 Register */ + __IO uint32_t AES_IV[4]; /*!< [0x0130 - 0x013c] AES Initial Vector Word 0 Register */ + __IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */ + __IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */ + __IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */ + __I uint32_t RESERVE4[109]; + __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ + __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ + __I uint32_t HMAC_DGST[16]; /*!< [0x0308 - 0x0344] SHA/HMAC Output Feedback Data 0 */ + __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ + __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ + __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ + __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */ + __IO uint32_t HMAC_FDBCK[88]; /*!< [0x0358 - 0x04b4] SHA/HMAC Output Feedback Data 0 After SHA/HMAC Operation */ + __I uint32_t RESERVE5[16]; + __IO uint32_t HMAC_SHA512T; /*!< [0x04f8] SHA/HMAC SHA512/t Control Register */ + __IO uint32_t HMAC_FBADDR; /*!< [0x04fc] SHA/HMAC DMA Feedback Address Register */ + __I uint32_t HMAC_SHAKEDGST[42]; /*!< [0x0500 - 0x05a4] SHA/HMAC SHAKE Digest Message 0 */ + __I uint32_t RESERVE6[150]; + __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ + __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ + __IO uint32_t ECC_X1[18]; /*!< [0x0808 - 0x084c] ECC the X-coordinate Word0 of the First Point */ + __IO uint32_t ECC_Y1[18]; /*!< [0x0850 - 0x0894] ECC the Y-coordinate Word0 of the First Point */ + __IO uint32_t ECC_X2[18]; /*!< [0x0898 - 0x08dc] ECC the X-coordinate Word0 of the Second Point */ + __IO uint32_t ECC_Y2[18]; /*!< [0x08e0 - 0x0924] ECC the Y-coordinate Word0 of the Second Point */ + __IO uint32_t ECC_A[18]; /*!< [0x0928 - 0x096c] ECC the Parameter CURVEA Word0 of Elliptic Curve */ + __IO uint32_t ECC_B[18]; /*!< [0x0970 - 0x09b4] ECC the Parameter CURVEB Word0 of Elliptic Curve */ + __IO uint32_t ECC_N[18]; /*!< [0x09b8 - 0x09fc] ECC the Parameter CURVEN Word0 of Elliptic Curve */ + __O uint32_t ECC_K[18]; /*!< [0x0a00 - 0x0a44] ECC the Scalar SCALARK Word0 of Point Multiplication */ + __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ + __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ + __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ + __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ + __I uint32_t RESERVE7[42]; + __IO uint32_t RSA_CTL; /*!< [0x0b00] RSA Control Register */ + __I uint32_t RSA_STS; /*!< [0x0b04] RSA Status Register */ + __IO uint32_t RSA_SADDR[5]; /*!< [0x0b08 - 0x0b18] RSA DMA Source Address Register0 */ + __IO uint32_t RSA_DADDR; /*!< [0x0b1c] RSA DMA Destination Address Register */ + __IO uint32_t RSA_MADDR[7]; /*!< [0x0b20 - 0x0b38] RSA DMA Middle Address Register0 */ + __I uint32_t RESERVE8[241]; + __O uint32_t PRNG_KSCTL; /*!< [0x0f00] PRNG Key Control Register */ + __I uint32_t PRNG_KSSTS; /*!< [0x0f04] PRNG Key Status Register */ + __I uint32_t RESERVE9[2]; + __O uint32_t AES_KSCTL; /*!< [0x0f10] AES Key Control Register */ + __I uint32_t RESERVE10[7]; + __O uint32_t HMAC_KSCTL; /*!< [0x0f30] HMAC Key Control Register */ + __I uint32_t RESERVE11[3]; + __O uint32_t ECC_KSCTL; /*!< [0x0f40] ECC Key Control Register */ + __I uint32_t ECC_KSSTS; /*!< [0x0f44] ECC Key Status Register */ + __O uint32_t ECC_KSXY; /*!< [0x0f48] ECC XY Number Register */ + __I uint32_t RESERVE12[1]; + __O uint32_t RSA_KSCTL; /*!< [0x0f50] RSA Key Control Register */ + __IO uint32_t RSA_KSSTS[2]; /*!< [0x0f54 - 0x0f58] RSA Key Status Register 0 */ + __I uint32_t RESERVE13[40]; + __I uint32_t VERSION; /*!< [0x0ffc] Crypto RTL Design Version Register */ + +} CRPT_T; + +/** + @addtogroup CRPT_CONST CRPT Bit Field Definition + Constant Definitions for CRPT Controller +@{ */ + +#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ +#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ + +#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ +#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ + +#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ +#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ + +#define CRPT_INTEN_PRNGEIEN_Pos (17) /*!< CRPT_T::INTEN: PRNGEIEN Position */ +#define CRPT_INTEN_PRNGEIEN_Msk (0x1ul << CRPT_INTEN_PRNGEIEN_Pos) /*!< CRPT_T::INTEN: PRNGEIEN Mask */ + +#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ +#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ + +#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ +#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ + +#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ +#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ + +#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ +#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ + +#define CRPT_INTEN_RSAIEN_Pos (30) /*!< CRPT_T::INTEN: RSAIEN Position */ +#define CRPT_INTEN_RSAIEN_Msk (0x1ul << CRPT_INTEN_RSAIEN_Pos) /*!< CRPT_T::INTEN: RSAIEN Mask */ + +#define CRPT_INTEN_RSAEIEN_Pos (31) /*!< CRPT_T::INTEN: RSAEIEN Position */ +#define CRPT_INTEN_RSAEIEN_Msk (0x1ul << CRPT_INTEN_RSAEIEN_Pos) /*!< CRPT_T::INTEN: RSAEIEN Mask */ + +#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ +#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ + +#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ +#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ + +#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ +#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ + +#define CRPT_INTSTS_PRNGEIF_Pos (17) /*!< CRPT_T::INTSTS: PRNGEIF Position */ +#define CRPT_INTSTS_PRNGEIF_Msk (0x1ul << CRPT_INTSTS_PRNGEIF_Pos) /*!< CRPT_T::INTSTS: PRNGEIF Mask */ + +#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ +#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ + +#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ +#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ + +#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ +#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ + +#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ +#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ + +#define CRPT_INTSTS_RSAIF_Pos (30) /*!< CRPT_T::INTSTS: RSAIF Position */ +#define CRPT_INTSTS_RSAIF_Msk (0x1ul << CRPT_INTSTS_RSAIF_Pos) /*!< CRPT_T::INTSTS: RSAIF Mask */ + +#define CRPT_INTSTS_RSAEIF_Pos (31) /*!< CRPT_T::INTSTS: RSAEIF Position */ +#define CRPT_INTSTS_RSAEIF_Msk (0x1ul << CRPT_INTSTS_RSAEIF_Pos) /*!< CRPT_T::INTSTS: RSAEIF Mask */ + +#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ +#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ + +#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ +#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ +#define CRPT_PRNG_CTL_KEYSZ_Msk (0xful << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ + +#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ +#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ + +#define CRPT_PRNG_CTL_SEEDSRC_Pos (16) /*!< CRPT_T::PRNG_CTL: SEEDSRC Position */ +#define CRPT_PRNG_CTL_SEEDSRC_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSRC_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSRC Mask */ + +#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ +#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ + +#define CRPT_PRNG_KEY0_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY0: KEY Position */ +#define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /*!< CRPT_T::PRNG_KEY0: KEY Mask */ + +#define CRPT_PRNG_KEY1_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY1: KEY Position */ +#define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /*!< CRPT_T::PRNG_KEY1: KEY Mask */ + +#define CRPT_PRNG_KEY2_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY2: KEY Position */ +#define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /*!< CRPT_T::PRNG_KEY2: KEY Mask */ + +#define CRPT_PRNG_KEY3_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY3: KEY Position */ +#define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /*!< CRPT_T::PRNG_KEY3: KEY Mask */ + +#define CRPT_PRNG_KEY4_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY4: KEY Position */ +#define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /*!< CRPT_T::PRNG_KEY4: KEY Mask */ + +#define CRPT_PRNG_KEY5_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY5: KEY Position */ +#define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /*!< CRPT_T::PRNG_KEY5: KEY Mask */ + +#define CRPT_PRNG_KEY6_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY6: KEY Position */ +#define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /*!< CRPT_T::PRNG_KEY6: KEY Mask */ + +#define CRPT_PRNG_KEY7_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY7: KEY Position */ +#define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /*!< CRPT_T::PRNG_KEY7: KEY Mask */ + +#define CRPT_PRNG_STS_BUSY_Pos (0) /*!< CRPT_T::PRNG_STS: BUSY Position */ +#define CRPT_PRNG_STS_BUSY_Msk (0x1ul << CRPT_PRNG_STS_BUSY_Pos) /*!< CRPT_T::PRNG_STS: BUSY Mask */ + +#define CRPT_PRNG_STS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_STS: KCTLERR Position */ +#define CRPT_PRNG_STS_KCTLERR_Msk (0x1ul << CRPT_PRNG_STS_KCTLERR_Pos) /*!< CRPT_T::PRNG_STS: KCTLERR Mask */ + +#define CRPT_PRNG_STS_KSERR_Pos (17) /*!< CRPT_T::PRNG_STS: KSERR Position */ +#define CRPT_PRNG_STS_KSERR_Msk (0x1ul << CRPT_PRNG_STS_KSERR_Pos) /*!< CRPT_T::PRNG_STS: KSERR Mask */ + +#define CRPT_AES_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK0: FDBCK Position */ +#define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK0: FDBCK Mask */ + +#define CRPT_AES_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK1: FDBCK Position */ +#define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK1: FDBCK Mask */ + +#define CRPT_AES_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK2: FDBCK Position */ +#define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK2: FDBCK Mask */ + +#define CRPT_AES_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK3: FDBCK Position */ +#define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK3: FDBCK Mask */ + +#define CRPT_AES_GCM_IVCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Position */ +#define CRPT_AES_GCM_IVCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_IVCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Mask */ + +#define CRPT_AES_GCM_IVCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Position */ +#define CRPT_AES_GCM_IVCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_IVCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Mask */ + +#define CRPT_AES_GCM_ACNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT0: CNT Position */ +#define CRPT_AES_GCM_ACNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_ACNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT0: CNT Mask */ + +#define CRPT_AES_GCM_ACNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT1: CNT Position */ +#define CRPT_AES_GCM_ACNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_ACNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT1: CNT Mask */ + +#define CRPT_AES_GCM_PCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT0: CNT Position */ +#define CRPT_AES_GCM_PCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_PCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT0: CNT Mask */ + +#define CRPT_AES_GCM_PCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT1: CNT Position */ +#define CRPT_AES_GCM_PCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_PCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT1: CNT Mask */ + +#define CRPT_AES_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::AES_FBADDR: FBADDR Position */ +#define CRPT_AES_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_AES_FBADDR_FBADDR_Pos) /*!< CRPT_T::AES_FBADDR: FBADDR Mask */ + +#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ +#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ + +#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ +#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ + +#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ +#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ + +#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ +#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ + +#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ +#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ + +#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ +#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ + +#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ +#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ + +#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */ +#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */ + +#define CRPT_AES_CTL_FBIN_Pos (20) /*!< CRPT_T::AES_CTL: FBIN Position */ +#define CRPT_AES_CTL_FBIN_Msk (0x1ul << CRPT_AES_CTL_FBIN_Pos) /*!< CRPT_T::AES_CTL: FBIN Mask */ + +#define CRPT_AES_CTL_FBOUT_Pos (21) /*!< CRPT_T::AES_CTL: FBOUT Position */ +#define CRPT_AES_CTL_FBOUT_Msk (0x1ul << CRPT_AES_CTL_FBOUT_Pos) /*!< CRPT_T::AES_CTL: FBOUT Mask */ + +#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ +#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ + +#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ +#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ + +#define CRPT_AES_CTL_KOUTSWAP_Pos (24) /*!< CRPT_T::AES_CTL: KOUTSWAP Position */ +#define CRPT_AES_CTL_KOUTSWAP_Msk (0x1ul << CRPT_AES_CTL_KOUTSWAP_Pos) /*!< CRPT_T::AES_CTL: KOUTSWAP Mask */ + +#define CRPT_AES_CTL_KINSWAP_Pos (25) /*!< CRPT_T::AES_CTL: KINSWAP Position */ +#define CRPT_AES_CTL_KINSWAP_Msk (0x1ul << CRPT_AES_CTL_KINSWAP_Pos) /*!< CRPT_T::AES_CTL: KINSWAP Mask */ + +#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ +#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ + +#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ +#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ + +#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ +#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ + +#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ +#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ + +#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ +#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ + +#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ +#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ + +#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ +#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ + +#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */ +#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ +#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ + +#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ +#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ + +#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ +#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ + +#define CRPT_AES_STS_KSERR_Pos (21) /*!< CRPT_T::AES_STS: KSERR Position */ +#define CRPT_AES_STS_KSERR_Msk (0x1ul << CRPT_AES_STS_KSERR_Pos) /*!< CRPT_T::AES_STS: KSERR Mask */ + +#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ +#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ + +#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ +#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ + +#define CRPT_AES_KEY0_KEY_Pos (0) /*!< CRPT_T::AES_KEY0: KEY Position */ +#define CRPT_AES_KEY0_KEY_Msk (0xfffffffful << CRPT_AES_KEY0_KEY_Pos) /*!< CRPT_T::AES_KEY0: KEY Mask */ + +#define CRPT_AES_KEY1_KEY_Pos (0) /*!< CRPT_T::AES_KEY1: KEY Position */ +#define CRPT_AES_KEY1_KEY_Msk (0xfffffffful << CRPT_AES_KEY1_KEY_Pos) /*!< CRPT_T::AES_KEY1: KEY Mask */ + +#define CRPT_AES_KEY2_KEY_Pos (0) /*!< CRPT_T::AES_KEY2: KEY Position */ +#define CRPT_AES_KEY2_KEY_Msk (0xfffffffful << CRPT_AES_KEY2_KEY_Pos) /*!< CRPT_T::AES_KEY2: KEY Mask */ + +#define CRPT_AES_KEY3_KEY_Pos (0) /*!< CRPT_T::AES_KEY3: KEY Position */ +#define CRPT_AES_KEY3_KEY_Msk (0xfffffffful << CRPT_AES_KEY3_KEY_Pos) /*!< CRPT_T::AES_KEY3: KEY Mask */ + +#define CRPT_AES_KEY4_KEY_Pos (0) /*!< CRPT_T::AES_KEY4: KEY Position */ +#define CRPT_AES_KEY4_KEY_Msk (0xfffffffful << CRPT_AES_KEY4_KEY_Pos) /*!< CRPT_T::AES_KEY4: KEY Mask */ + +#define CRPT_AES_KEY5_KEY_Pos (0) /*!< CRPT_T::AES_KEY5: KEY Position */ +#define CRPT_AES_KEY5_KEY_Msk (0xfffffffful << CRPT_AES_KEY5_KEY_Pos) /*!< CRPT_T::AES_KEY5: KEY Mask */ + +#define CRPT_AES_KEY6_KEY_Pos (0) /*!< CRPT_T::AES_KEY6: KEY Position */ +#define CRPT_AES_KEY6_KEY_Msk (0xfffffffful << CRPT_AES_KEY6_KEY_Pos) /*!< CRPT_T::AES_KEY6: KEY Mask */ + +#define CRPT_AES_KEY7_KEY_Pos (0) /*!< CRPT_T::AES_KEY7: KEY Position */ +#define CRPT_AES_KEY7_KEY_Msk (0xfffffffful << CRPT_AES_KEY7_KEY_Pos) /*!< CRPT_T::AES_KEY7: KEY Mask */ + +#define CRPT_AES_IV0_IV_Pos (0) /*!< CRPT_T::AES_IV0: IV Position */ +#define CRPT_AES_IV0_IV_Msk (0xfffffffful << CRPT_AES_IV0_IV_Pos) /*!< CRPT_T::AES_IV0: IV Mask */ + +#define CRPT_AES_IV1_IV_Pos (0) /*!< CRPT_T::AES_IV1: IV Position */ +#define CRPT_AES_IV1_IV_Msk (0xfffffffful << CRPT_AES_IV1_IV_Pos) /*!< CRPT_T::AES_IV1: IV Mask */ + +#define CRPT_AES_IV2_IV_Pos (0) /*!< CRPT_T::AES_IV2: IV Position */ +#define CRPT_AES_IV2_IV_Msk (0xfffffffful << CRPT_AES_IV2_IV_Pos) /*!< CRPT_T::AES_IV2: IV Mask */ + +#define CRPT_AES_IV3_IV_Pos (0) /*!< CRPT_T::AES_IV3: IV Position */ +#define CRPT_AES_IV3_IV_Msk (0xfffffffful << CRPT_AES_IV3_IV_Pos) /*!< CRPT_T::AES_IV3: IV Mask */ + +#define CRPT_AES_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES_SADDR: SADDR Position */ +#define CRPT_AES_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos) /*!< CRPT_T::AES_SADDR: SADDR Mask */ + +#define CRPT_AES_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES_DADDR: DADDR Position */ +#define CRPT_AES_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos) /*!< CRPT_T::AES_DADDR: DADDR Mask */ + +#define CRPT_AES_CNT_CNT_Pos (0) /*!< CRPT_T::AES_CNT: CNT Position */ +#define CRPT_AES_CNT_CNT_Msk (0xfffffffful << CRPT_AES_CNT_CNT_Pos) /*!< CRPT_T::AES_CNT: CNT Mask */ + +#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ +#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ + +#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ +#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ + +#define CRPT_HMAC_CTL_DMAFIRST_Pos (4) /*!< CRPT_T::HMAC_CTL: DMAFIRST Position */ +#define CRPT_HMAC_CTL_DMAFIRST_Msk (0x1ul << CRPT_HMAC_CTL_DMAFIRST_Pos) /*!< CRPT_T::HMAC_CTL: DMAFIRST Mask */ + +#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ +#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ + +#define CRPT_HMAC_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::HMAC_CTL: DMACSCAD Position */ +#define CRPT_HMAC_CTL_DMACSCAD_Msk (0x1ul << CRPT_HMAC_CTL_DMACSCAD_Pos) /*!< CRPT_T::HMAC_CTL: DMACSCAD Mask */ + +#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ +#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ + +#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ +#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ + +#define CRPT_HMAC_CTL_HMACEN_Pos (11) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ +#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ + +#define CRPT_HMAC_CTL_SHA3EN_Pos (12) /*!< CRPT_T::HMAC_CTL: SHA3EN Position */ +#define CRPT_HMAC_CTL_SHA3EN_Msk (0x1ul << CRPT_HMAC_CTL_SHA3EN_Pos) /*!< CRPT_T::HMAC_CTL: SHA3EN Mask */ + +#define CRPT_HMAC_CTL_FBIN_Pos (20) /*!< CRPT_T::HMAC_CTL: FBIN Position */ +#define CRPT_HMAC_CTL_FBIN_Msk (0x1ul << CRPT_HMAC_CTL_FBIN_Pos) /*!< CRPT_T::HMAC_CTL: FBIN Mask */ + +#define CRPT_HMAC_CTL_FBOUT_Pos (21) /*!< CRPT_T::HMAC_CTL: FBOUT Position */ +#define CRPT_HMAC_CTL_FBOUT_Msk (0x1ul << CRPT_HMAC_CTL_FBOUT_Pos) /*!< CRPT_T::HMAC_CTL: FBOUT Mask */ + +#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ +#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ + +#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ +#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ + +#define CRPT_HMAC_CTL_NEXTDGST_Pos (24) /*!< CRPT_T::HMAC_CTL: NEXTDGST Position */ +#define CRPT_HMAC_CTL_NEXTDGST_Msk (0x1ul << CRPT_HMAC_CTL_NEXTDGST_Pos) /*!< CRPT_T::HMAC_CTL: NEXTDGST Mask */ + +#define CRPT_HMAC_CTL_FINISHDGST_Pos (25) /*!< CRPT_T::HMAC_CTL: FINISHDGST Position */ +#define CRPT_HMAC_CTL_FINISHDGST_Msk (0x1ul << CRPT_HMAC_CTL_FINISHDGST_Pos) /*!< CRPT_T::HMAC_CTL: FINISHDGST Mask */ + +#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ +#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ + +#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ +#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ + +#define CRPT_HMAC_STS_SHAKEBUSY_Pos (2) /*!< CRPT_T::HMAC_STS: SHAKEBUSY Position */ +#define CRPT_HMAC_STS_SHAKEBUSY_Msk (0x1ul << CRPT_HMAC_STS_SHAKEBUSY_Pos) /*!< CRPT_T::HMAC_STS: SHAKEBUSY Mask */ + +#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ +#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ + +#define CRPT_HMAC_STS_KSERR_Pos (9) /*!< CRPT_T::HMAC_STS: KSERR Position */ +#define CRPT_HMAC_STS_KSERR_Msk (0x1ul << CRPT_HMAC_STS_KSERR_Pos) /*!< CRPT_T::HMAC_STS: KSERR Mask */ + +#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ +#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ + +#define CRPT_HMAC_DGST0_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST0: DGST Position */ +#define CRPT_HMAC_DGST0_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST0_DGST_Pos) /*!< CRPT_T::HMAC_DGST0: DGST Mask */ + +#define CRPT_HMAC_DGST1_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST1: DGST Position */ +#define CRPT_HMAC_DGST1_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST1_DGST_Pos) /*!< CRPT_T::HMAC_DGST1: DGST Mask */ + +#define CRPT_HMAC_DGST2_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST2: DGST Position */ +#define CRPT_HMAC_DGST2_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST2_DGST_Pos) /*!< CRPT_T::HMAC_DGST2: DGST Mask */ + +#define CRPT_HMAC_DGST3_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST3: DGST Position */ +#define CRPT_HMAC_DGST3_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST3_DGST_Pos) /*!< CRPT_T::HMAC_DGST3: DGST Mask */ + +#define CRPT_HMAC_DGST4_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST4: DGST Position */ +#define CRPT_HMAC_DGST4_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST4_DGST_Pos) /*!< CRPT_T::HMAC_DGST4: DGST Mask */ + +#define CRPT_HMAC_DGST5_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST5: DGST Position */ +#define CRPT_HMAC_DGST5_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST5_DGST_Pos) /*!< CRPT_T::HMAC_DGST5: DGST Mask */ + +#define CRPT_HMAC_DGST6_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST6: DGST Position */ +#define CRPT_HMAC_DGST6_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST6_DGST_Pos) /*!< CRPT_T::HMAC_DGST6: DGST Mask */ + +#define CRPT_HMAC_DGST7_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST7: DGST Position */ +#define CRPT_HMAC_DGST7_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST7_DGST_Pos) /*!< CRPT_T::HMAC_DGST7: DGST Mask */ + +#define CRPT_HMAC_DGST8_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST8: DGST Position */ +#define CRPT_HMAC_DGST8_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST8_DGST_Pos) /*!< CRPT_T::HMAC_DGST8: DGST Mask */ + +#define CRPT_HMAC_DGST9_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST9: DGST Position */ +#define CRPT_HMAC_DGST9_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST9_DGST_Pos) /*!< CRPT_T::HMAC_DGST9: DGST Mask */ + +#define CRPT_HMAC_DGST10_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST10: DGST Position */ +#define CRPT_HMAC_DGST10_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST10_DGST_Pos) /*!< CRPT_T::HMAC_DGST10: DGST Mask */ + +#define CRPT_HMAC_DGST11_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST11: DGST Position */ +#define CRPT_HMAC_DGST11_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST11_DGST_Pos) /*!< CRPT_T::HMAC_DGST11: DGST Mask */ + +#define CRPT_HMAC_DGST12_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST12: DGST Position */ +#define CRPT_HMAC_DGST12_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST12_DGST_Pos) /*!< CRPT_T::HMAC_DGST12: DGST Mask */ + +#define CRPT_HMAC_DGST13_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST13: DGST Position */ +#define CRPT_HMAC_DGST13_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST13_DGST_Pos) /*!< CRPT_T::HMAC_DGST13: DGST Mask */ + +#define CRPT_HMAC_DGST14_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST14: DGST Position */ +#define CRPT_HMAC_DGST14_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST14_DGST_Pos) /*!< CRPT_T::HMAC_DGST14: DGST Mask */ + +#define CRPT_HMAC_DGST15_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST15: DGST Position */ +#define CRPT_HMAC_DGST15_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST15_DGST_Pos) /*!< CRPT_T::HMAC_DGST15: DGST Mask */ + +#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ +#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ + +#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ +#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ + +#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ +#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ + +#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ +#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ + +#define CRPT_HMAC_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Position */ +#define CRPT_HMAC_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK0_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Position */ +#define CRPT_HMAC_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK1_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Position */ +#define CRPT_HMAC_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK2_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Position */ +#define CRPT_HMAC_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK3_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK4_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Position */ +#define CRPT_HMAC_FDBCK4_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK4_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK5_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Position */ +#define CRPT_HMAC_FDBCK5_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK5_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK6_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Position */ +#define CRPT_HMAC_FDBCK6_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK6_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK7_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Position */ +#define CRPT_HMAC_FDBCK7_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK7_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK8_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Position */ +#define CRPT_HMAC_FDBCK8_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK8_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK9_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Position */ +#define CRPT_HMAC_FDBCK9_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK9_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK10_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Position */ +#define CRPT_HMAC_FDBCK10_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK10_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK11_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Position */ +#define CRPT_HMAC_FDBCK11_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK11_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK12_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Position */ +#define CRPT_HMAC_FDBCK12_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK12_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK13_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Position */ +#define CRPT_HMAC_FDBCK13_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK13_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK14_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Position */ +#define CRPT_HMAC_FDBCK14_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK14_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK15_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Position */ +#define CRPT_HMAC_FDBCK15_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK15_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK16_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Position */ +#define CRPT_HMAC_FDBCK16_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK16_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK17_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Position */ +#define CRPT_HMAC_FDBCK17_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK17_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK18_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Position */ +#define CRPT_HMAC_FDBCK18_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK18_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK19_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Position */ +#define CRPT_HMAC_FDBCK19_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK19_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK20_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Position */ +#define CRPT_HMAC_FDBCK20_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK20_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK21_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Position */ +#define CRPT_HMAC_FDBCK21_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK21_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK22_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Position */ +#define CRPT_HMAC_FDBCK22_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK22_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK23_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Position */ +#define CRPT_HMAC_FDBCK23_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK23_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK24_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Position */ +#define CRPT_HMAC_FDBCK24_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK24_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK25_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Position */ +#define CRPT_HMAC_FDBCK25_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK25_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK26_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Position */ +#define CRPT_HMAC_FDBCK26_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK26_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK27_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Position */ +#define CRPT_HMAC_FDBCK27_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK27_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK28_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Position */ +#define CRPT_HMAC_FDBCK28_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK28_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK29_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Position */ +#define CRPT_HMAC_FDBCK29_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK29_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK30_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Position */ +#define CRPT_HMAC_FDBCK30_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK30_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK31_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Position */ +#define CRPT_HMAC_FDBCK31_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK31_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK32_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Position */ +#define CRPT_HMAC_FDBCK32_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK32_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK33_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Position */ +#define CRPT_HMAC_FDBCK33_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK33_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK34_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Position */ +#define CRPT_HMAC_FDBCK34_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK34_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK35_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Position */ +#define CRPT_HMAC_FDBCK35_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK35_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK36_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Position */ +#define CRPT_HMAC_FDBCK36_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK36_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK37_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Position */ +#define CRPT_HMAC_FDBCK37_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK37_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK38_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Position */ +#define CRPT_HMAC_FDBCK38_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK38_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK39_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Position */ +#define CRPT_HMAC_FDBCK39_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK39_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK40_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Position */ +#define CRPT_HMAC_FDBCK40_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK40_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK41_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Position */ +#define CRPT_HMAC_FDBCK41_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK41_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK42_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Position */ +#define CRPT_HMAC_FDBCK42_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK42_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK43_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Position */ +#define CRPT_HMAC_FDBCK43_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK43_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK44_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Position */ +#define CRPT_HMAC_FDBCK44_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK44_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK45_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Position */ +#define CRPT_HMAC_FDBCK45_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK45_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK46_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Position */ +#define CRPT_HMAC_FDBCK46_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK46_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK47_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Position */ +#define CRPT_HMAC_FDBCK47_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK47_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK48_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Position */ +#define CRPT_HMAC_FDBCK48_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK48_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK49_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Position */ +#define CRPT_HMAC_FDBCK49_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK49_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK50_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Position */ +#define CRPT_HMAC_FDBCK50_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK50_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK51_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Position */ +#define CRPT_HMAC_FDBCK51_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK51_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK52_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Position */ +#define CRPT_HMAC_FDBCK52_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK52_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK53_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Position */ +#define CRPT_HMAC_FDBCK53_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK53_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK54_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK54: FDBCK Position */ +#define CRPT_HMAC_FDBCK54_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK54_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK54: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK55_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK55: FDBCK Position */ +#define CRPT_HMAC_FDBCK55_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK55_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK55: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK56_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK56: FDBCK Position */ +#define CRPT_HMAC_FDBCK56_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK56_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK56: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK57_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK57: FDBCK Position */ +#define CRPT_HMAC_FDBCK57_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK57_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK57: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK58_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK58: FDBCK Position */ +#define CRPT_HMAC_FDBCK58_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK58_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK58: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK59_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK59: FDBCK Position */ +#define CRPT_HMAC_FDBCK59_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK59_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK59: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK60_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK60: FDBCK Position */ +#define CRPT_HMAC_FDBCK60_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK60_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK60: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK61_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK61: FDBCK Position */ +#define CRPT_HMAC_FDBCK61_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK61_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK61: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK62_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK62: FDBCK Position */ +#define CRPT_HMAC_FDBCK62_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK62_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK62: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK63_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK63: FDBCK Position */ +#define CRPT_HMAC_FDBCK63_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK63_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK63: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK64_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK64: FDBCK Position */ +#define CRPT_HMAC_FDBCK64_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK64_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK64: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK65_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK65: FDBCK Position */ +#define CRPT_HMAC_FDBCK65_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK65_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK65: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK66_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK66: FDBCK Position */ +#define CRPT_HMAC_FDBCK66_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK66_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK66: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK67_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK67: FDBCK Position */ +#define CRPT_HMAC_FDBCK67_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK67_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK67: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK68_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK68: FDBCK Position */ +#define CRPT_HMAC_FDBCK68_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK68_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK68: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK69_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK69: FDBCK Position */ +#define CRPT_HMAC_FDBCK69_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK69_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK69: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK70_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK70: FDBCK Position */ +#define CRPT_HMAC_FDBCK70_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK70_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK70: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK71_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK71: FDBCK Position */ +#define CRPT_HMAC_FDBCK71_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK71_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK71: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK72_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK72: FDBCK Position */ +#define CRPT_HMAC_FDBCK72_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK72_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK72: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK73_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK73: FDBCK Position */ +#define CRPT_HMAC_FDBCK73_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK73_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK73: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK74_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK74: FDBCK Position */ +#define CRPT_HMAC_FDBCK74_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK74_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK74: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK75_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK75: FDBCK Position */ +#define CRPT_HMAC_FDBCK75_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK75_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK75: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK76_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK76: FDBCK Position */ +#define CRPT_HMAC_FDBCK76_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK76_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK76: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK77_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK77: FDBCK Position */ +#define CRPT_HMAC_FDBCK77_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK77_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK77: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK78_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK78: FDBCK Position */ +#define CRPT_HMAC_FDBCK78_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK78_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK78: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK79_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK79: FDBCK Position */ +#define CRPT_HMAC_FDBCK79_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK79_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK79: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK80_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK80: FDBCK Position */ +#define CRPT_HMAC_FDBCK80_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK80_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK80: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK81_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK81: FDBCK Position */ +#define CRPT_HMAC_FDBCK81_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK81_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK81: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK82_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK82: FDBCK Position */ +#define CRPT_HMAC_FDBCK82_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK82_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK82: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK83_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK83: FDBCK Position */ +#define CRPT_HMAC_FDBCK83_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK83_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK83: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK84_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK84: FDBCK Position */ +#define CRPT_HMAC_FDBCK84_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK84_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK84: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK85_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK85: FDBCK Position */ +#define CRPT_HMAC_FDBCK85_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK85_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK85: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK86_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK86: FDBCK Position */ +#define CRPT_HMAC_FDBCK86_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK86_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK86: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK87_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK87: FDBCK Position */ +#define CRPT_HMAC_FDBCK87_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK87_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK87: FDBCK Mask */ + +#define CRPT_HMAC_SHA512T_SHA512TEN_Pos (0) /*!< CRPT_T::HMAC_SHA512T: SHA512TEN Position*/ +#define CRPT_HMAC_SHA512T_SHA512TEN_Msk (0x1ul << CRPT_HMAC_SHA512T_SHA512TEN_Pos) /*!< CRPT_T::HMAC_SHA512T: SHA512TEN Mask */ + +#define CRPT_HMAC_SHA512T_TLEN_Pos (8) /*!< CRPT_T::HMAC_SHA512T: TLEN Position */ +#define CRPT_HMAC_SHA512T_TLEN_Msk (0x1fful << CRPT_HMAC_SHA512T_TLEN_Pos) /*!< CRPT_T::HMAC_SHA512T: TLEN Mask */ + +#define CRPT_HMAC_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::HMAC_FBADDR: FBADDR Position */ +#define CRPT_HMAC_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_HMAC_FBADDR_FBADDR_Pos) /*!< CRPT_T::HMAC_FBADDR: FBADDR Mask */ + +#define CRPT_HMAC_SHAKEDGST0_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST0: DGST Position */ +#define CRPT_HMAC_SHAKEDGST0_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST0_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST0: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST1_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST1: DGST Position */ +#define CRPT_HMAC_SHAKEDGST1_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST1_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST1: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST2_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST2: DGST Position */ +#define CRPT_HMAC_SHAKEDGST2_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST2_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST2: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST3_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST3: DGST Position */ +#define CRPT_HMAC_SHAKEDGST3_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST3_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST3: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST4_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST4: DGST Position */ +#define CRPT_HMAC_SHAKEDGST4_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST4_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST4: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST5_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST5: DGST Position */ +#define CRPT_HMAC_SHAKEDGST5_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST5_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST5: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST6_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST6: DGST Position */ +#define CRPT_HMAC_SHAKEDGST6_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST6_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST6: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST7_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST7: DGST Position */ +#define CRPT_HMAC_SHAKEDGST7_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST7_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST7: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST8_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST8: DGST Position */ +#define CRPT_HMAC_SHAKEDGST8_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST8_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST8: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST9_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST9: DGST Position */ +#define CRPT_HMAC_SHAKEDGST9_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST9_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST9: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST10_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST10: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST10_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST10_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST10: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST11_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST11: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST11_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST11_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST11: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST12_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST12: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST12_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST12_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST12: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST13_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST13: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST13_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST13_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST13: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST14_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST14: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST14_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST14_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST14: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST15_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST15: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST15_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST15_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST15: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST16_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST16: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST16_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST16_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST16: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST17_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST17: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST17_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST17_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST17: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST18_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST18: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST18_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST18_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST18: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST19_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST19: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST19_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST19_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST19: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST20_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST20: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST20_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST20_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST20: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST21_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST21: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST21_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST21_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST21: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST22_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST22: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST22_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST22_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST22: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST23_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST23: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST23_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST23_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST23: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST24_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST24: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST24_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST24_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST24: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST25_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST25: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST25_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST25_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST25: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST26_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST26: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST26_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST26_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST26: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST27_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST27: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST27_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST27_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST27: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST28_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST28: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST28_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST28_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST28: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST29_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST29: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST29_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST29_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST29: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST30_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST30: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST30_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST30_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST30: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST31_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST31: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST31_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST31_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST31: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST32_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST32: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST32_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST32_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST32: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST33_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST33: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST33_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST33_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST33: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST34_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST34: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST34_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST34_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST34: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST35_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST35: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST35_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST35_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST35: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST36_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST36: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST36_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST36_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST36: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST37_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST37: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST37_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST37_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST37: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST38_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST38: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST38_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST38_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST38: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST39_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST39: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST39_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST39_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST39: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST40_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST40: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST40_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST40_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST40: DGST Mask */ + +#define CRPT_HMAC_SHAKEDGST41_DGST_Pos (0) /*!< CRPT_T::HMAC_SHAKEDGST41: DGST Position*/ +#define CRPT_HMAC_SHAKEDGST41_DGST_Msk (0xfffffffful << CRPT_HMAC_SHAKEDGST41_DGST_Pos) /*!< CRPT_T::HMAC_SHAKEDGST41: DGST Mask */ + +#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ +#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ + +#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ +#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ + +#define CRPT_ECC_CTL_PFA2C_Pos (3) /*!< CRPT_T::ECC_CTL: PFA2C Position */ +#define CRPT_ECC_CTL_PFA2C_Msk (0x1ul << CRPT_ECC_CTL_PFA2C_Pos) /*!< CRPT_T::ECC_CTL: PFA2C Mask */ + +#define CRPT_ECC_CTL_ECDSAS_Pos (4) /*!< CRPT_T::ECC_CTL: ECDSAS Position */ +#define CRPT_ECC_CTL_ECDSAS_Msk (0x1ul << CRPT_ECC_CTL_ECDSAS_Pos) /*!< CRPT_T::ECC_CTL: ECDSAS Mask */ + +#define CRPT_ECC_CTL_ECDSAR_Pos (5) /*!< CRPT_T::ECC_CTL: ECDSAR Position */ +#define CRPT_ECC_CTL_ECDSAR_Msk (0x1ul << CRPT_ECC_CTL_ECDSAR_Pos) /*!< CRPT_T::ECC_CTL: ECDSAR Mask */ + +#define CRPT_ECC_CTL_DFAP_Pos (6) /*!< CRPT_T::ECC_CTL: DFAP Position */ +#define CRPT_ECC_CTL_DFAP_Msk (0x1ul << CRPT_ECC_CTL_DFAP_Pos) /*!< CRPT_T::ECC_CTL: DFAP Mask */ + +#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ +#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ + +#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ +#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ + +#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ +#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ + +#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ +#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ + +#define CRPT_ECC_CTL_CSEL_Pos (13) /*!< CRPT_T::ECC_CTL: CSEL Position */ +#define CRPT_ECC_CTL_CSEL_Msk (0x1ul << CRPT_ECC_CTL_CSEL_Pos) /*!< CRPT_T::ECC_CTL: CSEL Mask */ + +#define CRPT_ECC_CTL_SCAP_Pos (14) /*!< CRPT_T::ECC_CTL: SCAP Position */ +#define CRPT_ECC_CTL_SCAP_Msk (0x1ul << CRPT_ECC_CTL_SCAP_Pos) /*!< CRPT_T::ECC_CTL: SCAP Mask */ + +#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ +#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ + +#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ +#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ + +#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ +#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ + +#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ +#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ + +#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ +#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ + +#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ +#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ + +#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ +#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ + +#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ +#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ + +#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ +#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ + +#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ +#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ + +#define CRPT_ECC_STS_KSERR_Pos (17) /*!< CRPT_T::ECC_STS: KSERR Position */ +#define CRPT_ECC_STS_KSERR_Msk (0x1ul << CRPT_ECC_STS_KSERR_Pos) /*!< CRPT_T::ECC_STS: KSERR Mask */ + +#define CRPT_ECC_STS_DFAERR_Pos (18) /*!< CRPT_T::ECC_STS: DFAERR Position */ +#define CRPT_ECC_STS_DFAERR_Msk (0x1ul << CRPT_ECC_STS_DFAERR_Pos) /*!< CRPT_T::ECC_STS: DFAERR Mask */ + +#define CRPT_ECC_X1_00_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_00: POINTX1 Position */ +#define CRPT_ECC_X1_00_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_00_POINTX1_Pos) /*!< CRPT_T::ECC_X1_00: POINTX1 Mask */ + +#define CRPT_ECC_X1_01_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_01: POINTX1 Position */ +#define CRPT_ECC_X1_01_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_01_POINTX1_Pos) /*!< CRPT_T::ECC_X1_01: POINTX1 Mask */ + +#define CRPT_ECC_X1_02_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_02: POINTX1 Position */ +#define CRPT_ECC_X1_02_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_02_POINTX1_Pos) /*!< CRPT_T::ECC_X1_02: POINTX1 Mask */ + +#define CRPT_ECC_X1_03_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_03: POINTX1 Position */ +#define CRPT_ECC_X1_03_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_03_POINTX1_Pos) /*!< CRPT_T::ECC_X1_03: POINTX1 Mask */ + +#define CRPT_ECC_X1_04_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_04: POINTX1 Position */ +#define CRPT_ECC_X1_04_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_04_POINTX1_Pos) /*!< CRPT_T::ECC_X1_04: POINTX1 Mask */ + +#define CRPT_ECC_X1_05_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_05: POINTX1 Position */ +#define CRPT_ECC_X1_05_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_05_POINTX1_Pos) /*!< CRPT_T::ECC_X1_05: POINTX1 Mask */ + +#define CRPT_ECC_X1_06_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_06: POINTX1 Position */ +#define CRPT_ECC_X1_06_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_06_POINTX1_Pos) /*!< CRPT_T::ECC_X1_06: POINTX1 Mask */ + +#define CRPT_ECC_X1_07_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_07: POINTX1 Position */ +#define CRPT_ECC_X1_07_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_07_POINTX1_Pos) /*!< CRPT_T::ECC_X1_07: POINTX1 Mask */ + +#define CRPT_ECC_X1_08_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_08: POINTX1 Position */ +#define CRPT_ECC_X1_08_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_08_POINTX1_Pos) /*!< CRPT_T::ECC_X1_08: POINTX1 Mask */ + +#define CRPT_ECC_X1_09_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_09: POINTX1 Position */ +#define CRPT_ECC_X1_09_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_09_POINTX1_Pos) /*!< CRPT_T::ECC_X1_09: POINTX1 Mask */ + +#define CRPT_ECC_X1_10_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_10: POINTX1 Position */ +#define CRPT_ECC_X1_10_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_10_POINTX1_Pos) /*!< CRPT_T::ECC_X1_10: POINTX1 Mask */ + +#define CRPT_ECC_X1_11_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_11: POINTX1 Position */ +#define CRPT_ECC_X1_11_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_11_POINTX1_Pos) /*!< CRPT_T::ECC_X1_11: POINTX1 Mask */ + +#define CRPT_ECC_X1_12_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_12: POINTX1 Position */ +#define CRPT_ECC_X1_12_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_12_POINTX1_Pos) /*!< CRPT_T::ECC_X1_12: POINTX1 Mask */ + +#define CRPT_ECC_X1_13_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_13: POINTX1 Position */ +#define CRPT_ECC_X1_13_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_13_POINTX1_Pos) /*!< CRPT_T::ECC_X1_13: POINTX1 Mask */ + +#define CRPT_ECC_X1_14_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_14: POINTX1 Position */ +#define CRPT_ECC_X1_14_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_14_POINTX1_Pos) /*!< CRPT_T::ECC_X1_14: POINTX1 Mask */ + +#define CRPT_ECC_X1_15_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_15: POINTX1 Position */ +#define CRPT_ECC_X1_15_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_15_POINTX1_Pos) /*!< CRPT_T::ECC_X1_15: POINTX1 Mask */ + +#define CRPT_ECC_X1_16_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_16: POINTX1 Position */ +#define CRPT_ECC_X1_16_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_16_POINTX1_Pos) /*!< CRPT_T::ECC_X1_16: POINTX1 Mask */ + +#define CRPT_ECC_X1_17_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1_17: POINTX1 Position */ +#define CRPT_ECC_X1_17_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_17_POINTX1_Pos) /*!< CRPT_T::ECC_X1_17: POINTX1 Mask */ + +#define CRPT_ECC_Y1_00_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_00: POINTY1 Position */ +#define CRPT_ECC_Y1_00_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_00_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_00: POINTY1 Mask */ + +#define CRPT_ECC_Y1_01_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_01: POINTY1 Position */ +#define CRPT_ECC_Y1_01_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_01_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_01: POINTY1 Mask */ + +#define CRPT_ECC_Y1_02_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_02: POINTY1 Position */ +#define CRPT_ECC_Y1_02_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_02_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_02: POINTY1 Mask */ + +#define CRPT_ECC_Y1_03_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_03: POINTY1 Position */ +#define CRPT_ECC_Y1_03_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_03_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_03: POINTY1 Mask */ + +#define CRPT_ECC_Y1_04_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_04: POINTY1 Position */ +#define CRPT_ECC_Y1_04_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_04_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_04: POINTY1 Mask */ + +#define CRPT_ECC_Y1_05_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_05: POINTY1 Position */ +#define CRPT_ECC_Y1_05_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_05_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_05: POINTY1 Mask */ + +#define CRPT_ECC_Y1_06_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_06: POINTY1 Position */ +#define CRPT_ECC_Y1_06_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_06_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_06: POINTY1 Mask */ + +#define CRPT_ECC_Y1_07_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_07: POINTY1 Position */ +#define CRPT_ECC_Y1_07_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_07_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_07: POINTY1 Mask */ + +#define CRPT_ECC_Y1_08_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_08: POINTY1 Position */ +#define CRPT_ECC_Y1_08_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_08_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_08: POINTY1 Mask */ + +#define CRPT_ECC_Y1_09_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_09: POINTY1 Position */ +#define CRPT_ECC_Y1_09_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_09_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_09: POINTY1 Mask */ + +#define CRPT_ECC_Y1_10_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_10: POINTY1 Position */ +#define CRPT_ECC_Y1_10_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_10_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_10: POINTY1 Mask */ + +#define CRPT_ECC_Y1_11_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_11: POINTY1 Position */ +#define CRPT_ECC_Y1_11_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_11_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_11: POINTY1 Mask */ + +#define CRPT_ECC_Y1_12_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_12: POINTY1 Position */ +#define CRPT_ECC_Y1_12_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_12_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_12: POINTY1 Mask */ + +#define CRPT_ECC_Y1_13_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_13: POINTY1 Position */ +#define CRPT_ECC_Y1_13_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_13_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_13: POINTY1 Mask */ + +#define CRPT_ECC_Y1_14_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_14: POINTY1 Position */ +#define CRPT_ECC_Y1_14_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_14_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_14: POINTY1 Mask */ + +#define CRPT_ECC_Y1_15_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_15: POINTY1 Position */ +#define CRPT_ECC_Y1_15_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_15_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_15: POINTY1 Mask */ + +#define CRPT_ECC_Y1_16_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_16: POINTY1 Position */ +#define CRPT_ECC_Y1_16_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_16_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_16: POINTY1 Mask */ + +#define CRPT_ECC_Y1_17_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1_17: POINTY1 Position */ +#define CRPT_ECC_Y1_17_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_17_POINTY1_Pos) /*!< CRPT_T::ECC_Y1_17: POINTY1 Mask */ + +#define CRPT_ECC_X2_00_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_00: POINTX2 Position */ +#define CRPT_ECC_X2_00_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_00_POINTX2_Pos) /*!< CRPT_T::ECC_X2_00: POINTX2 Mask */ + +#define CRPT_ECC_X2_01_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_01: POINTX2 Position */ +#define CRPT_ECC_X2_01_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_01_POINTX2_Pos) /*!< CRPT_T::ECC_X2_01: POINTX2 Mask */ + +#define CRPT_ECC_X2_02_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_02: POINTX2 Position */ +#define CRPT_ECC_X2_02_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_02_POINTX2_Pos) /*!< CRPT_T::ECC_X2_02: POINTX2 Mask */ + +#define CRPT_ECC_X2_03_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_03: POINTX2 Position */ +#define CRPT_ECC_X2_03_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_03_POINTX2_Pos) /*!< CRPT_T::ECC_X2_03: POINTX2 Mask */ + +#define CRPT_ECC_X2_04_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_04: POINTX2 Position */ +#define CRPT_ECC_X2_04_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_04_POINTX2_Pos) /*!< CRPT_T::ECC_X2_04: POINTX2 Mask */ + +#define CRPT_ECC_X2_05_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_05: POINTX2 Position */ +#define CRPT_ECC_X2_05_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_05_POINTX2_Pos) /*!< CRPT_T::ECC_X2_05: POINTX2 Mask */ + +#define CRPT_ECC_X2_06_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_06: POINTX2 Position */ +#define CRPT_ECC_X2_06_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_06_POINTX2_Pos) /*!< CRPT_T::ECC_X2_06: POINTX2 Mask */ + +#define CRPT_ECC_X2_07_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_07: POINTX2 Position */ +#define CRPT_ECC_X2_07_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_07_POINTX2_Pos) /*!< CRPT_T::ECC_X2_07: POINTX2 Mask */ + +#define CRPT_ECC_X2_08_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_08: POINTX2 Position */ +#define CRPT_ECC_X2_08_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_08_POINTX2_Pos) /*!< CRPT_T::ECC_X2_08: POINTX2 Mask */ + +#define CRPT_ECC_X2_09_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_09: POINTX2 Position */ +#define CRPT_ECC_X2_09_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_09_POINTX2_Pos) /*!< CRPT_T::ECC_X2_09: POINTX2 Mask */ + +#define CRPT_ECC_X2_10_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_10: POINTX2 Position */ +#define CRPT_ECC_X2_10_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_10_POINTX2_Pos) /*!< CRPT_T::ECC_X2_10: POINTX2 Mask */ + +#define CRPT_ECC_X2_11_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_11: POINTX2 Position */ +#define CRPT_ECC_X2_11_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_11_POINTX2_Pos) /*!< CRPT_T::ECC_X2_11: POINTX2 Mask */ + +#define CRPT_ECC_X2_12_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_12: POINTX2 Position */ +#define CRPT_ECC_X2_12_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_12_POINTX2_Pos) /*!< CRPT_T::ECC_X2_12: POINTX2 Mask */ + +#define CRPT_ECC_X2_13_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_13: POINTX2 Position */ +#define CRPT_ECC_X2_13_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_13_POINTX2_Pos) /*!< CRPT_T::ECC_X2_13: POINTX2 Mask */ + +#define CRPT_ECC_X2_14_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_14: POINTX2 Position */ +#define CRPT_ECC_X2_14_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_14_POINTX2_Pos) /*!< CRPT_T::ECC_X2_14: POINTX2 Mask */ + +#define CRPT_ECC_X2_15_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_15: POINTX2 Position */ +#define CRPT_ECC_X2_15_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_15_POINTX2_Pos) /*!< CRPT_T::ECC_X2_15: POINTX2 Mask */ + +#define CRPT_ECC_X2_16_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_16: POINTX2 Position */ +#define CRPT_ECC_X2_16_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_16_POINTX2_Pos) /*!< CRPT_T::ECC_X2_16: POINTX2 Mask */ + +#define CRPT_ECC_X2_17_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2_17: POINTX2 Position */ +#define CRPT_ECC_X2_17_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_17_POINTX2_Pos) /*!< CRPT_T::ECC_X2_17: POINTX2 Mask */ + +#define CRPT_ECC_Y2_00_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_00: POINTY2 Position */ +#define CRPT_ECC_Y2_00_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_00_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_00: POINTY2 Mask */ + +#define CRPT_ECC_Y2_01_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_01: POINTY2 Position */ +#define CRPT_ECC_Y2_01_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_01_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_01: POINTY2 Mask */ + +#define CRPT_ECC_Y2_02_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_02: POINTY2 Position */ +#define CRPT_ECC_Y2_02_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_02_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_02: POINTY2 Mask */ + +#define CRPT_ECC_Y2_03_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_03: POINTY2 Position */ +#define CRPT_ECC_Y2_03_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_03_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_03: POINTY2 Mask */ + +#define CRPT_ECC_Y2_04_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_04: POINTY2 Position */ +#define CRPT_ECC_Y2_04_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_04_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_04: POINTY2 Mask */ + +#define CRPT_ECC_Y2_05_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_05: POINTY2 Position */ +#define CRPT_ECC_Y2_05_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_05_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_05: POINTY2 Mask */ + +#define CRPT_ECC_Y2_06_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_06: POINTY2 Position */ +#define CRPT_ECC_Y2_06_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_06_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_06: POINTY2 Mask */ + +#define CRPT_ECC_Y2_07_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_07: POINTY2 Position */ +#define CRPT_ECC_Y2_07_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_07_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_07: POINTY2 Mask */ + +#define CRPT_ECC_Y2_08_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_08: POINTY2 Position */ +#define CRPT_ECC_Y2_08_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_08_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_08: POINTY2 Mask */ + +#define CRPT_ECC_Y2_09_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_09: POINTY2 Position */ +#define CRPT_ECC_Y2_09_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_09_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_09: POINTY2 Mask */ + +#define CRPT_ECC_Y2_10_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_10: POINTY2 Position */ +#define CRPT_ECC_Y2_10_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_10_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_10: POINTY2 Mask */ + +#define CRPT_ECC_Y2_11_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_11: POINTY2 Position */ +#define CRPT_ECC_Y2_11_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_11_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_11: POINTY2 Mask */ + +#define CRPT_ECC_Y2_12_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_12: POINTY2 Position */ +#define CRPT_ECC_Y2_12_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_12_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_12: POINTY2 Mask */ + +#define CRPT_ECC_Y2_13_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_13: POINTY2 Position */ +#define CRPT_ECC_Y2_13_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_13_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_13: POINTY2 Mask */ + +#define CRPT_ECC_Y2_14_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_14: POINTY2 Position */ +#define CRPT_ECC_Y2_14_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_14_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_14: POINTY2 Mask */ + +#define CRPT_ECC_Y2_15_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_15: POINTY2 Position */ +#define CRPT_ECC_Y2_15_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_15_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_15: POINTY2 Mask */ + +#define CRPT_ECC_Y2_16_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_16: POINTY2 Position */ +#define CRPT_ECC_Y2_16_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_16_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_16: POINTY2 Mask */ + +#define CRPT_ECC_Y2_17_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2_17: POINTY2 Position */ +#define CRPT_ECC_Y2_17_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_17_POINTY2_Pos) /*!< CRPT_T::ECC_Y2_17: POINTY2 Mask */ + +#define CRPT_ECC_A_00_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_00: CURVEA Position */ +#define CRPT_ECC_A_00_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_00_CURVEA_Pos) /*!< CRPT_T::ECC_A_00: CURVEA Mask */ + +#define CRPT_ECC_A_01_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_01: CURVEA Position */ +#define CRPT_ECC_A_01_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_01_CURVEA_Pos) /*!< CRPT_T::ECC_A_01: CURVEA Mask */ + +#define CRPT_ECC_A_02_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_02: CURVEA Position */ +#define CRPT_ECC_A_02_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_02_CURVEA_Pos) /*!< CRPT_T::ECC_A_02: CURVEA Mask */ + +#define CRPT_ECC_A_03_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_03: CURVEA Position */ +#define CRPT_ECC_A_03_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_03_CURVEA_Pos) /*!< CRPT_T::ECC_A_03: CURVEA Mask */ + +#define CRPT_ECC_A_04_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_04: CURVEA Position */ +#define CRPT_ECC_A_04_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_04_CURVEA_Pos) /*!< CRPT_T::ECC_A_04: CURVEA Mask */ + +#define CRPT_ECC_A_05_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_05: CURVEA Position */ +#define CRPT_ECC_A_05_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_05_CURVEA_Pos) /*!< CRPT_T::ECC_A_05: CURVEA Mask */ + +#define CRPT_ECC_A_06_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_06: CURVEA Position */ +#define CRPT_ECC_A_06_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_06_CURVEA_Pos) /*!< CRPT_T::ECC_A_06: CURVEA Mask */ + +#define CRPT_ECC_A_07_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_07: CURVEA Position */ +#define CRPT_ECC_A_07_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_07_CURVEA_Pos) /*!< CRPT_T::ECC_A_07: CURVEA Mask */ + +#define CRPT_ECC_A_08_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_08: CURVEA Position */ +#define CRPT_ECC_A_08_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_08_CURVEA_Pos) /*!< CRPT_T::ECC_A_08: CURVEA Mask */ + +#define CRPT_ECC_A_09_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_09: CURVEA Position */ +#define CRPT_ECC_A_09_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_09_CURVEA_Pos) /*!< CRPT_T::ECC_A_09: CURVEA Mask */ + +#define CRPT_ECC_A_10_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_10: CURVEA Position */ +#define CRPT_ECC_A_10_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_10_CURVEA_Pos) /*!< CRPT_T::ECC_A_10: CURVEA Mask */ + +#define CRPT_ECC_A_11_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_11: CURVEA Position */ +#define CRPT_ECC_A_11_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_11_CURVEA_Pos) /*!< CRPT_T::ECC_A_11: CURVEA Mask */ + +#define CRPT_ECC_A_12_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_12: CURVEA Position */ +#define CRPT_ECC_A_12_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_12_CURVEA_Pos) /*!< CRPT_T::ECC_A_12: CURVEA Mask */ + +#define CRPT_ECC_A_13_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_13: CURVEA Position */ +#define CRPT_ECC_A_13_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_13_CURVEA_Pos) /*!< CRPT_T::ECC_A_13: CURVEA Mask */ + +#define CRPT_ECC_A_14_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_14: CURVEA Position */ +#define CRPT_ECC_A_14_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_14_CURVEA_Pos) /*!< CRPT_T::ECC_A_14: CURVEA Mask */ + +#define CRPT_ECC_A_15_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_15: CURVEA Position */ +#define CRPT_ECC_A_15_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_15_CURVEA_Pos) /*!< CRPT_T::ECC_A_15: CURVEA Mask */ + +#define CRPT_ECC_A_16_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_16: CURVEA Position */ +#define CRPT_ECC_A_16_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_16_CURVEA_Pos) /*!< CRPT_T::ECC_A_16: CURVEA Mask */ + +#define CRPT_ECC_A_17_CURVEA_Pos (0) /*!< CRPT_T::ECC_A_17: CURVEA Position */ +#define CRPT_ECC_A_17_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_17_CURVEA_Pos) /*!< CRPT_T::ECC_A_17: CURVEA Mask */ + +#define CRPT_ECC_B_00_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_00: CURVEB Position */ +#define CRPT_ECC_B_00_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_00_CURVEB_Pos) /*!< CRPT_T::ECC_B_00: CURVEB Mask */ + +#define CRPT_ECC_B_01_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_01: CURVEB Position */ +#define CRPT_ECC_B_01_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_01_CURVEB_Pos) /*!< CRPT_T::ECC_B_01: CURVEB Mask */ + +#define CRPT_ECC_B_02_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_02: CURVEB Position */ +#define CRPT_ECC_B_02_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_02_CURVEB_Pos) /*!< CRPT_T::ECC_B_02: CURVEB Mask */ + +#define CRPT_ECC_B_03_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_03: CURVEB Position */ +#define CRPT_ECC_B_03_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_03_CURVEB_Pos) /*!< CRPT_T::ECC_B_03: CURVEB Mask */ + +#define CRPT_ECC_B_04_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_04: CURVEB Position */ +#define CRPT_ECC_B_04_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_04_CURVEB_Pos) /*!< CRPT_T::ECC_B_04: CURVEB Mask */ + +#define CRPT_ECC_B_05_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_05: CURVEB Position */ +#define CRPT_ECC_B_05_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_05_CURVEB_Pos) /*!< CRPT_T::ECC_B_05: CURVEB Mask */ + +#define CRPT_ECC_B_06_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_06: CURVEB Position */ +#define CRPT_ECC_B_06_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_06_CURVEB_Pos) /*!< CRPT_T::ECC_B_06: CURVEB Mask */ + +#define CRPT_ECC_B_07_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_07: CURVEB Position */ +#define CRPT_ECC_B_07_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_07_CURVEB_Pos) /*!< CRPT_T::ECC_B_07: CURVEB Mask */ + +#define CRPT_ECC_B_08_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_08: CURVEB Position */ +#define CRPT_ECC_B_08_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_08_CURVEB_Pos) /*!< CRPT_T::ECC_B_08: CURVEB Mask */ + +#define CRPT_ECC_B_09_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_09: CURVEB Position */ +#define CRPT_ECC_B_09_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_09_CURVEB_Pos) /*!< CRPT_T::ECC_B_09: CURVEB Mask */ + +#define CRPT_ECC_B_10_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_10: CURVEB Position */ +#define CRPT_ECC_B_10_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_10_CURVEB_Pos) /*!< CRPT_T::ECC_B_10: CURVEB Mask */ + +#define CRPT_ECC_B_11_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_11: CURVEB Position */ +#define CRPT_ECC_B_11_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_11_CURVEB_Pos) /*!< CRPT_T::ECC_B_11: CURVEB Mask */ + +#define CRPT_ECC_B_12_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_12: CURVEB Position */ +#define CRPT_ECC_B_12_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_12_CURVEB_Pos) /*!< CRPT_T::ECC_B_12: CURVEB Mask */ + +#define CRPT_ECC_B_13_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_13: CURVEB Position */ +#define CRPT_ECC_B_13_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_13_CURVEB_Pos) /*!< CRPT_T::ECC_B_13: CURVEB Mask */ + +#define CRPT_ECC_B_14_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_14: CURVEB Position */ +#define CRPT_ECC_B_14_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_14_CURVEB_Pos) /*!< CRPT_T::ECC_B_14: CURVEB Mask */ + +#define CRPT_ECC_B_15_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_15: CURVEB Position */ +#define CRPT_ECC_B_15_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_15_CURVEB_Pos) /*!< CRPT_T::ECC_B_15: CURVEB Mask */ + +#define CRPT_ECC_B_16_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_16: CURVEB Position */ +#define CRPT_ECC_B_16_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_16_CURVEB_Pos) /*!< CRPT_T::ECC_B_16: CURVEB Mask */ + +#define CRPT_ECC_B_17_CURVEB_Pos (0) /*!< CRPT_T::ECC_B_17: CURVEB Position */ +#define CRPT_ECC_B_17_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_17_CURVEB_Pos) /*!< CRPT_T::ECC_B_17: CURVEB Mask */ + +#define CRPT_ECC_N_00_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_00: CURVEN Position */ +#define CRPT_ECC_N_00_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_00_CURVEN_Pos) /*!< CRPT_T::ECC_N_00: CURVEN Mask */ + +#define CRPT_ECC_N_01_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_01: CURVEN Position */ +#define CRPT_ECC_N_01_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_01_CURVEN_Pos) /*!< CRPT_T::ECC_N_01: CURVEN Mask */ + +#define CRPT_ECC_N_02_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_02: CURVEN Position */ +#define CRPT_ECC_N_02_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_02_CURVEN_Pos) /*!< CRPT_T::ECC_N_02: CURVEN Mask */ + +#define CRPT_ECC_N_03_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_03: CURVEN Position */ +#define CRPT_ECC_N_03_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_03_CURVEN_Pos) /*!< CRPT_T::ECC_N_03: CURVEN Mask */ + +#define CRPT_ECC_N_04_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_04: CURVEN Position */ +#define CRPT_ECC_N_04_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_04_CURVEN_Pos) /*!< CRPT_T::ECC_N_04: CURVEN Mask */ + +#define CRPT_ECC_N_05_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_05: CURVEN Position */ +#define CRPT_ECC_N_05_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_05_CURVEN_Pos) /*!< CRPT_T::ECC_N_05: CURVEN Mask */ + +#define CRPT_ECC_N_06_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_06: CURVEN Position */ +#define CRPT_ECC_N_06_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_06_CURVEN_Pos) /*!< CRPT_T::ECC_N_06: CURVEN Mask */ + +#define CRPT_ECC_N_07_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_07: CURVEN Position */ +#define CRPT_ECC_N_07_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_07_CURVEN_Pos) /*!< CRPT_T::ECC_N_07: CURVEN Mask */ + +#define CRPT_ECC_N_08_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_08: CURVEN Position */ +#define CRPT_ECC_N_08_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_08_CURVEN_Pos) /*!< CRPT_T::ECC_N_08: CURVEN Mask */ + +#define CRPT_ECC_N_09_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_09: CURVEN Position */ +#define CRPT_ECC_N_09_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_09_CURVEN_Pos) /*!< CRPT_T::ECC_N_09: CURVEN Mask */ + +#define CRPT_ECC_N_10_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_10: CURVEN Position */ +#define CRPT_ECC_N_10_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_10_CURVEN_Pos) /*!< CRPT_T::ECC_N_10: CURVEN Mask */ + +#define CRPT_ECC_N_11_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_11: CURVEN Position */ +#define CRPT_ECC_N_11_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_11_CURVEN_Pos) /*!< CRPT_T::ECC_N_11: CURVEN Mask */ + +#define CRPT_ECC_N_12_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_12: CURVEN Position */ +#define CRPT_ECC_N_12_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_12_CURVEN_Pos) /*!< CRPT_T::ECC_N_12: CURVEN Mask */ + +#define CRPT_ECC_N_13_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_13: CURVEN Position */ +#define CRPT_ECC_N_13_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_13_CURVEN_Pos) /*!< CRPT_T::ECC_N_13: CURVEN Mask */ + +#define CRPT_ECC_N_14_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_14: CURVEN Position */ +#define CRPT_ECC_N_14_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_14_CURVEN_Pos) /*!< CRPT_T::ECC_N_14: CURVEN Mask */ + +#define CRPT_ECC_N_15_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_15: CURVEN Position */ +#define CRPT_ECC_N_15_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_15_CURVEN_Pos) /*!< CRPT_T::ECC_N_15: CURVEN Mask */ + +#define CRPT_ECC_N_16_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_16: CURVEN Position */ +#define CRPT_ECC_N_16_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_16_CURVEN_Pos) /*!< CRPT_T::ECC_N_16: CURVEN Mask */ + +#define CRPT_ECC_N_17_CURVEN_Pos (0) /*!< CRPT_T::ECC_N_17: CURVEN Position */ +#define CRPT_ECC_N_17_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_17_CURVEN_Pos) /*!< CRPT_T::ECC_N_17: CURVEN Mask */ + +#define CRPT_ECC_K_00_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_00: SCALARK Position */ +#define CRPT_ECC_K_00_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_00_SCALARK_Pos) /*!< CRPT_T::ECC_K_00: SCALARK Mask */ + +#define CRPT_ECC_K_01_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_01: SCALARK Position */ +#define CRPT_ECC_K_01_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_01_SCALARK_Pos) /*!< CRPT_T::ECC_K_01: SCALARK Mask */ + +#define CRPT_ECC_K_02_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_02: SCALARK Position */ +#define CRPT_ECC_K_02_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_02_SCALARK_Pos) /*!< CRPT_T::ECC_K_02: SCALARK Mask */ + +#define CRPT_ECC_K_03_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_03: SCALARK Position */ +#define CRPT_ECC_K_03_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_03_SCALARK_Pos) /*!< CRPT_T::ECC_K_03: SCALARK Mask */ + +#define CRPT_ECC_K_04_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_04: SCALARK Position */ +#define CRPT_ECC_K_04_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_04_SCALARK_Pos) /*!< CRPT_T::ECC_K_04: SCALARK Mask */ + +#define CRPT_ECC_K_05_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_05: SCALARK Position */ +#define CRPT_ECC_K_05_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_05_SCALARK_Pos) /*!< CRPT_T::ECC_K_05: SCALARK Mask */ + +#define CRPT_ECC_K_06_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_06: SCALARK Position */ +#define CRPT_ECC_K_06_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_06_SCALARK_Pos) /*!< CRPT_T::ECC_K_06: SCALARK Mask */ + +#define CRPT_ECC_K_07_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_07: SCALARK Position */ +#define CRPT_ECC_K_07_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_07_SCALARK_Pos) /*!< CRPT_T::ECC_K_07: SCALARK Mask */ + +#define CRPT_ECC_K_08_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_08: SCALARK Position */ +#define CRPT_ECC_K_08_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_08_SCALARK_Pos) /*!< CRPT_T::ECC_K_08: SCALARK Mask */ + +#define CRPT_ECC_K_09_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_09: SCALARK Position */ +#define CRPT_ECC_K_09_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_09_SCALARK_Pos) /*!< CRPT_T::ECC_K_09: SCALARK Mask */ + +#define CRPT_ECC_K_10_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_10: SCALARK Position */ +#define CRPT_ECC_K_10_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_10_SCALARK_Pos) /*!< CRPT_T::ECC_K_10: SCALARK Mask */ + +#define CRPT_ECC_K_11_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_11: SCALARK Position */ +#define CRPT_ECC_K_11_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_11_SCALARK_Pos) /*!< CRPT_T::ECC_K_11: SCALARK Mask */ + +#define CRPT_ECC_K_12_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_12: SCALARK Position */ +#define CRPT_ECC_K_12_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_12_SCALARK_Pos) /*!< CRPT_T::ECC_K_12: SCALARK Mask */ + +#define CRPT_ECC_K_13_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_13: SCALARK Position */ +#define CRPT_ECC_K_13_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_13_SCALARK_Pos) /*!< CRPT_T::ECC_K_13: SCALARK Mask */ + +#define CRPT_ECC_K_14_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_14: SCALARK Position */ +#define CRPT_ECC_K_14_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_14_SCALARK_Pos) /*!< CRPT_T::ECC_K_14: SCALARK Mask */ + +#define CRPT_ECC_K_15_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_15: SCALARK Position */ +#define CRPT_ECC_K_15_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_15_SCALARK_Pos) /*!< CRPT_T::ECC_K_15: SCALARK Mask */ + +#define CRPT_ECC_K_16_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_16: SCALARK Position */ +#define CRPT_ECC_K_16_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_16_SCALARK_Pos) /*!< CRPT_T::ECC_K_16: SCALARK Mask */ + +#define CRPT_ECC_K_17_SCALARK_Pos (0) /*!< CRPT_T::ECC_K_17: SCALARK Position */ +#define CRPT_ECC_K_17_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_17_SCALARK_Pos) /*!< CRPT_T::ECC_K_17: SCALARK Mask */ + +#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ +#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ + +#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ +#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ + +#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */ +#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ + +#define CRPT_RSA_CTL_START_Pos (0) /*!< CRPT_T::RSA_CTL: START Position */ +#define CRPT_RSA_CTL_START_Msk (0x1ul << CRPT_RSA_CTL_START_Pos) /*!< CRPT_T::RSA_CTL: START Mask */ + +#define CRPT_RSA_CTL_STOP_Pos (1) /*!< CRPT_T::RSA_CTL: STOP Position */ +#define CRPT_RSA_CTL_STOP_Msk (0x1ul << CRPT_RSA_CTL_STOP_Pos) /*!< CRPT_T::RSA_CTL: STOP Mask */ + +#define CRPT_RSA_CTL_CRT_Pos (2) /*!< CRPT_T::RSA_CTL: CRT Position */ +#define CRPT_RSA_CTL_CRT_Msk (0x1ul << CRPT_RSA_CTL_CRT_Pos) /*!< CRPT_T::RSA_CTL: CRT Mask */ + +#define CRPT_RSA_CTL_CRTBYP_Pos (3) /*!< CRPT_T::RSA_CTL: CRTBYP Position */ +#define CRPT_RSA_CTL_CRTBYP_Msk (0x1ul << CRPT_RSA_CTL_CRTBYP_Pos) /*!< CRPT_T::RSA_CTL: CRTBYP Mask */ + +#define CRPT_RSA_CTL_KEYLENG_Pos (4) /*!< CRPT_T::RSA_CTL: KEYLENG Position */ +#define CRPT_RSA_CTL_KEYLENG_Msk (0x3ul << CRPT_RSA_CTL_KEYLENG_Pos) /*!< CRPT_T::RSA_CTL: KEYLENG Mask */ + +#define CRPT_RSA_CTL_SCAP_Pos (8) /*!< CRPT_T::RSA_CTL: SCAP Position */ +#define CRPT_RSA_CTL_SCAP_Msk (0x1ul << CRPT_RSA_CTL_SCAP_Pos) /*!< CRPT_T::RSA_CTL: SCAP Mask */ + +#define CRPT_RSA_STS_BUSY_Pos (0) /*!< CRPT_T::RSA_STS: BUSY Position */ +#define CRPT_RSA_STS_BUSY_Msk (0x1ul << CRPT_RSA_STS_BUSY_Pos) /*!< CRPT_T::RSA_STS: BUSY Mask */ + +#define CRPT_RSA_STS_DMABUSY_Pos (1) /*!< CRPT_T::RSA_STS: DMABUSY Position */ +#define CRPT_RSA_STS_DMABUSY_Msk (0x1ul << CRPT_RSA_STS_DMABUSY_Pos) /*!< CRPT_T::RSA_STS: DMABUSY Mask */ + +#define CRPT_RSA_STS_BUSERR_Pos (16) /*!< CRPT_T::RSA_STS: BUSERR Position */ +#define CRPT_RSA_STS_BUSERR_Msk (0x1ul << CRPT_RSA_STS_BUSERR_Pos) /*!< CRPT_T::RSA_STS: BUSERR Mask */ + +#define CRPT_RSA_STS_CTLERR_Pos (17) /*!< CRPT_T::RSA_STS: CTLERR Position */ +#define CRPT_RSA_STS_CTLERR_Msk (0x1ul << CRPT_RSA_STS_CTLERR_Pos) /*!< CRPT_T::RSA_STS: CTLERR Mask */ + +#define CRPT_RSA_STS_KSERR_Pos (18) /*!< CRPT_T::RSA_STS: KSERR Position */ +#define CRPT_RSA_STS_KSERR_Msk (0x1ul << CRPT_RSA_STS_KSERR_Pos) /*!< CRPT_T::RSA_STS: KSERR Mask */ + +#define CRPT_RSA_SADDR0_SADDR0_Pos (0) /*!< CRPT_T::RSA_SADDR0: SADDR0 Position */ +#define CRPT_RSA_SADDR0_SADDR0_Msk (0xfffffffful << CRPT_RSA_SADDR0_SADDR0_Pos) /*!< CRPT_T::RSA_SADDR0: SADDR0 Mask */ + +#define CRPT_RSA_SADDR1_SADDR1_Pos (0) /*!< CRPT_T::RSA_SADDR1: SADDR1 Position */ +#define CRPT_RSA_SADDR1_SADDR1_Msk (0xfffffffful << CRPT_RSA_SADDR1_SADDR1_Pos) /*!< CRPT_T::RSA_SADDR1: SADDR1 Mask */ + +#define CRPT_RSA_SADDR2_SADDR2_Pos (0) /*!< CRPT_T::RSA_SADDR2: SADDR2 Position */ +#define CRPT_RSA_SADDR2_SADDR2_Msk (0xfffffffful << CRPT_RSA_SADDR2_SADDR2_Pos) /*!< CRPT_T::RSA_SADDR2: SADDR2 Mask */ + +#define CRPT_RSA_SADDR3_SADDR3_Pos (0) /*!< CRPT_T::RSA_SADDR3: SADDR3 Position */ +#define CRPT_RSA_SADDR3_SADDR3_Msk (0xfffffffful << CRPT_RSA_SADDR3_SADDR3_Pos) /*!< CRPT_T::RSA_SADDR3: SADDR3 Mask */ + +#define CRPT_RSA_SADDR4_SADDR4_Pos (0) /*!< CRPT_T::RSA_SADDR4: SADDR4 Position */ +#define CRPT_RSA_SADDR4_SADDR4_Msk (0xfffffffful << CRPT_RSA_SADDR4_SADDR4_Pos) /*!< CRPT_T::RSA_SADDR4: SADDR4 Mask */ + +#define CRPT_RSA_DADDR_DADDR_Pos (0) /*!< CRPT_T::RSA_DADDR: DADDR Position */ +#define CRPT_RSA_DADDR_DADDR_Msk (0xfffffffful << CRPT_RSA_DADDR_DADDR_Pos) /*!< CRPT_T::RSA_DADDR: DADDR Mask */ + +#define CRPT_RSA_MADDR0_MADDR0_Pos (0) /*!< CRPT_T::RSA_MADDR0: MADDR0 Position */ +#define CRPT_RSA_MADDR0_MADDR0_Msk (0xfffffffful << CRPT_RSA_MADDR0_MADDR0_Pos) /*!< CRPT_T::RSA_MADDR0: MADDR0 Mask */ + +#define CRPT_RSA_MADDR1_MADDR1_Pos (0) /*!< CRPT_T::RSA_MADDR1: MADDR1 Position */ +#define CRPT_RSA_MADDR1_MADDR1_Msk (0xfffffffful << CRPT_RSA_MADDR1_MADDR1_Pos) /*!< CRPT_T::RSA_MADDR1: MADDR1 Mask */ + +#define CRPT_RSA_MADDR2_MADDR2_Pos (0) /*!< CRPT_T::RSA_MADDR2: MADDR2 Position */ +#define CRPT_RSA_MADDR2_MADDR2_Msk (0xfffffffful << CRPT_RSA_MADDR2_MADDR2_Pos) /*!< CRPT_T::RSA_MADDR2: MADDR2 Mask */ + +#define CRPT_RSA_MADDR3_MADDR3_Pos (0) /*!< CRPT_T::RSA_MADDR3: MADDR3 Position */ +#define CRPT_RSA_MADDR3_MADDR3_Msk (0xfffffffful << CRPT_RSA_MADDR3_MADDR3_Pos) /*!< CRPT_T::RSA_MADDR3: MADDR3 Mask */ + +#define CRPT_RSA_MADDR4_MADDR4_Pos (0) /*!< CRPT_T::RSA_MADDR4: MADDR4 Position */ +#define CRPT_RSA_MADDR4_MADDR4_Msk (0xfffffffful << CRPT_RSA_MADDR4_MADDR4_Pos) /*!< CRPT_T::RSA_MADDR4: MADDR4 Mask */ + +#define CRPT_RSA_MADDR5_MADDR5_Pos (0) /*!< CRPT_T::RSA_MADDR5: MADDR5 Position */ +#define CRPT_RSA_MADDR5_MADDR5_Msk (0xfffffffful << CRPT_RSA_MADDR5_MADDR5_Pos) /*!< CRPT_T::RSA_MADDR5: MADDR5 Mask */ + +#define CRPT_RSA_MADDR6_MADDR6_Pos (0) /*!< CRPT_T::RSA_MADDR6: MADDR6 Position */ +#define CRPT_RSA_MADDR6_MADDR6_Msk (0xfffffffful << CRPT_RSA_MADDR6_MADDR6_Pos) /*!< CRPT_T::RSA_MADDR6: MADDR6 Mask */ + +#define CRPT_PRNG_KSCTL_NUM_Pos (0) /*!< CRPT_T::PRNG_KSCTL: NUM Position */ +#define CRPT_PRNG_KSCTL_NUM_Msk (0x1ful << CRPT_PRNG_KSCTL_NUM_Pos) /*!< CRPT_T::PRNG_KSCTL: NUM Mask */ + +#define CRPT_PRNG_KSCTL_TRUST_Pos (16) /*!< CRPT_T::PRNG_KSCTL: TRUST Position */ +#define CRPT_PRNG_KSCTL_TRUST_Msk (0x1ul << CRPT_PRNG_KSCTL_TRUST_Pos) /*!< CRPT_T::PRNG_KSCTL: TRUST Mask */ + +#define CRPT_PRNG_KSCTL_ECDH_Pos (19) /*!< CRPT_T::PRNG_KSCTL: ECDH Position */ +#define CRPT_PRNG_KSCTL_ECDH_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDH_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDH Mask */ + +#define CRPT_PRNG_KSCTL_ECDSA_Pos (20) /*!< CRPT_T::PRNG_KSCTL: ECDSA Position */ +#define CRPT_PRNG_KSCTL_ECDSA_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDSA_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDSA Mask */ + +#define CRPT_PRNG_KSCTL_WDST_Pos (21) /*!< CRPT_T::PRNG_KSCTL: WDST Position */ +#define CRPT_PRNG_KSCTL_WDST_Msk (0x1ul << CRPT_PRNG_KSCTL_WDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WDST Mask */ + +#define CRPT_PRNG_KSCTL_WSDST_Pos (22) /*!< CRPT_T::PRNG_KSCTL: WSDST Position */ +#define CRPT_PRNG_KSCTL_WSDST_Msk (0x3ul << CRPT_PRNG_KSCTL_WSDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WSDST Mask */ + +#define CRPT_PRNG_KSCTL_OWNER_Pos (24) /*!< CRPT_T::PRNG_KSCTL: OWNER Position */ +#define CRPT_PRNG_KSCTL_OWNER_Msk (0x7ul << CRPT_PRNG_KSCTL_OWNER_Pos) /*!< CRPT_T::PRNG_KSCTL: OWNER Mask */ + +#define CRPT_PRNG_KSSTS_NUM_Pos (0) /*!< CRPT_T::PRNG_KSSTS: NUM Position */ +#define CRPT_PRNG_KSSTS_NUM_Msk (0x1ful << CRPT_PRNG_KSSTS_NUM_Pos) /*!< CRPT_T::PRNG_KSSTS: NUM Mask */ + +#define CRPT_PRNG_KSSTS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Position */ +#define CRPT_PRNG_KSSTS_KCTLERR_Msk (0x1ul << CRPT_PRNG_KSSTS_KCTLERR_Pos) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Mask */ + +#define CRPT_AES_KSCTL_NUM_Pos (0) /*!< CRPT_T::AES_KSCTL: NUM Position */ +#define CRPT_AES_KSCTL_NUM_Msk (0x1ful << CRPT_AES_KSCTL_NUM_Pos) /*!< CRPT_T::AES_KSCTL: NUM Mask */ + +#define CRPT_AES_KSCTL_RSRC_Pos (5) /*!< CRPT_T::AES_KSCTL: RSRC Position */ +#define CRPT_AES_KSCTL_RSRC_Msk (0x1ul << CRPT_AES_KSCTL_RSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSRC Mask */ + +#define CRPT_AES_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::AES_KSCTL: RSSRC Position */ +#define CRPT_AES_KSCTL_RSSRC_Msk (0x3ul << CRPT_AES_KSCTL_RSSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSSRC Mask */ + +#define CRPT_HMAC_KSCTL_NUM_Pos (0) /*!< CRPT_T::HMAC_KSCTL: NUM Position */ +#define CRPT_HMAC_KSCTL_NUM_Msk (0x1ful << CRPT_HMAC_KSCTL_NUM_Pos) /*!< CRPT_T::HMAC_KSCTL: NUM Mask */ + +#define CRPT_HMAC_KSCTL_RSRC_Pos (5) /*!< CRPT_T::HMAC_KSCTL: RSRC Position */ +#define CRPT_HMAC_KSCTL_RSRC_Msk (0x1ul << CRPT_HMAC_KSCTL_RSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSRC Mask */ + +#define CRPT_HMAC_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::HMAC_KSCTL: RSSRC Position */ +#define CRPT_HMAC_KSCTL_RSSRC_Msk (0x3ul << CRPT_HMAC_KSCTL_RSSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSSRC Mask */ + +#define CRPT_ECC_KSCTL_NUMK_Pos (0) /*!< CRPT_T::ECC_KSCTL: NUMK Position */ +#define CRPT_ECC_KSCTL_NUMK_Msk (0x1ful << CRPT_ECC_KSCTL_NUMK_Pos) /*!< CRPT_T::ECC_KSCTL: NUMK Mask */ + +#define CRPT_ECC_KSCTL_RSRCK_Pos (5) /*!< CRPT_T::ECC_KSCTL: RSRCK Position */ +#define CRPT_ECC_KSCTL_RSRCK_Msk (0x1ul << CRPT_ECC_KSCTL_RSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSRCK Mask */ + +#define CRPT_ECC_KSCTL_RSSRCK_Pos (6) /*!< CRPT_T::ECC_KSCTL: RSSRCK Position */ +#define CRPT_ECC_KSCTL_RSSRCK_Msk (0x3ul << CRPT_ECC_KSCTL_RSSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSSRCK Mask */ + +#define CRPT_ECC_KSCTL_ECDH_Pos (14) /*!< CRPT_T::ECC_KSCTL: ECDH Position */ +#define CRPT_ECC_KSCTL_ECDH_Msk (0x1ul << CRPT_ECC_KSCTL_ECDH_Pos) /*!< CRPT_T::ECC_KSCTL: ECDH Mask */ + +#define CRPT_ECC_KSCTL_TRUST_Pos (16) /*!< CRPT_T::ECC_KSCTL: TRUST Position */ +#define CRPT_ECC_KSCTL_TRUST_Msk (0x1ul << CRPT_ECC_KSCTL_TRUST_Pos) /*!< CRPT_T::ECC_KSCTL: TRUST Mask */ + +#define CRPT_ECC_KSCTL_XY_Pos (20) /*!< CRPT_T::ECC_KSCTL: XY Position */ +#define CRPT_ECC_KSCTL_XY_Msk (0x1ul << CRPT_ECC_KSCTL_XY_Pos) /*!< CRPT_T::ECC_KSCTL: XY Mask */ + +#define CRPT_ECC_KSCTL_WDST_Pos (21) /*!< CRPT_T::ECC_KSCTL: WDST Position */ +#define CRPT_ECC_KSCTL_WDST_Msk (0x1ul << CRPT_ECC_KSCTL_WDST_Pos) /*!< CRPT_T::ECC_KSCTL: WDST Mask */ + +#define CRPT_ECC_KSCTL_WSDST_Pos (22) /*!< CRPT_T::ECC_KSCTL: WSDST Position */ +#define CRPT_ECC_KSCTL_WSDST_Msk (0x3ul << CRPT_ECC_KSCTL_WSDST_Pos) /*!< CRPT_T::ECC_KSCTL: WSDST Mask */ + +#define CRPT_ECC_KSCTL_OWNER_Pos (24) /*!< CRPT_T::ECC_KSCTL: OWNER Position */ +#define CRPT_ECC_KSCTL_OWNER_Msk (0x7ul << CRPT_ECC_KSCTL_OWNER_Pos) /*!< CRPT_T::ECC_KSCTL: OWNER Mask */ + +#define CRPT_ECC_KSSTS_NUM_Pos (0) /*!< CRPT_T::ECC_KSSTS: NUM Position */ +#define CRPT_ECC_KSSTS_NUM_Msk (0x1ful << CRPT_ECC_KSSTS_NUM_Pos) /*!< CRPT_T::ECC_KSSTS: NUM Mask */ + +#define CRPT_ECC_KSXY_NUMX_Pos (0) /*!< CRPT_T::ECC_KSXY: NUMX Position */ +#define CRPT_ECC_KSXY_NUMX_Msk (0x1ful << CRPT_ECC_KSXY_NUMX_Pos) /*!< CRPT_T::ECC_KSXY: NUMX Mask */ + +#define CRPT_ECC_KSXY_RSRCXY_Pos (5) /*!< CRPT_T::ECC_KSXY: RSRCXY Position */ +#define CRPT_ECC_KSXY_RSRCXY_Msk (0x1ul << CRPT_ECC_KSXY_RSRCXY_Pos) /*!< CRPT_T::ECC_KSXY: RSRCXY Mask */ + +#define CRPT_ECC_KSXY_RSSRCX_Pos (6) /*!< CRPT_T::ECC_KSXY: RSSRCX Position */ +#define CRPT_ECC_KSXY_RSSRCX_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCX_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCX Mask */ + +#define CRPT_ECC_KSXY_NUMY_Pos (8) /*!< CRPT_T::ECC_KSXY: NUMY Position */ +#define CRPT_ECC_KSXY_NUMY_Msk (0x1ful << CRPT_ECC_KSXY_NUMY_Pos) /*!< CRPT_T::ECC_KSXY: NUMY Mask */ + +#define CRPT_ECC_KSXY_RSSRCY_Pos (14) /*!< CRPT_T::ECC_KSXY: RSSRCY Position */ +#define CRPT_ECC_KSXY_RSSRCY_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCY_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCY Mask */ + +#define CRPT_RSA_KSCTL_NUM_Pos (0) /*!< CRPT_T::RSA_KSCTL: NUM Position */ +#define CRPT_RSA_KSCTL_NUM_Msk (0x1ful << CRPT_RSA_KSCTL_NUM_Pos) /*!< CRPT_T::RSA_KSCTL: NUM Mask */ + +#define CRPT_RSA_KSCTL_RSRC_Pos (5) /*!< CRPT_T::RSA_KSCTL: RSRC Position */ +#define CRPT_RSA_KSCTL_RSRC_Msk (0x1ul << CRPT_RSA_KSCTL_RSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSRC Mask */ + +#define CRPT_RSA_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::RSA_KSCTL: RSSRC Position */ +#define CRPT_RSA_KSCTL_RSSRC_Msk (0x3ul << CRPT_RSA_KSCTL_RSSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSSRC Mask */ + +#define CRPT_RSA_KSCTL_BKNUM_Pos (8) /*!< CRPT_T::RSA_KSCTL: BKNUM Position */ +#define CRPT_RSA_KSCTL_BKNUM_Msk (0x1ful << CRPT_RSA_KSCTL_BKNUM_Pos) /*!< CRPT_T::RSA_KSCTL: BKNUM Mask */ + +#define CRPT_RSA_KSSTS0_NUM0_Pos (0) /*!< CRPT_T::RSA_KSSTS0: NUM0 Position */ +#define CRPT_RSA_KSSTS0_NUM0_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM0_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM0 Mask */ + +#define CRPT_RSA_KSSTS0_NUM1_Pos (8) /*!< CRPT_T::RSA_KSSTS0: NUM1 Position */ +#define CRPT_RSA_KSSTS0_NUM1_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM1_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM1 Mask */ + +#define CRPT_RSA_KSSTS0_NUM2_Pos (16) /*!< CRPT_T::RSA_KSSTS0: NUM2 Position */ +#define CRPT_RSA_KSSTS0_NUM2_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM2_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM2 Mask */ + +#define CRPT_RSA_KSSTS0_NUM3_Pos (24) /*!< CRPT_T::RSA_KSSTS0: NUM3 Position */ +#define CRPT_RSA_KSSTS0_NUM3_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM3_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM3 Mask */ + +#define CRPT_RSA_KSSTS1_NUM4_Pos (0) /*!< CRPT_T::RSA_KSSTS1: NUM4 Position */ +#define CRPT_RSA_KSSTS1_NUM4_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM4_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM4 Mask */ + +#define CRPT_RSA_KSSTS1_NUM5_Pos (8) /*!< CRPT_T::RSA_KSSTS1: NUM5 Position */ +#define CRPT_RSA_KSSTS1_NUM5_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM5_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM5 Mask */ + +#define CRPT_RSA_KSSTS1_NUM6_Pos (16) /*!< CRPT_T::RSA_KSSTS1: NUM6 Position */ +#define CRPT_RSA_KSSTS1_NUM6_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM6_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM6 Mask */ + +#define CRPT_RSA_KSSTS1_NUM7_Pos (24) /*!< CRPT_T::RSA_KSSTS1: NUM7 Position */ +#define CRPT_RSA_KSSTS1_NUM7_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM7_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM7 Mask */ + +#define CRPT_VERSION_MINOR_Pos (0) /*!< CRPT_T::VERSION: MINOR Position */ +#define CRPT_VERSION_MINOR_Msk (0xfffful << CRPT_VERSION_MINOR_Pos) /*!< CRPT_T::VERSION: MINOR Mask */ + +#define CRPT_VERSION_SUB_Pos (16) /*!< CRPT_T::VERSION: SUB Position */ +#define CRPT_VERSION_SUB_Msk (0xfful << CRPT_VERSION_SUB_Pos) /*!< CRPT_T::VERSION: SUB Mask */ + +#define CRPT_VERSION_MAJOR_Pos (24) /*!< CRPT_T::VERSION: MAJOR Position */ +#define CRPT_VERSION_MAJOR_Msk (0xfful << CRPT_VERSION_MAJOR_Pos) /*!< CRPT_T::VERSION: MAJOR Mask */ + +/**@}*/ /* CRPT_CONST */ +/**@}*/ /* end of CRPT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __CRYPTO_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/dac_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/dac_reg.h new file mode 100644 index 0000000..7f3597b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/dac_reg.h @@ -0,0 +1,239 @@ +/**************************************************************************//** + * @file dac_reg.h + * @version V1.00 + * @brief DAC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DAC_REG_H__ +#define __DAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup DAC Digital to Analog Converter(DAC) + Memory Mapped Structure for DAC Controller +@{ */ + +typedef struct +{ + + + /** + * @var DAC_T::CTL + * Offset: 0x00 DAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DACEN |DAC Enable Bit + * | | |0 = DAC is Disabled. + * | | |1 = DAC is Enabled. + * |[1] |DACIEN |DAC Interrupt Enable Bit + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |DMAEN |DMA Mode Enable Bit + * | | |0 = DMA mode Disabled. + * | | |1 = DMA mode Enabled. + * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit + * | | |0 = DMA under-run interrupt Disabled. + * | | |1 = DMA under-run interrupt Enabled. + * |[4] |TRGEN |Trigger Mode Enable Bit + * | | |0 = DAC event trigger mode Disabled. + * | | |1 = DAC event trigger mode Enabled. + * |[7:5] |TRGSEL |Trigger Source Selection + * | | |000 = Software trigger. + * | | |001 = External pin DAC0_ST trigger. + * | | |010 = Timer 0 trigger. + * | | |011 = Timer 1 trigger. + * | | |100 = Timer 2 trigger. + * | | |101 = Timer 3 trigger. + * | | |110 = EPWM0 trigger. + * | | |111 = EPWM1 trigger. + * |[8] |BYPASS |Bypass Buffer Mode + * | | |0 = Output voltage buffer Enabled. + * | | |1 = Output voltage buffer Disabled. + * |[10] |LALIGN |DAC Data Left-aligned Enabled Control + * | | |0 = Right alignment. + * | | |1 = Left alignment. + * |[13:12] |ETRGSEL |External Pin Trigger Selection + * | | |00 = Low level trigger. + * | | |01 = High level trigger. + * | | |10 = Falling edge trigger. + * | | |11 = Rising edge trigger. + * |[15:14] |BWSEL |DAC Data Bit-width Selection + * | | |00 = data is 12 bits. + * | | |01 = data is 8 bits. + * | | |Others = reserved. + * |[16] |GRPEN |DAC Group Mode Enable Bit + * | | |0 = DAC0 and DAC1 are not grouped. + * | | |1 = DAC0 and DAC1 are grouped. + * @var DAC_T::SWTRG + * Offset: 0x04 DAC Software Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWTRG |Software Trigger + * | | |0 = Software trigger Disabled. + * | | |1 = Software trigger Enabled. + * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. + * @var DAC_T::DAT + * Offset: 0x08 DAC Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DACDAT |DAC 12-bit Holding Data + * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output + * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * @var DAC_T::DATOUT + * Offset: 0x0C DAC Data Output Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DATOUT |DAC 12-bit Output Data + * | | |These bits are current digital data for DAC output conversion. + * | | |It is loaded from DAC_DAT register and user cannot write it directly. + * @var DAC_T::STATUS + * Offset: 0x10 DAC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |DAC Conversion Complete Finish Flag + * | | |0 = DAC is in conversion state. + * | | |1 = DAC conversion finish. + * | | |This bit set to 1 when conversion time counter counts to SETTLET + * | | |It is cleared to 0 when DAC starts a new conversion + * | | |User writes 1 to clear this bit to 0. + * |[1] |DMAUDR |DMA Under-run Interrupt Flag + * | | |0 = No DMA under-run error condition occurred. + * | | |1 = DMA under-run error condition occurred. + * | | |User writes 1 to clear this bit. + * |[8] |BUSY |DAC Busy Flag (Read Only) + * | | |0 = DAC is ready for next conversion. + * | | |1 = DAC is busy in conversion. + * | | |This is read only bit. + * @var DAC_T::TCTL + * Offset: 0x14 DAC Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SETTLET |DAC Output Settling Time + * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. + * | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. + * | | |SELTTLET = DAC controller clock speed x settling time. + * @var DAC_T::GRPDAT + * Offset: 0x30 DAC Group Mode Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DAC0DAT |DAC0 12-bit Holding Data + * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output + * | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits. + * | | |Note: In group mode, user can write 12-bit conversion data for DAC0 in DAC_GRPDAT[15:0] or DAC0_DAT[15:0] + * | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[15:0] is that can share one PDMA transfer mechanism. + * | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs + * |[31:16] |DAC1DAT |DAC1 12-bit Holding Data + * | | |In group mode, user can write these bits for DAC1 12-bit conversion data + * | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits. + * | | |Note: In group mode, user can write 12-bit conversion data for DAC1 in DAC_GRPDAT[31:16] or DAC1_DAT[15:0] + * | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[31:16] is that can share one PDMA transfer mechanism. + * | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs + */ + __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ + __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ + __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ + __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ + __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ + __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ + __I uint32_t RESERVE0[6]; + __IO uint32_t GRPDAT; /*!< [0x0030] DAC Group Mode Data Holding Register */ + +} DAC_T; + +/** + @addtogroup DAC_CONST DAC Bit Field Definition + Constant Definitions for DAC Controller +@{ */ + +#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ +#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ + +#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ +#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ + +#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ +#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ + +#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ +#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ + +#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ +#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ + +#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ +#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ + +#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ +#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ + +#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ +#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ + +#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ +#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ + +#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ +#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ + +#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ +#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ + +#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ +#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ + +#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ +#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ + +#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ +#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ + +#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ +#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ + +#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ +#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ + +#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ +#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ + +#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ +#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ + +#define DAC_GRPDAT_DAC0DAT_Pos (0) /*!< DAC_T::GRPDAT: DAC0DAT Position */ +#define DAC_GRPDAT_DAC0DAT_Msk (0xfffful << DAC_GRPDAT_DAC0DAT_Pos) /*!< DAC_T::GRPDAT: DAC0DAT Mask */ + +#define DAC_GRPDAT_DAC1DAT_Pos (16) /*!< DAC_T::GRPDAT: DAC1DAT Position */ +#define DAC_GRPDAT_DAC1DAT_Msk (0xfffful << DAC_GRPDAT_DAC1DAT_Pos) /*!< DAC_T::GRPDAT: DAC1DAT Mask */ + +/**@}*/ /* DAC_CONST */ +/**@}*/ /* end of DAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __DAC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/eadc_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/eadc_reg.h new file mode 100644 index 0000000..a449df2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/eadc_reg.h @@ -0,0 +1,2390 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @version V1.00 + * @brief EADC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Enhanced Analog to Digital Converter -------------------------*/ +/** + @addtogroup EADC Enhanced Analog to Digital Converter(EADC) + Memory Mapped Structure for EADC Controller +@{ */ + +typedef struct +{ + + + /** + * @var EADC_T::DAT[19] + * Offset: 0x00 EADC Data Register 0~18 for Sample Module 0~18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |EADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |Note: When operating in oversampling mode, RESULT[15:0] can represent oversampling results. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |CURDAT |EADC PDMA Current Transfer Data (Read Only) + * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. + * @var EADC_T::CTL + * Offset: 0x50 EADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |EADC Converter Enable Bit + * | | |0 = EADC Disabled. + * | | |1 = EADC Enabled. + * | | |Note: Before starting EADC conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable EADC converter analog circuit power consumption. + * |[1] |ADCRST |EADC Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause EADC control circuits reset to initial state, but not change the EADC registers value. + * | | |Note: EADCRST bit remains 1 during EADC reset, when EADC reset end, the EADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module EADC ADINT0 Interrupt Enable Bit + * | | |The EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module EADC ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module EADC ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module EADC ADINT1 Interrupt Enable Bit + * | | |The EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion + * | | |If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module EADC ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module EADC ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module EADC ADINT2 Interrupt Enable Bit + * | | |The EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion + * | | |If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module EADC ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module EADC ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module EADC ADINT3 Interrupt Enable Bit + * | | |The EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion + * | | |If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module EADC ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module EADC ADINT3 interrupt function Enabled. + * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * | | |Note: In the differential mode, the input channel pair must be configured to EADC_CHx, EADC_CHx+1 , x=0,2,4,6,8,10,12,14. + * |[9] |DMOF |ADC Differential Input Mode Output Format + * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with unsigned format. + * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with 2'complement format. + * |[19:16] |INTDELAY0 |ADC Start Of Conversion ADINT0 Delay Cycle Selection + * | | |Start of conversion interrupt ADINT0 will delay INTDELAY0 PCLK cycles to generate interrupt + * | | |The function supports delay 1 PCLK to 15 PCLK cycles + * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. + * | | |4u2019h0 = No delay cycle. + * | | |4u2019h1 = Start of conversion interrupt ADINT0 delay 1 PCLK cycle. + * | | |4u2019h2 = Start of conversion interrupt ADINT0 delay 2 PCLK cycles. + * | | |4u2019h3 = Start of conversion interrupt ADINT0 delay 3 PCLK cycles. + * | | |4u2019h4 = Start of conversion interrupt ADINT0 delay 4 PCLK cycles. + * | | |4u2019h5 = Start of conversion interrupt ADINT0 delay 5 PCLK cycles. + * | | |4u2019h6 = Start of conversion interrupt ADINT0 delay 6 PCLK cycles. + * | | |4u2019h7 = Start of conversion interrupt ADINT0 delay 7 PCLK cycles. + * | | |4u2019h8 = Start of conversion interrupt ADINT0 delay 8 PCLK cycles. + * | | |4u2019h9 = Start of conversion interrupt ADINT0 delay 9 PCLK cycles. + * | | |4u2019ha = Start of conversion interrupt ADINT0 delay 10 PCLK cycles. + * | | |4u2019hb = Start of conversion interrupt ADINT0 delay 11 PCLK cycles. + * | | |4u2019hc = Start of conversion interrupt ADINT0 delay 12 PCLK cycles. + * | | |4u2019hd = Start of conversion interrupt ADINT0 delay 13 PCLK cycles. + * | | |4u2019he = Start of conversion interrupt ADINT0 delay 14 PCLK cycles. + * | | |4u2019hf = Start of conversion interrupt ADINT0 delay 15 PCLK cycles. + * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. + * | | |Note 2: It is noted that the delayed interrupt ADINT0 must occur before the next ADINT0 generated when using the same sample module to control EADC conversion. + * |[23:20] |INTDELAY1 |ADC Start Of Conversion ADINT1 Delay Cycle Selection + * | | |Start of conversion interrupt ADINT1 will delay INTDELAY1 PCLK cycles to generate interrupt + * | | |The function supports delay 1 PCLK to 15 PCLK cycles + * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. + * | | |4u2019h0 = No delay cycle. + * | | |4u2019h1 = Start of conversion interrupt ADINT1 delay 1 PCLK cycle. + * | | |4u2019h2 = Start of conversion interrupt ADINT1 delay 2 PCLK cycles. + * | | |4u2019h3 = Start of conversion interrupt ADINT1 delay 3 PCLK cycles. + * | | |4u2019h4 = Start of conversion interrupt ADINT1 delay 4 PCLK cycles. + * | | |4u2019h5 = Start of conversion interrupt ADINT1 delay 5 PCLK cycles. + * | | |4u2019h6 = Start of conversion interrupt ADINT1 delay 6 PCLK cycles. + * | | |4u2019h7 = Start of conversion interrupt ADINT1 delay 7 PCLK cycles. + * | | |4u2019h8 = Start of conversion interrupt ADINT1 delay 8 PCLK cycles. + * | | |4u2019h9 = Start of conversion interrupt ADINT1 delay 9 PCLK cycles. + * | | |4u2019ha = Start of conversion interrupt ADINT1 delay 10 PCLK cycles. + * | | |4u2019hb = Start of conversion interrupt ADINT1 delay 11 PCLK cycles. + * | | |4u2019hc = Start of conversion interrupt ADINT1 delay 12 PCLK cycles. + * | | |4u2019hd = Start of conversion interrupt ADINT1 delay 13 PCLK cycles. + * | | |4u2019he = Start of conversion interrupt ADINT1 delay 14 PCLK cycles. + * | | |4u2019hf = Start of conversion interrupt ADINT1 delay 15 PCLK cycles. + * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. + * | | |Note 2: It is noted that the delayed interrupt ADINT1 must occur before the next ADINT1 generated when using the same sample module to control EADC conversion. + * |[27:24] |INTDELAY2 |ADC Start Of Conversion ADINT2 Delay Cycle Selection + * | | |Start of conversion interrupt ADINT2 will delay INTDELAY2 PCLK cycles to generate interrupt + * | | |The function supports delay 1 PCLK to 15 PCLK cycles + * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. + * | | |4u2019h0 = No delay cycle. + * | | |4u2019h1 = Start of conversion interrupt ADINT2 delay 1 PCLK cycle. + * | | |4u2019h2 = Start of conversion interrupt ADINT2 delay 2 PCLK cycles. + * | | |4u2019h3 = Start of conversion interrupt ADINT2 delay 3 PCLK cycles. + * | | |4u2019h4 = Start of conversion interrupt ADINT2 delay 4 PCLK cycles. + * | | |4u2019h5 = Start of conversion interrupt ADINT2 delay 5 PCLK cycles. + * | | |4u2019h6 = Start of conversion interrupt ADINT2 delay 6 PCLK cycles. + * | | |4u2019h7 = Start of conversion interrupt ADINT2 delay 7 PCLK cycles. + * | | |4u2019h8 = Start of conversion interrupt ADINT2 delay 8 PCLK cycles. + * | | |4u2019h9 = Start of conversion interrupt ADINT2 delay 9 PCLK cycles. + * | | |4u2019ha = Start of conversion interrupt ADINT2 delay 10 PCLK cycles. + * | | |4u2019hb = Start of conversion interrupt ADINT2 delay 11 PCLK cycles. + * | | |4u2019hc = Start of conversion interrupt ADINT2 delay 12 PCLK cycles. + * | | |4u2019hd = Start of conversion interrupt ADINT2 delay 13 PCLK cycles. + * | | |4u2019he = Start of conversion interrupt ADINT2 delay 14 PCLK cycles. + * | | |4u2019hf = Start of conversion interrupt ADINT2 delay 15 PCLK cycles. + * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. + * | | |Note 2: It is noted that the delayed interrupt ADINT2 must occur before the next ADINT2 generated when using the same sample module to control EADC conversion. + * |[31:28] |INTDELAY3 |ADC Start Of Conversion ADINT3 Delay Cycle Selection + * | | |Start of conversion interrupt ADINT3 will delay INTDELAY3 PCLK cycles to generate interrupt + * | | |The function supports delay 1 PCLK to 15 PCLK cycles + * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. + * | | |4u2019h0 = No delay cycle. + * | | |4u2019h1 = Start of conversion interrupt ADINT3 delay 1 PCLK cycle. + * | | |4u2019h2 = Start of conversion interrupt ADINT3 delay 2 PCLK cycles. + * | | |4u2019h3 = Start of conversion interrupt ADINT3 delay 3 PCLK cycles. + * | | |4u2019h4 = Start of conversion interrupt ADINT3 delay 4 PCLK cycles. + * | | |4u2019h5 = Start of conversion interrupt ADINT3 delay 5 PCLK cycles. + * | | |4u2019h6 = Start of conversion interrupt ADINT3 delay 6 PCLK cycles. + * | | |4u2019h7 = Start of conversion interrupt ADINT3 delay 7 PCLK cycles. + * | | |4u2019h8 = Start of conversion interrupt ADINT3 delay 8 PCLK cycles. + * | | |4u2019h9 = Start of conversion interrupt ADINT3 delay 9 PCLK cycles. + * | | |4u2019ha = Start of conversion interrupt ADINT3 delay 10 PCLK cycles. + * | | |4u2019hb = Start of conversion interrupt ADINT3 delay 11 PCLK cycles. + * | | |4u2019hc = Start of conversion interrupt ADINT3 delay 12 PCLK cycles. + * | | |4u2019hd = Start of conversion interrupt ADINT3 delay 13 PCLK cycles. + * | | |4u2019he = Start of conversion interrupt ADINT3 delay 14 PCLK cycles. + * | | |4u2019hf = Start of conversion interrupt ADINT3 delay 15 PCLK cycles. + * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. + * | | |Note 2: It is noted that the delayed interrupt ADINT3 must occur before the next ADINT3 generated when using the same sample module to control EADC conversion. + * @var EADC_T::SWTRG + * Offset: 0x54 ADC Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SWTRG |EADC Sample Module 0~18 Software Force to Start EADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an EADC conversion when the priority is given to sample module. + * | | |Note: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 EADC Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |STPF |EADC Sample Module 0~18 Start of Conversion Pending Flag + * | | |Read Operation: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module EADC start of conversion is pending. + * | | |Write Operation: + * | | |1 = Clear pending flag & cancel the conversion for sample module. + * | | |Note: This bit remains 1 during pending state when the respective EADC conversion is ended + * | | |The STPFn (n=0~18) bit is automatically cleared to 0 + * @var EADC_T::OVSTS + * Offset: 0x5C EADC Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SPOVF |EADC SAMPLE0~18 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::CTL1 + * Offset: 0x60 EADC Control1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:4] |RESSEL |Resolution Select Bits + * | | |00 = ADC resolution 12 bits. + * | | |01 = ADC resolution 10 bits. + * | | |10 = ADC resolution 8 bits. + * | | |11 = Reserved. + * |[12] |ULPEN |Ultra Low Power Mode Enable Bit + * | | |0 = Ultra low power mode Disabled. + * | | |1 = Ultra low power mode Enabled. + * |[15:13] |ULPDIV |Ultra Low Power Mode Prescalar selection + * | | |000= ADC_CLK divided by 1. + * | | |001= ADC_CLK divided by 2. + * | | |010= ADC_CLK divided by 4. + * | | |011= ADC_CLK divided by 8. + * | | |100= ADC_CLK divided by 16. + * | | |Others = Reserved. + * | | |Note: the function is for internal used, itu2019s not complete function + * | | |Note: user set ULPEN and ULPDIV will get divided ADC_CLK only. The conversion time is still the same + * |[16] |DECSET |High Speed Oversampling Mode Enable Bit + * | | |0 = High speed oversampling mode Disabled. + * | | |1 = High speed oversampling mode Enabled. + * | | |Note: these bits is for analog RD used + * |[20] |CMP0TRG |ADC Comparator 0 Trigger EPWM Brake Enable Bit + * | | |0 = Comparator 0 trigger EPWM brake Disabled. + * | | |1 = Comparator 0 trigger EPWM brake Enabled. + * |[21] |CMP1TRG |ADC Comparator 1 Trigger EPWM Brake Enable Bit + * | | |0 = Comparator 1 trigger EPWM brake Disabled. + * | | |1 = Comparator 1 trigger EPWM brake Enabled. + * |[22] |CMP2TRG |ADC Comparator 2 Trigger EPWM Brake Enable Bit + * | | |0 = Comparator 2 trigger EPWM brake Disabled. + * | | |1 = Comparator 2 trigger EPWM brake Enabled. + * |[23] |CMP3TRG |ADC Comparator 3 Trigger EPWM Brake Enable Bit + * | | |0 = Comparator 3 trigger EPWM brake Disabled. + * | | |1 = Comparator 3 trigger EPWM brake Enabled. + * |[31:24] |OSR |Repeat Conversion Times Select + * | | |8u2019b00000000 = ADC converts for 1 time. + * | | |8u2019b00000001 = ADC converts for 2 times. + * | | |8u2019b00000010 = ADC converts for 3 times. + * | | |8u2019b00000011 = ADC converts for 4 times. + * | | |8u2019b00000100 = ADC converts for 5 times. + * | | |uFF1A + * | | |uFF1A + * | | |uFF1A + * | | |8u2019b11111101 = ADC converts for 254 times. + * | | |8u2019b11111110 = ADC converts for 255 times. + * | | |Note: The other steps of selection not listed above follow the same rule. + * | | |Note: these bits is for analog RD used + * @var EADC_T::SCTL[19] + * Offset: 0x80 EADC Sample Module 0~18 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CHSEL |EADC Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * |[5] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion. + * |[7:6] |TRGDLYDIV |EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = EADC_CLK/1. + * | | |01 = EADC_CLK/2. + * | | |10 = EADC_CLK/4. + * | | |11 = EADC_CLK/16. + * |[15:8] |TRGDLYCNT |EADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x EADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). + * |[20:16] |TRGSEL |EADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = EADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = EADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = EPWM0TG0. + * | | |9H = EPWM0TG1. + * | | |AH = EPWM0TG2. + * | | |BH = EPWM0TG3. + * | | |CH = EPWM0TG4. + * | | |DH = EPWM0TG5. + * | | |EH = EPWM1TG0. + * | | |FH = EPWM1TG1. + * | | |10H = EPWM1TG2. + * | | |11H = EPWM1TG3. + * | | |12H = EPWM1TG4. + * | | |13H = EPWM1TG5. + * | | |14H = BPWM0TG. + * | | |15H = BPWM1TG. + * | | |other = Reserved. + * |[21] |EXTREN |EADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when EADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when EADC selects EADC0_ST as trigger source. + * |[22] |EXTFEN |EADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when EADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when EADC selects EADC0_ST as trigger source. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register (default). + * | | |1 = Sample has two sample result registers. + * |[31:24] |EXTSMPT |EADC Sampling Time Extend + * | | |When EADC converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and user can extend EADC sampling time after trigger source is coming to get enough sampling time. + * | | |The range of start delay time is from 0~255 EADC clock. + * @var EADC_T::INTSRC[4] + * Offset: 0xD0 EADC interrupt 0~3 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit + * | | |0 = Sample Module 9 interrupt Disabled. + * | | |1 = Sample Module 9 interrupt Enabled. + * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit + * | | |0 = Sample Module 10 interrupt Disabled. + * | | |1 = Sample Module 10 interrupt Enabled. + * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit + * | | |0 = Sample Module 11 interrupt Disabled. + * | | |1 = Sample Module 11 interrupt Enabled. + * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit + * | | |0 = Sample Module 12 interrupt Disabled. + * | | |1 = Sample Module 12 interrupt Enabled. + * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit + * | | |0 = Sample Module 13 interrupt Disabled. + * | | |1 = Sample Module 13 interrupt Enabled. + * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit + * | | |0 = Sample Module 14 interrupt Disabled. + * | | |1 = Sample Module 14 interrupt Enabled. + * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit + * | | |0 = Sample Module 15 interrupt Disabled. + * | | |1 = Sample Module 15 interrupt Enabled. + * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit + * | | |0 = Sample Module 16 interrupt Disabled. + * | | |1 = Sample Module 16 interrupt Enabled. + * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit + * | | |0 = Sample Module 17 interrupt Disabled. + * | | |1 = Sample Module 17 interrupt Enabled. + * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit + * | | |0 = Sample Module 18 interrupt Disabled. + * | | |1 = Sample Module 18 interrupt Enabled. + * @var EADC_T::CMP[4] + * Offset: 0xE0 ADC Result Compare Register 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |EADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |EADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit EADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit EADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[7:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. + * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. + * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. + * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. + * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. + * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. + * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. + * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. + * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. + * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. + * | | |Others = reserved. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * | | |Note: When in compare window mode, the CMPCNT setting only follow EADC_CMP0, EADC_CMP2 registers + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 EADC Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module EADC result data register EADC_DATn. (n=0~15). + * |[31:16] |OV |EADC_DAT0~15 Overrun Flag + * | | |It is a mirror to OV bit in sample module EADC result data register EADC_DATn. (n=0~15). + * @var EADC_T::STATUS1 + * Offset: 0xF4 EADC Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module EADC result data register EADC_DATn. (n=16~18). + * |[18:16] |OV |EADC_DAT16~18 Overrun Flag + * | | |It is a mirror to OV bit in sample module EADC result data register EADC_DATn. (n=16~18). + * @var EADC_T::STATUS2 + * Offset: 0xF8 EADC Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |EADC ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed + * |[1] |ADIF1 |EADC ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed + * |[2] |ADIF2 |EADC ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed + * |[3] |ADIF3 |EADC ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed + * |[4] |ADCMPF0 |EADC Compare 0 Flag + * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |EADC Compare 1 Flag + * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |EADC Compare 2 Flag + * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |EADC Compare 3 Flag + * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |EADC ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |EADC ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |EADC ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is s overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |EADC ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |EADC Compare 0 Output Status (Read Only) + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. + * |[13] |ADCMPO1 |EADC Compare 1 Output Status (Read Only) + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT1 setting. + * |[14] |ADCMPO2 |EADC Compare 2 Output Status (Read Only) + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT2 setting. + * |[15] |ADCMPO3 |EADC Compare 3 Output Status (Read Only) + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) + * | | |This filed reflects EADC current conversion channel when BUSY=1. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |10H = VBG. + * | | |11H = VTEMP. + * | | |12H = DAC0_OUT. + * |[23] |BUSY |Busy/Idle (Read Only) + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy at conversion. + * | | |Note: This flag will be high after 4*EADC_CLK cycles when the trigger source is coming. + * |[24] |ADOVIF |All EADC Interrupt Flag Overrun Bits Check (Read Only) + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. + * |[26] |AVALID |for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. + * |[27] |AOV |for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC EADC Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |EADC Current Sample Module (Read Only) + * | | |This register shows the current EADC is controlled by which sample module control logic modules. + * | | |If the EADC is Idle, the bit filed will be set to 0x1F. + * @var EADC_T::DDAT[4] + * Offset: 0x100 EADC Double Data Register 0 for Sample Module 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |EADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |The 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is overwrite. + * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read + * | | |(n=0~3). + * @var EADC_T::CALCTL + * Offset: 0x114 EADC Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAL |Calibration Enable Bit + * | | |0 = = Calibration Disabled. + * | | |1 = = Calibration Enabled. + * | | |Note: This bit is hardware auto cleared when calibration is done + * |[1] |CALIE |Calibration Interrupt Enable Bit + * | | |0 = Calibration interrupt Disabled. + * | | |1= Calibration interrupt Enabled. + * |[2] |CALWR |Calibration Write Operation Bit for debug mode + * | | |0 = none. + * | | |1 = do calibration write operation. + * | | |Note: writing 1 to this bit can write CALWDATA to corresponding address CALADDR. + * | | |Note: this bit is hardware cleared + * |[3] |CALRD |Calibration Read Operation Bit for debug mode + * | | |0 = none. + * | | |1 = do calibration read operation. + * |[4] |OUTSEL |Calibration Output Mode Selection + * |[5] |CALSEL16T |Calibration Select Times Bit + * | | |0 = Calibration 1 times. + * | | |1 = Calibration 16 times (default). + * | | |Note: CALSEL16T shoule keep value = 1 before doing calibration. + * |[12:8] |CALADDR |Calibration Data Address + * | | |Calibration Data address in the calibration circuit, write CALADDR and corresponding sw write CALWDATA will store into the CALADDR. + * |[19:16] |CALSEL |Calibration Select Bits + * | | |0 = Calibrate offset.1. + * | | |1 = Calibrate MSB. + * | | |2 = Calibrate MSB-1. + * | | |3 = Calibrate MSB-2. + * | | |4 = Calibrate MSB-3. + * | | |5 = Calibrate MSB-4. + * | | |6 = Reserved. + * | | |7 = Calibrate offset.1. + * | | |Others = reserved. + * |[31:24] |CALWRDATA |Calibration Write Data + * | | |SW write 8-bit data into the calibration circuit to debug R/W + * @var EADC_T::CALSR + * Offset: 0x118 EADC Calibration Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CALRDATA |Calibration Read Data + * | | |Read CALRDATA (EADC_CALSR[11:0]) will get CALWRDATA (EADC_CALCTL[31:24]) in the corresponding CALADDR setting . + * | | |Note: CALRDATA is read only + * | | |Note: when perform read operation, CALADDR, OUTSEL setting must be the same when perform write operation + * |[16] |CALIF |Calibration Finish Interrupt Flag + * | | |If calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it. + * @var EADC_T::PDMACTL + * Offset: 0x130 EADC PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |PDMATEN |PDMA Transfer Enable Bit + * | | |When EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer Enabled. + * | | |Note:When setting this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * @var EADC_T::M0CTL1 + * Offset: 0x140 EADC Sample Module0 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M1CTL1 + * Offset: 0x144 EADC Sample Module1 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M2CTL1 + * Offset: 0x148 EADC Sample Module2 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M3CTL1 + * Offset: 0x14C EADC Sample Module3 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M4CTL1 + * Offset: 0x150 EADC Sample Module4 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M5CTL1 + * Offset: 0x154 EADC Sample Module5 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M6CTL1 + * Offset: 0x158 EADC Sample Module6 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M7CTL1 + * Offset: 0x15C EADC Sample Module7 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M8CTL1 + * Offset: 0x160 EADC Sample Module8 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M9CTL1 + * Offset: 0x164 EADC Sample Module9 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M10CTL1 + * Offset: 0x168 EADC Sample Module10 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M11CTL1 + * Offset: 0x16C EADC Sample Module11 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M12CTL1 + * Offset: 0x170 EADC Sample Module12 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M13CTL1 + * Offset: 0x174 EADC Sample Module13 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M14CTL1 + * Offset: 0x178 EADC Sample Module14 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + * @var EADC_T::M15CTL1 + * Offset: 0x17C EADC Sample Module15 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0000 = 1 conversion result will be accumulated. + * | | |0001 = 2 conversion result will be accumulated. + * | | |0010 = 4 conversion result will be accumulated. + * | | |0011 = 8 conversion result will be accumulated. + * | | |0100 = 16 conversion result will be accumulated. + * | | |0101 = 32 conversion result will be accumulated. + * | | |0110 = 64 conversion result will be accumulated. + * | | |0111 = 128 conversion result will be accumulated. + * | | |1000 = 256 conversion result will be accumulated. + * | | |Others = Reserved. + */ + __I uint32_t DAT[19]; /*!< [0x0000] EADC Data Register 0~18 for Sample Module 0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] EADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] EADC Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] EADC Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] EADC Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] EADC Sample Module Start of Conversion Overrun Flag Register */ + __IO uint32_t CTL1; /*!< [0x0060] EADC Control1 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[7]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SCTL[19]; /*!< [0x0080] EADC Sample Module 0~18 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t INTSRC[4]; /*!< [0x00d0] EADC interrupt 0~3 Source Enable Control Register. */ + __IO uint32_t CMP[4]; /*!< [0x00e0] EADC Result Compare Register 0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] EADC Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] EADC Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] EADC Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] EADC Status Register 3 */ + __I uint32_t DDAT[4]; /*!< [0x0100] EADC Double Data Register 0~3 for Sample Module 0~3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CALCTL; /*!< [0x0114] EADC Calibration Control Register */ + __IO uint32_t CALSR; /*!< [0x0118] EADC Calibration Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PDMACTL; /*!< [0x0130] EADC PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t MCTL1[15]; /*!< [0x0140 - 0x017c] EADC Sample Module 0~15 Control Register */ +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller +@{ */ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ + +#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ +#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ + +#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ +#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ + +#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ +#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ + +#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ +#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ + +#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ +#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ + +#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ +#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ + +#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ +#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ + +#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ +#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ + +#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ +#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ + +#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ +#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ + +#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ +#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ + +#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ +#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ + +#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ +#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ + +#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ +#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ + +#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ +#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ + +#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ +#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ + +#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ +#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ + +#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ +#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ + +#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ +#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ + +#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ +#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ + +#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ +#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ + +#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ +#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ + +#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ +#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ + +#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ +#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ + +#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ +#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ + +#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ +#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ + +#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ +#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ + +#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ +#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ + +#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ +#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ + +#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ +#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ + +#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ +#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ + +#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ +#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ + +#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ +#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ + +#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ +#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ + +#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ +#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ + +#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ +#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ + +#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ +#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ + +#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ +#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ + +#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ +#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ + +#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ +#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ + +#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ +#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ + +#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ +#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ + +#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ +#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ + +#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ +#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ + +#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ +#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ + +#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ +#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ + +#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ +#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ + +#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ +#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ + +#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ +#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ + +#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ +#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ + +#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ +#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ + +#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ +#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ + +#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ +#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ + +#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ +#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ + +#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ +#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ + +#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ +#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ + +#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ +#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x7fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ +#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ + +#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ +#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ + +#define EADC_CTL_INTDELAY0_Pos (16) /*!< EADC_T::CTL: INTDELAY0 Position */ +#define EADC_CTL_INTDELAY0_Msk (0xful << EADC_CTL_INTDELAY0_Pos) /*!< EADC_T::CTL: INTDELAY0 Mask */ + +#define EADC_CTL_INTDELAY1_Pos (20) /*!< EADC_T::CTL: INTDELAY1 Position */ +#define EADC_CTL_INTDELAY1_Msk (0xful << EADC_CTL_INTDELAY1_Pos) /*!< EADC_T::CTL: INTDELAY1 Mask */ + +#define EADC_CTL_INTDELAY2_Pos (24) /*!< EADC_T::CTL: INTDELAY2 Position */ +#define EADC_CTL_INTDELAY2_Msk (0xful << EADC_CTL_INTDELAY2_Pos) /*!< EADC_T::CTL: INTDELAY2 Mask */ + +#define EADC_CTL_INTDELAY3_Pos (28) /*!< EADC_T::CTL: INTDELAY3 Position */ +#define EADC_CTL_INTDELAY3_Msk (0xful << EADC_CTL_INTDELAY3_Pos) /*!< EADC_T::CTL: INTDELAY3 Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_CTL1_RESSEL_Pos (4) /*!< EADC_T::CTL1: RESSEL Position */ +#define EADC_CTL1_RESSEL_Msk (0x3ul << EADC_CTL1_RESSEL_Pos) /*!< EADC_T::CTL1: RESSEL Mask */ + +#define EADC_CTL1_CMP0TRG_Pos (20) /*!< EADC_T::CTL1: CMP0TRG Position */ +#define EADC_CTL1_CMP0TRG_Msk (0x1ul << EADC_CTL1_CMP0TRG_Pos) /*!< EADC_T::CTL1: CMP0TRG Mask */ + +#define EADC_CTL1_CMP1TRG_Pos (21) /*!< EADC_T::CTL1: CMP1TRG Position */ +#define EADC_CTL1_CMP1TRG_Msk (0x1ul << EADC_CTL1_CMP1TRG_Pos) /*!< EADC_T::CTL1: CMP1TRG Mask */ + +#define EADC_CTL1_CMP2TRG_Pos (22) /*!< EADC_T::CTL1: CMP2TRG Position */ +#define EADC_CTL1_CMP2TRG_Msk (0x1ul << EADC_CTL1_CMP2TRG_Pos) /*!< EADC_T::CTL1: CMP2TRG Mask */ + +#define EADC_CTL1_CMP3TRG_Pos (23) /*!< EADC_T::CTL1: CMP3TRG Position */ +#define EADC_CTL1_CMP3TRG_Msk (0x1ul << EADC_CTL1_CMP3TRG_Pos) /*!< EADC_T::CTL1: CMP3TRG Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0x1ful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (5) /*!< EADC_T::SCTL: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (21) /*!< EADC_T::SCTL: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (22) /*!< EADC_T::SCTL: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ + +#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ +#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ + +#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ +#define EADC_SCTL0_CHSEL_Msk (0x1ful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ + +#define EADC_SCTL0_INTPOS_Pos (5) /*!< EADC_T::SCTL0: INTPOS Position */ +#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ + +#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ +#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ + +#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ +#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ + +#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ +#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ + +#define EADC_SCTL0_EXTREN_Pos (21) /*!< EADC_T::SCTL0: EXTREN Position */ +#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ + +#define EADC_SCTL0_EXTFEN_Pos (22) /*!< EADC_T::SCTL0: EXTFEN Position */ +#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ + +#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ +#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ + +#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ +#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ + +#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ +#define EADC_SCTL1_CHSEL_Msk (0x1ful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ + +#define EADC_SCTL1_INTPOS_Pos (5) /*!< EADC_T::SCTL1: INTPOS Position */ +#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ + +#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ +#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ + +#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ +#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ + +#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ +#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ + +#define EADC_SCTL1_EXTREN_Pos (21) /*!< EADC_T::SCTL1: EXTREN Position */ +#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ + +#define EADC_SCTL1_EXTFEN_Pos (22) /*!< EADC_T::SCTL1: EXTFEN Position */ +#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ + +#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ +#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ + +#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ +#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ + +#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ +#define EADC_SCTL2_CHSEL_Msk (0x1ful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ + +#define EADC_SCTL2_INTPOS_Pos (5) /*!< EADC_T::SCTL2: INTPOS Position */ +#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ + +#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ +#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ + +#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ +#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ + +#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ +#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ + +#define EADC_SCTL2_EXTREN_Pos (21) /*!< EADC_T::SCTL2: EXTREN Position */ +#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ + +#define EADC_SCTL2_EXTFEN_Pos (22) /*!< EADC_T::SCTL2: EXTFEN Position */ +#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ + +#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ +#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ + +#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ +#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ + +#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ +#define EADC_SCTL3_CHSEL_Msk (0x1ful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ + +#define EADC_SCTL3_INTPOS_Pos (5) /*!< EADC_T::SCTL3: INTPOS Position */ +#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ + +#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ +#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ + +#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ +#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ + +#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ +#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ + +#define EADC_SCTL3_EXTREN_Pos (21) /*!< EADC_T::SCTL3: EXTREN Position */ +#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ + +#define EADC_SCTL3_EXTFEN_Pos (22) /*!< EADC_T::SCTL3: EXTFEN Position */ +#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ + +#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ +#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ + +#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ +#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ + +#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ +#define EADC_SCTL4_CHSEL_Msk (0x1ful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ + +#define EADC_SCTL4_INTPOS_Pos (5) /*!< EADC_T::SCTL4: INTPOS Position */ +#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ + +#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ +#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ + +#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ +#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ + +#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ +#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ + +#define EADC_SCTL4_EXTREN_Pos (21) /*!< EADC_T::SCTL4: EXTREN Position */ +#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ + +#define EADC_SCTL4_EXTFEN_Pos (22) /*!< EADC_T::SCTL4: EXTFEN Position */ +#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ + +#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ +#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ + +#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ +#define EADC_SCTL5_CHSEL_Msk (0x1ful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ + +#define EADC_SCTL5_INTPOS_Pos (5) /*!< EADC_T::SCTL5: INTPOS Position */ +#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ + +#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ +#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ + +#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ +#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ + +#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ +#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ + +#define EADC_SCTL5_EXTREN_Pos (21) /*!< EADC_T::SCTL5: EXTREN Position */ +#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ + +#define EADC_SCTL5_EXTFEN_Pos (22) /*!< EADC_T::SCTL5: EXTFEN Position */ +#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ + +#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ +#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ + +#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ +#define EADC_SCTL6_CHSEL_Msk (0x1ful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ + +#define EADC_SCTL6_INTPOS_Pos (5) /*!< EADC_T::SCTL6: INTPOS Position */ +#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ + +#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ +#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ + +#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ +#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ + +#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ +#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ + +#define EADC_SCTL6_EXTREN_Pos (21) /*!< EADC_T::SCTL6: EXTREN Position */ +#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ + +#define EADC_SCTL6_EXTFEN_Pos (22) /*!< EADC_T::SCTL6: EXTFEN Position */ +#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ + +#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ +#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ + +#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ +#define EADC_SCTL7_CHSEL_Msk (0x1ful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ + +#define EADC_SCTL7_INTPOS_Pos (5) /*!< EADC_T::SCTL7: INTPOS Position */ +#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ + +#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ +#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ + +#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ +#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ + +#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ +#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ + +#define EADC_SCTL7_EXTREN_Pos (21) /*!< EADC_T::SCTL7: EXTREN Position */ +#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ + +#define EADC_SCTL7_EXTFEN_Pos (22) /*!< EADC_T::SCTL7: EXTFEN Position */ +#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ + +#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ +#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ + +#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ +#define EADC_SCTL8_CHSEL_Msk (0x1ful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ + +#define EADC_SCTL8_INTPOS_Pos (5) /*!< EADC_T::SCTL8: INTPOS Position */ +#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ + +#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ +#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ + +#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ +#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ + +#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ +#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ + +#define EADC_SCTL8_EXTREN_Pos (21) /*!< EADC_T::SCTL8: EXTREN Position */ +#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ + +#define EADC_SCTL8_EXTFEN_Pos (22) /*!< EADC_T::SCTL8: EXTFEN Position */ +#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ + +#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ +#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ + +#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ +#define EADC_SCTL9_CHSEL_Msk (0x1ful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ + +#define EADC_SCTL9_INTPOS_Pos (5) /*!< EADC_T::SCTL9: INTPOS Position */ +#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ + +#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ +#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ + +#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ +#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ + +#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ +#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ + +#define EADC_SCTL9_EXTREN_Pos (21) /*!< EADC_T::SCTL9: EXTREN Position */ +#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ + +#define EADC_SCTL9_EXTFEN_Pos (22) /*!< EADC_T::SCTL9: EXTFEN Position */ +#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ + +#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ +#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ + +#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ +#define EADC_SCTL10_CHSEL_Msk (0x1ful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ + +#define EADC_SCTL10_INTPOS_Pos (5) /*!< EADC_T::SCTL10: INTPOS Position */ +#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ + +#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ +#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ + +#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ +#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ + +#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ +#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ + +#define EADC_SCTL10_EXTREN_Pos (21) /*!< EADC_T::SCTL10: EXTREN Position */ +#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ + +#define EADC_SCTL10_EXTFEN_Pos (22) /*!< EADC_T::SCTL10: EXTFEN Position */ +#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ + +#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ +#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ + +#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ +#define EADC_SCTL11_CHSEL_Msk (0x1ful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ + +#define EADC_SCTL11_INTPOS_Pos (5) /*!< EADC_T::SCTL11: INTPOS Position */ +#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ + +#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ +#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ + +#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ +#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ + +#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ +#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ + +#define EADC_SCTL11_EXTREN_Pos (21) /*!< EADC_T::SCTL11: EXTREN Position */ +#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ + +#define EADC_SCTL11_EXTFEN_Pos (22) /*!< EADC_T::SCTL11: EXTFEN Position */ +#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ + +#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ +#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ + +#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ +#define EADC_SCTL12_CHSEL_Msk (0x1ful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ + +#define EADC_SCTL12_INTPOS_Pos (5) /*!< EADC_T::SCTL12: INTPOS Position */ +#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ + +#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ +#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ + +#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ +#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ + +#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ +#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ + +#define EADC_SCTL12_EXTREN_Pos (21) /*!< EADC_T::SCTL12: EXTREN Position */ +#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ + +#define EADC_SCTL12_EXTFEN_Pos (22) /*!< EADC_T::SCTL12: EXTFEN Position */ +#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ + +#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ +#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ + +#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ +#define EADC_SCTL13_CHSEL_Msk (0x1ful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ + +#define EADC_SCTL13_INTPOS_Pos (5) /*!< EADC_T::SCTL13: INTPOS Position */ +#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ + +#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ +#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ + +#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ +#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ + +#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ +#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ + +#define EADC_SCTL13_EXTREN_Pos (21) /*!< EADC_T::SCTL13: EXTREN Position */ +#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ + +#define EADC_SCTL13_EXTFEN_Pos (22) /*!< EADC_T::SCTL13: EXTFEN Position */ +#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ + +#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ +#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ + +#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ +#define EADC_SCTL14_CHSEL_Msk (0x1ful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ + +#define EADC_SCTL14_INTPOS_Pos (5) /*!< EADC_T::SCTL14: INTPOS Position */ +#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ + +#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ +#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ + +#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ +#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ + +#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ +#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ + +#define EADC_SCTL14_EXTREN_Pos (21) /*!< EADC_T::SCTL14: EXTREN Position */ +#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ + +#define EADC_SCTL14_EXTFEN_Pos (22) /*!< EADC_T::SCTL14: EXTFEN Position */ +#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ + +#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ +#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ + +#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ +#define EADC_SCTL15_CHSEL_Msk (0x1ful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ + +#define EADC_SCTL15_INTPOS_Pos (5) /*!< EADC_T::SCTL15: INTPOS Position */ +#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ + +#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ +#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ + +#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ +#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ + +#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ +#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ + +#define EADC_SCTL15_EXTREN_Pos (21) /*!< EADC_T::SCTL15: EXTREN Position */ +#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ + +#define EADC_SCTL15_EXTFEN_Pos (22) /*!< EADC_T::SCTL15: EXTFEN Position */ +#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ + +#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ +#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ + +#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ +#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ + +#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ +#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ + +#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ +#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ + +#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ +#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ + +#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ +#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ + +#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ +#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ + +#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ +#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ + +#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ +#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ + +#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ +#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ + +#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ +#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ + +#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ +#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ + +#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ +#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ + +#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ +#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ + +#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ +#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ + +#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ +#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ + +#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ +#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ + +#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ +#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ + +#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ +#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ + +#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ +#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ + +#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ +#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ + +#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ +#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ + +#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ +#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ + +#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ +#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ + +#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ +#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ + +#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ +#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ + +#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ +#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ + +#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ +#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ + +#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ +#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ + +#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ +#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ + +#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ +#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ + +#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ +#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ + +#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ +#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ + +#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ +#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ + +#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ +#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ + +#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ +#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ + +#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ +#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ + +#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ +#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ + +#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ +#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ + +#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ +#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ + +#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ +#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ + +#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ +#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ + +#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ +#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ + +#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ +#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ + +#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ +#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ + +#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ +#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ + +#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ +#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ + +#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ +#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ + +#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ +#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ + +#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ +#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ + +#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ +#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ + +#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ +#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ + +#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ +#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ + +#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ +#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ + +#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ +#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ + +#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ +#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ + +#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ +#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ + +#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ +#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ + +#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ +#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ + +#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ +#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ + +#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ +#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ + +#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ +#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ + +#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ +#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ + +#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ +#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ + +#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ +#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ + +#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ +#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ + +#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ +#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ + +#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ +#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ + +#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ +#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ + +#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ +#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ + +#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ +#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ + +#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ +#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ + +#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ +#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ + +#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ +#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ + +#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ +#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ + +#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ +#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ + +#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ +#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ + +#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ +#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ + +#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ +#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ + +#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ +#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ + +#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ +#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ + +#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ +#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ + +#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ +#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ + +#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ +#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ + +#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ +#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ + +#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ +#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ + +#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ +#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ + +#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ +#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ + +#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ +#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ + +#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ +#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ + +#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ +#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ + +#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ +#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ + +#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ +#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ + +#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ +#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ + +#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ +#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ + +#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ +#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ + +#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ +#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ + +#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ +#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ + +#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ +#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ + +#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ +#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ + +#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ +#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ + +#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ +#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ + +#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ +#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ + +#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ +#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ + +#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ +#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ + +#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ +#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ + +#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ +#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ + +#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ +#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ +#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ + +#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ +#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ +#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ + +#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ +#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ + +#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ +#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ + +#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ +#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ + +#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ +#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ + +#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ +#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ + +#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ +#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ + +#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ +#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ + +#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ +#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ + +#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ +#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ + +#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ +#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ + +#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ +#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ + +#define EADC_CALCTL_CAL_Pos (0) /*!< EADC_T::CALCTL: CAL Position */ +#define EADC_CALCTL_CAL_Msk (0x1ul << EADC_CALCTL_CAL_Pos) /*!< EADC_T::CALCTL: CAL Mask */ + +#define EADC_CALCTL_CALIE_Pos (1) /*!< EADC_T::CALCTL: CALIE Position */ +#define EADC_CALCTL_CALIE_Msk (0x1ul << EADC_CALCTL_CALIE_Pos) /*!< EADC_T::CALCTL: CALIE Mask */ + +#define EADC_CALSR_CALIF_Pos (16) /*!< EADC_T::CALSR: CALIF Position */ +#define EADC_CALSR_CALIF_Msk (0x1ul << EADC_CALSR_CALIF_Pos) /*!< EADC_T::CALSR: CALIF Mask */ + +#define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ +#define EADC_PDMACTL_PDMATEN_Msk (0x7fffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ + +#define EADC_MCTL1_ALIGN_Pos (0) /*!< EADC_T::MCTL1: ALIGN Position */ +#define EADC_MCTL1_ALIGN_Msk (0x1ul << EADC_MCTL1_ALIGN_Pos) /*!< EADC_T::MCTL1: ALIGN Mask */ + +#define EADC_MCTL1_AVG_Pos (1) /*!< EADC_T::MCTL1: AVG Position */ +#define EADC_MCTL1_AVG_Msk (0x1ul << EADC_MCTL1_AVG_Pos) /*!< EADC_T::MCTL1: AVG Mask */ + +#define EADC_MCTL1_ACU_Pos (4) /*!< EADC_T::MCTL1: ACU Position */ +#define EADC_MCTL1_ACU_Msk (0xful << EADC_MCTL1_ACU_Pos) /*!< EADC_T::MCTL1: ACU Mask */ + +#define EADC_M0CTL1_ALIGN_Pos (0) /*!< EADC_T::M0CTL1: ALIGN Position */ +#define EADC_M0CTL1_ALIGN_Msk (0x1ul << EADC_M0CTL1_ALIGN_Pos) /*!< EADC_T::M0CTL1: ALIGN Mask */ + +#define EADC_M0CTL1_AVG_Pos (1) /*!< EADC_T::M0CTL1: AVG Position */ +#define EADC_M0CTL1_AVG_Msk (0x1ul << EADC_M0CTL1_AVG_Pos) /*!< EADC_T::M0CTL1: AVG Mask */ + +#define EADC_M0CTL1_ACU_Pos (4) /*!< EADC_T::M0CTL1: ACU Position */ +#define EADC_M0CTL1_ACU_Msk (0xful << EADC_M0CTL1_ACU_Pos) /*!< EADC_T::M0CTL1: ACU Mask */ + +#define EADC_M1CTL1_ALIGN_Pos (0) /*!< EADC_T::M1CTL1: ALIGN Position */ +#define EADC_M1CTL1_ALIGN_Msk (0x1ul << EADC_M1CTL1_ALIGN_Pos) /*!< EADC_T::M1CTL1: ALIGN Mask */ + +#define EADC_M1CTL1_AVG_Pos (1) /*!< EADC_T::M1CTL1: AVG Position */ +#define EADC_M1CTL1_AVG_Msk (0x1ul << EADC_M1CTL1_AVG_Pos) /*!< EADC_T::M1CTL1: AVG Mask */ + +#define EADC_M1CTL1_ACU_Pos (4) /*!< EADC_T::M1CTL1: ACU Position */ +#define EADC_M1CTL1_ACU_Msk (0xful << EADC_M1CTL1_ACU_Pos) /*!< EADC_T::M1CTL1: ACU Mask */ + +#define EADC_M2CTL1_ALIGN_Pos (0) /*!< EADC_T::M2CTL1: ALIGN Position */ +#define EADC_M2CTL1_ALIGN_Msk (0x1ul << EADC_M2CTL1_ALIGN_Pos) /*!< EADC_T::M2CTL1: ALIGN Mask */ + +#define EADC_M2CTL1_AVG_Pos (1) /*!< EADC_T::M2CTL1: AVG Position */ +#define EADC_M2CTL1_AVG_Msk (0x1ul << EADC_M2CTL1_AVG_Pos) /*!< EADC_T::M2CTL1: AVG Mask */ + +#define EADC_M2CTL1_ACU_Pos (4) /*!< EADC_T::M2CTL1: ACU Position */ +#define EADC_M2CTL1_ACU_Msk (0xful << EADC_M2CTL1_ACU_Pos) /*!< EADC_T::M2CTL1: ACU Mask */ + +#define EADC_M3CTL1_ALIGN_Pos (0) /*!< EADC_T::M3CTL1: ALIGN Position */ +#define EADC_M3CTL1_ALIGN_Msk (0x1ul << EADC_M3CTL1_ALIGN_Pos) /*!< EADC_T::M3CTL1: ALIGN Mask */ + +#define EADC_M3CTL1_AVG_Pos (1) /*!< EADC_T::M3CTL1: AVG Position */ +#define EADC_M3CTL1_AVG_Msk (0x1ul << EADC_M3CTL1_AVG_Pos) /*!< EADC_T::M3CTL1: AVG Mask */ + +#define EADC_M3CTL1_ACU_Pos (4) /*!< EADC_T::M3CTL1: ACU Position */ +#define EADC_M3CTL1_ACU_Msk (0xful << EADC_M3CTL1_ACU_Pos) /*!< EADC_T::M3CTL1: ACU Mask */ + +#define EADC_M4CTL1_ALIGN_Pos (0) /*!< EADC_T::M4CTL1: ALIGN Position */ +#define EADC_M4CTL1_ALIGN_Msk (0x1ul << EADC_M4CTL1_ALIGN_Pos) /*!< EADC_T::M4CTL1: ALIGN Mask */ + +#define EADC_M4CTL1_AVG_Pos (1) /*!< EADC_T::M4CTL1: AVG Position */ +#define EADC_M4CTL1_AVG_Msk (0x1ul << EADC_M4CTL1_AVG_Pos) /*!< EADC_T::M4CTL1: AVG Mask */ + +#define EADC_M4CTL1_ACU_Pos (4) /*!< EADC_T::M4CTL1: ACU Position */ +#define EADC_M4CTL1_ACU_Msk (0xful << EADC_M4CTL1_ACU_Pos) /*!< EADC_T::M4CTL1: ACU Mask */ + +#define EADC_M5CTL1_ALIGN_Pos (0) /*!< EADC_T::M5CTL1: ALIGN Position */ +#define EADC_M5CTL1_ALIGN_Msk (0x1ul << EADC_M5CTL1_ALIGN_Pos) /*!< EADC_T::M5CTL1: ALIGN Mask */ + +#define EADC_M5CTL1_AVG_Pos (1) /*!< EADC_T::M5CTL1: AVG Position */ +#define EADC_M5CTL1_AVG_Msk (0x1ul << EADC_M5CTL1_AVG_Pos) /*!< EADC_T::M5CTL1: AVG Mask */ + +#define EADC_M5CTL1_ACU_Pos (4) /*!< EADC_T::M5CTL1: ACU Position */ +#define EADC_M5CTL1_ACU_Msk (0xful << EADC_M5CTL1_ACU_Pos) /*!< EADC_T::M5CTL1: ACU Mask */ + +#define EADC_M6CTL1_ALIGN_Pos (0) /*!< EADC_T::M6CTL1: ALIGN Position */ +#define EADC_M6CTL1_ALIGN_Msk (0x1ul << EADC_M6CTL1_ALIGN_Pos) /*!< EADC_T::M6CTL1: ALIGN Mask */ + +#define EADC_M6CTL1_AVG_Pos (1) /*!< EADC_T::M6CTL1: AVG Position */ +#define EADC_M6CTL1_AVG_Msk (0x1ul << EADC_M6CTL1_AVG_Pos) /*!< EADC_T::M6CTL1: AVG Mask */ + +#define EADC_M6CTL1_ACU_Pos (4) /*!< EADC_T::M6CTL1: ACU Position */ +#define EADC_M6CTL1_ACU_Msk (0xful << EADC_M6CTL1_ACU_Pos) /*!< EADC_T::M6CTL1: ACU Mask */ + +#define EADC_M7CTL1_ALIGN_Pos (0) /*!< EADC_T::M7CTL1: ALIGN Position */ +#define EADC_M7CTL1_ALIGN_Msk (0x1ul << EADC_M7CTL1_ALIGN_Pos) /*!< EADC_T::M7CTL1: ALIGN Mask */ + +#define EADC_M7CTL1_AVG_Pos (1) /*!< EADC_T::M7CTL1: AVG Position */ +#define EADC_M7CTL1_AVG_Msk (0x1ul << EADC_M7CTL1_AVG_Pos) /*!< EADC_T::M7CTL1: AVG Mask */ + +#define EADC_M7CTL1_ACU_Pos (4) /*!< EADC_T::M7CTL1: ACU Position */ +#define EADC_M7CTL1_ACU_Msk (0xful << EADC_M7CTL1_ACU_Pos) /*!< EADC_T::M7CTL1: ACU Mask */ + +#define EADC_M8CTL1_ALIGN_Pos (0) /*!< EADC_T::M8CTL1: ALIGN Position */ +#define EADC_M8CTL1_ALIGN_Msk (0x1ul << EADC_M8CTL1_ALIGN_Pos) /*!< EADC_T::M8CTL1: ALIGN Mask */ + +#define EADC_M8CTL1_AVG_Pos (1) /*!< EADC_T::M8CTL1: AVG Position */ +#define EADC_M8CTL1_AVG_Msk (0x1ul << EADC_M8CTL1_AVG_Pos) /*!< EADC_T::M8CTL1: AVG Mask */ + +#define EADC_M8CTL1_ACU_Pos (4) /*!< EADC_T::M8CTL1: ACU Position */ +#define EADC_M8CTL1_ACU_Msk (0xful << EADC_M8CTL1_ACU_Pos) /*!< EADC_T::M8CTL1: ACU Mask */ + +#define EADC_M9CTL1_ALIGN_Pos (0) /*!< EADC_T::M9CTL1: ALIGN Position */ +#define EADC_M9CTL1_ALIGN_Msk (0x1ul << EADC_M9CTL1_ALIGN_Pos) /*!< EADC_T::M9CTL1: ALIGN Mask */ + +#define EADC_M9CTL1_AVG_Pos (1) /*!< EADC_T::M9CTL1: AVG Position */ +#define EADC_M9CTL1_AVG_Msk (0x1ul << EADC_M9CTL1_AVG_Pos) /*!< EADC_T::M9CTL1: AVG Mask */ + +#define EADC_M9CTL1_ACU_Pos (4) /*!< EADC_T::M9CTL1: ACU Position */ +#define EADC_M9CTL1_ACU_Msk (0xful << EADC_M9CTL1_ACU_Pos) /*!< EADC_T::M9CTL1: ACU Mask */ + +#define EADC_M10CTL1_ALIGN_Pos (0) /*!< EADC_T::M10CTL1: ALIGN Position */ +#define EADC_M10CTL1_ALIGN_Msk (0x1ul << EADC_M10CTL1_ALIGN_Pos) /*!< EADC_T::M10CTL1: ALIGN Mask */ + +#define EADC_M10CTL1_AVG_Pos (1) /*!< EADC_T::M10CTL1: AVG Position */ +#define EADC_M10CTL1_AVG_Msk (0x1ul << EADC_M10CTL1_AVG_Pos) /*!< EADC_T::M10CTL1: AVG Mask */ + +#define EADC_M10CTL1_ACU_Pos (4) /*!< EADC_T::M10CTL1: ACU Position */ +#define EADC_M10CTL1_ACU_Msk (0xful << EADC_M10CTL1_ACU_Pos) /*!< EADC_T::M10CTL1: ACU Mask */ + +#define EADC_M11CTL1_ALIGN_Pos (0) /*!< EADC_T::M11CTL1: ALIGN Position */ +#define EADC_M11CTL1_ALIGN_Msk (0x1ul << EADC_M11CTL1_ALIGN_Pos) /*!< EADC_T::M11CTL1: ALIGN Mask */ + +#define EADC_M11CTL1_AVG_Pos (1) /*!< EADC_T::M11CTL1: AVG Position */ +#define EADC_M11CTL1_AVG_Msk (0x1ul << EADC_M11CTL1_AVG_Pos) /*!< EADC_T::M11CTL1: AVG Mask */ + +#define EADC_M11CTL1_ACU_Pos (4) /*!< EADC_T::M11CTL1: ACU Position */ +#define EADC_M11CTL1_ACU_Msk (0xful << EADC_M11CTL1_ACU_Pos) /*!< EADC_T::M11CTL1: ACU Mask */ + +#define EADC_M12CTL1_ALIGN_Pos (0) /*!< EADC_T::M12CTL1: ALIGN Position */ +#define EADC_M12CTL1_ALIGN_Msk (0x1ul << EADC_M12CTL1_ALIGN_Pos) /*!< EADC_T::M12CTL1: ALIGN Mask */ + +#define EADC_M12CTL1_AVG_Pos (1) /*!< EADC_T::M12CTL1: AVG Position */ +#define EADC_M12CTL1_AVG_Msk (0x1ul << EADC_M12CTL1_AVG_Pos) /*!< EADC_T::M12CTL1: AVG Mask */ + +#define EADC_M12CTL1_ACU_Pos (4) /*!< EADC_T::M12CTL1: ACU Position */ +#define EADC_M12CTL1_ACU_Msk (0xful << EADC_M12CTL1_ACU_Pos) /*!< EADC_T::M12CTL1: ACU Mask */ + +#define EADC_M13CTL1_ALIGN_Pos (0) /*!< EADC_T::M13CTL1: ALIGN Position */ +#define EADC_M13CTL1_ALIGN_Msk (0x1ul << EADC_M13CTL1_ALIGN_Pos) /*!< EADC_T::M13CTL1: ALIGN Mask */ + +#define EADC_M13CTL1_AVG_Pos (1) /*!< EADC_T::M13CTL1: AVG Position */ +#define EADC_M13CTL1_AVG_Msk (0x1ul << EADC_M13CTL1_AVG_Pos) /*!< EADC_T::M13CTL1: AVG Mask */ + +#define EADC_M13CTL1_ACU_Pos (4) /*!< EADC_T::M13CTL1: ACU Position */ +#define EADC_M13CTL1_ACU_Msk (0xful << EADC_M13CTL1_ACU_Pos) /*!< EADC_T::M13CTL1: ACU Mask */ + +#define EADC_M14CTL1_ALIGN_Pos (0) /*!< EADC_T::M14CTL1: ALIGN Position */ +#define EADC_M14CTL1_ALIGN_Msk (0x1ul << EADC_M14CTL1_ALIGN_Pos) /*!< EADC_T::M14CTL1: ALIGN Mask */ + +#define EADC_M14CTL1_AVG_Pos (1) /*!< EADC_T::M14CTL1: AVG Position */ +#define EADC_M14CTL1_AVG_Msk (0x1ul << EADC_M14CTL1_AVG_Pos) /*!< EADC_T::M14CTL1: AVG Mask */ + +#define EADC_M14CTL1_ACU_Pos (4) /*!< EADC_T::M14CTL1: ACU Position */ +#define EADC_M14CTL1_ACU_Msk (0xful << EADC_M14CTL1_ACU_Pos) /*!< EADC_T::M14CTL1: ACU Mask */ + +#define EADC_M15CTL1_ALIGN_Pos (0) /*!< EADC_T::M15CTL1: ALIGN Position */ +#define EADC_M15CTL1_ALIGN_Msk (0x1ul << EADC_M15CTL1_ALIGN_Pos) /*!< EADC_T::M15CTL1: ALIGN Mask */ + +#define EADC_M15CTL1_AVG_Pos (1) /*!< EADC_T::M15CTL1: AVG Position */ +#define EADC_M15CTL1_AVG_Msk (0x1ul << EADC_M15CTL1_AVG_Pos) /*!< EADC_T::M15CTL1: AVG Mask */ + +#define EADC_M15CTL1_ACU_Pos (4) /*!< EADC_T::M15CTL1: ACU Position */ +#define EADC_M15CTL1_ACU_Msk (0xful << EADC_M15CTL1_ACU_Pos) /*!< EADC_T::M15CTL1: ACU Mask */ + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EADC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ebi_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ebi_reg.h new file mode 100644 index 0000000..7b92f41 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ebi_reg.h @@ -0,0 +1,168 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @version V3.00 + * @brief EBI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- External Bus Interface Controller -------------------------*/ +/** + @addtogroup EBI External Bus Interface Controller(EBI) + Memory Mapped Structure for EBI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var EBI_T::CTL + * Offset: 0x00 External Bus Interface Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL + * Offset: 0x04 External Bus Interface Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC+1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD+1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller + @{ +*/ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ + +#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ +#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ + + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EBI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ecap_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ecap_reg.h new file mode 100644 index 0000000..d22d9dc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ecap_reg.h @@ -0,0 +1,390 @@ +/**************************************************************************//** + * @file ecap_reg.h + * @version V1.00 + * @brief ECAP register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ECAP_REG_H__ +#define __ECAP_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ECAP Enhanced Input Capture Timer(ECAP) + Memory Mapped Structure for ECAP Controller +@{ */ + +typedef struct +{ + + /** + * @var ECAP_T::CNT + * Offset: 0x00 Input Capture Counter (24-bit up counter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Input Capture Timer/Counter + * | | |The input Capture Timer/Counter is a 24-bit up-counting counter + * | | |The clock source for the counter is from the clock divider + * @var ECAP_T::HLD0 + * Offset: 0x04 Input Capture Hold Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD1 + * Offset: 0x08 Input Capture Hold Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD2 + * Offset: 0x0C Input Capture Hold Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::CNTCMP + * Offset: 0x10 Input Capture Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNTCMP |Input Capture Counter Compare Register + * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). + * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. + * @var ECAP_T::CTL0 + * Offset: 0x14 Input Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock + * | | |000 = CAP_CLK. + * | | |001 = CAP_CLK/2. + * | | |010 = CAP_CLK/4. + * | | |011 = CAP_CLK/16. + * | | |100 = CAP_CLK/32. + * | | |101 = CAP_CLK/64. + * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control + * | | |0 = Noise filter of Input Capture Enabled. + * | | |1 = Noise filter of Input Capture Disabled (Bypass). + * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control + * | | |0 = IC0 input to Input Capture Unit Disabled. + * | | |1 = IC0 input to Input Capture Unit Enabled. + * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control + * | | |0 = IC1 input to Input Capture Unit Disabled. + * | | |1 = IC1 input to Input Capture Unit Enabled. + * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control + * | | |0 = IC2 input to Input Capture Unit Disabled. + * | | |1 = IC2 input to Input Capture Unit Enabled. + * |[9:8] |CAPSEL0 |CAP0 Input Source Selection + * | | |00 = CAP0 input is from port pin ICAP0. + * | | |01 = Reserved. + * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[11:10] |CAPSEL1 |CAP1 Input Source Selection + * | | |00 = CAP1 input is from port pin ICAP1. + * | | |01 = Reserved. + * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[13:12] |CAPSEL2 |CAP2 Input Source Selection + * | | |00 = CAP2 input is from port pin ICAP2. + * | | |01 = Reserved. + * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control + * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. + * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control + * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. + * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control + * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. + * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. + * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. + * |[24] |CNTEN |Input Capture Counter Start Counting Control + * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . + * | | |0 = ECAP_CNT stop counting. + * | | |1 = ECAP_CNT starts up-counting. + * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control + * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. + * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. + * |[28] |CMPEN |Compare Function Enable Control + * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. + * | | |0 = The compare function Disabled. + * | | |1 = The compare function Enabled. + * |[29] |CAPEN |Input Capture Timer/Counter Enable Control + * | | |0 = Input Capture function Disabled. + * | | |1 = Input Capture function Enabled. + * @var ECAP_T::CTL1 + * Offset: 0x18 Input Capture Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection + * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection + * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection + * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit + * | | |0 = The reload triggered by Event CAPTE0 Disabled. + * | | |1 = The reload triggered by Event CAPTE0 Enabled. + * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit + * | | |0 = The reload triggered by Event CAPTE1 Disabled. + * | | |1 = The reload triggered by Event CAPTE1 Enabled. + * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit + * | | |0 = The reload triggered by Event CAPTE2 Disabled. + * | | |1 = The reload triggered by Event CAPTE2 Enabled. + * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit + * | | |0 = The reload triggered by CAPOV Disabled. + * | | |1 = The reload triggered by CAPOV Enabled. + * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection + * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. + * | | |000 = CAP_CLK/1. + * | | |001 = CAP_CLK/4. + * | | |010 = CAP_CLK/16. + * | | |011 = CAP_CLK/32. + * | | |100 = CAP_CLK/64. + * | | |101 = CAP_CLK/96. + * | | |110 = CAP_CLK/112. + * | | |111 = CAP_CLK/128. + * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection + * | | |Select the capture timer/counter clock source. + * | | |00 = CAP_CLK (default). + * | | |01 = CAP0. + * | | |10 = CAP1. + * | | |11 = CAP2. + * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control + * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. + * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control + * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. + * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control + * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. + * @var ECAP_T::STATUS + * Offset: 0x1C Input Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag + * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. + * | | |0 = No valid edge change has been detected at CAP0 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag + * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. + * | | |0 = No valid edge change has been detected at CAP1 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag + * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. + * | | |0 = No valid edge change has been detected at CAP2 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[4] |CAPCMPF |Input Capture Compare-match Flag + * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. + * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. + * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[5] |CAPOVF |Input Capture Counter Overflow Flag + * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. + * | | |0 = No overflow event has occurred since last clear. + * | | |1 = Overflow event(s) has/have occurred since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) + * | | |Reflecting the value of input channel 0, CAP0 + * | | |(The bit is read only and write is ignored) + * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) + * | | |Reflecting the value of input channel 1, CAP1 + * | | |(The bit is read only and write is ignored) + * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) + * | | |Reflecting the value of input channel 2, CAP2. + * | | |(The bit is read only and write is ignored) + */ + __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ + __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ + __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ + __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ + __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ + __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ + __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ + +} ECAP_T; + +/** + @addtogroup ECAP_CONST ECAP Bit Field Definition + Constant Definitions for ECAP Controller +@{ */ + +#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ +#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ + +#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ +#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ + +#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ +#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ + +#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ +#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ + +#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ +#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ + +#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ +#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ + +#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ +#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ + +#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ +#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ + +#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ +#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ + +#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ +#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ + +#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ +#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ + +#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ +#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ + +#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ +#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ + +#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ +#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ + +#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ +#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ + +#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ +#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ + +#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ +#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ + +#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ +#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ + +#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ +#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ + +#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ +#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ + +#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ +#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ + +#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ +#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ + +#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ +#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ + +#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ +#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ + +#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ +#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ + +#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ +#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ + +#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ +#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ + +#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ +#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ + +#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ +#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ + +#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ +#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ + +#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ +#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ + +#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ +#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ + +#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ +#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ + +#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ +#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ + +#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ +#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ + +#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ +#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ + +#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ +#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ + +#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ +#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ + +#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ +#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ + +#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ +#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ + +#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ +#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ + +#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ +#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ + +/**@}*/ /* ECAP_CONST */ +/**@}*/ /* end of ECAP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __ECAP_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/emac_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/emac_reg.h new file mode 100644 index 0000000..831df4a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/emac_reg.h @@ -0,0 +1,2063 @@ +/**************************************************************************//** + * @file emac_reg.h + * @version V1.00 + * @brief EMAC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EMAC_REG_H__ +#define __EMAC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EMAC Ethernet MAC Controller(EMAC) + Memory Mapped Structure for EMAC Controller +@{ */ + +typedef struct +{ + + /** + * @var EMAC_T::CAMCTL + * Offset: 0x00 CAM Comparison Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AUP |Accept Unicast Packet + * | | |The AUP controls the unicast packet reception + * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all unicast packets. + * |[1] |AMP |Accept Multicast Packet + * | | |The AMP controls the multicast packet reception + * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all multicast packets. + * |[2] |ABP |Accept Broadcast Packet + * | | |The ABP controls the broadcast packet reception + * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address. + * | | |0 = EMAC receives packet depends on the CAM comparison result. + * | | |1 = EMAC receives all broadcast packets. + * |[3] |COMPEN |Complement CAM Comparison Enable Bit + * | | |The COMPEN controls the complement of the CAM comparison result + * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address + * | | |configured in CAM entry will be dropped + * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received. + * | | |0 = Complement CAM comparison result Disabled. + * | | |1 = Complement CAM comparison result Enabled. + * |[4] |CMPEN |CAM Compare Enable Bit + * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition + * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address + * | | |into CAM 12~0, then enables that CAM entry and set CMPEN to 1. + * | | |0 = CAM comparison function for destination MAC address recognition Disabled. + * | | |1 = CAM comparison function for destination MAC address recognition Enabled. + * @var EMAC_T::CAMEN + * Offset: 0x04 CAM Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAMxEN |CAM Entry X Enable Bit + * | | |The CAMxEN controls the validation of CAM entry x. + * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission + * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM + * | | |entries all must be enabled first. + * | | |0 = CAM entry x Disabled. + * | | |1 = CAM entry x Enabled. + * @var EMAC_T::CAM0M + * Offset: 0x08 CAM0 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM0L + * Offset: 0x0C CAM0 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1M + * Offset: 0x10 CAM1 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM1L + * Offset: 0x14 CAM1 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2M + * Offset: 0x18 CAM2 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM2L + * Offset: 0x1C CAM2 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3M + * Offset: 0x20 CAM3 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM3L + * Offset: 0x24 CAM3 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4M + * Offset: 0x28 CAM4 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM4L + * Offset: 0x2C CAM4 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5M + * Offset: 0x30 CAM5 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM5L + * Offset: 0x34 CAM5 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6M + * Offset: 0x38 CAM6 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM6L + * Offset: 0x3C CAM6 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7M + * Offset: 0x40 CAM7 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM7L + * Offset: 0x44 CAM7 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8M + * Offset: 0x48 CAM8 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM8L + * Offset: 0x4C CAM8 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9M + * Offset: 0x50 CAM9 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM9L + * Offset: 0x54 CAM9 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10M + * Offset: 0x58 CAM10 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM10L + * Offset: 0x5C CAM10 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11M + * Offset: 0x60 CAM11 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM11L + * Offset: 0x64 CAM11 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12M + * Offset: 0x68 CAM12 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM12L + * Offset: 0x6C CAM12 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13M + * Offset: 0x70 CAM13 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM13L + * Offset: 0x74 CAM13 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14M + * Offset: 0x78 CAM14 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |MACADDR2 |MAC Address Byte 2 + * |[15:8] |MACADDR3 |MAC Address Byte 3 + * |[23:16] |MACADDR4 |MAC Address Byte 4 + * |[31:24] |MACADDR5 |MAC Address Byte 5 + * | | |The CAMxM keeps the bit 47~16 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM14L + * Offset: 0x7C CAM14 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:16] |MACADDR0 |MAC Address Byte 0 + * |[31:24] |MACADDR1 |MAC Address Byte 1 + * | | |The CAMxL keeps the bit 15~0 of MAC address + * | | |The x can be the 0~14 + * | | |The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address. + * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is + * | | |0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000. + * @var EMAC_T::CAM15MSB + * Offset: 0x80 CAM15 Most Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |OPCODE |OP Code Field of PAUSE Control Frame + * | | |In the PAUSE control frame, an op code field defined and is 0x0001. + * |[31:16] |LENGTH |LENGTH Field of PAUSE Control Frame + * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808. + * @var EMAC_T::CAM15LSB + * Offset: 0x84 CAM15 Least Significant Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:24] |OPERAND |Pause Parameter + * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination + * | | |Ethernet MAC Controller paused + * | | |The unit of the OPERAND is a slot time, the 512-bit time. + * @var EMAC_T::TXDSA + * Offset: 0x88 Transmit Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDSA |Transmit Descriptor Link-list Start Address + * | | |The TXDSA keeps the start address of transmit descriptor link-list + * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the + * | | |current transmit descriptor start address register (EMAC_CTXDSA) + * | | |The TXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA + * | | |This means that TX descriptors must locate at word boundary memory address. + * @var EMAC_T::RXDSA + * Offset: 0x8C Receive Descriptor Link List Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDSA |Receive Descriptor Link-list Start Address + * | | |The RXDSA keeps the start address of receive descriptor link-list + * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current + * | | |receive descriptor start address register (EMAC_CRXDSA) + * | | |The RXDSA does not be updated by EMAC + * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA + * | | |This means that RX descriptors must locate at word boundary memory address. + * @var EMAC_T::CTL + * Offset: 0x90 MAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXON |Frame Reception ON + * | | |The RXON controls the normal packet reception of EMAC + * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX + * | | |descriptor fetching, packet reception and RX descriptor modification. + * | | |It is necessary to finish EMAC initial sequence before enable RXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet + * | | |reception process after the current packet reception finished. + * | | |0 = Packet reception process stopped. + * | | |1 = Packet reception process started. + * |[1] |ALP |Accept Long Packet + * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception + * | | |If the ALP is set to high, the EMAC will accept the long packet. + * | | |Otherwise, the long packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the long packet. + * | | |1 = Ethernet MAC controller received the long packet. + * |[2] |ARP |Accept Runt Packet + * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception + * | | |If the ARP is set to high, the EMAC will accept the runt packet. + * | | |Otherwise, the runt packet will be dropped. + * | | |0 = Ethernet MAC controller dropped the runt packet. + * | | |1 = Ethernet MAC controller received the runt packet. + * |[3] |ACP |Accept Control Packet + * | | |The ACP controls the control frame reception + * | | |If the ACP is set to high, the EMAC will accept the control frame + * | | |Otherwise, the control frame will be dropped + * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode. + * | | |0 = Ethernet MAC controller dropped the control frame. + * | | |1 = Ethernet MAC controller received the control frame. + * |[4] |AEP |Accept CRC Error Packet + * | | |The AEP controls the EMAC accepts or drops the CRC error packet + * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet. + * | | |0 = Ethernet MAC controller dropped the CRC error packet. + * | | |1 = Ethernet MAC controller received the CRC error packet. + * |[5] |STRIPCRC |Strip CRC Checksum + * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum + * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet. + * | | |0 = The 4 bytes CRC checksum is included in packet length calculation. + * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation. + * |[6] |WOLEN |Wake on LAN Enable Bit + * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet + * | | |is Magic Packet and wakeup system from Power-down mode. + * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller + * | | |would generate a wakeup event to wake system up from Power-down mode. + * | | |0 = Wake-up by Magic Packet function Disabled. + * | | |1 = Wake-up by Magic Packet function Enabled. + * |[8] |TXON |Frame Transmission ON + * | | |The TXON controls the normal packet transmission of EMAC + * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX + * | | |descriptor fetching, packet transmission and TX descriptor modification. + * | | |It is must to finish EMAC initial sequence before enable TXON + * | | |Otherwise, the EMAC operation is undefined. + * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet + * | | |transmission process after the current packet transmission finished. + * | | |0 = Packet transmission process stopped. + * | | |1 = Packet transmission process started. + * |[9] |NODEF |No Deferral + * | | |The NODEF controls the enable of deferral exceed counter + * | | |If NODEF is set to high, the deferral exceed counter is disabled + * | | |The NODEF is only useful while EMAC is operating on half duplex mode. + * | | |0 = The deferral exceed counter Enabled. + * | | |1 = The deferral exceed counter Disabled. + * |[16] |SDPZ |Send PAUSE Frame + * | | |The SDPZ controls the PAUSE control frame transmission. + * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured + * | | |first and the corresponding CAM enable bit of CAMEN register also must be set. + * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission. + * | | |The SDPZ is a self-clear bit + * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically. + * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode. + * | | |0 = PAUSE control frame transmission completed. + * | | |1 = PAUSE control frame transmission Enabled. + * |[17] |SQECHKEN |SQE Checking Enable Bit + * | | |The SQECHKEN controls the enable of SQE checking + * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode + * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100Mbps + * | | |or full duplex mode. + * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode. + * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode. + * |[18] |FUDUP |Full Duplex Mode Selection + * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode. + * | | |0 = EMAC operates in half duplex mode. + * | | |1 = EMAC operates in full duplex mode. + * |[19] |RMIIRXCTL |RMII RX Control + * | | |The RMIIRXCTL control the receive data sample in RMII mode + * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high. + * | | |0 = RMII RX control disabled. + * | | |1 = RMII RX control enabled. + * |[20] |OPMODE |Operation Mode Selection + * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode + * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value. + * | | |0 = EMAC operates in 10Mbps mode. + * | | |1 = EMAC operates in 100Mbps mode. + * |[22] |RMIIEN |RMII Mode Enable Bit + * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII + * | | |interface or RMII interface + * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value. + * | | |0 = Ethernet MAC controller RMII mode Disabled. + * | | |1 = Ethernet MAC controller RMII mode Enabled. + * | | |NOTE: This field must keep 1. + * |[24] |RST |Software Reset + * | | |The RST implements a reset function to make the EMAC return default state + * | | |The RST is a self-clear bit + * | | |This means after the software reset finished, the RST will be cleared automatically + * | | |Enable RST can also reset all control and status registers, exclusive of the control bits + * | | |RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]). + * | | |The EMAC re-initial is necessary after the software reset completed. + * | | |0 = Software reset completed. + * | | |1 = Software reset Enabled. + * @var EMAC_T::MIIMDAT + * Offset: 0x94 MII Management Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATA |MII Management Data + * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII + * | | |Management write command or the data from the registers of external PHY for MII Management read command. + * @var EMAC_T::MIIMCTL + * Offset: 0x98 MII Management Control and Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PHYREG |PHY Register Address + * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the + * | | |MII management command. + * |[12:8] |PHYADDR |PHY Address + * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command. + * |[16] |WRITE |Write Command + * | | |The Write defines the MII management command is a read or write. + * | | |0 = MII management command is a read command. + * | | |1 = MII management command is a write command. + * |[17] |BUSY |Busy Bit + * | | |The BUSY controls the enable of the MII management frame generation + * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates + * | | |the MII management frame to external PHY through MII Management I/F + * | | |The BUSY is a self-clear bit + * | | |This means the BUSY will be cleared automatically after the MII management command finished. + * | | |0 = MII management command generation finished. + * | | |1 = MII management command generation Enabled. + * |[18] |PREAMSP |Preamble Suppress + * | | |The PREAMSP controls the preamble field generation of MII management frame + * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped. + * | | |0 = Preamble field generation of MII management frame not skipped. + * | | |1 = Preamble field generation of MII management frame skipped. + * |[19] |MDCON |MDC Clock ON + * | | |The MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on. + * | | |0 = MDC clock off. + * | | |1 = MDC clock on. + * @var EMAC_T::FIFOCTL + * Offset: 0x9C FIFO Threshold Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RXFIFOTH |RXFIFO Low Threshold + * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO + * | | |and system memory + * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold + * | | |The low threshold is the half of high threshold always + * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to + * | | |transfer frame data from RXFIFO to system memory + * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame + * | | |data to system memory. + * | | |00 = Depend on the burst length setting + * | | |If the burst length is 8 words, high threshold is 8 words, too. + * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B. + * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B. + * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B. + * |[9:8] |TXFIFOTH |TXFIFO Low Threshold + * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system + * | | |memory and TXFIFO + * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold + * | | |The high threshold is the twice of low threshold always + * | | |During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops + * | | |generate request to transfer frame data from system memory to TXFIFO + * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data + * | | |from system memory to TXFIFO. + * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network + * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold + * | | |during the transmission of the frame + * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame + * | | |out after the frame data are all inside the TXFIFO. + * | | |00 = Undefined. + * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B. + * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B. + * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B. + * |[21:20] |BURSTLEN |DMA Burst Length + * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory. + * | | |00 = 4 words. + * | | |01 = 8 words. + * | | |10 = 16 words. + * | | |11 = 16 words. + * @var EMAC_T::TXST + * Offset: 0xA0 Transmit Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXST |Transmit Start Demand + * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, + * | | |the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted + * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write + * | | |command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission. + * | | |The EMAC_TXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state. + * @var EMAC_T::RXST + * Offset: 0xA4 Receive Start Demand Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXST |Receive Start Demand + * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, + * | | |the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted + * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write + * | | |command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception. + * | | |The EMAC_RXST is a write only register and read from this register is undefined. + * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state. + * @var EMAC_T::MRFL + * Offset: 0xA8 Maximum Receive Frame Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MRFL |Maximum Receive Frame Length + * | | |The MRFL defines the maximum frame length for received frame + * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) + * | | |is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered. + * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to + * | | |receive a frame which length is greater than 1518 bytes. + * @var EMAC_T::INTEN + * Offset: 0xAC MAC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIEN |Receive Interrupt Enable Bit + * | | |The RXIEN controls the RX interrupt generation. + * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU + * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] + * | | |is set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit. + * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled. + * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled. + * |[1] |CRCEIEN |CRC Error Interrupt Enable Bit + * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation + * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CRCEIF (EMAC_INTSTS[1]) is set. + * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled. + * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled. + * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Bit + * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation + * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXOVIF (EMAC_INTSTS[2]) is set. + * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled. + * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled. + * |[3] |LPIEN |Long Packet Interrupt Enable Bit + * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation + * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF + * | | |(EMAC_INTSTS[3]) is set. + * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled. + * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled. + * |[4] |RXGDIEN |Receive Good Interrupt Enable Bit + * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation + * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXGDIF (EMAC_INTSTS[4]) is set. + * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled. + * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled. + * |[5] |ALIEIEN |Alignment Error Interrupt Enable Bit + * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation + * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |ALIEIF (EMAC_INTSTS[5]) is set. + * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled. + * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled. + * |[6] |RPIEN |Runt Packet Interrupt Enable Bit + * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation + * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC + * | | |generates the RX interrupt to CPU + * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RPIF (EMAC_INTSTS[6]) is set. + * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled. + * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled. + * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable Bit + * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation + * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MPCOVIF (EMAC_INTSTS[7]) is set. + * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled. + * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled. + * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable Bit + * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation + * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |MFLEIF (EMAC_INTSTS[8]) is set. + * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled. + * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled. + * |[9] |DENIEN |DMA Early Notification Interrupt Enable Bit + * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation + * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |DENIF (EMAC_INTSTS[9]) is set. + * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled. + * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled. + * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Bit + * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation + * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RDUIF (EMAC_MIOSTA[10]) register is set. + * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled. + * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled. + * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Bit + * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation + * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |RXBEIF (EMAC_INTSTS[11]) is set. + * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled. + * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled. + * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Bit + * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation + * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the + * | | |EMAC generates the RX interrupt to CPU + * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |CFRIF (EMAC_INTSTS[14]) register is set. + * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled. + * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled. + * |[15] |WOLIEN |Wake on LAN Interrupt Enable Bit + * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation + * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, + * | | |the EMAC generates the RX interrupt to CPU + * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the + * | | |WOLIF (EMAC_INTSTS[15]) is set. + * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled. + * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled. + * |[16] |TXIEN |Transmit Interrupt Enable Bit + * | | |The TXIEN controls the TX interrupt generation. + * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU + * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of + * | | |EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled + * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled + * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit. + * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled. + * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled. + * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Bit + * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation + * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even + * | | |the TXUDIF (EMAC_INTSTS[17]) is set. + * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled. + * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled. + * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Bit + * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation + * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXCPIF (EMAC_INTSTS[18]) is set. + * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled. + * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled. + * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Bit + * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation + * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |EXDEFIF (EMAC_INTSTS[19]) is set. + * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled. + * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled. + * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Bit + * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation + * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |NCSIF (EMAC_INTSTS[20]) is set. + * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled. + * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled. + * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Bit + * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation + * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, + * | | |the EMAC generates the TX interrupt to CPU + * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXABTIF (EMAC_INTSTS[21]) is set. + * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled. + * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled. + * |[22] |LCIEN |Late Collision Interrupt Enable Bit + * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation + * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |LCIF (EMAC_INTSTS[22]) is set. + * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled. + * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled. + * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Bit + * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation + * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TDUIF (EMAC_INTSTS[23]) is set. + * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled. + * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled. + * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Bit + * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation + * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the + * | | |TXBEIF (EMAC_INTSTS[24]) is set. + * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled. + * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled. + * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Bit + * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation + * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the + * | | |EMAC generates the TX interrupt to CPU + * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the + * | | |TXTSALMIF (EMAC_INTEN[28]) is set. + * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled. + * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled. + * @var EMAC_T::INTSTS + * Offset: 0xB0 MAC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXIF |Receive Interrupt + * | | |The RXIF indicates the RX interrupt status. + * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates + * | | |the EMAC generates RX interrupt to CPU + * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated. + * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1] + * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is also enabled, the RXIF will be high. + * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in + * | | |EMAC_INTEN[15:1] is enabled, too. + * |[1] |CRCEIF |CRC Error Interrupt + * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped + * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and + * | | |CRCEIF will not be set. + * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CRCEIF status. + * | | |0 = The frame does not incur CRC error. + * | | |1 = The frame incurred CRC error. + * |[2] |RXOVIF |Receive FIFO Overflow Interrupt + * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception + * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer + * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, + * | | |the RXFIFOTH of FFTCR register, to higher level. + * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXOVIF status. + * | | |0 = No RXFIFO overflow occurred during packet reception. + * | | |1 = RXFIFO overflow occurred during packet reception. + * |[3] |LPIF |Long Packet Interrupt Flag + * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the + * | | |incoming packet is dropped + * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set. + * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the LPIF status. + * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame. + * | | |1 = The incoming frame is a long frame and dropped. + * |[4] |RXGDIF |Receive Good Interrupt + * | | |The RXGDIF high indicates the frame reception has completed. + * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXGDIF status. + * | | |0 = The frame reception has not complete yet. + * | | |1 = The frame reception has completed. + * |[5] |ALIEIF |Alignment Error Interrupt + * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte + * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the ALIEIF status. + * | | |0 = The frame length is a multiple of byte. + * | | |1 = The frame length is not a multiple of byte. + * |[6] |RPIF |Runt Packet Interrupt + * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped + * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set. + * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RPIF status. + * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame. + * | | |1 = The incoming frame is a short frame and dropped. + * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag + * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow + * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MPCOVIF status. + * | | |0 = The MPCNT has not rolled over yet. + * | | |1 = The MPCNT has rolled over yet. + * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag + * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation + * | | |configured in DMARFC register and the incoming packet is dropped + * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the MFLEIF status. + * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC. + * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC. + * |[9] |DENIF |DMA Early Notification Interrupt + * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet. + * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the DENIF status. + * | | |0 = The LENGTH field of incoming packet has not received yet. + * | | |1 = The LENGTH field of incoming packet has received. + * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt + * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and + * | | |RXDMA will stay at Halt state + * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to + * | | |make RXDMA leave Halt state while new RX descriptor is available. + * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RDUIF status. + * | | |0 = RX descriptor is available. + * | | |1 = RX descriptor is unavailable. + * |[11] |RXBEIF |Receive Bus Error Interrupt + * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access + * | | |system memory through RXDMA during packet reception process + * | | |Reset EMAC is recommended while RXBEIF status is high. + * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the RXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[14] |CFRIF |Control Frame Receive Interrupt + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the CFRIF status. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[15] |WOLIF |Wake on LAN Interrupt Flag + * | | |The WOLIF high indicates EMAC receives a Magic Packet + * | | |The CFRIF only available while system is in power down mode and WOLEN is set high. + * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high + * | | |Write 1 to this bit clears the WOLIF status. + * | | |0 = The EMAC does not receive the Magic Packet. + * | | |1 = The EMAC receives a Magic Packet. + * |[16] |TXIF |Transmit Interrupt + * | | |The TXIF indicates the TX interrupt status. + * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates + * | | |the EMAC generates TX interrupt to CPU + * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated. + * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17] + * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is also enabled, the TXIF will be high + * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too. + * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled. + * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit + * | | |in EMAC_INTEN[28:17] is enabled, too. + * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt + * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission + * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically + * | | |without S/W intervention + * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, + * | | |the TXFIFOTH of FFTCR register, to higher level. + * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXUDIF status. + * | | |0 = No TXFIFO underflow occurred during packet transmission. + * | | |1 = TXFIFO underflow occurred during packet transmission. + * |[18] |TXCPIF |Transmit Completion Interrupt + * | | |The TXCPIF indicates the packet transmission has completed correctly. + * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXCPIF status. + * | | |0 = The packet transmission not completed. + * | | |1 = The packet transmission has completed. + * |[19] |EXDEFIF |Defer Exceed Interrupt + * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms + * | | |on 100Mbps mode, or 3.2768ms on 10Mbps mode. + * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC + * | | |is operating on half-duplex mode. + * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the EXDEFIF status. + * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps). + * |[20] |NCSIF |No Carrier Sense Interrupt + * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during + * | | |the packet transmission + * | | |The NCSIF is only available while EMAC is operating on half-duplex mode + * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the NCSIF status. + * | | |0 = CRS signal actives correctly. + * | | |1 = CRS signal does not active at the start of or during the packet transmission. + * |[21] |TXABTIF |Transmit Abort Interrupt + * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, + * | | |and then the transmission process for this packet is aborted + * | | |The transmission abort is only available while EMAC is operating on half-duplex mode. + * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high + * | | |Write 1 to this bit clears the TXABTIF status. + * | | |0 = Packet does not incur 16 consecutive collisions during transmission. + * | | |1 = Packet incurred 16 consecutive collisions during transmission. + * |[22] |LCIF |Late Collision Interrupt + * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window + * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision + * | | |still occurred. + * | | |The late collision check will only be done while EMAC is operating on half-duplex mode + * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the LCIF status. + * | | |0 = No collision occurred in the outside of 64 bytes collision window. + * | | |1 = Collision occurred in the outside of 64 bytes collision window. + * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt + * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and + * | | |TXDMA will stay at Halt state. + * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make + * | | |TXDMA leave Halt state while new TX descriptor is available. + * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TDUIF status. + * | | |0 = TX descriptor is available. + * | | |1 = TX descriptor is unavailable. + * |[24] |TXBEIF |Transmit Bus Error Interrupt + * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system + * | | |memory through TXDMA during packet transmission process + * | | |Reset EMAC is recommended while TXBEIF status is high. + * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TXBEIF status. + * | | |0 = No ERROR response is received. + * | | |1 = ERROR response is received. + * |[28] |TSALMIF |Time Stamp Alarm Interrupt + * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and + * | | |EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBLSR. + * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high. + * | | |Write 1 to this bit clears the TSALMIF status. + * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC. + * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC. + * @var EMAC_T::GENSTS + * Offset: 0xB4 MAC General Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CFR |Control Frame Received + * | | |The CFRIF high indicates EMAC receives a flow control frame + * | | |The CFRIF only available while EMAC is operating on full duplex mode. + * | | |0 = The EMAC does not receive the flow control frame. + * | | |1 = The EMAC receives a flow control frame. + * |[1] |RXHALT |Receive Halted + * | | |The RXHALT high indicates the next normal packet reception process will be halted because + * | | |the bit RXON of MCMDR is disabled be S/W. + * | | |0 = Next normal packet reception process will go on. + * | | |1 = Next normal packet reception process will be halted. + * |[2] |RXFFULL |RXFIFO Full + * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO + * | | |and the following incoming packet will be dropped. + * | | |0 = The RXFIFO is not full. + * | | |1 = The RXFIFO is full and the following incoming packet will be dropped. + * |[7:4] |COLCNT |Collision Count + * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission + * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be + * | | |0 and bit TXABTIF will be set to 1. + * |[8] |DEF |Deferred Transmission + * | | |The DEF high indicates the packet transmission has deferred once + * | | |The DEF is only available while EMAC is operating on half-duplex mode. + * | | |0 = Packet transmission does not defer. + * | | |1 = Packet transmission has deferred once. + * |[9] |TXPAUSED |Transmission Paused + * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally + * | | |because EMAC received a PAUSE control frame. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be paused. + * |[10] |SQE |Signal Quality Error + * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode + * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC + * | | |is operating on 10Mbps half-duplex mode. + * | | |0 = No SQE error found at end of packet transmission. + * | | |1 = SQE error found at end of packet transmission. + * |[11] |TXHALT |Transmission Halted + * | | |The TXHALT high indicates the next normal packet transmission process will be halted because + * | | |the bit TXON (EMAC_CTL[8]) is disabled be S/W. + * | | |0 = Next normal packet transmission process will go on. + * | | |1 = Next normal packet transmission process will be halted. + * |[12] |RPSTS |Remote Pause Status + * | | |The RPSTS indicates that remote pause counter down counting actives. + * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause + * | | |counter down counting + * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet + * | | |transmission until the down counting done. + * | | |0 = Remote pause counter down counting done. + * | | |1 = Remote pause counter down counting actives. + * @var EMAC_T::MPCNT + * Offset: 0xB8 Missed Packet Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MPCNT |Miss Packet Count + * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors + * | | |The following type of receiving error makes missed packet counter increase: + * | | |1. Incoming packet is incurred RXFIFO overflow. + * | | |2. Incoming packet is dropped due to RXON is disabled. + * | | |3. Incoming packet is incurred CRC error. + * @var EMAC_T::RPCNT + * Offset: 0xBC MAC Receive Pause Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RPCNT |MAC Receive Pause Count + * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame + * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused. + * @var EMAC_T::FRSTS + * Offset: 0xC8 DMA Receive Frame Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXFLT |Receive Frame LENGTH + * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet + * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has + * | | |received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. + * | | |And, the content of LENGTH field will be stored in RXFLT. + * @var EMAC_T::CTXDSA + * Offset: 0xCC Current Transmit Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXDSA |Current Transmit Descriptor Start Address + * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently + * | | |The CTXDSA is read only and write to this register has no effect. + * @var EMAC_T::CTXBSA + * Offset: 0xD0 Current Transmit Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CTXBSA |Current Transmit Buffer Start Address + * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently + * | | |The CTXBSA is read only and write to this register has no effect. + * @var EMAC_T::CRXDSA + * Offset: 0xD4 Current Receive Descriptor Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXDSA |Current Receive Descriptor Start Address + * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently + * | | |The CRXDSA is read only and write to this register has no effect. + * @var EMAC_T::CRXBSA + * Offset: 0xD8 Current Receive Buffer Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CRXBSA |Current Receive Buffer Start Address + * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently + * | | |The CRXBSA is read only and write to this register has no effect. + * @var EMAC_T::TSCTL + * Offset: 0x100 Time Stamp Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TSEN |Time Stamp Function Enable Bit + * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not. + * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low + * | | |to disable IEEE 1588 PTP time stamp function. + * | | |0 = I EEE 1588 PTP time stamp function Disabled. + * | | |1 = IEEE 1588 PTP time stamp function Enabled. + * |[1] |TSIEN |Time Stamp Counter Initialization Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC + * | | |and EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = Time stamp counter initialization done. + * | | |1 = Time stamp counter initialization Enabled. + * |[2] |TSMODE |Time Stamp Fine Update Enable Bit + * | | |This bit chooses the time stamp counter update mode. + * | | |0 = Time stamp counter is in coarse update mode. + * | | |1 = Time stamp counter is in fine update mode. + * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Bit + * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and + * | | |EMAC_UPDSUBSEC to PTP time stamp counter. + * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically. + * | | |0 = No action. + * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC. + * |[5] |TSALMEN |Time Stamp Alarm Enable Bit + * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when + * | | |EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC. + * @var EMAC_T::TSSEC + * Offset: 0x110 Time Stamp Counter Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second + * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSSUBSEC + * Offset: 0x114 Time Stamp Counter Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second + * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter + * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high. + * @var EMAC_T::TSINC + * Offset: 0x118 Time Stamp Increment Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNTINC |Time Stamp Counter Increment + * | | |Time stamp counter increment value. + * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every + * | | |time when it wants to increase the EMAC_TSSUBSEC value. + * @var EMAC_T::TSADDEND + * Offset: 0x11C Time Stamp Addend Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDEND |Time Stamp Counter Addend + * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC. + * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator + * | | |with this 32-bit value in each HCLK + * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit + * | | |value kept in register EMAC_TSINC. + * @var EMAC_T::UPDSEC + * Offset: 0x120 Time Stamp Update Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value. + * @var EMAC_T::UPDSUBSEC + * Offset: 0x124 Time Stamp Update Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Update + * | | |When TSIEN (EMAC_TSCTL[1]) is high + * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly + * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value. + * @var EMAC_T::ALMSEC + * Offset: 0x128 Time Stamp Alarm Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEC |Time Stamp Counter Second Alarm + * | | |Time stamp counter second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + * @var EMAC_T::ALMSUBSEC + * Offset: 0x12C Time Stamp Alarm Sub Second Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SUBSEC |Time Stamp Counter Sub-second Alarm + * | | |Time stamp counter sub-second part alarm value. + * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high + * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to + * | | |EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high. + */ + __IO uint32_t CAMCTL; /*!< [0x0000] CAM Comparison Control Register */ + __IO uint32_t CAMEN; /*!< [0x0004] CAM Enable Register */ + __IO uint32_t CAM0M; /*!< [0x0008] CAM0 Most Significant Word Register */ + __IO uint32_t CAM0L; /*!< [0x000c] CAM0 Least Significant Word Register */ + __IO uint32_t CAM1M; /*!< [0x0010] CAM1 Most Significant Word Register */ + __IO uint32_t CAM1L; /*!< [0x0014] CAM1 Least Significant Word Register */ + __IO uint32_t CAM2M; /*!< [0x0018] CAM2 Most Significant Word Register */ + __IO uint32_t CAM2L; /*!< [0x001c] CAM2 Least Significant Word Register */ + __IO uint32_t CAM3M; /*!< [0x0020] CAM3 Most Significant Word Register */ + __IO uint32_t CAM3L; /*!< [0x0024] CAM3 Least Significant Word Register */ + __IO uint32_t CAM4M; /*!< [0x0028] CAM4 Most Significant Word Register */ + __IO uint32_t CAM4L; /*!< [0x002c] CAM4 Least Significant Word Register */ + __IO uint32_t CAM5M; /*!< [0x0030] CAM5 Most Significant Word Register */ + __IO uint32_t CAM5L; /*!< [0x0034] CAM5 Least Significant Word Register */ + __IO uint32_t CAM6M; /*!< [0x0038] CAM6 Most Significant Word Register */ + __IO uint32_t CAM6L; /*!< [0x003c] CAM6 Least Significant Word Register */ + __IO uint32_t CAM7M; /*!< [0x0040] CAM7 Most Significant Word Register */ + __IO uint32_t CAM7L; /*!< [0x0044] CAM7 Least Significant Word Register */ + __IO uint32_t CAM8M; /*!< [0x0048] CAM8 Most Significant Word Register */ + __IO uint32_t CAM8L; /*!< [0x004c] CAM8 Least Significant Word Register */ + __IO uint32_t CAM9M; /*!< [0x0050] CAM9 Most Significant Word Register */ + __IO uint32_t CAM9L; /*!< [0x0054] CAM9 Least Significant Word Register */ + __IO uint32_t CAM10M; /*!< [0x0058] CAM10 Most Significant Word Register */ + __IO uint32_t CAM10L; /*!< [0x005c] CAM10 Least Significant Word Register */ + __IO uint32_t CAM11M; /*!< [0x0060] CAM11 Most Significant Word Register */ + __IO uint32_t CAM11L; /*!< [0x0064] CAM11 Least Significant Word Register */ + __IO uint32_t CAM12M; /*!< [0x0068] CAM12 Most Significant Word Register */ + __IO uint32_t CAM12L; /*!< [0x006c] CAM12 Least Significant Word Register */ + __IO uint32_t CAM13M; /*!< [0x0070] CAM13 Most Significant Word Register */ + __IO uint32_t CAM13L; /*!< [0x0074] CAM13 Least Significant Word Register */ + __IO uint32_t CAM14M; /*!< [0x0078] CAM14 Most Significant Word Register */ + __IO uint32_t CAM14L; /*!< [0x007c] CAM14 Least Significant Word Register */ + __IO uint32_t CAM15MSB; /*!< [0x0080] CAM15 Most Significant Word Register */ + __IO uint32_t CAM15LSB; /*!< [0x0084] CAM15 Least Significant Word Register */ + __IO uint32_t TXDSA; /*!< [0x0088] Transmit Descriptor Link List Start Address Register */ + __IO uint32_t RXDSA; /*!< [0x008c] Receive Descriptor Link List Start Address Register */ + __IO uint32_t CTL; /*!< [0x0090] MAC Control Register */ + __IO uint32_t MIIMDAT; /*!< [0x0094] MII Management Data Register */ + __IO uint32_t MIIMCTL; /*!< [0x0098] MII Management Control and Address Register */ + __IO uint32_t FIFOCTL; /*!< [0x009c] FIFO Threshold Control Register */ + __O uint32_t TXST; /*!< [0x00a0] Transmit Start Demand Register */ + __O uint32_t RXST; /*!< [0x00a4] Receive Start Demand Register */ + __IO uint32_t MRFL; /*!< [0x00a8] Maximum Receive Frame Control Register */ + __IO uint32_t INTEN; /*!< [0x00ac] MAC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x00b0] MAC Interrupt Status Register */ + __IO uint32_t GENSTS; /*!< [0x00b4] MAC General Status Register */ + __IO uint32_t MPCNT; /*!< [0x00b8] Missed Packet Count Register */ + __I uint32_t RPCNT; /*!< [0x00bc] MAC Receive Pause Count Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[2]; + /** @endcond */ + __IO uint32_t FRSTS; /*!< [0x00c8] DMA Receive Frame Status Register */ + __I uint32_t CTXDSA; /*!< [0x00cc] Current Transmit Descriptor Start Address Register */ + __I uint32_t CTXBSA; /*!< [0x00d0] Current Transmit Buffer Start Address Register */ + __I uint32_t CRXDSA; /*!< [0x00d4] Current Receive Descriptor Start Address Register */ + __I uint32_t CRXBSA; /*!< [0x00d8] Current Receive Buffer Start Address Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[9]; + /** @endcond */ + __IO uint32_t TSCTL; /*!< [0x0100] Time Stamp Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[3]; + /** @endcond */ + __I uint32_t TSSEC; /*!< [0x0110] Time Stamp Counter Second Register */ + __I uint32_t TSSUBSEC; /*!< [0x0114] Time Stamp Counter Sub Second Register */ + __IO uint32_t TSINC; /*!< [0x0118] Time Stamp Increment Register */ + __IO uint32_t TSADDEND; /*!< [0x011c] Time Stamp Addend Register */ + __IO uint32_t UPDSEC; /*!< [0x0120] Time Stamp Update Second Register */ + __IO uint32_t UPDSUBSEC; /*!< [0x0124] Time Stamp Update Sub Second Register */ + __IO uint32_t ALMSEC; /*!< [0x0128] Time Stamp Alarm Second Register */ + __IO uint32_t ALMSUBSEC; /*!< [0x012c] Time Stamp Alarm Sub Second Register */ + +} EMAC_T; + +/** + @addtogroup EMAC_CONST EMAC Bit Field Definition + Constant Definitions for EMAC Controller +@{ */ + +#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC_T::CAMCTL: AUP Position */ +#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC_T::CAMCTL: AUP Mask */ + +#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC_T::CAMCTL: AMP Position */ +#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC_T::CAMCTL: AMP Mask */ + +#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC_T::CAMCTL: ABP Position */ +#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC_T::CAMCTL: ABP Mask */ + +#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC_T::CAMCTL: COMPEN Position */ +#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC_T::CAMCTL: COMPEN Mask */ + +#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC_T::CAMCTL: CMPEN Position */ +#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC_T::CAMCTL: CMPEN Mask */ + +#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC_T::CAMEN: CAMxEN Position */ +#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC_T::CAMEN: CAMxEN Mask */ + +#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC_T::CAM0M: MACADDR2 Position */ +#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC_T::CAM0M: MACADDR2 Mask */ + +#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC_T::CAM0M: MACADDR3 Position */ +#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC_T::CAM0M: MACADDR3 Mask */ + +#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC_T::CAM0M: MACADDR4 Position */ +#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC_T::CAM0M: MACADDR4 Mask */ + +#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC_T::CAM0M: MACADDR5 Position */ +#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC_T::CAM0M: MACADDR5 Mask */ + +#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC_T::CAM0L: MACADDR0 Position */ +#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC_T::CAM0L: MACADDR0 Mask */ + +#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC_T::CAM0L: MACADDR1 Position */ +#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC_T::CAM0L: MACADDR1 Mask */ + +#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC_T::CAM1M: MACADDR2 Position */ +#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC_T::CAM1M: MACADDR2 Mask */ + +#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC_T::CAM1M: MACADDR3 Position */ +#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC_T::CAM1M: MACADDR3 Mask */ + +#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC_T::CAM1M: MACADDR4 Position */ +#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC_T::CAM1M: MACADDR4 Mask */ + +#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC_T::CAM1M: MACADDR5 Position */ +#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC_T::CAM1M: MACADDR5 Mask */ + +#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC_T::CAM1L: MACADDR0 Position */ +#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC_T::CAM1L: MACADDR0 Mask */ + +#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC_T::CAM1L: MACADDR1 Position */ +#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC_T::CAM1L: MACADDR1 Mask */ + +#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC_T::CAM2M: MACADDR2 Position */ +#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC_T::CAM2M: MACADDR2 Mask */ + +#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC_T::CAM2M: MACADDR3 Position */ +#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC_T::CAM2M: MACADDR3 Mask */ + +#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC_T::CAM2M: MACADDR4 Position */ +#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC_T::CAM2M: MACADDR4 Mask */ + +#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC_T::CAM2M: MACADDR5 Position */ +#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC_T::CAM2M: MACADDR5 Mask */ + +#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC_T::CAM2L: MACADDR0 Position */ +#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC_T::CAM2L: MACADDR0 Mask */ + +#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC_T::CAM2L: MACADDR1 Position */ +#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC_T::CAM2L: MACADDR1 Mask */ + +#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC_T::CAM3M: MACADDR2 Position */ +#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC_T::CAM3M: MACADDR2 Mask */ + +#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC_T::CAM3M: MACADDR3 Position */ +#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC_T::CAM3M: MACADDR3 Mask */ + +#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC_T::CAM3M: MACADDR4 Position */ +#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC_T::CAM3M: MACADDR4 Mask */ + +#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC_T::CAM3M: MACADDR5 Position */ +#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC_T::CAM3M: MACADDR5 Mask */ + +#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC_T::CAM3L: MACADDR0 Position */ +#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC_T::CAM3L: MACADDR0 Mask */ + +#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC_T::CAM3L: MACADDR1 Position */ +#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC_T::CAM3L: MACADDR1 Mask */ + +#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC_T::CAM4M: MACADDR2 Position */ +#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC_T::CAM4M: MACADDR2 Mask */ + +#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC_T::CAM4M: MACADDR3 Position */ +#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC_T::CAM4M: MACADDR3 Mask */ + +#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC_T::CAM4M: MACADDR4 Position */ +#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC_T::CAM4M: MACADDR4 Mask */ + +#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC_T::CAM4M: MACADDR5 Position */ +#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC_T::CAM4M: MACADDR5 Mask */ + +#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC_T::CAM4L: MACADDR0 Position */ +#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC_T::CAM4L: MACADDR0 Mask */ + +#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC_T::CAM4L: MACADDR1 Position */ +#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC_T::CAM4L: MACADDR1 Mask */ + +#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC_T::CAM5M: MACADDR2 Position */ +#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC_T::CAM5M: MACADDR2 Mask */ + +#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC_T::CAM5M: MACADDR3 Position */ +#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC_T::CAM5M: MACADDR3 Mask */ + +#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC_T::CAM5M: MACADDR4 Position */ +#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC_T::CAM5M: MACADDR4 Mask */ + +#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC_T::CAM5M: MACADDR5 Position */ +#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC_T::CAM5M: MACADDR5 Mask */ + +#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC_T::CAM5L: MACADDR0 Position */ +#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC_T::CAM5L: MACADDR0 Mask */ + +#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC_T::CAM5L: MACADDR1 Position */ +#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC_T::CAM5L: MACADDR1 Mask */ + +#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC_T::CAM6M: MACADDR2 Position */ +#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC_T::CAM6M: MACADDR2 Mask */ + +#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC_T::CAM6M: MACADDR3 Position */ +#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC_T::CAM6M: MACADDR3 Mask */ + +#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC_T::CAM6M: MACADDR4 Position */ +#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC_T::CAM6M: MACADDR4 Mask */ + +#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC_T::CAM6M: MACADDR5 Position */ +#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC_T::CAM6M: MACADDR5 Mask */ + +#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC_T::CAM6L: MACADDR0 Position */ +#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC_T::CAM6L: MACADDR0 Mask */ + +#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC_T::CAM6L: MACADDR1 Position */ +#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC_T::CAM6L: MACADDR1 Mask */ + +#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC_T::CAM7M: MACADDR2 Position */ +#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC_T::CAM7M: MACADDR2 Mask */ + +#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC_T::CAM7M: MACADDR3 Position */ +#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC_T::CAM7M: MACADDR3 Mask */ + +#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC_T::CAM7M: MACADDR4 Position */ +#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC_T::CAM7M: MACADDR4 Mask */ + +#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC_T::CAM7M: MACADDR5 Position */ +#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC_T::CAM7M: MACADDR5 Mask */ + +#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC_T::CAM7L: MACADDR0 Position */ +#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC_T::CAM7L: MACADDR0 Mask */ + +#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC_T::CAM7L: MACADDR1 Position */ +#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC_T::CAM7L: MACADDR1 Mask */ + +#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC_T::CAM8M: MACADDR2 Position */ +#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC_T::CAM8M: MACADDR2 Mask */ + +#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC_T::CAM8M: MACADDR3 Position */ +#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC_T::CAM8M: MACADDR3 Mask */ + +#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC_T::CAM8M: MACADDR4 Position */ +#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC_T::CAM8M: MACADDR4 Mask */ + +#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC_T::CAM8M: MACADDR5 Position */ +#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC_T::CAM8M: MACADDR5 Mask */ + +#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC_T::CAM8L: MACADDR0 Position */ +#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC_T::CAM8L: MACADDR0 Mask */ + +#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC_T::CAM8L: MACADDR1 Position */ +#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC_T::CAM8L: MACADDR1 Mask */ + +#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC_T::CAM9M: MACADDR2 Position */ +#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC_T::CAM9M: MACADDR2 Mask */ + +#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC_T::CAM9M: MACADDR3 Position */ +#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC_T::CAM9M: MACADDR3 Mask */ + +#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC_T::CAM9M: MACADDR4 Position */ +#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC_T::CAM9M: MACADDR4 Mask */ + +#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC_T::CAM9M: MACADDR5 Position */ +#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC_T::CAM9M: MACADDR5 Mask */ + +#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC_T::CAM9L: MACADDR0 Position */ +#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC_T::CAM9L: MACADDR0 Mask */ + +#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC_T::CAM9L: MACADDR1 Position */ +#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC_T::CAM9L: MACADDR1 Mask */ + +#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC_T::CAM10M: MACADDR2 Position */ +#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC_T::CAM10M: MACADDR2 Mask */ + +#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC_T::CAM10M: MACADDR3 Position */ +#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC_T::CAM10M: MACADDR3 Mask */ + +#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC_T::CAM10M: MACADDR4 Position */ +#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC_T::CAM10M: MACADDR4 Mask */ + +#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC_T::CAM10M: MACADDR5 Position */ +#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC_T::CAM10M: MACADDR5 Mask */ + +#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC_T::CAM10L: MACADDR0 Position */ +#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC_T::CAM10L: MACADDR0 Mask */ + +#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC_T::CAM10L: MACADDR1 Position */ +#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC_T::CAM10L: MACADDR1 Mask */ + +#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC_T::CAM11M: MACADDR2 Position */ +#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC_T::CAM11M: MACADDR2 Mask */ + +#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC_T::CAM11M: MACADDR3 Position */ +#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC_T::CAM11M: MACADDR3 Mask */ + +#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC_T::CAM11M: MACADDR4 Position */ +#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC_T::CAM11M: MACADDR4 Mask */ + +#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC_T::CAM11M: MACADDR5 Position */ +#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC_T::CAM11M: MACADDR5 Mask */ + +#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC_T::CAM11L: MACADDR0 Position */ +#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC_T::CAM11L: MACADDR0 Mask */ + +#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC_T::CAM11L: MACADDR1 Position */ +#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC_T::CAM11L: MACADDR1 Mask */ + +#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC_T::CAM12M: MACADDR2 Position */ +#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC_T::CAM12M: MACADDR2 Mask */ + +#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC_T::CAM12M: MACADDR3 Position */ +#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC_T::CAM12M: MACADDR3 Mask */ + +#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC_T::CAM12M: MACADDR4 Position */ +#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC_T::CAM12M: MACADDR4 Mask */ + +#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC_T::CAM12M: MACADDR5 Position */ +#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC_T::CAM12M: MACADDR5 Mask */ + +#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC_T::CAM12L: MACADDR0 Position */ +#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC_T::CAM12L: MACADDR0 Mask */ + +#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC_T::CAM12L: MACADDR1 Position */ +#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC_T::CAM12L: MACADDR1 Mask */ + +#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC_T::CAM13M: MACADDR2 Position */ +#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC_T::CAM13M: MACADDR2 Mask */ + +#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC_T::CAM13M: MACADDR3 Position */ +#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC_T::CAM13M: MACADDR3 Mask */ + +#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC_T::CAM13M: MACADDR4 Position */ +#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC_T::CAM13M: MACADDR4 Mask */ + +#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC_T::CAM13M: MACADDR5 Position */ +#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC_T::CAM13M: MACADDR5 Mask */ + +#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC_T::CAM13L: MACADDR0 Position */ +#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC_T::CAM13L: MACADDR0 Mask */ + +#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC_T::CAM13L: MACADDR1 Position */ +#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC_T::CAM13L: MACADDR1 Mask */ + +#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC_T::CAM14M: MACADDR2 Position */ +#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC_T::CAM14M: MACADDR2 Mask */ + +#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC_T::CAM14M: MACADDR3 Position */ +#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC_T::CAM14M: MACADDR3 Mask */ + +#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC_T::CAM14M: MACADDR4 Position */ +#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC_T::CAM14M: MACADDR4 Mask */ + +#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC_T::CAM14M: MACADDR5 Position */ +#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC_T::CAM14M: MACADDR5 Mask */ + +#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC_T::CAM14L: MACADDR0 Position */ +#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC_T::CAM14L: MACADDR0 Mask */ + +#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC_T::CAM14L: MACADDR1 Position */ +#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC_T::CAM14L: MACADDR1 Mask */ + +#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC_T::CAM15MSB: OPCODE Position */ +#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC_T::CAM15MSB: OPCODE Mask */ + +#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC_T::CAM15MSB: LENGTH Position */ +#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC_T::CAM15MSB: LENGTH Mask */ + +#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC_T::CAM15LSB: OPERAND Position */ +#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC_T::CAM15LSB: OPERAND Mask */ + +#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC_T::TXDSA: TXDSA Position */ +#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC_T::TXDSA: TXDSA Mask */ + +#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC_T::RXDSA: RXDSA Position */ +#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC_T::RXDSA: RXDSA Mask */ + +#define EMAC_CTL_RXON_Pos (0) /*!< EMAC_T::CTL: RXON Position */ +#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC_T::CTL: RXON Mask */ + +#define EMAC_CTL_ALP_Pos (1) /*!< EMAC_T::CTL: ALP Position */ +#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC_T::CTL: ALP Mask */ + +#define EMAC_CTL_ARP_Pos (2) /*!< EMAC_T::CTL: ARP Position */ +#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC_T::CTL: ARP Mask */ + +#define EMAC_CTL_ACP_Pos (3) /*!< EMAC_T::CTL: ACP Position */ +#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC_T::CTL: ACP Mask */ + +#define EMAC_CTL_AEP_Pos (4) /*!< EMAC_T::CTL: AEP Position */ +#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC_T::CTL: AEP Mask */ + +#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC_T::CTL: STRIPCRC Position */ +#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC_T::CTL: STRIPCRC Mask */ + +#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC_T::CTL: WOLEN Position */ +#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC_T::CTL: WOLEN Mask */ + +#define EMAC_CTL_TXON_Pos (8) /*!< EMAC_T::CTL: TXON Position */ +#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC_T::CTL: TXON Mask */ + +#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC_T::CTL: NODEF Position */ +#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC_T::CTL: NODEF Mask */ + +#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC_T::CTL: SDPZ Position */ +#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC_T::CTL: SDPZ Mask */ + +#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC_T::CTL: SQECHKEN Position */ +#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC_T::CTL: SQECHKEN Mask */ + +#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC_T::CTL: FUDUP Position */ +#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC_T::CTL: FUDUP Mask */ + +#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC_T::CTL: RMIIRXCTL Position */ +#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC_T::CTL: RMIIRXCTL Mask */ + +#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC_T::CTL: OPMODE Position */ +#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC_T::CTL: OPMODE Mask */ + +#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC_T::CTL: RMIIEN Position */ +#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC_T::CTL: RMIIEN Mask */ + +#define EMAC_CTL_RST_Pos (24) /*!< EMAC_T::CTL: RST Position */ +#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC_T::CTL: RST Mask */ + +#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC_T::MIIMDAT: DATA Position */ +#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC_T::MIIMDAT: DATA Mask */ + +#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC_T::MIIMCTL: PHYREG Position */ +#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC_T::MIIMCTL: PHYREG Mask */ + +#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC_T::MIIMCTL: PHYADDR Position */ +#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC_T::MIIMCTL: PHYADDR Mask */ + +#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC_T::MIIMCTL: WRITE Position */ +#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC_T::MIIMCTL: WRITE Mask */ + +#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC_T::MIIMCTL: BUSY Position */ +#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC_T::MIIMCTL: BUSY Mask */ + +#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC_T::MIIMCTL: PREAMSP Position */ +#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC_T::MIIMCTL: PREAMSP Mask */ + +#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC_T::MIIMCTL: MDCON Position */ +#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC_T::MIIMCTL: MDCON Mask */ + +#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC_T::FIFOCTL: RXFIFOTH Position */ +#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: RXFIFOTH Mask */ + +#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC_T::FIFOCTL: TXFIFOTH Position */ +#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC_T::FIFOCTL: TXFIFOTH Mask */ + +#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC_T::FIFOCTL: BURSTLEN Position */ +#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC_T::FIFOCTL: BURSTLEN Mask */ + +#define EMAC_TXST_TXST_Pos (0) /*!< EMAC_T::TXST: TXST Position */ +#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC_T::TXST: TXST Mask */ + +#define EMAC_RXST_RXST_Pos (0) /*!< EMAC_T::RXST: RXST Position */ +#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC_T::RXST: RXST Mask */ + +#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC_T::MRFL: MRFL Position */ +#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC_T::MRFL: MRFL Mask */ + +#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC_T::INTEN: RXIEN Position */ +#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC_T::INTEN: RXIEN Mask */ + +#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC_T::INTEN: CRCEIEN Position */ +#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC_T::INTEN: CRCEIEN Mask */ + +#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC_T::INTEN: RXOVIEN Position */ +#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC_T::INTEN: RXOVIEN Mask */ + +#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC_T::INTEN: LPIEN Position */ +#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC_T::INTEN: LPIEN Mask */ + +#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC_T::INTEN: RXGDIEN Position */ +#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC_T::INTEN: RXGDIEN Mask */ + +#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC_T::INTEN: ALIEIEN Position */ +#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC_T::INTEN: ALIEIEN Mask */ + +#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC_T::INTEN: RPIEN Position */ +#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC_T::INTEN: RPIEN Mask */ + +#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC_T::INTEN: MPCOVIEN Position */ +#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC_T::INTEN: MPCOVIEN Mask */ + +#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC_T::INTEN: MFLEIEN Position */ +#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC_T::INTEN: MFLEIEN Mask */ + +#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC_T::INTEN: DENIEN Position */ +#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC_T::INTEN: DENIEN Mask */ + +#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC_T::INTEN: RDUIEN Position */ +#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC_T::INTEN: RDUIEN Mask */ + +#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC_T::INTEN: RXBEIEN Position */ +#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC_T::INTEN: RXBEIEN Mask */ + +#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC_T::INTEN: CFRIEN Position */ +#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC_T::INTEN: CFRIEN Mask */ + +#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC_T::INTEN: WOLIEN Position */ +#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC_T::INTEN: WOLIEN Mask */ + +#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC_T::INTEN: TXIEN Position */ +#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC_T::INTEN: TXIEN Mask */ + +#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC_T::INTEN: TXUDIEN Position */ +#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC_T::INTEN: TXUDIEN Mask */ + +#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC_T::INTEN: TXCPIEN Position */ +#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC_T::INTEN: TXCPIEN Mask */ + +#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC_T::INTEN: EXDEFIEN Position */ +#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC_T::INTEN: EXDEFIEN Mask */ + +#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC_T::INTEN: NCSIEN Position */ +#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC_T::INTEN: NCSIEN Mask */ + +#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC_T::INTEN: TXABTIEN Position */ +#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC_T::INTEN: TXABTIEN Mask */ + +#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC_T::INTEN: LCIEN Position */ +#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC_T::INTEN: LCIEN Mask */ + +#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC_T::INTEN: TDUIEN Position */ +#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC_T::INTEN: TDUIEN Mask */ + +#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC_T::INTEN: TXBEIEN Position */ +#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC_T::INTEN: TXBEIEN Mask */ + +#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC_T::INTEN: TSALMIEN Position */ +#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC_T::INTEN: TSALMIEN Mask */ + +#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC_T::INTSTS: RXIF Position */ +#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC_T::INTSTS: RXIF Mask */ + +#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC_T::INTSTS: CRCEIF Position */ +#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC_T::INTSTS: CRCEIF Mask */ + +#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC_T::INTSTS: RXOVIF Position */ +#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC_T::INTSTS: RXOVIF Mask */ + +#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC_T::INTSTS: LPIF Position */ +#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC_T::INTSTS: LPIF Mask */ + +#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC_T::INTSTS: RXGDIF Position */ +#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC_T::INTSTS: RXGDIF Mask */ + +#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC_T::INTSTS: ALIEIF Position */ +#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC_T::INTSTS: ALIEIF Mask */ + +#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC_T::INTSTS: RPIF Position */ +#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC_T::INTSTS: RPIF Mask */ + +#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC_T::INTSTS: MPCOVIF Position */ +#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC_T::INTSTS: MPCOVIF Mask */ + +#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC_T::INTSTS: MFLEIF Position */ +#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC_T::INTSTS: MFLEIF Mask */ + +#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC_T::INTSTS: DENIF Position */ +#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC_T::INTSTS: DENIF Mask */ + +#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC_T::INTSTS: RDUIF Position */ +#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC_T::INTSTS: RDUIF Mask */ + +#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC_T::INTSTS: RXBEIF Position */ +#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC_T::INTSTS: RXBEIF Mask */ + +#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC_T::INTSTS: CFRIF Position */ +#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC_T::INTSTS: CFRIF Mask */ + +#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC_T::INTSTS: WOLIF Position */ +#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC_T::INTSTS: WOLIF Mask */ + +#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC_T::INTSTS: TXIF Position */ +#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC_T::INTSTS: TXIF Mask */ + +#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC_T::INTSTS: TXUDIF Position */ +#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC_T::INTSTS: TXUDIF Mask */ + +#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC_T::INTSTS: TXCPIF Position */ +#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC_T::INTSTS: TXCPIF Mask */ + +#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC_T::INTSTS: EXDEFIF Position */ +#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC_T::INTSTS: EXDEFIF Mask */ + +#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC_T::INTSTS: NCSIF Position */ +#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC_T::INTSTS: NCSIF Mask */ + +#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC_T::INTSTS: TXABTIF Position */ +#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC_T::INTSTS: TXABTIF Mask */ + +#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC_T::INTSTS: LCIF Position */ +#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC_T::INTSTS: LCIF Mask */ + +#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC_T::INTSTS: TDUIF Position */ +#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC_T::INTSTS: TDUIF Mask */ + +#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC_T::INTSTS: TXBEIF Position */ +#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC_T::INTSTS: TXBEIF Mask */ + +#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC_T::INTSTS: TSALMIF Position */ +#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC_T::INTSTS: TSALMIF Mask */ + +#define EMAC_GENSTS_CFR_Pos (0) /*!< EMAC_T::GENSTS: CFR Position */ +#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos) /*!< EMAC_T::GENSTS: CFR Mask */ + +#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC_T::GENSTS: RXHALT Position */ +#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC_T::GENSTS: RXHALT Mask */ + +#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC_T::GENSTS: RXFFULL Position */ +#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC_T::GENSTS: RXFFULL Mask */ + +#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC_T::GENSTS: COLCNT Position */ +#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC_T::GENSTS: COLCNT Mask */ + +#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC_T::GENSTS: DEF Position */ +#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC_T::GENSTS: DEF Mask */ + +#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC_T::GENSTS: TXPAUSED Position */ +#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC_T::GENSTS: TXPAUSED Mask */ + +#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC_T::GENSTS: SQE Position */ +#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC_T::GENSTS: SQE Mask */ + +#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC_T::GENSTS: TXHALT Position */ +#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC_T::GENSTS: TXHALT Mask */ + +#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC_T::GENSTS: RPSTS Position */ +#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC_T::GENSTS: RPSTS Mask */ + +#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC_T::MPCNT: MPCNT Position */ +#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC_T::MPCNT: MPCNT Mask */ + +#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC_T::RPCNT: RPCNT Position */ +#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC_T::RPCNT: RPCNT Mask */ + +#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC_T::FRSTS: RXFLT Position */ +#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC_T::FRSTS: RXFLT Mask */ + +#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC_T::CTXDSA: CTXDSA Position */ +#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC_T::CTXDSA: CTXDSA Mask */ + +#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC_T::CTXBSA: CTXBSA Position */ +#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC_T::CTXBSA: CTXBSA Mask */ + +#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC_T::CRXDSA: CRXDSA Position */ +#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC_T::CRXDSA: CRXDSA Mask */ + +#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC_T::CRXBSA: CRXBSA Position */ +#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC_T::CRXBSA: CRXBSA Mask */ + +#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC_T::TSCTL: TSEN Position */ +#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC_T::TSCTL: TSEN Mask */ + +#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC_T::TSCTL: TSIEN Position */ +#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC_T::TSCTL: TSIEN Mask */ + +#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC_T::TSCTL: TSMODE Position */ +#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC_T::TSCTL: TSMODE Mask */ + +#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC_T::TSCTL: TSUPDATE Position */ +#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC_T::TSCTL: TSUPDATE Mask */ + +#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC_T::TSCTL: TSALMEN Position */ +#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC_T::TSCTL: TSALMEN Mask */ + +#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC_T::TSSEC: SEC Position */ +#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC_T::TSSEC: SEC Mask */ + +#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::TSSUBSEC: SUBSEC Position */ +#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC_T::TSSUBSEC: SUBSEC Mask */ + +#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC_T::TSINC: CNTINC Position */ +#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC_T::TSINC: CNTINC Mask */ + +#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC_T::TSADDEND: ADDEND Position */ +#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC_T::TSADDEND: ADDEND Mask */ + +#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC_T::UPDSEC: SEC Position */ +#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC_T::UPDSEC: SEC Mask */ + +#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::UPDSUBSEC: SUBSEC Position */ +#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC_T::UPDSUBSEC: SUBSEC Mask */ + +#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC_T::ALMSEC: SEC Position */ +#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC_T::ALMSEC: SEC Mask */ + +#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC_T::ALMSUBSEC: SUBSEC Position */ +#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC_T::ALMSUBSEC: SUBSEC Mask */ + +/**@}*/ /* EMAC_CONST */ +/**@}*/ /* end of EMAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EMAC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/epwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/epwm_reg.h new file mode 100644 index 0000000..40ca9f9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/epwm_reg.h @@ -0,0 +1,5418 @@ +/**************************************************************************//** + * @file epwm_reg.h + * @version V1.00 + * @brief EPWM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_REG_H__ +#define __EPWM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EPWM Pulse Width Modulation Controller(EPWM) + Memory Mapped Structure for EPWM Controller +@{ */ + +typedef struct +{ + /** + * @var ECAPDAT_T::RCAPDAT + * Offset: 0x20C EPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var ECAPDAT_T::FCAPDAT + * Offset: 0x210 EPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ +} ECAPDAT_T; + +typedef struct +{ + + + /** + * @var EPWM_T::CTL0 + * Offset: 0x00 EPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the center point of a period + * |[8] |WINLDEN0 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[9] |WINLDEN1 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[10] |WINLDEN2 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[11] |WINLDEN3 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[12] |WINLDEN4 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[13] |WINLDEN5 |Window Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point of each period when valid reload window is set + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success. + * |[16] |IMMLDEN0 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[24] |GROUPEN |Group Function Enable Bit + * | | |0 = The output waveform of each EPWM channel are independent. + * | | |1 = Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disabled. + * | | |1 = ICE debug mode counter halt Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects EPWM output. + * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::CTL1 + * Offset: 0x04 EPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[16] |CNTMODE0 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[17] |CNTMODE1 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[18] |CNTMODE2 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[19] |CNTMODE3 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[20] |CNTMODE4 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[21] |CNTMODE5 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[24] |OUTMODE0 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[25] |OUTMODE2 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[26] |OUTMODE4 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var EPWM_T::SYNC + * Offset: 0x08 EPWM Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHSEN0 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[1] |PHSEN2 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[2] |PHSEN4 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits + * | | |0 = Noise filter of input pin EPWM0_SYNC_IN Disabled. + * | | |1 = Noise filter of input pin EPWM0_SYNC_IN Enabled. + * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count + * | | |The register bits control the counter number of edge detector. + * |[23] |SINPINV |SYNC Input Pin Inverse + * | | |0 = The state of pin SYNC is passed to the negative edge detector. + * | | |1 = The inversed state of pin SYNC is passed to the negative edge detector. + * |[24] |PHSDIR0 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[25] |PHSDIR2 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[26] |PHSDIR4 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * @var EPWM_T::SWSYNC + * Offset: 0x0C EPWM Software Control Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWSYNC0 |Software SYNC Function (Write Only) + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. + * |[1] |SWSYNC2 |Software SYNC Function (Write Only) + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. + * |[2] |SWSYNC4 |Software SYNC Function (Write Only) + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit. + * @var EPWM_T::CLKSRC + * Offset: 0x10 EPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var EPWM_T::CNTEN + * Offset: 0x20 EPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[1] |CNTEN1 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[2] |CNTEN2 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[3] |CNTEN3 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[4] |CNTEN4 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * |[5] |CNTEN5 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler stop running. + * | | |1 = EPWM Counter and clock prescaler start running. + * @var EPWM_T::CNTCLR + * Offset: 0x24 EPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * @var EPWM_T::LOAD + * Offset: 0x28 EPWM Load Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LOAD0 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[1] |LOAD1 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[2] |LOAD2 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[3] |LOAD3 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[4] |LOAD4 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * |[5] |LOAD5 |Re-load EPWM Comparator Register Control Bit + * | | |This bit is software write to reload EPWM_CMPDATn, n=0~5. Hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * @var EPWM_T::PERIOD[6] + * Offset: 0x30 EPWM Period Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Down-Count mode: + * | | |In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * (CLKPSC+1) * EPWM_CLK . + * | | |Up-Down-Count mode: + * | | |In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * (CLKPSC+1) * EPWM_CLK. + * @var EPWM_T::CMPDAT[6] + * Offset: 0x50 EPWM Comparator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC/DAC. + * | | |In independent mode, EPWM_CMPDATn, n=0,1..5 denote as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, EPWM_CMPDAT0, EPWM_CMPDAT 2, EPWM_CMPDAT4 denote as first compared point, and EPWM_CMPDAT1, EPWM_CMPDAT3, EPWM_CMPDAT5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::PHS[3] + * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. + * @var EPWM_T::CNT[6] + * Offset: 0x90 EPWM Counter Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var EPWM_T::WGCTL0 + * Offset: 0xB0 EPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[3:2] |ZPCTL1 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[5:4] |ZPCTL2 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[7:6] |ZPCTL3 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[9:8] |ZPCTL4 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[11:10] |ZPCTL5 |EPWM Zero Point Control + * | | |EPWM can control output level when EPWM counter counts to 0. + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * |[17:16] |PRDPCTL0 |EPWM Period or Center Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |EPWM Period or Center Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |EPWM Period or Center Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |EPWM Period or Center Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |EPWM Period or Center Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |EPWM Period or Center Point Control + * | | |EPWM can control output level when EPWM counter counts to (PERIODn+1). + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * @var EPWM_T::WGCTL1 + * Offset: 0xB4 EPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control + * | | |EPWM can control output level when EPWM counter counts up to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control + * | | |EPWM can control output level when EPWM counter counts down to CMP. + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * @var EPWM_T::MSKEN + * Offset: 0xB8 EPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled + * | | |The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDATn data. + * @var EPWM_T::MSK + * Offset: 0xBC EPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[1] |MSKDAT1 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[2] |MSKDAT2 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[3] |MSKDAT3 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[4] |MSKDAT4 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * |[5] |MSKDAT5 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWMn output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM channel n. + * | | |1 = Output logic high to EPWM channel n. + * @var EPWM_T::BNF + * Offset: 0xC0 EPWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 0 Disabled. + * | | |1 = Noise filter of EPWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect. + * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 1 Disabled. + * | | |1 = Noise filter of EPWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect. + * |[16] |BK0SRC |Brake 0 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |For EPWM1 setting: + * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * |[24] |BK1SRC |Brake 1 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |For EPWM1 setting: + * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * @var EPWM_T::FAILBRK + * Offset: 0xC4 EPWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by BOD Disabled. + * | | |1 = Brake Function triggered by BOD Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var EPWM_T::BRKCTL[3] + * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as edge-detect brake source Disabled. + * | | |1 = ACMP0_O as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as edge-detect brake source Disabled. + * | | |1 = ACMP1_O as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[2] |CPO2EBEN |Enable ACMP2_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP2_O as edge-detect brake source Disabled. + * | | |1 = ACMP2_O as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[3] |CPO3EBEN |Enable ACMP3_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP3_O as edge-detect brake source Disabled. + * | | |1 = ACMP3_O as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as level-detect brake source Disabled. + * | | |1 = ACMP0_O as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as level-detect brake source Disabled. + * | | |1 = ACMP1_O as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[10] |CPO2LBEN |Enable ACMP2_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP2_O as level-detect brake source Disabled. + * | | |1 = ACMP2_O as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[11] |CPO3LBEN |Enable ACMP3_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP3_O as level-detect brake source Disabled. + * | | |1 = ACMP3_O as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[20] |EADC0EBEN |Enable EADC0 Result Monitor as Edge-detect Brake Source (Write Protect) + * | | |0 = EADC0RM as edge-detect brake source Disabled. + * | | |1 = EADC0RM as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[21] |EADC1EBEN |Enable EADC1 Result Monitor as Edge-detect Brake Source (Write Protect) + * | | |0 = EADC1RM as edge-detect brake source Disabled. + * | | |1 = EADC1RM as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[22] |EADC2EBEN |Enable EADC2 Result Monitor as Edge-detect Brake Source (Write Protect) + * | | |0 = EADC1RM as edge-detect brake source Disabled. + * | | |1 = EADC1RM as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[28] |EADC0LBEN |Enable EADC0 Result Monitor as Level-detect Brake Source (Write Protect) + * | | |0 = EADC0RM as level-detect brake source Disabled. + * | | |1 = EADC0RM as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[29] |EADC1LBEN |Enable EADC1 Result Monitor as Level-detect Brake Source (Write Protect) + * | | |0 = EADC1RM as level-detect brake source Disabled. + * | | |1 = EADC1RM as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[30] |EADC2LBEN |Enable EADC2 Result Monitor as Level-detect Brake Source (Write Protect) + * | | |0 = EADC2RM as level-detect brake source Disabled. + * | | |1 = EADC2RM as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::POLCTL + * Offset: 0xD4 EPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[1] |PINV1 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[2] |PINV2 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[3] |PINV3 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[4] |PINV4 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * |[5] |PINV5 |EPWM PIN Polar Inverse Control + * | | |The register controls polarity state of EPWMx_CHn output pin. + * | | |0 = EPWMx_CHn output pin polar inverse Disabled. + * | | |1 = EPWMx_CHn output pin polar inverse Enabled. + * @var EPWM_T::POEN + * Offset: 0xD8 EPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[1] |POEN1 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[2] |POEN2 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[3] |POEN3 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[4] |POEN4 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * |[5] |POEN5 |EPWM Pin Output Enable Bits + * | | |0 = EPWMx_CHn pin at tri-state. + * | | |1 = EPWMx_CHn pin in output mode. + * @var EPWM_T::SWBRK + * Offset: 0xDC EPWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::INTEN0 + * Offset: 0xE0 EPWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * @var EPWM_T::INTEN1 + * Offset: 0xE4 EPWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * @var EPWM_T::INTSTS0 + * Offset: 0xE8 EPWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1 + * |[8] |PIF0 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[9] |PIF1 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[10] |PIF2 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[11] |PIF3 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[12] |PIF4 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[13] |PIF5 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * @var EPWM_T::INTSTS1 + * Offset: 0xEC EPWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 edge-detect brake event do not happened. + * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 edge-detect brake event do not happened. + * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 edge-detect brake event do not happened. + * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 edge-detect brake event do not happened. + * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 edge-detect brake event do not happened. + * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 edge-detect brake event do not happened. + * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 level-detect brake event do not happened. + * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 level-detect brake event do not happened. + * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 level-detect brake event do not happened. + * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 level-detect brake event do not happened. + * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 level-detect brake event do not happened. + * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 level-detect brake event do not happened. + * | | |1 = When EEPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 edge-detect brake state is released. + * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 edge-detect brake state is released. + * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 edge-detect brake state is released. + * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 edge-detect brake state is released. + * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 edge-detect brake state is released. + * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 edge-detect brake state is released. + * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 level-detect brake state is released. + * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 level-detect brake state is released. + * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 level-detect brake state is released. + * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 level-detect brake state is released. + * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 level-detect brake state is released. + * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 level-detect brake state is released. + * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * @var EPWM_T::DACTRGEN + * Offset: 0xF4 EPWM Trigger DAC Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[16] |CUTRGEN0 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. + * |[17] |CUTRGEN1 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. + * |[18] |CUTRGEN2 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. + * |[19] |CUTRGEN3 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. + * |[20] |CUTRGEN4 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. + * |[21] |CUTRGEN5 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note 2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4. + * |[24] |CDTRGEN0 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. + * |[25] |CDTRGEN1 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. + * |[26] |CDTRGEN2 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. + * |[27] |CDTRGEN3 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. + * |[28] |CDTRGEN4 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. + * |[29] |CDTRGEN5 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note 1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note 2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4. + * @var EPWM_T::EADCTS0 + * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select + * | | |00000 = EPWM_CH0 zero point. + * | | |00001 = EPWM_CH0 period point. + * | | |00010 = EPWM_CH0 zero or period point. + * | | |00011 = EPWM_CH0 up-count compared point. + * | | |00100 = EPWM_CH0 down-count compared point. + * | | |00101 = EPWM_CH1 zero point. + * | | |00110 = EPWM_CH1 period point. + * | | |00111 = EPWM_CH1 zero or period point. + * | | |01000 = EPWM_CH1 up-count compared point. + * | | |01001 = EPWM_CH1 down-count compared point. + * | | |01010 = EPWM_CH0 up-count free trigger compared point. + * | | |01011 = EPWM_CH0 down-count free trigger compared point. + * | | |01100 = EPWM_CH2 up-count free trigger compared point. + * | | |01101 = EPWM_CH2 down-count free trigger compared point. + * | | |01110 = EPWM_CH4 up-count free trigger compared point. + * | | |01111 = EPWM_CH4 down-count free trigger compared point. + * | | |10000 = EPWM_CH0 Interrupt Flag Accumulator Interrupt. + * | | |10001 = EPWM_CH1 Interrupt Flag Accumulator Interrupt. + * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC Enable Bit + * | | |0 = EPWM_CH0 Trigger EADC function Disabled. + * | | |1 = EPWM_CH0 Trigger EADC function Enabled. + * |[12:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select + * | | |00000 = EPWM_CH0 zero point. + * | | |00001 = EPWM_CH0 period point. + * | | |00010 = EPWM_CH0 zero or period point. + * | | |00011 = EPWM_CH0 up-count compared point. + * | | |00100 = EPWM_CH0 down-count compared point. + * | | |00101 = EPWM_CH1 zero point. + * | | |00110 = EPWM_CH1 period point. + * | | |00111 = EPWM_CH1 zero or period point. + * | | |01000 = EPWM_CH1 up-count compared point. + * | | |01001 = EPWM_CH1 down-count compared point. + * | | |01010 = EPWM_CH0 up-count free trigger compared point. + * | | |01011 = EPWM_CH0 down-count free trigger compared point. + * | | |01100 = EPWM_CH2 up-count free trigger compared point. + * | | |01101 = EPWM_CH2 down-count free trigger compared point. + * | | |01110 = EPWM_CH4 up-count free trigger compared point. + * | | |01111 = EPWM_CH4 down-count free trigger compared point. + * | | |10000 = EPWM_CH0 Interrupt Flag Accumulator Interrupt. + * | | |10001 = EPWM_CH1 Interrupt Flag Accumulator Interrupt. + * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC Enable Bit + * | | |0 = EPWM_CH1 Trigger EADC function Disabled. + * | | |1 = EPWM_CH1 Trigger EADC function Enabled. + * |[20:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select + * | | |00000 = EPWM_CH2 zero point. + * | | |00001 = EPWM_CH2 period point. + * | | |00010 = EPWM_CH2 zero or period point. + * | | |00011 = EPWM_CH2 up-count compared point. + * | | |00100 = EPWM_CH2 down-count compared point. + * | | |00101 = EPWM_CH3 zero point. + * | | |00110 = EPWM_CH3 period point. + * | | |00111 = EPWM_CH3 zero or period point. + * | | |01000 = EPWM_CH3 up-count compared point. + * | | |01001 = EPWM_CH3 down-count compared point. + * | | |01010 = EPWM_CH0 up-count free trigger compared point. + * | | |01011 = EPWM_CH0 down-count free trigger compared point. + * | | |01100 = EPWM_CH2 up-count free trigger compared point. + * | | |01101 = EPWM_CH2 down-count free trigger compared point. + * | | |01110 = EPWM_CH4 up-count free trigger compared point. + * | | |01111 = EPWM_CH4 down-count free trigger compared point. + * | | |10000 = EPWM_CH2 Interrupt Flag Accumulator Interrupt. + * | | |10001 = EPWM_CH3 Interrupt Flag Accumulator Interrupt. + * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC Enable Bit + * | | |0 = EPWM_CH2 Trigger EADC function Disabled. + * | | |1 = EPWM_CH2 Trigger EADC function Enabled. + * |[28:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select + * | | |00000 = EPWM_CH2 zero point. + * | | |00001 = EPWM_CH2 period point. + * | | |00010 = EPWM_CH2 zero or period point. + * | | |00011 = EPWM_CH2 up-count compared point. + * | | |00100 = EPWM_CH2 down-count compared point. + * | | |00101 = EPWM_CH3 zero point. + * | | |00110 = EPWM_CH3 period point. + * | | |00111 = EPWM_CH3 zero or period point. + * | | |01000 = EPWM_CH3 up-count compared point. + * | | |01001 = EPWM_CH3 down-count compared point. + * | | |01010 = EPWM_CH0 up-count free trigger compared point. + * | | |01011 = EPWM_CH0 down-count free trigger compared point. + * | | |01100 = EPWM_CH2 up-count free trigger compared point. + * | | |01101 = EPWM_CH2 down-count free trigger compared point. + * | | |01110 = EPWM_CH4 up-count free trigger compared point. + * | | |01111 = EPWM_CH4 down-count free trigger compared point. + * | | |10000 = EPWM_CH2 Interrupt Flag Accumulator Interrupt. + * | | |10001 = EPWM_CH3 Interrupt Flag Accumulator Interrupt. + * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC Enable Bit + * | | |0 = EPWM_CH3 Trigger EADC function Disabled. + * | | |1 = EPWM_CH3 Trigger EADC function Enabled. + * @var EPWM_T::EADCTS1 + * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select + * | | |00000 = EPWM_CH4 zero point. + * | | |00001 = EPWM_CH4 period point. + * | | |00010 = EPWM_CH4 zero or period point. + * | | |00011 = EPWM_CH4 up-count compared point. + * | | |00100 = EPWM_CH4 down-count compared point. + * | | |00101 = EPWM_CH5 zero point. + * | | |00110 = EPWM_CH5 period point. + * | | |00111 = EPWM_CH5 zero or period point. + * | | |01000 = EPWM_CH5 up-count compared point. + * | | |01001 = EPWM_CH5 down-count compared point. + * | | |01010 = EPWM_CH0 up-count free trigger compared point. + * | | |01011 = EPWM_CH0 down-count free trigger compared point. + * | | |01100 = EPWM_CH2 up-count free trigger compared point. + * | | |01101 = EPWM_CH2 down-count free trigger compared point. + * | | |01110 = EPWM_CH4 up-count free trigger compared point. + * | | |01111 = EPWM_CH4 down-count free trigger compared point. + * | | |10000 = EPWM_CH4 Interrupt Flag Accumulator Interrupt. + * | | |10001 = EPWM_CH5 Interrupt Flag Accumulator Interrupt. + * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC Enable Bit + * | | |0 = EPWM_CH4 Trigger EADC function Disabled. + * | | |1 = EPWM_CH4 Trigger EADC function Enabled. + * |[12:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select + * | | |00000 = EPWM_CH4 zero point. + * | | |00001 = EPWM_CH4 period point. + * | | |00010 = EPWM_CH4 zero or period point. + * | | |00011 = EPWM_CH4 up-count compared point. + * | | |00100 = EPWM_CH4 down-count compared point. + * | | |00101 = EPWM_CH5 zero point. + * | | |00110 = EPWM_CH5 period point. + * | | |00111 = EPWM_CH5 zero or period point. + * | | |01000 = EPWM_CH5 up-count compared point. + * | | |01001 = EPWM_CH5 down-count compared point. + * | | |01010 = EPWM_CH0 up-count free trigger compared point. + * | | |01011 = EPWM_CH0 down-count free trigger compared point. + * | | |01100 = EPWM_CH2 up-count free trigger compared point. + * | | |01101 = EPWM_CH2 down-count free trigger compared point. + * | | |01110 = EPWM_CH4 up-count free trigger compared point. + * | | |01111 = EPWM_CH4 down-count free trigger compared point. + * | | |10000 = EPWM_CH4 Interrupt Flag Accumulator Interrupt. + * | | |10001 = EPWM_CH5 Interrupt Flag Accumulator Interrupt. + * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC Enable Bit + * | | |0 = EPWM_CH5 Trigger EADC function Disabled. + * | | |1 = EPWM_CH5 Trigger EADC function Enabled. + * @var EPWM_T::FTCMPDAT[3] + * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP use to compare with even CNT (EPWM_CNTm[15:0], m=0,2,4) to trigger EADC + * | | |EPWM_FTCMPDAT0_1, EPWM_FTCMPDAT2_3, EPWM_FTCMPDAT4_5 corresponding complementary pairs EPWM_CH0and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::SSCTL + * Offset: 0x110 EPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from EPWM0. + * | | |01 = Synchronous start source come from EPWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var EPWM_T::SSTRG + * Offset: 0x114 EPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. + * @var EPWM_T::LEBCTL + * Offset: 0x118 EPWM Leading Edge Blanking Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit + * | | |0 = EPWM Leading Edge Blanking Disabled. + * | | |1 = EPWM Leading Edge Blanking Enabled. + * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. + * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. + * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. + * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type + * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. + * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. + * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. + * | | |3 = Reserved. + * @var EPWM_T::LEBCNT + * Offset: 0x11C EPWM Leading Edge Blanking Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter + * | | |This counter value decides leading edge blanking window size + * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. + * @var EPWM_T::STATUS + * Offset: 0x120 EPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[8] |SYNCINF0 |Input Synchronization Latched Flag + * | | |0 = No SYNC_IN event has occurred. + * | | |1 = A SYNC_IN event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[9] |SYNCINF2 |Input Synchronization Latched Flag + * | | |0 = No SYNC_IN event has occurred. + * | | |1 = A SYNC_IN event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[10] |SYNCINF4 |Input Synchronization Latched Flag + * | | |0 = No SYNC_IN event has occurred. + * | | |1 = A SYNC_IN event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[16] |EADCTRGF0 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[17] |EADCTRGF1 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[18] |EADCTRGF2 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[19] |EADCTRGF3 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[20] |EADCTRGF4 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[21] |EADCTRGF5 |EADC Start of Conversion Flag + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[24] |DACTRGF |DAC Start of Conversion Flag + * | | |0 = No DAC start of conversion trigger event has occurred. + * | | |1 = A DAC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * @var EPWM_T::IFA[6] + * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn Stop Mode Disabled. + * | | |1 = EPWM_CHn Stop Mode Enabled. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = EPWM_CHn zero point. + * | | |01 = EPWM_CHn period in channel n. + * | | |10 = EPWM_CHn up-count compared point. + * | | |11 = EPWM_CHn down-count compared point. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator disable. + * | | |1 = EPWM_CHn interrupt flag accumulator enable. + * @var EPWM_T::AINTSTS + * Offset: 0x150 EPWM Accumulator Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * @var EPWM_T::AINTEN + * Offset: 0x154 EPWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * @var EPWM_T::APDMACTL + * Offset: 0x158 EPWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN0 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[1] |APDMAEN1 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[2] |APDMAEN2 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[3] |APDMAEN3 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[4] |APDMAEN4 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[5] |APDMAEN5 |Channel n Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * @var EPWM_T::FDEN + * Offset: 0x160 EPWM Fault Detect Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FDEN0 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disabled. + * | | |1 = Fault detect function Enabled. + * |[1] |FDEN1 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disabled. + * | | |1 = Fault detect function Enabled. + * |[2] |FDEN2 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disabled. + * | | |1 = Fault detect function Enabled. + * |[3] |FDEN3 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disabled. + * | | |1 = Fault detect function Enabled. + * |[4] |FDEN4 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disabled. + * | | |1 = Fault detect function Enabled. + * |[5] |FDEN5 |EPWM Fault Detect Function Enable Bit + * | | |0 = Fault detect function Disabled. + * | | |1 = Fault detect function Enabled. + * |[8] |FDODIS0 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enabled. + * | | |1 = EPWM detect fault and output Disabled. + * |[9] |FDODIS1 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enabled. + * | | |1 = EPWM detect fault and output Disabled. + * |[10] |FDODIS2 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enabled. + * | | |1 = EPWM detect fault and output Disabled. + * |[11] |FDODIS3 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enabled. + * | | |1 = EPWM detect fault and output Disabled. + * |[12] |FDODIS4 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enabled. + * | | |1 = EPWM detect fault and output Disabled. + * |[13] |FDODIS5 |EPWM Channel n Output Fault Detect Disable Bit + * | | |0 = EPWM detect fault and output Enabled. + * | | |1 = EPWM detect fault and output Disabled. + * |[16] |FDCKS0 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0 or 1. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. + * |[17] |FDCKS1 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0 or 1. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. + * |[18] |FDCKS2 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0 or 1. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. + * |[19] |FDCKS3 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0 or 1. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. + * |[20] |FDCKS4 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0 or 1. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. + * |[21] |FDCKS5 |EPWM Channel n Fault Detect Clock Source Select Bit + * | | |0 = EPWMx_CLK, x denotes 0 or 1. + * | | |1 = EPWMx_CLK divide by prescaler, x denotes 0 or 1. + * @var EPWM_T::FDCTL0 + * Offset: 0x164 EPWM Fault Detect Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |1. FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |2. FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |1. FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |2. FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disabled. + * | | |1 = Fault detect deglitch function Enabled. + * @var EPWM_T::FDCTL1 + * Offset: 0x168 EPWM Fault Detect Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |1. FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |2. FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |1. FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |2. FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disabled. + * | | |1 = Fault detect deglitch function Enabled. + * @var EPWM_T::FDCTL2 + * Offset: 0x16C EPWM Fault Detect Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |1. FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |2. FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |1. FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |2. FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disabled. + * | | |1 = Fault detect deglitch function Enabled. + * @var EPWM_T::FDCTL3 + * Offset: 0x170 EPWM Fault Detect Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |1. FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |2. FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |1. FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |2. FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disabled. + * | | |1 = Fault detect deglitch function Enabled. + * @var EPWM_T::FDCTL4 + * Offset: 0x174 EPWM Fault Detect Control Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |1. FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |2. FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |1. FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |2. FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disabled. + * | | |1 = Fault detect deglitch function Enabled. + * @var EPWM_T::FDCTL5 + * Offset: 0x178 EPWM Fault Detect Control Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |TRMSKCNT |Transition Mask Counter + * | | |The fault detect result will be masked before counter count from 0 to TRMSKCNT. + * | | |1. FDCKS is set to 0: + * | | |Mask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |2. FDCKS is set to 1: + * | | |Mask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2) + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[15] |FDMSKEN |Fault Detect Mask Enable Bit + * | | |0 = Fault detect mask function Disabled. + * | | |1 = Fault detect mask function Enabled. + * |[18:16] |DGSMPCYC |Deglitch Sampling Cycle + * | | |1. FDCKS is set to 0: + * | | |Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |2. FDCKS is set to 1: + * | | |Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times + * | | |Note: + * | | |CLKPSC (EPWM_CLKPSCn[11:0]) is 0: + * | | |TRMSKCNT >= DGSMPCYC + 2. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 1: + * | | |TRMSKCNT >= DGSMPCYC + 1. + * | | |FDCKS is 1 and CLKPSC (EPWM_CLKPSCn[11:0]) is 2: + * | | |TRMSKCNT >= DGSMPCYC. + * |[29:28] |FDCKSEL |EPWM Channel Fault Detect Clock Select + * | | |00 = FLT_CLK/1. + * | | |01 = FLT_CLK/2. + * | | |10 = FLT_CLK/4. + * | | |11 = FLT_CLK/8. + * | | |Note: FLT_CLK is FDCKSn (EPWM_FDENn[16+n], n=0,1..5) selected clock. + * |[31] |FDDGEN |Fault Detect Deglitch Enable Bit + * | | |0 = Fault detect deglitch function Disabled. + * | | |1 = Fault detect deglitch function Enabled. + * @var EPWM_T::FDIEN + * Offset: 0x17C EPWM Fault Detect Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FDIENn |EPWM Channel n Fault Detect Interrupt Enable Bit + * | | |0 = EPWM Channel n Fault Detect Interrupt Disabled. + * | | |1 = EPWM Channel n Fault Detect Interrupt Enabled. + * @var EPWM_T::FDSTS + * Offset: 0x180 EPWM Fault Detect Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FDIFn |EPWM Channel n Fault Detect Interrupt Flag Bit + * | | |Fault Detect Interrupt Flag will be set when EPWM output short + * | | |Software can clear this bit by writing 1 to it. + * @var EPWM_T::EADCPSCCTL + * Offset: 0x184 EPWM Trigger EADC Prescale Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PSCEN0 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[1] |PSCEN1 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[2] |PSCEN2 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[3] |PSCEN3 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[4] |PSCEN4 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * |[5] |PSCEN5 |EPWM Trigger EADC Pre-scale Function Enable Bits + * | | |0 = EPWM Trigger EADC Pre-scale Function Disabled. + * | | |1 = EPWM Trigger EADC Pre-scale Function Enabled. + * @var EPWM_T::EADCPSC0 + * Offset: 0x188 EPWM Trigger EADC Prescale Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EADCPSC0 |EPWM Channel 0 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0. + * |[11:8] |EADCPSC1 |EPWM Channel 1 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1. + * |[19:16] |EADCPSC2 |EPWM Channel 2 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2. + * |[27:24] |EADCPSC3 |EPWM Channel 3 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3. + * @var EPWM_T::EADCPSC1 + * Offset: 0x18C EPWM Trigger EADC Prescale Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EADCPSC4 |EPWM Channel 4 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4. + * |[11:8] |EADCPSC5 |EPWM Channel 5 Trigger EADC Prescale + * | | |The register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5. + * @var EPWM_T::EADCPSCNT0 + * Offset: 0x190 EPWM Trigger EADC Prescale Counter Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PSCNT0 |EPWM Trigger EADC Prescale Counter 0 + * | | |User can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN0 is 0. + * | | |Note 2: Write data limitation: PSCNT0 < EADCPSC0. + * |[11:8] |PSCNT1 |EPWM Trigger EADC Prescale Counter 1 + * | | |User can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN1 is 0. + * | | |Note 2: Write data limitation: PSCNT1 < EADCPSC1. + * |[19:16] |PSCNT2 |EPWM Trigger EADC Prescale Counter 2 + * | | |User can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN2 is 0. + * | | |Note 2: Write data limitation: PSCNT2 < EADCPSC2. + * |[27:24] |PSCNT3 |EPWM Trigger EADC Prescale Counter 3 + * | | |User can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: user can write only when PSCEN3 is 0. + * | | |Note 2: Write data limitation: PSCNT3 < EADCPSC3. + * @var EPWM_T::EADCPSCNT1 + * Offset: 0x194 EPWM Trigger EADC Prescale Counter Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PSCNT4 |EPWM Trigger EADC Prescale Counter 4 + * | | |User can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: User can write only when PSCEN4 is 0. + * | | |Note 2: Write data limitation: PSCNT4 < EADCPSC4. + * |[11:8] |PSCNT5 |EPWM Trigger EADC Prescale Counter 5 + * | | |User can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter. + * | | |Note 1: User can write only when PSCEN5 is 0. + * | | |Note 2: Write data limitation: PSCNT5 < EADCPSC5. + * @var EPWM_T::CAPINEN + * Offset: 0x200 EPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * @var EPWM_T::CAPCTL + * Offset: 0x204 EPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var EPWM_T::CAPSTS + * Offset: 0x208 EPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CRLIFn(EPWM_CAPIF[n]). + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1. + * | | |Note: This bit will be cleared automatically when user clears corresponding CFLIFn(EPWM_CAPIF[8+n]). + * @var EPWM_T::RCAPDAT0 + * Offset: 0x20C EPWM Rising Capture Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT0 + * Offset: 0x210 EPWM Falling Capture Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT1 + * Offset: 0x214 EPWM Rising Capture Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT1 + * Offset: 0x218 EPWM Falling Capture Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT2 + * Offset: 0x21C EPWM Rising Capture Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT2 + * Offset: 0x220 EPWM Falling Capture Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT3 + * Offset: 0x224 EPWM Rising Capture Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT3 + * Offset: 0x228 EPWM Falling Capture Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT4 + * Offset: 0x22C EPWM Rising Capture Data Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT4 + * Offset: 0x230 EPWM Falling Capture Data Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::RCAPDAT5 + * Offset: 0x234 EPWM Rising Capture Data Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data Register (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::FCAPDAT5 + * Offset: 0x238 EPWM Falling Capture Data Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data Register (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + * @var EPWM_T::PDMACTL + * Offset: 0x23C EPWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable Bit + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT0/1. + * | | |10 = EPWM_FCAPDAT0/1. + * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. + * | | |0 = EPWM_FCAPDAT0/1 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT0/1 is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable Bit + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT2/3. + * | | |10 = EPWM_FCAPDAT2/3. + * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. + * | | |0 = EPWM_FCAPDAT2/3 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT2/3 is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable Bit + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT4/5. + * | | |10 = EPWM_FCAPDAT4/5. + * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. + * | | |0 = EPWM_FCAPDAT4/5 is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT4/5 is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var EPWM_T::PDMACAP[3] + * Offset: 0x240 EPWM Capture Channel 01 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::CAPIEN + * Offset: 0x250 EPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var EPWM_T::CAPIF + * Offset: 0x254 EPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, and this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, and this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, and this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, and this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, and this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, and this flag will be set to high. + * | | |Note 1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data. + * | | |Note 2: This bit is cleared by writing 1 to it. + * @var EPWM_T::CAPNF0 + * Offset: 0x258 EPWM Capture Input Noise Filter Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPNFEN |Capture Noise Filter Enable + * | | |0 = Capture Noise Filter function Disabled. + * | | |1 = Capture Noise Filter function Enabled. + * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection + * | | |000 = Filter clock = PCLK. + * | | |001 = Filter clock = PCLK/2. + * | | |010 = Filter clock = PCLK/4. + * | | |011 = Filter clock = PCLK/8. + * | | |100 = Filter clock = PCLK/16. + * | | |101 = Filter clock = PCLK/32. + * | | |110 = Filter clock = PCLK/64. + * | | |111 = Filter clock = PCLK/128. + * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count + * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. + * @var EPWM_T::CAPNF1 + * Offset: 0x25C EPWM Capture Input Noise Filter Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPNFEN |Capture Noise Filter Enable + * | | |0 = Capture Noise Filter function Disabled. + * | | |1 = Capture Noise Filter function Enabled. + * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection + * | | |000 = Filter clock = PCLK. + * | | |001 = Filter clock = PCLK/2. + * | | |010 = Filter clock = PCLK/4. + * | | |011 = Filter clock = PCLK/8. + * | | |100 = Filter clock = PCLK/16. + * | | |101 = Filter clock = PCLK/32. + * | | |110 = Filter clock = PCLK/64. + * | | |111 = Filter clock = PCLK/128. + * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count + * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. + * @var EPWM_T::CAPNF2 + * Offset: 0x260 EPWM Capture Input Noise Filter Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPNFEN |Capture Noise Filter Enable + * | | |0 = Capture Noise Filter function Disabled. + * | | |1 = Capture Noise Filter function Enabled. + * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection + * | | |000 = Filter clock = PCLK. + * | | |001 = Filter clock = PCLK/2. + * | | |010 = Filter clock = PCLK/4. + * | | |011 = Filter clock = PCLK/8. + * | | |100 = Filter clock = PCLK/16. + * | | |101 = Filter clock = PCLK/32. + * | | |110 = Filter clock = PCLK/64. + * | | |111 = Filter clock = PCLK/128. + * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count + * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. + * @var EPWM_T::CAPNF3 + * Offset: 0x264 EPWM Capture Input Noise Filter Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPNFEN |Capture Noise Filter Enable + * | | |0 = Capture Noise Filter function Disabled. + * | | |1 = Capture Noise Filter function Enabled. + * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection + * | | |000 = Filter clock = PCLK. + * | | |001 = Filter clock = PCLK/2. + * | | |010 = Filter clock = PCLK/4. + * | | |011 = Filter clock = PCLK/8. + * | | |100 = Filter clock = PCLK/16. + * | | |101 = Filter clock = PCLK/32. + * | | |110 = Filter clock = PCLK/64. + * | | |111 = Filter clock = PCLK/128. + * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count + * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. + * @var EPWM_T::CAPNF4 + * Offset: 0x268 EPWM Capture Input Noise Filter Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPNFEN |Capture Noise Filter Enable + * | | |0 = Capture Noise Filter function Disabled. + * | | |1 = Capture Noise Filter function Enabled. + * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection + * | | |000 = Filter clock = PCLK. + * | | |001 = Filter clock = PCLK/2. + * | | |010 = Filter clock = PCLK/4. + * | | |011 = Filter clock = PCLK/8. + * | | |100 = Filter clock = PCLK/16. + * | | |101 = Filter clock = PCLK/32. + * | | |110 = Filter clock = PCLK/64. + * | | |111 = Filter clock = PCLK/128. + * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count + * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. + * @var EPWM_T::CAPNF5 + * Offset: 0x26C EPWM Capture Input Noise Filter Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPNFEN |Capture Noise Filter Enable + * | | |0 = Capture Noise Filter function Disabled. + * | | |1 = Capture Noise Filter function Enabled. + * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection + * | | |000 = Filter clock = PCLK. + * | | |001 = Filter clock = PCLK/2. + * | | |010 = Filter clock = PCLK/4. + * | | |011 = Filter clock = PCLK/8. + * | | |100 = Filter clock = PCLK/16. + * | | |101 = Filter clock = PCLK/32. + * | | |110 = Filter clock = PCLK/64. + * | | |111 = Filter clock = PCLK/128. + * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count + * | | |The register bits control the capture filter counter to count from 0 to CAPNFCNT. + * @var EPWM_T::EXTETCTL0 + * Offset: 0x270 EPWM External Event Trigger Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EXETEN |External Event Trigger Enable Bit + * | | |0 = External Event Trigger function Disabled. + * | | |1 = External Event Trigger function Enabled. + * |[5:4] |CNTACTS |Counter Action Selection + * | | |00 = Counter reset. + * | | |01 = Counter start. + * | | |10 = Counter reset and start. + * | | |11 = Reserved. + * |[11:8] |EXTTRGS |External Trigger Selection + * | | |0000 = INT0. + * | | |0001 = INT1. + * | | |0010 = INT2. + * | | |0011 = INT3. + * | | |0100 = INT4. + * | | |0101 = INT5. + * | | |0110 = INT6. + * | | |0111 = INT7. + * | | |Other = Reserved. + * @var EPWM_T::EXTETCTL1 + * Offset: 0x274 EPWM External Event Trigger Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EXETEN |External Event Trigger Enable Bit + * | | |0 = External Event Trigger function Disabled. + * | | |1 = External Event Trigger function Enabled. + * |[5:4] |CNTACTS |Counter Action Selection + * | | |00 = Counter reset. + * | | |01 = Counter start. + * | | |10 = Counter reset and start. + * | | |11 = Reserved. + * |[11:8] |EXTTRGS |External Trigger Selection + * | | |0000 = INT0. + * | | |0001 = INT1. + * | | |0010 = INT2. + * | | |0011 = INT3. + * | | |0100 = INT4. + * | | |0101 = INT5. + * | | |0110 = INT6. + * | | |0111 = INT7. + * | | |Other = Reserved. + * @var EPWM_T::EXTETCTL2 + * Offset: 0x278 EPWM External Event Trigger Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EXETEN |External Event Trigger Enable Bit + * | | |0 = External Event Trigger function Disabled. + * | | |1 = External Event Trigger function Enabled. + * |[5:4] |CNTACTS |Counter Action Selection + * | | |00 = Counter reset. + * | | |01 = Counter start. + * | | |10 = Counter reset and start. + * | | |11 = Reserved. + * |[11:8] |EXTTRGS |External Trigger Selection + * | | |0000 = INT0. + * | | |0001 = INT1. + * | | |0010 = INT2. + * | | |0011 = INT3. + * | | |0100 = INT4. + * | | |0101 = INT5. + * | | |0110 = INT6. + * | | |0111 = INT7. + * | | |Other = Reserved. + * @var EPWM_T::EXTETCTL3 + * Offset: 0x27C EPWM External Event Trigger Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EXETEN |External Event Trigger Enable Bit + * | | |0 = External Event Trigger function Disabled. + * | | |1 = External Event Trigger function Enabled. + * |[5:4] |CNTACTS |Counter Action Selection + * | | |00 = Counter reset. + * | | |01 = Counter start. + * | | |10 = Counter reset and start. + * | | |11 = Reserved. + * |[11:8] |EXTTRGS |External Trigger Selection + * | | |0000 = INT0. + * | | |0001 = INT1. + * | | |0010 = INT2. + * | | |0011 = INT3. + * | | |0100 = INT4. + * | | |0101 = INT5. + * | | |0110 = INT6. + * | | |0111 = INT7. + * | | |Other = Reserved. + * @var EPWM_T::EXTETCTL4 + * Offset: 0x280 EPWM External Event Trigger Control Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EXETEN |External Event Trigger Enable Bit + * | | |0 = External Event Trigger function Disabled. + * | | |1 = External Event Trigger function Enabled. + * |[5:4] |CNTACTS |Counter Action Selection + * | | |00 = Counter reset. + * | | |01 = Counter start. + * | | |10 = Counter reset and start. + * | | |11 = Reserved. + * |[11:8] |EXTTRGS |External Trigger Selection + * | | |0000 = INT0. + * | | |0001 = INT1. + * | | |0010 = INT2. + * | | |0011 = INT3. + * | | |0100 = INT4. + * | | |0101 = INT5. + * | | |0110 = INT6. + * | | |0111 = INT7. + * | | |Other = Reserved. + * @var EPWM_T::EXTETCTL5 + * Offset: 0x284 EPWM External Event Trigger Control Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EXETEN |External Event Trigger Enable Bit + * | | |0 = External Event Trigger function Disabled. + * | | |1 = External Event Trigger function Enabled. + * |[5:4] |CNTACTS |Counter Action Selection + * | | |00 = Counter reset. + * | | |01 = Counter start. + * | | |10 = Counter reset and start. + * | | |11 = Reserved. + * |[11:8] |EXTTRGS |External Trigger Selection + * | | |0000 = INT0. + * | | |0001 = INT1. + * | | |0010 = INT2. + * | | |0011 = INT3. + * | | |0100 = INT4. + * | | |0101 = INT5. + * | | |0110 = INT6. + * | | |0111 = INT7. + * | | |Other = Reserved. + * @var EPWM_T::SWEOFCTL + * Offset: 0x288 EPWM Software Event Output Force Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OUTACTS0 |Output Action Selection + * | | |00 = Do nothing. + * | | |01 = EPWM output Low. + * | | |10 = EPWM output High. + * | | |11 = EPWM output Toggle. + * |[3:2] |OUTACTS1 |Output Action Selection + * | | |00 = Do nothing. + * | | |01 = EPWM output Low. + * | | |10 = EPWM output High. + * | | |11 = EPWM output Toggle. + * |[5:4] |OUTACTS2 |Output Action Selection + * | | |00 = Do nothing. + * | | |01 = EPWM output Low. + * | | |10 = EPWM output High. + * | | |11 = EPWM output Toggle. + * |[7:6] |OUTACTS3 |Output Action Selection + * | | |00 = Do nothing. + * | | |01 = EPWM output Low. + * | | |10 = EPWM output High. + * | | |11 = EPWM output Toggle. + * |[9:8] |OUTACTS4 |Output Action Selection + * | | |00 = Do nothing. + * | | |01 = EPWM output Low. + * | | |10 = EPWM output High. + * | | |11 = EPWM output Toggle. + * |[11:10] |OUTACTS5 |Output Action Selection + * | | |00 = Do nothing. + * | | |01 = EPWM output Low. + * | | |10 = EPWM output High. + * | | |11 = EPWM output Toggle. + * @var EPWM_T::SWEOFTRG + * Offset: 0x28C EPWM Software Event Output Force Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWETRG0 |Software Event Trigger + * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. + * | | |Note: This bit will auto cleared by hardware. + * |[1] |SWETRG1 |Software Event Trigger + * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. + * | | |Note: This bit will auto cleared by hardware. + * |[2] |SWETRG2 |Software Event Trigger + * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. + * | | |Note: This bit will auto cleared by hardware. + * |[3] |SWETRG3 |Software Event Trigger + * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. + * | | |Note: This bit will auto cleared by hardware. + * |[4] |SWETRG4 |Software Event Trigger + * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. + * | | |Note: This bit will auto cleared by hardware. + * |[5] |SWETRG5 |Software Event Trigger + * | | |Write 1 to this bit will change EPWM output status according to OUTACTSn in EPWMx_SWEOFCTL setting. + * | | |Note: This bit will auto cleared by hardware. + * @var EPWM_T::CLKPSC0 + * Offset: 0x290 EPWM Clock Prescale Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair shares one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CLKPSC1 + * Offset: 0x294 EPWM Clock Prescale Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair shares one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CLKPSC2 + * Offset: 0x298 EPWM Clock Prescale Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair shares one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CLKPSC3 + * Offset: 0x29C EPWM Clock Prescale Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair shares one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CLKPSC4 + * Offset: 0x2A0 EPWM Clock Prescale Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair shares one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CLKPSC5 + * Offset: 0x2A4 EPWM Clock Prescale Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair shares one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::RDTCNT0_1 + * Offset: 0x2A8 EPWM Rising Dead-time Counter Register 0/1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |RDTCNT |Rising Dead-time Counter (Write Protect) + * | | |The Rising dead-time can be calculated from the following formula: + * | | |RDTCKSEL=0: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period. + * | | |RDTCKSEL=1: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::RDTCNT2_3 + * Offset: 0x2AC EPWM Rising Dead-time Counter Register 2/3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |RDTCNT |Rising Dead-time Counter (Write Protect) + * | | |The Rising dead-time can be calculated from the following formula: + * | | |RDTCKSEL=0: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period. + * | | |RDTCKSEL=1: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::RDTCNT4_5 + * Offset: 0x2B0 EPWM Rising Dead-time Counter Register 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |RDTCNT |Rising Dead-time Counter (Write Protect) + * | | |The Rising dead-time can be calculated from the following formula: + * | | |RDTCKSEL=0: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period. + * | | |RDTCKSEL=1: Rising Dead-time = (RDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::FDTCNT0_1 + * Offset: 0x2B4 EPWM Falling Dead-time Counter Register 0/1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |FDTCNT |Falling Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |FDTCKSEL=0: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period. + * | | |FDTCKSEL=1: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::FDTCNT2_3 + * Offset: 0x2B8 EPWM Falling Dead-time Counter Register 2/3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |FDTCNT |Falling Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |FDTCKSEL=0: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period. + * | | |FDTCKSEL=1: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::FDTCNT4_5 + * Offset: 0x2BC EPWM Falling Dead-time Counter Register 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |FDTCNT |Falling Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |FDTCKSEL=0: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period. + * | | |FDTCKSEL=1: Falling Dead-time = (FDTCNT[11:0]+1) * EPWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::DTCTL + * Offset: 0x2C0 EPWM Dead-time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDTEN0 |Enable Rising Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Rising Dead-time insertion Disabled on the pin pair. + * | | |1 = Rising Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |RDTEN2 |Enable Rising Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Rising Dead-time insertion Disabled on the pin pair. + * | | |1 = Rising Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[2] |RDTEN4 |Enable Rising Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Rising Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If rising dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Rising Dead-time insertion Disabled on the pin pair. + * | | |1 = Rising Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |FDTEN0 |Enable Falling Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Falling Dead-time insertion Disabled on the pin pair. + * | | |1 = Falling Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |FDTEN2 |Enable Falling Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Falling Dead-time insertion Disabled on the pin pair. + * | | |1 = Falling Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[10] |FDTEN4 |Enable Falling Dead-time Insertion for EPWM Pair (Write Protect) + * | | |Falling Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If falling dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Falling Dead-time insertion Disabled on the pin pair. + * | | |1 = Falling Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[16] |DTCKSELn |Dead-time Clock Select for EPWM Pair (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::PBUF[6] + * Offset: 0x304 EPWM PERIOD0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::CMPBUF[6] + * Offset: 0x31C EPWM CMPDAT0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CPSCBUF[3] + * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Use as EPWM counter clock prescale active register. + * @var EPWM_T::FTCBUF[3] + * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMP active buffer. + * @var EPWM_T::FTCI + * Offset: 0x34C EPWM FTCMPDAT Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator + * | | |Indicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn + * | | |Software can clear this bit by writing 1 to it. + * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator + * | | |Indicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn + * | | |Software can clear this bit by writing 1 to it. + * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator + * | | |Indicator is set by hardware when EPWM counter up counts and reaches EPWM_FTCMPDATn + * | | |Software can clear this bit by writing 1 to it. + * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator + * | | |Indicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn + * | | |Software can clear this bit by writing 1 to it. + * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator + * | | |Indicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn + * | | |Software can clear this bit by writing 1 to it. + * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator + * | | |Indicator is set by hardware when EPWM counter down counts and reaches EPWM_FTCMPDATn + * | | |Software can clear this bit by writing 1 to it. + * @var EPWM_T::CPSCBUF0 + * Offset: 0x350 EPWM CLKPSC0 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::CPSCBUF1 + * Offset: 0x354 EPWM CLKPSC1 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::CPSCBUF2 + * Offset: 0x358 EPWM CLKPSC2 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::CPSCBUF3 + * Offset: 0x35C EPWM CLKPSC3 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::CPSCBUF4 + * Offset: 0x360 EPWM CLKPSC4 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::CPSCBUF5 + * Offset: 0x364 EPWM CLKPSC5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Used as EPWM counter clock pre-scare active register. + * @var EPWM_T::IFACNT0 + * Offset: 0x368 EPWM Interrupt Flag Accumulator Counter 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACUCNT |Accumulator Counter (Read Only) + * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. + * @var EPWM_T::IFACNT1 + * Offset: 0x36C EPWM Interrupt Flag Accumulator Counter 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACUCNT |Accumulator Counter (Read Only) + * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. + * @var EPWM_T::IFACNT2 + * Offset: 0x370 EPWM Interrupt Flag Accumulator Counter 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACUCNT |Accumulator Counter (Read Only) + * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. + * @var EPWM_T::IFACNT3 + * Offset: 0x374 EPWM Interrupt Flag Accumulator Counter 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACUCNT |Accumulator Counter (Read Only) + * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. + * @var EPWM_T::IFACNT4 + * Offset: 0x378 EPWM Interrupt Flag Accumulator Counter 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACUCNT |Accumulator Counter (Read Only) + * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. + * @var EPWM_T::IFACNT5 + * Offset: 0x37C EPWM Interrupt Flag Accumulator Counter 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ACUCNT |Accumulator Counter (Read Only) + * | | |This value indicates how many interrupt are accumulated when using interrupt flag accumulator function. + */ + __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ + __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ + __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ + __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ + __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PERIOD[6]; /*!< [0x0030] EPWM Period Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CMPDAT[6]; /*!< [0x0050] EPWM Comparator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[6]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PHS[3]; /*!< [0x0080] EPWM Counter Phase Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t CNT[6]; /*!< [0x0090] EPWM Counter Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE5[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8] EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 */ + __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE6[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ + __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ + __IO uint32_t FTCMPDAT[3]; /*!< [0x0100] EPWM Free Trigger Compare Register 0/1,2/3,4/5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE7[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ + __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ + __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ + __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE8[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t IFA[6]; /*!< [0x0130] EPWM Interrupt Flag Accumulator Register 0~5 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE9[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ + __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ + __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE10[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ + __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ + __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ + __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ + __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ + __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ + __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ + __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ + __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE11[26]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ + ECAPDAT_T CAPDAT[6]; /*!< [0x020C] EPWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240] EPWM Capture Channel 01,23,45 PDMA Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE12[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ + __IO uint32_t CAPNF[6]; /*!< [0x0258~0x26C] EPWM Capture Input Noise Filter Register 0~5 */ + __IO uint32_t EXTETCTL[6]; /*!< [0x0270~0x284] EPWM External Event Trigger Control Register 0~5 */ + __IO uint32_t SWEOFCTL; /*!< [0x0288] EPWM Software Event Output Force Control Register */ + __IO uint32_t SWEOFTRG; /*!< [0x028C] EPWM Software Event Output Force Trigger Register */ + __IO uint32_t CLKPSC[6]; /*!< [0x0290~0x2A4] EPWM Clock Prescale Register 0~5 */ + __IO uint32_t RDTCNT[3]; /*!< [0x02A8~0x2B0] EPWM Rising Dead-time Counter Register 0/1, 2/3, 4/5 */ + __IO uint32_t FDTCNT[3]; /*!< [0x02B4~0x2BC] EPWM Falling Dead-time Counter Register 0/1, 2/3, 4/5 */ + __IO uint32_t DTCTL; /*!< [0x02C0] EPWM Dead-Time Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE13[16]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t PBUF[6]; /*!< [0x0304] EPWM PERIOD0~5 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031c] EPWM CMPDAT0~5 Buffer */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE14[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t FTCBUF[3]; /*!< [0x0340] EPWM FTCMPDAT0_1/2_3/4_5 Buffer */ + __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ + __I uint32_t CPSCBUF[5]; /*!< [0x0350~0x364] EPWM CLKPSC0~5 Buffer */ + __I uint32_t IFACNT[5]; /*!< [0x0368~0x37C] EPWM Interrupt Flag Accumulator Counter 0~5 */ + +} EPWM_T; + +/** + @addtogroup EPWM_CONST EPWM Bit Field Definition + Constant Definitions for EPWM Controller +@{ */ + +#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ +#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ + +#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ +#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ + +#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ +#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ + +#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ +#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ + +#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ +#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ + +#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ +#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ + +#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ +#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ + +#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ +#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ + +#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ +#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ + +#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ +#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ + +#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ +#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ + +#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ +#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ + +#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ +#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ + +#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ +#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ + +#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ +#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ + +#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ +#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ + +#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ +#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ + +#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ +#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ + +#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ +#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ + +#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ +#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ + +#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ +#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ + +#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ +#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ + +#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ +#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ + +#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ +#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ + +#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ +#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ + +#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ +#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ + +#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ +#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ + +#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ +#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ + +#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ +#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ + +#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ +#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ + +#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ +#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ + +#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ +#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ + +#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ +#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ + +#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ +#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ + +#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ +#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ + +#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ +#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ + +#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ +#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ + +#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ +#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ + +#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ +#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ + +#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ +#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ + +#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ +#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ + +#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ +#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ + +#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ +#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ + +#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ +#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ + +#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ +#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ + +#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ +#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ + +#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ +#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ + +#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ +#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ + +#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ +#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ + +#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ +#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ + +#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ +#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ + +#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ +#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ + +#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ +#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ +#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ +#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ +#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ + +#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ +#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ + +#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ +#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ + +#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ +#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ + +#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ +#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ + +#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ +#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ + +#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ +#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ +#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ + +#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ +#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ + +#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ +#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ + +#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ +#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ + +#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ +#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ + +#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ +#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ + +#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ +#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ + +#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ +#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ + +#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ +#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ + +#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ +#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ + +#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ +#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ + +#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ +#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ + +#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ +#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ + +#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ +#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ + +#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ +#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ + +#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ +#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ + +#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ +#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ + +#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ +#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ + +#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ +#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ + +#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ +#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ + +#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ +#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ + +#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ +#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ + +#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ +#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ + +#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ +#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ + +#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ +#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ + +#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ +#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ + +#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ +#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ + +#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ +#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ + +#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ +#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ + +#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ +#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ + +#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ +#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ + +#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ +#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ + +#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ +#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ + +#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ +#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ + +#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ +#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ + +#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ +#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ + +#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ +#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ + +#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ +#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ + +#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ +#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ +#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ +#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ +#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ +#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ +#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ +#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ +#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ +#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ +#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ +#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ +#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ +#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ +#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ +#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ +#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ +#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ +#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ +#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ +#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ +#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ +#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ +#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ +#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ +#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ + +#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ +#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ + +#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ +#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ + +#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ +#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ + +#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ +#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ + +#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ +#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ + +#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ +#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ + +#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ +#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ + +#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ +#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ + +#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ +#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ + +#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ +#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ + +#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ +#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ + +#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ +#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ + +#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ +#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ + +#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ +#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ + +#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ +#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ + +#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ +#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ + +#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ +#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ + +#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ +#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ + +#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ +#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ + +#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ +#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ + +#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ +#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ + +#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ +#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ + +#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ +#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ + +#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ +#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ + +#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ +#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ +#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ +#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO2EBEN_Pos (2) /*!< EPWM_T::BRKCTL0_1: CPO2EBEN Position */ +#define EPWM_BRKCTL0_1_CPO2EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO2EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO2EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO3EBEN_Pos (3) /*!< EPWM_T::BRKCTL0_1: CPO3EBEN Position */ +#define EPWM_BRKCTL0_1_CPO3EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO3EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO3EBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ +#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ +#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ +#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO2LBEN_Pos (10) /*!< EPWM_T::BRKCTL0_1: CPO2LBEN Position */ +#define EPWM_BRKCTL0_1_CPO2LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO2LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO2LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO3LBEN_Pos (11) /*!< EPWM_T::BRKCTL0_1: CPO3LBEN Position */ +#define EPWM_BRKCTL0_1_CPO3LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO3LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO3LBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ +#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ +#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define EPWM_BRKCTL0_1_EADC0EBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADC0EBEN Position */ +#define EPWM_BRKCTL0_1_EADC0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC0EBEN Mask */ + +#define EPWM_BRKCTL0_1_EADC1EBEN_Pos (21) /*!< EPWM_T::BRKCTL0_1: EADC1EBEN Position */ +#define EPWM_BRKCTL0_1_EADC1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC1EBEN Mask */ + +#define EPWM_BRKCTL0_1_EADC2EBEN_Pos (22) /*!< EPWM_T::BRKCTL0_1: EADC2EBEN Position */ +#define EPWM_BRKCTL0_1_EADC2EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC2EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC2EBEN Mask */ + +#define EPWM_BRKCTL0_1_EADC0LBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADC0LBEN Position */ +#define EPWM_BRKCTL0_1_EADC0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC0LBEN Mask */ + +#define EPWM_BRKCTL0_1_EADC1LBEN_Pos (29) /*!< EPWM_T::BRKCTL0_1: EADC1LBEN Position */ +#define EPWM_BRKCTL0_1_EADC1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC1LBEN Mask */ + +#define EPWM_BRKCTL0_1_EADC2LBEN_Pos (30) /*!< EPWM_T::BRKCTL0_1: EADC2LBEN Position */ +#define EPWM_BRKCTL0_1_EADC2LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADC2LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADC2LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ +#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ +#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO2EBEN_Pos (2) /*!< EPWM_T::BRKCTL2_3: CPO2EBEN Position */ +#define EPWM_BRKCTL2_3_CPO2EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO2EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO2EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO3EBEN_Pos (3) /*!< EPWM_T::BRKCTL2_3: CPO3EBEN Position */ +#define EPWM_BRKCTL2_3_CPO3EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO3EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO3EBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ +#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ +#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ +#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO2LBEN_Pos (10) /*!< EPWM_T::BRKCTL2_3: CPO2LBEN Position */ +#define EPWM_BRKCTL2_3_CPO2LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO2LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO2LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO3LBEN_Pos (11) /*!< EPWM_T::BRKCTL2_3: CPO3LBEN Position */ +#define EPWM_BRKCTL2_3_CPO3LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO3LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO3LBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ +#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ +#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define EPWM_BRKCTL2_3_EADC0EBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADC0EBEN Position */ +#define EPWM_BRKCTL2_3_EADC0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC0EBEN Mask */ + +#define EPWM_BRKCTL2_3_EADC1EBEN_Pos (21) /*!< EPWM_T::BRKCTL2_3: EADC1EBEN Position */ +#define EPWM_BRKCTL2_3_EADC1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC1EBEN Mask */ + +#define EPWM_BRKCTL2_3_EADC2EBEN_Pos (22) /*!< EPWM_T::BRKCTL2_3: EADC2EBEN Position */ +#define EPWM_BRKCTL2_3_EADC2EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC2EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC2EBEN Mask */ + +#define EPWM_BRKCTL2_3_EADC0LBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADC0LBEN Position */ +#define EPWM_BRKCTL2_3_EADC0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC0LBEN Mask */ + +#define EPWM_BRKCTL2_3_EADC1LBEN_Pos (29) /*!< EPWM_T::BRKCTL2_3: EADC1LBEN Position */ +#define EPWM_BRKCTL2_3_EADC1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC1LBEN Mask */ + +#define EPWM_BRKCTL2_3_EADC2LBEN_Pos (30) /*!< EPWM_T::BRKCTL2_3: EADC2LBEN Position */ +#define EPWM_BRKCTL2_3_EADC2LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADC2LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADC2LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ +#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ +#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO2EBEN_Pos (2) /*!< EPWM_T::BRKCTL4_5: CPO2EBEN Position */ +#define EPWM_BRKCTL4_5_CPO2EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO2EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO2EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO3EBEN_Pos (3) /*!< EPWM_T::BRKCTL4_5: CPO3EBEN Position */ +#define EPWM_BRKCTL4_5_CPO3EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO3EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO3EBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ +#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ +#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ +#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO2LBEN_Pos (10) /*!< EPWM_T::BRKCTL4_5: CPO2LBEN Position */ +#define EPWM_BRKCTL4_5_CPO2LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO2LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO2LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO3LBEN_Pos (11) /*!< EPWM_T::BRKCTL4_5: CPO3LBEN Position */ +#define EPWM_BRKCTL4_5_CPO3LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO3LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO3LBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ +#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ +#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define EPWM_BRKCTL4_5_EADC0EBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADC0EBEN Position */ +#define EPWM_BRKCTL4_5_EADC0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC0EBEN Mask */ + +#define EPWM_BRKCTL4_5_EADC1EBEN_Pos (21) /*!< EPWM_T::BRKCTL4_5: EADC1EBEN Position */ +#define EPWM_BRKCTL4_5_EADC1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC1EBEN Mask */ + +#define EPWM_BRKCTL4_5_EADC2EBEN_Pos (22) /*!< EPWM_T::BRKCTL4_5: EADC2EBEN Position */ +#define EPWM_BRKCTL4_5_EADC2EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC2EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC2EBEN Mask */ + +#define EPWM_BRKCTL4_5_EADC0LBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADC0LBEN Position */ +#define EPWM_BRKCTL4_5_EADC0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC0LBEN Mask */ + +#define EPWM_BRKCTL4_5_EADC1LBEN_Pos (29) /*!< EPWM_T::BRKCTL4_5: EADC1LBEN Position */ +#define EPWM_BRKCTL4_5_EADC1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC1LBEN Mask */ + +#define EPWM_BRKCTL4_5_EADC2LBEN_Pos (30) /*!< EPWM_T::BRKCTL4_5: EADC2LBEN Position */ +#define EPWM_BRKCTL4_5_EADC2LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADC2LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADC2LBEN Mask */ + +#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ +#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ + +#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ +#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ + +#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ +#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ + +#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ +#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ + +#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ +#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ + +#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ +#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ + +#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ +#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ + +#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ +#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ + +#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ +#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ + +#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ +#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ + +#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ +#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ + +#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ +#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ + +#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ +#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ + +#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ +#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ + +#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ +#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ + +#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ +#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ + +#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ +#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ + +#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ +#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ + +#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ +#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ + +#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ +#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ + +#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ +#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ + +#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ +#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ + +#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ +#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ + +#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ +#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ + +#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ +#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ + +#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ +#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ + +#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ +#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ + +#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ +#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ + +#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ +#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ + +#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ +#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ + +#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ +#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ + +#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ +#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ + +#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ +#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ + +#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ +#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ + +#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ +#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ + +#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ +#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ + +#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ +#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ + +#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ +#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ + +#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ +#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ + +#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ +#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ + +#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ +#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ + +#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ +#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ + +#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ +#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ +#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ +#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ +#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ +#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ +#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ +#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ + +#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ +#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ + +#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ +#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ + +#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ +#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ + +#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ +#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ + +#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ +#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ + +#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ +#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ + +#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ +#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ + +#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ +#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ + +#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ +#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ + +#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ +#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ + +#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ +#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ + +#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ +#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ + +#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ +#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ + +#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ +#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ + +#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ +#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ + +#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ +#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ + +#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ +#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ + +#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ +#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ + +#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ +#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ + +#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ +#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ + +#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ +#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ + +#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ +#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ + +#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ +#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ + +#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ +#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ + +#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ +#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ + +#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ +#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ + +#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ +#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ + +#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ +#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ + +#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ +#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ + +#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ +#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ + +#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ +#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ + +#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ +#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ + +#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ +#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ + +#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ +#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ + +#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ +#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ + +#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ +#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ + +#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ +#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ + +#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ +#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ + +#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ +#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ + +#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ +#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ + +#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ +#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ + +#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ +#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ +#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ +#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ +#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ +#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ +#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ +#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ + +#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ +#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ + +#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ +#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ + +#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ +#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ + +#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ +#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ + +#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ +#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ + +#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ +#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ + +#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ +#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ + +#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ +#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ + +#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ +#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ + +#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ +#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ + +#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ +#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ + +#define EPWM_DACTRGEN_CUTRGEN0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGEN0 Position */ +#define EPWM_DACTRGEN_CUTRGEN0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN0 Mask */ + +#define EPWM_DACTRGEN_CUTRGEN1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGEN1 Position */ +#define EPWM_DACTRGEN_CUTRGEN1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN1 Mask */ + +#define EPWM_DACTRGEN_CUTRGEN2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGEN2 Position */ +#define EPWM_DACTRGEN_CUTRGEN2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN2 Mask */ + +#define EPWM_DACTRGEN_CUTRGEN3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGEN3 Position */ +#define EPWM_DACTRGEN_CUTRGEN3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN3 Mask */ + +#define EPWM_DACTRGEN_CUTRGEN4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGEN4 Position */ +#define EPWM_DACTRGEN_CUTRGEN4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN4 Mask */ + +#define EPWM_DACTRGEN_CUTRGEN5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGEN5 Position */ +#define EPWM_DACTRGEN_CUTRGEN5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGEN5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGEN5 Mask */ + +#define EPWM_DACTRGEN_CDTRGEN0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGEN0 Position */ +#define EPWM_DACTRGEN_CDTRGEN0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN0 Mask */ + +#define EPWM_DACTRGEN_CDTRGEN1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGEN1 Position */ +#define EPWM_DACTRGEN_CDTRGEN1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN1 Mask */ + +#define EPWM_DACTRGEN_CDTRGEN2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGEN2 Position */ +#define EPWM_DACTRGEN_CDTRGEN2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN2 Mask */ + +#define EPWM_DACTRGEN_CDTRGEN3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGEN3 Position */ +#define EPWM_DACTRGEN_CDTRGEN3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN3 Mask */ + +#define EPWM_DACTRGEN_CDTRGEN4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGEN4 Position */ +#define EPWM_DACTRGEN_CDTRGEN4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN4 Mask */ + +#define EPWM_DACTRGEN_CDTRGEN5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGEN5 Position */ +#define EPWM_DACTRGEN_CDTRGEN5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGEN5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGEN5 Mask */ + +#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ +#define EPWM_EADCTS0_TRGSEL0_Msk (0x1ful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ +#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ + +#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ +#define EPWM_EADCTS0_TRGSEL1_Msk (0x1ful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ +#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ + +#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ +#define EPWM_EADCTS0_TRGSEL2_Msk (0x1ful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ +#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ + +#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ +#define EPWM_EADCTS0_TRGSEL3_Msk (0x1ful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ +#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ + +#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ +#define EPWM_EADCTS1_TRGSEL4_Msk (0x1ful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ +#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ + +#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ +#define EPWM_EADCTS1_TRGSEL5_Msk (0x1ful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ +#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ + +#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ +#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ + +#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ +#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ + +#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ +#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ + +#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ +#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ + +#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ +#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ + +#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ +#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ + +#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ +#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ + +#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ +#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ + +#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ +#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ + +#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ +#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ + +#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ +#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ + +#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ +#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ + +#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ +#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ + +#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ +#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ + +#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ +#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ + +#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ +#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ + +#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ +#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ + +#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ +#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ + +#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ +#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ + +#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ +#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ + +#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ +#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ + +#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ +#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ + +#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ +#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ + +#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ +#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ + +#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ +#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ + +#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ +#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ + +#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ +#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ + +#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ +#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ + +#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ +#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ + +#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ +#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ + +#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ +#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ + +#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ +#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ + +#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ +#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ + +#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ +#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ + +#define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ +#define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ + +#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ +#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ + +#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ +#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ + +#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ +#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ + +#define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ +#define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ + +#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ +#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ + +#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ +#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ + +#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ +#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ + +#define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ +#define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ + +#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ +#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ + +#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ +#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ + +#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ +#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ + +#define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ +#define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ + +#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ +#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ + +#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ +#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ + +#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ +#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ + +#define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ +#define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ + +#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ +#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ + +#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ +#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ + +#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ +#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ + +#define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ +#define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ + +#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ +#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ + +#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ +#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ + +#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ +#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ + +#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ +#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ + +#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ +#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ + +#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ +#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ + +#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ +#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ + +#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ +#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ + +#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ +#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ + +#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ +#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ + +#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ +#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ + +#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ +#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ + +#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ +#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ + +#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ +#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ + +#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ +#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ + +#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ +#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ + +#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ +#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ + +#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ +#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ + +#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ +#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ + +#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ +#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ + +#define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ +#define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ + +#define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ +#define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ + +#define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ +#define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ + +#define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ +#define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ + +#define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ +#define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ + +#define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ +#define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ + +#define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ +#define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ + +#define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ +#define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ + +#define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ +#define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ + +#define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ +#define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ + +#define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ +#define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ + +#define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ +#define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ + +#define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ +#define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ + +#define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ +#define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ + +#define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ +#define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ + +#define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ +#define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ + +#define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ +#define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ + +#define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ +#define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ + +#define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ +#define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ + +#define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ +#define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ + +#define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ +#define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ + +#define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ +#define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ + +#define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ +#define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ + +#define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ +#define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ + +#define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ +#define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ + +#define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ +#define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ + +#define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ +#define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ + +#define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ +#define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ + +#define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ +#define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ + +#define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ +#define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ + +#define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ +#define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ + +#define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ +#define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ + +#define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ +#define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ + +#define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ +#define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ + +#define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ +#define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ + +#define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ +#define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ + +#define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ +#define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ + +#define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ +#define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ + +#define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ +#define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ + +#define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ +#define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ + +#define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ +#define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ + +#define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ +#define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ + +#define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ +#define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ + +#define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ +#define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ + +#define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ +#define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ + +#define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ +#define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ + +#define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ +#define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ + +#define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ +#define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ + +#define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ +#define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ + +#define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ +#define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ + +#define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ +#define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ + +#define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ +#define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ + +#define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ +#define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ + +#define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ +#define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ + +#define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ +#define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ + +#define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ +#define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ + +#define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ +#define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ + +#define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ +#define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ + +#define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ +#define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ + +#define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ +#define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ +#define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ +#define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ +#define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ +#define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ +#define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ +#define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ + +#define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ +#define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ + +#define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ +#define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ + +#define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ +#define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ + +#define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ +#define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ + +#define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ +#define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ + +#define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ +#define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ +#define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ +#define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ +#define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ +#define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ +#define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ +#define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ + +#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ +#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ +#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ +#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ +#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ +#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ +#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ +#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ + +#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ +#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ + +#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ +#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ + +#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ +#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ + +#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ +#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ + +#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ +#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ + +#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ +#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ + +#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ +#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ + +#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ +#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ + +#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ +#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ + +#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ +#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ + +#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ +#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ + +#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ +#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ +#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ +#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ +#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ +#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ +#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ +#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ +#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ +#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ +#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ +#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ +#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ +#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ +#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ +#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ +#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ +#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ +#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ +#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ +#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ +#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ +#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ +#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ +#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ +#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ +#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ +#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ +#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ +#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ +#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ +#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ +#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ +#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ +#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ +#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ +#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ +#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ + +#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ +#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ +#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ +#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ +#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ + +#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ +#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ +#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ +#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ +#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ + +#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ +#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ +#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ +#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ +#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ +#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ +#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ +#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ +#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ +#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ +#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ +#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ +#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ +#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ +#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ +#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ +#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ +#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ +#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ +#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ + +#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ +#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ + +#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ +#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ + +#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ +#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ + +#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ +#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ + +#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ +#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ + +#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ +#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ + +#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ +#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ + +#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ +#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ + +#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ +#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ + +#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ +#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ + +#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ +#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ + +#define EPWM_CAPNF0_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF0: CAPNFEN Position */ +#define EPWM_CAPNF0_CAPNFEN_Msk (0x1ul << EPWM_CAPNF0_CAPNFEN_Pos) /*!< EPWM_T::CAPNF0: CAPNFEN Mask */ + +#define EPWM_CAPNF0_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF0: CAPNFSEL Position */ +#define EPWM_CAPNF0_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF0_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF0: CAPNFSEL Mask */ + +#define EPWM_CAPNF0_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF0: CAPNFCNT Position */ +#define EPWM_CAPNF0_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF0_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF0: CAPNFCNT Mask */ + +#define EPWM_CAPNF1_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF1: CAPNFEN Position */ +#define EPWM_CAPNF1_CAPNFEN_Msk (0x1ul << EPWM_CAPNF1_CAPNFEN_Pos) /*!< EPWM_T::CAPNF1: CAPNFEN Mask */ + +#define EPWM_CAPNF1_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF1: CAPNFSEL Position */ +#define EPWM_CAPNF1_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF1_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF1: CAPNFSEL Mask */ + +#define EPWM_CAPNF1_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF1: CAPNFCNT Position */ +#define EPWM_CAPNF1_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF1_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF1: CAPNFCNT Mask */ + +#define EPWM_CAPNF2_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF2: CAPNFEN Position */ +#define EPWM_CAPNF2_CAPNFEN_Msk (0x1ul << EPWM_CAPNF2_CAPNFEN_Pos) /*!< EPWM_T::CAPNF2: CAPNFEN Mask */ + +#define EPWM_CAPNF2_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF2: CAPNFSEL Position */ +#define EPWM_CAPNF2_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF2_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF2: CAPNFSEL Mask */ + +#define EPWM_CAPNF2_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF2: CAPNFCNT Position */ +#define EPWM_CAPNF2_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF2_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF2: CAPNFCNT Mask */ + +#define EPWM_CAPNF3_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF3: CAPNFEN Position */ +#define EPWM_CAPNF3_CAPNFEN_Msk (0x1ul << EPWM_CAPNF3_CAPNFEN_Pos) /*!< EPWM_T::CAPNF3: CAPNFEN Mask */ + +#define EPWM_CAPNF3_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF3: CAPNFSEL Position */ +#define EPWM_CAPNF3_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF3_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF3: CAPNFSEL Mask */ + +#define EPWM_CAPNF3_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF3: CAPNFCNT Position */ +#define EPWM_CAPNF3_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF3_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF3: CAPNFCNT Mask */ + +#define EPWM_CAPNF4_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF4: CAPNFEN Position */ +#define EPWM_CAPNF4_CAPNFEN_Msk (0x1ul << EPWM_CAPNF4_CAPNFEN_Pos) /*!< EPWM_T::CAPNF4: CAPNFEN Mask */ + +#define EPWM_CAPNF4_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF4: CAPNFSEL Position */ +#define EPWM_CAPNF4_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF4_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF4: CAPNFSEL Mask */ + +#define EPWM_CAPNF4_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF4: CAPNFCNT Position */ +#define EPWM_CAPNF4_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF4_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF4: CAPNFCNT Mask */ + +#define EPWM_CAPNF5_CAPNFEN_Pos (0) /*!< EPWM_T::CAPNF5: CAPNFEN Position */ +#define EPWM_CAPNF5_CAPNFEN_Msk (0x1ul << EPWM_CAPNF5_CAPNFEN_Pos) /*!< EPWM_T::CAPNF5: CAPNFEN Mask */ + +#define EPWM_CAPNF5_CAPNFSEL_Pos (4) /*!< EPWM_T::CAPNF5: CAPNFSEL Position */ +#define EPWM_CAPNF5_CAPNFSEL_Msk (0x7ul << EPWM_CAPNF5_CAPNFSEL_Pos) /*!< EPWM_T::CAPNF5: CAPNFSEL Mask */ + +#define EPWM_CAPNF5_CAPNFCNT_Pos (8) /*!< EPWM_T::CAPNF5: CAPNFCNT Position */ +#define EPWM_CAPNF5_CAPNFCNT_Msk (0x7ul << EPWM_CAPNF5_CAPNFCNT_Pos) /*!< EPWM_T::CAPNF5: CAPNFCNT Mask */ + +#define EPWM_EXTETCTL0_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL0: EXETEN Position */ +#define EPWM_EXTETCTL0_EXETEN_Msk (0x1ul << EPWM_EXTETCTL0_EXETEN_Pos) /*!< EPWM_T::EXTETCTL0: EXETEN Mask */ + +#define EPWM_EXTETCTL0_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL0: CNTACTS Position */ +#define EPWM_EXTETCTL0_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL0_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL0: CNTACTS Mask */ + +#define EPWM_EXTETCTL0_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL0: EXTTRGS Position */ +#define EPWM_EXTETCTL0_EXTTRGS_Msk (0xful << EPWM_EXTETCTL0_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL0: EXTTRGS Mask */ + +#define EPWM_EXTETCTL1_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL1: EXETEN Position */ +#define EPWM_EXTETCTL1_EXETEN_Msk (0x1ul << EPWM_EXTETCTL1_EXETEN_Pos) /*!< EPWM_T::EXTETCTL1: EXETEN Mask */ + +#define EPWM_EXTETCTL1_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL1: CNTACTS Position */ +#define EPWM_EXTETCTL1_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL1_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL1: CNTACTS Mask */ + +#define EPWM_EXTETCTL1_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL1: EXTTRGS Position */ +#define EPWM_EXTETCTL1_EXTTRGS_Msk (0xful << EPWM_EXTETCTL1_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL1: EXTTRGS Mask */ + +#define EPWM_EXTETCTL2_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL2: EXETEN Position */ +#define EPWM_EXTETCTL2_EXETEN_Msk (0x1ul << EPWM_EXTETCTL2_EXETEN_Pos) /*!< EPWM_T::EXTETCTL2: EXETEN Mask */ + +#define EPWM_EXTETCTL2_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL2: CNTACTS Position */ +#define EPWM_EXTETCTL2_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL2_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL2: CNTACTS Mask */ + +#define EPWM_EXTETCTL2_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL2: EXTTRGS Position */ +#define EPWM_EXTETCTL2_EXTTRGS_Msk (0xful << EPWM_EXTETCTL2_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL2: EXTTRGS Mask */ + +#define EPWM_EXTETCTL3_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL3: EXETEN Position */ +#define EPWM_EXTETCTL3_EXETEN_Msk (0x1ul << EPWM_EXTETCTL3_EXETEN_Pos) /*!< EPWM_T::EXTETCTL3: EXETEN Mask */ + +#define EPWM_EXTETCTL3_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL3: CNTACTS Position */ +#define EPWM_EXTETCTL3_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL3_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL3: CNTACTS Mask */ + +#define EPWM_EXTETCTL3_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL3: EXTTRGS Position */ +#define EPWM_EXTETCTL3_EXTTRGS_Msk (0xful << EPWM_EXTETCTL3_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL3: EXTTRGS Mask */ + +#define EPWM_EXTETCTL4_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL4: EXETEN Position */ +#define EPWM_EXTETCTL4_EXETEN_Msk (0x1ul << EPWM_EXTETCTL4_EXETEN_Pos) /*!< EPWM_T::EXTETCTL4: EXETEN Mask */ + +#define EPWM_EXTETCTL4_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL4: CNTACTS Position */ +#define EPWM_EXTETCTL4_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL4_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL4: CNTACTS Mask */ + +#define EPWM_EXTETCTL4_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL4: EXTTRGS Position */ +#define EPWM_EXTETCTL4_EXTTRGS_Msk (0xful << EPWM_EXTETCTL4_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL4: EXTTRGS Mask */ + +#define EPWM_EXTETCTL5_EXETEN_Pos (0) /*!< EPWM_T::EXTETCTL5: EXETEN Position */ +#define EPWM_EXTETCTL5_EXETEN_Msk (0x1ul << EPWM_EXTETCTL5_EXETEN_Pos) /*!< EPWM_T::EXTETCTL5: EXETEN Mask */ + +#define EPWM_EXTETCTL5_CNTACTS_Pos (4) /*!< EPWM_T::EXTETCTL5: CNTACTS Position */ +#define EPWM_EXTETCTL5_CNTACTS_Msk (0x3ul << EPWM_EXTETCTL5_CNTACTS_Pos) /*!< EPWM_T::EXTETCTL5: CNTACTS Mask */ + +#define EPWM_EXTETCTL5_EXTTRGS_Pos (8) /*!< EPWM_T::EXTETCTL5: EXTTRGS Position */ +#define EPWM_EXTETCTL5_EXTTRGS_Msk (0xful << EPWM_EXTETCTL5_EXTTRGS_Pos) /*!< EPWM_T::EXTETCTL5: EXTTRGS Mask */ + +#define EPWM_SWEOFCTL_OUTACTS0_Pos (0) /*!< EPWM_T::SWEOFCTL: OUTACTS0 Position */ +#define EPWM_SWEOFCTL_OUTACTS0_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS0_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS0 Mask */ + +#define EPWM_SWEOFCTL_OUTACTS1_Pos (2) /*!< EPWM_T::SWEOFCTL: OUTACTS1 Position */ +#define EPWM_SWEOFCTL_OUTACTS1_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS1_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS1 Mask */ + +#define EPWM_SWEOFCTL_OUTACTS2_Pos (4) /*!< EPWM_T::SWEOFCTL: OUTACTS2 Position */ +#define EPWM_SWEOFCTL_OUTACTS2_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS2_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS2 Mask */ + +#define EPWM_SWEOFCTL_OUTACTS3_Pos (6) /*!< EPWM_T::SWEOFCTL: OUTACTS3 Position */ +#define EPWM_SWEOFCTL_OUTACTS3_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS3_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS3 Mask */ + +#define EPWM_SWEOFCTL_OUTACTS4_Pos (8) /*!< EPWM_T::SWEOFCTL: OUTACTS4 Position */ +#define EPWM_SWEOFCTL_OUTACTS4_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS4_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS4 Mask */ + +#define EPWM_SWEOFCTL_OUTACTS5_Pos (10) /*!< EPWM_T::SWEOFCTL: OUTACTS5 Position */ +#define EPWM_SWEOFCTL_OUTACTS5_Msk (0x3ul << EPWM_SWEOFCTL_OUTACTS5_Pos) /*!< EPWM_T::SWEOFCTL: OUTACTS5 Mask */ + +#define EPWM_SWEOFTRG_SWETRG0_Pos (0) /*!< EPWM_T::SWEOFTRG: SWETRG0 Position */ +#define EPWM_SWEOFTRG_SWETRG0_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG0_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG0 Mask */ + +#define EPWM_SWEOFTRG_SWETRG1_Pos (1) /*!< EPWM_T::SWEOFTRG: SWETRG1 Position */ +#define EPWM_SWEOFTRG_SWETRG1_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG1_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG1 Mask */ + +#define EPWM_SWEOFTRG_SWETRG2_Pos (2) /*!< EPWM_T::SWEOFTRG: SWETRG2 Position */ +#define EPWM_SWEOFTRG_SWETRG2_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG2_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG2 Mask */ + +#define EPWM_SWEOFTRG_SWETRG3_Pos (3) /*!< EPWM_T::SWEOFTRG: SWETRG3 Position */ +#define EPWM_SWEOFTRG_SWETRG3_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG3_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG3 Mask */ + +#define EPWM_SWEOFTRG_SWETRG4_Pos (4) /*!< EPWM_T::SWEOFTRG: SWETRG4 Position */ +#define EPWM_SWEOFTRG_SWETRG4_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG4_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG4 Mask */ + +#define EPWM_SWEOFTRG_SWETRG5_Pos (5) /*!< EPWM_T::SWEOFTRG: SWETRG5 Position */ +#define EPWM_SWEOFTRG_SWETRG5_Msk (0x1ul << EPWM_SWEOFTRG_SWETRG5_Pos) /*!< EPWM_T::SWEOFTRG: SWETRG5 Mask */ + +#define EPWM_CLKPSC0_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0: CLKPSC Position */ +#define EPWM_CLKPSC0_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0: CLKPSC Mask */ + +#define EPWM_CLKPSC1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC1: CLKPSC Position */ +#define EPWM_CLKPSC1_CLKPSC_Msk (0xffful << EPWM_CLKPSC1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC1: CLKPSC Mask */ + +#define EPWM_CLKPSC2_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2: CLKPSC Position */ +#define EPWM_CLKPSC2_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2: CLKPSC Mask */ + +#define EPWM_CLKPSC3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC3: CLKPSC Position */ +#define EPWM_CLKPSC3_CLKPSC_Msk (0xffful << EPWM_CLKPSC3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC3: CLKPSC Mask */ + +#define EPWM_CLKPSC4_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4: CLKPSC Position */ +#define EPWM_CLKPSC4_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4: CLKPSC Mask */ + +#define EPWM_CLKPSC5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC5: CLKPSC Position */ +#define EPWM_CLKPSC5_CLKPSC_Msk (0xffful << EPWM_CLKPSC5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC5: CLKPSC Mask */ + +#define EPWM_RDTCNT0_1_RDTCNT_Pos (0) /*!< EPWM_T::RDTCNT0_1: RDTCNT Position */ +#define EPWM_RDTCNT0_1_RDTCNT_Msk (0xffful << EPWM_RDTCNT0_1_RDTCNT_Pos) /*!< EPWM_T::RDTCNT0_1: RDTCNT Mask */ + +#define EPWM_RDTCNT2_3_RDTCNT_Pos (0) /*!< EPWM_T::RDTCNT2_3: RDTCNT Position */ +#define EPWM_RDTCNT2_3_RDTCNT_Msk (0xffful << EPWM_RDTCNT2_3_RDTCNT_Pos) /*!< EPWM_T::RDTCNT2_3: RDTCNT Mask */ + +#define EPWM_RDTCNT4_5_RDTCNT_Pos (0) /*!< EPWM_T::RDTCNT4_5: RDTCNT Position */ +#define EPWM_RDTCNT4_5_RDTCNT_Msk (0xffful << EPWM_RDTCNT4_5_RDTCNT_Pos) /*!< EPWM_T::RDTCNT4_5: RDTCNT Mask */ + +#define EPWM_FDTCNT0_1_FDTCNT_Pos (0) /*!< EPWM_T::FDTCNT0_1: FDTCNT Position */ +#define EPWM_FDTCNT0_1_FDTCNT_Msk (0xffful << EPWM_FDTCNT0_1_FDTCNT_Pos) /*!< EPWM_T::FDTCNT0_1: FDTCNT Mask */ + +#define EPWM_FDTCNT2_3_FDTCNT_Pos (0) /*!< EPWM_T::FDTCNT2_3: FDTCNT Position */ +#define EPWM_FDTCNT2_3_FDTCNT_Msk (0xffful << EPWM_FDTCNT2_3_FDTCNT_Pos) /*!< EPWM_T::FDTCNT2_3: FDTCNT Mask */ + +#define EPWM_FDTCNT4_5_FDTCNT_Pos (0) /*!< EPWM_T::FDTCNT4_5: FDTCNT Position */ +#define EPWM_FDTCNT4_5_FDTCNT_Msk (0xffful << EPWM_FDTCNT4_5_FDTCNT_Pos) /*!< EPWM_T::FDTCNT4_5: FDTCNT Mask */ + +#define EPWM_DTCTL_RDTEN0_Pos (0) /*!< EPWM_T::DTCTL: RDTEN0 Position */ +#define EPWM_DTCTL_RDTEN0_Msk (0x1ul << EPWM_DTCTL_RDTEN0_Pos) /*!< EPWM_T::DTCTL: RDTEN0 Mask */ + +#define EPWM_DTCTL_RDTEN2_Pos (1) /*!< EPWM_T::DTCTL: RDTEN2 Position */ +#define EPWM_DTCTL_RDTEN2_Msk (0x1ul << EPWM_DTCTL_RDTEN2_Pos) /*!< EPWM_T::DTCTL: RDTEN2 Mask */ + +#define EPWM_DTCTL_RDTEN4_Pos (2) /*!< EPWM_T::DTCTL: RDTEN4 Position */ +#define EPWM_DTCTL_RDTEN4_Msk (0x1ul << EPWM_DTCTL_RDTEN4_Pos) /*!< EPWM_T::DTCTL: RDTEN4 Mask */ + +#define EPWM_DTCTL_FDTEN0_Pos (8) /*!< EPWM_T::DTCTL: FDTEN0 Position */ +#define EPWM_DTCTL_FDTEN0_Msk (0x1ul << EPWM_DTCTL_FDTEN0_Pos) /*!< EPWM_T::DTCTL: FDTEN0 Mask */ + +#define EPWM_DTCTL_FDTEN2_Pos (9) /*!< EPWM_T::DTCTL: FDTEN2 Position */ +#define EPWM_DTCTL_FDTEN2_Msk (0x1ul << EPWM_DTCTL_FDTEN2_Pos) /*!< EPWM_T::DTCTL: FDTEN2 Mask */ + +#define EPWM_DTCTL_FDTEN4_Pos (10) /*!< EPWM_T::DTCTL: FDTEN4 Position */ +#define EPWM_DTCTL_FDTEN4_Msk (0x1ul << EPWM_DTCTL_FDTEN4_Pos) /*!< EPWM_T::DTCTL: FDTEN4 Mask */ + +#define EPWM_DTCTL_DTCKSEL0_Pos (16) /*!< EPWM_T::DTCTL: DTCKSEL0 Position */ +#define EPWM_DTCTL_DTCKSEL0_Msk (0x1ul << EPWM_DTCTL_DTCKSEL0_Pos) /*!< EPWM_T::DTCTL: DTCKSEL0 Mask */ + +#define EPWM_DTCTL_DTCKSEL2_Pos (17) /*!< EPWM_T::DTCTL: DTCKSEL2 Position */ +#define EPWM_DTCTL_DTCKSEL2_Msk (0x1ul << EPWM_DTCTL_DTCKSEL2_Pos) /*!< EPWM_T::DTCTL: DTCKSEL2 Mask */ + +#define EPWM_DTCTL_DTCKSEL4_Pos (18) /*!< EPWM_T::DTCTL: DTCKSEL4 Position */ +#define EPWM_DTCTL_DTCKSEL4_Msk (0x1ul << EPWM_DTCTL_DTCKSEL4_Pos) /*!< EPWM_T::DTCTL: DTCKSEL4 Mask */ + +#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ +#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ + +#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ +#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ + +#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ +#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ + +#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ +#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ + +#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ +#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ + +#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ +#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ + +#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ +#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ + +#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ +#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ + +#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ +#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ + +#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ +#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ + +#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ +#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ + +#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ +#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ + +#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ +#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ + +#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ +#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ + +#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ +#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ + +#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ +#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ + +#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ +#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ + +#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ +#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ + +#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ +#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ + +#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ +#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ + +#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ +#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ + +#define EPWM_CPSCBUF0_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0: CPSCBUF Position */ +#define EPWM_CPSCBUF0_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0: CPSCBUF Mask */ + +#define EPWM_CPSCBUF1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF1: CPSCBUF Position */ +#define EPWM_CPSCBUF1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF1: CPSCBUF Mask */ + +#define EPWM_CPSCBUF2_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2: CPSCBUF Position */ +#define EPWM_CPSCBUF2_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2: CPSCBUF Mask */ + +#define EPWM_CPSCBUF3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF3: CPSCBUF Position */ +#define EPWM_CPSCBUF3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF3: CPSCBUF Mask */ + +#define EPWM_CPSCBUF4_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4: CPSCBUF Position */ +#define EPWM_CPSCBUF4_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4: CPSCBUF Mask */ + +#define EPWM_CPSCBUF5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF5: CPSCBUF Position */ +#define EPWM_CPSCBUF5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF5: CPSCBUF Mask */ + +#define EPWM_IFACNT0_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT0: ACUCNT Position */ +#define EPWM_IFACNT0_ACUCNT_Msk (0xfffful << EPWM_IFACNT0_ACUCNT_Pos) /*!< EPWM_T::IFACNT0: ACUCNT Mask */ + +#define EPWM_IFACNT1_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT1: ACUCNT Position */ +#define EPWM_IFACNT1_ACUCNT_Msk (0xfffful << EPWM_IFACNT1_ACUCNT_Pos) /*!< EPWM_T::IFACNT1: ACUCNT Mask */ + +#define EPWM_IFACNT2_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT2: ACUCNT Position */ +#define EPWM_IFACNT2_ACUCNT_Msk (0xfffful << EPWM_IFACNT2_ACUCNT_Pos) /*!< EPWM_T::IFACNT2: ACUCNT Mask */ + +#define EPWM_IFACNT3_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT3: ACUCNT Position */ +#define EPWM_IFACNT3_ACUCNT_Msk (0xfffful << EPWM_IFACNT3_ACUCNT_Pos) /*!< EPWM_T::IFACNT3: ACUCNT Mask */ + +#define EPWM_IFACNT4_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT4: ACUCNT Position */ +#define EPWM_IFACNT4_ACUCNT_Msk (0xfffful << EPWM_IFACNT4_ACUCNT_Pos) /*!< EPWM_T::IFACNT4: ACUCNT Mask */ + +#define EPWM_IFACNT5_ACUCNT_Pos (0) /*!< EPWM_T::IFACNT5: ACUCNT Position */ +#define EPWM_IFACNT5_ACUCNT_Msk (0xfffful << EPWM_IFACNT5_ACUCNT_Pos) /*!< EPWM_T::IFACNT5: ACUCNT Mask */ + +/**@}*/ /* EPWM_CONST */ +/**@}*/ /* end of EPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EPWM_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/eqei_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/eqei_reg.h new file mode 100644 index 0000000..4198870 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/eqei_reg.h @@ -0,0 +1,445 @@ +/**************************************************************************//** + * @file qei_reg.h + * @version V1.00 + * @brief EQEI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EQEI_REG_H__ +#define __EQEI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EQEI Quadrature Encoder Interface(EQEI) + Memory Mapped Structure for EQEI Controller +@{ */ + +typedef struct +{ + + + /** + * @var EQEI_T::CNT + * Offset: 0x00 EQEI Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |Quadrature Encoder Interface Counter + * | | |A 32-bit up/down counter + * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is zero + * | | |This register performs an integrator which count value is proportional to the encoder position + * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: + * | | |1. Software is written if EQEIEN (EQEI_CTL[29]) = 0. + * | | |2. Compare-match event if EQEIEN(EQEI_CTL[29])=1 and EQEI is in compare-counting mode. + * | | |3. Index signal change if EQEIEN(EQEI_CTL[29])=1 and IDXRLDEN (EQEI_CTL[27])=1. + * @var EQEI_T::CNTHOLD + * Offset: 0x04 EQEI Counter Hold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold + * | | |When bit HOLDCNT (EQEI_CTL[24]) goes from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register. + * @var EQEI_T::CNTLATCH + * Offset: 0x08 EQEI Counter Index Latch Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch + * | | |When the IDXF (EQEI_STATUS[0]) bit is set, the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register. + * @var EQEI_T::CNTCMP + * Offset: 0x0C EQEI Counter Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare + * | | |If the EQEI controller is in the compare-counting mode CMPEN (EQEI_CTL[28]) =1, when the value of CNT(EQEI_CNT[31:0]) matches CNTCMP(EQEI_CNTCMP[31:0]), CMPF will be set + * | | |This register is software writable. + * @var EQEI_T::CNTMAX + * Offset: 0x14 EQEI Pre-set Maximum Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count + * | | |This register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode + * @var EQEI_T::CTL + * Offset: 0x18 EQEI Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock . + * | | |000 = EQEI_CLK. + * | | |001 = EQEI_CLK/2. + * | | |010 = EQEI_CLK/4. + * | | |011 = EQEI_CLK/16. + * | | |100 = EQEI_CLK/32. + * | | |101 = EQEI_CLK/64. + * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit + * | | |0 = The noise filter of EQEI controller Enabled. + * | | |1 = The noise filter of EQEI controller Disabled. + * |[4] |CHAEN |QEA Input to EQEI Controller Enable Bit + * | | |0 = QEA input to EQEI Controller Disabled. + * | | |1 = QEA input to EQEI Controller Enabled. + * |[5] |CHBEN |QEB Input to EQEI Controller Enable Bit + * | | |0 = QEB input to EQEI Controller Disabled. + * | | |1 = QEB input to EQEI Controller Enabled. + * |[6] |IDXEN |IDX Input to EQEI Controller Enable Bit + * | | |0 = IDX input to EQEI Controller Disabled. + * | | |1 = IDX input to EQEI Controller Enabled. + * |[7] |IDXRSTEN |IDX Reset EQEI Position Counter Enable Bit + * | | |0 = Reset EQEI position counter in every time IDX signal. + * | | |1 = Reset EQEI position counter in first time IDX signal. + * | | |Note: IDXRLDEN(EQEI_CTL[27]) should be set 1. + * |[10:8] |MODE |QEI Counting Mode Selection + * | | |There are seven quadrature encoder pulse counter operation modes. + * | | |000 = X4 Free-counting Mode. + * | | |001 = X2 Free-counting Mode. + * | | |010 = X4 Compare-counting Mode. + * | | |011 = X2 Compare-counting Mode. + * | | |100 = Phase Counting Mode Type 1. (PCMT1). + * | | |101 = Phase Counting Mode Type 2. (PCMT2). + * | | |110 = Directional Counting Mode. + * | | |111 = Reserved. + * | | |Note: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode. + * |[12] |CHAINV |Inverse QEA Input Polarity + * | | |0 = Not inverse QEA input polarity. + * | | |1 = QEA input polarity is inversed to EQEI controller. + * |[13] |CHBINV |Inverse QEB Input Polarity + * | | |0 = Not inverse QEB input polarity. + * | | |1 = QEB input polarity is inversed to EQEI controller. + * |[14] |IDXINV |Inverse IDX Input Polarity + * | | |0 = Not inverse IDX input polarity. + * | | |1 = IDX input polarity is inversed to EQEI controller. + * |[15] |IDXRSTEV |IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only) + * | | |0 = The next IDX level high signal reset function is disabled. + * | | |1 = The next IDX level high signal reset function is enabled. + * | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1. + * |[16] |OVUNIEN |OVUNF Trigger EQEI Interrupt Enable Bit + * | | |0 = OVUNF can trigger EQEI controller interrupt Disabled. + * | | |1 = OVUNF can trigger EQEI controller interrupt Enabled. + * |[17] |DIRIEN |DIRCHGF Trigger EQEI Interrupt Enable Bit + * | | |0 = DIRCHGF can trigger EQEI controller interrupt Disabled. + * | | |1 = DIRCHGF can trigger EQEI controller interrupt Enabled. + * |[18] |CMPIEN |CMPF Trigger EQEI Interrupt Enable Bit + * | | |0 = CMPF can trigger EQEI controller interrupt Disabled. + * | | |1 = CMPF can trigger EQEI controller interrupt Enabled. + * |[19] |IDXIEN |IDXF Trigger EQEI Interrupt Enable Bit + * | | |0 = The IDXF can trigger EQEI interrupt Disabled. + * | | |1 = The IDXF can trigger EQEI interrupt Enabled. + * |[20] |HOLDTMR0 |Hold EQEI_CNT by Timer 0 + * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. + * |[21] |HOLDTMR1 |Hold EQEI_CNT by Timer 1 + * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. + * |[22] |HOLDTMR2 |Hold EQEI_CNT by Timer 2 + * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. + * |[23] |HOLDTMR3 |Hold EQEI_CNT by Timer 3 + * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. + * |[24] |HOLDCNT |Hold EQEI_CNT Control + * | | |When this bit is set from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]) + * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). + * | | |0 = No operation. + * | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]). + * | | |Note: This bit is automatically cleared after EQEI_CNTHOLD holds EQEI_CNT value. + * |[25] |IDXLATEN |Index Latch EQEI_CNT Enable Bit + * | | |If this bit is set to high, the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX. + * | | |0 = The index signal latch EQEI counter function Disabled. + * | | |1 = The index signal latch EQEI counter function Enabled. + * |[27] |IDXRLDEN |Index Trigger EQEI_CNT Reload Enable Bit + * | | |When this bit is high and a rising edge comes on signal CHX, the CNT(EQEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(EQEI_STATUS[8]) = 1); while the CNT(EQEI_CNT[31:0]) will be reloaded with CNTMAX (EQEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(EQEI_STATUS[8]) = 0). + * | | |0 = Reload function Disabled. + * | | |1 = EQEI_CNT re-initialized by Index signal Enabled. + * |[28] |CMPEN |The Compare Function Enable Bit + * | | |The compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0]), if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0]), the flag CMPF will be set. + * | | |0 = Compare function Disabled. + * | | |1 = Compare function Enabled. + * |[29] |EQEIEN |Enhanced Quadrature Encoder Interface Controller Enable Bit + * | | |0 = EQEI controller function Disabled. + * | | |1 = EQEI controller function Enabled. + * @var EQEI_T::CTL2 + * Offset: 0x1C EQEI Controller Control Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWAPEN |Swap Function Enable Bit + * | | |0 = EQEI swap function Disabled. + * | | |1 = EQEI swap function Enabled. + * |[2:1] |CRS |Clock Rate Setting without Quadrature Mode + * | | |00 = EQEI counter only counts the falling edge. + * | | |01 = EQEI counter only counts the rising edge. + * | | |10 = EQEI counter counts the rising and falling edge. + * | | |11 = reserved. + * |[5:4] |DIRSRC |Direction Signal Source Select + * | | |00 = Direction signal is determined from EQEI system calculation. + * | | |01 = reserved. + * | | |10 = Direction signal is tied 1 only for direction up count mode. + * | | |11 = Direction signal is tied 0 only for down count mode. + * |[8] |UTEN |Unit Timer Function Enable Bit + * | | |0 = EQEI unit timer function is disable. + * | | |1 = EQEI unit timer function is enable. + * |[9] |UTHOLDEN |Unit Timer Counter Hold Enable Bit + * | | |0 = No operation. + * | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]) when UTCNT matches UTCMP(EQEI_UTCMP[31:0]). + * |[10] |UTEVTRST |Enable Bit to Reset EQEI Position Counter by Unit Timer Event + * | | |0 = Disable to reset EQEI position counter feature when unit timer counter event occurs. + * | | |1 = Enable to reset EQEI position counter feature when unit timer counter event occurs. + * |[11] |IDXRSTUTS |IDX Resets Unit Timer Select Bit + * | | |0 = Unit timer will not be reset when IDX reset event happens. + * | | |1 = Resets unit timer or not will follow EQEI_CNT when IDX reset event happens. + * |[16] |PHEIEN |PHEF Trigger EQEI Interrupt Enable Bit + * | | |0 = PHEF can trigger EQEI controller interrupt Disabled. + * | | |1 = PHEF can trigger EQEI controller interrupt Enabled. + * |[17] |UTIEIEN |UTIEF Trigger EQEI Interrupt Enable Bit + * | | |0 = UTIEF can trigger EQEI controller interrupt Disabled. + * | | |1 = UTIEF can trigger EQEI controller interrupt Enabled. + * @var EQEI_T::UTCNT + * Offset: 0x20 EQEI Unit Timer Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UTCNT |Unit Timer Counter + * | | |A 32-bit unit timer counter which may be reset to an initial value when any of the following events occur: + * | | |1. Software is written if UTEN (EQEI_CTL2[8]) = 0. + * | | |2. UT_EN (EQEI_CTL2[8]) =1, and the unit timer counter value matches UTCMP(EQEI_UTCMP[31:0]). + * | | |3. IDXRLDEN(EQEI_CTL[27]) =1 and IDXRSTUTS(EQEI_CTL2[11]=1, determine the unit timer to be reset or not will follow EQEI_CNT when IDX reset event happens. + * @var EQEI_T::UTCMP + * Offset: 0x24 EQEI Unit Timer Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |UTCMP |Unit Timer Counter Compare + * | | |If the EQEI unit timer is enable (EQEI_CTL2[8]) =1, and the unit timer counter value also matches UTCMP(EQEI_UTCMP[31:0]), then UTIEF (EQEI_STATUS[10]) will be set. This register is software writable. + * @var EQEI_T::STATUS + * Offset: 0x2C EQEI Controller Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDXF |IDX Detected Flag + * | | |When the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high. + * | | |0 = No rising edge detected on signal CHX. + * | | |1 = A rising edge occurs on signal CHX. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CMPF |Compare-match Flag + * | | |If the EQEI compare function is enabled, the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]). + * | | |0 = EQEI counter does not match with CNTCMP(EQEI_CNTCMP[31:0]). + * | | |1 = EQEI counter counts to the same as CNTCMP(EQEI_CNTCMP[31:0]). + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag + * | | |Flag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to zero in compare-counting mode + * | | |Similarly, the flag is set while EQEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (EQEI_CNTMAX[31:0]). + * | | |0 = No overflow or underflow occurs in EQEI counter. + * | | |1 = EQEI counter occurs counting overflow or underflow. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[3] |DIRCHGF |Direction Change Flag + * | | |Flag is set by hardware while EQEI counter counting direction is changed. + * | | |Software can clear this bit by writing 1 to it. + * | | |0 = No change in EQEI counter counting direction. + * | | |1 = EQEI counter counting direction is changed. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[8] |DIRF |QEI Counter Counting Direction Indication + * | | |0 = EQEI Counter is in down-counting. + * | | |1 = EQEI Counter is in up-counting. + * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. + * |[9] |FIDXEF |First IDX Signal Reset Event Flag (Read Only) + * | | |0 = The first IDX reset event has not happened yet. + * | | |1 = The first IDX reset event has happened. + * | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1. + * |[16] |PHEF EQEI |Phase Error Flag + * | | |0 = No Phase error occurs in EQEI CHA and CHB. + * | | |1 = Phase error occurs in EQEI CHA and CHB. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[17] |UTIEF |EQEI Unit Timer Event Flag + * | | |0 = No timer event occurs in EQEI unit timer counter. + * | | |1 = Unit timer event occurs in EQEI unit timer counter. + * | | |Note: This bit is only cleared by writing 1 to it. + */ + __IO uint32_t CNT; /*!< [0x0000] EQEI Counter Register */ + __IO uint32_t CNTHOLD; /*!< [0x0004] EQEI Counter Hold Register */ + __IO uint32_t CNTLATCH; /*!< [0x0008] EQEI Counter Index Latch Register */ + __IO uint32_t CNTCMP; /*!< [0x000c] EQEI Counter Compare Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CNTMAX; /*!< [0x0014] EQEI Pre-set Maximum Count Register */ + __IO uint32_t CTL; /*!< [0x0018] EQEI Controller Control Register */ + __IO uint32_t CTL2; /*!< [0x001C] EQEI Controller Control Register2 */ + __IO uint32_t UTCNT; /*!< [0x0020] EQEI Unit Timer Counter Register */ + __IO uint32_t UTCMP; /*!< [0x0024] EQEI Unit Timer Compare Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t STATUS; /*!< [0x002c] EQEI Controller Status Register */ + +} EQEI_T; + +/** + @addtogroup EQEI_CONST EQEI Bit Field Definition + Constant Definitions for EQEI Controller +@{ */ + +#define EQEI_CNT_CNT_Pos (0) /*!< EQEI_T::CNT: CNT Position */ +#define EQEI_CNT_CNT_Msk (0xfffffffful << EQEI_CNT_CNT_Pos) /*!< EQEI_T::CNT: CNT Mask */ + +#define EQEI_CNTHOLD_CNTHOLD_Pos (0) /*!< EQEI_T::CNTHOLD: CNTHOLD Position */ +#define EQEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << EQEI_CNTHOLD_CNTHOLD_Pos) /*!< EQEI_T::CNTHOLD: CNTHOLD Mask */ + +#define EQEI_CNTLATCH_CNTLATCH_Pos (0) /*!< EQEI_T::CNTLATCH: CNTLATCH Position */ +#define EQEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << EQEI_CNTLATCH_CNTLATCH_Pos) /*!< EQEI_T::CNTLATCH: CNTLATCH Mask */ + +#define EQEI_CNTCMP_CNTCMP_Pos (0) /*!< EQEI_T::CNTCMP: CNTCMP Position */ +#define EQEI_CNTCMP_CNTCMP_Msk (0xfffffffful << EQEI_CNTCMP_CNTCMP_Pos) /*!< EQEI_T::CNTCMP: CNTCMP Mask */ + +#define EQEI_CNTMAX_CNTMAX_Pos (0) /*!< EQEI_T::CNTMAX: CNTMAX Position */ +#define EQEI_CNTMAX_CNTMAX_Msk (0xfffffffful << EQEI_CNTMAX_CNTMAX_Pos) /*!< EQEI_T::CNTMAX: CNTMAX Mask */ + +#define EQEI_CTL_NFCLKSEL_Pos (0) /*!< EQEI_T::CTL: NFCLKSEL Position */ +#define EQEI_CTL_NFCLKSEL_Msk (0x7ul << EQEI_CTL_NFCLKSEL_Pos) /*!< EQEI_T::CTL: NFCLKSEL Mask */ + +#define EQEI_CTL_NFDIS_Pos (3) /*!< EQEI_T::CTL: NFDIS Position */ +#define EQEI_CTL_NFDIS_Msk (0x1ul << EQEI_CTL_NFDIS_Pos) /*!< EQEI_T::CTL: NFDIS Mask */ + +#define EQEI_CTL_CHAEN_Pos (4) /*!< EQEI_T::CTL: CHAEN Position */ +#define EQEI_CTL_CHAEN_Msk (0x1ul << EQEI_CTL_CHAEN_Pos) /*!< EQEI_T::CTL: CHAEN Mask */ + +#define EQEI_CTL_CHBEN_Pos (5) /*!< EQEI_T::CTL: CHBEN Position */ +#define EQEI_CTL_CHBEN_Msk (0x1ul << EQEI_CTL_CHBEN_Pos) /*!< EQEI_T::CTL: CHBEN Mask */ + +#define EQEI_CTL_IDXEN_Pos (6) /*!< EQEI_T::CTL: IDXEN Position */ +#define EQEI_CTL_IDXEN_Msk (0x1ul << EQEI_CTL_IDXEN_Pos) /*!< EQEI_T::CTL: IDXEN Mask */ + +#define EQEI_CTL_IDXRSTEN_Pos (7) /*!< EQEI_T::CTL: IDXRSTEN Position */ +#define EQEI_CTL_IDXRSTEN_Msk (0x1ul << EQEI_CTL_IDXRSTEN_Pos) /*!< EQEI_T::CTL: IDXRSTEN Mask */ + +#define EQEI_CTL_MODE_Pos (8) /*!< EQEI_T::CTL: MODE Position */ +#define EQEI_CTL_MODE_Msk (0x7ul << EQEI_CTL_MODE_Pos) /*!< EQEI_T::CTL: MODE Mask */ + +#define EQEI_CTL_CHAINV_Pos (12) /*!< EQEI_T::CTL: CHAINV Position */ +#define EQEI_CTL_CHAINV_Msk (0x1ul << EQEI_CTL_CHAINV_Pos) /*!< EQEI_T::CTL: CHAINV Mask */ + +#define EQEI_CTL_CHBINV_Pos (13) /*!< EQEI_T::CTL: CHBINV Position */ +#define EQEI_CTL_CHBINV_Msk (0x1ul << EQEI_CTL_CHBINV_Pos) /*!< EQEI_T::CTL: CHBINV Mask */ + +#define EQEI_CTL_IDXINV_Pos (14) /*!< EQEI_T::CTL: IDXINV Position */ +#define EQEI_CTL_IDXINV_Msk (0x1ul << EQEI_CTL_IDXINV_Pos) /*!< EQEI_T::CTL: IDXINV Mask */ + +#define EQEI_CTL_IDXRSTEV_Pos (15) /*!< EQEI_T::CTL: IDXRSTEV Position */ +#define EQEI_CTL_IDXRSTEV_Msk (0x1ul << EQEI_CTL_IDXRSTEV_Pos) /*!< EQEI_T::CTL: IDXRSTEV Mask */ + +#define EQEI_CTL_OVUNIEN_Pos (16) /*!< EQEI_T::CTL: OVUNIEN Position */ +#define EQEI_CTL_OVUNIEN_Msk (0x1ul << EQEI_CTL_OVUNIEN_Pos) /*!< EQEI_T::CTL: OVUNIEN Mask */ + +#define EQEI_CTL_DIRIEN_Pos (17) /*!< EQEI_T::CTL: DIRIEN Position */ +#define EQEI_CTL_DIRIEN_Msk (0x1ul << EQEI_CTL_DIRIEN_Pos) /*!< EQEI_T::CTL: DIRIEN Mask */ + +#define EQEI_CTL_CMPIEN_Pos (18) /*!< EQEI_T::CTL: CMPIEN Position */ +#define EQEI_CTL_CMPIEN_Msk (0x1ul << EQEI_CTL_CMPIEN_Pos) /*!< EQEI_T::CTL: CMPIEN Mask */ + +#define EQEI_CTL_IDXIEN_Pos (19) /*!< EQEI_T::CTL: IDXIEN Position */ +#define EQEI_CTL_IDXIEN_Msk (0x1ul << EQEI_CTL_IDXIEN_Pos) /*!< EQEI_T::CTL: IDXIEN Mask */ + +#define EQEI_CTL_HOLDTMR0_Pos (20) /*!< EQEI_T::CTL: HOLDTMR0 Position */ +#define EQEI_CTL_HOLDTMR0_Msk (0x1ul << EQEI_CTL_HOLDTMR0_Pos) /*!< EQEI_T::CTL: HOLDTMR0 Mask */ + +#define EQEI_CTL_HOLDTMR1_Pos (21) /*!< EQEI_T::CTL: HOLDTMR1 Position */ +#define EQEI_CTL_HOLDTMR1_Msk (0x1ul << EQEI_CTL_HOLDTMR1_Pos) /*!< EQEI_T::CTL: HOLDTMR1 Mask */ + +#define EQEI_CTL_HOLDTMR2_Pos (22) /*!< EQEI_T::CTL: HOLDTMR2 Position */ +#define EQEI_CTL_HOLDTMR2_Msk (0x1ul << EQEI_CTL_HOLDTMR2_Pos) /*!< EQEI_T::CTL: HOLDTMR2 Mask */ + +#define EQEI_CTL_HOLDTMR3_Pos (23) /*!< EQEI_T::CTL: HOLDTMR3 Position */ +#define EQEI_CTL_HOLDTMR3_Msk (0x1ul << EQEI_CTL_HOLDTMR3_Pos) /*!< EQEI_T::CTL: HOLDTMR3 Mask */ + +#define EQEI_CTL_HOLDCNT_Pos (24) /*!< EQEI_T::CTL: HOLDCNT Position */ +#define EQEI_CTL_HOLDCNT_Msk (0x1ul << EQEI_CTL_HOLDCNT_Pos) /*!< EQEI_T::CTL: HOLDCNT Mask */ + +#define EQEI_CTL_IDXLATEN_Pos (25) /*!< EQEI_T::CTL: IDXLATEN Position */ +#define EQEI_CTL_IDXLATEN_Msk (0x1ul << EQEI_CTL_IDXLATEN_Pos) /*!< EQEI_T::CTL: IDXLATEN Mask */ + +#define EQEI_CTL_IDXRLDEN_Pos (27) /*!< EQEI_T::CTL: IDXRLDEN Position */ +#define EQEI_CTL_IDXRLDEN_Msk (0x1ul << EQEI_CTL_IDXRLDEN_Pos) /*!< EQEI_T::CTL: IDXRLDEN Mask */ + +#define EQEI_CTL_CMPEN_Pos (28) /*!< EQEI_T::CTL: CMPEN Position */ +#define EQEI_CTL_CMPEN_Msk (0x1ul << EQEI_CTL_CMPEN_Pos) /*!< EQEI_T::CTL: CMPEN Mask */ + +#define EQEI_CTL_QEIEN_Pos (29) /*!< EQEI_T::CTL: EQEIEN Position */ +#define EQEI_CTL_QEIEN_Msk (0x1ul << EQEI_CTL_QEIEN_Pos) /*!< EQEI_T::CTL: EQEIEN Mask */ + +#define EQEI_CTL2_SWAPEN_Pos (0) /*!< EQEI_T::CTL2: SWAPEN Position */ +#define EQEI_CTL2_SWAPEN_Msk (0x1ul << EQEI_CTL2_SWAPEN_Pos) /*!< EQEI_T::CTL2: SWAPEN Mask */ + +#define EQEI_CTL2_CRS_Pos (1) /*!< EQEI_T::CTL2: CRS Position */ +#define EQEI_CTL2_CRS_Msk (0x3ul << EQEI_CTL2_CRS_Pos) /*!< EQEI_T::CTL2: CRS Mask */ + +#define EQEI_CTL2_DIRSRC_Pos (4) /*!< EQEI_T::CTL2: DIRSRC Position */ +#define EQEI_CTL2_DIRSRC_Msk (0x3ul << EQEI_CTL2_DIRSRC_Pos) /*!< EQEI_T::CTL2: DIRSRC Mask */ + +#define EQEI_CTL2_UTEN_Pos (8) /*!< EQEI_T::CTL2: UTEN Position */ +#define EQEI_CTL2_UTEN_Msk (0x1ul << EQEI_CTL2_UTEN_Pos) /*!< EQEI_T::CTL2: UTEN Mask */ + +#define EQEI_CTL2_UTHOLDEN_Pos (9) /*!< EQEI_T::CTL2: UTHOLDEN Position */ +#define EQEI_CTL2_UTHOLDEN_Msk (0x1ul << EQEI_CTL2_UTHOLDEN_Pos) /*!< EQEI_T::CTL2: UTHOLDEN Mask */ + +#define EQEI_CTL2_UTEVTRST_Pos (10) /*!< EQEI_T::CTL2: UTEVTRST Position */ +#define EQEI_CTL2_UTEVTRST_Msk (0x1ul << EQEI_CTL2_UTEVTRST_Pos) /*!< EQEI_T::CTL2: UTEVTRST Mask */ + +#define EQEI_CTL2_IDXRSTUTS_Pos (11) /*!< EQEI_T::CTL2: IDXRSTUTS Position */ +#define EQEI_CTL2_IDXRSTUTS_Msk (0x1ul << EQEI_CTL2_IDXRSTUTS_Pos) /*!< EQEI_T::CTL2: IDXRSTUTS Mask */ + +#define EQEI_CTL2_PHEIEN_Pos (16) /*!< EQEI_T::CTL2: PHEIEN Position */ +#define EQEI_CTL2_PHEIEN_Msk (0x1ul << EQEI_CTL2_PHEIEN_Pos) /*!< EQEI_T::CTL2: PHEIEN Mask */ + +#define EQEI_CTL2_UTIEIEN_Pos (17) /*!< EQEI_T::CTL2: UTIEIEN Position */ +#define EQEI_CTL2_UTIEIEN_Msk (0x1ul << EQEI_CTL2_UTIEIEN_Pos) /*!< EQEI_T::CTL2: UTIEIEN Mask */ + +#define EQEI_UTCNT_UTCNT_Pos (0) /*!< EQEI_T::UTCNT: UTCNT Position */ +#define EQEI_UTCNT_UTCNT_Msk (0xfffffffful << EQEI_UTCNT_UTCNT_Pos) /*!< EQEI_T::UTCNT: UTCNT Mask */ + +#define EQEI_UTCMP_UTCMP_Pos (0) /*!< EQEI_T::UTCMP: UTCMP Position */ +#define EQEI_UTCMP_UTCMP_Msk (0xfffffffful << EQEI_UTCMP_UTCMP_Pos) /*!< EQEI_T::UTCMP: UTCMP Mask */ + +#define EQEI_STATUS_IDXF_Pos (0) /*!< EQEI_T::STATUS: IDXF Position */ +#define EQEI_STATUS_IDXF_Msk (0x1ul << EQEI_STATUS_IDXF_Pos) /*!< EQEI_T::STATUS: IDXF Mask */ + +#define EQEI_STATUS_CMPF_Pos (1) /*!< EQEI_T::STATUS: CMPF Position */ +#define EQEI_STATUS_CMPF_Msk (0x1ul << EQEI_STATUS_CMPF_Pos) /*!< EQEI_T::STATUS: CMPF Mask */ + +#define EQEI_STATUS_OVUNF_Pos (2) /*!< EQEI_T::STATUS: OVUNF Position */ +#define EQEI_STATUS_OVUNF_Msk (0x1ul << EQEI_STATUS_OVUNF_Pos) /*!< EQEI_T::STATUS: OVUNF Mask */ + +#define EQEI_STATUS_DIRCHGF_Pos (3) /*!< EQEI_T::STATUS: DIRCHGF Position */ +#define EQEI_STATUS_DIRCHGF_Msk (0x1ul << EQEI_STATUS_DIRCHGF_Pos) /*!< EQEI_T::STATUS: DIRCHGF Mask */ + +#define EQEI_STATUS_DIRF_Pos (8) /*!< EQEI_T::STATUS: DIRF Position */ +#define EQEI_STATUS_DIRF_Msk (0x1ul << EQEI_STATUS_DIRF_Pos) /*!< EQEI_T::STATUS: DIRF Mask */ + +#define EQEI_STATUS_FIDXEF_Pos (9) /*!< EQEI_T::STATUS: FIDXEF Position */ +#define EQEI_STATUS_FIDXEF_Msk (0x1ul << EQEI_STATUS_FIDXEF_Pos) /*!< EQEI_T::STATUS: FIDXEF Mask */ + +#define EQEI_STATUS_PHEF_Pos (16) /*!< EQEI_T::STATUS: PHEF Position */ +#define EQEI_STATUS_PHEF_Msk (0x1ul << EQEI_STATUS_PHEF_Pos) /*!< EQEI_T::STATUS: PHEF Mask */ + +#define EQEI_STATUS_UTIEF_Pos (17) /*!< EQEI_T::STATUS: UTIEF Position */ +#define EQEI_STATUS_UTIEF_Msk (0x1ul << EQEI_STATUS_UTIEF_Pos) /*!< EQEI_T::STATUS: UTIEF Mask */ + + +/**@}*/ /* EQEI_CONST */ +/**@}*/ /* end of EQEI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __EQEI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/fmc_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/fmc_reg.h new file mode 100644 index 0000000..fd439f4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/fmc_reg.h @@ -0,0 +1,687 @@ +/**************************************************************************//** + * @file fmc_reg.h + * @version V1.00 + * @brief FMC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FMC_REG_H__ +#define __FMC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup FMC Flash Memory Controller(FMC) + Memory Mapped Structure for FMC Controller +@{ */ + +typedef struct +{ + /** + * @var FMC_T::ISPCTL + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable Bit (Write Protect) + * | | |ISP function enable bit. Set this bit to enable ISP function. + * | | |0 = ISP function Disabled. + * | | |1 = ISP function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |BS |Boot Select (Write Protect) + * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively + * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from + * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. + * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |APUEN |APROM Update Enable Bit (Write Protect) + * | | |0 = APROM cannot be updated when the chip runs in APROM. + * | | |1 = APROM can be updated when the chip runs in APROM. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) + * | | |0 = CONFIG cannot be updated. + * | | |1 = CONFIG can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) + * | | |LDROM update enable bit. + * | | |0 = LDROM cannot be updated. + * | | |1 = LDROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |This bit needs to be cleared by writing 1 to it. + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |BL |Boot Loader Booting (Write Protect) + * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5]) + * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded + * | | |This bit is used to check chip boot from Boot Loader or not + * | | |User should keep original value of this bit when updating FMC_ISPCTL register. + * | | |0 = Booting from APROM or LDROM. + * | | |1 = Booting from Boot Loader. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPADDR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADDR |ISP Address + * | | |The NuMicro M480 series is equipped with embedded flash + * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation + * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. + * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. + * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) + * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation. + * | | |Read data from this register after ISP read operation. + * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff + * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment + * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result + * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CMD |ISP Command + * | | |ISP command table is shown below: + * | | |0x00= FLASH Read. + * | | |0x04= Read Unique ID. + * | | |0x08= Read Flash All-One Result. + * | | |0x0B= Read Company ID. + * | | |0x0C= Read Device ID. + * | | |0x0D= Read Checksum. + * | | |0x21= FLASH 32-bit Program. + * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. + * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. + * | | |0x27= FLASH Multi-Word Program. + * | | |0x28= Run Flash All-One Verification. + * | | |0x2C= Bank Remap. + * | | |0x2D= Run Checksum Calculation. + * | | |0x2E= Vector Remap. + * | | |0x40= FLASH 64-bit Read. + * | | |0x61= FLASH 64-bit Program. + * | | |The other commands are invalid. + * @var FMC_T::ISPTRG + * Offset: 0x10 ISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Write Protect) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::DFBA + * Offset: 0x14 Data Flash Base Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DFBA |Data Flash Base Address + * | | |This register indicates Data Flash start address. It is a read only register. + * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 + * | | |This register is valid when DFEN (CONFIG0[0]) =0 . + * @var FMC_T::ISPSTS + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPBUSY |ISP Busy Flag (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) + * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. + * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. + * | | |00 = LDROM with IAP mode. + * | | |01 = LDROM without IAP mode. + * | | |10 = APROM with IAP mode. + * | | |11 = APROM without IAP mode. + * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) + * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from Boot Loader. + * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) + * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) + * | | |This bit is set if data is mismatched at ISP programming verification + * | | |This bit is clear by performing ISP flash erase or ISP read CID operation + * | | |0 = Flash Program is success. + * | | |1 = Flash Program is fail. Program data is different with data in the flash memory + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 + * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. + * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A + * | | |(17) Read any content of boot loader with ICE connection + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |ALLONE |Flash All-one Verification Flag + * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 + * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. + * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. + * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF} + * |[24] |INTFLAG |ISP Interrupt Flag + * | | |0 = ISP Not Finished. + * | | |1 = ISP done or ISPFF set. + * | | |Note: This function needs to be enabled by FMC_ISPCTRL[24]. + * |[28] |ISPCERR |ISP Conflict Error + * | | |This bit shows when FMC is doing ISP operation. User cannot access FMC_ISP_ADDR,FMC_ISPDAT,FMC_ISPCMD,FMC_ISPTRG. It would cause ISPFF. + * |[30] |FBS |Flash Bank Selection + * | | |This bit indicate which bank is selected to boot. + * | | |0 = Booting from BANK0. + * | | |1 = Booting from BANK1. + * @var FMC_T::CYCCTL + * Offset: 0x4C Flash Access Cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) + * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. + * | | |The HCLK working frequency range range is<27MHz + * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. + * | | | The optimized HCLK working frequency range is 27~54 MHz + * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. + * | | |The optimized HCLK working frequency range is 54~81MHz + * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. + * | | | The optimized HCLK working frequency range is81~108MHz + * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. + * | | |The optimized HCLK working frequency range is 108~135MHz + * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. + * | | | The optimized HCLK working frequency range is 135~162MHz + * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. + * | | | The optimized HCLK working frequency range is 162~192MHz + * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. + * | | |The optimized HCLK working frequency range is >192MHz + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::MPDAT0 + * Offset: 0x80 ISP Data0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT0 |ISP Data 0 + * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data + * @var FMC_T::MPDAT1 + * Offset: 0x84 ISP Data1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT1 |ISP Data 1 + * | | |This register is the second 32-bit data for 64-bit/multi-word programming. + * @var FMC_T::MPDAT2 + * Offset: 0x88 ISP Data2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT2 |ISP Data 2 + * | | |This register is the third 32-bit data for multi-word programming. + * @var FMC_T::MPDAT3 + * Offset: 0x8C ISP Data3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT3 |ISP Data 3 + * | | |This register is the fourth 32-bit data for multi-word programming. + * @var FMC_T::MPSTS + * Offset: 0xC0 ISP Multi-Program Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) + * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP Multi-Word program operation is finished. + * | | |1 = ISP Multi-Word program operation is progressed. + * |[1] |PPGO |ISP Multi-program Status (Read Only) + * | | |0 = ISP multi-word program operation is not active. + * | | |1 = ISP multi-word program operation is in progress. + * |[2] |ISPFF |ISP Fail Flag (Read Only) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 + * | | |(5) SPROM is programmed at SPROM secured mode. + * | | |(6) Page Erase command at LOCK mode with ICE connection + * | | |(7) Erase or Program command at brown-out detected + * | | |(8) Destination address is illegal, such as over an available range. + * | | |(9) Invalid ISP commands + * | | |(10) Vector address is mapping to SPROM region. + * |[4] |D0 |ISP DATA 0 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. + * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. + * |[5] |D1 |ISP DATA 1 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. + * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. + * |[6] |D2 |ISP DATA 2 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. + * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. + * |[7] |D3 |ISP DATA 3 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. + * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. + * @var FMC_T::MPADDR + * Offset: 0xC4 ISP Multi-Program Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MPADDR |ISP Multi-word Program Address + * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. + * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. + * @var FMC_T::XOMR0STS + * Offset: 0xD0 XOM Region 0 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 0. + * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 0. + * @var FMC_T::XOMR1STS + * Offset: 0xD4 XOM Region 1 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 1. + * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 1. + * @var FMC_T::XOMR2STS + * Offset: 0xD8 XOM Region 2 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 2. + * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 2. + * @var FMC_T::XOMR3STS + * Offset: 0xDC XOM Region 3 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 3. + * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 3. + * @var FMC_T::XOMSTS + * Offset: 0xE0 XOM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XOMR0ON |XOM Region 0 On + * | | |XOM Region 0 active status. + * | | |0 = No active. + * | | |1 = XOM region 0 is active. + * |[1] |XOMR1ON |XOM Region 1 On + * | | |XOM Region 1 active status. + * | | |0 = No active. + * | | |1 = XOM region 1 is active. + * |[2] |XOMR2ON |XOM Region 2 On + * | | |XOM Region 2 active status. + * | | |0 = No active. + * | | |1 = XOM region 2 is active. + * |[3] |XOMR3ON |XOM Region 3 On + * | | |XOM Region 3 active status. + * | | |0 = No active. + * | | |1 = XOM region 3 is active. + * |[4] |XOMPEF |XOM Page Erase Function Fail + * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. + * | | |0 = Success. + * | | |1 = Fail. + * @var FMC_T::APPROT + * Offset: 0x110 APROM Protect Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |APPROENn |APROM Proect enable + * | n=0,1..| |This bit indicates which APROM region is protected. + * | ..31 | |0 = APROM region n is not protected. + * | | |1 = APROM region n is protected. + * | | |Note: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000) + */ + + __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ + __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ + __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ + __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ + __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ + __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[10]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[12]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ + __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ + __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ + __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[12]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ + __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[2]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ + __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ + __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ + __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ + __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ + __I uint32_t RESERVE5[11]; + __IO uint32_t APPROT; /*!< [0x0110] XOM Status Register */ + +} FMC_T; + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller +@{ */ + +#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ +#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ + +#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ +#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ + +#define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ +#define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ + +#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ +#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ + +#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ +#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ + +#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ +#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ + +#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ +#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ + +#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ +#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ + +#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ +#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ + +#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ +#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ + +#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ +#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ + +#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ +#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ + +#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ +#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ + +#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ +#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ + +#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ +#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ + +#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ +#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ + +#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ +#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ + +#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ +#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ + +#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */ +#define FMC_ISPSTS_INTFLAG_Msk (0x01ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Position */ + +#define FMC_ISPSTS_ISPCERR_Pos (28) /*!< FMC_T::ISPSTS: ISPCERR Position */ +#define FMC_ISPSTS_ISPCERR_Msk (0x01ul << FMC_ISPSTS_ISPCERR_Pos) /*!< FMC_T::ISPSTS: ISPCERR Position */ + +#define FMC_ISPSTS_FBS_Pos (30) /*!< FMC_T::ISPSTS: FBS Position */ +#define FMC_ISPSTS_FBS_Msk (0x1ul << FMC_ISPSTS_FBS_Pos) /*!< FMC_T::ISPSTS: FBS Msk */ + +#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ +#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ + +#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ +#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ + +#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ +#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ + +#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ +#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ + +#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ +#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ + +#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ +#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ + +#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ +#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ + +#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ +#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ + +#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ +#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ + +#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ +#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ + +#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ +#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ + +#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ +#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ + +#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ +#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ + +#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ +#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ + +#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ +#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ + +#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ +#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ + +#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ +#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ + +#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ +#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ + +#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ +#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOM20STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ + +#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ +#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ + +#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ +#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ + +#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ +#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ + +#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ +#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ + +#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ +#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ + +#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ +#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ + +#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ +#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ + +#define FMC_APPROT_APPROEN0_Pos (0) /*!< FMC_T::APPROT: APPROEN0 Position */ +#define FMC_APPROT_APPROEN0_Msk (0x1ul << FMC_APPROT_APPROEN0_Pos) /*!< FMC_T::APPROT: APPROEN0 Mask */ + +#define FMC_APPROT_APPROEN1_Pos (1) /*!< FMC_T::APPROT: APPROEN1 Position */ +#define FMC_APPROT_APPROEN1_Msk (0x1ul << FMC_APPROT_APPROEN1_Pos) /*!< FMC_T::APPROT: APPROEN1 Mask */ + +#define FMC_APPROT_APPROEN2_Pos (2) /*!< FMC_T::APPROT: APPROEN2 Position */ +#define FMC_APPROT_APPROEN2_Msk (0x1ul << FMC_APPROT_APPROEN2_Pos) /*!< FMC_T::APPROT: APPROEN2 Mask */ + +#define FMC_APPROT_APPROEN3_Pos (3) /*!< FMC_T::APPROT: APPROEN3 Position */ +#define FMC_APPROT_APPROEN3_Msk (0x1ul << FMC_APPROT_APPROEN3_Pos) /*!< FMC_T::APPROT: APPROEN3 Mask */ + +#define FMC_APPROT_APPROEN4_Pos (4) /*!< FMC_T::APPROT: APPROEN4 Position */ +#define FMC_APPROT_APPROEN4_Msk (0x1ul << FMC_APPROT_APPROEN4_Pos) /*!< FMC_T::APPROT: APPROEN4 Mask */ + +#define FMC_APPROT_APPROEN5_Pos (5) /*!< FMC_T::APPROT: APPROEN5 Position */ +#define FMC_APPROT_APPROEN5_Msk (0x1ul << FMC_APPROT_APPROEN5_Pos) /*!< FMC_T::APPROT: APPROEN5 Mask */ + +#define FMC_APPROT_APPROEN6_Pos (6) /*!< FMC_T::APPROT: APPROEN6 Position */ +#define FMC_APPROT_APPROEN6_Msk (0x1ul << FMC_APPROT_APPROEN6_Pos) /*!< FMC_T::APPROT: APPROEN6 Mask */ + +#define FMC_APPROT_APPROEN7_Pos (7) /*!< FMC_T::APPROT: APPROEN7 Position */ +#define FMC_APPROT_APPROEN7_Msk (0x1ul << FMC_APPROT_APPROEN7_Pos) /*!< FMC_T::APPROT: APPROEN7 Mask */ + +#define FMC_APPROT_APPROEN8_Pos (8) /*!< FMC_T::APPROT: APPROEN8 Position */ +#define FMC_APPROT_APPROEN8_Msk (0x1ul << FMC_APPROT_APPROEN8_Pos) /*!< FMC_T::APPROT: APPROEN8 Mask */ + +#define FMC_APPROT_APPROEN9_Pos (9) /*!< FMC_T::APPROT: APPROEN9 Position */ +#define FMC_APPROT_APPROEN9_Msk (0x1ul << FMC_APPROT_APPROEN9_Pos) /*!< FMC_T::APPROT: APPROEN9 Mask */ + +#define FMC_APPROT_APPROEN10_Pos (10) /*!< FMC_T::APPROT: APPROEN10 Position */ +#define FMC_APPROT_APPROEN10_Msk (0x1ul << FMC_APPROT_APPROEN10_Pos) /*!< FMC_T::APPROT: APPROEN10 Mask */ + +#define FMC_APPROT_APPROEN11_Pos (11) /*!< FMC_T::APPROT: APPROEN11 Position */ +#define FMC_APPROT_APPROEN11_Msk (0x1ul << FMC_APPROT_APPROEN11_Pos) /*!< FMC_T::APPROT: APPROEN11 Mask */ + +#define FMC_APPROT_APPROEN12_Pos (12) /*!< FMC_T::APPROT: APPROEN12 Position */ +#define FMC_APPROT_APPROEN12_Msk (0x1ul << FMC_APPROT_APPROEN12_Pos) /*!< FMC_T::APPROT: APPROEN12 Mask */ + +#define FMC_APPROT_APPROEN13_Pos (13) /*!< FMC_T::APPROT: APPROEN13 Position */ +#define FMC_APPROT_APPROEN13_Msk (0x1ul << FMC_APPROT_APPROEN13_Pos) /*!< FMC_T::APPROT: APPROEN13 Mask */ + +#define FMC_APPROT_APPROEN14_Pos (14) /*!< FMC_T::APPROT: APPROEN14 Position */ +#define FMC_APPROT_APPROEN14_Msk (0x1ul << FMC_APPROT_APPROEN14_Pos) /*!< FMC_T::APPROT: APPROEN14 Mask */ + +#define FMC_APPROT_APPROEN15_Pos (15) /*!< FMC_T::APPROT: APPROEN15 Position */ +#define FMC_APPROT_APPROEN15_Msk (0x1ul << FMC_APPROT_APPROEN15_Pos) /*!< FMC_T::APPROT: APPROEN15 Mask */ + +#define FMC_APPROT_APPROEN16_Pos (16) /*!< FMC_T::APPROT: APPROEN16 Position */ +#define FMC_APPROT_APPROEN16_Msk (0x1ul << FMC_APPROT_APPROEN16_Pos) /*!< FMC_T::APPROT: APPROEN16 Mask */ + +#define FMC_APPROT_APPROEN17_Pos (17) /*!< FMC_T::APPROT: APPROEN17 Position */ +#define FMC_APPROT_APPROEN17_Msk (0x1ul << FMC_APPROT_APPROEN17_Pos) /*!< FMC_T::APPROT: APPROEN17 Mask */ + +#define FMC_APPROT_APPROEN18_Pos (18) /*!< FMC_T::APPROT: APPROEN18 Position */ +#define FMC_APPROT_APPROEN18_Msk (0x1ul << FMC_APPROT_APPROEN18_Pos) /*!< FMC_T::APPROT: APPROEN18 Mask */ + +#define FMC_APPROT_APPROEN19_Pos (19) /*!< FMC_T::APPROT: APPROEN19 Position */ +#define FMC_APPROT_APPROEN19_Msk (0x1ul << FMC_APPROT_APPROEN19_Pos) /*!< FMC_T::APPROT: APPROEN19 Mask */ + +#define FMC_APPROT_APPROEN20_Pos (20) /*!< FMC_T::APPROT: APPROEN20 Position */ +#define FMC_APPROT_APPROEN20_Msk (0x1ul << FMC_APPROT_APPROEN20_Pos) /*!< FMC_T::APPROT: APPROEN20 Mask */ + +#define FMC_APPROT_APPROEN21_Pos (21) /*!< FMC_T::APPROT: APPROEN21 Position */ +#define FMC_APPROT_APPROEN21_Msk (0x1ul << FMC_APPROT_APPROEN21_Pos) /*!< FMC_T::APPROT: APPROEN21 Mask */ + +#define FMC_APPROT_APPROEN22_Pos (22) /*!< FMC_T::APPROT: APPROEN22 Position */ +#define FMC_APPROT_APPROEN22_Msk (0x1ul << FMC_APPROT_APPROEN22_Pos) /*!< FMC_T::APPROT: APPROEN22 Mask */ + +#define FMC_APPROT_APPROEN23_Pos (23) /*!< FMC_T::APPROT: APPROEN23 Position */ +#define FMC_APPROT_APPROEN23_Msk (0x1ul << FMC_APPROT_APPROEN23_Pos) /*!< FMC_T::APPROT: APPROEN23 Mask */ + +#define FMC_APPROT_APPROEN24_Pos (24) /*!< FMC_T::APPROT: APPROEN24 Position */ +#define FMC_APPROT_APPROEN24_Msk (0x1ul << FMC_APPROT_APPROEN24_Pos) /*!< FMC_T::APPROT: APPROEN24 Mask */ + +#define FMC_APPROT_APPROEN25_Pos (25) /*!< FMC_T::APPROT: APPROEN25 Position */ +#define FMC_APPROT_APPROEN25_Msk (0x1ul << FMC_APPROT_APPROEN25_Pos) /*!< FMC_T::APPROT: APPROEN25 Mask */ + +#define FMC_APPROT_APPROEN26_Pos (26) /*!< FMC_T::APPROT: APPROEN26 Position */ +#define FMC_APPROT_APPROEN26_Msk (0x1ul << FMC_APPROT_APPROEN26_Pos) /*!< FMC_T::APPROT: APPROEN26 Mask */ + +#define FMC_APPROT_APPROEN27_Pos (27) /*!< FMC_T::APPROT: APPROEN27 Position */ +#define FMC_APPROT_APPROEN27_Msk (0x1ul << FMC_APPROT_APPROEN27_Pos) /*!< FMC_T::APPROT: APPROEN27 Mask */ + +#define FMC_APPROT_APPROEN28_Pos (28) /*!< FMC_T::APPROT: APPROEN28 Position */ +#define FMC_APPROT_APPROEN28_Msk (0x1ul << FMC_APPROT_APPROEN28_Pos) /*!< FMC_T::APPROT: APPROEN28 Mask */ + +#define FMC_APPROT_APPROEN29_Pos (29) /*!< FMC_T::APPROT: APPROEN29 Position */ +#define FMC_APPROT_APPROEN29_Msk (0x1ul << FMC_APPROT_APPROEN29_Pos) /*!< FMC_T::APPROT: APPROEN29 Mask */ + +#define FMC_APPROT_APPROEN30_Pos (30) /*!< FMC_T::APPROT: APPROEN30 Position */ +#define FMC_APPROT_APPROEN30_Msk (0x1ul << FMC_APPROT_APPROEN30_Pos) /*!< FMC_T::APPROT: APPROEN30 Mask */ + +#define FMC_APPROT_APPROEN31_Pos (31) /*!< FMC_T::APPROT: APPROEN31 Position */ +#define FMC_APPROT_APPROEN31_Msk (0x1ul << FMC_APPROT_APPROEN31_Pos) /*!< FMC_T::APPROT: APPROEN31 Mask */ + +/**@}*/ /* FMC_CONST */ +/**@}*/ /* end of FMC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __FMC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/gpio_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/gpio_reg.h new file mode 100644 index 0000000..b83c983 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/gpio_reg.h @@ -0,0 +1,1104 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @version V3.00 + * @brief GPIO register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup GPIO General Purpose Input/Output Controller(GPIO) + Memory Mapped Structure for GPIO Controller +@{ */ + + +typedef struct +{ + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0/0x200/0x240 Port A-J I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-J I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Px.n is in Quasi-bidirectional mode. + * | | |Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). + * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. + * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note 2: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4/0x204/0x244 Port A-J Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-J Pin[n] Digital Input Path Disable Control + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8/0x208/0x248 Port A-J Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-J Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC/0x20C/0x24C Port A-J Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-J Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[n]) bit. + * | | |Note 2: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0/0x210/0x250 Port A-J Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-J Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin. + * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4/0x214/0x254 Port A-J De-Bounce Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-J Pin[n] Input Signal De-Bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8/0x208/0x258 Port A-J Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-J Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC/0x21C Port A-J Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-J Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * |[n+16] |RHIENn |Port A-J Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0/0x220/0x260 Port A-J Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-J Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4/0x224/0x264 Port A-J Input Schmitt Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-J Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input Schmitt trigger function Disabled. + * | | |1 = Px.n input Schmitt trigger function Enabled. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8/0x228/0x268 Port A-J High Slew Rate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-J Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode. + * | | |01 = Px.n output with high slew rate mode. + * | | |10 = Px.n output with fast slew rate mode. + * | | |11 = Reserved. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0/0x230/0x270 Port A-J Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-J Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-down disable. + * | | |01 = Px.n pull-up enable. + * | | |10 = Px.n pull-down enable. + * | | |11 = Reserved. + * | | |Note 1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation: + * | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when MODEn set as tri-state mode. + * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode. + * | | |Note 2: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var GPIO_T::DBCTL + * Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4/0x234/0x274 Port A-J Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * |[5] |ICLKON |Interrupt Clock On Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |If corresponding RHIEN or FLIEN is 0, the clock of I/O detect circuit is stopped and interrupt source flag(Px_INTSRC) cannot be clear also. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + * |[31] |DBCLKBUSY |De-bounce Clock Switching Busy Flag (Read Only) + * | | |This bit is set when de-bounce clock source is changed by setting DBCLKSRC(Px_DBCTL[4]). + * | | |And it is cleared after de-bounce clock source switching is finished. De-bounce function can work normally after de-bounce clock switch done. + * | | |0 = De-bounce clock switch done. + * | | |1 = De-bounce clock is switching. + */ + + __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0/0x200/0x240 Port A-J I/O Mode Control */ + __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4/0x204/0x244 Port A-J Digital Input Path Disable Control */ + __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8/0x208/0x248 Port A-J Data Output Value */ + __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC/0x20C/0x24C Port A-J Data Output Write Mask */ + __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0/0x210/0x250 Port A-J Pin Value */ + __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4/0x214/0x254 Port A-J De-Bounce Enable Control Register */ + __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8/0x218/0x258 Port A-J Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC/0x21C/0x25C Port A-J Interrupt Enable Control Register */ + __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0/0x220/0x260 Port A-J Interrupt Source Flag */ + __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4/0x224/0x264 Port A-J Input Schmitt Trigger Enable Register */ + __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8/0x228/0x268 Port A-J High Slew Rate Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PUSEL; /* Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0/0x230/0x270 Port A-J Pull-up and Pull-down Enable Register */ + __IO uint32_t DBCTL; /* Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4/0x234/0x274 Port A-J Interrupt De-bounce Control Register */ + +} GPIO_T; + +typedef struct +{ + + /** + * @var GPIO_INT_T::INTn_INNF + * Offset: 0x450/0x454/0x458/0x45C/0x460/0x464/0x468/0x46C INT0~7 Input Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |NFEN |Noise Filter Enable + * | | |0 = Noise Filter function Disabled. + * | | |1 = Noise Filter function Enabled. + * |[6:4] |NFSEL |Noise Filter Clock Selection + * | | |000 = Filter clock is HCLK. + * | | |001 = Filter clock is HCLK/2. + * | | |010 = Filter clock is HCLK/4. + * | | |011 = Filter clock is HCLK/8. + * | | |100 = Filter clock is HCLK/16 + * | | |101 = Filter clock is HCLK/32. + * | | |110 = Filter clock is HCLK/64. + * | | |111 = Filter clock is HCLK/128. + * |[10:8] |NFCNT |Noise Filter Count + * | | |The register bits control the filter counter to count from 0 to NFCNT. + * @var GPIO_INT_T::INT_EDETCTL + * Offset: 0x490 INT Edge Detect Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|EDETCTLn |INTn Edge Detect Control Bits + * | | |00 = Not detect. + * | | |01 = INTn low to high detection Enable. + * | | |10 = INTn high to low detection Enable. + * | | |11 = INTn both low to high and high to low detection Enable. + * @var GPIO_INT_T::INT_EDINTEN + * Offset: 0x498 INT Edge Detect Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |EDIENn |INTn Edge Detect Interrupt Enable Bit + * | | |0 = INTn Edge Detect Interrupt Disable. + * | | |1 = INTn Edge Detect Interrupt Enable. + * @var GPIO_INT_T::INT_EDSTS + * Offset: 0x49C INT Edge Detect Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |EDIFn |INTn Edge Detect Interrupt Flag + * | | |0 = No Edge Detection happened. + * | | |1 = Rising Edge or Falling edge has been detected. + * | | |Note: This bit is cleared by writing 1 to it. + */ + + __IO uint32_t INT_INNF[8]; /* Offset: 0x450/0x454/0x458/0x45C/0x460/0x464/0x468/0x46C INT0~7 Input Noise Filter Register */ + __I uint32_t RESERVE1[8]; + __IO uint32_t INT_EDETCTL; /* Offset: 0x490 INT Edge Detect Control Register */ + __I uint32_t RESERVE2[1]; + __IO uint32_t INT_EDINTEN; /* Offset: 0x498 INT Edge Detect Interrupt Enable Control Register */ + __IO uint32_t INT_EDSTS; /* Offset: 0x49C INT Edge Detect Interrupt Flag Register */ + +} GPIO_INT_T; + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller +@{ */ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */ +#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */ + +#define GPIO_DBCTL_DBCLKBUSY_Pos (31) /*!< GPIO_T::DBCTL: DBCLKBUSY Position */ +#define GPIO_DBCTL_DBCLKBUSY_Msk (1ul << GPIO_DBCTL_DBCLKBUSY_Pos) /*!< GPIO_T::DBCTL: DBCLKBUSY Mask */ + +#define GPIO_INT_INNF_NFEN_Pos (0) /*!< GPIO_T::INT_INNF: NFEN Position */ +#define GPIO_INT_INNF_NFEN_Msk (0x1ul << GPIO_INT_INNF_NFEN_Pos) /*!< GPIO_T::INT_INNF: NFEN Mask */ + +#define GPIO_INT_INNF_NFSEL_Pos (4) /*!< GPIO_T::INT_INNF: NFSEL Position */ +#define GPIO_INT_INNF_NFSEL_Msk (0x7ul << GPIO_INT_INNF_NFSEL_Pos) /*!< GPIO_T::INT_INNF: NFSEL Mask */ + +#define GPIO_INT_INNF_NFCNT_Pos (8) /*!< GPIO_T::INT_INNF: NFCNT Position */ +#define GPIO_INT_INNF_NFCNT_Msk (0x7ul << GPIO_INT_INNF_NFCNT_Pos) /*!< GPIO_T::INT_INNF: NFCNT Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL0_Pos (0) /*!< GPIO_T::INT_EDETCTL: EDETCTL0 Position */ +#define GPIO_INT_EDETCTL_EDETCTL0_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL0_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL0 Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL1_Pos (2) /*!< GPIO_T::INT_EDETCTL: EDETCTL1 Position */ +#define GPIO_INT_EDETCTL_EDETCTL1_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL1_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL1 Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL2_Pos (4) /*!< GPIO_T::INT_EDETCTL: EDETCTL2 Position */ +#define GPIO_INT_EDETCTL_EDETCTL2_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL2_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL2 Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL3_Pos (6) /*!< GPIO_T::INT_EDETCTL: EDETCTL3 Position */ +#define GPIO_INT_EDETCTL_EDETCTL3_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL3_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL3 Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL4_Pos (8) /*!< GPIO_T::INT_EDETCTL: EDETCTL4 Position */ +#define GPIO_INT_EDETCTL_EDETCTL4_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL4_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL4 Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL5_Pos (10) /*!< GPIO_T::INT_EDETCTL: EDETCTL5 Position */ +#define GPIO_INT_EDETCTL_EDETCTL5_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL5_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL5 Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL6_Pos (12) /*!< GPIO_T::INT_EDETCTL: EDETCTL6 Position */ +#define GPIO_INT_EDETCTL_EDETCTL6_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL6_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL6 Mask */ + +#define GPIO_INT_EDETCTL_EDETCTL7_Pos (14) /*!< GPIO_T::INT_EDETCTL: EDETCTL7 Position */ +#define GPIO_INT_EDETCTL_EDETCTL7_Msk (0x3ul << GPIO_INT_EDETCTL_EDETCTL7_Pos) /*!< GPIO_T::INT_EDETCTL: EDETCTL7 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN0_Pos (0) /*!< GPIO_T::INT_EDINTEN: EDIEN0 Position */ +#define GPIO_INT_EDINTEN_EDIEN0_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN0_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN0 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN1_Pos (1) /*!< GPIO_T::INT_EDINTEN: EDIEN1 Position */ +#define GPIO_INT_EDINTEN_EDIEN1_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN1_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN1 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN2_Pos (2) /*!< GPIO_T::INT_EDINTEN: EDIEN2 Position */ +#define GPIO_INT_EDINTEN_EDIEN2_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN2_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN2 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN3_Pos (3) /*!< GPIO_T::INT_EDINTEN: EDIEN3 Position */ +#define GPIO_INT_EDINTEN_EDIEN3_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN3_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN3 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN4_Pos (4) /*!< GPIO_T::INT_EDINTEN: EDIEN4 Position */ +#define GPIO_INT_EDINTEN_EDIEN4_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN4_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN4 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN5_Pos (5) /*!< GPIO_T::INT_EDINTEN: EDIEN5 Position */ +#define GPIO_INT_EDINTEN_EDIEN5_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN5_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN5 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN6_Pos (6) /*!< GPIO_T::INT_EDINTEN: EDIEN6 Position */ +#define GPIO_INT_EDINTEN_EDIEN6_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN6_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN6 Mask */ + +#define GPIO_INT_EDINTEN_EDIEN7_Pos (7) /*!< GPIO_T::INT_EDINTEN: EDIEN7 Position */ +#define GPIO_INT_EDINTEN_EDIEN7_Msk (0x1ul << GPIO_INT_EDINTEN_EDIEN7_Pos) /*!< GPIO_T::INT_EDINTEN: EDIEN7 Mask */ + +#define GPIO_INT_EDSTS_EDIF0_Pos (0) /*!< GPIO_T::INT_EDSTS: EDIF0 Position */ +#define GPIO_INT_EDSTS_EDIF0_Msk (0x1ul << GPIO_INT_EDSTS_EDIF0_Pos) /*!< GPIO_T::INT_EDSTS: EDIF0 Mask */ + +#define GPIO_INT_EDSTS_EDIF1_Pos (1) /*!< GPIO_T::INT_EDSTS: EDIF1 Position */ +#define GPIO_INT_EDSTS_EDIF1_Msk (0x1ul << GPIO_INT_EDSTS_EDIF1_Pos) /*!< GPIO_T::INT_EDSTS: EDIF1 Mask */ + +#define GPIO_INT_EDSTS_EDIF2_Pos (2) /*!< GPIO_T::INT_EDSTS: EDIF2 Position */ +#define GPIO_INT_EDSTS_EDIF2_Msk (0x1ul << GPIO_INT_EDSTS_EDIF2_Pos) /*!< GPIO_T::INT_EDSTS: EDIF2 Mask */ + +#define GPIO_INT_EDSTS_EDIF3_Pos (3) /*!< GPIO_T::INT_EDSTS: EDIF3 Position */ +#define GPIO_INT_EDSTS_EDIF3_Msk (0x1ul << GPIO_INT_EDSTS_EDIF3_Pos) /*!< GPIO_T::INT_EDSTS: EDIF3 Mask */ + +#define GPIO_INT_EDSTS_EDIF4_Pos (4) /*!< GPIO_T::INT_EDSTS: EDIF4 Position */ +#define GPIO_INT_EDSTS_EDIF4_Msk (0x1ul << GPIO_INT_EDSTS_EDIF4_Pos) /*!< GPIO_T::INT_EDSTS: EDIF4 Mask */ + +#define GPIO_INT_EDSTS_EDIF5_Pos (5) /*!< GPIO_T::INT_EDSTS: EDIF5 Position */ +#define GPIO_INT_EDSTS_EDIF5_Msk (0x1ul << GPIO_INT_EDSTS_EDIF5_Pos) /*!< GPIO_T::INT_EDSTS: EDIF5 Mask */ + +#define GPIO_INT_EDSTS_EDIF6_Pos (6) /*!< GPIO_T::INT_EDSTS: EDIF6 Position */ +#define GPIO_INT_EDSTS_EDIF6_Msk (0x1ul << GPIO_INT_EDSTS_EDIF6_Pos) /*!< GPIO_T::INT_EDSTS: EDIF6 Mask */ + +#define GPIO_INT_EDSTS_EDIF7_Pos (7) /*!< GPIO_T::INT_EDSTS: EDIF7 Position */ +#define GPIO_INT_EDSTS_EDIF7_Msk (0x1ul << GPIO_INT_EDSTS_EDIF7_Pos) /*!< GPIO_T::INT_EDSTS: EDIF7 Mask */ + +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __GPIO_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hbi_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hbi_reg.h new file mode 100644 index 0000000..4f6cb5f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hbi_reg.h @@ -0,0 +1,233 @@ +/**************************************************************************//** + * @file hbi_reg.h + * @version V1.00 + * @brief HBI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HBI_REG_H__ +#define __HBI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup Hyper Bus Interface Controller (HBI) + Memory Mapped Structure for HBI Controller +@{ */ +typedef struct +{ + + + /** + * @var HBI_T::CMD + * Offset: 0x00 HyperBus Command and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HYPCMD |HyperBus Command and Status + * | | |Write + * | | |0001 = Reset HyperRAM. + * | | |0010 = Read HyperRAM regsiter (16-Bit, Read Data[15:0]. + * | | |0101 = Exit From Hybrid Sleep and deep power down. + * | | |0111 = Write HyperRAM regsiter (16-Bit, Write Data[15:0]. + * | | |1000 = Read 1 word (Read Data[15:0]) from HyperRAM. + * | | |1001 = Read 2 word (Read Data[31:0]) from HyperRAM. + * | | |1100 = Write 1 Byte (Write Data[7:0]) to HyperRAM. + * | | |1101 = Write 2 Bytes (Write Data[15:0]) to HyperRAM. + * | | |1110 = Write 3 Byte (Write Data[23:0]) to HyperRAM. + * | | |1111 = Write 4 Byte (Write Data[31:0]) to HyperRAM. + * | | |Other value = reserved. + * | | |Read + * | | |0000 = HyperBus interface is Idle. + * | | |Other value = HyperBus interface is busy. + * | | |Note: When an operation is Done, the read value automatically return to 4'b0000. + * @var HBI_T::CONFIG + * Offset: 0x04 HyperBus Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CSST |Chip Select Setup Time to Next CK Rising Edge + * | | |This field indicates the setup time between the chip select and the next CK rising edge + * | | |00 = 1.5 HCLK cycles. + * | | |01 = 2.5 HCLK cycles. + * | | |10 = 3.5 HCLK cycles. + * | | |11 = 4.5 HCLK cycles. + * |[5:2] |ACCT |Initial Access Time + * | | |This field indicates the initial access cycles of the Hyper Bus transaction + * | | |0000 = 5 CK cycles. + * | | |0001 = 6 CK cycles. + * | | |0010 = 7 CK cycles. + * | | |1110 = 3 CK cycles. + * | | |1111 = 4 CK cycles. + * | | |Others = Reserved. + * | | |Note: This field must be set to the same value as I + * | | |initial Latency in HyperRAMs Configuration Register 0. + * |[7:6] |CSH |Chip Select Hold Time After CK Falling Edge + * | | |This field indicates the hold time between the last CK falling edge and chip select + * | | |00 = 0.5 HCLK cycles. + * | | |01 = 1.5 HCLK cycles. + * | | |10 = 2.5 HCLK cycles. + * | | |11 = 3.5 HCLK cycles. + * |[11:8] |CSHI |Chip Select High between Transaction + * | | |This field indicates the inactive period between two Hyper Bus transactions + * | | |0000 = 1 HCLK cycle. + * | | |0001 = 2 HCLK cycles. + * | | |0010 = 3 HCLK cycles. + * | | |0011 = 4 HCLK cycles. + * | | |... + * | | |1111 = 16 HCLK cycles. + * | | |Note : This field must meet the HyperRAM devices specification of tCSHI. + * |[13:12] |BGSIZE |Burst Group Size + * | | |This field indicates the burst length on the Hyper Bus transaction + * | | |00 = 128 Bytes. + * | | |01 = 64 Bytes. + * | | |10 = 16 Bytes. + * | | |11 = 32 Bytes. + * | | |Note : This field must be set to the same value as Burst Length in HyperRAMs Configuration Regsiter 0. + * |[14] |ENDIAN |Endian Condition on the Hyper Bus Data Pipe + * | | |0 = Little-Endian. + * | | | Byte A = Bits[7:0] of a 16-Bit ..........word + * | | | Byte B = Bits[15:8] of a 16-Bit ..........word + * | | |1 = Big-Endia. + * | | | Byte A = Bits[15:8] of a 16-Bit ..........word + * | | | Byte B = Bits[7:0] of a 16-Bit ..........word + * |[15] |CKDIV |Hyper Bus Clock Divider + * | | | 0 = Hyper Bus Clock rate is HCLK/2. + * | | | 1 = Hyper Bus Clock rate is HCLK/4. + * |[26:16] |CSMAXLT |Chip Select Maximum Low Time + * | | | This field indicates the maximum Low period of the chip select (CS#) in one transaction + * | | | 00000000000 = 1 HCLK cycle. + * | | | 00000000001 = 2 HCLK cycles. + * | | | 00000000010 = 3 HCLK cycles. + * | | | 00000000011 = 4 HCLK cycles. + * | | | ... + * | | | 01011101100 = 749 HCLK cycles (3.9us @192 MHz). + * | | | ... + * | | | 11111111110 = 2047 HCLK cycles. + * | | | 11111111111 = 2048 HCLK cycles. + * | | | Note: This field inidcates the timing of HyperRAM Chip Select specification so that it has to relative the frequency of HCLK and the CLKDIV (HBI_CONFIG[15]). + * @var HBI_T::ADR + * Offset: 0x08 HyperBus Byte Address access Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |HBI_ADR |HyperBus Byte Address + * | | |Memory Space Range: + * | | | 0x0000_0000 ~ 0x01FF_FFFF + * | | |Register Space Range: + * | | | 0X0000_0000 = Identification Register 0 + * | | | 0X0000_0002 = Identification Register 1 + * | | | 0X0000_1000 = Configuration Register 0 + * | | | 0X0000_1002 = Configuration Register 1 + * | | |Note: + * | | |1. It is "Byte" address, not "word" address + * | | |2. Up to 32M Bytes of memory space is supported. + * @var HBI_T::WDATA + * Offset: 0x0C HyperBus 32-Bits Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WDATA |HyperBus 32-Bits Write Data + * | | |To write 1 Byte to HyperRAM, Byte 0 (Data[7:0]) is used + * | | |To write 2 Bytes to HyperRAM, Byte 1~0 (Data[15:0]) is used + * | | |To write 3 Bytes to HyperRAM, Byte 2~0 (Data[23:0]) is used + * | | |To write 4 Bytes to HyperRAM, Byte 3~ (Data[31:0]) is used + * @var HBI_T::RDATA + * Offset: 0x10 HyperBus 32-Bits Read Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RDATA |HyperBus 32-Bits Read Data + * | | |32-Bits Data for HyperBus Read + * | | |Note: The data order is depened on the ENDIAN (HBI_CONFIG[14]). Refer to 1.1.5.4 for detail information. + * @var HBI_T::INTEN + * Offset: 0x14 HyperBus Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPINTEN |HyperBus Operation Done Interrupt Enable + * | | |0 = Operation done interrupt is Disab led. + * | | |1 = Operation done interrupt is Enabled. + * @var HBI_T::INTSTS + * Offset: 0x18 HyperBus Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPDONE |HyperBus Operation Done Interrupt + * | | |0 = HyperBus operation is busy. + * | | |1 = HyperBus operation is done. + */ + __IO uint32_t CMD ; /*!< [0x0000] HyperBus Command and Status Register */ + __IO uint32_t CONFIG; /*!< [0x0004] HyperBus Configuration Register */ + __IO uint32_t ADR; /*!< [0x0008] HyperBus Byte Address access Register */ + __IO uint32_t WDATA; /*!< [0x000C] HyperBus 32-Bits Write Data Register */ + __IO uint32_t RDATA; /*!< [0x0010] HyperBus 32-Bits Read Data Register */ + __IO uint32_t INTEN; /*!< [0x0014] HyperBus Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0018] HyperBus Interrupt Status Register */ +} HBI_T; + +/** + @addtogroup HBI_CONST HBI Bit Field Definition + Constant Definitions for HBI Controller +@{ */ + +#define HBI_CMD_HYPCMD_Pos (0) /*!< HBI_T::CMD: HYPCMD Position */ +#define HBI_CMD_HYPCMD_Msk (0xful << HBI_CMD_HYPCMD_Pos) /*!< HBI_T::CMD: HYPCMD Mask */ + +#define HBI_CONFIG_CSST_Pos (0) /*!< HBI_T::CONFIG: CSST Position */ +#define HBI_CONFIG_CSST_Msk (0x3ul << HBI_CONFIG_CSST_Pos) /*!< HBI_T::CONFIG: CSST Mask */ + +#define HBI_CONFIG_ACCT_Pos (2) /*!< HBI_T::CONFIG: ACCT Position */ +#define HBI_CONFIG_ACCT_Msk (0xful << HBI_CONFIG_ACCT_Pos) /*!< HBI_T::CONFIG: ACCT Mask */ + +#define HBI_CONFIG_CSH_Pos (6) /*!< HBI_T::CONFIG: CSH Position */ +#define HBI_CONFIG_CSH_Msk (0x3ul << HBI_CONFIG_CSH_Pos) /*!< HBI_T::CONFIG: CSH Mask */ + +#define HBI_CONFIG_CSHI_Pos (8) /*!< HBI_T::CONFIG: CSHI Position */ +#define HBI_CONFIG_CSHI_Msk (0xful << HBI_CONFIG_CSHI_Pos) /*!< HBI_T::CONFIG: CSHI Mask */ + +#define HBI_CONFIG_BGSIZE_Pos (12) /*!< HBI_T::CONFIG: BGSIZE Position */ +#define HBI_CONFIG_BGSIZE_Msk (0x3ul << HBI_CONFIG_BGSIZE_Pos) /*!< HBI_T::CONFIG: BGSIZE Mask */ + +#define HBI_CONFIG_ENDIAN_Pos (14) /*!< HBI_T::CONFIG: ENDIAN Position */ +#define HBI_CONFIG_ENDIAN_Msk (0x1ul << HBI_CONFIG_ENDIAN_Pos) /*!< HBI_T::CONFIG: ENDIAN Mask */ + +#define HBI_CONFIG_CKDIV_Pos (15) /*!< HBI_T::CONFIG: CKDIV Position */ +#define HBI_CONFIG_CKDIV_Msk (0x1ul << HBI_CONFIG_CKDIV_Pos) /*!< HBI_T::CONFIG: CKDIV Mask */ + +#define HBI_CONFIG_CSMAXLT_Pos (16) /*!< HBI_T::CONFIG: CSMAXLT Position */ +#define HBI_CONFIG_CSMAXLT_Msk (0x7fful << HBI_CONFIG_CSMAXLT_Pos) /*!< HBI_T::CONFIG: CSMAXLT Mask */ + +#define HBI_ADR_ADR_Pos (0) /*!< HBI_T::ADR: ADR Position */ +#define HBI_ADR_ADR_Msk (0xfffffffful << HBI_ADR_ADR_Pos) /*!< HBI_T::ADR: ADR Mask */ + +#define HBI_WDATA_WDATA_Pos (0) /*!< HBI_T::WDATA: WDATA Position */ +#define HBI_WDATA_WDATA_Msk (0xfffffffful << HBI_WDATA_WDATA_Pos) /*!< HBI_T::WDATA: WDATA Mask */ + +#define HBI_RDATA_RDATA_Pos (0) /*!< HBI_T::RDATA: RDATA Position */ +#define HBI_RDATA_RDATA_Msk (0xfffffffful << HBI_RDATA_RDATA_Pos) /*!< HBI_T::RDATA: RDATA Mask */ + +#define HBI_INTEN_OPINTEN_Pos (0) /*!< HBI_T::INTEN: OPINTEN Position */ +#define HBI_INTEN_OPINTEN_Msk (0x1ul << HBI_INTEN_OPINTEN_Pos) /*!< HBI_T::INTEN: OPINTEN Mask */ + +#define HBI_INTSTS_OPDONE_Pos (0) /*!< HBI_T::INTSTS: OPDONE Position */ +#define HBI_INTSTS_OPDONE_Msk (0x1ul << HBI_INTSTS_OPDONE_Pos) /*!< HBI_T::INTSTS: OPDONE Mask */ + + +/**@}*/ /* HBI_CONST */ +/**@}*/ /* end of HBI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HBI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsotg_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsotg_reg.h new file mode 100644 index 0000000..beb9300 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsotg_reg.h @@ -0,0 +1,401 @@ +/**************************************************************************//** + * @file hsotg_reg.h + * @version V3.00 + * @brief HSOTG register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSOTG_REG_H__ +#define __HSOTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSOTG High Speed USB On-The-Go Controller(HSOTG) + Memory Mapped Structure for HSOTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSOTG_T::CTL + * Offset: 0x00 HSOTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var HSOTG_T::PHYCTL + * Offset: 0x04 HSOTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent, this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var HSOTG_T::INTEN + * Offset: 0x08 HSOTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var HSOTG_T::INTSTS + * Offset: 0x0C HSOTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var HSOTG_T::STATUS + * Offset: 0x10 HSOTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V and A-device drives VBUS , this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] HSOTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] HSOTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] HSOTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] HSOTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] HSOTG Status Register */ + +} HSOTG_T; + +/** + @addtogroup HSOTG_CONST HSOTG Bit Field Definition + Constant Definitions for HSOTG Controller +@{ */ + +#define HSOTG_CTL_VBUSDROP_Pos (0) /*!< HSOTG_T::CTL: VBUSDROP Position */ +#define HSOTG_CTL_VBUSDROP_Msk (0x1ul << HSOTG_CTL_VBUSDROP_Pos) /*!< HSOTG_T::CTL: VBUSDROP Mask */ + +#define HSOTG_CTL_BUSREQ_Pos (1) /*!< HSOTG_T::CTL: BUSREQ Position */ +#define HSOTG_CTL_BUSREQ_Msk (0x1ul << HSOTG_CTL_BUSREQ_Pos) /*!< HSOTG_T::CTL: BUSREQ Mask */ + +#define HSOTG_CTL_HNPREQEN_Pos (2) /*!< HSOTG_T::CTL: HNPREQEN Position */ +#define HSOTG_CTL_HNPREQEN_Msk (0x1ul << HSOTG_CTL_HNPREQEN_Pos) /*!< HSOTG_T::CTL: HNPREQEN Mask */ + +#define HSOTG_CTL_OTGEN_Pos (4) /*!< HSOTG_T::CTL: OTGEN Position */ +#define HSOTG_CTL_OTGEN_Msk (0x1ul << HSOTG_CTL_OTGEN_Pos) /*!< HSOTG_T::CTL: OTGEN Mask */ + +#define HSOTG_CTL_WKEN_Pos (5) /*!< HSOTG_T::CTL: WKEN Position */ +#define HSOTG_CTL_WKEN_Msk (0x1ul << HSOTG_CTL_WKEN_Pos) /*!< HSOTG_T::CTL: WKEN Mask */ + +#define HSOTG_PHYCTL_OTGPHYEN_Pos (0) /*!< HSOTG_T::PHYCTL: OTGPHYEN Position */ +#define HSOTG_PHYCTL_OTGPHYEN_Msk (0x1ul << HSOTG_PHYCTL_OTGPHYEN_Pos) /*!< HSOTG_T::PHYCTL: OTGPHYEN Mask */ + +#define HSOTG_PHYCTL_IDDETEN_Pos (1) /*!< HSOTG_T::PHYCTL: IDDETEN Position */ +#define HSOTG_PHYCTL_IDDETEN_Msk (0x1ul << HSOTG_PHYCTL_IDDETEN_Pos) /*!< HSOTG_T::PHYCTL: IDDETEN Mask */ + +#define HSOTG_PHYCTL_VBENPOL_Pos (4) /*!< HSOTG_T::PHYCTL: VBENPOL Position */ +#define HSOTG_PHYCTL_VBENPOL_Msk (0x1ul << HSOTG_PHYCTL_VBENPOL_Pos) /*!< HSOTG_T::PHYCTL: VBENPOL Mask */ + +#define HSOTG_PHYCTL_VBSTSPOL_Pos (5) /*!< HSOTG_T::PHYCTL: VBSTSPOL Position */ +#define HSOTG_PHYCTL_VBSTSPOL_Msk (0x1ul << HSOTG_PHYCTL_VBSTSPOL_Pos) /*!< HSOTG_T::PHYCTL: VBSTSPOL Mask */ + +#define HSOTG_PHYCTL_FSEL_Pos (8) /*!< HSOTG_T::PHYCTL: FSEL Position */ +#define HSOTG_PHYCTL_FSEL_Msk (0x7ul << HSOTG_PHYCTL_FSEL_Pos) /*!< HSOTG_T::PHYCTL: FSEL Mask */ + +#define HSOTG_INTEN_ROLECHGIEN_Pos (0) /*!< HSOTG_T::INTEN: ROLECHGIEN Position */ +#define HSOTG_INTEN_ROLECHGIEN_Msk (0x1ul << HSOTG_INTEN_ROLECHGIEN_Pos) /*!< HSOTG_T::INTEN: ROLECHGIEN Mask */ + +#define HSOTG_INTEN_VBEIEN_Pos (1) /*!< HSOTG_T::INTEN: VBEIEN Position */ +#define HSOTG_INTEN_VBEIEN_Msk (0x1ul << HSOTG_INTEN_VBEIEN_Pos) /*!< HSOTG_T::INTEN: VBEIEN Mask */ + +#define HSOTG_INTEN_SRPFIEN_Pos (2) /*!< HSOTG_T::INTEN: SRPFIEN Position */ +#define HSOTG_INTEN_SRPFIEN_Msk (0x1ul << HSOTG_INTEN_SRPFIEN_Pos) /*!< HSOTG_T::INTEN: SRPFIEN Mask */ + +#define HSOTG_INTEN_HNPFIEN_Pos (3) /*!< HSOTG_T::INTEN: HNPFIEN Position */ +#define HSOTG_INTEN_HNPFIEN_Msk (0x1ul << HSOTG_INTEN_HNPFIEN_Pos) /*!< HSOTG_T::INTEN: HNPFIEN Mask */ + +#define HSOTG_INTEN_GOIDLEIEN_Pos (4) /*!< HSOTG_T::INTEN: GOIDLEIEN Position */ +#define HSOTG_INTEN_GOIDLEIEN_Msk (0x1ul << HSOTG_INTEN_GOIDLEIEN_Pos) /*!< HSOTG_T::INTEN: GOIDLEIEN Mask */ + +#define HSOTG_INTEN_IDCHGIEN_Pos (5) /*!< HSOTG_T::INTEN: IDCHGIEN Position */ +#define HSOTG_INTEN_IDCHGIEN_Msk (0x1ul << HSOTG_INTEN_IDCHGIEN_Pos) /*!< HSOTG_T::INTEN: IDCHGIEN Mask */ + +#define HSOTG_INTEN_PDEVIEN_Pos (6) /*!< HSOTG_T::INTEN: PDEVIEN Position */ +#define HSOTG_INTEN_PDEVIEN_Msk (0x1ul << HSOTG_INTEN_PDEVIEN_Pos) /*!< HSOTG_T::INTEN: PDEVIEN Mask */ + +#define HSOTG_INTEN_HOSTIEN_Pos (7) /*!< HSOTG_T::INTEN: HOSTIEN Position */ +#define HSOTG_INTEN_HOSTIEN_Msk (0x1ul << HSOTG_INTEN_HOSTIEN_Pos) /*!< HSOTG_T::INTEN: HOSTIEN Mask */ + +#define HSOTG_INTEN_BVLDCHGIEN_Pos (8) /*!< HSOTG_T::INTEN: BVLDCHGIEN Position */ +#define HSOTG_INTEN_BVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_BVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: BVLDCHGIEN Mask */ + +#define HSOTG_INTEN_AVLDCHGIEN_Pos (9) /*!< HSOTG_T::INTEN: AVLDCHGIEN Position */ +#define HSOTG_INTEN_AVLDCHGIEN_Msk (0x1ul << HSOTG_INTEN_AVLDCHGIEN_Pos) /*!< HSOTG_T::INTEN: AVLDCHGIEN Mask */ + +#define HSOTG_INTEN_VBCHGIEN_Pos (10) /*!< HSOTG_T::INTEN: VBCHGIEN Position */ +#define HSOTG_INTEN_VBCHGIEN_Msk (0x1ul << HSOTG_INTEN_VBCHGIEN_Pos) /*!< HSOTG_T::INTEN: VBCHGIEN Mask */ + +#define HSOTG_INTEN_SECHGIEN_Pos (11) /*!< HSOTG_T::INTEN: SECHGIEN Position */ +#define HSOTG_INTEN_SECHGIEN_Msk (0x1ul << HSOTG_INTEN_SECHGIEN_Pos) /*!< HSOTG_T::INTEN: SECHGIEN Mask */ + +#define HSOTG_INTEN_SRPDETIEN_Pos (13) /*!< HSOTG_T::INTEN: SRPDETIEN Position */ +#define HSOTG_INTEN_SRPDETIEN_Msk (0x1ul << HSOTG_INTEN_SRPDETIEN_Pos) /*!< HSOTG_T::INTEN: SRPDETIEN Mask */ + +#define HSOTG_INTSTS_ROLECHGIF_Pos (0) /*!< HSOTG_T::INTSTS: ROLECHGIF Position */ +#define HSOTG_INTSTS_ROLECHGIF_Msk (0x1ul << HSOTG_INTSTS_ROLECHGIF_Pos) /*!< HSOTG_T::INTSTS: ROLECHGIF Mask */ + +#define HSOTG_INTSTS_VBEIF_Pos (1) /*!< HSOTG_T::INTSTS: VBEIF Position */ +#define HSOTG_INTSTS_VBEIF_Msk (0x1ul << HSOTG_INTSTS_VBEIF_Pos) /*!< HSOTG_T::INTSTS: VBEIF Mask */ + +#define HSOTG_INTSTS_SRPFIF_Pos (2) /*!< HSOTG_T::INTSTS: SRPFIF Position */ +#define HSOTG_INTSTS_SRPFIF_Msk (0x1ul << HSOTG_INTSTS_SRPFIF_Pos) /*!< HSOTG_T::INTSTS: SRPFIF Mask */ + +#define HSOTG_INTSTS_HNPFIF_Pos (3) /*!< HSOTG_T::INTSTS: HNPFIF Position */ +#define HSOTG_INTSTS_HNPFIF_Msk (0x1ul << HSOTG_INTSTS_HNPFIF_Pos) /*!< HSOTG_T::INTSTS: HNPFIF Mask */ + +#define HSOTG_INTSTS_GOIDLEIF_Pos (4) /*!< HSOTG_T::INTSTS: GOIDLEIF Position */ +#define HSOTG_INTSTS_GOIDLEIF_Msk (0x1ul << HSOTG_INTSTS_GOIDLEIF_Pos) /*!< HSOTG_T::INTSTS: GOIDLEIF Mask */ + +#define HSOTG_INTSTS_IDCHGIF_Pos (5) /*!< HSOTG_T::INTSTS: IDCHGIF Position */ +#define HSOTG_INTSTS_IDCHGIF_Msk (0x1ul << HSOTG_INTSTS_IDCHGIF_Pos) /*!< HSOTG_T::INTSTS: IDCHGIF Mask */ + +#define HSOTG_INTSTS_PDEVIF_Pos (6) /*!< HSOTG_T::INTSTS: PDEVIF Position */ +#define HSOTG_INTSTS_PDEVIF_Msk (0x1ul << HSOTG_INTSTS_PDEVIF_Pos) /*!< HSOTG_T::INTSTS: PDEVIF Mask */ + +#define HSOTG_INTSTS_HOSTIF_Pos (7) /*!< HSOTG_T::INTSTS: HOSTIF Position */ +#define HSOTG_INTSTS_HOSTIF_Msk (0x1ul << HSOTG_INTSTS_HOSTIF_Pos) /*!< HSOTG_T::INTSTS: HOSTIF Mask */ + +#define HSOTG_INTSTS_BVLDCHGIF_Pos (8) /*!< HSOTG_T::INTSTS: BVLDCHGIF Position */ +#define HSOTG_INTSTS_BVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_BVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: BVLDCHGIF Mask */ + +#define HSOTG_INTSTS_AVLDCHGIF_Pos (9) /*!< HSOTG_T::INTSTS: AVLDCHGIF Position */ +#define HSOTG_INTSTS_AVLDCHGIF_Msk (0x1ul << HSOTG_INTSTS_AVLDCHGIF_Pos) /*!< HSOTG_T::INTSTS: AVLDCHGIF Mask */ + +#define HSOTG_INTSTS_VBCHGIF_Pos (10) /*!< HSOTG_T::INTSTS: VBCHGIF Position */ +#define HSOTG_INTSTS_VBCHGIF_Msk (0x1ul << HSOTG_INTSTS_VBCHGIF_Pos) /*!< HSOTG_T::INTSTS: VBCHGIF Mask */ + +#define HSOTG_INTSTS_SECHGIF_Pos (11) /*!< HSOTG_T::INTSTS: SECHGIF Position */ +#define HSOTG_INTSTS_SECHGIF_Msk (0x1ul << HSOTG_INTSTS_SECHGIF_Pos) /*!< HSOTG_T::INTSTS: SECHGIF Mask */ + +#define HSOTG_INTSTS_SRPDETIF_Pos (13) /*!< HSOTG_T::INTSTS: SRPDETIF Position */ +#define HSOTG_INTSTS_SRPDETIF_Msk (0x1ul << HSOTG_INTSTS_SRPDETIF_Pos) /*!< HSOTG_T::INTSTS: SRPDETIF Mask */ + +#define HSOTG_STATUS_OVERCUR_Pos (0) /*!< HSOTG_T::STATUS: OVERCUR Position */ +#define HSOTG_STATUS_OVERCUR_Msk (0x1ul << HSOTG_STATUS_OVERCUR_Pos) /*!< HSOTG_T::STATUS: OVERCUR Mask */ + +#define HSOTG_STATUS_IDSTS_Pos (1) /*!< HSOTG_T::STATUS: IDSTS Position */ +#define HSOTG_STATUS_IDSTS_Msk (0x1ul << HSOTG_STATUS_IDSTS_Pos) /*!< HSOTG_T::STATUS: IDSTS Mask */ + +#define HSOTG_STATUS_SESSEND_Pos (2) /*!< HSOTG_T::STATUS: SESSEND Position */ +#define HSOTG_STATUS_SESSEND_Msk (0x1ul << HSOTG_STATUS_SESSEND_Pos) /*!< HSOTG_T::STATUS: SESSEND Mask */ + +#define HSOTG_STATUS_BVLD_Pos (3) /*!< HSOTG_T::STATUS: BVLD Position */ +#define HSOTG_STATUS_BVLD_Msk (0x1ul << HSOTG_STATUS_BVLD_Pos) /*!< HSOTG_T::STATUS: BVLD Mask */ + +#define HSOTG_STATUS_AVLD_Pos (4) /*!< HSOTG_T::STATUS: AVLD Position */ +#define HSOTG_STATUS_AVLD_Msk (0x1ul << HSOTG_STATUS_AVLD_Pos) /*!< HSOTG_T::STATUS: AVLD Mask */ + +#define HSOTG_STATUS_VBUSVLD_Pos (5) /*!< HSOTG_T::STATUS: VBUSVLD Position */ +#define HSOTG_STATUS_VBUSVLD_Msk (0x1ul << HSOTG_STATUS_VBUSVLD_Pos) /*!< HSOTG_T::STATUS: VBUSVLD Mask */ + +#define HSOTG_STATUS_ASPERI_Pos (6) /*!< HSOTG_T::STATUS: ASPERI Position */ +#define HSOTG_STATUS_ASPERI_Msk (0x1ul << HSOTG_STATUS_ASPERI_Pos) /*!< HSOTG_T::STATUS: ASPERI Mask */ + +#define HSOTG_STATUS_ASHOST_Pos (7) /*!< HSOTG_T::STATUS: ASHOST Position */ +#define HSOTG_STATUS_ASHOST_Msk (0x1ul << HSOTG_STATUS_ASHOST_Pos) /*!< HSOTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* HSOTG_CONST */ +/**@}*/ /* end of HSOTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSOTG_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsusbd_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsusbd_reg.h new file mode 100644 index 0000000..0e47c3e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsusbd_reg.h @@ -0,0 +1,1425 @@ +/**************************************************************************//** + * @file hsusbd_reg.h + * @version V3.00 + * @brief HSUSBD register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBD_REG_H__ +#define __HSUSBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBD USB 2.0 Device Controller(HSUSBD) + Memory Mapped Structure for HSUSBD Controller +@{ */ + +typedef struct +{ + + /** + * @var HSUSBD_EP_T::EPDAT + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_EP_T::EPDAT_BYTE + * Offset: 0x00 Endpoint n Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EPDAT |Endpoint A~L Data Register + * | | |Endpoint A~L data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_EP_T::EPINTSTS + * Offset: 0x04 Endpoint n Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIF |Buffer Full + * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write) + * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading). + * | | |0 = The endpoint packet buffer is not full. + * | | |1 = The endpoint packet buffer is full. + * | | |Note: This bit is read-only. + * |[1] |BUFEMPTYIF|Buffer Empty + * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. + * | | |0 = The endpoint buffer is not empty. + * | | |1 = The endpoint buffer is empty. + * | | |For an OUT endpoint: + * | | |0 = The currently selected buffer has not a count of 0. + * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read). + * | | |Note: This bit is read-only. + * |[2] |SHORTTXIF |Short Packet Transferred Interrupt + * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS). + * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS). + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is transmitted from the endpoint to the host. + * | | |1 = A data packet is transmitted from the endpoint to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |RXPKIF |Data Packet Received Interrupt + * | | |0 = No data packet is received from the host by the endpoint. + * | | |1 = A data packet is received from the host by the endpoint. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |OUTTKIF |Data OUT Token Interrupt + * | | |0 = A Data OUT token has not been received from the host. + * | | |1 = A Data OUT token has been received from the host + * | | |This bit also set by PING token (in high-speed only). + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |INTKIF |Data IN Token Interrupt + * | | |0 = Not Data IN token has been received from the host. + * | | |1 = A Data IN token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |PINGIF |PING Token Interrupt + * | | |0 = A Data PING token has not been received from the host. + * | | |1 = A Data PING token has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |NAKIF |USB NAK Sent + * | | |0 = The last USB IN packet could be provided, and was acknowledged with an ACK. + * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |STALLIF |USB STALL Sent + * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |NYETIF |NYET Sent + * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet. + * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |ERRIF |ERR Sent + * | | |0 = No any error in the transaction. + * | | |1 = There occurs any error in the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |SHORTRXIF |Bulk Out Short Packet Received + * | | |0 = No bulk out short packet is received. + * | | |1 = Received bulk out short packet (including zero length packet). + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_EP_T::EPINTEN + * Offset: 0x08 Endpoint n Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUFFULLIEN|Buffer Full Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus. + * | | |0 = Buffer full interrupt Disabled. + * | | |1 = Buffer full interrupt Enabled. + * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus. + * | | |0 = Buffer empty interrupt Disabled. + * | | |1 = Buffer empty interrupt Enabled. + * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host. + * | | |0 = Short data packet interrupt Disabled. + * | | |1 = Short data packet interrupt Enabled. + * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host. + * | | |0 = Data packet has been received from the host interrupt Disabled. + * | | |1 = Data packet has been received from the host interrupt Enabled. + * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host. + * | | |0 = Data packet has been transmitted to the host interrupt Disabled. + * | | |1 = Data packet has been transmitted to the host interrupt Enabled. + * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host. + * | | |0 = Data OUT token interrupt Disabled. + * | | |1 = Data OUT token interrupt Enabled. + * |[6] |INTKIEN |Data IN Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host. + * | | |0 = Data IN token interrupt Disabled. + * | | |1 = Data IN token interrupt Enabled. + * |[7] |PINGIEN |PING Token Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host. + * | | |0 = PING token interrupt Disabled. + * | | |1 = PING token interrupt Enabled. + * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host. + * | | |0 = NAK token interrupt Disabled. + * | | |1 = NAK token interrupt Enabled. + * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host. + * | | |0 = STALL token interrupt Disabled. + * | | |1 = STALL token interrupt Enabled. + * |[10] |NYETIEN |NYET Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint. + * | | |0 = NYET condition interrupt Disabled. + * | | |1 = NYET condition interrupt Enabled. + * |[11] |ERRIEN |ERR Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint. + * | | |0 = Error event interrupt Disabled. + * | | |1 = Error event interrupt Enabled. + * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint. + * | | |0 = Bulk out interrupt Disabled. + * | | |1 = Bulk out interrupt Enabled. + * @var HSUSBD_EP_T::EPDATCNT + * Offset: 0x0C Endpoint n Data Available Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Data Count + * | | |For an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer. + * | | |For an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer. + * |[30:16] |DMALOOP |DMA Loop + * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer. + * @var HSUSBD_EP_T::EPRSPCTL + * Offset: 0x10 Endpoint n Response Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FLUSH |Buffer Flush + * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared + * | | |This bit is self-clearing + * | | |This bit should always be written after an configuration event. + * | | |0 = The packet buffer is not flushed. + * | | |1 = The packet buffer is flushed by user. + * |[2:1] |MODE |Mode Control + * | | |The two bits decide the operation mode of the in-endpoint. + * | | |00: Auto-Validate Mode + * | | |01: Manual-Validate Mode + * | | |10: Fly Mode + * | | |11: Reserved + * | | |These bits are not valid for an out-endpoint + * | | |The auto validate mode will be activated when the reserved mode is selected + * |[3] |TOGGLE |Endpoint Toggle + * | | |This bit is used to clear the endpoint data toggle bit + * | | |Reading this bit returns the current state of the endpoint data toggle bit. + * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host + * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3]. + * | | |0 = Not clear the endpoint data toggle bit. + * | | |1 = Clear the endpoint data toggle bit. + * |[4] |HALT |Endpoint Halt + * | | |This bit is used to send a STALL handshake as response to the token from the host + * | | |When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit. + * | | |0 = Not send a STALL handshake as response to the token from the host. + * | | |1 = Send a STALL handshake as response to the token from the host. + * |[5] |ZEROLEN |Zero Length + * | | |This bit is used to send a zero-length packet response to an IN-token + * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token + * | | |This bit gets cleared once the zero length data packet is sent. + * | | |0 = A zero packet is not sent to the host on reception of an IN-token. + * | | |1 = A zero packet is sent to the host on reception of an IN-token. + * |[6] |SHORTTXEN |Short Packet Transfer Enable + * | | |This bit is applicable only in case of Auto-Validate Method + * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer + * | | |This bit gets cleared once the data packet is sent. + * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint. + * |[7] |DISBUF |Buffer Disable Bit + * | | |This bit is used to receive unknown size OUT short packet + * | | |The received packet size is reference USBD_EPxDATCNT register. + * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received. + * | | |1 = Buffer Disabled when Bulk-OUT short packet is received. + * @var HSUSBD_EP_T::EPMPS + * Offset: 0x14 Endpoint n Maximum Packet Size Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |EPMPS |Endpoint Maximum Packet Size + * | | |This field determines the Maximum Packet Size of the Endpoint. + * @var HSUSBD_EP_T::EPTXCNT + * Offset: 0x18 Endpoint n Transfer Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |TXCNT |Endpoint Transfer Count + * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method. + * | | |For OUT endpoints, this field has no effect. + * @var HSUSBD_EP_T::EPCFG + * Offset: 0x1C Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPEN |Endpoint Valid + * | | |When set, this bit enables this endpoint + * | | |This bit has no effect on Endpoint 0, which is always enabled. + * | | |0 = The endpoint Disabled. + * | | |1 = The endpoint Enabled. + * |[2:1] |EPTYPE |Endpoint Type + * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type. + * | | |00 = Reserved. + * | | |01 = Bulk. + * | | |10 = Interrupt. + * | | |11 = Isochronous. + * |[3] |EPDIR |Endpoint Direction + * | | |0 = out-endpoint (Host OUT to Device). + * | | |1 = in-endpoint (Host IN to Device). + * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number. + * |[7:4] |EPNUM |Endpoint Number + * | | |This field selects the number of the endpoint. Valid numbers 1 to 15. + * | | |Note: Do not support two endpoints have same endpoint number. + * @var HSUSBD_EP_T::EPBUFST + * Offset: 0x20 Endpoint n RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the endpoint A~L. + * @var HSUSBD_EP_T::EPBUFEND + * Offset: 0x24 Endpoint n RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Endpoint End Address + * | | |This is the end-address of the RAM space allocated for the endpoint A~L. + */ + + union + { + __IO uint32_t EPDAT; + __IO uint8_t EPDAT_BYTE; + + }; /*!< [0x0000] Endpoint n Data Register */ + + __IO uint32_t EPINTSTS; /*!< [0x0004] Endpoint n Interrupt Status Register */ + __IO uint32_t EPINTEN; /*!< [0x0008] Endpoint n Interrupt Enable Register */ + __I uint32_t EPDATCNT; /*!< [0x000c] Endpoint n Data Available Count Register */ + __IO uint32_t EPRSPCTL; /*!< [0x0010] Endpoint n Response Control Register */ + __IO uint32_t EPMPS; /*!< [0x0014] Endpoint n Maximum Packet Size Register */ + __IO uint32_t EPTXCNT; /*!< [0x0018] Endpoint n Transfer Count Register */ + __IO uint32_t EPCFG; /*!< [0x001c] Endpoint n Configuration Register */ + __IO uint32_t EPBUFST; /*!< [0x0020] Endpoint n RAM Start Address Register */ + __IO uint32_t EPBUFEND; /*!< [0x0024] Endpoint n RAM End Address Register */ + +} HSUSBD_EP_T; + +typedef struct +{ + + /** + * @var HSUSBD_T::GINTSTS + * Offset: 0x00 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIF |USB Interrupt + * | | |This bit conveys the interrupt status for USB specific events endpoint + * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[1] |CEPIF |Control Endpoint Interrupt + * | | |This bit conveys the interrupt status for control endpoint + * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[2] |EPAIF |Endpoint a Interrupt + * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[3] |EPBIF |Endpoint B Interrupt + * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[4] |EPCIF |Endpoint C Interrupt + * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[5] |EPDIF |Endpoint D Interrupt + * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[6] |EPEIF |Endpoint E Interrupt + * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[7] |EPFIF |Endpoint F Interrupt + * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[8] |EPGIF |Endpoint G Interrupt + * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[9] |EPHIF |Endpoint H Interrupt + * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[10] |EPIIF |Endpoint I Interrupt + * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[11] |EPJIF |Endpoint J Interrupt + * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[12] |EPKIF |Endpoint K Interrupt + * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * |[13] |EPLIF |Endpoint L Interrupt + * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. + * | | |0 = No interrupt event occurred. + * | | |1 = The related interrupt event is occurred. + * @var HSUSBD_T::GINTEN + * Offset: 0x08 Global Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[1] |CEPIEN |Control Endpoint Interrupt Enable Bit + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[2] |EPAIEN |Interrupt Enable Control for Endpoint a + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A. + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[3] |EPBIEN |Interrupt Enable Control for Endpoint B + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[4] |EPCIEN |Interrupt Enable Control for Endpoint C + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[5] |EPDIEN |Interrupt Enable Control for Endpoint D + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[6] |EPEIEN |Interrupt Enable Control for Endpoint E + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[7] |EPFIEN |Interrupt Enable Control for Endpoint F + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[8] |EPGIEN |Interrupt Enable Control for Endpoint G + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[9] |EPHIEN |Interrupt Enable Control for Endpoint H + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[10] |EPIIEN |Interrupt Enable Control for Endpoint I + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[11] |EPJIEN |Interrupt Enable Control for Endpoint J + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[12] |EPKIEN |Interrupt Enable Control for Endpoint K + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * |[13] |EPLIEN |Interrupt Enable Control for Endpoint L + * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L + * | | |0 = The related interrupt Disabled. + * | | |1 = The related interrupt Enabled. + * @var HSUSBD_T::BUSINTSTS + * Offset: 0x10 USB Bus Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIF |SOF Receive Control + * | | |This bit indicates when a start-of-frame packet has been received. + * | | |0 = No start-of-frame packet has been received. + * | | |1 = Start-of-frame packet has been received. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |RSTIF |Reset Status + * | | |When set, this bit indicates that either the USB root port reset is end. + * | | |0 = No USB root port reset is end. + * | | |1 = USB root port reset is end. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |RESUMEIF |Resume + * | | |When set, this bit indicates that a device resume has occurred. + * | | |0 = No device resume has occurred. + * | | |1 = Device resume has occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |SUSPENDIF |Suspend Request + * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset + * | | |This bit is also set when a USB Suspend request is detected from the host. + * | | |0 = No USB Suspend request is detected from the host. + * | | |1= USB Suspend request is detected from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |HISPDIF |High-speed Settle + * | | |0 = No valid high-speed reset protocol is detected. + * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |DMADONEIF |DMA Completion Interrupt + * | | |0 = No DMA transfer over. + * | | |1 = DMA transfer is over. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |PHYCLKVLDIF|Usable Clock Interrupt + * | | |0 = Usable clock is not available. + * | | |1 = Usable clock is available from the transceiver. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |VBUSDETIF |VBUS Detection Interrupt Status + * | | |0 = No VBUS is plug-in. + * | | |1 = VBUS is plug-in. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::BUSINTEN + * Offset: 0x14 USB Bus Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SOFIEN |SOF Interrupt + * | | |This bit enables the SOF interrupt. + * | | |0 = SOF interrupt Disabled. + * | | |1 = SOF interrupt Enabled. + * |[1] |RSTIEN |Reset Status + * | | |This bit enables the USB-Reset interrupt. + * | | |0 = USB-Reset interrupt Disabled. + * | | |1 = USB-Reset interrupt Enabled. + * |[2] |RESUMEIEN |Resume + * | | |This bit enables the Resume interrupt. + * | | |0 = Resume interrupt Disabled. + * | | |1 = Resume interrupt Enabled. + * |[3] |SUSPENDIEN|Suspend Request + * | | |This bit enables the Suspend interrupt. + * | | |0 = Suspend interrupt Disabled. + * | | |1 = Suspend interrupt Enabled. + * |[4] |HISPDIEN |High-speed Settle + * | | |This bit enables the high-speed settle interrupt. + * | | |0 = High-speed settle interrupt Disabled. + * | | |1 = High-speed settle interrupt Enabled. + * |[5] |DMADONEIEN|DMA Completion Interrupt + * | | |This bit enables the DMA completion interrupt + * | | |0 = DMA completion interrupt Disabled. + * | | |1 = DMA completion interrupt Enabled. + * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt + * | | |This bit enables the usable clock interrupt. + * | | |0 = Usable clock interrupt Disabled. + * | | |1 = Usable clock interrupt Enabled. + * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Bit + * | | |This bit enables the VBUS floating detection interrupt. + * | | |0 = VBUS floating detection interrupt Disabled. + * | | |1 = VBUS floating detection interrupt Enabled. + * @var HSUSBD_T::OPER + * Offset: 0x18 USB Operational Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RESUMEEN |Generate Resume + * | | |0 = No Resume sequence to be initiated to the host. + * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled + * | | |This bit is self-clearing. + * |[1] |HISPDEN |USB High-speed + * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host. + * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol. + * |[2] |CURSPD |USB Current Speed + * | | |0 = The device has settled in Full Speed. + * | | |1 = The USB device controller has settled in High-speed. + * @var HSUSBD_T::FRAMECNT + * Offset: 0x1C USB Frame Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |MFRAMECNT |Micro-frame Counter + * | | |This field contains the micro-frame number for the frame number in the frame counter field. + * |[13:3] |FRAMECNT |Frame Counter + * | | |This field contains the frame count from the most recent start-of-frame packet. + * @var HSUSBD_T::FADDR + * Offset: 0x20 USB Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Function Address + * | | |This field contains the current USB address of the device + * | | |This field is cleared when a root port reset is detected + * @var HSUSBD_T::TEST + * Offset: 0x24 USB Test Mode Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TESTMODE |Test Mode Selection + * | | |000 = Normal Operation. + * | | |001 = Test_J. + * | | |010 = Test_K. + * | | |011 = Test_SE0_NAK. + * | | |100 = Test_Packet. + * | | |101 = Test_Force_Enable. + * | | |110 = Reserved. + * | | |111 = Reserved. + * | | |Note: This field is cleared when root port reset is detected. + * @var HSUSBD_T::CEPDAT + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only word access is supported. + * @var HSUSBD_T::CEPDAT_BYTE + * Offset: 0x28 Control-Endpoint Data Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Control-endpoint Data Buffer + * | | |Control endpoint data buffer for the buffer transaction (read or write). + * | | |Note: Only byte access is supported. + * @var HSUSBD_T::CEPCTL + * Offset: 0x2C Control-Endpoint Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |NAKCLR |No Acknowledge Control + * | | |This bit plays a crucial role in any control transfer. + * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase + * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request. + * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received + * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[1] |STALLEN |Stall Enable Bit + * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter + * | | |This is typically used for response to invalid/unsupported requests + * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL + * | | |It is automatically cleared on receipt of a next setup-token + * | | |So, the local CPU need not write again to clear this bit. + * | | |0 = No sends a stall handshake in response to any in or out token thereafter. + * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter. + * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated. + * |[2] |ZEROLEN |Zero Packet Length + * | | |This bit is valid for Auto Validation mode only. + * | | |0 = No zero length packet to the host during Data stage to an IN token. + * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token + * | | |This bit gets cleared once the zero length data packet is sent + * | | |So, the local CPU need not write again to clear this bit. + * |[3] |FLUSH |CEP-flush Bit + * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. + * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared + * | | |This bit is self-cleaning. + * @var HSUSBD_T::CEPINTEN + * Offset: 0x30 Control-Endpoint Interrupt Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Bit + * | | |0 = The SETUP token interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP token interrupt in Control Endpoint Enabled. + * |[1] |SETUPPKIEN|Setup Packet Interrupt + * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled. + * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled. + * |[2] |OUTTKIEN |Out Token Interrupt + * | | |0 = The OUT token interrupt in Control Endpoint Disabled. + * | | |1 = The OUT token interrupt in Control Endpoint Enabled. + * |[3] |INTKIEN |In Token Interrupt + * | | |0 = The IN token interrupt in Control Endpoint Disabled. + * | | |1 = The IN token interrupt in Control Endpoint Enabled. + * |[4] |PINGIEN |Ping Token Interrupt + * | | |0 = The ping token interrupt in Control Endpoint Disabled. + * | | |1 = The ping token interrupt Control Endpoint Enabled. + * |[5] |TXPKIEN |Data Packet Transmitted Interrupt + * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled. + * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled. + * |[6] |RXPKIEN |Data Packet Received Interrupt + * | | |0 = The data received interrupt in Control Endpoint Disabled. + * | | |1 = The data received interrupt in Control Endpoint Enabled. + * |[7] |NAKIEN |NAK Sent Interrupt + * | | |0 = The NAK sent interrupt in Control Endpoint Disabled. + * | | |1 = The NAK sent interrupt in Control Endpoint Enabled. + * |[8] |STALLIEN |STALL Sent Interrupt + * | | |0 = The STALL sent interrupt in Control Endpoint Disabled. + * | | |1 = The STALL sent interrupt in Control Endpoint Enabled. + * |[9] |ERRIEN |USB Error Interrupt + * | | |0 = The USB Error interrupt in Control Endpoint Disabled. + * | | |1 = The USB Error interrupt in Control Endpoint Enabled. + * |[10] |STSDONEIEN|Status Completion Interrupt + * | | |0 = The Status Completion interrupt in Control Endpoint Disabled. + * | | |1 = The Status Completion interrupt in Control Endpoint Enabled. + * |[11] |BUFFULLIEN|Buffer Full Interrupt + * | | |0 = The buffer full interrupt in Control Endpoint Disabled. + * | | |1 = The buffer full interrupt in Control Endpoint Enabled. + * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt + * | | |0 = The buffer empty interrupt in Control Endpoint Disabled. + * | | |1= The buffer empty interrupt in Control Endpoint Enabled. + * @var HSUSBD_T::CEPINTSTS + * Offset: 0x34 Control-Endpoint Interrupt Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SETUPTKIF |Setup Token Interrupt + * | | |0 = Not a Setup token is received. + * | | |1 = A Setup token is received. Writing 1 clears this status bit + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |SETUPPKIF |Setup Packet Interrupt + * | | |This bit must be cleared (by writing 1) before the next setup packet can be received + * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer. + * | | |0 = Not a Setup packet has been received from the host. + * | | |1 = A Setup packet has been received from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |OUTTKIF |Out Token Interrupt + * | | |0 = The control-endpoint does not received an OUT token from the host. + * | | |1 = The control-endpoint receives an OUT token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[3] |INTKIF |in Token Interrupt + * | | |0 = The control-endpoint does not received an IN token from the host. + * | | |1 = The control-endpoint receives an IN token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |PINGIF |Ping Token Interrupt + * | | |0 = The control-endpoint does not received a ping token from the host. + * | | |1 = The control-endpoint receives a ping token from the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |TXPKIF |Data Packet Transmitted Interrupt + * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |RXPKIF |Data Packet Received Interrupt + * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |NAKIF |NAK Sent Interrupt + * | | |0 = Not a NAK-token is sent in response to an IN/OUT token. + * | | |1 = A NAK-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |STALLIF |STALL Sent Interrupt + * | | |0 = Not a stall-token is sent in response to an IN/OUT token. + * | | |1 = A stall-token is sent in response to an IN/OUT token. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |ERRIF |USB Error Interrupt + * | | |0 = No error had occurred during the transaction. + * | | |1 = An error had occurred during the transaction. + * | | |Note: Write 1 to clear this bit to 0. + * |[10] |STSDONEIF |Status Completion Interrupt + * | | |0 = Not a USB transaction has completed successfully. + * | | |1 = The status stage of a USB transaction has completed successfully. + * | | |Note: Write 1 to clear this bit to 0. + * |[11] |BUFFULLIF |Buffer Full Interrupt + * | | |0 = The control-endpoint buffer is not full. + * | | |1 = The control-endpoint buffer is full. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |BUFEMPTYIF|Buffer Empty Interrupt + * | | |0 = The control-endpoint buffer is not empty. + * | | |1 = The control-endpoint buffer is empty. + * | | |Note: Write 1 to clear this bit to 0. + * @var HSUSBD_T::CEPTXCNT + * Offset: 0x38 Control-Endpoint In-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TXCNT |In-transfer Data Count + * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register + * | | |When zero is written into this field, a zero length packet is sent to the host + * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS. + * @var HSUSBD_T::CEPRXCNT + * Offset: 0x3C Control-Endpoint Out-transfer Data Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RXCNT |Out-transfer Data Count + * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer. + * @var HSUSBD_T::CEPDATCNT + * Offset: 0x40 Control-Endpoint data count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DATCNT |Control-endpoint Data Count + * | | |The USB device controller maintains the count of the data of control-endpoint. + * @var HSUSBD_T::SETUP1_0 + * Offset: 0x44 Setup1 & Setup0 bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP0 |Setup Byte 0[7:0] + * | | |This register provides byte 0 of the last setup packet received + * | | |For a Standard Device Request, the following bmRequestType information is returned. + * | | |Bit 7(Direction): + * | | | 0: Host to device + * | | | 1: Device to host + * | | |Bit 6-5 (Type): + * | | | 00: Standard + * | | | 01: Class + * | | | 10: Vendor + * | | | 11: Reserved + * | | |Bit 4-0 (Recipient) + * | | | 00000: Device + * | | | 00001: Interface + * | | | 00010: Endpoint + * | | | 00011: Other + * | | | Others: Reserved + * |[15:8] |SETUP1 |Setup Byte 1[15:8] + * | | |This register provides byte 1 of the last setup packet received + * | | |For a Standard Device Request, the following bRequest Code information is returned. + * | | |00000000 = Get Status. + * | | |00000001 = Clear Feature. + * | | |00000010 = Reserved. + * | | |00000011 = Set Feature. + * | | |00000100 = Reserved. + * | | |00000101 = Set Address. + * | | |00000110 = Get Descriptor. + * | | |00000111 = Set Descriptor. + * | | |00001000 = Get Configuration. + * | | |00001001 = Set Configuration. + * | | |00001010 = Get Interface. + * | | |00001011 = Set Interface. + * | | |00001100 = Sync Frame. + * @var HSUSBD_T::SETUP3_2 + * Offset: 0x48 Setup3 & Setup2 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP2 |Setup Byte 2 [7:0] + * | | |This register provides byte 2 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wValue field is returned + * |[15:8] |SETUP3 |Setup Byte 3 [15:8] + * | | |This register provides byte 3 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wValue field is returned. + * @var HSUSBD_T::SETUP5_4 + * Offset: 0x4C Setup5 & Setup4 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP4 |Setup Byte 4[7:0] + * | | |This register provides byte 4 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wIndex is returned. + * |[15:8] |SETUP5 |Setup Byte 5[15:8] + * | | |This register provides byte 5 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned. + * @var HSUSBD_T::SETUP7_6 + * Offset: 0x50 Setup7 & Setup6 Bytes + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SETUP6 |Setup Byte 6[7:0] + * | | |This register provides byte 6 of the last setup packet received + * | | |For a Standard Device Request, the least significant byte of the wLength field is returned. + * |[15:8] |SETUP7 |Setup Byte 7[15:8] + * | | |This register provides byte 7 of the last setup packet received + * | | |For a Standard Device Request, the most significant byte of the wLength field is returned. + * @var HSUSBD_T::CEPBUFST + * Offset: 0x54 Control Endpoint RAM Start Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SADDR |Control-endpoint Start Address + * | | |This is the start-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::CEPBUFEND + * Offset: 0x58 Control Endpoint RAM End Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |EADDR |Control-endpoint End Address + * | | |This is the end-address of the RAM space allocated for the control-endpoint. + * @var HSUSBD_T::DMACTL + * Offset: 0x5C DMA Control Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |DMA Endpoint Address Bits + * | | |Used to define the Endpoint Address + * |[4] |DMARD |DMA Operation + * | | |0 : The operation is a DMA write (read from USB buffer) + * | | |DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation. + * | | |1 : The operation is a DMA read (write to USB buffer). + * |[5] |DMAEN |DMA Enable Bit + * | | |0 : DMA function Disabled. + * | | |1 : DMA function Enabled. + * |[6] |SGEN |Scatter Gather Function Enable Bit + * | | |0 : Scatter gather function Disabled. + * | | |1 : Scatter gather function Enabled. + * |[7] |DMARST |Reset DMA State Machine + * | | |0 : No reset the DMA state machine. + * | | |1 : Reset the DMA state machine. + * |[8] |SVINEP |Serve IN Endpoint + * | | |This bit is used to specify DMA serving endpoint-IN endpoint or OUT endpoint. + * | | |0: DMA serves OUT endpoint + * | | |1: DMA serves IN endpoint + * @var HSUSBD_T::DMACNT + * Offset: 0x60 DMA Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |DMACNT |DMA Transfer Count + * | | |The transfer count of the DMA operation to be performed is written to this register. + * @var HSUSBD_T::DMAADDR + * Offset: 0x700 AHB DMA Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMAADDR |DMAADDR + * | | |The register specifies the address from which the DMA has to read / write + * | | |The address must WORD (32-bit) aligned. + * @var HSUSBD_T::PHYCTL + * Offset: 0x704 USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |DPPUEN |DP Pull-up + * | | |0 = Pull-up resistor on D+ Disabled. + * | | |1 = Pull-up resistor on D+ Enabled. + * |[9] |PHYEN |PHY Suspend Enable Bit + * | | |0 = The USB PHY is suspend. + * | | |1 = The USB PHY is not suspend. + * |[24] |VBUSWKEN |Wake-up Enable Bit + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * |[31] |VBUSDET |VBUS Status + * | | |0 = The VBUS is not detected yet. + * | | |1 = The VBUS is detected. + */ + + __I uint32_t GINTSTS; /*!< [0x0000] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GINTEN; /*!< [0x0008] Global Interrupt Enable Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BUSINTSTS; /*!< [0x0010] USB Bus Interrupt Status Register */ + __IO uint32_t BUSINTEN; /*!< [0x0014] USB Bus Interrupt Enable Register */ + __IO uint32_t OPER; /*!< [0x0018] USB Operational Register */ + __I uint32_t FRAMECNT; /*!< [0x001c] USB Frame Count Register */ + __IO uint32_t FADDR; /*!< [0x0020] USB Function Address Register */ + __IO uint32_t TEST; /*!< [0x0024] USB Test Mode Register */ + + union + { + __IO uint32_t CEPDAT; + __IO uint8_t CEPDAT_BYTE; + + }; /*!< [0x0028] Control-Endpoint Data Buffer */ + + __IO uint32_t CEPCTL; /*!< [0x002c] Control-Endpoint Control Register */ + __IO uint32_t CEPINTEN; /*!< [0x0030] Control-Endpoint Interrupt Enable */ + __IO uint32_t CEPINTSTS; /*!< [0x0034] Control-Endpoint Interrupt Status */ + __IO uint32_t CEPTXCNT; /*!< [0x0038] Control-Endpoint In-transfer Data Count */ + __I uint32_t CEPRXCNT; /*!< [0x003c] Control-Endpoint Out-transfer Data Count */ + __I uint32_t CEPDATCNT; /*!< [0x0040] Control-Endpoint data count */ + __I uint32_t SETUP1_0; /*!< [0x0044] Setup1 & Setup0 bytes */ + __I uint32_t SETUP3_2; /*!< [0x0048] Setup3 & Setup2 Bytes */ + __I uint32_t SETUP5_4; /*!< [0x004c] Setup5 & Setup4 Bytes */ + __I uint32_t SETUP7_6; /*!< [0x0050] Setup7 & Setup6 Bytes */ + __IO uint32_t CEPBUFST; /*!< [0x0054] Control Endpoint RAM Start Address Register */ + __IO uint32_t CEPBUFEND; /*!< [0x0058] Control Endpoint RAM End Address Register */ + __IO uint32_t DMACTL; /*!< [0x005c] DMA Control Status Register */ + __IO uint32_t DMACNT; /*!< [0x0060] DMA Count Register */ + + HSUSBD_EP_T EP[12]; + + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[301]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BCDC; /*!< [0x06f8] Battery Charge Detect Control Register */ + __IO uint32_t LPMCSR; /*!< [0x06fc] LPM Control and Status Register */ + __IO uint32_t DMAADDR; /*!< [0x0700] AHB DMA Address Register */ + __IO uint32_t PHYCTL; /*!< [0x0704] USB PHY Control Register */ + +} HSUSBD_T; + +/** + @addtogroup HSUSBD_CONST HSUSBD Bit Field Definition + Constant Definitions for HSUSBD Controller +@{ */ + +#define HSUSBD_GINTSTS_USBIF_Pos (0) /*!< HSUSBD_T::GINTSTS: USBIF Position */ +#define HSUSBD_GINTSTS_USBIF_Msk (0x1ul << HSUSBD_GINTSTS_USBIF_Pos) /*!< HSUSBD_T::GINTSTS: USBIF Mask */ + +#define HSUSBD_GINTSTS_CEPIF_Pos (1) /*!< HSUSBD_T::GINTSTS: CEPIF Position */ +#define HSUSBD_GINTSTS_CEPIF_Msk (0x1ul << HSUSBD_GINTSTS_CEPIF_Pos) /*!< HSUSBD_T::GINTSTS: CEPIF Mask */ + +#define HSUSBD_GINTSTS_EPAIF_Pos (2) /*!< HSUSBD_T::GINTSTS: EPAIF Position */ +#define HSUSBD_GINTSTS_EPAIF_Msk (0x1ul << HSUSBD_GINTSTS_EPAIF_Pos) /*!< HSUSBD_T::GINTSTS: EPAIF Mask */ + +#define HSUSBD_GINTSTS_EPBIF_Pos (3) /*!< HSUSBD_T::GINTSTS: EPBIF Position */ +#define HSUSBD_GINTSTS_EPBIF_Msk (0x1ul << HSUSBD_GINTSTS_EPBIF_Pos) /*!< HSUSBD_T::GINTSTS: EPBIF Mask */ + +#define HSUSBD_GINTSTS_EPCIF_Pos (4) /*!< HSUSBD_T::GINTSTS: EPCIF Position */ +#define HSUSBD_GINTSTS_EPCIF_Msk (0x1ul << HSUSBD_GINTSTS_EPCIF_Pos) /*!< HSUSBD_T::GINTSTS: EPCIF Mask */ + +#define HSUSBD_GINTSTS_EPDIF_Pos (5) /*!< HSUSBD_T::GINTSTS: EPDIF Position */ +#define HSUSBD_GINTSTS_EPDIF_Msk (0x1ul << HSUSBD_GINTSTS_EPDIF_Pos) /*!< HSUSBD_T::GINTSTS: EPDIF Mask */ + +#define HSUSBD_GINTSTS_EPEIF_Pos (6) /*!< HSUSBD_T::GINTSTS: EPEIF Position */ +#define HSUSBD_GINTSTS_EPEIF_Msk (0x1ul << HSUSBD_GINTSTS_EPEIF_Pos) /*!< HSUSBD_T::GINTSTS: EPEIF Mask */ + +#define HSUSBD_GINTSTS_EPFIF_Pos (7) /*!< HSUSBD_T::GINTSTS: EPFIF Position */ +#define HSUSBD_GINTSTS_EPFIF_Msk (0x1ul << HSUSBD_GINTSTS_EPFIF_Pos) /*!< HSUSBD_T::GINTSTS: EPFIF Mask */ + +#define HSUSBD_GINTSTS_EPGIF_Pos (8) /*!< HSUSBD_T::GINTSTS: EPGIF Position */ +#define HSUSBD_GINTSTS_EPGIF_Msk (0x1ul << HSUSBD_GINTSTS_EPGIF_Pos) /*!< HSUSBD_T::GINTSTS: EPGIF Mask */ + +#define HSUSBD_GINTSTS_EPHIF_Pos (9) /*!< HSUSBD_T::GINTSTS: EPHIF Position */ +#define HSUSBD_GINTSTS_EPHIF_Msk (0x1ul << HSUSBD_GINTSTS_EPHIF_Pos) /*!< HSUSBD_T::GINTSTS: EPHIF Mask */ + +#define HSUSBD_GINTSTS_EPIIF_Pos (10) /*!< HSUSBD_T::GINTSTS: EPIIF Position */ +#define HSUSBD_GINTSTS_EPIIF_Msk (0x1ul << HSUSBD_GINTSTS_EPIIF_Pos) /*!< HSUSBD_T::GINTSTS: EPIIF Mask */ + +#define HSUSBD_GINTSTS_EPJIF_Pos (11) /*!< HSUSBD_T::GINTSTS: EPJIF Position */ +#define HSUSBD_GINTSTS_EPJIF_Msk (0x1ul << HSUSBD_GINTSTS_EPJIF_Pos) /*!< HSUSBD_T::GINTSTS: EPJIF Mask */ + +#define HSUSBD_GINTSTS_EPKIF_Pos (12) /*!< HSUSBD_T::GINTSTS: EPKIF Position */ +#define HSUSBD_GINTSTS_EPKIF_Msk (0x1ul << HSUSBD_GINTSTS_EPKIF_Pos) /*!< HSUSBD_T::GINTSTS: EPKIF Mask */ + +#define HSUSBD_GINTSTS_EPLIF_Pos (13) /*!< HSUSBD_T::GINTSTS: EPLIF Position */ +#define HSUSBD_GINTSTS_EPLIF_Msk (0x1ul << HSUSBD_GINTSTS_EPLIF_Pos) /*!< HSUSBD_T::GINTSTS: EPLIF Mask */ + +#define HSUSBD_GINTEN_USBIEN_Pos (0) /*!< HSUSBD_T::GINTEN: USBIEN Position */ +#define HSUSBD_GINTEN_USBIEN_Msk (0x1ul << HSUSBD_GINTEN_USBIEN_Pos) /*!< HSUSBD_T::GINTEN: USBIEN Mask */ + +#define HSUSBD_GINTEN_CEPIEN_Pos (1) /*!< HSUSBD_T::GINTEN: CEPIEN Position */ +#define HSUSBD_GINTEN_CEPIEN_Msk (0x1ul << HSUSBD_GINTEN_CEPIEN_Pos) /*!< HSUSBD_T::GINTEN: CEPIEN Mask */ + +#define HSUSBD_GINTEN_EPAIEN_Pos (2) /*!< HSUSBD_T::GINTEN: EPAIEN Position */ +#define HSUSBD_GINTEN_EPAIEN_Msk (0x1ul << HSUSBD_GINTEN_EPAIEN_Pos) /*!< HSUSBD_T::GINTEN: EPAIEN Mask */ + +#define HSUSBD_GINTEN_EPBIEN_Pos (3) /*!< HSUSBD_T::GINTEN: EPBIEN Position */ +#define HSUSBD_GINTEN_EPBIEN_Msk (0x1ul << HSUSBD_GINTEN_EPBIEN_Pos) /*!< HSUSBD_T::GINTEN: EPBIEN Mask */ + +#define HSUSBD_GINTEN_EPCIEN_Pos (4) /*!< HSUSBD_T::GINTEN: EPCIEN Position */ +#define HSUSBD_GINTEN_EPCIEN_Msk (0x1ul << HSUSBD_GINTEN_EPCIEN_Pos) /*!< HSUSBD_T::GINTEN: EPCIEN Mask */ + +#define HSUSBD_GINTEN_EPDIEN_Pos (5) /*!< HSUSBD_T::GINTEN: EPDIEN Position */ +#define HSUSBD_GINTEN_EPDIEN_Msk (0x1ul << HSUSBD_GINTEN_EPDIEN_Pos) /*!< HSUSBD_T::GINTEN: EPDIEN Mask */ + +#define HSUSBD_GINTEN_EPEIEN_Pos (6) /*!< HSUSBD_T::GINTEN: EPEIEN Position */ +#define HSUSBD_GINTEN_EPEIEN_Msk (0x1ul << HSUSBD_GINTEN_EPEIEN_Pos) /*!< HSUSBD_T::GINTEN: EPEIEN Mask */ + +#define HSUSBD_GINTEN_EPFIEN_Pos (7) /*!< HSUSBD_T::GINTEN: EPFIEN Position */ +#define HSUSBD_GINTEN_EPFIEN_Msk (0x1ul << HSUSBD_GINTEN_EPFIEN_Pos) /*!< HSUSBD_T::GINTEN: EPFIEN Mask */ + +#define HSUSBD_GINTEN_EPGIEN_Pos (8) /*!< HSUSBD_T::GINTEN: EPGIEN Position */ +#define HSUSBD_GINTEN_EPGIEN_Msk (0x1ul << HSUSBD_GINTEN_EPGIEN_Pos) /*!< HSUSBD_T::GINTEN: EPGIEN Mask */ + +#define HSUSBD_GINTEN_EPHIEN_Pos (9) /*!< HSUSBD_T::GINTEN: EPHIEN Position */ +#define HSUSBD_GINTEN_EPHIEN_Msk (0x1ul << HSUSBD_GINTEN_EPHIEN_Pos) /*!< HSUSBD_T::GINTEN: EPHIEN Mask */ + +#define HSUSBD_GINTEN_EPIIEN_Pos (10) /*!< HSUSBD_T::GINTEN: EPIIEN Position */ +#define HSUSBD_GINTEN_EPIIEN_Msk (0x1ul << HSUSBD_GINTEN_EPIIEN_Pos) /*!< HSUSBD_T::GINTEN: EPIIEN Mask */ + +#define HSUSBD_GINTEN_EPJIEN_Pos (11) /*!< HSUSBD_T::GINTEN: EPJIEN Position */ +#define HSUSBD_GINTEN_EPJIEN_Msk (0x1ul << HSUSBD_GINTEN_EPJIEN_Pos) /*!< HSUSBD_T::GINTEN: EPJIEN Mask */ + +#define HSUSBD_GINTEN_EPKIEN_Pos (12) /*!< HSUSBD_T::GINTEN: EPKIEN Position */ +#define HSUSBD_GINTEN_EPKIEN_Msk (0x1ul << HSUSBD_GINTEN_EPKIEN_Pos) /*!< HSUSBD_T::GINTEN: EPKIEN Mask */ + +#define HSUSBD_GINTEN_EPLIEN_Pos (13) /*!< HSUSBD_T::GINTEN: EPLIEN Position */ +#define HSUSBD_GINTEN_EPLIEN_Msk (0x1ul << HSUSBD_GINTEN_EPLIEN_Pos) /*!< HSUSBD_T::GINTEN: EPLIEN Mask */ + +#define HSUSBD_BUSINTSTS_SOFIF_Pos (0) /*!< HSUSBD_T::BUSINTSTS: SOFIF Position */ +#define HSUSBD_BUSINTSTS_SOFIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SOFIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SOFIF Mask */ + +#define HSUSBD_BUSINTSTS_RSTIF_Pos (1) /*!< HSUSBD_T::BUSINTSTS: RSTIF Position */ +#define HSUSBD_BUSINTSTS_RSTIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RSTIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RSTIF Mask */ + +#define HSUSBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Position */ +#define HSUSBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_RESUMEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: RESUMEIF Mask */ + +#define HSUSBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Position*/ +#define HSUSBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_SUSPENDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: SUSPENDIF Mask */ + +#define HSUSBD_BUSINTSTS_HISPDIF_Pos (4) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Position */ +#define HSUSBD_BUSINTSTS_HISPDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_HISPDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: HISPDIF Mask */ + +#define HSUSBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Position*/ +#define HSUSBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << HSUSBD_BUSINTSTS_DMADONEIF_Pos) /*!< HSUSBD_T::BUSINTSTS: DMADONEIF Mask */ + +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Position*/ +#define HSUSBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << HSUSBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< HSUSBD_T::BUSINTSTS: PHYCLKVLDIF Mask */ + +#define HSUSBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Position*/ +#define HSUSBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << HSUSBD_BUSINTSTS_VBUSDETIF_Pos) /*!< HSUSBD_T::BUSINTSTS: VBUSDETIF Mask */ + +#define HSUSBD_BUSINTSTS_LPMTKNIF_Pos (9) /*!< HSUSBD_T::BUSINTSTS: LPMTKNIF Position */ +#define HSUSBD_BUSINTSTS_LPMTKNIF_Msk (0x1ul << HSUSBD_BUSINTSTS_LPMTKNIF_Pos) /*!< HSUSBD_T::BUSINTSTS: LPMTKNIF Mask */ + +#define HSUSBD_BUSINTEN_SOFIEN_Pos (0) /*!< HSUSBD_T::BUSINTEN: SOFIEN Position */ +#define HSUSBD_BUSINTEN_SOFIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SOFIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SOFIEN Mask */ + +#define HSUSBD_BUSINTEN_RSTIEN_Pos (1) /*!< HSUSBD_T::BUSINTEN: RSTIEN Position */ +#define HSUSBD_BUSINTEN_RSTIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RSTIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RSTIEN Mask */ + +#define HSUSBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Position */ +#define HSUSBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_RESUMEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: RESUMEIEN Mask */ + +#define HSUSBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Position*/ +#define HSUSBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_SUSPENDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: SUSPENDIEN Mask */ + +#define HSUSBD_BUSINTEN_HISPDIEN_Pos (4) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Position */ +#define HSUSBD_BUSINTEN_HISPDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_HISPDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: HISPDIEN Mask */ + +#define HSUSBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Position*/ +#define HSUSBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << HSUSBD_BUSINTEN_DMADONEIEN_Pos) /*!< HSUSBD_T::BUSINTEN: DMADONEIEN Mask */ + +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Position*/ +#define HSUSBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << HSUSBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< HSUSBD_T::BUSINTEN: PHYCLKVLDIEN Mask */ + +#define HSUSBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Position*/ +#define HSUSBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << HSUSBD_BUSINTEN_VBUSDETIEN_Pos) /*!< HSUSBD_T::BUSINTEN: VBUSDETIEN Mask */ + +#define HSUSBD_BUSINTEN_LPMTKNIEN_Pos (9) /*!< HSUSBD_T::BUSINTEN: LPMTKNIEN Position */ +#define HSUSBD_BUSINTEN_LPMTKNIEN_Msk (0x1ul << HSUSBD_BUSINTEN_LPMTKNIEN_Pos) /*!< HSUSBD_T::BUSINTEN: LPMTKNIEN Mask */ + +#define HSUSBD_OPER_RESUMEEN_Pos (0) /*!< HSUSBD_T::OPER: RESUMEEN Position */ +#define HSUSBD_OPER_RESUMEEN_Msk (0x1ul << HSUSBD_OPER_RESUMEEN_Pos) /*!< HSUSBD_T::OPER: RESUMEEN Mask */ + +#define HSUSBD_OPER_HISPDEN_Pos (1) /*!< HSUSBD_T::OPER: HISPDEN Position */ +#define HSUSBD_OPER_HISPDEN_Msk (0x1ul << HSUSBD_OPER_HISPDEN_Pos) /*!< HSUSBD_T::OPER: HISPDEN Mask */ + +#define HSUSBD_OPER_CURSPD_Pos (2) /*!< HSUSBD_T::OPER: CURSPD Position */ +#define HSUSBD_OPER_CURSPD_Msk (0x1ul << HSUSBD_OPER_CURSPD_Pos) /*!< HSUSBD_T::OPER: CURSPD Mask */ + +#define HSUSBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Position */ +#define HSUSBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << HSUSBD_FRAMECNT_MFRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: MFRAMECNT Mask */ + +#define HSUSBD_FRAMECNT_FRAMECNT_Pos (3) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Position */ +#define HSUSBD_FRAMECNT_FRAMECNT_Msk (0x7fful << HSUSBD_FRAMECNT_FRAMECNT_Pos) /*!< HSUSBD_T::FRAMECNT: FRAMECNT Mask */ + +#define HSUSBD_FADDR_FADDR_Pos (0) /*!< HSUSBD_T::FADDR: FADDR Position */ +#define HSUSBD_FADDR_FADDR_Msk (0x7ful << HSUSBD_FADDR_FADDR_Pos) /*!< HSUSBD_T::FADDR: FADDR Mask */ + +#define HSUSBD_TEST_TESTMODE_Pos (0) /*!< HSUSBD_T::TEST: TESTMODE Position */ +#define HSUSBD_TEST_TESTMODE_Msk (0x7ul << HSUSBD_TEST_TESTMODE_Pos) /*!< HSUSBD_T::TEST: TESTMODE Mask */ + +#define HSUSBD_CEPDAT_DAT_Pos (0) /*!< HSUSBD_T::CEPDAT: DAT Position */ +#define HSUSBD_CEPDAT_DAT_Msk (0xfffffffful << HSUSBD_CEPDAT_DAT_Pos) /*!< HSUSBD_T::CEPDAT: DAT Mask */ + +#define HSUSBD_CEPCTL_NAKCLR_Pos (0) /*!< HSUSBD_T::CEPCTL: NAKCLR Position */ +#define HSUSBD_CEPCTL_NAKCLR_Msk (0x1ul << HSUSBD_CEPCTL_NAKCLR_Pos) /*!< HSUSBD_T::CEPCTL: NAKCLR Mask */ + +#define HSUSBD_CEPCTL_STALLEN_Pos (1) /*!< HSUSBD_T::CEPCTL: STALLEN Position */ +#define HSUSBD_CEPCTL_STALLEN_Msk (0x1ul << HSUSBD_CEPCTL_STALLEN_Pos) /*!< HSUSBD_T::CEPCTL: STALLEN Mask */ + +#define HSUSBD_CEPCTL_ZEROLEN_Pos (2) /*!< HSUSBD_T::CEPCTL: ZEROLEN Position */ +#define HSUSBD_CEPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_CEPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::CEPCTL: ZEROLEN Mask */ + +#define HSUSBD_CEPCTL_FLUSH_Pos (3) /*!< HSUSBD_T::CEPCTL: FLUSH Position */ +#define HSUSBD_CEPCTL_FLUSH_Msk (0x1ul << HSUSBD_CEPCTL_FLUSH_Pos) /*!< HSUSBD_T::CEPCTL: FLUSH Mask */ + +#define HSUSBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPTKIEN Mask */ + +#define HSUSBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Position*/ +#define HSUSBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_SETUPPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: SETUPPKIEN Mask */ + +#define HSUSBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Position */ +#define HSUSBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_CEPINTEN_INTKIEN_Pos (3) /*!< HSUSBD_T::CEPINTEN: INTKIEN Position */ +#define HSUSBD_CEPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: INTKIEN Mask */ + +#define HSUSBD_CEPINTEN_PINGIEN_Pos (4) /*!< HSUSBD_T::CEPINTEN: PINGIEN Position */ +#define HSUSBD_CEPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_CEPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::CEPINTEN: PINGIEN Mask */ + +#define HSUSBD_CEPINTEN_TXPKIEN_Pos (5) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Position */ +#define HSUSBD_CEPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: TXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_RXPKIEN_Pos (6) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Position */ +#define HSUSBD_CEPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: RXPKIEN Mask */ + +#define HSUSBD_CEPINTEN_NAKIEN_Pos (7) /*!< HSUSBD_T::CEPINTEN: NAKIEN Position */ +#define HSUSBD_CEPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_CEPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::CEPINTEN: NAKIEN Mask */ + +#define HSUSBD_CEPINTEN_STALLIEN_Pos (8) /*!< HSUSBD_T::CEPINTEN: STALLIEN Position */ +#define HSUSBD_CEPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STALLIEN Mask */ + +#define HSUSBD_CEPINTEN_ERRIEN_Pos (9) /*!< HSUSBD_T::CEPINTEN: ERRIEN Position */ +#define HSUSBD_CEPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_CEPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::CEPINTEN: ERRIEN Mask */ + +#define HSUSBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Position*/ +#define HSUSBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << HSUSBD_CEPINTEN_STSDONEIEN_Pos) /*!< HSUSBD_T::CEPINTEN: STSDONEIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Position*/ +#define HSUSBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::CEPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPTKIF Mask */ + +#define HSUSBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Position*/ +#define HSUSBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_SETUPPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: SETUPPKIF Mask */ + +#define HSUSBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Position */ +#define HSUSBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_CEPINTSTS_INTKIF_Pos (3) /*!< HSUSBD_T::CEPINTSTS: INTKIF Position */ +#define HSUSBD_CEPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: INTKIF Mask */ + +#define HSUSBD_CEPINTSTS_PINGIF_Pos (4) /*!< HSUSBD_T::CEPINTSTS: PINGIF Position */ +#define HSUSBD_CEPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_CEPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::CEPINTSTS: PINGIF Mask */ + +#define HSUSBD_CEPINTSTS_TXPKIF_Pos (5) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Position */ +#define HSUSBD_CEPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: TXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_RXPKIF_Pos (6) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Position */ +#define HSUSBD_CEPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: RXPKIF Mask */ + +#define HSUSBD_CEPINTSTS_NAKIF_Pos (7) /*!< HSUSBD_T::CEPINTSTS: NAKIF Position */ +#define HSUSBD_CEPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_CEPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::CEPINTSTS: NAKIF Mask */ + +#define HSUSBD_CEPINTSTS_STALLIF_Pos (8) /*!< HSUSBD_T::CEPINTSTS: STALLIF Position */ +#define HSUSBD_CEPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STALLIF Mask */ + +#define HSUSBD_CEPINTSTS_ERRIF_Pos (9) /*!< HSUSBD_T::CEPINTSTS: ERRIF Position */ +#define HSUSBD_CEPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_CEPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::CEPINTSTS: ERRIF Mask */ + +#define HSUSBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Position*/ +#define HSUSBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << HSUSBD_CEPINTSTS_STSDONEIF_Pos) /*!< HSUSBD_T::CEPINTSTS: STSDONEIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Position*/ +#define HSUSBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::CEPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_CEPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::CEPTXCNT: TXCNT Position */ +#define HSUSBD_CEPTXCNT_TXCNT_Msk (0xfful << HSUSBD_CEPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::CEPTXCNT: TXCNT Mask */ + +#define HSUSBD_CEPRXCNT_RXCNT_Pos (0) /*!< HSUSBD_T::CEPRXCNT: RXCNT Position */ +#define HSUSBD_CEPRXCNT_RXCNT_Msk (0xfful << HSUSBD_CEPRXCNT_RXCNT_Pos) /*!< HSUSBD_T::CEPRXCNT: RXCNT Mask */ + +#define HSUSBD_CEPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::CEPDATCNT: DATCNT Position */ +#define HSUSBD_CEPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_CEPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::CEPDATCNT: DATCNT Mask */ + +#define HSUSBD_SETUP1_0_SETUP0_Pos (0) /*!< HSUSBD_T::SETUP1_0: SETUP0 Position */ +#define HSUSBD_SETUP1_0_SETUP0_Msk (0xfful << HSUSBD_SETUP1_0_SETUP0_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP0 Mask */ + +#define HSUSBD_SETUP1_0_SETUP1_Pos (8) /*!< HSUSBD_T::SETUP1_0: SETUP1 Position */ +#define HSUSBD_SETUP1_0_SETUP1_Msk (0xfful << HSUSBD_SETUP1_0_SETUP1_Pos) /*!< HSUSBD_T::SETUP1_0: SETUP1 Mask */ + +#define HSUSBD_SETUP3_2_SETUP2_Pos (0) /*!< HSUSBD_T::SETUP3_2: SETUP2 Position */ +#define HSUSBD_SETUP3_2_SETUP2_Msk (0xfful << HSUSBD_SETUP3_2_SETUP2_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP2 Mask */ + +#define HSUSBD_SETUP3_2_SETUP3_Pos (8) /*!< HSUSBD_T::SETUP3_2: SETUP3 Position */ +#define HSUSBD_SETUP3_2_SETUP3_Msk (0xfful << HSUSBD_SETUP3_2_SETUP3_Pos) /*!< HSUSBD_T::SETUP3_2: SETUP3 Mask */ + +#define HSUSBD_SETUP5_4_SETUP4_Pos (0) /*!< HSUSBD_T::SETUP5_4: SETUP4 Position */ +#define HSUSBD_SETUP5_4_SETUP4_Msk (0xfful << HSUSBD_SETUP5_4_SETUP4_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP4 Mask */ + +#define HSUSBD_SETUP5_4_SETUP5_Pos (8) /*!< HSUSBD_T::SETUP5_4: SETUP5 Position */ +#define HSUSBD_SETUP5_4_SETUP5_Msk (0xfful << HSUSBD_SETUP5_4_SETUP5_Pos) /*!< HSUSBD_T::SETUP5_4: SETUP5 Mask */ + +#define HSUSBD_SETUP7_6_SETUP6_Pos (0) /*!< HSUSBD_T::SETUP7_6: SETUP6 Position */ +#define HSUSBD_SETUP7_6_SETUP6_Msk (0xfful << HSUSBD_SETUP7_6_SETUP6_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP6 Mask */ + +#define HSUSBD_SETUP7_6_SETUP7_Pos (8) /*!< HSUSBD_T::SETUP7_6: SETUP7 Position */ +#define HSUSBD_SETUP7_6_SETUP7_Msk (0xfful << HSUSBD_SETUP7_6_SETUP7_Pos) /*!< HSUSBD_T::SETUP7_6: SETUP7 Mask */ + +#define HSUSBD_CEPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::CEPBUFST: SADDR Position */ +#define HSUSBD_CEPBUFST_SADDR_Msk (0xffful << HSUSBD_CEPBUFST_SADDR_Pos) /*!< HSUSBD_T::CEPBUFST: SADDR Mask */ + +#define HSUSBD_CEPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::CEPBUFEND: EADDR Position */ +#define HSUSBD_CEPBUFEND_EADDR_Msk (0xffful << HSUSBD_CEPBUFEND_EADDR_Pos) /*!< HSUSBD_T::CEPBUFEND: EADDR Mask */ + +#define HSUSBD_DMACTL_EPNUM_Pos (0) /*!< HSUSBD_T::DMACTL: EPNUM Position */ +#define HSUSBD_DMACTL_EPNUM_Msk (0xful << HSUSBD_DMACTL_EPNUM_Pos) /*!< HSUSBD_T::DMACTL: EPNUM Mask */ + +#define HSUSBD_DMACTL_DMARD_Pos (4) /*!< HSUSBD_T::DMACTL: DMARD Position */ +#define HSUSBD_DMACTL_DMARD_Msk (0x1ul << HSUSBD_DMACTL_DMARD_Pos) /*!< HSUSBD_T::DMACTL: DMARD Mask */ + +#define HSUSBD_DMACTL_DMAEN_Pos (5) /*!< HSUSBD_T::DMACTL: DMAEN Position */ +#define HSUSBD_DMACTL_DMAEN_Msk (0x1ul << HSUSBD_DMACTL_DMAEN_Pos) /*!< HSUSBD_T::DMACTL: DMAEN Mask */ + +#define HSUSBD_DMACTL_SGEN_Pos (6) /*!< HSUSBD_T::DMACTL: SGEN Position */ +#define HSUSBD_DMACTL_SGEN_Msk (0x1ul << HSUSBD_DMACTL_SGEN_Pos) /*!< HSUSBD_T::DMACTL: SGEN Mask */ + +#define HSUSBD_DMACTL_DMARST_Pos (7) /*!< HSUSBD_T::DMACTL: DMARST Position */ +#define HSUSBD_DMACTL_DMARST_Msk (0x1ul << HSUSBD_DMACTL_DMARST_Pos) /*!< HSUSBD_T::DMACTL: DMARST Mask */ + +#define HSUSBD_DMACTL_SVINEP_Pos (8) /*!< HSUSBD_T::DMACTL: SVINEP Position */ +#define HSUSBD_DMACTL_SVINEP_Msk (0x1ul << HSUSBD_DMACTL_SVINEP_Pos) /*!< HSUSBD_T::DMACTL: SVINEP Mask */ + +#define HSUSBD_DMACNT_DMACNT_Pos (0) /*!< HSUSBD_T::DMACNT: DMACNT Position */ +#define HSUSBD_DMACNT_DMACNT_Msk (0xffffful << HSUSBD_DMACNT_DMACNT_Pos) /*!< HSUSBD_T::DMACNT: DMACNT Mask */ + +#define HSUSBD_EPDAT_EPDAT_Pos (0) /*!< HSUSBD_T::EPDAT: EPDAT Position */ +#define HSUSBD_EPDAT_EPDAT_Msk (0xfffffffful << HSUSBD_EPDAT_EPDAT_Pos) /*!< HSUSBD_T::EPDAT: EPDAT Mask */ + +#define HSUSBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Position */ +#define HSUSBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFFULLIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFFULLIF Mask */ + +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Position*/ +#define HSUSBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << HSUSBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< HSUSBD_T::EPINTSTS: BUFEMPTYIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Position */ +#define HSUSBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTTXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTTXIF Mask */ + +#define HSUSBD_EPINTSTS_TXPKIF_Pos (3) /*!< HSUSBD_T::EPINTSTS: TXPKIF Position */ +#define HSUSBD_EPINTSTS_TXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_TXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: TXPKIF Mask */ + +#define HSUSBD_EPINTSTS_RXPKIF_Pos (4) /*!< HSUSBD_T::EPINTSTS: RXPKIF Position */ +#define HSUSBD_EPINTSTS_RXPKIF_Msk (0x1ul << HSUSBD_EPINTSTS_RXPKIF_Pos) /*!< HSUSBD_T::EPINTSTS: RXPKIF Mask */ + +#define HSUSBD_EPINTSTS_OUTTKIF_Pos (5) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Position */ +#define HSUSBD_EPINTSTS_OUTTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_OUTTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: OUTTKIF Mask */ + +#define HSUSBD_EPINTSTS_INTKIF_Pos (6) /*!< HSUSBD_T::EPINTSTS: INTKIF Position */ +#define HSUSBD_EPINTSTS_INTKIF_Msk (0x1ul << HSUSBD_EPINTSTS_INTKIF_Pos) /*!< HSUSBD_T::EPINTSTS: INTKIF Mask */ + +#define HSUSBD_EPINTSTS_PINGIF_Pos (7) /*!< HSUSBD_T::EPINTSTS: PINGIF Position */ +#define HSUSBD_EPINTSTS_PINGIF_Msk (0x1ul << HSUSBD_EPINTSTS_PINGIF_Pos) /*!< HSUSBD_T::EPINTSTS: PINGIF Mask */ + +#define HSUSBD_EPINTSTS_NAKIF_Pos (8) /*!< HSUSBD_T::EPINTSTS: NAKIF Position */ +#define HSUSBD_EPINTSTS_NAKIF_Msk (0x1ul << HSUSBD_EPINTSTS_NAKIF_Pos) /*!< HSUSBD_T::EPINTSTS: NAKIF Mask */ + +#define HSUSBD_EPINTSTS_STALLIF_Pos (9) /*!< HSUSBD_T::EPINTSTS: STALLIF Position */ +#define HSUSBD_EPINTSTS_STALLIF_Msk (0x1ul << HSUSBD_EPINTSTS_STALLIF_Pos) /*!< HSUSBD_T::EPINTSTS: STALLIF Mask */ + +#define HSUSBD_EPINTSTS_NYETIF_Pos (10) /*!< HSUSBD_T::EPINTSTS: NYETIF Position */ +#define HSUSBD_EPINTSTS_NYETIF_Msk (0x1ul << HSUSBD_EPINTSTS_NYETIF_Pos) /*!< HSUSBD_T::EPINTSTS: NYETIF Mask */ + +#define HSUSBD_EPINTSTS_ERRIF_Pos (11) /*!< HSUSBD_T::EPINTSTS: ERRIF Position */ +#define HSUSBD_EPINTSTS_ERRIF_Msk (0x1ul << HSUSBD_EPINTSTS_ERRIF_Pos) /*!< HSUSBD_T::EPINTSTS: ERRIF Mask */ + +#define HSUSBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Position */ +#define HSUSBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << HSUSBD_EPINTSTS_SHORTRXIF_Pos) /*!< HSUSBD_T::EPINTSTS: SHORTRXIF Mask */ + +#define HSUSBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Position */ +#define HSUSBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFFULLIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFFULLIEN Mask */ + +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Position*/ +#define HSUSBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << HSUSBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< HSUSBD_T::EPINTEN: BUFEMPTYIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Position */ +#define HSUSBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTTXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTTXIEN Mask */ + +#define HSUSBD_EPINTEN_TXPKIEN_Pos (3) /*!< HSUSBD_T::EPINTEN: TXPKIEN Position */ +#define HSUSBD_EPINTEN_TXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_TXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: TXPKIEN Mask */ + +#define HSUSBD_EPINTEN_RXPKIEN_Pos (4) /*!< HSUSBD_T::EPINTEN: RXPKIEN Position */ +#define HSUSBD_EPINTEN_RXPKIEN_Msk (0x1ul << HSUSBD_EPINTEN_RXPKIEN_Pos) /*!< HSUSBD_T::EPINTEN: RXPKIEN Mask */ + +#define HSUSBD_EPINTEN_OUTTKIEN_Pos (5) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Position */ +#define HSUSBD_EPINTEN_OUTTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_OUTTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: OUTTKIEN Mask */ + +#define HSUSBD_EPINTEN_INTKIEN_Pos (6) /*!< HSUSBD_T::EPINTEN: INTKIEN Position */ +#define HSUSBD_EPINTEN_INTKIEN_Msk (0x1ul << HSUSBD_EPINTEN_INTKIEN_Pos) /*!< HSUSBD_T::EPINTEN: INTKIEN Mask */ + +#define HSUSBD_EPINTEN_PINGIEN_Pos (7) /*!< HSUSBD_T::EPINTEN: PINGIEN Position */ +#define HSUSBD_EPINTEN_PINGIEN_Msk (0x1ul << HSUSBD_EPINTEN_PINGIEN_Pos) /*!< HSUSBD_T::EPINTEN: PINGIEN Mask */ + +#define HSUSBD_EPINTEN_NAKIEN_Pos (8) /*!< HSUSBD_T::EPINTEN: NAKIEN Position */ +#define HSUSBD_EPINTEN_NAKIEN_Msk (0x1ul << HSUSBD_EPINTEN_NAKIEN_Pos) /*!< HSUSBD_T::EPINTEN: NAKIEN Mask */ + +#define HSUSBD_EPINTEN_STALLIEN_Pos (9) /*!< HSUSBD_T::EPINTEN: STALLIEN Position */ +#define HSUSBD_EPINTEN_STALLIEN_Msk (0x1ul << HSUSBD_EPINTEN_STALLIEN_Pos) /*!< HSUSBD_T::EPINTEN: STALLIEN Mask */ + +#define HSUSBD_EPINTEN_NYETIEN_Pos (10) /*!< HSUSBD_T::EPINTEN: NYETIEN Position */ +#define HSUSBD_EPINTEN_NYETIEN_Msk (0x1ul << HSUSBD_EPINTEN_NYETIEN_Pos) /*!< HSUSBD_T::EPINTEN: NYETIEN Mask */ + +#define HSUSBD_EPINTEN_ERRIEN_Pos (11) /*!< HSUSBD_T::EPINTEN: ERRIEN Position */ +#define HSUSBD_EPINTEN_ERRIEN_Msk (0x1ul << HSUSBD_EPINTEN_ERRIEN_Pos) /*!< HSUSBD_T::EPINTEN: ERRIEN Mask */ + +#define HSUSBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Position */ +#define HSUSBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << HSUSBD_EPINTEN_SHORTRXIEN_Pos) /*!< HSUSBD_T::EPINTEN: SHORTRXIEN Mask */ + +#define HSUSBD_EPDATCNT_DATCNT_Pos (0) /*!< HSUSBD_T::EPDATCNT: DATCNT Position */ +#define HSUSBD_EPDATCNT_DATCNT_Msk (0xfffful << HSUSBD_EPDATCNT_DATCNT_Pos) /*!< HSUSBD_T::EPDATCNT: DATCNT Mask */ + +#define HSUSBD_EPDATCNT_DMALOOP_Pos (16) /*!< HSUSBD_T::EPDATCNT: DMALOOP Position */ +#define HSUSBD_EPDATCNT_DMALOOP_Msk (0x7ffful << HSUSBD_EPDATCNT_DMALOOP_Pos) /*!< HSUSBD_T::EPDATCNT: DMALOOP Mask */ + +#define HSUSBD_EPRSPCTL_FLUSH_Pos (0) /*!< HSUSBD_T::EPRSPCTL: FLUSH Position */ +#define HSUSBD_EPRSPCTL_FLUSH_Msk (0x1ul << HSUSBD_EPRSPCTL_FLUSH_Pos) /*!< HSUSBD_T::EPRSPCTL: FLUSH Mask */ + +#define HSUSBD_EPRSPCTL_MODE_Pos (1) /*!< HSUSBD_T::EPRSPCTL: MODE Position */ +#define HSUSBD_EPRSPCTL_MODE_Msk (0x3ul << HSUSBD_EPRSPCTL_MODE_Pos) /*!< HSUSBD_T::EPRSPCTL: MODE Mask */ + +#define HSUSBD_EPRSPCTL_TOGGLE_Pos (3) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Position */ +#define HSUSBD_EPRSPCTL_TOGGLE_Msk (0x1ul << HSUSBD_EPRSPCTL_TOGGLE_Pos) /*!< HSUSBD_T::EPRSPCTL: TOGGLE Mask */ + +#define HSUSBD_EPRSPCTL_HALT_Pos (4) /*!< HSUSBD_T::EPRSPCTL: HALT Position */ +#define HSUSBD_EPRSPCTL_HALT_Msk (0x1ul << HSUSBD_EPRSPCTL_HALT_Pos) /*!< HSUSBD_T::EPRSPCTL: HALT Mask */ + +#define HSUSBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Position */ +#define HSUSBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << HSUSBD_EPRSPCTL_ZEROLEN_Pos) /*!< HSUSBD_T::EPRSPCTL: ZEROLEN Mask */ + +#define HSUSBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Position */ +#define HSUSBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << HSUSBD_EPRSPCTL_SHORTTXEN_Pos) /*!< HSUSBD_T::EPRSPCTL: SHORTTXEN Mask */ + +#define HSUSBD_EPRSPCTL_DISBUF_Pos (7) /*!< HSUSBD_T::EPRSPCTL: DISBUF Position */ +#define HSUSBD_EPRSPCTL_DISBUF_Msk (0x1ul << HSUSBD_EPRSPCTL_DISBUF_Pos) /*!< HSUSBD_T::EPRSPCTL: DISBUF Mask */ + +#define HSUSBD_EPMPS_EPMPS_Pos (0) /*!< HSUSBD_T::EPMPS: EPMPS Position */ +#define HSUSBD_EPMPS_EPMPS_Msk (0x7fful << HSUSBD_EPMPS_EPMPS_Pos) /*!< HSUSBD_T::EPMPS: EPMPS Mask */ + +#define HSUSBD_EPTXCNT_TXCNT_Pos (0) /*!< HSUSBD_T::EPTXCNT: TXCNT Position */ +#define HSUSBD_EPTXCNT_TXCNT_Msk (0x7fful << HSUSBD_EPTXCNT_TXCNT_Pos) /*!< HSUSBD_T::EPTXCNT: TXCNT Mask */ + +#define HSUSBD_EPCFG_EPEN_Pos (0) /*!< HSUSBD_T::EPCFG: EPEN Position */ +#define HSUSBD_EPCFG_EPEN_Msk (0x1ul << HSUSBD_EPCFG_EPEN_Pos) /*!< HSUSBD_T::EPCFG: EPEN Mask */ + +#define HSUSBD_EPCFG_EPTYPE_Pos (1) /*!< HSUSBD_T::EPCFG: EPTYPE Position */ +#define HSUSBD_EPCFG_EPTYPE_Msk (0x3ul << HSUSBD_EPCFG_EPTYPE_Pos) /*!< HSUSBD_T::EPCFG: EPTYPE Mask */ + +#define HSUSBD_EPCFG_EPDIR_Pos (3) /*!< HSUSBD_T::EPCFG: EPDIR Position */ +#define HSUSBD_EPCFG_EPDIR_Msk (0x1ul << HSUSBD_EPCFG_EPDIR_Pos) /*!< HSUSBD_T::EPCFG: EPDIR Mask */ + +#define HSUSBD_EPCFG_EPNUM_Pos (4) /*!< HSUSBD_T::EPCFG: EPNUM Position */ +#define HSUSBD_EPCFG_EPNUM_Msk (0xful << HSUSBD_EPCFG_EPNUM_Pos) /*!< HSUSBD_T::EPCFG: EPNUM Mask */ + +#define HSUSBD_EPBUFST_SADDR_Pos (0) /*!< HSUSBD_T::EPBUFST: SADDR Position */ +#define HSUSBD_EPBUFST_SADDR_Msk (0xffful << HSUSBD_EPBUFST_SADDR_Pos) /*!< HSUSBD_T::EPBUFST: SADDR Mask */ + +#define HSUSBD_EPBUFEND_EADDR_Pos (0) /*!< HSUSBD_T::EPBUFEND: EADDR Position */ +#define HSUSBD_EPBUFEND_EADDR_Msk (0xffful << HSUSBD_EPBUFEND_EADDR_Pos) /*!< HSUSBD_T::EPBUFEND: EADDR Mask */ + +#define HSUSBD_BCDC_BCDEN_Pos (0) /*!< HSUSBD_T::BCDC: BCDEN Position */ +#define HSUSBD_BCDC_BCDEN_Msk (0x1ul << HSUSBD_BCDC_BCDEN_Pos) /*!< HSUSBD_T::BCDC: BCDEN Mask */ + +#define HSUSBD_BCDC_DETMOD_Pos (1) /*!< HSUSBD_T::BCDC: DETMOD Position */ +#define HSUSBD_BCDC_DETMOD_Msk (0x7ul << HSUSBD_BCDC_DETMOD_Pos) /*!< HSUSBD_T::BCDC: DETMOD Mask */ + +#define HSUSBD_BCDC_DETSTS_Pos (4) /*!< HSUSBD_T::BCDC: DETSTS Position */ +#define HSUSBD_BCDC_DETSTS_Msk (0x1ul << HSUSBD_BCDC_DETSTS_Pos) /*!< HSUSBD_T::BCDC: DETSTS Mask */ + +#define HSUSBD_BCDC_USP_Pos (5) /*!< HSUSBD_T::BCDC: USP Position */ +#define HSUSBD_BCDC_USP_Msk (0x1ul << HSUSBD_BCDC_USP_Pos) /*!< HSUSBD_T::BCDC: USP Mask */ + +#define HSUSBD_BCDC_BCDIEN_Pos (30) /*!< HSUSBD_T::BCDC: BCDIEN Position */ +#define HSUSBD_BCDC_BCDIEN_Msk (0x1ul << HSUSBD_BCDC_BCDIEN_Pos) /*!< HSUSBD_T::BCDC: BCDIEN Mask */ + +#define HSUSBD_BCDC_BCDIF_Pos (31) /*!< HSUSBD_T::BCDC: BCDIF Position */ +#define HSUSBD_BCDC_BCDIF_Msk (0x1ul << HSUSBD_BCDC_BCDIF_Pos) /*!< HSUSBD_T::BCDC: BCDIF Mask */ + +#define HSUSBD_LPMCSR_LPMEN_Pos (12) /*!< HSUSBD_T::LPMCSR: LPMEN Position */ +#define HSUSBD_LPMCSR_LPMEN_Msk (0x1ul << HSUSBD_LPMCSR_LPMEN_Pos) /*!< HSUSBD_T::LPMCSR: LPMEN Mask */ + +#define HSUSBD_LPMCSR_LPMSLEEPEN_Pos (13) /*!< HSUSBD_T::LPMCSR: LPMSLEEPEN Position */ +#define HSUSBD_LPMCSR_LPMSLEEPEN_Msk (0x1ul << HSUSBD_LPMCSR_LPMSLEEPEN_Pos) /*!< HSUSBD_T::LPMCSR: LPMSLEEPEN Mask */ + +#define HSUSBD_LPMCSR_LPMSENDNYET_Pos (14) /*!< HSUSBD_T::LPMCSR: LPMSENDNYET Position */ +#define HSUSBD_LPMCSR_LPMSENDNYET_Msk (0x1ul << HSUSBD_LPMCSR_LPMSENDNYET_Pos) /*!< HSUSBD_T::LPMCSR: LPMSENDNYET Mask */ + +#define HSUSBD_DMAADDR_DMAADDR_Pos (0) /*!< HSUSBD_T::DMAADDR: DMAADDR Position */ +#define HSUSBD_DMAADDR_DMAADDR_Msk (0xfffffffful << HSUSBD_DMAADDR_DMAADDR_Pos) /*!< HSUSBD_T::DMAADDR: DMAADDR Mask */ + +#define HSUSBD_PHYCTL_DPPUEN_Pos (8) /*!< HSUSBD_T::PHYCTL: DPPUEN Position */ +#define HSUSBD_PHYCTL_DPPUEN_Msk (0x1ul << HSUSBD_PHYCTL_DPPUEN_Pos) /*!< HSUSBD_T::PHYCTL: DPPUEN Mask */ + +#define HSUSBD_PHYCTL_PHYEN_Pos (9) /*!< HSUSBD_T::PHYCTL: PHYEN Position */ +#define HSUSBD_PHYCTL_PHYEN_Msk (0x1ul << HSUSBD_PHYCTL_PHYEN_Pos) /*!< HSUSBD_T::PHYCTL: PHYEN Mask */ + +#define HSUSBD_PHYCTL_VBUSWKEN_Pos (24) /*!< HSUSBD_T::PHYCTL: VBUSWKEN Position */ +#define HSUSBD_PHYCTL_VBUSWKEN_Msk (0x1ul << HSUSBD_PHYCTL_VBUSWKEN_Pos) /*!< HSUSBD_T::PHYCTL: VBUSWKEN Mask */ + +#define HSUSBD_PHYCTL_LINESTATEWKEN_Pos (25) /*!< HSUSBD_T::PHYCTL: LINESTATEWKEN Position*/ +#define HSUSBD_PHYCTL_LINESTATEWKEN_Msk (0x1ul << HSUSBD_PHYCTL_LINESTATEWKEN_Pos) /*!< HSUSBD_T::PHYCTL: LINESTATEWKEN Mask */ + +#define HSUSBD_PHYCTL_STALLREVERT_Pos (26) /*!< HSUSBD_T::PHYCTL: STALLREVERT Position */ +#define HSUSBD_PHYCTL_STALLREVERT_Msk (0x1ul << HSUSBD_PHYCTL_STALLREVERT_Pos) /*!< HSUSBD_T::PHYCTL: STALLREVERT Mask */ + +#define HSUSBD_PHYCTL_PHYCLKSTB_Pos (27) /*!< HSUSBD_T::PHYCTL: PHYCLKSTB Position */ +#define HSUSBD_PHYCTL_PHYCLKSTB_Msk (0x1ul << HSUSBD_PHYCTL_PHYCLKSTB_Pos) /*!< HSUSBD_T::PHYCTL: PHYCLKSTB Mask */ + +#define HSUSBD_PHYCTL_VBUSDET_Pos (31) /*!< HSUSBD_T::PHYCTL: VBUSDET Position */ +#define HSUSBD_PHYCTL_VBUSDET_Msk (0x1ul << HSUSBD_PHYCTL_VBUSDET_Pos) /*!< HSUSBD_T::PHYCTL: VBUSDET Mask */ + +/**@}*/ /* HSUSBD_CONST */ +/**@}*/ /* end of HSUSBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBD_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsusbh_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsusbh_reg.h new file mode 100644 index 0000000..57cc5d0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/hsusbh_reg.h @@ -0,0 +1,653 @@ +/**************************************************************************//** + * @file hsusbh_reg.h + * @version V1.00 + * @brief HSUSBH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HSUSBH_REG_H__ +#define __HSUSBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup HSUSBH High Speed USB Host Controller (HSUSBH) + Memory Mapped Structure for HSUSBH Controller +@{ */ + +typedef struct +{ + + + /** + * @var HSUSBH_T::EHCVNR + * Offset: 0x00 EHCI Version Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CRLEN |Capability Registers Length + * | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space. + * |[31:16] |VERSION |Host Controller Interface Version Number + * | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller + * | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision. + * @var HSUSBH_T::EHCSPR + * Offset: 0x04 EHCI Structural Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |N_PORTS |Number of Physical Downstream Ports + * | | |This field specifies the number of physical downstream ports implemented on this host controller + * | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8) + * | | |Valid values are in the range of 1H to FH. + * | | |A zero in this field is undefined. + * |[4] |PPC |Port Power Control + * | | |This field indicates whether the host controller implementation includes port power control + * | | |A one in this bit indicates the ports have port power switches + * | | |A zero in this bit indicates the port do not have port power stitches + * | | |The value of this field affects the functionality of the Port Power field in each port status and control register. + * |[11:8] |N_PCC |Number of Ports Per Companion Controller + * | | |This field indicates the number of ports supported per companion host controller + * | | |It is used to indicate the port routing configuration to system software. + * | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3 + * | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc + * | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. + * | | |The number in this field must be consistent with N_PORTS and N_CC. + * |[15:12] |N_CC |Number of Companion Controller + * | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller. + * | | |A zero in this field indicates there are no companion host controllers + * | | |Port-ownership hand-off is not supported + * | | |Only high-speed devices are supported on the host controller root ports. + * | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s) + * | | |Port-ownership hand-offs are supported + * | | |High, Full- and Low-speed devices are supported on the host controller root ports. + * @var HSUSBH_T::EHCCPR + * Offset: 0x08 EHCI Capability Parameters Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AC64 |64-bit Addressing Capability + * | | |0 = Data structure using 32-bit address memory pointers. + * |[1] |PFLF |Programmable Frame List Flag + * | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller. + * |[2] |ASPC |Asynchronous Schedule Park Capability + * | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule. + * |[7:4] |IST |Isochronous Scheduling Threshold + * | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. + * | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. + * |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP) + * | | |0 = No extended capabilities are implemented. + * @var HSUSBH_T::UCMDR + * Offset: 0x20 USB Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RUN |Run/Stop (R/W) + * | | |When set to a 1, the Host Controller proceeds with execution of the schedule + * | | |The Host Controller continues execution as long as this bit is set to a 1 + * | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts + * | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit + * | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state + * | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e. + * | | |HCHalted in the USBSTS register is a one) + * | | |Doing so will yield undefined results. + * | | |0 = Stop. + * | | |1 = Run. + * |[1] |HCRST |Host Controller Reset (HCRESET) (R/W) + * | | |This control bit is used by software to reset the host controller + * | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset. + * | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc + * | | |to their initial value + * | | |Any transaction currently in progress on USB is immediately terminated + * | | |A USB reset is not driven on downstream ports. + * | | |All operational registers, including port registers and port state machines are set to their initial values + * | | |Port ownership reverts to the companion host controller(s), with the side effects + * | | |Software must reinitialize the host controller in order to return the host controller to an operational state. + * | | |This bit is set to zero by the Host Controller when the reset process is complete + * | | |Software cannot terminate the reset process early by writing a zero to this register. + * | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero + * | | |Attempting to reset an actively running host controller will result in undefined behavior. + * |[3:2] |FLSZ |Frame List Size (R/W or RO) + * | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one + * | | |This field specifies the size of the frame list + * | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index + * | | |Values mean: + * | | |00 = 1024 elements (4096 bytes) Default value. + * | | |01 = 512 elements (2048 bytes). + * | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment. + * | | |11 = Reserved. + * |[4] |PSEN |Periodic Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: + * | | |0 = Do not process the Periodic Schedule. + * | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. + * |[5] |ASEN |Asynchronous Schedule Enable (R/W) + * | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: + * | | |0 = Do not process the Asynchronous Schedule. + * | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + * |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W) + * | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule + * | | |Software must write a 1 to this bit to ring the doorbell. + * | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register + * | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. + * | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one. + * | | |Software should not write a one to this bit when the asynchronous schedule is disabled + * | | |Doing so will yield undefined results. + * |[23:16] |ITC |Interrupt Threshold Control (R/W) + * | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts + * | | |The only valid values are defined below + * | | |If software writes an invalid value to this register, the results are undefined + * | | |Value Maximum Interrupt Interval + * | | |0x00 = Reserved. + * | | |0x01 = 1 micro-frame. + * | | |0x02 = 2 micro-frames. + * | | |0x04 = 4 micro-frames. + * | | |0x08 = 8 micro-frames (default, equates to 1 ms). + * | | |0x10 = 16 micro-frames (2 ms). + * | | |0x20 = 32 micro-frames (4 ms). + * | | |0x40 = 64 micro-frames (8 ms). + * | | |Any other value in this register yields undefined results. + * | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior. + * @var HSUSBH_T::USTSR + * Offset: 0x24 USB Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBINT |USB Interrupt (USBINT) (R/WC) + * | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. + * | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). + * |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC) + * | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow) + * | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. + * |[2] |PCD |Port Change Detect (R/WC) + * | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port + * | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit. + * | | |This bit is allowed to be maintained in the Auxiliary power well + * | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change). + * |[3] |FLR |Frame List Rollover (R/WC) + * | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero + * | | |The exact value at which the rollover occurs depends on the frame list size + * | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles + * | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. + * |[4] |HSERR |Host System Error (R/WC) + * | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. + * |[5] |IAA |Interrupt on Asynchronous Advance (R/WC) + * | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register + * | | |This status bit indicates the assertion of that interrupt source. + * |[12] |HCHalted |HCHalted (RO) + * | | |This bit is a zero whenever the Run/Stop bit is a one + * | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. + * | | |internal error). + * |[13] |RECLA |Reclamation (RO) + * | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule. + * |[14] |PSS |Periodic Schedule Status (RO) + * | | |The bit reports the current real status of the Periodic Schedule + * | | |If this bit is a zero then the status of the Periodic Schedule is disabled + * | | |If this bit is a one then the status of the Periodic Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register + * | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). + * |[15] |ASS |Asynchronous Schedule Status (RO) + * | | |The bit reports the current real status of the Asynchronous Schedule + * | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled + * | | |If this bit is a one then the status of the Asynchronous Schedule is enabled + * | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register + * | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). + * @var HSUSBH_T::UIENR + * Offset: 0x28 USB Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBIEN |USB Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBINT bit. + * | | |0 = USB interrupt Disabled. + * | | |1 = USB interrupt Enabled. + * |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the USBERRINT bit. + * | | |0 = USB Error interrupt Disabled. + * | | |1 = USB Error interrupt Enabled. + * |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit + * | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Port Change Detect bit. + * | | |0 = Port Change interrupt Disabled. + * | | |1 = Port Change interrupt Enabled. + * |[3] |FLREN |Frame List Rollover Enable or Disable Bit + * | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit. + * | | |0 = Frame List Rollover interrupt Disabled. + * | | |1 = Frame List Rollover interrupt Enabled. + * |[4] |HSERREN |Host System Error Enable or Disable Bit + * | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt + * | | |The interrupt is acknowledged by software clearing the Host System Error bit. + * | | |0 = Host System Error interrupt Disabled. + * | | |1 = Host System Error interrupt Enabled. + * |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit + * | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold + * | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit. + * | | |0 = Interrupt on Asynchronous Advance Disabled. + * | | |1 = Interrupt on Asynchronous Advance Enabled. + * @var HSUSBH_T::UFINDR + * Offset: 0x2C USB Frame Index Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Index + * | | |The value in this register increment at the end of each time frame (e.g. + * | | |micro-frame) + * | | |Bits [N:3] are used for the Frame List current index + * | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index + * | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register. + * | | |FLSZ (UCMDR[3:2] Number Elements N + * | | |0x0 1024 12 + * | | |0x1 512 11 + * | | |0x2 256 10 + * | | |0x3 Reserved + * @var HSUSBH_T::UPFLBAR + * Offset: 0x34 USB Periodic Frame List Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:12] |BADDR |Base Address + * | | |These bits correspond to memory address signals [31:12], respectively. + * @var HSUSBH_T::UCALAR + * Offset: 0x38 USB Current Asynchronous List Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:5] |LPL |Link Pointer Low (LPL) + * | | |These bits correspond to memory address signals [31:5], respectively + * | | |This field may only reference a Queue Head (QH). + * @var HSUSBH_T::UASSTR + * Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer + * | | |This field defines the AsyncSchedSleepTime of EHCI spec. + * | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty. + * | | |The default value of this timer is 12'hBD6 + * | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us. + * @var HSUSBH_T::UCFGR + * Offset: 0x60 USB Configure Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CF |Configure Flag (CF) + * | | |Host software sets this bit as the last action in its process of configuring the Host Controller + * | | |This bit controls the default port-routing control logic + * | | |Bit values and side-effects are listed below. + * | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller. + * | | |1 = Port routing control logic default-routes all ports to this host controller. + * @var HSUSBH_T::UPSCR[2] + * Offset: 0x64~0x68 USB Port 0~1 Status and Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |Current Connect Status (RO) + * | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. + * | | |This field is zero if Port Power is zero. + * | | |0 = No device is present. + * | | |1 = Device is present on port. + * |[1] |CSC |Connect Status Change (R/W) + * | | |Indicates a change has occurred in the port's Current Connect Status + * | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change + * | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Change in Current Connect Status. + * |[2] |PE |Port Enabled/Disabled (R/W) + * | | |Ports can only be enabled by the host controller as a part of the reset and enable + * | | |Software cannot enable a port by writing a one to this field + * | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. + * | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software + * | | |Note that the bit status does not change until the port state actually changes + * | | |There may be a delay in disabling or enabling a port due to other host controller and bus events. + * | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[3] |PEC |Port Enable/Disable Change (R/WC) + * | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error) + * | | |Software clears this bit by writing a 1 to it. + * | | |This field is zero if Port Power is zero. + * | | |0 = No change. + * | | |1 = Port enabled/disabled status has changed. + * |[4] |OCA |Over-current Active (RO) + * | | |This bit will automatically transition from a one to a zero when the over current condition is removed. + * | | |0 = This port does not have an over-current condition. + * | | |1 = This port currently has an over-current condition. + * |[5] |OCC |Over-current Change (R/WC) + * | | |1 = This bit gets set to a one when there is a change to Over-current Active + * | | |Software clears this bit by writing a one to this bit position. + * |[6] |FPR |Force Port Resume (R/W) + * | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit + * | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. + * | | |Software sets this bit to a 1 to drive resume signaling + * | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state + * | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one + * | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit. + * | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0 + * | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one + * | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed + * | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle) + * | | |This bit will remain a one until the port has switched to the high-speed idle + * | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. + * | | |This field is zero if Port Power is zero. + * | | |0 = No resume (K-state) detected/driven on port. + * | | |1 = Resume detected/driven on port. + * |[7] |SUSPEND |Suspend (R/W) + * | | |Port Enabled Bit and Suspend bit of this register define the port states as follows: + * | | |Port enable is 0 and suspend is 0 = Disable. + * | | |Port enable is 0 and suspend is 1 = Disable. + * | | |Port enable is 1 and suspend is 0 = Enable. + * | | |Port enable is 1 and suspend is 1 = Suspend. + * | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset + * | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1 + * | | |In the suspend state, the port is sensitive to resume detection + * | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. + * | | |A write of zero to this bit is ignored by the host controller + * | | |The host controller will unconditionally set this bit to a zero when: + * | | |Software sets the Force Port Resume bit to a zero (from a one). + * | | |Software sets the Port Reset bit to a one (from a zero). + * | | |If host software sets this bit to a one when the port is not enabled (i.e. + * | | |Port enabled bit is a zero) the results are undefined. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port not in suspend state. + * | | |1 = Port in suspend state. + * |[8] |PRST |Port Reset (R/W) + * | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started + * | | |Software writes a zero to this bit to terminate the bus reset sequence + * | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes + * | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. + * | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero + * | | |The bit status will not read as a zero until after the reset has completed + * | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. + * | | |set the Port Enable bit to a one) + * | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero + * | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. + * | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit + * | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. + * | | |This field is zero if Port Power is zero. + * | | |0 = Port is not in Reset. + * | | |1 = Port is in Reset. + * |[11:10] |LSTS |Line Status (RO) + * | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines + * | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence + * | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. + * | | |The encoding of the bits are: + * | | |Bits[11:10] USB State Interpretation + * | | |00 = SE0 Not Low-speed device, perform EHCI reset. + * | | |01 = K-state Low-speed device, release ownership of port. + * | | |10 = J-state Not Low-speed device, perform EHCI reset. + * | | |11 = Undefined Not Low-speed device, perform EHCI reset. + * | | |This value of this field is undefined if Port Power is zero. + * |[12] |PP |Port Power (PP) + * | | |Host controller has port power control switches + * | | |This bit represents the Current setting of the switch (0 = off, 1 = on) + * | | |When power is not available on a port (i.e. + * | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc. + * | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port). + * |[13] |PO |Port Owner (R/W) + * | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition + * | | |This bit unconditionally goes to 1 whenever the Configured bit is zero. + * | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device) + * | | |Software writes a one to this bit when the attached device is not a high-speed device + * | | |A one in this bit means that a companion host controller owns and controls the port. + * |[19:16] |PTC |Port Test Control (R/W) + * | | |When this field is zero, the port is NOT operating in a test mode + * | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value + * | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved): + * | | |Bits Test Mode + * | | |0x0 = Test mode not enabled. + * | | |0x1 = Test J_STATE. + * | | |0x2 = Test K_STATE. + * | | |0x3 = Test SE0_NAK. + * | | |0x4 = Test Packet. + * | | |0x5 = Test FORCE_ENABLE. + * @var HSUSBH_T::USBPCR0 + * Offset: 0xC4 USB PHY 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 0. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 0 was suspended. + * | | |1 = USB PHY 0 was not suspended. + * |[11] |CLKVALID |UTMI Clock Valid + * | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready + * | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active. + * | | |0 = UTMI clock is not valid. + * | | |1 = UTMI clock is valid. + * @var HSUSBH_T::USBPCR1 + * Offset: 0xC8 USB PHY 1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |SUSPEND |Suspend Assertion + * | | |This bit controls the suspend mode of USB PHY 1. + * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. + * | | |This bit is 1'b0 in default + * | | |This means the USB PHY 0 is suspended in default + * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. + * | | |0 = USB PHY 1 was suspended. + * | | |1 = USB PHY 1 was not suspended. + */ + __I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */ + __I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */ + __I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */ + __IO uint32_t USTSR; /*!< [0x0024] USB Status Register */ + __IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */ + __IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */ + __IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */ + __IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */ + __IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[22]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */ + __IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */ + +} HSUSBH_T; + +/** + @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition + Constant Definitions for HSUSBH Controller +@{ */ + +#define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */ +#define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */ + +#define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */ +#define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */ + +#define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */ +#define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */ + +#define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */ +#define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */ + +#define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */ +#define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */ + +#define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */ +#define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */ + +#define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */ +#define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */ + +#define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */ +#define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */ + +#define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */ +#define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */ + +#define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */ +#define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */ + +#define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */ +#define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */ + +#define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */ +#define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */ + +#define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */ +#define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */ + +#define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */ +#define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */ + +#define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */ +#define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */ + +#define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */ +#define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */ + +#define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */ +#define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */ + +#define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */ +#define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */ + +#define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */ +#define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */ + +#define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */ +#define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */ + +#define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */ +#define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */ + +#define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */ +#define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */ + +#define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */ +#define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */ + +#define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */ +#define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */ + +#define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */ +#define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */ + +#define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */ +#define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */ + +#define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */ +#define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */ + +#define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */ +#define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */ + +#define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */ +#define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */ + +#define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */ +#define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */ + +#define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */ +#define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */ + +#define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */ +#define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */ + +#define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */ +#define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */ + +#define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */ +#define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */ + +#define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */ +#define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */ + +#define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */ +#define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */ + +#define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */ +#define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */ + +#define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */ +#define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */ + +#define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */ +#define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */ + +#define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */ +#define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */ + +#define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */ +#define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */ + +#define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */ +#define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */ + +#define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */ +#define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */ + +#define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */ +#define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */ + +#define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */ +#define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */ + +#define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */ +#define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */ + +#define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */ +#define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */ + +#define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */ +#define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */ + +#define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */ +#define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */ + +#define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */ +#define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */ + +#define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */ +#define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */ + +#define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */ +#define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */ + +#define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */ +#define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */ + +#define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */ +#define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */ + +#define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */ +#define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */ + +/**@}*/ /* HSUSBH_CONST */ +/**@}*/ /* end of HSUSBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __HSUSBH_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/i2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/i2c_reg.h new file mode 100644 index 0000000..e298017 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/i2c_reg.h @@ -0,0 +1,816 @@ +/**************************************************************************//** + * @file i2c_reg.h + * @version V1.00 + * @brief I2C register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2C Inter-IC Bus Controller(I2C) + Memory Mapped Structure for I2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2C_T::CTL0 + * Offset: 0x00 I2C Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware + * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested + * | | |SI must be cleared by software + * | | |Clear SI by writing 1 to this bit. + * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected + * | | |This bit will be cleared by hardware automatically. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[6] |I2CEN |I2C Controller Enable Bit + * | | |Set to enable I2C serial function controller + * | | |When I2CEN=1 the I2C serial function enable + * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. + * | | |0 = I2C controller Disabled. + * | | |1 = I2C controller Enabled. + * |[7] |INTEN |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * |[9:8] |DPBITSEL |Data Phase Bit Count Select + * | | |00 = DPCIF never set by hardware. + * | | |01 = When I2C is transfer data and bit count equal to 6, DPCIF will be set by hardware. + * | | |10 = When I2C is transfer data and bit count equal to 7, DPCIF will be set by hardware. + * | | |11 = When I2C is transfer data and bit count equal to 8, DPCIF will be set by hardware. + * |[12] |DPCINTEN |Data Phase Count Interrupt Enable Bit + * | | |0 = Data Phase Count Interrupt Disabled. + * | | |1 = Data Phase Count Interrupt Enabled. + * |[13] |SRCINTEN |Slave Read Command Interrupt Enable Bit + * | | |0 = Slave Read Command Interrupt Disabled. + * | | |1 = Slave Read Command Interrupt Enabled. + * |[14] |DPCIF |Data Phase Count Interrupt Flag + * | | |This bit is set by hardware when I2C transfer bit count equal to DPBITSEL setting + * | | |This bit is cleared by write 1 to it. + * |[15] |SARCIF |Slave Address Read Command Interrupt Flag + * | | |This bit is set by hardware when I2C receive address match read command. + * | | |This bit is cleared by write 1 to it. + * @var I2C_T::ADDR0 + * Offset: 0x04 I2C Slave Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::DAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |I2C Data + * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. + * @var I2C_T::STATUS0 + * Offset: 0x0C I2C Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STATUS |I2C Status + * | | |The three least significant bits are always 0 + * | | |The five most significant bits contain the status code + * | | |There are 28 possible status codes + * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested + * | | |Others I2C_STATUS values correspond to defined I2C states + * | | |When each of these states is entered, a status interrupt is requested (SI = 1) + * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software + * | | |In addition, states 00H stands for a Bus Error + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. + * @var I2C_T::CLKDIV + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DIVIDER |I2C Clock Divided + * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). + * | | |Note: The minimum value of I2C_CLKDIV is 4. + * |[15:12] |NFCNT |Noise Filter Count + * | | |The register bits control the input filter width. + * | | |0 = filter width 3*PCLK + * | | |1 = filter width 4*PCLK + * | | |N = filter width (3+N)*PCKL + * | | |Note: Filter width Min :3*PCLK, Max : 18*PCLK + * @var I2C_T::TOCTL + * Offset: 0x14 I2C Time-out Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIF |Time-out Flag + * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. + * | | |Note: Software can write 1 to clear this bit. + * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 + * | | |When Enabled, The time-out period is extend 4 times. + * | | |0 = Time-out period is extend 4 times Disabled. + * | | |1 = Time-out period is extend 4 times Enabled. + * |[2] |TOCEN |Time-out Counter Enable Bit + * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear + * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * @var I2C_T::ADDR1 + * Offset: 0x18 I2C Slave Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR2 + * Offset: 0x1C I2C Slave Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDR3 + * Offset: 0x20 I2C Slave Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDRMSK0 + * Offset: 0x24 I2C Slave Address Mask Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK1 + * Offset: 0x28 I2C Slave Address Mask Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK2 + * Offset: 0x2C I2C Slave Address Mask Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK3 + * Offset: 0x30 I2C Slave Address Mask Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::WKCTL + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |I2C Wake-up Enable Bit + * | | |0 = I2C wake-up function Disabled. + * | | |1 = I2C wake-up function Enabled. + * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit + * | | |0 = I2C hold bus after wake-up. + * | | |1 = I2C don't hold bus after wake-up. + * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received + * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. + * @var I2C_T::WKSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. + * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. + * @var I2C_T::CTL1 + * Offset: 0x44 I2C Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function disable. + * | | |1 = Transmit PDMA function enable. + * |[1] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function disable. + * | | |1 = Receive PDMA function enable. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the I2C request to PDMA. + * |[3] |OVRIEN |I2C over Run Interrupt Control Bit + * | | |Setting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer. + * |[4] |UDRIEN |I2C Under Run Interrupt Control Bit + * | | |Setting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer. + * |[5] |TWOBUFEN |Two-level BUFFER Enable Bit + * | | |0 = Two-level buffer Disabled. + * | | |1 = Two-level buffer Enabled. + * | | |Set to enable the two-level buffer for I2C transmitted or received buffer. It is used to improve the performance of the I2C bus. + * |[8] |PDMASTR |PDMA Stretch Bit + * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) + * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared + * | | |(only master TX) + * |[9] |ADDR10EN |Address 10-bit Function Enable + * | | |0 = Address match 10-bit function is disabled. + * | | |1 = Address match 10-bit function is enabled. + * |[10] |SWITCHEN |SCL And SDA Pin Switch Enable Bit + * | | |0 = I2C use original pin configuration. + * | | |1 = I2C switch SCL and SDA pin configuration. + * | | |Note: Original pin configuration table is shown in Basic Configuration chapter. + * @var I2C_T::STATUS1 + * Offset: 0x48 I2C Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |I2C Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |I2C Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[2] |ADMAT2 |I2C Address 2 Match Status Register + * | | |When address 2 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[3] |ADMAT3 |I2C Address 3 Match Status Register + * | | |When address 3 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[4] |FULL |TWO-LEVEL BUFFER FULL + * | | |This bit indicates two-level buffer TX or RX full or not when the TWOBUFEN = 1. + * | | |This bit is set when POINTER is equal to 2 + * | | |Note: This bit is read only. + * |[5] |EMPTY |TWO-LEVEL BUFFER EMPTY + * | | |This bit indicates two-level buffer TX or RX empty or not when the TWOBUFEN = 1. + * | | |This bit is set when POINTER is equal to 0. + * | | |Note: This bit is read only. + * |[6] |OVR |I2C over Run Status Bit + * | | |This bit indicates the received two-level buffer TX or RX is over run when the TWOBUFEN = 1. + * | | |Note: This bit is read only. + * |[7] |UDR |I2C Under Run Status Bit + * | | |This bit indicates the transmitted two-level buffer TX or RX is under run when the TWOBUFEN = 1. + * | | |Note: This bit is read only. + * |[8] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected. + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * | | |Note:This bit is read only. + * @var I2C_T::TMCTL + * Offset: 0x4C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. + * | | |Note: Setup time setting should not make SCL output less than three PCLKs. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. + * @var I2C_T::BUSCTL + * Offset: 0x50 I2C Bus Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACKMEN |Acknowledge Control by Manual + * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. + * | | |0 = Slave byte control Disabled. + * | | |1 = Slave byte control Enabled + * | | |The 9th bit can response the ACK or NACK according the received data by user + * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. + * | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. + * |[1] |PECEN |Packet Error Checking Calculation Enable Bit + * | | |0 = Packet Error Checking Calculation Disabled. + * | | |1 = Packet Error Checking Calculation Enabled. + * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation. + * |[2] |BMDEN |Bus Management Device Default Address Enable Bit + * | | |0 = Device default address Disable + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed + * | | |1 = Device default address Enabled + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. + * |[3] |BMHEN |Bus Management Host Enable Bit + * | | |0 = Host function Disabled. + * | | |1 = Host function Enabled. + * |[4] |ALERTEN |Bus Management Alert Enable Bit + * | | |Device Mode (BMHEN=0). + * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. + * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. + * | | |Host Mode (BMHEN=1). + * | | |0 = BM_ALERT pin not supported. + * | | |1 = BM_ALERT pin supported. + * |[5] |SCTLOSTS |Suspend/Control Data Output Status + * | | |0 = The output of SUSCON pin is low. + * | | |1 = The output of SUSCON pin is high. + * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit + * | | |0 = The SUSCON pin in input. + * | | |1 = The output enable is active on the SUSCON pin. + * |[7] |BUSEN |BUS Enable Bit + * | | |0 = The system management function is Disabled. + * | | |1 = The system management function is Enable. + * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. + * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception + * | | |0 = No PEC transfer. + * | | |1 = PEC transmission is requested. + * | | |Note: This bit has no effect in slave mode when ACKMEN=0. + * |[9] |TIDLE |Timer Check in Idle State + * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle + * | | |This bit is used to define which condition is enabled. + * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active. + * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. + * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. + * |[10] |PECCLR |PEC Clear at Repeat Start + * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected + * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. + * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled. + * | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled. + * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt + * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. + * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit + * | | |0 = Indicates the byte count done interrupt is Disabled. + * | | |1 = Indicates the byte count done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit + * | | |0 = Indicates the PEC transfer done interrupt is Disabled. + * | | |1 = Indicates the PEC transfer done interrupt is Enabled. + * | | |Note: This bit is used in PECEN=1. + * @var I2C_T::BUSTCTL + * Offset: 0x54 I2C Bus Management Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSTOEN |Bus Time Out Enable Bit + * | | |0 = Indicates the bus clock low time-out detection is Disabled. + * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) + * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit + * | | |0 = Indicates the cumulative clock low time-out detection is Disabled. + * | | |1 = Indicates the cumulative clock low time-out detection is Enabled. + * | | |For Master, it calculates the period from START to ACK + * | | |For Slave, it calculates the period from START to STOP + * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit + * | | |BUSY =1. + * | | |0 = Indicates the SCLK low time-out interrupt is Disabled. + * | | |1 = Indicates the SCLK low time-out interrupt is Enabled. + * | | |BUSY =0. + * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled. + * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled. + * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit + * | | |0 = Indicates the clock time out interrupt is Disabled. + * | | |1 = Indicates the clock time out interrupt is Enabled. + * |[4] |TORSTEN |Time Out Reset Enable Bit + * | | |0 = Indicates the I2C state machine reset is Disable. + * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) + * @var I2C_T::BUSSTS + * Offset: 0x58 I2C Bus Management Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[1] |BCDONE |Byte Count Transmission/Receive Done + * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * |[2] |PECERR |PEC Error in Reception + * | | |0 = Indicates the PEC value equal the received PEC data packet. + * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet. + * | | |Note: Software can write 1 to clear this bit. + * |[3] |ALERT |SMBus Alert Status + * | | |Device Mode (BMHEN =0). + * | | |0 = Indicates SMBALERT pin state is low. + * | | |1 = Indicates SMBALERT pin state is high. + * | | |Host Mode (BMHEN =1). + * | | |0 = No SMBALERT event. + * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. + * | | |Note: + * | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system + * | | |2. Software can write 1 to clear this bit. + * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status + * | | |0 = The input status of SUSCON pin is 0. + * | | |1 = The input status of SUSCON pin is 1. + * |[5] |BUSTO |Bus Time-out Status + * | | |0 = Indicates that there is no any time-out or external clock time-out. + * | | |1 = Indicates that a time-out or external clock time-out occurred. + * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[6] |CLKTO |Clock Low Cumulate Time-out Status + * | | |0 = Indicates that the cumulative clock low is no any time-out. + * | | |1 = Indicates that the cumulative clock low time-out occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[7] |PECDONE |PEC Byte Transmission/Receive Done + * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * @var I2C_T::PKTSIZE + * Offset: 0x5C I2C Packet Error Checking Byte Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PLDSIZE |Transfer Byte Number + * | | |The transmission or receive byte number in one transaction when the PECEN is set + * | | |The maximum transaction or receive byte is 256 Bytes. + * | | |Notice: The byte number counting includes address, command code, and data frame. + * @var I2C_T::PKTCRC + * Offset: 0x60 I2C Packet Error Checking Byte Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PECCRC |Packet Error Checking Byte Value + * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 + * | | |It is read only. + * @var I2C_T::BUSTOUT + * Offset: 0x64 I2C Bus Management Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BUSTO |Bus Management Time-out Value + * | | |Indicate the bus time-out value in bus is IDLE or SCLK low. + * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. + * @var I2C_T::CLKTOUT + * Offset: 0x68 I2C Bus Management Clock Low Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKTO |Bus Clock Low Timer + * | | |The field is used to configure the cumulative clock extension time-out. + * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ + __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ + __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ + __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ + __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ + __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ + __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ + __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ + __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ + __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ + __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ + __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ + __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ + __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ + __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ + __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ + __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ + __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ + __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ + __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ + +} I2C_T; + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller +@{ */ + +#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */ +#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */ + +#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */ +#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */ + +#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */ +#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */ + +#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */ +#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */ + +#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */ +#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */ + +#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */ +#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */ + +#define I2C_CTL0_DPBITSEL_Pos (8) /*!< I2C_T::CTL: DPBITSEL Position */ +#define I2C_CTL0_DPBITSEL_Msk (0x3ul << I2C_CTL0_DPBITSEL_Pos) /*!< I2C_T::CTL: DPBITSEL Mask */ + +#define I2C_CTL0_DPCINTEN_Pos (12) /*!< I2C_T::CTL: DPCINTEN Position */ +#define I2C_CTL0_DPCINTEN_Msk (0x1ul << I2C_CTL0_DPCINTEN_Pos) /*!< I2C_T::CTL: DPCINTEN Mask */ + +#define I2C_CTL0_SRCINTEN_Pos (13) /*!< I2C_T::CTL: SRCINTEN Position */ +#define I2C_CTL0_SRCINTEN_Msk (0x1ul << I2C_CTL0_SRCINTEN_Pos) /*!< I2C_T::CTL: SRCINTEN Mask */ + +#define I2C_CTL0_DPCIF_Pos (14) /*!< I2C_T::CTL: DPCIF Position */ +#define I2C_CTL0_DPCIF_Msk (0x1ul << I2C_CTL0_DPCIF_Pos) /*!< I2C_T::CTL: DPCIF Mask */ + +#define I2C_CTL0_SARCIF_Pos (15) /*!< I2C_T::CTL: SARCIF Position */ +#define I2C_CTL0_SARCIF_Msk (0x1ul << I2C_CTL0_SARCIF_Pos) /*!< I2C_T::CTL: SARCIF Mask */ + +#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ +#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ + +#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ +#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ + +#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ +#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ + +#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */ +#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */ + +#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ +#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ + +#define I2C_CLKDIV_NFCNT_Pos (12) /*!< I2C_T::CLKDIV: NFCNT Position */ +#define I2C_CLKDIV_NFCNT_Msk (0xful << I2C_CLKDIV_NFCNT_Pos) /*!< I2C_T::CLKDIV: NFCNT Mask */ + +#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ +#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ + +#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ +#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ + +#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ +#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ + +#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ +#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ + +#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ +#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ + +#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ +#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ + +#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ +#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ + +#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ +#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ + +#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ +#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ + +#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ +#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ +#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ +#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ + +#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ +#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ + +#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ +#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ + +#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ +#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ + +#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ +#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ + +#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ +#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ + +#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ +#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ + +#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ +#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ + +#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ +#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ + +#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ +#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ + +#define I2C_CTL1_OVRIEN_Pos (3) /*!< I2C_T::CTL1: OVRIEN Position */ +#define I2C_CTL1_OVRIEN_Msk (0x1ul << I2C_CTL1_OVRIEN_Pos) /*!< I2C_T::CTL1: OVRIEN Mask */ + +#define I2C_CTL1_UDRIEN_Pos (4) /*!< I2C_T::CTL1: UDRIEN Position */ +#define I2C_CTL1_UDRIEN_Msk (0x1ul << I2C_CTL1_UDRIEN_Pos) /*!< I2C_T::CTL1: UDRIEN Mask */ + +#define I2C_CTL1_TWOBUFEN_Pos (5) /*!< I2C_T::CTL1: TWOBUFEN Position */ +#define I2C_CTL1_TWOBUFEN_Msk (0x1ul << I2C_CTL1_TWOBUFEN_Pos) /*!< I2C_T::CTL1: TWOBUFEN Mask */ + +#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ +#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ + +#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ +#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ + +#define I2C_CTL1_SWITCHEN_Pos (10) /*!< I2C_T::CTL1: SWITCHEN Position */ +#define I2C_CTL1_SWITCHEN_Msk (0x1ul << I2C_CTL1_SWITCHEN_Pos) /*!< I2C_T::CTL1: SWITCHEN Mask */ + +#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ +#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ + +#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ +#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ + +#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ +#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ + +#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ +#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ + +#define I2C_STATUS1_FULL_Pos (4) /*!< I2C_T::STATUS1: FULL Position */ +#define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos) /*!< I2C_T::STATUS1: FULL Mask */ + +#define I2C_STATUS1_EMPTY_Pos (5) /*!< I2C_T::STATUS1: EMPTY Position */ +#define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos) /*!< I2C_T::STATUS1: EMPTY Mask */ + +#define I2C_STATUS1_OVR_Pos (6) /*!< I2C_T::STATUS1: OVR Position */ +#define I2C_STATUS1_OVR_Msk (0x1ul << I2C_STATUS1_OVR_Pos) /*!< I2C_T::STATUS1: OVR Mask */ + +#define I2C_STATUS1_UDR_Pos (7) /*!< I2C_T::STATUS1: UDR Position */ +#define I2C_STATUS1_UDR_Msk (0x1ul << I2C_STATUS1_UDR_Pos) /*!< I2C_T::STATUS1: UDR Mask */ + +#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ +#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ + +#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ +#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ + +#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ +#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ + +#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ +#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ + +#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ +#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ + +#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ +#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ + +#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ +#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ + +#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ +#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ + +#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ +#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ + +#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ +#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ + +#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ +#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ + +#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ +#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ + +#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ +#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ + +#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ +#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ + +#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ +#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ + +#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ +#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ + +#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ +#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ + +#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ +#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ + +#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ +#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ + +#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ +#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ + +#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ +#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ + +#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ +#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ + +#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ +#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ + +#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ +#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ + +#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ +#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ + +#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ +#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ + +#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ +#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ + +#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ +#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ + +#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ +#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ + +#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ +#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ + +#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ +#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ + +#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ +#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ + +#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ +#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ + +#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ +#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ + +/**@}*/ /* I2C_CONST */ +/**@}*/ /* end of I2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2C_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/i2s_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/i2s_reg.h new file mode 100644 index 0000000..9a37093 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/i2s_reg.h @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file i2s_reg.h + * @version V3.00 + * @brief I2S register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup I2S I2S Interface Controller(I2S) + Memory Mapped Structure for I2S Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2S_T::CTL0 + * Offset: 0x00 I2S Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Control + * | | |0 = I2S controller Disabled. + * | | |1 = I2S controller Enabled. + * |[1] |TXEN |Transmit Enable Control + * | | |0 = Data transmission Disabled. + * | | |1 = Data transmission Enabled. + * |[2] |RXEN |Receive Enable Control + * | | |0 = Data receiving Disabled. + * | | |1 = Data receiving Enabled. + * |[3] |MUTE |Transmit Mute Enable Control + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Send zero on transmit channel. + * |[5:4] |DATWIDTH |Data Width + * | | |This bit field is used to define the bit-width of data word in each audio channel + * | | |00 = The bit-width of data word is 8-bit. + * | | |01 = The bit-width of data word is 16-bit. + * | | |10 = The bit-width of data word is 24-bit. + * | | |11 = The bit-width of data word is 32-bit. + * |[6] |MONO |Monaural Data Control + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte + * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. + * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. + * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. + * | | |1 = Even channel data at low byte. + * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. + * |[8] |SLAVE |Slave Mode Enable Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * | | |Note: I2S can operate as master or slave + * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip + * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. + * |[15] |MCLKEN |Master Clock Enable Control + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[18] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear TX FIFO. + * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. + * | | |Note2: This bit is clear by hardware automatically, read it return zero. + * |[19] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear RX FIFO. + * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. + * | | |Note2: This bit is cleared by hardware automatically, read it return zero. + * |[20] |TXPDMAEN |Transmit PDMA Enable Control + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[21] |RXPDMAEN |Receive PDMA Enable Control + * | | |0 = Receiver PDMA function Disabled. + * | | |1 = Receiver PDMA function Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Control + * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. + * | | |0 = Receives channel1 data in MONO mode. + * | | |1 = Receives channel0 data in MONO mode. + * |[26:24] |FORMAT |Data Format Selection + * | | |000 = I2S standard data format. + * | | |001 = I2S with MSB justified. + * | | |010 = I2S with LSB justified. + * | | |011 = Reserved. + * | | |100 = PCM standard data format. + * | | |101 = PCM with MSB justified. + * | | |110 = PCM with LSB justified. + * | | |111 = Reserved. + * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection + * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol + * | | |0 = One BCLK period. + * | | |1 = One channel period. + * | | |Note: This bit is only available in master mode + * |[29:28] |CHWIDTH |Channel Width + * | | |This bit fields are used to define the length of audio channel + * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. + * | | |00 = The bit-width of each audio channel is 8-bit. + * | | |01 = The bit-width of each audio channel is 16-bit. + * | | |10 = The bit-width of each audio channel is 24-bit. + * | | |11 = The bit-width of each audio channel is 32-bit. + * |[31:30] |TDMCHNUM |TDM Channel Number + * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). + * | | |00 = 2 channels in audio frame. + * | | |01 = 4 channels in audio frame. + * | | |10 = 6 channels in audio frame. + * | | |11 = 8 channels in audio frame. + * @var I2S_T::CLKDIV + * Offset: 0x04 I2S Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MCLKDIV |Master Clock Divider + * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip + * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. + * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. + * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ). + * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). + * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK + * |[16:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |Software can program these bit fields to generate sampling rate clock frequency. + * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)). + * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK + * @var I2S_T::IEN + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. + * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1 + * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 + * | | |If RXTHIEN bit is enabled, interrupt occur. + * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. + * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1 + * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). + * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * @var I2S_T::STATUS0 + * Offset: 0x0C I2S Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag (Read Only) + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. + * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * |[5:3] |DATACH |Transmission Data Channel (Read Only) + * | | |This bit fields are used to indicate which audio channel is current transmit data belong. + * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). + * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). + * | | |010 = channel2 (available while 4-channel TDM PCM mode). + * | | |011 = channel3 (available while 4-channel TDM PCM mode). + * | | |100 = channel4 (available while 6-channel TDM PCM mode). + * | | |101 = channel5 (available while 6-channel TDM PCM mode). + * | | |110 = channel6 (available while 8-channel TDM PCM mode). + * | | |111 = channel7 (available while 8-channel TDM PCM mode). + * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag + * | | |0 = No underflow occur. + * | | |1 = Underflow occur. + * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again + * | | |This bit will be set to 1, and it indicates underflow situation occurs. + * | | |Note2: Write 1 to clear this bit to zero + * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag + * | | |0 = No overflow occur. + * | | |1 = Overflow occur. + * | | |Note1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. + * | | |Note2: Write 1 to clear this bit to 0. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is not higher than threshold level. + * | | |1 = Data word(s) in FIFO is higher than threshold level. + * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 + * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. + * |[11] |RXFULL |Receive FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in receive FIFO is 16. + * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in receive FIFO is zero + * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. + * | | |Note2: Write 1 to clear this bit to 0. + * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1 + * | | |Note2: Write 1 to clear this bit to 0. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is higher than threshold level. + * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. + * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 + * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. + * |[19] |TXFULL |Transmit FIFO Full (Read Only) + * | | |This bit reflect data word number in transmit FIFO is 16 + * | | |0 = Not full. + * | | |1 = Full. + * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) + * | | |This bit reflect data word number in transmit FIFO is zero + * | | |0 = Not empty. + * | | |1 = Empty. + * |[21] |TXBUSY |Transmit Busy (Read Only) + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is busy. + * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out + * | | |And set to 1 when 1st data is load to shift buffer + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit + * | | |Write data to this register to prepare data for transmit + * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data receive + * | | |Read this register to get data in FIFO + * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). + * @var I2S_T::CTL1 + * Offset: 0x20 I2S Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control + * | | |0 = channel0 zero-cross detect Disabled. + * | | |1 = channel0 zero-cross detect Enabled. + * | | |Note1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. + * | | |Note3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. + * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control + * | | |0 = channel1 zero-cross detect Disabled. + * | | |1 = channel1 zero-cross detect Enabled. + * | | |Note1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. + * | | |Note3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. + * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control + * | | |0 = channel2 zero-cross detect Disabled. + * | | |1 = channel2 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. + * | | |Note3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. + * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control + * | | |0 = channel3 zero-cross detect Disabled. + * | | |1 = channel3 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. + * | | |Note3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. + * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control + * | | |0 = channel4 zero-cross detect Disabled. + * | | |1 = channel4 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. + * | | |Note3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. + * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control + * | | |0 = channel5 zero-cross detect Disabled. + * | | |1 = channel5 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. + * | | |Note3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. + * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control + * | | |0 = channel6 zero-cross detect Disabled. + * | | |1 = channel6 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. + * | | |Note3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. + * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control + * | | |0 = channel7 zero-cross detect Disabled. + * | | |1 = channel7 zero-cross detect Enabled. + * | | |Note1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. + * | | |Note3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. + * |[11:8] |TXTH |Transmit FIFO Threshold Level + * | | |0000 = 0 data word in transmit FIFO. + * | | |0001 = 1 data word in transmit FIFO. + * | | |0010 = 2 data words in transmit FIFO. + * | | |... + * | | |1110 = 14 data words in transmit FIFO. + * | | |1111 = 15 data words in transmit FIFO. + * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. + * |[19:16] |RXTH |Receive FIFO Threshold Level + * | | |0000 = 1 data word in receive FIFO. + * | | |0001 = 2 data words in receive FIFO. + * | | |0010 = 3 data words in receive FIFO. + * | | |... + * | | |1110 = 15 data words in receive FIFO. + * | | |1111 = 16 data words in receive FIFO. + * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. + * |[24] |PBWIDTH |Peripheral Bus Data Width Selection + * | | |This bit is used to choice the available data width of APB bus + * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode + * | | |0 = 32 bits data width. + * | | |1 = 16 bits data width. + * | | |Note1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. + * | | |Note2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. + * | | |Note3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. + * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus + * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access + * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. + * | | |0 = Low 16-bit read/write access first. + * | | |1 = High 16-bit read/write access first. + * | | |Note: This bit is available while PBWIDTH = 1. + * @var I2S_T::STATUS1 + * Offset: 0x24 I2S Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag + * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel0. + * | | |1 = Channel0 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag + * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel1. + * | | |1 = Channel1 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag + * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel2. + * | | |1 = Channel2 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag + * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel3. + * | | |1 = Channel3 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag + * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel4. + * | | |1 = Channel4 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag + * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel5. + * | | |1 = Channel5 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag + * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel6. + * | | |1 = Channel6 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag + * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel7. + * | | |1 = Channel7 zero-cross is detected. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in transmit FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in transmit FIFO. + * | | |00010 = 2 words in transmit FIFO. + * | | |... + * | | |01110 = 14 words in transmit FIFO. + * | | |01111 = 15 words in transmit FIFO. + * | | |10000 = 16 words in transmit FIFO. + * | | |Others are reserved. + * |[20:16] |RXCNT |Receive FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in receive FIFO + * | | |00000 = No data. + * | | |00001 = 1 word in receive FIFO. + * | | |00010 = 2 words in receive FIFO. + * | | |... + * | | |01110 = 14 words in receive FIFO. + * | | |01111 = 15 words in receive FIFO. + * | | |10000 = 16 words in receive FIFO. + * | | |Others are reserved. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ + __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ + __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ + __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ + +} I2S_T; + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller +@{ */ + +#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ +#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ + +#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ +#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ + +#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ +#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ + +#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ +#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ + +#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ +#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ + +#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ +#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ + +#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ +#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ + +#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ +#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ + +#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ +#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ + +#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ +#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ + +#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ +#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ + +#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ +#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ + +#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ +#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ + +#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ +#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ + +#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ +#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ + +#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ +#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ + +#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ +#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ + +#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ +#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ + +#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ +#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ + +#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ +#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ + +#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ +#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ + +#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ +#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ + +#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ +#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ + +#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ +#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ + +#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ +#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ + +#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ +#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ + +#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ +#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ + +#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ +#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ + +#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ +#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ + +#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ +#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ + +#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ +#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ + +#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ +#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ + +#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ +#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ + +#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ +#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ + +#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ +#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ + +#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ +#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ + +#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ +#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ + +#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ +#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ + +#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ +#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ + +#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ +#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ + +#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ +#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ + +#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ +#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ + +#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ +#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ + +#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ +#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ + +#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ +#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ + +#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ +#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ + +#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ +#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ + +#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ +#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ + +#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ +#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ + +#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ +#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ + +#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ +#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ + +#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ +#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ + +#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ +#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ + +#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ +#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ + +#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ +#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ + +#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ +#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ + +#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ +#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ + +#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ +#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ + +#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ +#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ + +#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ +#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ + +#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ +#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ + +#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ +#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ + +#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ +#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ + +#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ +#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ + +#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ +#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ + +#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ +#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ + +#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ +#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ + +#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ +#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ + +#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ +#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ + +#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ +#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ + +#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ +#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ + +#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ +#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ + +#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ +#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ + +/**@}*/ /* I2S_CONST */ +/**@}*/ /* end of I2S register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __I2S_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/keystore_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/keystore_reg.h new file mode 100644 index 0000000..6976991 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/keystore_reg.h @@ -0,0 +1,398 @@ +/**************************************************************************//** + * @file keystore_reg.h + * @version V1.00 + * @brief Key store register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KEYSTORE_REG_H__ +#define __KEYSTORE_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Key Store -------------------------*/ +/** + @addtogroup KS Key Store(KS) + Memory Mapped Structure for KS Controller +@{ */ + +typedef struct +{ + + +/** + * @var KS_T::CTL + * Offset: 0x00 Key Store Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Key Store Start Control Bit + * | | |0 = No operation. + * | | |1 = Start the operation. + * |[3:1] |OPMODE |Key Store Operation Mode + * | | |000 = Read operation. + * | | |001 = Create operation. + * | | |010 = Erase one key operation (only for key is in SRAM and OTP). + * | | |011 = Erase all keys operation (only for SRAM and Flash). + * | | |100 = Revoke key operation. + * | | |101 = Data Remanence prevention operation (only for SRAM). + * | | |111 = Lock operation (only for OTP). + * | | |Others = reserved. + * |[7] |CONT |Read/Write Key Continue Bit + * | | |0 = Read/Write key operation is not continuous to previous operation. + * | | |1 = Read/Write key operation is continuous to previous operation. + * |[8] |INIT |Key Store Initialization + * | | |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initializationed. + * | | |After Key Store is initialized, INIT will be cleared. + * | | |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00. + * |[15] |IEN |Key Store Interrupt Enable Bit + * | | |0 = Key Store Interrupt Disabled. + * | | |1 = Key Store Interrupt Enabled. + * @var KS_T::METADATA + * Offset: 0x04 Key Store Metadata Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SEC |Secure Key Selection Bit + * | | |0 = Set key as the non-secure key. + * | | |1 = Set key as the secure key. + * |[1] |PRIV |Privilege Key Selection Bit + * | | |0 = Set key as the non-privilege key. + * | | |1 = Set key as the privilege key. + * |[2] |READABLE |Key Readable Control Bit + * | | |0 = key is un-readable. + * | | |1 = key is readable. + * |[4] |BS |Booting State Selection Bit + * | | |0 = Set key used at all state. + * | | |1 = Set key used at boot loader state 1 (BL1 state). + * |[12:8] |SIZE |Key Size Selection Bits + * | | |00000 = 128 bits. + * | | |00001 = 163 bits. + * | | |00010 = 192 bits. + * | | |00011 = 224 bits. + * | | |00100 = 233 bits. + * | | |00101 = 255 bits. + * | | |00110 = 256 bits. + * | | |00111 = 283 bits. + * | | |01000 = 384 bits. + * | | |01001 = 409 bits. + * | | |01010 = 512 bits. + * | | |01011 = 521 bits. + * | | |01100 = 571 bits. + * | | |10000 = 1024 bits. + * | | |10001 = 1536 bits. + * | | |10010 = 2048 bits. + * | | |10011 = 3072 bits. + * | | |10100 = 4096 bits. + * | | |Others = reserved. + * |[18:16] |OWNER |Key Owner Selection Bits + * | | |000 = AES + * | | |001 = HMAC + * | | |010 = RSA exponent blind key for SCAP(CRYPTO_RSA_CTL[8]) = 1 and CRT(CRYPTO_RSA_CTL[2]) = 0 + * | | |011 = RSA middle data, p, q and private key. + * | | |100 = ECC. + * | | |101 = CPU. + * | | |Others = reserved. + * |[25:20] |NUMBER |Key Number + * | | |Before read or erase one key operation starts, user should write the key number to be operated + * | | |When create operation is finished, user can read these bits to get its key number. + * |[31:30] |DST |Key Location Selection Bits + * | | |00 = Key is in SRAM. + * | | |01 = Key is in Flash. + * | | |10 = Key is in OTP. + * | | |Others = reserved. + * @var KS_T::STS + * Offset: 0x08 Key Store Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IF |Key Store Finish Interrupt Flag + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store interrupt. + * | | |1 = Key Store operation done interrupt. + * |[1] |EIF |Key Store Error Flag + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store error. + * | | |1 = Key Store error interrupt. + * |[2] |BUSY |Key Store Busy Flag (read only) + * | | |0 = Key Store is idle or finished. + * | | |1 = Key Store is busy. + * |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (read only) + * | | |0 = Key Storage at SRAM is not full. + * | | |1 = Key Storage at SRAM is full. + * |[4] |FLASHFULL |Key Storage at Flash Full Status Bit (read only) + * | | |0 = Key Storage at Flash is not full. + * | | |1 = Key Storage at Flash is full. + * |[7] |INITDONE |Key Store Initialization Done Status (read only) + * | | |0 = Key Store is un-initialized. + * | | |1 = Key Store is initialized. + * |[8] |RAMINV |Key Store SRAM Invert Status (read only) + * | | |0 = Key Store key in SRAM is normal. + * | | |1 = Key Store key in SRAM is inverted. + * @var KS_T::REMAIN + * Offset: 0x0C Key Store Remaining Space Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |RRMNG |Key Store SRAM Remaining Space + * | | |The RRMNG shows the remaining byte count space for SRAM. + * |[28:16] |FRMNG |Key Store Flash Remaining Space + * | | |The FRMNG shows the remaining byte count space for Flash. + * @var KS_T::KEY0 + * Offset: 0x20 Key Store Entry Key Word 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY1 + * Offset: 0x24 Key Store Entry Key Word 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY2 + * Offset: 0x28 Key Store Entry Key Word 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY3 + * Offset: 0x2C Key Store Entry Key Word 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY4 + * Offset: 0x30 Key Store Entry Key Word 4 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY5 + * Offset: 0x34 Key Store Entry Key Word 5 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY6 + * Offset: 0x38 Key Store Entry Key Word 6 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::KEY7 + * Offset: 0x3C Key Store Entry Key Word 7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::OTPSTS + * Offset: 0x40 Key Store OTP Keys Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KEY0 |OTP Key 0 Used Status + * | | |0 = OTP key 0 is unused. + * | | |1 = OTP key 0 is used. + * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[1] |KEY1 |OTP Key 1 Used Status + * | | |0 = OTP key 1 is unused. + * | | |1 = OTP key 1 is used. + * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[2] |KEY2 |OTP Key 2 Used Status + * | | |0 = OTP key 2 is unused. + * | | |1 = OTP key 2 is used. + * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[3] |KEY3 |OTP Key 3 Used Status + * | | |0 = OTP key 3 is unused. + * | | |1 = OTP key 3 is used. + * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[4] |KEY4 |OTP Key 4 Used Status + * | | |0 = OTP key 4 is unused. + * | | |1 = OTP key 4 is used. + * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, existing key will be revoked after initialization. + * |[5] |KEY5 |OTP Key 5 Used Status + * | | |0 = OTP key 5 is unused. + * | | |1 = OTP key 5 is used. + * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[6] |KEY6 |OTP Key 6 Used Status + * | | |0 = OTP key 6 is unused. + * | | |1 = OTP key 6 is used. + * | | |Note: If chip is in RMA stage, this bit will set to 1 and key is revoked after initialization if key is existed.Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[7] |KEY7 |OTP Key 7 Used Status + * | | |0 = OTP key 7 is unused. + * | | |1 = OTP key 7 is used. + * | | |Note: If chip is inchanged to RMA stage, this bit will set to 1 and key is revoked after initialization if key is existedthe existing key will be revoked after initialization. + * @var KS_T::REMKCNT + * Offset: 0x44 Key Store Remaining Key Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count + * | | |The RRMKCNT shows the remaining key count for SRAM. + * |[21:16] |FRMKCNT |Key Store Flash Remaining Key Count + * | | |The FRMKCNT shows the remaining key count for Flash. + * @var KS_T::VERSION + * Offset: 0xFFC Key Store RTL Design Version Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MINOR |RTL Design Minor Version Number + * | | |Minor version number is dependent on moduleu2019s ECO version control. + * | | |0x0000 (Current Minor Version Number) + * |[23:16] |SUB |RTL Design Sub Version Number + * | | |Sub version number is correlated to moduleu2019s key feature. + * | | |0x01 (Current Sub Version Number) + * |[31:24] |MAJOR |RTL Design Major Version Number + * | | |Major version number is correlated to Product Line. + * | | |0x021 (Current Major Version Number) + */ + __IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */ + __IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */ + __IO uint32_t STS; /*!< [0x0008] Key Store Status Register */ + __I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */ + __I uint32_t RESERVE0[4]; + __IO uint32_t KEY[8]; /*!< [0x0020-0x003c] Key Store Entry Key Word 0 Register */ + __I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */ + __I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */ + __I uint32_t RESERVE1[1005]; + __I uint32_t VERSION; /*!< [0x0ffc] Key Store RTL Design Version Register */ + +} KS_T; + +/** + @addtogroup KS_CONST KS Bit Field Definition + Constant Definitions for KS Controller +@{ */ + +#define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */ +#define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */ + +#define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */ +#define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */ + +#define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */ +#define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */ + +#define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */ +#define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */ + +#define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */ +#define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */ + +#define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */ +#define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */ + +#define KS_METADATA_PRIV_Pos (1) /*!< KS_T::METADATA: PRIV Position */ +#define KS_METADATA_PRIV_Msk (0x1ul << KS_METADATA_PRIV_Pos) /*!< KS_T::METADATA: PRIV Mask */ + +#define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */ +#define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */ + +#define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */ +#define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */ + +#define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */ +#define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */ + +#define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */ +#define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */ + +#define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */ +#define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */ + +#define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */ +#define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */ + +#define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */ +#define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */ + +#define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */ +#define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */ + +#define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */ +#define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */ + +#define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */ +#define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */ + +#define KS_STS_FLASHFULL_Pos (4) /*!< KS_T::STS: FLASHFULL Position */ +#define KS_STS_FLASHFULL_Msk (0x1ul << KS_STS_FLASHFULL_Pos) /*!< KS_T::STS: FLASHFULL Mask */ + +#define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */ +#define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */ + +#define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */ +#define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */ + +#define KS_STS_KRVKF_Pos (9) /*!< KS_T::STS: KRVKF Position */ +#define KS_STS_KRVKF_Msk (0x1ul << KS_STS_KRVKF_Pos) /*!< KS_T::STS: KRVKF Mask */ + +#define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */ +#define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */ + +#define KS_REMAIN_FRMNG_Pos (16) /*!< KS_T::REMAIN: FRMNG Position */ +#define KS_REMAIN_FRMNG_Msk (0x1ffful << KS_REMAIN_FRMNG_Pos) /*!< KS_T::REMAIN: FRMNG Mask */ + +#define KS_KEY_KEY_Pos (0) /*!< KS_T::KEY: KEY Position */ +#define KS_KEY_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY: KEY Mask */ + +#define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */ +#define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */ + +#define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */ +#define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */ + +#define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */ +#define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */ + +#define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */ +#define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */ + +#define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */ +#define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */ + +#define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */ +#define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */ + +#define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */ +#define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */ + +#define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */ +#define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */ + +#define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */ +#define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */ + +#define KS_REMKCNT_FRMKCNT_Pos (16) /*!< KS_T::REMKCNT: FRMKCNT Position */ +#define KS_REMKCNT_FRMKCNT_Msk (0x3ful << KS_REMKCNT_FRMKCNT_Pos) /*!< KS_T::REMKCNT: FRMKCNT Mask */ + +#define KS_VERSION_MINOR_Pos (0) /*!< KS_T::VERSION: MINOR Position */ +#define KS_VERSION_MINOR_Msk (0xfffful << KS_VERSION_MINOR_Pos) /*!< KS_T::VERSION: MINOR Mask */ + +#define KS_VERSION_SUB_Pos (16) /*!< KS_T::VERSION: SUB Position */ +#define KS_VERSION_SUB_Msk (0xfful << KS_VERSION_SUB_Pos) /*!< KS_T::VERSION: SUB Mask */ + +#define KS_VERSION_MAJOR_Pos (24) /*!< KS_T::VERSION: MAJOR Position */ +#define KS_VERSION_MAJOR_Msk (0xfful << KS_VERSION_MAJOR_Pos) /*!< KS_T::VERSION: MAJOR Mask */ + +/**@}*/ /* KS_CONST */ +/**@}*/ /* end of KS register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __KEYSTORE_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/kpi_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/kpi_reg.h new file mode 100644 index 0000000..404eeb9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/kpi_reg.h @@ -0,0 +1,370 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V1.00 + * @brief CLK register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KEYPAD_REG_H__ +#define __KEYPAD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Keypad Control Interface -------------------------*/ +/** + @addtogroup KPI Keypad Control Interface (KPI) + Memory Mapped Structure for KPI Controller +@{ */ + +typedef struct +{ + + +/** + * @var KPI_T::CTL + * Offset: 0x00 Keypad Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KPEN |Keypad Scan Enable Bit + * | | |Setting this bit high enables the key scan function. + * | | |0 = Keypad scan Disabled. + * | | |1 = Keypad scan Enabled. + * |[1] |KPIEN |Key Press Key Interrupt Enable Bit + * | | |The keypad controller will generate an interrupt when the controller detects any effective key press. + * | | |0 = Keypad press interrupt Disabled. + * | | |1 = Keypad press interrupt Enabled. + * | | |Note: The bit will be reset when KPI reset occurs. + * |[2] |KRIEN |Key Release Key Interrupt Enable Bit + * | | |The keypad controller will generate an interrupt when the controller detects keypad status changes from press to release. + * | | |0 = Keypad release interrupt Disabled. + * | | |1 = Keypad release interrupt Enabled. + * | | |Note: The bit will be reset when KPI reset occurs. + * |[3] |KIEN |Key Interrupt Enable Bit + * | | |0 = Keypad interrupt Disabled. + * | | |1 = Keypad interrupt Enabled. + * | | |Note: The bit will be reset when KPI reset occurs. + * |[5:4] |DBCT |De-bounce Cycle Time + * | | |For keypad debounce, keypad will generate an interrupt when key press, key release or three key reset continued n * key array scan time. + * | | |00 = n=1. + * | | |01 = n=2. + * | | |10 = n=3. + * | | |11 = n=4. + * | | |Note: It would need more time to indicate key press and release event when users selected more debounce cycle time. + * |[15:8] |PSC |Row Scan Cycle Pre-scale Value + * | | |This value is used to pre-scale row scan cycle. + * | | |The pre-scale counter is clocked by the divided crystal clock, xCLOCK. + * | | |The divided number is from 1 to 256. + * | | |E.g.If the crystal clock is 1Mhz then the xCLOCK period is 1us. + * | | |If the keypad matric is 3x3 then + * | | |Each row scan time = xCLOCK x PRESCALE PSC x PrescaleDividerPSCDIV. + * | | |Key array scan time = Each row scan time x ROWS. + * | | |Example scan time for PRESCALE = 0x40, and PrescaleDividerPSCDIV = 0x1F. + * | | |Each row scan time = 1us x 65 x 32 = 2.08ms. + * | | |Scan time = 2.08 x 3 = 6.24ms. + * | | |Note: + * | | |When PRESCALEPSC is determined, De-bounce sampling cycle should not exceed the half of (PRESCALEPSC x PrescaleDividerPSCDIV), + * | | |in the above example, and if scan row delay cycle is 4 xclock + * | | |The maximum DBCLKSEL should be 10244*256 xCLOCK, bouncing time is 1ms. + * |[19:16] |DBCLKSEL |Scan in De-bounce Sampling Cycle Selection + * | | |0000 = Reserved. + * | | |0001 = Reserved. + * | | |0010 = Reserved. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 512 clocks. + * | | |1010 = Sample interrupt input once per 1024 clocks. + * | | |1011 = Sample interrupt input once per 2048 clocks. + * | | |1100 = Sample interrupt input once per 4096 clocks. + * | | |1101 = Sample interrupt input once per 8192 clocks. + * | | |1110 = reserved. + * | | |1111 = reserved. + * | | |Note: + * | | |scan row delay cycle < debounce sampling cycle. + * | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle) + 1 xclock cycle(change row) + 2 xclock cycle(cross clock domain). + * | | |row scan time = xCLOCK x PRESCALEPSC x PrescaleDividerPSCDIVprescale * 32 (xclock). + * | | |xclock = 1 MHz ~32 kHz. + * | | |bouncing time last for 1ms + * | | |For example, if xclock = 1 MHz,. + * | | |debounce sampling cycle choose 1024 xclock, + * | | |and scan row delay cycle choose 8 xclock, + * | | |row scan time should choose larger than (8+2048+3) xclock, + * | | |suppose PrescaleDividerPSCDIV = 0x1F, then prescale = 65 (20562059/32 = 64.2535). + * |[23:22] |ROWDLY |Scan Row Delay + * | | |Setting delay cycle when row change, for avoid KPI from detecting wrong key.. + * | | |00 = 4 KPI engine clock cycle. + * | | |01 = 8 KPI engine clock cycle. + * | | |10 = 16 KPI engine clock cycle. + * | | |11 = 32 KPI engine clock cycle. + * | | |Note: + * | | |scan row delay cycle < debounce sampling cycle. + * | | |row scan time > scan row delay cycle + (2 * debounce sampling cycle) + 1 xclock cycle(change row) + 2 xclock cycle(cross clock domain). + * |[26:24] |KCOL |Keypad Matrix COL Number + * | | |The keypad matrix is set by ROW x COL. The COL number can be set 1 to 8. + * | | |000 = 1. + * | | |001 = 2. + * | | |010 = 3. + * | | |011 = 4. + * | | |100 = 5. + * | | |101 = 6. + * | | |110 = 7. + * | | |111 = 8. + * |[30:28] |KROW |Keypad Matrix ROW Number + * | | |The keypad matrix is set by ROW x COL. The ROW number can be set 2 to 6. + * | | |000 = reserved. + * | | |001 = 2. + * | | |010 = 3. + * | | |011 = 4. + * | | |100 = 5. + * | | |101 = 6. + * | | |110 = Reserved. + * | | |111 = Reserved. + * @var KPI_T::STATUS + * Offset: 0x08 Keypad Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TKRIF |3Three-keys Reset Interrupt Flag + * | | |This bit will be set after 3Three-keys reset occurs. + * | | |When READ: + * | | |0 = No reset. + * | | |1 = 3Three -keys reset interrupt occurred. + * | | |When WRITE: + * | | |0 = No operation. + * | | |1 = Clear interrupt flag. + * |[2] |KIF |Key Interrupt Flag + * | | |This bit indicates the key scan interrupt is active when any key press or, key release or three key reset or wake up. + * | | |When READ: + * | | |0 = No reset. + * | | |1 = Key press/Key release/3Three-key reset/wakeup interrupt occurred. + * | | |To clear KIF, software must clear KPIF, KRIF and TKRIF + * | | |(u9019u6BB5WSu81EAu5DF1u731Cu7684uFF0Cu5C0Du55CE?) + * |[3] |KRIF |Release Key Release Interrupt Flag + * | | |This bit indicates that some keys (one or multiple key) have been released. + * | | |When READ: + * | | |0 = No key release. + * | | |1 = At least one key release. + * | | |Note: To clear KRKEYINTIF, software must clear each releasing event flag that are shown on u201Ckey releasing eventu201D + * | | |KPI_KRF0/1 registers. + * | | |C code example: + * | | |DWORD RKE0, RKE1 + * | | |PKE0 = reg_read(KPIKRE0); PKE1 = reg_read(KPIKRE1);. + * | | |Reg_write(KPIKRE0, RKE0); Reg_write(KPIKRE1, RKE1) + * |[4] |KPIF |Key Press Key Interrupt Flag + * | | |This bit indicates that some keys (one or multiple key) have been pressed. + * | | |When READ: + * | | |0 = No key press. + * | | |1 = At least one key press. + * | | |Note: To clear KPIFPKEYINT, software must clear each pressing event flag that are shown on u201CKPIKPE1KPI_KPF0/1, KPIKPE0u201D + * | | |registers. + * | | |C code example: + * | | |DWORD PKE0, PKE1 + * | | |PKE0 = reg_read(KPIKPE0); PKE1 = reg_read(KPIKPE1);. + * | | |Reg_write(KPIKPE0, PKE0); Reg_write(KPIKPE1, PKE1) + * @var KPI_T::KST0 + * Offset: 0x10 Keypad State Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KSTmn |Key State + * | | |KESTm,n: m is row number, n is column number. + * | | |0 = Key m,n is pressing. + * | | |1 = Key m,n is releasing. + * @var KPI_T::KST1 + * Offset: 0x14 Keypad State Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |KESTmn |Key State + * | | |KESTm,n: m is row number, n is column number. + * | | |0 = Key m,n is pressing. + * | | |1 = Key m,n is releasing. + * @var KPI_T::KPF0 + * Offset: 0x18 Lower 32 Key Press Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KPFmn |Lower 32 Key Press Event Change IndicatorFlag + * | | |m is row number, n is column number. + * | | |KPE mn[X] = 1, m=row, n=column:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a high to low event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear PKEYINT KPIF (KPI_STATUS[4]) by writing 1 bit by bit to this register. + * @var KPI_T::KPF1 + * Offset: 0x1C Upper 32 Key Press Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |KPEmn |Upper 32 Key Press Event Change IndicatorFlag + * | | |KPE mn[X] = 1, m =is row number, n =is column number.:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a high to low event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear PKEYINT (KPISTATUS[4]) by writing 1 bit by bit to this register. + * @var KPI_T::KRF0 + * Offset: 0x20 Lower 32 Key Release Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KRFmn |Lower 32 Key Release Event Change IndicatorFlag + * | | |KRE mn[X] = 1, m= is row number, n= is column number.:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a low to high event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register. + * @var KPI_T::KRF1 + * Offset: 0x24 Upper 32 Key Release Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |KRFmn |Upper 32 Key Release Event Change IndicatorFlag + * | | |KRE mn[X] = 1, m =is row number, n =is column number.:. + * | | |0 = No key event. + * | | |1 = Corresponding key has a low to high event change. + * | | |Note: + * | | |Hardware will set this bit, and software should clear this bit by writing 1. + * | | |Software can clear RKEYINT (KPISTATUS[3]) by writing 1 bit by bit to this register. + * @var KPI_T::DLYCTL + * Offset: 0x28 Delay Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSCDIV |Pre-scale Divider + * | | |This value is used to divide RESCALE that is set in KPICONFKPI_CTL[15:8] + * | | |The prescale divider counter is clocked by the divided crystal clock, xCLOCK + * | | |The number is from 1 to 256. + * | | |E.g. If the crystal clock is 1Mhz then the xCLOCK period is 1us. If the keypad matrix is 3x3. Then, + * | | |each row scan time = xCLOCK x PRESCALEPSC x PrescaleDividerPSCDIV. + * | | |key array scan time = each row scan time x ROWS. + * | | |example scan time for PRESCALEPSC = 0x40, and PrescaleDividerPSCDIV = 0x1F. + * | | |each row scan time = 1us x 65 x 32 = 2.08ms. + * | | |scan time = 2.08 x 3 = 6.24ms. + * | | |Note: + * | | |When PRESCALEPSC (KPICONFKPI_CTL[15:8]) is determined, De-bounce sampling cycle should not exceed the half of (PRESCALEPSC x PrescaleDividerPSCDIV), + * | | |in the above example, and if scan row delay cycle is 4 xclock + * | | |The maximum DBCLKSEL(KPICONFKPI_CTL[19:16]) should be 1024 x clock, bouncing time is 1ms. + * |[17:8] |SCANDLY |Key Array Scan Delay + * | | |This value is used to insert delay cycle between each key array scan. + * | | |The key array scan delay counter is clocked by the divided crystal clock, xCLOCK. + * | | |Key array scan delay time = xCLOCK x KASDSCANDLY. + * | | |The number of key array scan delay cycle is 0 and from 2 to 1024. + * | | |0 = No delay. + * | | |Others = others + 1 cycles. + * | | |Note: + * | | |If the key array scan delay is set to 0, there are no delay between each key array scan. + * | | |There are no delay 1 cycle situation. + */ + __IO uint32_t CTL; /*!< [0x0000] Keypad Control Register */ + __IO uint32_t Reserved0; /*!< [0x0004] Reserved */ + __IO uint32_t STATUS; /*!< [0x0008] Keypad Status Register */ + __IO uint32_t Reserved1; /*!< [0x000c] Reserved */ + __I uint32_t KST[2]; /*!< [0x0010-0x0014] Keypad State Register 0 */ + __IO uint32_t KPF[2]; /*!< [0x0018-0x001c] Lower 32 Key Press Flag Register 0 */ + __IO uint32_t KRF[2]; /*!< [0x0020-0x0024] Lower 32 Key Release Flag Register 0 */ + __IO uint32_t DLYCTL; /*!< [0x0028] Delay Control Register */ + +} KPI_T; + +/** + @addtogroup KPI_CONST KPI Bit Field Definition + Constant Definitions for KPI Controller +@{ */ + +#define KPI_CTL_KPEN_Pos (0) /*!< KPI_T::CTL: KPEN Position */ +#define KPI_CTL_KPEN_Msk (0x1ul << KPI_CTL_KPEN_Pos) /*!< KPI_T::CTL: KPEN Mask */ + +#define KPI_CTL_KPIEN_Pos (1) /*!< KPI_T::CTL: KPIEN Position */ +#define KPI_CTL_KPIEN_Msk (0x1ul << KPI_CTL_KPIEN_Pos) /*!< KPI_T::CTL: KPIEN Mask */ + +#define KPI_CTL_KRIEN_Pos (2) /*!< KPI_T::CTL: KRIEN Position */ +#define KPI_CTL_KRIEN_Msk (0x1ul << KPI_CTL_KRIEN_Pos) /*!< KPI_T::CTL: KRIEN Mask */ + +#define KPI_CTL_KIEN_Pos (3) /*!< KPI_T::CTL: KIEN Position */ +#define KPI_CTL_KIEN_Msk (0x1ul << KPI_CTL_KIEN_Pos) /*!< KPI_T::CTL: KIEN Mask */ + +#define KPI_CTL_DBCT_Pos (4) /*!< KPI_T::CTL: DBCT Position */ +#define KPI_CTL_DBCT_Msk (0x3ul << KPI_CTL_DBCT_Pos) /*!< KPI_T::CTL: DBCT Mask */ + +#define KPI_CTL_PSC_Pos (8) /*!< KPI_T::CTL: PSC Position */ +#define KPI_CTL_PSC_Msk (0xfful << KPI_CTL_PSC_Pos) /*!< KPI_T::CTL: PSC Mask */ + +#define KPI_CTL_DBCLKSEL_Pos (16) /*!< KPI_T::CTL: DBCLKSEL Position */ +#define KPI_CTL_DBCLKSEL_Msk (0xful << KPI_CTL_DBCLKSEL_Pos) /*!< KPI_T::CTL: DBCLKSEL Mask */ + +#define KPI_CTL_ROWDLY_Pos (22) /*!< KPI_T::CTL: ROWDLY Position */ +#define KPI_CTL_ROWDLY_Msk (0x3ul << KPI_CTL_ROWDLY_Pos) /*!< KPI_T::CTL: ROWDLY Mask */ + +#define KPI_CTL_KCOL_Pos (24) /*!< KPI_T::CTL: KCOL Position */ +#define KPI_CTL_KCOL_Msk (0x7ul << KPI_CTL_KCOL_Pos) /*!< KPI_T::CTL: KCOL Mask */ + +#define KPI_CTL_KROW_Pos (28) /*!< KPI_T::CTL: KROW Position */ +#define KPI_CTL_KROW_Msk (0x7ul << KPI_CTL_KROW_Pos) /*!< KPI_T::CTL: KROW Mask */ + +#define KPI_STATUS_TKRIF_Pos (1) /*!< KPI_T::STATUS: TKRIF Position */ +#define KPI_STATUS_TKRIF_Msk (0x1ul << KPI_STATUS_TKRIF_Pos) /*!< KPI_T::STATUS: TKRIF Mask */ + +#define KPI_STATUS_KIF_Pos (2) /*!< KPI_T::STATUS: KIF Position */ +#define KPI_STATUS_KIF_Msk (0x1ul << KPI_STATUS_KIF_Pos) /*!< KPI_T::STATUS: KIF Mask */ + +#define KPI_STATUS_KRIF_Pos (3) /*!< KPI_T::STATUS: KRIF Position */ +#define KPI_STATUS_KRIF_Msk (0x1ul << KPI_STATUS_KRIF_Pos) /*!< KPI_T::STATUS: KRIF Mask */ + +#define KPI_STATUS_KPIF_Pos (4) /*!< KPI_T::STATUS: KPIF Position */ +#define KPI_STATUS_KPIF_Msk (0x1ul << KPI_STATUS_KPIF_Pos) /*!< KPI_T::STATUS: KPIF Mask */ + +#define KPI_KST0_KSTmn_Pos (0) /*!< KPI_T::KST0: KSTmn Position */ +#define KPI_KST0_KSTmn_Msk (0xfffffffful << KPI_KST0_KSTmn_Pos) /*!< KPI_T::KST0: KSTmn Mask */ + +#define KPI_KST1_KESTmn_Pos (0) /*!< KPI_T::KST1: KESTmn Position */ +#define KPI_KST1_KESTmn_Msk (0xfffful << KPI_KST1_KESTmn_Pos) /*!< KPI_T::KST1: KESTmn Mask */ + +#define KPI_KPF0_KPFmn_Pos (0) /*!< KPI_T::KPF0: KPFmn Position */ +#define KPI_KPF0_KPFmn_Msk (0xfffffffful << KPI_KPF0_KPFmn_Pos) /*!< KPI_T::KPF0: KPFmn Mask */ + +#define KPI_KPF1_KPEmn_Pos (0) /*!< KPI_T::KPF1: KPEmn Position */ +#define KPI_KPF1_KPEmn_Msk (0xfffful << KPI_KPF1_KPEmn_Pos) /*!< KPI_T::KPF1: KPEmn Mask */ + +#define KPI_KRF0_KRFmn_Pos (0) /*!< KPI_T::KRF0: KRFmn Position */ +#define KPI_KRF0_KRFmn_Msk (0xfffffffful << KPI_KRF0_KRFmn_Pos) /*!< KPI_T::KRF0: KRFmn Mask */ + +#define KPI_KRF1_KRFmn_Pos (0) /*!< KPI_T::KRF1: KRFmn Position */ +#define KPI_KRF1_KRFmn_Msk (0xfffful << KPI_KRF1_KRFmn_Pos) /*!< KPI_T::KRF1: KRFmn Mask */ + +#define KPI_DLYCTL_PSCDIV_Pos (0) /*!< KPI_T::DLYCTL: PSCDIV Position */ +#define KPI_DLYCTL_PSCDIV_Msk (0xfful << KPI_DLYCTL_PSCDIV_Pos) /*!< KPI_T::DLYCTL: PSCDIV Mask */ + +#define KPI_DLYCTL_SCANDLY_Pos (8) /*!< KPI_T::DLYCTL: SCANDLY Position */ +#define KPI_DLYCTL_SCANDLY_Msk (0x3fful << KPI_DLYCTL_SCANDLY_Pos) /*!< KPI_T::DLYCTL: SCANDLY Mask */ + +/**@}*/ /* KPI_CONST */ +/**@}*/ /* end of KPI register group */ + + +/**@}*/ /* end of REGISTER group */ +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __KEYPAD_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/otg_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/otg_reg.h new file mode 100644 index 0000000..b837c92 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/otg_reg.h @@ -0,0 +1,399 @@ +/**************************************************************************//** + * @file otg_reg.h + * @version V3.00 + * @brief OTG register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OTG_REG_H__ +#define __OTG_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OTG USB On-The-Go Controller(OTG) + Memory Mapped Structure for OTG Controller +@{ */ + +typedef struct +{ + + + /** + * @var OTG_T::CTL + * Offset: 0x00 OTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame not configured as OTG device, this bit is must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var OTG_T::PHYCTL + * Offset: 0x04 OTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable + * | | |When USB frame is configured as OTG-device or ID-dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG-device nor ID-dependent , this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var OTG_T::INTEN + * Offset: 0x08 OTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var OTG_T::INTSTS + * Offset: 0x0C OTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var OTG_T::STATUS + * Offset: 0x10 OTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-b/Micro-plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V, this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */ + +} OTG_T; + + +/** + @addtogroup OTG_CONST OTG Bit Field Definition + Constant Definitions for OTG Controller +@{ */ + +#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */ +#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */ + +#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */ +#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */ + +#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */ +#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */ + +#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */ +#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */ + +#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */ +#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */ + +#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */ +#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */ + +#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */ +#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */ + +#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */ +#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */ + +#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */ +#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */ + +#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */ +#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */ + +#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */ +#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */ + +#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */ +#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */ + +#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */ +#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */ + +#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */ +#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */ + +#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */ +#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */ + +#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */ +#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */ + +#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */ +#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */ + +#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */ +#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */ + +#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */ +#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */ + +#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */ +#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */ + +#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */ +#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */ + +#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */ +#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */ + +#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */ +#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */ + +#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */ +#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */ + +#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */ +#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */ + +#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */ +#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */ + +#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */ +#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */ + +#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */ +#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */ + +#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */ +#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */ + +#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */ +#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */ + +#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */ +#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */ + +#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */ +#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */ + +#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */ +#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */ + +#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */ +#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */ + +#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */ +#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */ + +#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */ +#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */ + +#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */ +#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */ + +#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */ +#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */ + +#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */ +#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */ + +#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */ +#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */ + +#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */ +#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */ + +#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */ +#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */ + +#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */ +#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* OTG_CONST */ +/**@}*/ /* end of OTG register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __OTG_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/pdma_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/pdma_reg.h new file mode 100644 index 0000000..3b4f4b3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/pdma_reg.h @@ -0,0 +1,1887 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @version V1.00 + * @brief PDMA register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) + Memory Mapped Structure for PDMA Controller +@{ */ + + +typedef struct +{ + + /** + * @var DSCT_T::CTL + * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE |PDMA Operation Mode Selection + * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. + * | | |01 = Basic mode: The descriptor table only has one task + * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted. + * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. + * | | |11 = Reserved. + * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. + * |[2] |TXTYPE |Transfer Type + * | | |0 = Burst transfer type. + * | | |1 = Single transfer type. + * |[6:4] |BURSIZE |Burst Size + * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. + * | | |000 = 128 Transfers. + * | | |001 = 64 Transfers. + * | | |010 = 32 Transfers. + * | | |011 = 16 Transfers. + * | | |100 = 8 Transfers. + * | | |101 = 4 Transfers. + * | | |110 = 2 Transfers. + * | | |111 = 1 Transfers. + * | | |Note: This field is only useful in burst transfer type. + * |[7] |TBINTDIS |Table Interrupt Disable Bit + * | | |This field can be used to decide whether to enable table interrupt or not + * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. + * | | |0 = Table interrupt Enabled. + * | | |1 = Table interrupt Disabled. + * |[9:8] |SAINC |Source Address Increment + * | | |This field is used to set the source address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[11:10] |DAINC |Destination Address Increment + * | | |This field is used to set the destination address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[13:12] |TXWIDTH |Transfer Width Selection + * | | |This field is used for transfer width. + * | | |00 = One byte (8 bit) is transferred for every operation. + * | | |01= One half-word (16 bit) is transferred for every operation. + * | | |10 = One word (32-bit) is transferred for every operation. + * | | |11 = Reserved. + * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection + * |[14] |TXACK |Transfer Acknowledge Selection + * | | |0 = transfer ack when transfer done. + * | | |1 = transfer ack when PDMA get transfer data. + * |[15] |STRIDEEN |Stride Mode Enable Bit + * | | |0 = Stride transfer mode Disabled. + * | | |1 = Stride transfer mode Enabled. + * |[31:16] |TXCNT |Transfer Count + * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 32768, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. + * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. + * @var DSCT_T::SA + * Offset: 0x04 Source Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SA |PDMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of PDMA controller. + * @var DSCT_T::DA + * Offset: 0x08 Destination Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DA |PDMA Transfer Destination Address Register + * | | |This field indicates a 32-bit destination address of PDMA controller. + * @var DSCT_T::NEXT + * Offset: 0x0C Next Scatter-Gather Descriptor Table Offset Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |EXENEXT |PDMA Execution Next Descriptor Table Offset + * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. + * | | |Note: write operation is useless in this field. + * |[31:16] |NEXT |PDMA Next Descriptor Table Offset. + * | | |This field indicates the offset of the next descriptor table address in system memory. + * | | |Write Operation: + * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. + * | | |Read Operation: + * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. + * | | |Note1: The descriptor table address must be word boundary. + * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. + */ + __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */ + __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ + __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ + __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */ +} DSCT_T; + + +typedef struct +{ + /** + * @var STRIDE_T::STCR + * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STC |PDMA Stride Transfer Count + * | | |The 16-bit register defines the stride transfer count of each row. + * @var STRIDE_T::ASOCR + * Offset: 0x504 Address Stride Offset Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SASOL |VDMA Source Address Stride Offset Length + * | | |The 16-bit register defines the source address stride transfer offset count of each row. + * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length + * | | |The 16-bit register defines the destination address stride transfer offset count of each row. + */ + __IO uint32_t STCR; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */ + __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */ +} STRIDE_T; + +typedef struct +{ + /** + * @var REPEAT_T::AICTL + * Offset: 0x600 Address Interval Control Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SAICNT |PDMA Source Address Interval Count + * | | |The 16-bit register defines the source address interval count of each row. + * |[31:16] |DAICNT |PDMA Destination Address Interval Count + * | | |The 16-bit register defines the destination address interval count of each row. + * @var REPEAT_T::RCNT + * Offset: 0x604 Repeat Count Register of PDMA Channe n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCNT |PDMA Repeat Count + * | | |The 16-bit register defines the repeat times of block transfer. + */ + __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */ + __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */ +} REPEAT_T; + +typedef struct +{ + + + /** + * @var PDMA_T::CURSCAT + * Offset: 0x100 Current Scatter-Gather Descriptor Table Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) + * | | |This field indicates a 32-bit current external description address of PDMA controller. + * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. + * @var PDMA_T::CHCTL + * Offset: 0x400 PDMA Channel Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHENn |PDMA Channel Enable Bit + * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. + * | | |0 = PDMA channel [n] Disabled. + * | | |1 = PDMA channel [n] Enabled. + * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. + * @var PDMA_T::PAUSE + * Offset: 0x404 PDMA Transfer Stop Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) + * | | |User can set PAUSEn bit field to pause the PDMA transfer + * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag + * | | |If re-enable the paused channel again, the remaining transfers will be processed. + * | | |0 = No effect. + * | | |1 = Pause PDMA channel n transfer. + * @var PDMA_T::SWREQ + * Offset: 0x408 PDMA Software Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) + * | | |Set this bit to 1 to generate a software request to PDMA [n]. + * | | |0 = No effect. + * | | |1 = Generate a software request. + * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active + * | | |Active flag may be triggered by software request or peripheral request. + * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. + * @var PDMA_T::TRGSTS + * Offset: 0x40C PDMA Channel Request Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) + * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral + * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. + * | | |0 = PDMA Channel n has no request. + * | | |1 = PDMA Channel n has a request. + * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. + * @var PDMA_T::PRISET + * Offset: 0x410 PDMA Fixed Priority Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register + * | | |Set this bit to 1 to enable fixed priority level. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set PDMA channel [n] to fixed priority channel. + * | | |Read Operation: + * | | |0 = Corresponding PDMA channel is round-robin priority. + * | | |1 = Corresponding PDMA channel is fixed priority. + * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. + * @var PDMA_T::PRICLR + * Offset: 0x414 PDMA Fixed Priority Clear Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) + * | | |Set this bit to 1 to clear fixed priority level. + * | | |0 = No effect. + * | | |1 = Clear PDMA channel [n] fixed priority setting. + * | | |Note: User can read PDMA_PRISET register to know the channel priority. + * @var PDMA_T::INTEN + * Offset: 0x418 PDMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |INTENn |PDMA Interrupt Enable Register + * | | |This field is used for enabling PDMA channel[n] interrupt. + * | | |0 = PDMA channel n interrupt Disabled. + * | | |1 = PDMA channel n interrupt Enabled. + * @var PDMA_T::INTSTS + * Offset: 0x41C PDMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-only) + * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. + * | | |0 = No AHB bus ERROR response received. + * | | |1 = AHB bus ERROR response received. + * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. + * | | |0 = Not finished yet. + * | | |1 = PDMA channel has finished transmission. + * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC0(PDMA_TOC0_1[15:0], user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC1(PDMA_TOC0_1[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[10] |REQTOF2 |Request Time-out Flag for Channel 2 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC2(PDMA_TOC2_3[15:0]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[11] |REQTOF3 |Request Time-out Flag for Channel 3 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC3(PDMA_TOC2_3[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[12] |REQTOF4 |Request Time-out Flag for Channel 4 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC4(PDMA_TOC4_5[15:0]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[13] |REQTOF5 |Request Time-out Flag for Channel 5 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC5(PDMA_TOC4_5[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[14] |REQTOF6 |Request Time-out Flag for Channel 6 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC6(PDMA_TOC6_7[15:0]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[15] |REQTOF7 |Request Time-out Flag for Channel 7 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC7(PDMA_TOC6_7[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[16] |REQTOF8 |Request Time-out Flag for Channel 8 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC8(PDMA_TOC8_9[15:0]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[17] |REQTOF9 |Request Time-out Flag for Channel 9 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC9(PDMA_TOC8_9[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[18] |REQTOF10 |Request Time-out Flag for Channel 10 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC10(PDMA_TOC10_11[15:0]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[19] |REQTOF11 |Request Time-out Flag for Channel 11 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC11(PDMA_TOC10_11[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[20] |REQTOF12 |Request Time-out Flag for Channel 12 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC12(PDMA_TOC13_12[15:0]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[21] |REQTOF13 |Request Time-out Flag for Channel 13 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC13(PDMA_TOC13_12[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[22] |REQTOF14 |Request Time-out Flag for Channel 14 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC14(PDMA_TOC15_14[15:0]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[23] |REQTOF15 |Request Time-out Flag for Channel 15 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by TOC15(PDMA_TOC15_14[31:16]), user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * @var PDMA_T::ABTSTS + * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag + * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. + * | | |0 = No AHB bus ERROR response received when channel n transfer. + * | | |1 = AHB bus ERROR response received when channel n transfer. + * @var PDMA_T::TDSTS + * Offset: 0x424 PDMA Channel Transfer Done Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TDIFn |Transfer Done Flag Register + * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. + * | | |0 = PDMA channel transfer has not finished. + * | | |1 = PDMA channel has finished transmission. + * @var PDMA_T::ALIGN + * Offset: 0x428 PDMA Transfer Alignment Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ALIGNn |Transfer Alignment Flag Register + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * @var PDMA_T::TACTSTS + * Offset: 0x42C PDMA Transfer Active Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) + * | | |This bit indicates which PDMA channel is in active. + * | | |0 = PDMA channel is not finished. + * | | |1 = PDMA channel is active. + * @var PDMA_T::TOUTPSC0_7 + * Offset: 0x430 PDMA Time-out Prescaler Register(CH0 to CH7) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 0 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 0 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 0 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 0 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 0 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 0 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 0 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 0 time-out clock source is HCLK/215. + * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 1 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 1 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 1 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 1 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 1 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 1 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 1 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 1 time-out clock source is HCLK/215. + * |[10:8] |TOUTPSC2 |PDMA Channel 2 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 2 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 2 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 2 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 2 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 2 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 2 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 2 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 2 time-out clock source is HCLK/215. + * |[14:12] |TOUTPSC3 |PDMA Channel 3 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 3 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 3 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 3 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 3 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 3 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 3 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 3 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 3 time-out clock source is HCLK/215. + * |[18:16] |TOUTPSC4 |PDMA Channel 4 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 4 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 4 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 4 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 4 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 4 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 4 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 4 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 4 time-out clock source is HCLK/215. + * |[22:20] |TOUTPSC5 |PDMA Channel 5 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 5 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 5 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 5 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 5 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 5 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 5 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 5 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 5 time-out clock source is HCLK/215. + * |[26:24] |TOUTPSC6 |PDMA Channel 6 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 6 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 6 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 6 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 6 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 6 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 6 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 6 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 6 time-out clock source is HCLK/215. + * |[30:28] |TOUTPSC7 |PDMA Channel 7 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 7 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 7 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 7 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 7 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 7 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 7 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 7 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 7 time-out clock source is HCLK/215. + * @var PDMA_T::TOUTEN + * Offset: 0x434 PDMA Time-out Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOUTENn |PDMA Time-out Enable Bits + * | | |0 = PDMA Channel n time-out function Disable. + * | | |1 = PDMA Channel n time-out function Enable. + * @var PDMA_T::TOUTIEN + * Offset: 0x438 PDMA Time-out Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits + * | | |0 = PDMA Channel n time-out interrupt Disable. + * | | |1 = PDMA Channel n time-out interrupt Enable. + * @var PDMA_T::SCATBA + * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register + * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address + * | | |The next link address equation is + * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. + * | | |Note: Only useful in Scatter-Gather mode. + * @var PDMA_T::TOC0_1 + * Offset: 0x440 PDMA Time-out Counter Ch0 and Ch1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC0 |Time-out Counter for Channel 0 + * | | |This controls the period of time-out function for channel 0 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC1 |Time-out Counter for Channel 1 + * | | |This controls the period of time-out function for channel 1 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::TOC2_3 + * Offset: 0x444 PDMA Time-out Counter Ch2 and Ch3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC2 |Time-out Counter for Channel 2 + * | | |This controls the period of time-out function for channel 2 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC3 |Time-out Counter for Channel 3 + * | | |This controls the period of time-out function for channel 3 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::TOC4_5 + * Offset: 0x448 PDMA Time-out Counter Ch4 and Ch5 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC4 |Time-out Counter for Channel 4 + * | | |This controls the period of time-out function for channel 4 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC5 |Time-out Counter for Channel 5 + * | | |This controls the period of time-out function for channel 5 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::TOC6_7 + * Offset: 0x44C PDMA Time-out Counter Ch6 and Ch7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC6 |Time-out Counter for Channel 6 + * | | |This controls the period of time-out function for channel 6 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC7 |Time-out Counter for Channel 7 + * | | |This controls the period of time-out function for channel 7 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::TOC8_9 + * Offset: 0x450 PDMA Time-out Counter Ch8 and Ch9 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC8 |Time-out Counter for Channel 8 + * | | |This controls the period of time-out function for channel 8 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC9 |Time-out Counter for Channel 9 + * | | |This controls the period of time-out function for channel 9 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::TOC10_11 + * Offset: 0x454 PDMA Time-out Counter Ch10 and Ch11 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC10 |Time-out Counter for Channel 10 + * | | |This controls the period of time-out function for channel 10 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC11 |Time-out Counter for Channel 11 + * | | |This controls the period of time-out function for channel 11 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::TOC12_13 + * Offset: 0x458 PDMA Time-out Counter Ch12 and Ch13 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC12 |Time-out Counter for Channel 12 + * | | |This controls the period of time-out function for channel 12 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC13 |Time-out Counter for Channel 13 + * | | |This controls the period of time-out function for channel 13 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::TOC14_15 + * Offset: 0x45C PDMA Time-out Counter Ch14 and Ch15 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC14 |Time-out Counter for Channel 14 + * | | |This controls the period of time-out function for channel 14 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC15 |Time-out Counter for Channel 15 + * | | |This controls the period of time-out function for channel 15 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::CHRST + * Offset: 0x460 PDMA Channel Reset Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHnRST |Channel N Reset + * | | |0 = corresponding channel n not reset. + * | | |1 = corresponding channel n is reset. + * @var PDMA_T::TOUTPSC8_15 + * Offset: 0x468 PDMA Time-out Prescaler Register(CH8 to CH15) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC8 |PDMA Channel 8 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 8 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 8 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 8 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 8 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 8 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 8 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 8 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 8 time-out clock source is HCLK/215. + * |[6:4] |TOUTPSC9 |PDMA Channel 9 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 9 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 9 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 9 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 9 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 9 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 9 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 9 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 9 time-out clock source is HCLK/215. + * |[10:8] |TOUTPSC10 |PDMA Channel 10 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 10 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 10 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 10 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 10 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 10 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 10 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 10 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 10 time-out clock source is HCLK/215. + * |[14:12] |TOUTPSC11 |PDMA Channel 11 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 11 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 11 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 11 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 11 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 11 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 11 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 11 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 11 time-out clock source is HCLK/215. + * |[18:16] |TOUTPSC12 |PDMA Channel 12 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 12 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 12 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 12 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 12 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 12 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 12 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 12 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 12 time-out clock source is HCLK/215. + * |[22:20] |TOUTPSC13 |PDMA Channel 13 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 13 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 13 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 13 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 13 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 13 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 13 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 13 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 13 time-out clock source is HCLK/215. + * |[26:24] |TOUTPSC14 |PDMA Channel 14 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 14 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 14 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 14 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 14 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 14 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 14 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 14 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 14 time-out clock source is HCLK/215. + * |[30:28] |TOUTPSC15 |PDMA Channel 15 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 15 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 15 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 15 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 15 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 15 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 15 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 15 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 15 time-out clock source is HCLK/215. + * @var PDMA_T::REQSEL0_3 + * Offset: 0x480 PDMA Request Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC0 |Channel 0 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 0 + * | | |User can configure the peripheral by setting REQSRC0. + * | | |0 = Disable PDMA peripheral request. + * | | |1 = Reserved. + * | | |2 = Channel connects to USB_TX. + * | | |3 = Channel connects to USB_RX. + * | | |4 = Channel connects to UART0_TX. + * | | |5 = Channel connects to UART0_RX. + * | | |6 = Channel connects to UART1_TX. + * | | |7 = Channel connects to UART1_RX. + * | | |8 = Channel connects to UART2_TX. + * | | |9 = Channel connects to UART2_RX. + * | | |10=Channel connects to UART3_TX. + * | | |11 = Channel connects to UART3_RX. + * | | |12 = Channel connects to UART4_TX. + * | | |13 = Channel connects to UART4_RX. + * | | |14 = Channel connects to UART5_TX. + * | | |15 = Channel connects to UART5_RX. + * | | |16 = Channel connects to USCI0_TX. + * | | |17 = Channel connects to USCI0_RX. + * | | |18 = Reserved. + * | | |19 = Reserved. + * | | |20 = Channel connects to QSPI0_TX. + * | | |21 = Channel connects to QSPI0_RX. + * | | |22 = Channel connects to SPI0_TX. + * | | |23 = Channel connects to SPI0_RX. + * | | |24 = Channel connects to SPI1_TX. + * | | |25 = Channel connects to SPI1_RX. + * | | |26 = Channel connects to SPI2_TX. + * | | |27 = Channel connects to SPI2_RX. + * | | |28 = Channel connects to SPI3_TX. + * | | |29 = Channel connects to SPI3_RX. + * | | |30 = Channel connects to QSPI1_TX + * | | |31 = Channel connects to QSPI1_RX. + * | | |32 = Channel connects to EPWM0_P1_RX. + * | | |33 = Channel connects to EPWM0_P2_RX. + * | | |34 = Channel connects to EPWM0_P3_RX. + * | | |35 = Channel connects to EPWM1_P1_RX. + * | | |36 = Channel connects to EPWM1_P2_RX. + * | | |37 = Channel connects to EPWM1_P3_RX. + * | | |38 = Channel connects to I2C0_TX. + * | | |39 = Channel connects to I2C0_RX. + * | | |40 = Channel connects to I2C1_TX. + * | | |41 = Channel connects to I2C1_RX. + * | | |42 = Channel connects to I2C2_TX. + * | | |43 = Channel connects to I2C2_RX. + * | | |44 = Channel connects to I2S0_TX. + * | | |45 = Channel connects to I2S0_RX. + * | | |46 = Channel connects to TMR0. + * | | |47 = Channel connects to TMR1. + * | | |48 = Channel connects to TMR2. + * | | |49 = Channel connects to TMR3. + * | | |50 = Channel connects to ADC0_RX. + * | | |51 = Channel connects to DAC0_TX. + * | | |52 = Channel connects to DAC1_TX. + * | | |53 = Channel connects to EPWM0_CH0_TX. + * | | |54 = Channel connects to EPWM0_CH1_TX. + * | | |55 = Channel connects to EPWM0_CH2_TX. + * | | |56 = Channel connects to EPWM0_CH3_TX. + * | | |57 = Channel connects to EPWM0_CH4_TX. + * | | |58 = Channel connects to EPWM0_CH5_TX. + * | | |59 = Channel connects to EPWM1_CH0_TX. + * | | |60 = Channel connects to EPWM1_CH1_TX. + * | | |61 = Channel connects to EPWM1_CH2_TX. + * | | |62 = Channel connects to EPWM1_CH3_TX. + * | | |63 = Channel connects to EPWM1_CH4_TX. + * | | |64 = Channel connects to EPWM1_CH5_TX. + * | | |65 = Reserved. + * | | |66 = Channel connects to UART6_TX. + * | | |67 = Channel connects to UART6_RX. + * | | |68 = Channel connects to UART7_TX. + * | | |69 = Channel connects to UART7_RX. + * | | |70 = Channel connects to ADC1_RX. + * | | |71 = Channel connects to ACMP0. + * | | |72 = Channel connects to ACMP1. + * | | |73 = Channel connects to PSIO_TX. + * | | |74 = Channel connects to PSIO_RX. + * | | |75 = Channel connects to I2C3_TX. + * | | |76 = Channel connects to I2C3_RX. + * | | |77 = Channel connects to I2C4_TX. + * | | |78 = Channel connects to I2C4_RX. + * | | |79 = Channel connects to I2S1_TX. + * | | |80 = Channel connects to I2S1_RX. + * | | |81 = Channel connects to EINT0. + * | | |82 = Channel connects to EINT1. + * | | |83 = Channel connects to EINT2. + * | | |84 = Channel connects to EINT3. + * | | |85 = Channel connects to EINT4. + * | | |86 = Channel connects to EINT5. + * | | |87 = Channel connects to EINT6. + * | | |88 = Channel connects to EINT7. + * | | |89 = Channel connects to UART8_TX. + * | | |90 = Channel connects to UART8_RX. + * | | |91 = Channel connects to UART9_TX. + * | | |92 = Channel connects to UART9_RX. + * | | |93 = Channel connects to ADC2_RX. + * | | |94 = Channel connects to ACMP2. + * | | |95 = Channel connects to ACMP3. + * | | |Others = Reserved. + * | | |Note 1: A peripheral can't assign to two channels at the same time. + * | | |Note 2: This field is useless when transfer between memory and memory. + * |[14:8] |REQSRC1 |Channel 1 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 1 + * | | |User can configure the peripheral setting by REQSRC1. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC2 |Channel 2 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 2 + * | | |User can configure the peripheral setting by REQSRC2. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC3 |Channel 3 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 3 + * | | |User can configure the peripheral setting by REQSRC3. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL4_7 + * Offset: 0x484 PDMA Request Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC4 |Channel 4 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 4 + * | | |User can configure the peripheral setting by REQSRC4. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC5 |Channel 5 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 5 + * | | |User can configure the peripheral setting by REQSRC5. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC6 |Channel 6 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 6 + * | | |User can configure the peripheral setting by REQSRC6. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC7 |Channel 7 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 7 + * | | |User can configure the peripheral setting by REQSRC7. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL8_11 + * Offset: 0x488 PDMA Request Source Select Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC8 |Channel 8 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 8 + * | | |User can configure the peripheral setting by REQSRC8. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC9 |Channel 9 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 9 + * | | |User can configure the peripheral setting by REQSRC9. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC10 |Channel 10 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 10 + * | | |User can configure the peripheral setting by REQSRC10. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC11 |Channel 11 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 11 + * | | |User can configure the peripheral setting by REQSRC11. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL12_15 + * Offset: 0x48C PDMA Request Source Select Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC12 |Channel 12 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 12 + * | | |User can configure the peripheral setting by REQSRC12. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC13 |Channel 13 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 13 + * | | |User can configure the peripheral setting by REQSRC13. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC14 |Channel 14 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 14 + * | | |User can configure the peripheral setting by REQSRC14. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC15 |Channel 15 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 15 + * | | |User can configure the peripheral setting by REQSRC15. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + */ + DSCT_T DSCT[16]; + __I uint32_t CURSCAT[16]; /*!< [0x0100] Current Scatter-Gather Descriptor Table Address of PDMA Channel n */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[176]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ + __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ + __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ + __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ + __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ + __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ + __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ + __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ + __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ + __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ + __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ + __IO uint32_t TOUTPSC0_7; /*!< [0x0430] PDMA Time-out Prescaler Register(CH0 to CH7) */ + __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ + __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ + __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ + __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch0 and Ch1 Register */ + __IO uint32_t TOC2_3; /*!< [0x0444] PDMA Time-out Counter Ch2 and Ch3 Register */ + __IO uint32_t TOC4_5; /*!< [0x0448] PDMA Time-out Counter Ch4 and Ch5 Register */ + __IO uint32_t TOC6_7; /*!< [0x044C] PDMA Time-out Counter Ch6 and Ch7 Register */ + __IO uint32_t TOC8_9; /*!< [0x0450] PDMA Time-out Counter Ch8 and Ch9 Register */ + __IO uint32_t TOC10_11; /*!< [0x0454] PDMA Time-out Counter Ch10 and Ch11 Register */ + __IO uint32_t TOC12_13; /*!< [0x0458] PDMA Time-out Counter Ch12 and Ch13 Register */ + __IO uint32_t TOC14_15; /*!< [0x045C] PDMA Time-out Counter Ch14 and Ch15 Register */ + __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t TOUTPSC8_15; /*!< [0x0468] PDMA Time-out Prescaler Register(CH8 to CH15) */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ + __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ + __IO uint32_t REQSEL8_11; /*!< [0x0488] PDMA Request Source Select Register 2 */ + __IO uint32_t REQSEL12_15; /*!< [0x048c] PDMA Request Source Select Register 3 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE4[28]; + /// @endcond //HIDDEN_SYMBOLS + STRIDE_T STRIDE[6]; + /// @cond HIDDEN_SYMBOLS + __IO uint32_t RESERVE5[52]; + /// @endcond //HIDDEN_SYMBOLS + REPEAT_T REPEAT[2]; +} PDMA_T; + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller +@{ */ + +#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ +#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ + +#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ +#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ + +#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ +#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ + +#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ +#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ + +#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ +#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ + +#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ +#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ + +#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ +#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ + +#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ +#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ + +#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ +#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ + +#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ +#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ + +#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ +#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ + +#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ +#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ + +#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ +#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ + +#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ +#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ + +#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ +#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ + +#define PDMA_CHCTL_CHEN0_Pos (0) /*!< PDMA_T::CHCTL: CHEN0 Position */ +#define PDMA_CHCTL_CHEN0_Msk (0x1ul << PDMA_CHCTL_CHEN0_Pos) /*!< PDMA_T::CHCTL: CHEN0 Mask */ + +#define PDMA_CHCTL_CHEN1_Pos (1) /*!< PDMA_T::CHCTL: CHEN1 Position */ +#define PDMA_CHCTL_CHEN1_Msk (0x1ul << PDMA_CHCTL_CHEN1_Pos) /*!< PDMA_T::CHCTL: CHEN1 Mask */ + +#define PDMA_CHCTL_CHEN2_Pos (2) /*!< PDMA_T::CHCTL: CHEN2 Position */ +#define PDMA_CHCTL_CHEN2_Msk (0x1ul << PDMA_CHCTL_CHEN2_Pos) /*!< PDMA_T::CHCTL: CHEN2 Mask */ + +#define PDMA_CHCTL_CHEN3_Pos (3) /*!< PDMA_T::CHCTL: CHEN3 Position */ +#define PDMA_CHCTL_CHEN3_Msk (0x1ul << PDMA_CHCTL_CHEN3_Pos) /*!< PDMA_T::CHCTL: CHEN3 Mask */ + +#define PDMA_CHCTL_CHEN4_Pos (4) /*!< PDMA_T::CHCTL: CHEN4 Position */ +#define PDMA_CHCTL_CHEN4_Msk (0x1ul << PDMA_CHCTL_CHEN4_Pos) /*!< PDMA_T::CHCTL: CHEN4 Mask */ + +#define PDMA_CHCTL_CHEN5_Pos (5) /*!< PDMA_T::CHCTL: CHEN5 Position */ +#define PDMA_CHCTL_CHEN5_Msk (0x1ul << PDMA_CHCTL_CHEN5_Pos) /*!< PDMA_T::CHCTL: CHEN5 Mask */ + +#define PDMA_CHCTL_CHEN6_Pos (6) /*!< PDMA_T::CHCTL: CHEN6 Position */ +#define PDMA_CHCTL_CHEN6_Msk (0x1ul << PDMA_CHCTL_CHEN6_Pos) /*!< PDMA_T::CHCTL: CHEN6 Mask */ + +#define PDMA_CHCTL_CHEN7_Pos (7) /*!< PDMA_T::CHCTL: CHEN7 Position */ +#define PDMA_CHCTL_CHEN7_Msk (0x1ul << PDMA_CHCTL_CHEN7_Pos) /*!< PDMA_T::CHCTL: CHEN7 Mask */ + +#define PDMA_CHCTL_CHEN8_Pos (8) /*!< PDMA_T::CHCTL: CHEN8 Position */ +#define PDMA_CHCTL_CHEN8_Msk (0x1ul << PDMA_CHCTL_CHEN8_Pos) /*!< PDMA_T::CHCTL: CHEN8 Mask */ + +#define PDMA_CHCTL_CHEN9_Pos (9) /*!< PDMA_T::CHCTL: CHEN9 Position */ +#define PDMA_CHCTL_CHEN9_Msk (0x1ul << PDMA_CHCTL_CHEN9_Pos) /*!< PDMA_T::CHCTL: CHEN9 Mask */ + +#define PDMA_CHCTL_CHEN10_Pos (10) /*!< PDMA_T::CHCTL: CHEN10 Position */ +#define PDMA_CHCTL_CHEN10_Msk (0x1ul << PDMA_CHCTL_CHEN10_Pos) /*!< PDMA_T::CHCTL: CHEN10 Mask */ + +#define PDMA_CHCTL_CHEN11_Pos (11) /*!< PDMA_T::CHCTL: CHEN11 Position */ +#define PDMA_CHCTL_CHEN11_Msk (0x1ul << PDMA_CHCTL_CHEN11_Pos) /*!< PDMA_T::CHCTL: CHEN11 Mask */ + +#define PDMA_CHCTL_CHEN12_Pos (12) /*!< PDMA_T::CHCTL: CHEN12 Position */ +#define PDMA_CHCTL_CHEN12_Msk (0x1ul << PDMA_CHCTL_CHEN12_Pos) /*!< PDMA_T::CHCTL: CHEN12 Mask */ + +#define PDMA_CHCTL_CHEN13_Pos (13) /*!< PDMA_T::CHCTL: CHEN13 Position */ +#define PDMA_CHCTL_CHEN13_Msk (0x1ul << PDMA_CHCTL_CHEN13_Pos) /*!< PDMA_T::CHCTL: CHEN13 Mask */ + +#define PDMA_CHCTL_CHEN14_Pos (14) /*!< PDMA_T::CHCTL: CHEN14 Position */ +#define PDMA_CHCTL_CHEN14_Msk (0x1ul << PDMA_CHCTL_CHEN14_Pos) /*!< PDMA_T::CHCTL: CHEN14 Mask */ + +#define PDMA_CHCTL_CHEN15_Pos (15) /*!< PDMA_T::CHCTL: CHEN15 Position */ +#define PDMA_CHCTL_CHEN15_Msk (0x1ul << PDMA_CHCTL_CHEN15_Pos) /*!< PDMA_T::CHCTL: CHEN15 Mask */ + +#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ +#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ + +#define PDMA_PAUSE_PAUSE0_Pos (0) /*!< PDMA_T::PAUSE: PAUSE0 Position */ +#define PDMA_PAUSE_PAUSE0_Msk (0x1ul << PDMA_PAUSE_PAUSE0_Pos) /*!< PDMA_T::PAUSE: PAUSE0 Mask */ + +#define PDMA_PAUSE_PAUSE1_Pos (1) /*!< PDMA_T::PAUSE: PAUSE1 Position */ +#define PDMA_PAUSE_PAUSE1_Msk (0x1ul << PDMA_PAUSE_PAUSE1_Pos) /*!< PDMA_T::PAUSE: PAUSE1 Mask */ + +#define PDMA_PAUSE_PAUSE2_Pos (2) /*!< PDMA_T::PAUSE: PAUSE2 Position */ +#define PDMA_PAUSE_PAUSE2_Msk (0x1ul << PDMA_PAUSE_PAUSE2_Pos) /*!< PDMA_T::PAUSE: PAUSE2 Mask */ + +#define PDMA_PAUSE_PAUSE3_Pos (3) /*!< PDMA_T::PAUSE: PAUSE3 Position */ +#define PDMA_PAUSE_PAUSE3_Msk (0x1ul << PDMA_PAUSE_PAUSE3_Pos) /*!< PDMA_T::PAUSE: PAUSE3 Mask */ + +#define PDMA_PAUSE_PAUSE4_Pos (4) /*!< PDMA_T::PAUSE: PAUSE4 Position */ +#define PDMA_PAUSE_PAUSE4_Msk (0x1ul << PDMA_PAUSE_PAUSE4_Pos) /*!< PDMA_T::PAUSE: PAUSE4 Mask */ + +#define PDMA_PAUSE_PAUSE5_Pos (5) /*!< PDMA_T::PAUSE: PAUSE5 Position */ +#define PDMA_PAUSE_PAUSE5_Msk (0x1ul << PDMA_PAUSE_PAUSE5_Pos) /*!< PDMA_T::PAUSE: PAUSE5 Mask */ + +#define PDMA_PAUSE_PAUSE6_Pos (6) /*!< PDMA_T::PAUSE: PAUSE6 Position */ +#define PDMA_PAUSE_PAUSE6_Msk (0x1ul << PDMA_PAUSE_PAUSE6_Pos) /*!< PDMA_T::PAUSE: PAUSE6 Mask */ + +#define PDMA_PAUSE_PAUSE7_Pos (7) /*!< PDMA_T::PAUSE: PAUSE7 Position */ +#define PDMA_PAUSE_PAUSE7_Msk (0x1ul << PDMA_PAUSE_PAUSE7_Pos) /*!< PDMA_T::PAUSE: PAUSE7 Mask */ + +#define PDMA_PAUSE_PAUSE8_Pos (8) /*!< PDMA_T::PAUSE: PAUSE8 Position */ +#define PDMA_PAUSE_PAUSE8_Msk (0x1ul << PDMA_PAUSE_PAUSE8_Pos) /*!< PDMA_T::PAUSE: PAUSE8 Mask */ + +#define PDMA_PAUSE_PAUSE9_Pos (9) /*!< PDMA_T::PAUSE: PAUSE9 Position */ +#define PDMA_PAUSE_PAUSE9_Msk (0x1ul << PDMA_PAUSE_PAUSE9_Pos) /*!< PDMA_T::PAUSE: PAUSE9 Mask */ + +#define PDMA_PAUSE_PAUSE10_Pos (10) /*!< PDMA_T::PAUSE: PAUSE10 Position */ +#define PDMA_PAUSE_PAUSE10_Msk (0x1ul << PDMA_PAUSE_PAUSE10_Pos) /*!< PDMA_T::PAUSE: PAUSE10 Mask */ + +#define PDMA_PAUSE_PAUSE11_Pos (11) /*!< PDMA_T::PAUSE: PAUSE11 Position */ +#define PDMA_PAUSE_PAUSE11_Msk (0x1ul << PDMA_PAUSE_PAUSE11_Pos) /*!< PDMA_T::PAUSE: PAUSE11 Mask */ + +#define PDMA_PAUSE_PAUSE12_Pos (12) /*!< PDMA_T::PAUSE: PAUSE12 Position */ +#define PDMA_PAUSE_PAUSE12_Msk (0x1ul << PDMA_PAUSE_PAUSE12_Pos) /*!< PDMA_T::PAUSE: PAUSE12 Mask */ + +#define PDMA_PAUSE_PAUSE13_Pos (13) /*!< PDMA_T::PAUSE: PAUSE13 Position */ +#define PDMA_PAUSE_PAUSE13_Msk (0x1ul << PDMA_PAUSE_PAUSE13_Pos) /*!< PDMA_T::PAUSE: PAUSE13 Mask */ + +#define PDMA_PAUSE_PAUSE14_Pos (14) /*!< PDMA_T::PAUSE: PAUSE14 Position */ +#define PDMA_PAUSE_PAUSE14_Msk (0x1ul << PDMA_PAUSE_PAUSE14_Pos) /*!< PDMA_T::PAUSE: PAUSE14 Mask */ + +#define PDMA_PAUSE_PAUSE15_Pos (15) /*!< PDMA_T::PAUSE: PAUSE15 Position */ +#define PDMA_PAUSE_PAUSE15_Msk (0x1ul << PDMA_PAUSE_PAUSE15_Pos) /*!< PDMA_T::PAUSE: PAUSE15 Mask */ + +#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ +#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ + +#define PDMA_SWREQ_SWREQ0_Pos (0) /*!< PDMA_T::SWREQ: SWREQ0 Position */ +#define PDMA_SWREQ_SWREQ0_Msk (0x1ul << PDMA_SWREQ_SWREQ0_Pos) /*!< PDMA_T::SWREQ: SWREQ0 Mask */ + +#define PDMA_SWREQ_SWREQ1_Pos (1) /*!< PDMA_T::SWREQ: SWREQ1 Position */ +#define PDMA_SWREQ_SWREQ1_Msk (0x1ul << PDMA_SWREQ_SWREQ1_Pos) /*!< PDMA_T::SWREQ: SWREQ1 Mask */ + +#define PDMA_SWREQ_SWREQ2_Pos (2) /*!< PDMA_T::SWREQ: SWREQ2 Position */ +#define PDMA_SWREQ_SWREQ2_Msk (0x1ul << PDMA_SWREQ_SWREQ2_Pos) /*!< PDMA_T::SWREQ: SWREQ2 Mask */ + +#define PDMA_SWREQ_SWREQ3_Pos (3) /*!< PDMA_T::SWREQ: SWREQ3 Position */ +#define PDMA_SWREQ_SWREQ3_Msk (0x1ul << PDMA_SWREQ_SWREQ3_Pos) /*!< PDMA_T::SWREQ: SWREQ3 Mask */ + +#define PDMA_SWREQ_SWREQ4_Pos (4) /*!< PDMA_T::SWREQ: SWREQ4 Position */ +#define PDMA_SWREQ_SWREQ4_Msk (0x1ul << PDMA_SWREQ_SWREQ4_Pos) /*!< PDMA_T::SWREQ: SWREQ4 Mask */ + +#define PDMA_SWREQ_SWREQ5_Pos (5) /*!< PDMA_T::SWREQ: SWREQ5 Position */ +#define PDMA_SWREQ_SWREQ5_Msk (0x1ul << PDMA_SWREQ_SWREQ5_Pos) /*!< PDMA_T::SWREQ: SWREQ5 Mask */ + +#define PDMA_SWREQ_SWREQ6_Pos (6) /*!< PDMA_T::SWREQ: SWREQ6 Position */ +#define PDMA_SWREQ_SWREQ6_Msk (0x1ul << PDMA_SWREQ_SWREQ6_Pos) /*!< PDMA_T::SWREQ: SWREQ6 Mask */ + +#define PDMA_SWREQ_SWREQ7_Pos (7) /*!< PDMA_T::SWREQ: SWREQ7 Position */ +#define PDMA_SWREQ_SWREQ7_Msk (0x1ul << PDMA_SWREQ_SWREQ7_Pos) /*!< PDMA_T::SWREQ: SWREQ7 Mask */ + +#define PDMA_SWREQ_SWREQ8_Pos (8) /*!< PDMA_T::SWREQ: SWREQ8 Position */ +#define PDMA_SWREQ_SWREQ8_Msk (0x1ul << PDMA_SWREQ_SWREQ8_Pos) /*!< PDMA_T::SWREQ: SWREQ8 Mask */ + +#define PDMA_SWREQ_SWREQ9_Pos (9) /*!< PDMA_T::SWREQ: SWREQ9 Position */ +#define PDMA_SWREQ_SWREQ9_Msk (0x1ul << PDMA_SWREQ_SWREQ9_Pos) /*!< PDMA_T::SWREQ: SWREQ9 Mask */ + +#define PDMA_SWREQ_SWREQ10_Pos (10) /*!< PDMA_T::SWREQ: SWREQ10 Position */ +#define PDMA_SWREQ_SWREQ10_Msk (0x1ul << PDMA_SWREQ_SWREQ10_Pos) /*!< PDMA_T::SWREQ: SWREQ10 Mask */ + +#define PDMA_SWREQ_SWREQ11_Pos (11) /*!< PDMA_T::SWREQ: SWREQ11 Position */ +#define PDMA_SWREQ_SWREQ11_Msk (0x1ul << PDMA_SWREQ_SWREQ11_Pos) /*!< PDMA_T::SWREQ: SWREQ11 Mask */ + +#define PDMA_SWREQ_SWREQ12_Pos (12) /*!< PDMA_T::SWREQ: SWREQ12 Position */ +#define PDMA_SWREQ_SWREQ12_Msk (0x1ul << PDMA_SWREQ_SWREQ12_Pos) /*!< PDMA_T::SWREQ: SWREQ12 Mask */ + +#define PDMA_SWREQ_SWREQ13_Pos (13) /*!< PDMA_T::SWREQ: SWREQ13 Position */ +#define PDMA_SWREQ_SWREQ13_Msk (0x1ul << PDMA_SWREQ_SWREQ13_Pos) /*!< PDMA_T::SWREQ: SWREQ13 Mask */ + +#define PDMA_SWREQ_SWREQ14_Pos (14) /*!< PDMA_T::SWREQ: SWREQ14 Position */ +#define PDMA_SWREQ_SWREQ14_Msk (0x1ul << PDMA_SWREQ_SWREQ14_Pos) /*!< PDMA_T::SWREQ: SWREQ14 Mask */ + +#define PDMA_SWREQ_SWREQ15_Pos (15) /*!< PDMA_T::SWREQ: SWREQ15 Position */ +#define PDMA_SWREQ_SWREQ15_Msk (0x1ul << PDMA_SWREQ_SWREQ15_Pos) /*!< PDMA_T::SWREQ: SWREQ15 Mask */ + +#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ +#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ + +#define PDMA_TRGSTS_REQSTS0_Pos (0) /*!< PDMA_T::TRGSTS: REQSTS0 Position */ +#define PDMA_TRGSTS_REQSTS0_Msk (0x1ul << PDMA_TRGSTS_REQSTS0_Pos) /*!< PDMA_T::TRGSTS: REQSTS0 Mask */ + +#define PDMA_TRGSTS_REQSTS1_Pos (1) /*!< PDMA_T::TRGSTS: REQSTS1 Position */ +#define PDMA_TRGSTS_REQSTS1_Msk (0x1ul << PDMA_TRGSTS_REQSTS1_Pos) /*!< PDMA_T::TRGSTS: REQSTS1 Mask */ + +#define PDMA_TRGSTS_REQSTS2_Pos (2) /*!< PDMA_T::TRGSTS: REQSTS2 Position */ +#define PDMA_TRGSTS_REQSTS2_Msk (0x1ul << PDMA_TRGSTS_REQSTS2_Pos) /*!< PDMA_T::TRGSTS: REQSTS2 Mask */ + +#define PDMA_TRGSTS_REQSTS3_Pos (3) /*!< PDMA_T::TRGSTS: REQSTS3 Position */ +#define PDMA_TRGSTS_REQSTS3_Msk (0x1ul << PDMA_TRGSTS_REQSTS3_Pos) /*!< PDMA_T::TRGSTS: REQSTS3 Mask */ + +#define PDMA_TRGSTS_REQSTS4_Pos (4) /*!< PDMA_T::TRGSTS: REQSTS4 Position */ +#define PDMA_TRGSTS_REQSTS4_Msk (0x1ul << PDMA_TRGSTS_REQSTS4_Pos) /*!< PDMA_T::TRGSTS: REQSTS4 Mask */ + +#define PDMA_TRGSTS_REQSTS5_Pos (5) /*!< PDMA_T::TRGSTS: REQSTS5 Position */ +#define PDMA_TRGSTS_REQSTS5_Msk (0x1ul << PDMA_TRGSTS_REQSTS5_Pos) /*!< PDMA_T::TRGSTS: REQSTS5 Mask */ + +#define PDMA_TRGSTS_REQSTS6_Pos (6) /*!< PDMA_T::TRGSTS: REQSTS6 Position */ +#define PDMA_TRGSTS_REQSTS6_Msk (0x1ul << PDMA_TRGSTS_REQSTS6_Pos) /*!< PDMA_T::TRGSTS: REQSTS6 Mask */ + +#define PDMA_TRGSTS_REQSTS7_Pos (7) /*!< PDMA_T::TRGSTS: REQSTS7 Position */ +#define PDMA_TRGSTS_REQSTS7_Msk (0x1ul << PDMA_TRGSTS_REQSTS7_Pos) /*!< PDMA_T::TRGSTS: REQSTS7 Mask */ + +#define PDMA_TRGSTS_REQSTS8_Pos (8) /*!< PDMA_T::TRGSTS: REQSTS8 Position */ +#define PDMA_TRGSTS_REQSTS8_Msk (0x1ul << PDMA_TRGSTS_REQSTS8_Pos) /*!< PDMA_T::TRGSTS: REQSTS8 Mask */ + +#define PDMA_TRGSTS_REQSTS9_Pos (9) /*!< PDMA_T::TRGSTS: REQSTS9 Position */ +#define PDMA_TRGSTS_REQSTS9_Msk (0x1ul << PDMA_TRGSTS_REQSTS9_Pos) /*!< PDMA_T::TRGSTS: REQSTS9 Mask */ + +#define PDMA_TRGSTS_REQSTS10_Pos (10) /*!< PDMA_T::TRGSTS: REQSTS10 Position */ +#define PDMA_TRGSTS_REQSTS10_Msk (0x1ul << PDMA_TRGSTS_REQSTS10_Pos) /*!< PDMA_T::TRGSTS: REQSTS10 Mask */ + +#define PDMA_TRGSTS_REQSTS11_Pos (11) /*!< PDMA_T::TRGSTS: REQSTS11 Position */ +#define PDMA_TRGSTS_REQSTS11_Msk (0x1ul << PDMA_TRGSTS_REQSTS11_Pos) /*!< PDMA_T::TRGSTS: REQSTS11 Mask */ + +#define PDMA_TRGSTS_REQSTS12_Pos (12) /*!< PDMA_T::TRGSTS: REQSTS12 Position */ +#define PDMA_TRGSTS_REQSTS12_Msk (0x1ul << PDMA_TRGSTS_REQSTS12_Pos) /*!< PDMA_T::TRGSTS: REQSTS12 Mask */ + +#define PDMA_TRGSTS_REQSTS13_Pos (13) /*!< PDMA_T::TRGSTS: REQSTS13 Position */ +#define PDMA_TRGSTS_REQSTS13_Msk (0x1ul << PDMA_TRGSTS_REQSTS13_Pos) /*!< PDMA_T::TRGSTS: REQSTS13 Mask */ + +#define PDMA_TRGSTS_REQSTS14_Pos (14) /*!< PDMA_T::TRGSTS: REQSTS14 Position */ +#define PDMA_TRGSTS_REQSTS14_Msk (0x1ul << PDMA_TRGSTS_REQSTS14_Pos) /*!< PDMA_T::TRGSTS: REQSTS14 Mask */ + +#define PDMA_TRGSTS_REQSTS15_Pos (15) /*!< PDMA_T::TRGSTS: REQSTS15 Position */ +#define PDMA_TRGSTS_REQSTS15_Msk (0x1ul << PDMA_TRGSTS_REQSTS15_Pos) /*!< PDMA_T::TRGSTS: REQSTS15 Mask */ + +#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ +#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ + +#define PDMA_PRISET_FPRISET0_Pos (0) /*!< PDMA_T::PRISET: FPRISET0 Position */ +#define PDMA_PRISET_FPRISET0_Msk (0x1ul << PDMA_PRISET_FPRISET0_Pos) /*!< PDMA_T::PRISET: FPRISET0 Mask */ + +#define PDMA_PRISET_FPRISET1_Pos (1) /*!< PDMA_T::PRISET: FPRISET1 Position */ +#define PDMA_PRISET_FPRISET1_Msk (0x1ul << PDMA_PRISET_FPRISET1_Pos) /*!< PDMA_T::PRISET: FPRISET1 Mask */ + +#define PDMA_PRISET_FPRISET2_Pos (2) /*!< PDMA_T::PRISET: FPRISET2 Position */ +#define PDMA_PRISET_FPRISET2_Msk (0x1ul << PDMA_PRISET_FPRISET2_Pos) /*!< PDMA_T::PRISET: FPRISET2 Mask */ + +#define PDMA_PRISET_FPRISET3_Pos (3) /*!< PDMA_T::PRISET: FPRISET3 Position */ +#define PDMA_PRISET_FPRISET3_Msk (0x1ul << PDMA_PRISET_FPRISET3_Pos) /*!< PDMA_T::PRISET: FPRISET3 Mask */ + +#define PDMA_PRISET_FPRISET4_Pos (4) /*!< PDMA_T::PRISET: FPRISET4 Position */ +#define PDMA_PRISET_FPRISET4_Msk (0x1ul << PDMA_PRISET_FPRISET4_Pos) /*!< PDMA_T::PRISET: FPRISET4 Mask */ + +#define PDMA_PRISET_FPRISET5_Pos (5) /*!< PDMA_T::PRISET: FPRISET5 Position */ +#define PDMA_PRISET_FPRISET5_Msk (0x1ul << PDMA_PRISET_FPRISET5_Pos) /*!< PDMA_T::PRISET: FPRISET5 Mask */ + +#define PDMA_PRISET_FPRISET6_Pos (6) /*!< PDMA_T::PRISET: FPRISET6 Position */ +#define PDMA_PRISET_FPRISET6_Msk (0x1ul << PDMA_PRISET_FPRISET6_Pos) /*!< PDMA_T::PRISET: FPRISET6 Mask */ + +#define PDMA_PRISET_FPRISET7_Pos (7) /*!< PDMA_T::PRISET: FPRISET7 Position */ +#define PDMA_PRISET_FPRISET7_Msk (0x1ul << PDMA_PRISET_FPRISET7_Pos) /*!< PDMA_T::PRISET: FPRISET7 Mask */ + +#define PDMA_PRISET_FPRISET8_Pos (8) /*!< PDMA_T::PRISET: FPRISET8 Position */ +#define PDMA_PRISET_FPRISET8_Msk (0x1ul << PDMA_PRISET_FPRISET8_Pos) /*!< PDMA_T::PRISET: FPRISET8 Mask */ + +#define PDMA_PRISET_FPRISET9_Pos (9) /*!< PDMA_T::PRISET: FPRISET9 Position */ +#define PDMA_PRISET_FPRISET9_Msk (0x1ul << PDMA_PRISET_FPRISET9_Pos) /*!< PDMA_T::PRISET: FPRISET9 Mask */ + +#define PDMA_PRISET_FPRISET10_Pos (10) /*!< PDMA_T::PRISET: FPRISET10 Position */ +#define PDMA_PRISET_FPRISET10_Msk (0x1ul << PDMA_PRISET_FPRISET10_Pos) /*!< PDMA_T::PRISET: FPRISET10 Mask */ + +#define PDMA_PRISET_FPRISET11_Pos (11) /*!< PDMA_T::PRISET: FPRISET11 Position */ +#define PDMA_PRISET_FPRISET11_Msk (0x1ul << PDMA_PRISET_FPRISET11_Pos) /*!< PDMA_T::PRISET: FPRISET11 Mask */ + +#define PDMA_PRISET_FPRISET12_Pos (12) /*!< PDMA_T::PRISET: FPRISET12 Position */ +#define PDMA_PRISET_FPRISET12_Msk (0x1ul << PDMA_PRISET_FPRISET12_Pos) /*!< PDMA_T::PRISET: FPRISET12 Mask */ + +#define PDMA_PRISET_FPRISET13_Pos (13) /*!< PDMA_T::PRISET: FPRISET13 Position */ +#define PDMA_PRISET_FPRISET13_Msk (0x1ul << PDMA_PRISET_FPRISET13_Pos) /*!< PDMA_T::PRISET: FPRISET13 Mask */ + +#define PDMA_PRISET_FPRISET14_Pos (14) /*!< PDMA_T::PRISET: FPRISET14 Position */ +#define PDMA_PRISET_FPRISET14_Msk (0x1ul << PDMA_PRISET_FPRISET14_Pos) /*!< PDMA_T::PRISET: FPRISET14 Mask */ + +#define PDMA_PRISET_FPRISET15_Pos (15) /*!< PDMA_T::PRISET: FPRISET15 Position */ +#define PDMA_PRISET_FPRISET15_Msk (0x1ul << PDMA_PRISET_FPRISET15_Pos) /*!< PDMA_T::PRISET: FPRISET15 Mask */ + +#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ +#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ + +#define PDMA_PRICLR_FPRICLR0_Pos (0) /*!< PDMA_T::PRICLR: FPRICLR0 Position */ +#define PDMA_PRICLR_FPRICLR0_Msk (0x1ul << PDMA_PRICLR_FPRICLR0_Pos) /*!< PDMA_T::PRICLR: FPRICLR0 Mask */ + +#define PDMA_PRICLR_FPRICLR1_Pos (1) /*!< PDMA_T::PRICLR: FPRICLR1 Position */ +#define PDMA_PRICLR_FPRICLR1_Msk (0x1ul << PDMA_PRICLR_FPRICLR1_Pos) /*!< PDMA_T::PRICLR: FPRICLR1 Mask */ + +#define PDMA_PRICLR_FPRICLR2_Pos (2) /*!< PDMA_T::PRICLR: FPRICLR2 Position */ +#define PDMA_PRICLR_FPRICLR2_Msk (0x1ul << PDMA_PRICLR_FPRICLR2_Pos) /*!< PDMA_T::PRICLR: FPRICLR2 Mask */ + +#define PDMA_PRICLR_FPRICLR3_Pos (3) /*!< PDMA_T::PRICLR: FPRICLR3 Position */ +#define PDMA_PRICLR_FPRICLR3_Msk (0x1ul << PDMA_PRICLR_FPRICLR3_Pos) /*!< PDMA_T::PRICLR: FPRICLR3 Mask */ + +#define PDMA_PRICLR_FPRICLR4_Pos (4) /*!< PDMA_T::PRICLR: FPRICLR4 Position */ +#define PDMA_PRICLR_FPRICLR4_Msk (0x1ul << PDMA_PRICLR_FPRICLR4_Pos) /*!< PDMA_T::PRICLR: FPRICLR4 Mask */ + +#define PDMA_PRICLR_FPRICLR5_Pos (5) /*!< PDMA_T::PRICLR: FPRICLR5 Position */ +#define PDMA_PRICLR_FPRICLR5_Msk (0x1ul << PDMA_PRICLR_FPRICLR5_Pos) /*!< PDMA_T::PRICLR: FPRICLR5 Mask */ + +#define PDMA_PRICLR_FPRICLR6_Pos (6) /*!< PDMA_T::PRICLR: FPRICLR6 Position */ +#define PDMA_PRICLR_FPRICLR6_Msk (0x1ul << PDMA_PRICLR_FPRICLR6_Pos) /*!< PDMA_T::PRICLR: FPRICLR6 Mask */ + +#define PDMA_PRICLR_FPRICLR7_Pos (7) /*!< PDMA_T::PRICLR: FPRICLR7 Position */ +#define PDMA_PRICLR_FPRICLR7_Msk (0x1ul << PDMA_PRICLR_FPRICLR7_Pos) /*!< PDMA_T::PRICLR: FPRICLR7 Mask */ + +#define PDMA_PRICLR_FPRICLR8_Pos (8) /*!< PDMA_T::PRICLR: FPRICLR8 Position */ +#define PDMA_PRICLR_FPRICLR8_Msk (0x1ul << PDMA_PRICLR_FPRICLR8_Pos) /*!< PDMA_T::PRICLR: FPRICLR8 Mask */ + +#define PDMA_PRICLR_FPRICLR9_Pos (9) /*!< PDMA_T::PRICLR: FPRICLR9 Position */ +#define PDMA_PRICLR_FPRICLR9_Msk (0x1ul << PDMA_PRICLR_FPRICLR9_Pos) /*!< PDMA_T::PRICLR: FPRICLR9 Mask */ + +#define PDMA_PRICLR_FPRICLR10_Pos (10) /*!< PDMA_T::PRICLR: FPRICLR10 Position */ +#define PDMA_PRICLR_FPRICLR10_Msk (0x1ul << PDMA_PRICLR_FPRICLR10_Pos) /*!< PDMA_T::PRICLR: FPRICLR10 Mask */ + +#define PDMA_PRICLR_FPRICLR11_Pos (11) /*!< PDMA_T::PRICLR: FPRICLR11 Position */ +#define PDMA_PRICLR_FPRICLR11_Msk (0x1ul << PDMA_PRICLR_FPRICLR11_Pos) /*!< PDMA_T::PRICLR: FPRICLR11 Mask */ + +#define PDMA_PRICLR_FPRICLR12_Pos (12) /*!< PDMA_T::PRICLR: FPRICLR12 Position */ +#define PDMA_PRICLR_FPRICLR12_Msk (0x1ul << PDMA_PRICLR_FPRICLR12_Pos) /*!< PDMA_T::PRICLR: FPRICLR12 Mask */ + +#define PDMA_PRICLR_FPRICLR13_Pos (13) /*!< PDMA_T::PRICLR: FPRICLR13 Position */ +#define PDMA_PRICLR_FPRICLR13_Msk (0x1ul << PDMA_PRICLR_FPRICLR13_Pos) /*!< PDMA_T::PRICLR: FPRICLR13 Mask */ + +#define PDMA_PRICLR_FPRICLR14_Pos (14) /*!< PDMA_T::PRICLR: FPRICLR14 Position */ +#define PDMA_PRICLR_FPRICLR14_Msk (0x1ul << PDMA_PRICLR_FPRICLR14_Pos) /*!< PDMA_T::PRICLR: FPRICLR14 Mask */ + +#define PDMA_PRICLR_FPRICLR15_Pos (15) /*!< PDMA_T::PRICLR: FPRICLR15 Position */ +#define PDMA_PRICLR_FPRICLR15_Msk (0x1ul << PDMA_PRICLR_FPRICLR15_Pos) /*!< PDMA_T::PRICLR: FPRICLR15 Mask */ + +#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ +#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ + +#define PDMA_INTEN_INTEN0_Pos (0) /*!< PDMA_T::INTEN: INTEN0 Position */ +#define PDMA_INTEN_INTEN0_Msk (0x1ul << PDMA_INTEN_INTEN0_Pos) /*!< PDMA_T::INTEN: INTEN0 Mask */ + +#define PDMA_INTEN_INTEN1_Pos (1) /*!< PDMA_T::INTEN: INTEN1 Position */ +#define PDMA_INTEN_INTEN1_Msk (0x1ul << PDMA_INTEN_INTEN1_Pos) /*!< PDMA_T::INTEN: INTEN1 Mask */ + +#define PDMA_INTEN_INTEN2_Pos (2) /*!< PDMA_T::INTEN: INTEN2 Position */ +#define PDMA_INTEN_INTEN2_Msk (0x1ul << PDMA_INTEN_INTEN2_Pos) /*!< PDMA_T::INTEN: INTEN2 Mask */ + +#define PDMA_INTEN_INTEN3_Pos (3) /*!< PDMA_T::INTEN: INTEN3 Position */ +#define PDMA_INTEN_INTEN3_Msk (0x1ul << PDMA_INTEN_INTEN3_Pos) /*!< PDMA_T::INTEN: INTEN3 Mask */ + +#define PDMA_INTEN_INTEN4_Pos (4) /*!< PDMA_T::INTEN: INTEN4 Position */ +#define PDMA_INTEN_INTEN4_Msk (0x1ul << PDMA_INTEN_INTEN4_Pos) /*!< PDMA_T::INTEN: INTEN4 Mask */ + +#define PDMA_INTEN_INTEN5_Pos (5) /*!< PDMA_T::INTEN: INTEN5 Position */ +#define PDMA_INTEN_INTEN5_Msk (0x1ul << PDMA_INTEN_INTEN5_Pos) /*!< PDMA_T::INTEN: INTEN5 Mask */ + +#define PDMA_INTEN_INTEN6_Pos (6) /*!< PDMA_T::INTEN: INTEN6 Position */ +#define PDMA_INTEN_INTEN6_Msk (0x1ul << PDMA_INTEN_INTEN6_Pos) /*!< PDMA_T::INTEN: INTEN6 Mask */ + +#define PDMA_INTEN_INTEN7_Pos (7) /*!< PDMA_T::INTEN: INTEN7 Position */ +#define PDMA_INTEN_INTEN7_Msk (0x1ul << PDMA_INTEN_INTEN7_Pos) /*!< PDMA_T::INTEN: INTEN7 Mask */ + +#define PDMA_INTEN_INTEN8_Pos (8) /*!< PDMA_T::INTEN: INTEN8 Position */ +#define PDMA_INTEN_INTEN8_Msk (0x1ul << PDMA_INTEN_INTEN8_Pos) /*!< PDMA_T::INTEN: INTEN8 Mask */ + +#define PDMA_INTEN_INTEN9_Pos (9) /*!< PDMA_T::INTEN: INTEN9 Position */ +#define PDMA_INTEN_INTEN9_Msk (0x1ul << PDMA_INTEN_INTEN9_Pos) /*!< PDMA_T::INTEN: INTEN9 Mask */ + +#define PDMA_INTEN_INTEN10_Pos (10) /*!< PDMA_T::INTEN: INTEN10 Position */ +#define PDMA_INTEN_INTEN10_Msk (0x1ul << PDMA_INTEN_INTEN10_Pos) /*!< PDMA_T::INTEN: INTEN10 Mask */ + +#define PDMA_INTEN_INTEN11_Pos (11) /*!< PDMA_T::INTEN: INTEN11 Position */ +#define PDMA_INTEN_INTEN11_Msk (0x1ul << PDMA_INTEN_INTEN11_Pos) /*!< PDMA_T::INTEN: INTEN11 Mask */ + +#define PDMA_INTEN_INTEN12_Pos (12) /*!< PDMA_T::INTEN: INTEN12 Position */ +#define PDMA_INTEN_INTEN12_Msk (0x1ul << PDMA_INTEN_INTEN12_Pos) /*!< PDMA_T::INTEN: INTEN12 Mask */ + +#define PDMA_INTEN_INTEN13_Pos (13) /*!< PDMA_T::INTEN: INTEN13 Position */ +#define PDMA_INTEN_INTEN13_Msk (0x1ul << PDMA_INTEN_INTEN13_Pos) /*!< PDMA_T::INTEN: INTEN13 Mask */ + +#define PDMA_INTEN_INTEN14_Pos (14) /*!< PDMA_T::INTEN: INTEN14 Position */ +#define PDMA_INTEN_INTEN14_Msk (0x1ul << PDMA_INTEN_INTEN14_Pos) /*!< PDMA_T::INTEN: INTEN14 Mask */ + +#define PDMA_INTEN_INTEN15_Pos (15) /*!< PDMA_T::INTEN: INTEN15 Position */ +#define PDMA_INTEN_INTEN15_Msk (0x1ul << PDMA_INTEN_INTEN15_Pos) /*!< PDMA_T::INTEN: INTEN15 Mask */ + +#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ +#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ + +#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ +#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ + +#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ +#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ + +#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ +#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ + +#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ +#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ + +#define PDMA_INTSTS_REQTOF2_Pos (10) /*!< PDMA_T::INTSTS: REQTOF2 Position */ +#define PDMA_INTSTS_REQTOF2_Msk (0x1ul << PDMA_INTSTS_REQTOF2_Pos) /*!< PDMA_T::INTSTS: REQTOF2 Mask */ + +#define PDMA_INTSTS_REQTOF3_Pos (11) /*!< PDMA_T::INTSTS: REQTOF3 Position */ +#define PDMA_INTSTS_REQTOF3_Msk (0x1ul << PDMA_INTSTS_REQTOF3_Pos) /*!< PDMA_T::INTSTS: REQTOF3 Mask */ + +#define PDMA_INTSTS_REQTOF4_Pos (12) /*!< PDMA_T::INTSTS: REQTOF4 Position */ +#define PDMA_INTSTS_REQTOF4_Msk (0x1ul << PDMA_INTSTS_REQTOF4_Pos) /*!< PDMA_T::INTSTS: REQTOF4 Mask */ + +#define PDMA_INTSTS_REQTOF5_Pos (13) /*!< PDMA_T::INTSTS: REQTOF5 Position */ +#define PDMA_INTSTS_REQTOF5_Msk (0x1ul << PDMA_INTSTS_REQTOF5_Pos) /*!< PDMA_T::INTSTS: REQTOF5 Mask */ + +#define PDMA_INTSTS_REQTOF6_Pos (14) /*!< PDMA_T::INTSTS: REQTOF6 Position */ +#define PDMA_INTSTS_REQTOF6_Msk (0x1ul << PDMA_INTSTS_REQTOF6_Pos) /*!< PDMA_T::INTSTS: REQTOF6 Mask */ + +#define PDMA_INTSTS_REQTOF7_Pos (15) /*!< PDMA_T::INTSTS: REQTOF7 Position */ +#define PDMA_INTSTS_REQTOF7_Msk (0x1ul << PDMA_INTSTS_REQTOF7_Pos) /*!< PDMA_T::INTSTS: REQTOF7 Mask */ + +#define PDMA_INTSTS_REQTOF8_Pos (16) /*!< PDMA_T::INTSTS: REQTOF8 Position */ +#define PDMA_INTSTS_REQTOF8_Msk (0x1ul << PDMA_INTSTS_REQTOF8_Pos) /*!< PDMA_T::INTSTS: REQTOF8 Mask */ + +#define PDMA_INTSTS_REQTOF9_Pos (17) /*!< PDMA_T::INTSTS: REQTOF9 Position */ +#define PDMA_INTSTS_REQTOF9_Msk (0x1ul << PDMA_INTSTS_REQTOF9_Pos) /*!< PDMA_T::INTSTS: REQTOF9 Mask */ + +#define PDMA_INTSTS_REQTOF10_Pos (18) /*!< PDMA_T::INTSTS: REQTOF10 Position */ +#define PDMA_INTSTS_REQTOF10_Msk (0x1ul << PDMA_INTSTS_REQTOF10_Pos) /*!< PDMA_T::INTSTS: REQTOF10 Mask */ + +#define PDMA_INTSTS_REQTOF11_Pos (19) /*!< PDMA_T::INTSTS: REQTOF11 Position */ +#define PDMA_INTSTS_REQTOF11_Msk (0x1ul << PDMA_INTSTS_REQTOF11_Pos) /*!< PDMA_T::INTSTS: REQTOF11 Mask */ + +#define PDMA_INTSTS_REQTOF12_Pos (20) /*!< PDMA_T::INTSTS: REQTOF12 Position */ +#define PDMA_INTSTS_REQTOF12_Msk (0x1ul << PDMA_INTSTS_REQTOF12_Pos) /*!< PDMA_T::INTSTS: REQTOF12 Mask */ + +#define PDMA_INTSTS_REQTOF13_Pos (21) /*!< PDMA_T::INTSTS: REQTOF13 Position */ +#define PDMA_INTSTS_REQTOF13_Msk (0x1ul << PDMA_INTSTS_REQTOF13_Pos) /*!< PDMA_T::INTSTS: REQTOF13 Mask */ + +#define PDMA_INTSTS_REQTOF14_Pos (22) /*!< PDMA_T::INTSTS: REQTOF14 Position */ +#define PDMA_INTSTS_REQTOF14_Msk (0x1ul << PDMA_INTSTS_REQTOF14_Pos) /*!< PDMA_T::INTSTS: REQTOF14 Mask */ + +#define PDMA_INTSTS_REQTOF15_Pos (23) /*!< PDMA_T::INTSTS: REQTOF15 Position */ +#define PDMA_INTSTS_REQTOF15_Msk (0x1ul << PDMA_INTSTS_REQTOF15_Pos) /*!< PDMA_T::INTSTS: REQTOF15 Mask */ + +#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ +#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ + +#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ +#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ + +#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ +#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ + +#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ +#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ + +#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ +#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ + +#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ +#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ + +#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ +#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ + +#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ +#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ + +#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ +#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ + +#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ +#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ + +#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ +#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ + +#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ +#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ + +#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ +#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ + +#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ +#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ + +#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ +#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ + +#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ +#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ + +#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ +#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ + +#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ +#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ + +#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ +#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ + +#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ +#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ + +#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ +#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ + +#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ +#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ + +#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ +#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ + +#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ +#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ + +#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ +#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ + +#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ +#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ + +#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ +#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ + +#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ +#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ + +#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ +#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ + +#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ +#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ + +#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ +#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ + +#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ +#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ + +#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ +#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ + +#define PDMA_ALIGN_ALIGN0_Pos (0) /*!< PDMA_T::ALIGN: ALIGN0 Position */ +#define PDMA_ALIGN_ALIGN0_Msk (0x1ul << PDMA_ALIGN_ALIGN0_Pos) /*!< PDMA_T::ALIGN: ALIGN0 Mask */ + +#define PDMA_ALIGN_ALIGN1_Pos (1) /*!< PDMA_T::ALIGN: ALIGN1 Position */ +#define PDMA_ALIGN_ALIGN1_Msk (0x1ul << PDMA_ALIGN_ALIGN1_Pos) /*!< PDMA_T::ALIGN: ALIGN1 Mask */ + +#define PDMA_ALIGN_ALIGN2_Pos (2) /*!< PDMA_T::ALIGN: ALIGN2 Position */ +#define PDMA_ALIGN_ALIGN2_Msk (0x1ul << PDMA_ALIGN_ALIGN2_Pos) /*!< PDMA_T::ALIGN: ALIGN2 Mask */ + +#define PDMA_ALIGN_ALIGN3_Pos (3) /*!< PDMA_T::ALIGN: ALIGN3 Position */ +#define PDMA_ALIGN_ALIGN3_Msk (0x1ul << PDMA_ALIGN_ALIGN3_Pos) /*!< PDMA_T::ALIGN: ALIGN3 Mask */ + +#define PDMA_ALIGN_ALIGN4_Pos (4) /*!< PDMA_T::ALIGN: ALIGN4 Position */ +#define PDMA_ALIGN_ALIGN4_Msk (0x1ul << PDMA_ALIGN_ALIGN4_Pos) /*!< PDMA_T::ALIGN: ALIGN4 Mask */ + +#define PDMA_ALIGN_ALIGN5_Pos (5) /*!< PDMA_T::ALIGN: ALIGN5 Position */ +#define PDMA_ALIGN_ALIGN5_Msk (0x1ul << PDMA_ALIGN_ALIGN5_Pos) /*!< PDMA_T::ALIGN: ALIGN5 Mask */ + +#define PDMA_ALIGN_ALIGN6_Pos (6) /*!< PDMA_T::ALIGN: ALIGN6 Position */ +#define PDMA_ALIGN_ALIGN6_Msk (0x1ul << PDMA_ALIGN_ALIGN6_Pos) /*!< PDMA_T::ALIGN: ALIGN6 Mask */ + +#define PDMA_ALIGN_ALIGN7_Pos (7) /*!< PDMA_T::ALIGN: ALIGN7 Position */ +#define PDMA_ALIGN_ALIGN7_Msk (0x1ul << PDMA_ALIGN_ALIGN7_Pos) /*!< PDMA_T::ALIGN: ALIGN7 Mask */ + +#define PDMA_ALIGN_ALIGN8_Pos (8) /*!< PDMA_T::ALIGN: ALIGN8 Position */ +#define PDMA_ALIGN_ALIGN8_Msk (0x1ul << PDMA_ALIGN_ALIGN8_Pos) /*!< PDMA_T::ALIGN: ALIGN8 Mask */ + +#define PDMA_ALIGN_ALIGN9_Pos (9) /*!< PDMA_T::ALIGN: ALIGN9 Position */ +#define PDMA_ALIGN_ALIGN9_Msk (0x1ul << PDMA_ALIGN_ALIGN9_Pos) /*!< PDMA_T::ALIGN: ALIGN9 Mask */ + +#define PDMA_ALIGN_ALIGN10_Pos (10) /*!< PDMA_T::ALIGN: ALIGN10 Position */ +#define PDMA_ALIGN_ALIGN10_Msk (0x1ul << PDMA_ALIGN_ALIGN10_Pos) /*!< PDMA_T::ALIGN: ALIGN10 Mask */ + +#define PDMA_ALIGN_ALIGN11_Pos (11) /*!< PDMA_T::ALIGN: ALIGN11 Position */ +#define PDMA_ALIGN_ALIGN11_Msk (0x1ul << PDMA_ALIGN_ALIGN11_Pos) /*!< PDMA_T::ALIGN: ALIGN11 Mask */ + +#define PDMA_ALIGN_ALIGN12_Pos (12) /*!< PDMA_T::ALIGN: ALIGN12 Position */ +#define PDMA_ALIGN_ALIGN12_Msk (0x1ul << PDMA_ALIGN_ALIGN12_Pos) /*!< PDMA_T::ALIGN: ALIGN12 Mask */ + +#define PDMA_ALIGN_ALIGN13_Pos (13) /*!< PDMA_T::ALIGN: ALIGN13 Position */ +#define PDMA_ALIGN_ALIGN13_Msk (0x1ul << PDMA_ALIGN_ALIGN13_Pos) /*!< PDMA_T::ALIGN: ALIGN13 Mask */ + +#define PDMA_ALIGN_ALIGN14_Pos (14) /*!< PDMA_T::ALIGN: ALIGN14 Position */ +#define PDMA_ALIGN_ALIGN14_Msk (0x1ul << PDMA_ALIGN_ALIGN14_Pos) /*!< PDMA_T::ALIGN: ALIGN14 Mask */ + +#define PDMA_ALIGN_ALIGN15_Pos (15) /*!< PDMA_T::ALIGN: ALIGN15 Position */ +#define PDMA_ALIGN_ALIGN15_Msk (0x1ul << PDMA_ALIGN_ALIGN15_Pos) /*!< PDMA_T::ALIGN: ALIGN15 Mask */ + +#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ +#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ + +#define PDMA_TACTSTS_TXACTF0_Pos (0) /*!< PDMA_T::TACTSTS: TXACTF0 Position */ +#define PDMA_TACTSTS_TXACTF0_Msk (0x1ul << PDMA_TACTSTS_TXACTF0_Pos) /*!< PDMA_T::TACTSTS: TXACTF0 Mask */ + +#define PDMA_TACTSTS_TXACTF1_Pos (1) /*!< PDMA_T::TACTSTS: TXACTF1 Position */ +#define PDMA_TACTSTS_TXACTF1_Msk (0x1ul << PDMA_TACTSTS_TXACTF1_Pos) /*!< PDMA_T::TACTSTS: TXACTF1 Mask */ + +#define PDMA_TACTSTS_TXACTF2_Pos (2) /*!< PDMA_T::TACTSTS: TXACTF2 Position */ +#define PDMA_TACTSTS_TXACTF2_Msk (0x1ul << PDMA_TACTSTS_TXACTF2_Pos) /*!< PDMA_T::TACTSTS: TXACTF2 Mask */ + +#define PDMA_TACTSTS_TXACTF3_Pos (3) /*!< PDMA_T::TACTSTS: TXACTF3 Position */ +#define PDMA_TACTSTS_TXACTF3_Msk (0x1ul << PDMA_TACTSTS_TXACTF3_Pos) /*!< PDMA_T::TACTSTS: TXACTF3 Mask */ + +#define PDMA_TACTSTS_TXACTF4_Pos (4) /*!< PDMA_T::TACTSTS: TXACTF4 Position */ +#define PDMA_TACTSTS_TXACTF4_Msk (0x1ul << PDMA_TACTSTS_TXACTF4_Pos) /*!< PDMA_T::TACTSTS: TXACTF4 Mask */ + +#define PDMA_TACTSTS_TXACTF5_Pos (5) /*!< PDMA_T::TACTSTS: TXACTF5 Position */ +#define PDMA_TACTSTS_TXACTF5_Msk (0x1ul << PDMA_TACTSTS_TXACTF5_Pos) /*!< PDMA_T::TACTSTS: TXACTF5 Mask */ + +#define PDMA_TACTSTS_TXACTF6_Pos (6) /*!< PDMA_T::TACTSTS: TXACTF6 Position */ +#define PDMA_TACTSTS_TXACTF6_Msk (0x1ul << PDMA_TACTSTS_TXACTF6_Pos) /*!< PDMA_T::TACTSTS: TXACTF6 Mask */ + +#define PDMA_TACTSTS_TXACTF7_Pos (7) /*!< PDMA_T::TACTSTS: TXACTF7 Position */ +#define PDMA_TACTSTS_TXACTF7_Msk (0x1ul << PDMA_TACTSTS_TXACTF7_Pos) /*!< PDMA_T::TACTSTS: TXACTF7 Mask */ + +#define PDMA_TACTSTS_TXACTF8_Pos (8) /*!< PDMA_T::TACTSTS: TXACTF8 Position */ +#define PDMA_TACTSTS_TXACTF8_Msk (0x1ul << PDMA_TACTSTS_TXACTF8_Pos) /*!< PDMA_T::TACTSTS: TXACTF8 Mask */ + +#define PDMA_TACTSTS_TXACTF9_Pos (9) /*!< PDMA_T::TACTSTS: TXACTF9 Position */ +#define PDMA_TACTSTS_TXACTF9_Msk (0x1ul << PDMA_TACTSTS_TXACTF9_Pos) /*!< PDMA_T::TACTSTS: TXACTF9 Mask */ + +#define PDMA_TACTSTS_TXACTF10_Pos (10) /*!< PDMA_T::TACTSTS: TXACTF10 Position */ +#define PDMA_TACTSTS_TXACTF10_Msk (0x1ul << PDMA_TACTSTS_TXACTF10_Pos) /*!< PDMA_T::TACTSTS: TXACTF10 Mask */ + +#define PDMA_TACTSTS_TXACTF11_Pos (11) /*!< PDMA_T::TACTSTS: TXACTF11 Position */ +#define PDMA_TACTSTS_TXACTF11_Msk (0x1ul << PDMA_TACTSTS_TXACTF11_Pos) /*!< PDMA_T::TACTSTS: TXACTF11 Mask */ + +#define PDMA_TACTSTS_TXACTF12_Pos (12) /*!< PDMA_T::TACTSTS: TXACTF12 Position */ +#define PDMA_TACTSTS_TXACTF12_Msk (0x1ul << PDMA_TACTSTS_TXACTF12_Pos) /*!< PDMA_T::TACTSTS: TXACTF12 Mask */ + +#define PDMA_TACTSTS_TXACTF13_Pos (13) /*!< PDMA_T::TACTSTS: TXACTF13 Position */ +#define PDMA_TACTSTS_TXACTF13_Msk (0x1ul << PDMA_TACTSTS_TXACTF13_Pos) /*!< PDMA_T::TACTSTS: TXACTF13 Mask */ + +#define PDMA_TACTSTS_TXACTF14_Pos (14) /*!< PDMA_T::TACTSTS: TXACTF14 Position */ +#define PDMA_TACTSTS_TXACTF14_Msk (0x1ul << PDMA_TACTSTS_TXACTF14_Pos) /*!< PDMA_T::TACTSTS: TXACTF14 Mask */ + +#define PDMA_TACTSTS_TXACTF15_Pos (15) /*!< PDMA_T::TACTSTS: TXACTF15 Position */ +#define PDMA_TACTSTS_TXACTF15_Msk (0x1ul << PDMA_TACTSTS_TXACTF15_Pos) /*!< PDMA_T::TACTSTS: TXACTF15 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC0 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC0 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC1 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC1 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC2_Pos (8) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC2 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC2_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC2_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC2 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC3_Pos (12) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC3 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC3_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC3_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC3 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC4_Pos (16) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC4 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC4_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC4_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC4 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC5_Pos (20) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC5 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC5_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC5_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC5 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC6_Pos (24) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC6 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC6_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC6_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC6 Mask */ + +#define PDMA_TOUTPSC0_7_TOUTPSC7_Pos (28) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC7 Position */ +#define PDMA_TOUTPSC0_7_TOUTPSC7_Msk (0x7ul << PDMA_TOUTPSC0_7_TOUTPSC7_Pos) /*!< PDMA_T::TOUTPSC0_7: TOUTPSC7 Mask */ + +#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ +#define PDMA_TOUTEN_TOUTENn_Msk (0xfffful << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ + +#define PDMA_TOUTEN_TOUTEN0_Pos (0) /*!< PDMA_T::TOUTEN: TOUTEN0 Position */ +#define PDMA_TOUTEN_TOUTEN0_Msk (0x1ul << PDMA_TOUTEN_TOUTEN0_Pos) /*!< PDMA_T::TOUTEN: TOUTEN0 Mask */ + +#define PDMA_TOUTEN_TOUTEN1_Pos (1) /*!< PDMA_T::TOUTEN: TOUTEN1 Position */ +#define PDMA_TOUTEN_TOUTEN1_Msk (0x1ul << PDMA_TOUTEN_TOUTEN1_Pos) /*!< PDMA_T::TOUTEN: TOUTEN1 Mask */ + +#define PDMA_TOUTEN_TOUTEN2_Pos (2) /*!< PDMA_T::TOUTEN: TOUTEN2 Position */ +#define PDMA_TOUTEN_TOUTEN2_Msk (0x1ul << PDMA_TOUTEN_TOUTEN2_Pos) /*!< PDMA_T::TOUTEN: TOUTEN2 Mask */ + +#define PDMA_TOUTEN_TOUTEN3_Pos (3) /*!< PDMA_T::TOUTEN: TOUTEN3 Position */ +#define PDMA_TOUTEN_TOUTEN3_Msk (0x1ul << PDMA_TOUTEN_TOUTEN3_Pos) /*!< PDMA_T::TOUTEN: TOUTEN3 Mask */ + +#define PDMA_TOUTEN_TOUTEN4_Pos (4) /*!< PDMA_T::TOUTEN: TOUTEN4 Position */ +#define PDMA_TOUTEN_TOUTEN4_Msk (0x1ul << PDMA_TOUTEN_TOUTEN4_Pos) /*!< PDMA_T::TOUTEN: TOUTEN4 Mask */ + +#define PDMA_TOUTEN_TOUTEN5_Pos (5) /*!< PDMA_T::TOUTEN: TOUTEN5 Position */ +#define PDMA_TOUTEN_TOUTEN5_Msk (0x1ul << PDMA_TOUTEN_TOUTEN5_Pos) /*!< PDMA_T::TOUTEN: TOUTEN5 Mask */ + +#define PDMA_TOUTEN_TOUTEN6_Pos (6) /*!< PDMA_T::TOUTEN: TOUTEN6 Position */ +#define PDMA_TOUTEN_TOUTEN6_Msk (0x1ul << PDMA_TOUTEN_TOUTEN6_Pos) /*!< PDMA_T::TOUTEN: TOUTEN6 Mask */ + +#define PDMA_TOUTEN_TOUTEN7_Pos (7) /*!< PDMA_T::TOUTEN: TOUTEN7 Position */ +#define PDMA_TOUTEN_TOUTEN7_Msk (0x1ul << PDMA_TOUTEN_TOUTEN7_Pos) /*!< PDMA_T::TOUTEN: TOUTEN7 Mask */ + +#define PDMA_TOUTEN_TOUTEN8_Pos (8) /*!< PDMA_T::TOUTEN: TOUTEN8 Position */ +#define PDMA_TOUTEN_TOUTEN8_Msk (0x1ul << PDMA_TOUTEN_TOUTEN8_Pos) /*!< PDMA_T::TOUTEN: TOUTEN8 Mask */ + +#define PDMA_TOUTEN_TOUTEN9_Pos (9) /*!< PDMA_T::TOUTEN: TOUTEN9 Position */ +#define PDMA_TOUTEN_TOUTEN9_Msk (0x1ul << PDMA_TOUTEN_TOUTEN9_Pos) /*!< PDMA_T::TOUTEN: TOUTEN9 Mask */ + +#define PDMA_TOUTEN_TOUTEN10_Pos (10) /*!< PDMA_T::TOUTEN: TOUTEN10 Position */ +#define PDMA_TOUTEN_TOUTEN10_Msk (0x1ul << PDMA_TOUTEN_TOUTEN10_Pos) /*!< PDMA_T::TOUTEN: TOUTEN10 Mask */ + +#define PDMA_TOUTEN_TOUTEN11_Pos (11) /*!< PDMA_T::TOUTEN: TOUTEN11 Position */ +#define PDMA_TOUTEN_TOUTEN11_Msk (0x1ul << PDMA_TOUTEN_TOUTEN11_Pos) /*!< PDMA_T::TOUTEN: TOUTEN11 Mask */ + +#define PDMA_TOUTEN_TOUTEN12_Pos (12) /*!< PDMA_T::TOUTEN: TOUTEN12 Position */ +#define PDMA_TOUTEN_TOUTEN12_Msk (0x1ul << PDMA_TOUTEN_TOUTEN12_Pos) /*!< PDMA_T::TOUTEN: TOUTEN12 Mask */ + +#define PDMA_TOUTEN_TOUTEN13_Pos (13) /*!< PDMA_T::TOUTEN: TOUTEN13 Position */ +#define PDMA_TOUTEN_TOUTEN13_Msk (0x1ul << PDMA_TOUTEN_TOUTEN13_Pos) /*!< PDMA_T::TOUTEN: TOUTEN13 Mask */ + +#define PDMA_TOUTEN_TOUTEN14_Pos (14) /*!< PDMA_T::TOUTEN: TOUTEN14 Position */ +#define PDMA_TOUTEN_TOUTEN14_Msk (0x1ul << PDMA_TOUTEN_TOUTEN14_Pos) /*!< PDMA_T::TOUTEN: TOUTEN14 Mask */ + +#define PDMA_TOUTEN_TOUTEN15_Pos (15) /*!< PDMA_T::TOUTEN: TOUTEN15 Position */ +#define PDMA_TOUTEN_TOUTEN15_Msk (0x1ul << PDMA_TOUTEN_TOUTEN15_Pos) /*!< PDMA_T::TOUTEN: TOUTEN15 Mask */ + +#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ +#define PDMA_TOUTIEN_TOUTIENn_Msk (0xfffful << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ + +#define PDMA_TOUTIEN_TOUTIEN0_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIEN0 Position */ +#define PDMA_TOUTIEN_TOUTIEN0_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN0_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN0 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN1_Pos (1) /*!< PDMA_T::TOUTIEN: TOUTIEN1 Position */ +#define PDMA_TOUTIEN_TOUTIEN1_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN1_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN1 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN2_Pos (2) /*!< PDMA_T::TOUTIEN: TOUTIEN2 Position */ +#define PDMA_TOUTIEN_TOUTIEN2_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN2_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN2 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN3_Pos (3) /*!< PDMA_T::TOUTIEN: TOUTIEN3 Position */ +#define PDMA_TOUTIEN_TOUTIEN3_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN3_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN3 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN4_Pos (4) /*!< PDMA_T::TOUTIEN: TOUTIEN4 Position */ +#define PDMA_TOUTIEN_TOUTIEN4_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN4_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN4 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN5_Pos (5) /*!< PDMA_T::TOUTIEN: TOUTIEN5 Position */ +#define PDMA_TOUTIEN_TOUTIEN5_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN5_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN5 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN6_Pos (6) /*!< PDMA_T::TOUTIEN: TOUTIEN6 Position */ +#define PDMA_TOUTIEN_TOUTIEN6_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN6_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN6 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN7_Pos (7) /*!< PDMA_T::TOUTIEN: TOUTIEN7 Position */ +#define PDMA_TOUTIEN_TOUTIEN7_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN7_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN7 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN8_Pos (8) /*!< PDMA_T::TOUTIEN: TOUTIEN8 Position */ +#define PDMA_TOUTIEN_TOUTIEN8_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN8_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN8 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN9_Pos (9) /*!< PDMA_T::TOUTIEN: TOUTIEN9 Position */ +#define PDMA_TOUTIEN_TOUTIEN9_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN9_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN9 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN10_Pos (10) /*!< PDMA_T::TOUTIEN: TOUTIEN10 Position */ +#define PDMA_TOUTIEN_TOUTIEN10_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN10_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN10 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN11_Pos (11) /*!< PDMA_T::TOUTIEN: TOUTIEN11 Position */ +#define PDMA_TOUTIEN_TOUTIEN11_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN11_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN11 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN12_Pos (12) /*!< PDMA_T::TOUTIEN: TOUTIEN12 Position */ +#define PDMA_TOUTIEN_TOUTIEN12_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN12_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN12 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN13_Pos (13) /*!< PDMA_T::TOUTIEN: TOUTIEN13 Position */ +#define PDMA_TOUTIEN_TOUTIEN13_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN13_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN13 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN14_Pos (14) /*!< PDMA_T::TOUTIEN: TOUTIEN14 Position */ +#define PDMA_TOUTIEN_TOUTIEN14_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN14_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN14 Mask */ + +#define PDMA_TOUTIEN_TOUTIEN15_Pos (15) /*!< PDMA_T::TOUTIEN: TOUTIEN15 Position */ +#define PDMA_TOUTIEN_TOUTIEN15_Msk (0x1ul << PDMA_TOUTIEN_TOUTIEN15_Pos) /*!< PDMA_T::TOUTIEN: TOUTIEN15 Mask */ + +#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ +#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ + +#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ +#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ + +#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ +#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ + +#define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA_T::TOC2_3: TOC2 Position */ +#define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA_T::TOC2_3: TOC2 Mask */ + +#define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA_T::TOC2_3: TOC3 Position */ +#define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA_T::TOC2_3: TOC3 Mask */ + +#define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA_T::TOC4_5: TOC4 Position */ +#define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA_T::TOC4_5: TOC4 Mask */ + +#define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA_T::TOC4_5: TOC5 Position */ +#define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA_T::TOC4_5: TOC5 Mask */ + +#define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA_T::TOC6_7: TOC6 Position */ +#define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA_T::TOC6_7: TOC6 Mask */ + +#define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA_T::TOC6_7: TOC7 Position */ +#define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA_T::TOC6_7: TOC7 Mask */ + +#define PDMA_TOC8_9_TOC8_Pos (0) /*!< PDMA_T::TOC8_9: TOC8 Position */ +#define PDMA_TOC8_9_TOC8_Msk (0xfffful << PDMA_TOC8_9_TOC8_Pos) /*!< PDMA_T::TOC8_9: TOC8 Mask */ + +#define PDMA_TOC8_9_TOC9_Pos (16) /*!< PDMA_T::TOC8_9: TOC9 Position */ +#define PDMA_TOC8_9_TOC9_Msk (0xfffful << PDMA_TOC8_9_TOC9_Pos) /*!< PDMA_T::TOC8_9: TOC9 Mask */ + +#define PDMA_TOC10_11_TOC10_Pos (0) /*!< PDMA_T::TOC10_11: TOC10 Position */ +#define PDMA_TOC10_11_TOC10_Msk (0xfffful << PDMA_TOC10_11_TOC10_Pos) /*!< PDMA_T::TOC10_11: TOC10 Mask */ + +#define PDMA_TOC10_11_TOC11_Pos (16) /*!< PDMA_T::TOC10_11: TOC11 Position */ +#define PDMA_TOC10_11_TOC11_Msk (0xfffful << PDMA_TOC10_11_TOC11_Pos) /*!< PDMA_T::TOC10_11: TOC11 Mask */ + +#define PDMA_TOC12_13_TOC12_Pos (0) /*!< PDMA_T::TOC12_13: TOC12 Position */ +#define PDMA_TOC12_13_TOC12_Msk (0xfffful << PDMA_TOC12_13_TOC12_Pos) /*!< PDMA_T::TOC12_13: TOC12 Mask */ + +#define PDMA_TOC12_13_TOC13_Pos (16) /*!< PDMA_T::TOC12_13: TOC13 Position */ +#define PDMA_TOC12_13_TOC13_Msk (0xfffful << PDMA_TOC12_13_TOC13_Pos) /*!< PDMA_T::TOC12_13: TOC13 Mask */ + +#define PDMA_TOC14_15_TOC14_Pos (0) /*!< PDMA_T::TOC14_15: TOC14 Position */ +#define PDMA_TOC14_15_TOC14_Msk (0xfffful << PDMA_TOC14_15_TOC14_Pos) /*!< PDMA_T::TOC14_15: TOC14 Mask */ + +#define PDMA_TOC14_15_TOC15_Pos (16) /*!< PDMA_T::TOC14_15: TOC15 Position */ +#define PDMA_TOC14_15_TOC15_Msk (0xfffful << PDMA_TOC14_15_TOC15_Pos) /*!< PDMA_T::TOC14_15: TOC15 Mask */ + +#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ +#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ + +#define PDMA_CHRST_CH0RST_Pos (0) /*!< PDMA_T::CHRST: CH0RST Position */ +#define PDMA_CHRST_CH0RST_Msk (0x1ul << PDMA_CHRST_CH0RST_Pos) /*!< PDMA_T::CHRST: CH0RST Mask */ + +#define PDMA_CHRST_CH1RST_Pos (1) /*!< PDMA_T::CHRST: CH1RST Position */ +#define PDMA_CHRST_CH1RST_Msk (0x1ul << PDMA_CHRST_CH1RST_Pos) /*!< PDMA_T::CHRST: CH1RST Mask */ + +#define PDMA_CHRST_CH2RST_Pos (2) /*!< PDMA_T::CHRST: CH2RST Position */ +#define PDMA_CHRST_CH2RST_Msk (0x1ul << PDMA_CHRST_CH2RST_Pos) /*!< PDMA_T::CHRST: CH2RST Mask */ + +#define PDMA_CHRST_CH3RST_Pos (3) /*!< PDMA_T::CHRST: CH3RST Position */ +#define PDMA_CHRST_CH3RST_Msk (0x1ul << PDMA_CHRST_CH3RST_Pos) /*!< PDMA_T::CHRST: CH3RST Mask */ + +#define PDMA_CHRST_CH4RST_Pos (4) /*!< PDMA_T::CHRST: CH4RST Position */ +#define PDMA_CHRST_CH4RST_Msk (0x1ul << PDMA_CHRST_CH4RST_Pos) /*!< PDMA_T::CHRST: CH4RST Mask */ + +#define PDMA_CHRST_CH5RST_Pos (5) /*!< PDMA_T::CHRST: CH5RST Position */ +#define PDMA_CHRST_CH5RST_Msk (0x1ul << PDMA_CHRST_CH5RST_Pos) /*!< PDMA_T::CHRST: CH5RST Mask */ + +#define PDMA_CHRST_CH6RST_Pos (6) /*!< PDMA_T::CHRST: CH6RST Position */ +#define PDMA_CHRST_CH6RST_Msk (0x1ul << PDMA_CHRST_CH6RST_Pos) /*!< PDMA_T::CHRST: CH6RST Mask */ + +#define PDMA_CHRST_CH7RST_Pos (7) /*!< PDMA_T::CHRST: CH7RST Position */ +#define PDMA_CHRST_CH7RST_Msk (0x1ul << PDMA_CHRST_CH7RST_Pos) /*!< PDMA_T::CHRST: CH7RST Mask */ + +#define PDMA_CHRST_CH8RST_Pos (8) /*!< PDMA_T::CHRST: CH8RST Position */ +#define PDMA_CHRST_CH8RST_Msk (0x1ul << PDMA_CHRST_CH8RST_Pos) /*!< PDMA_T::CHRST: CH8RST Mask */ + +#define PDMA_CHRST_CH9RST_Pos (9) /*!< PDMA_T::CHRST: CH9RST Position */ +#define PDMA_CHRST_CH9RST_Msk (0x1ul << PDMA_CHRST_CH9RST_Pos) /*!< PDMA_T::CHRST: CH9RST Mask */ + +#define PDMA_CHRST_CH10RST_Pos (10) /*!< PDMA_T::CHRST: CH10RST Position */ +#define PDMA_CHRST_CH10RST_Msk (0x1ul << PDMA_CHRST_CH10RST_Pos) /*!< PDMA_T::CHRST: CH10RST Mask */ + +#define PDMA_CHRST_CH11RST_Pos (11) /*!< PDMA_T::CHRST: CH11RST Position */ +#define PDMA_CHRST_CH11RST_Msk (0x1ul << PDMA_CHRST_CH11RST_Pos) /*!< PDMA_T::CHRST: CH11RST Mask */ + +#define PDMA_CHRST_CH12RST_Pos (12) /*!< PDMA_T::CHRST: CH12RST Position */ +#define PDMA_CHRST_CH12RST_Msk (0x1ul << PDMA_CHRST_CH12RST_Pos) /*!< PDMA_T::CHRST: CH12RST Mask */ + +#define PDMA_CHRST_CH13RST_Pos (13) /*!< PDMA_T::CHRST: CH13RST Position */ +#define PDMA_CHRST_CH13RST_Msk (0x1ul << PDMA_CHRST_CH13RST_Pos) /*!< PDMA_T::CHRST: CH13RST Mask */ + +#define PDMA_CHRST_CH14RST_Pos (14) /*!< PDMA_T::CHRST: CH14RST Position */ +#define PDMA_CHRST_CH14RST_Msk (0x1ul << PDMA_CHRST_CH14RST_Pos) /*!< PDMA_T::CHRST: CH14RST Mask */ + +#define PDMA_CHRST_CH15RST_Pos (15) /*!< PDMA_T::CHRST: CH15RST Position */ +#define PDMA_CHRST_CH15RST_Msk (0x1ul << PDMA_CHRST_CH15RST_Pos) /*!< PDMA_T::CHRST: CH15RST Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC8_Pos (0) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC8 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC8_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC8_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC8 Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC9_Pos (4) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC9 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC9_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC9_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC9 Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC10_Pos (8) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC10 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC10_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC10_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC10 Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC11_Pos (12) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC11 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC11_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC11_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC11 Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC12_Pos (16) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC12 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC12_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC12_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC12 Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC13_Pos (20) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC13 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC13_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC13_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC13 Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC14_Pos (24) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC14 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC14_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC14_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC14 Mask */ + +#define PDMA_TOUTPSC8_15_TOUTPSC15_Pos (28) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC15 Position */ +#define PDMA_TOUTPSC8_15_TOUTPSC15_Msk (0x7ul << PDMA_TOUTPSC8_15_TOUTPSC15_Pos) /*!< PDMA_T::TOUTPSC8_15: TOUTPSC15 Mask */ + +#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ +#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ + +#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ +#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ + +#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ +#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ + +#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ +#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ + +#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ +#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ + +#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ +#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ + +#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ +#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ + +#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ +#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ + +#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */ +#define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */ + +#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */ +#define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */ + +#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */ +#define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */ + +#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */ +#define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */ + +#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA_T::REQSEL12_15: REQSRC12 Position */ +#define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC12 Mask */ + +#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA_T::REQSEL12_15: REQSRC13 Position */ +#define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC13 Mask */ + +#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA_T::REQSEL12_15: REQSRC14 Position */ +#define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC14 Mask */ + +#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA_T::REQSEL12_15: REQSRC15 Position */ +#define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA_T::REQSEL12_15: REQSRC15 Mask */ + +#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ +#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ + +#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ +#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ + +#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ +#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ + +#define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */ +#define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */ + +#define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */ +#define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */ + +#define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */ +#define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */ + +/**@}*/ /* PDMA_CONST */ +/**@}*/ /* end of PDMA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __PDMA_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/psio_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/psio_reg.h new file mode 100644 index 0000000..1e46327 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/psio_reg.h @@ -0,0 +1,1439 @@ +/**************************************************************************//** + * @file psio_reg.h + * @version V3.00 + * @brief PSIO register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef __PSIO_REG_H__ +#define __PSIO_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PSIO Programmable Serial IO (PSIO) + Memory Mapped Structure for PSIO Controller +@{ */ + +typedef struct +{ + /** + * @var SCCT_T::SCCTL + * Offset: 0x20/0x28/0x30/0x38 PSIO Slot Controller n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |INISLOT |Initial Slot Period + * | | |The initial slot of the repeat period. + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * |[7:4] |ENDSLOT |End Slot Period + * | | |The end slot of the repeat period. + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * |[13:8] |SPLCNT |Slot Period Loop Count + * | | |000000 ~ 111110 is loop count. + * | | |000000 = Slot period loop count function is disable. + * | | |000001 = Repeat selection loop once, which means total go through selected repeat slots 2 times. + * | | |111111 = Loop until stop PSIO slot controller. + * | | |Note 1: If setting this register 111111 with PDMA mode and OUTPUT mode, it will stop automatically when PDMA is finish and output data in shift register is finished. + * | | |Note 2: If setting this register 111111 with PDMA mode and INPUT mode, it will stop automatically when PDMA is finish. + * | | |Note 3: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished. + * |[15:14] |TRIGSRC |PSIO_SCn Trigger Source + * | | |00 = Trigger by software. + * | | |01 = Trigger PSIO_SCn when related PSIO_PIN occurred falling edge. + * | | |10 = Trigger PSIO_SCn when related PSIO_PIN occurred rising edge. + * | | |11 = Trigger PSIO_SCn when related PSIO_PIN occurred rising edge or falling edge. + * | | |Note 1: PSIO slot controller pin can only be trigger by related pins which is setting from SCSEL(PSIOn_GENCTL[25:24]). + * | | |Note 2: Configuring rising or falling signal trigger PSIO, the signal need to hold for at least two PSIO_CLK for de-bounce or PSIO will not be triggered. + * |[16] |START |PSIO_SCn Start + * | | |0 = No use. + * | | |1 = Start PSIO_SCn to count and active related PSIO_PIN. + * | | |Note: this bit is always read as 0. + * |[17] |REPEAT |Whole Repeat Mode + * | | |Slot controller repeats counting forever. + * | | |0 = Repeat mode disabled. + * | | |1 = Repeat mode enabled. + * | | |Note 1: If this bit is enabled with PDMA mode, slot controller will stop automatically when the PDMA finish transferring number of data. + * | | |Note 2: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished. + * |[18] |STOP |PSIO_SCn Stop + * | | |0 = No use. + * | | |1 = Stop PSIO_SCn. + * | | |Note: This bit is always read as 0. + * |[24] |BUSY |PSIO_SCn Busy Flag + * | | |0 = PSIO_SCn is not busy. + * | | |1 = PSIO_SCn is busy. + * | | |Note: This bit will be set to 1 when slot controller starts to count automatically and it will be cleared to 0 automatically when slot controller stops counting, too. + * |[25] |IDLE |PSIO_SCn Idle Flag + * | | |0 = PSIO_SCn is not IDLE. + * | | |1 = PSIO_SCn is IDLE. + * | | |Note 1: This bit will be cleared to 0 when slot controller starts to count automatically. + * | | |Note 2: This bit will be set to 1 when configuring it 1 by software. + * | | |Note 3: This bit is set to distinguish INTERVAL(PSIOn_GENCTL[5:4]) and INITIAL(PSIOn_GENCTL[3:2]). + * @var SCCT_T::SCSLOT + * Offset: 0x24/0x2C/0x34/0x3C PSIO Slot Controller n Slot Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SLOT0 |PSIO Slot Controller Slot0 Tick Count + * | | |0 to 15. + * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[7:4] |SLOT1 |PSIO Slot Controller Slot1 Tick Count + * | | |0 to 15. + * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[11:8] |SLOT2 |PSIO Slot Controller Slot2 Tick Count + * | | |0 to 15. + * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[15:12] |SLOT3 |PSIO Slot Controller Slot3 Tick Count + * | | |0 to 15. + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[19:16] |SLOT4 |PSIO Slot Controller Slot4 Tick Count + * | | |0 to 15. + * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[23:20] |SLOT5 |PSIO Slot Controller Slot5 Tick Count + * | | |0 to 15 + * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[27:24] |SLOT6 |PSIO Slot Controller Slot6 Tick Count + * | | |0 to 15 + * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[31:28] |SLOT7 |PSIO Slot Controller Slot7 Tick Count + * | | |0 to 15. + * | | |Note 1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note 2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enabled. + * | | |Note 3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + */ + __IO uint32_t SCCTL; /*!< PSIO Slot Counter n Control register */ + __IO uint32_t SCSLOT; /*!< PSIO Slot Counter n Slot Register */ + +} SCCT_T; + +typedef struct +{ + /** + * @var GNCT_T::GENCTL + * Offset: 0x40/0x60/0x80/0xA0/0xC0/0xE0/0x100/0x120 PSIOn General Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |IOMODE |IO Mode + * | | |I/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point. + * | | |00 = Input mode. + * | | |01 = Output mode. + * | | |10 = Open-drain mode. + * | | |11 = Quasi-bidirectional mode. + * | | |Note 1: When slot controller stops counting, it will switch to the current I/O mode setting. + * | | |Note 2: When PSIO uses quasi-bidirectional mode or open-drain mode to trigger slot controller, the initial or interval output state need to be set output high level, or the pin will not be trigger. + * |[3:2] |INITIAL |Initial Output + * | | |The output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1. + * | | |00 = Low level. + * | | |01 = High level. + * | | |10 = Last output. + * | | |11 = Toggle. + * | | |Note 1: Only when IOMODE is not input mode, then this register is effective. + * | | |Note 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is high. + * |[5:4] |INTERVAL |Interval Output + * | | |The output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0. + * | | |00 = Low level. + * | | |01 = High level. + * | | |10 = Last output. + * | | |11 = Toggle. + * | | |Note 1: Only when IOMODE is not input mode, then this register is effective. + * | | |Note 2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is low. + * |[11:8] |SW0CP |Switch0 Check Point + * | | |0000 = No use. + * | | |0001 = CHECK POINT 0. + * | | |0010 = CHECK POINT 1. + * | | |0011 = CHECK POINT 2. + * | | |0100 = CHECK POINT 3. + * | | |0101 = CHECK POINT 4. + * | | |0110 = CHECK POINT 5. + * | | |0111 = CHECK POINT 6. + * | | |1000 = CHECK POINT 7. + * | | |Others = Reserved. + * |[15:12] |SW1CP |Switch1 Check Point + * | | |0000 = No use. + * | | |0001 = CHECK POINT 0. + * | | |0010 = CHECK POINT 1. + * | | |0011 = CHECK POINT 2. + * | | |0100 = CHECK POINT 3. + * | | |0101 = CHECK POINT 4. + * | | |0110 = CHECK POINT 5. + * | | |0111 = CHECK POINT 6. + * | | |1000 = CHECK POINT 7. + * | | |Others = Reserved. + * |[17:16] |MODESW0 |Mode Switch0 Point + * | | |Mode at the switch0 point + * | | |00 = Input mode. + * | | |01 = Output mode. + * | | |10 = Open-drain mode. + * | | |11 = Quasi-bidirectional mode. + * |[19:18] |MODESW1 |Mode Switch1 Point + * | | |Mode at the switch1 point + * | | |00 = Input mode. + * | | |01 = Output mode. + * | | |10 = Open-drain mode. + * | | |11 = Quasi-bidirectional mode. + * |[25:24] |SCSEL |Slot Controller Selection + * | | |Select slot controller for check point. + * | | |00 = SLOT CONTROLLER0. + * | | |01 = SLOT CONTROLLER1. + * | | |10 = SLOT CONTROLLER2. + * | | |11 = SLOT CONTROLLER3. + * |[26] |PINEN |Pin Enable Bit + * | | |0 = Pin Disabled. + * | | |1 = Pin Enabled. + * @var GNCT_T::DATCTL + * Offset: 0x44/0x64/0x84/0xA4/0xC4/0xE4/0x104/0x124 PSIOn Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |OUTDATWD |Output Data Width + * | | |Indicate the data width of OUTPUT DATA register. + * | | |Output data size = OUTDATWD +1. + * | | |e.g. + * | | |5'b00000 = 1 bit. + * | | |5'b11111 = 32 bit. + * |[12:8] |INDATWD |Input Data Width + * | | |Indicate the data width of INPUT DATA register. + * | | |Input data size = INDATWD +1. + * | | |e.g. + * | | |5'b00000 = 1 bit. + * | | |5'b11111 = 32 bit. + * |[16] |ORDER |Order + * | | |The order of output data and input data. + * | | |0 = Data transfer start form LSB. + * | | |1 = Data transfer start form MSB. + * |[25:24] |OUTDEPTH |Output Data Depth + * | | |Represent the data depth of the output buffer, when data width is larger than 16-bit, this setting can be ignored. + * | | |When the data width is between 9-bit and 16 bit, + * | | |0 = OUTDEPTH [0], the data depth is 1. + * | | |1 = OUTDEPTH [0], the data depth is 2. + * | | |When the data width is less than or equal to 8-bit, + * | | |0 = OUTDEPTH, the data depth is 1. + * | | |1 = OUTDEPTH, the data depth is 2. + * | | |2 = OUTDEPTH, the data depth is 3. + * | | |3 = OUTDEPTH, the data depth is 4. + * | | |Note 1: The output data depth impacts when the output data empty flag and output under flow data flag is set to 1. + * | | |Note 2: There is no difference of data depth no matter using software program data or PDMA program data. + * |[29:28] |INDEPTH |Input Data Depth + * | | |Represent the data depth of the input buffer, when data width is larger than 16-bit, this setting can be ignored. + * | | |When the data width is between 9-bit and 16 bit, + * | | |0 = INDEPTH[0], the data depth is 1. + * | | |1 = INDEPTH[0], the data depth is 2. + * | | |When the data width is less than or equal to 8-bit, + * | | |0 = INDEPTH, the data depth is 1. + * | | |1 = INDEPTH, the data depth is 2. + * | | |2 = INDEPTH, the data depth is 3. + * | | |3 = INDEPTH, the data depth is 4. + * | | |Note 1: The input data depth impacts when the input data full flag and input data over flow flag is set to 1. + * | | |Note 2: There is no difference of data depth no matter using software program data or PDMA program data. + * @var GNCT_T::INSTS + * Offset: 0x48/0x68/0x88/0xA8/0xC8/0xE8/0x108/0x128 PSIOn Input Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |INSTS |Input Status + * | | |Status input buffer. This register can be read clear. + * | | |Note: When the valid bit is set, the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update. + * @var GNCT_T::INDAT + * Offset: 0x4C/0x6C/0x8C/0xAC/0xCC/0xEC/0x10C/0x12C PSIOn Input Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |INDAT |Input Data Buffer + * | | |This register can be read clear. + * | | |Note: The input data sample time is according to the slot length. + * | | |The sampling time is near 3/4 slot. + * | | |When the slot length is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, PSIO sample input data when the slot controller count to 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9. + * @var GNCT_T::OUTDAT + * Offset: 0x50/0x70/0x90/0xB0/0xD0/0xF0/0x110/0x130 PSIOn Output Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |OUTDAT |Output Data Buffer + * | | |This field is used to configure output data. + * @var GNCT_T::CPCTL0 + * Offset: 0x54/0x74/0x94/0xB4/0xD4/0xF4/0x114/0x134 PSIOn Check Point Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CKPT0 |Check Point 0 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[6:4] |CKPT1 |Check Point 1 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[10:8] |CKPT2 |Check Point 2 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[14:12] |CKPT3 |Check Point 3 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[18:16] |CKPT4 |Check Point 4 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[22:20] |CKPT5 |Check Point 5 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[26:24] |CKPT6 |Check Point 6 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[30:28] |CKPT7 |Check Point 7 + * | | |This field is used to link check point and slot controller slot. + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note 1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number. + * | | |Note 2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * @var GNCT_T::CPCTL1 + * Offset: 0x58/0x78/0x98/0xB8/0xD8/0xF8/0x118/0x138 PSIOn Check Point Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CKPT0ACT |Check Point 0 Action + * | | |Select check point action at check point0. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + * |[6:4] |CKPT1ACT |Check Point 1 Action + * | | |Select check point action at check point1. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + * |[10:8] |CKPT2ACT |Check Point 2 Action + * | | |Select check point action at check point2. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + * |[14:12] |CKPT3ACT |Check Point 3 Action + * | | |Select check point action at check point3. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + * |[18:16] |CKPT4ACT |Check Point 4 Action + * | | |Select check point action at check point4. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + * |[22:20] |CKPT5ACT |Check Point 5 Action + * | | |Select check point action at check point5. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + * |[26:24] |CKPT6ACT |Check Point 6 Action + * | | |Select check point action at check point6. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + * |[30:28] |CKPT7ACT |Check Point 7 Action + * | | |Select check point action at check point7. + * | | |000 = Output level low. + * | | |001 = Output level high. + * | | |010 = Output from data buffer. + * | | |011 = Output toggle. + * | | |100 = Input data buffer. + * | | |101 = Input status. + * | | |110 = Input status record and update. + * | | |Others = Reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]). + */ + __IO uint32_t GENCTL; /*!< PSIOn General Control Register */ + __IO uint32_t DATCTL; /*!< PSIOn Data Control Register */ + __I uint32_t INSTS; /*!< PSIOn Input Status Register */ + __I uint32_t INDAT; /*!< PSIOn Input Data Register */ + __O uint32_t OUTDAT; /*!< PSIOn Output Data Register */ + __IO uint32_t CPCTL0; /*!< PSIOn Check Point Control Register 0 */ + __IO uint32_t CPCTL1; /*!< PSIOn Check Point Control Register 1 */ + __I uint32_t RESERVE0[1]; +} GNCT_T; + +typedef struct +{ + /** + * @var PSIO_T::INTCTL + * Offset: 0x00 PSIO Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CONI0SS |Configurable Interrupt 0 Slot Selection + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * |[6:4] |CONI1SS |Configurable Interrupt 1 Slot Selection + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * |[9:8] |CONI0SCS |Configurable Interrupt 0 Slot Controller Selection + * | | |Select Slot controller for interrupt 0. + * | | |00 = Slot controller 0. + * | | |01 = Slot controller 1. + * | | |10 = Slot controller 2. + * | | |11 = Slot controller 3. + * |[13:12] |CONI1SCS |Configurable Interrupt 1 Slot Controller Selection + * | | |Select Slot controller for interrupt 1. + * | | |00 = Slot controller 0. + * | | |01 = Slot controller 1. + * | | |10 = Slot controller 2. + * | | |11 = Slot controller 3. + * @var PSIO_T::INTEN + * Offset: 0x04 PSIO Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CON0IE |Configurable Interrupt 0 Enable Bit + * | | |This field is used to enable selective interrupt 0. + * | | |0 = Selective interrupt 0 Disabled. + * | | |1 = Selective interrupt 0 Enabled. + * |[1] |CON1IE |Configurable Interrupt 1 Enable Bit + * | | |This field is used to enable selective interrupt 1. + * | | |0 = Selective interrupt 1 Disabled. + * | | |1 = Selective interrupt 1 Enabled. + * |[2] |MISMATIE |Mismatch Interrupt Enable Bit + * | | |This field is used to enable mismatch interrupt. + * | | |0 = Mismatch interrupt Disabled. + * | | |1 = Mismatch interrupt Enabled. + * |[3] |TERRIE |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt. + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[4] |SC0IE |Slot Controller 0 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 0 finish interrupt. + * | | |0 = Slot controller 0 finish interrupt Disabled. + * | | |1 = Slot controller 0 finish interrupt Enabled. + * |[5] |SC1IE |Slot Controller 1 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 1 finish interrupt. + * | | |0 = Slot controller 1 finish interrupt Disabled. + * | | |1 = Slot controller 1 finish interrupt Enabled. + * |[6] |SC2IE |Slot Controller 2 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 2 finish interrupt. + * | | |0 = Slot controller 2 finish interrupt Disabled. + * | | |1 = Slot controller 2 finish interrupt Enabled. + * |[7] |SC3IE |Slot Controller 3 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 3 finish interrupt. + * | | |0 = Slot controller 3 finish interrupt Disabled. + * | | |1 = Slot controller 3 finish interrupt Enabled. + * @var PSIO_T::INTSTS + * Offset: 0x08 PSIO Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CON0IF |Configurable Interrupt 0 Flag + * | | |The setting interrupt is trigger at the end of the check point of the pin. + * | | |0 = Condition in PSIO_INTCTL is not triggered. + * | | |1 = Condition in PSIO_INTCTL is triggered. + * | | |Note: This bit can be cleared by writing 1. + * |[1] |CON1IF |Configurable Interrupt 1 Flag + * | | |The setting interrupt is trigger at the end of the check point of the pin. + * | | |0 = Condition in PSIO_INTCTL is not triggered. + * | | |1 = Condition in PSIO_INTCTL is triggered. + * | | |Note: This bit can be cleared by writing 1. + * |[2] |MISMATIF |Mismatch Interrupt Flag + * | | |This flag shows the amounts of data are not the same in each pins with PDMA enabled. + * | | |If this situation happens, all slot controllers stop counting. + * | | |0 = Each pin with PDMA enabled receive or transfer data in the same rate. + * | | |1 = Each pin with PDMA enabled receive or transfer data in different rate. + * | | |Note 1: This flag is only effective on the pin with PDMA enabled. + * | | |Note 2: This bit can be cleared by writing 1. + * |[3] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag. + * | | |The transfer error states is at PSIO_TRANSTS register which includes input data overflow flag INOVERn (PSIO_TRANSTS[29,25,21,17,13,9,5,1] and output data underflow flag OUTUFn (PSIO_TRANSTS[31,27,23,19,15,11,7,3]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note 1: This field is the status flag of INOVER or OUTUFER. + * | | |Note 2: This bit can only be cleared by writing 1 to coordinate transfer error. + * |[4] |SC0IF |Slot Controller 0 Done Interrupt Status Flag + * | | |This field is used for slot controller 0 finish interrupt status flag. + * | | |0 = Slot controller 0 done interrupt did not occur. + * | | |1 = Slot controller 0 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * |[5] |SC1IF |Slot Controller 1 Done Interrupt Status Flag + * | | |This field is used for slot controller 1 finish interrupt status flag. + * | | |0 = Slot controller 1 done interrupt did not occur. + * | | |1 = Slot controller 1 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * |[6] |SC2IF |Slot Controller 2 Done Interrupt Status Flag + * | | |This field is used for slot controller 2 finish interrupt status flag. + * | | |0 = Slot controller 2 done interrupt did not occur. + * | | |1 = Slot controller 2 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * |[7] |SC3IF |Slot Controller 3 Done Interrupt Status Flag + * | | |This field is used for slot controller 3 finish interrupt status flag. + * | | |0 = Slot controller 3 done interrupt did not occur. + * | | |1 = Slot controller 3 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * @var PSIO_T::TRANSTS + * Offset: 0x0C PSIO Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INFULL0 |Input Data Full Flag0 (Read Only) + * | | |0 = The pin0 input data is empty. + * | | |1 = The pin0 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[1] |INOVER0 |Input Data Overflow Flag0 + * | | |0 = The pin0 input data does not occur overflow. + * | | |1 = The pin0 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[2] |OUTEPY0 |Output Data Empty Flag0 (Read Only) + * | | |0 = The pin0 output data is full. + * | | |1 = The pin0 output data is empty. + * |[3] |OUTUF0 |Output Data Underflow Flag0 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin0 output data is not underflow. + * | | |1 = The pin0 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[4] |INFULL1 |Input Data Full Flag1 (Read Only) + * | | |0 = The pin1 input data is empty. + * | | |1 = The pin1 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[5] |INOVER1 |Input Data Overflow Flag1 + * | | |0 = The pin1 input data does not occur overflow. + * | | |1 = The pin1 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[6] |OUTEPY1 |Output Data Empty Flag1 (Read Only) + * | | |0 = The pin1 output data is full. + * | | |1 = The pin1 output data is empty. + * |[7] |OUTUF1 |Output Data Underflow Flag1 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. + * | | |0 = The pin1 output data is not underflow. + * | | |1 = The pin1 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[8] |INFULL2 |Input Data Full Flag2 (Read Only) + * | | |0 = The pin2 input data is empty. + * | | |1 = The pin2 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin is enabled. + * |[9] |INOVER2 |Input Data Overflow Flag2 + * | | |0 = The pin2 input data does not occur overflow. + * | | |1 = The pin2 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[10] |OUTEPY2 |Output Data Empty Flag2 (Read Only) + * | | |0 = The pin2 output data is full. + * | | |1 = The pin2 output data is empty. + * |[11] |OUTUF2 |Output Data Underflow Flag2 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. + * | | |0 = The pin3 output data is not underflow. + * | | |1 = The pin3 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[12] |INFULL3 |Input Data Full Flag3 (Read Only) + * | | |0 = The pin3 input data is empty. + * | | |1 = The pin3 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin is enabled. + * |[13] |INOVER3 |Input Data Overflow Flag3 + * | | |0 = The pin3 input data does not occur overflow. + * | | |1 = The pin3 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[14] |OUTEPY3 |Output Data Empty Flag3 (Read Only) + * | | |0 = The pin3 output data is full. + * | | |1 = The pin3 output data is empty. + * |[15] |OUTUF3 |Output Data Underflow Flag3 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. + * | | |0 = The pin3 output data is not underflow. + * | | |1 = The pin3 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[16] |INFULL4 |Input Data Full Flag4 (Read Only) + * | | |0 = The pin4 input data is empty. + * | | |1 = The pin4 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin is enabled. + * |[17] |INOVER4 |Input Data Overflow Flag4 + * | | |0 = The pin4 input data does not occur overflow. + * | | |1 = The pin4 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[18] |OUTEPY4 |Output Data Empty Flag4 (Read Only) + * | | |0 = The pin4 output data is full. + * | | |1 = The pin4 output data is empty. + * |[19] |OUTUF4 |Output Data Underflow Flag4 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. + * | | |0 = The pin4 output data is not underflow. + * | | |1 = The pin4 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[20] |INFULL5 |Input Data Full Flag5 (Read Only) + * | | |0 = The pin5 input data is empty. + * | | |1 = The pin5 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[21] |INOVER5 |Input Data Overflow Flag5 + * | | |0 = The pin5 input data does not occur overflow. + * | | |1 = The pin5 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[22] |OUTEPY5 |Output Data Empty Flag5 (Read Only) + * | | |0 = The pin5 output data is full. + * | | |1 = The pin5 output data is empty. + * |[23] |OUTUF5 |Output Data Underflow Flag5 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. + * | | |0 = The pin5 output data is not underflow. + * | | |1 = The pin5 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin is enabled. + * |[24] |INFULL6 |Input Data Full Flag6 (Read Only) + * | | |0 = The pin6 input data is empty. + * | | |1 = The pin6 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[25] |INOVER6 |Input Data Overflow Flag6 + * | | |0 = The pin6 input data does not occur overflow. + * | | |1 = The pin6 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[26] |OUTEPY6 |Output Data Empty Flag6 (Read Only) + * | | |0 = The pin6 output data is full. + * | | |1 = The pin6 output data is empty. + * |[27] |OUTUF6 |Output Data Underflow Flag6 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. + * | | |0 = The pin6 output data is not underflow. + * | | |1 = The pin6 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[28] |INFULL7 |Input Data Full Flag7 (Read Only) + * | | |0 = The pin7 input data is empty. + * | | |1 = The pin7 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[29] |INOVER7 |Input Data Overflow Flag7 + * | | |0 = The pin7 input data does not occur overflow. + * | | |1 = The pin7 input data occurs overflow. + * | | |Note 1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note 2: When overflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * |[30] |OUTEPY7 |Output Data Empty Flag7 (Read Only) + * | | |0 = The pin7 output data is full. + * | | |1 = The pin7 output data is empty. + * |[31] |OUTUF7 |Output Data Underflow Flag7 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready, this flag will be set to 1. + * | | |0 = The pin7 output data is not underflow. + * | | |1 = The pin7 output data is underflow. + * | | |Note 1: When output data shortage happened, it will output 0. + * | | |Note 2: When underflow happens, related slot controller will be stopped. + * | | |Note 3: This bit can be cleared by configure 1 to it. + * | | |Note 4: This bit will be cleared automatically when related slot controller started and pin enabled. + * @var PSIO_T::ISSTS + * Offset: 0x10 PSIO Input Status State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VALID0 |Input Status Valid 0 + * | | |0 = The pin 0 input status is not ready. + * | | |1 = The pin 0 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[1] |INSTSOV0 |Input Status Overflow 0 + * | | |0 = The pin 0 input status does not overflow. + * | | |1 = The pin 0 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * |[2] |VALID1 |Input Status Valid 1 + * | | |0 = The pin 1 input status is not ready. + * | | |1 = The pin 1 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[3] |INSTSOV1 |Input Status Overflow 1 + * | | |0 = The pin 1 input status does not overflow. + * | | |1 = The pin 1 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * |[4] |VALID2 |Input Status Valid 2 + * | | |0 = The pin 2 input status is not ready. + * | | |1 = The pin 2 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[5] |INSTSOV2 |Input Status Overflow 2 + * | | |0 = The pin 2 input status does not overflow. + * | | |1 = The pin 2 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * |[6] |VALID3 |Input Status Valid 3 + * | | |0 = The pin 3 input status is not ready. + * | | |1 = The pin 3 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[7] |INSTSOV3 |Input Status Overflow 3 + * | | |0 = The pin 3 input status does not overflow. + * | | |1 = The pin 3 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * |[8] |VALID4 |Input Status Valid 4 + * | | |0 = The pin 4 input status is not ready. + * | | |1 = The pin 4 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[9] |INSTSOV4 |Input Status Overflow 4 + * | | |0 = The pin 4 input status does not overflow. + * | | |1 = The pin 4 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * |[10] |VALID5 |Input Status Valid 5 + * | | |0 = The pin 5 input status is not ready. + * | | |1 = The pin 5 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[11] |INSTSOV5 |Input Status Overflow 5 + * | | |0 = The pin 5 input status does not overflow. + * | | |1 = The pin 5 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * |[12] |VALID6 |Input Status Valid 6 + * | | |0 = The pin 6 input status is not ready. + * | | |1 = The pin 6 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[13] |INSTSOV6 |Input Status Overflow 6 + * | | |0 = The pin 6 input status does not overflow. + * | | |1 = The pin 6 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * |[14] |VALID7 |Input Status Valid 7 + * | | |0 = The pin7 input status is not ready. + * | | |1 = The pin7 input status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[15] |INSTSOV7 |Input Status Overflow 7 + * | | |0 = The pin7 input status does not overflow. + * | | |1 = The pin7 input status occur overflow. + * | | |Note: This overflow bit can be cleared by writing 1. + * @var PSIO_T::PDMACTL + * Offset: 0x14 PSIO PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPIN0EN |Output PDMA Pin0 Enable Bit + * | | |0 = Pin0 output PDMA function Disabled. + * | | |1 = Pin0 output PDMA function Enabled. + * |[1] |OPIN1EN |Output PDMA Pin1 Enable Bit + * | | |0 = Pin1 output PDMA function Disabled. + * | | |1 = Pin1 output PDMA function Enabled. + * |[2] |OPIN2EN |Output PDMA Pin2 Enable Bit + * | | |0 = Pin2 output PDMA function Disabled. + * | | |1 = Pin2 output PDMA function Enabled. + * |[3] |OPIN3EN |Output PDMA Pin3 Enable Bit + * | | |0 = Pin3 output PDMA function Disabled. + * | | |1 = Pin3 output PDMA function Enabled. + * |[4] |OPIN4EN |Output PDMA Pin4 Enable Bit + * | | |0 = Pin4 output PDMA function Disabled. + * | | |1 = Pin4 output PDMA function Enabled. + * |[5] |OPIN5EN |Output PDMA Pin5 Enable Bit + * | | |0 = Pin5 output PDMA function Disabled. + * | | |1 = Pin5 output PDMA function Enabled. + * |[6] |OPIN6EN |Output PDMA Pin6 Enable Bit + * | | |0 = Pin6 output PDMA function Disabled. + * | | |1 = Pin6 output PDMA function Enabled. + * |[7] |OPIN7EN |Output PDMA Pin7 Enable Bit + * | | |0 = Pin7 output PDMA function Disabled. + * | | |1 = Pin7 output PDMA function Enabled. + * |[8] |IPIN0EN |Input PDMA Pin0 Enable Bit + * | | |0 = Pin0 input PDMA function Disabled. + * | | |1 = Pin0 input PDMA function Enabled. + * |[9] |IPIN1EN |Input PDMA Pin1 Enable Bit + * | | |0 = Pin1 input PDMA function Disabled. + * | | |1 = Pin1 input PDMA function Enabled. + * |[10] |IPIN2EN |Input PDMA Pin2 Enable Bit + * | | |0 = Pin2 input PDMA function Disabled. + * | | |1 = Pin2 input PDMA function Enabled. + * |[11] |IPIN3EN |Input PDMA Pin3 Enable Bit + * | | |0 = Pin3 input PDMA function Disabled. + * | | |1 = Pin3 input PDMA function Enabled. + * |[12] |IPIN4EN |Input PDMA Pin4 Enable Bit + * | | |0 = Pin4 input PDMA function Disabled. + * | | |1 = Pin4 input PDMA function Enabled. + * |[13] |IPIN5EN |Input PDMA Pin5 Enable Bit + * | | |0 = Pin5 input PDMA function Disabled. + * | | |1 = Pin5 input PDMA function Enabled. + * |[14] |IPIN6EN |Input PDMA Pin6 Enable Bit + * | | |0 = Pin6 input PDMA function Disabled. + * | | |1 = Pin6 input PDMA function Enabled. + * |[15] |IPIN7EN |Input PDMA Pin7 Enable Bit + * | | |0 = Pin7 input PDMA function Disabled. + * | | |1 = Pin7 input PDMA function Enabled. + * |[19:16] |OUTNUM |PDMA Output Current Number (Read Only) + * | | |0000 = PDMA IDLE. + * | | |0001 = Pin 0. + * | | |0010 = Pin 1. + * | | |0011 = Pin 2. + * | | |0100 = Pin 3. + * | | |0101 = Pin 4. + * | | |0110 = Pin 5. + * | | |0111 = Pin 6. + * | | |1000 = Pin 7. + * | | |1001 = PDMA WAIT. + * | | |Others = Reserved. + * | | |This register shows the current pin number of output register write by PDMA. + * |[21:20] |OUTSCSEL |PDMA Output Data Slot Controller Selection + * | | |00 = Slot controller 0. + * | | |01 = Slot controller 1. + * | | |10 = Slot controller 2. + * | | |11 = Slot controller 3. + * |[27:24] |INNUM |PDMA Input Current Number (Read Only) + * | | |0000 = PDMA IDLE. + * | | |0001 = Pin 0. + * | | |0010 = Pin 1. + * | | |0011 = Pin 2. + * | | |0100 = Pin 3. + * | | |0101 = Pin 4. + * | | |0110 = Pin 5. + * | | |0111 = Pin 6. + * | | |1000 = Pin 7. + * | | |1001 = PDMA WAIT. + * | | |Others = reserved. + * | | |This register shows the current pin number of input register read by PDMA. + * |[29:28] |INSCSEL |PDMA Input Data Slot Controller Selection + * | | |00 = Slot controller 0. + * | | |01 = Slot controller 1. + * | | |10 = Slot controller 2. + * | | |11 = Slot controller 3. + * @var PSIO_T::PODAT + * Offset: 0x18 PSIO PDMA Output Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMAOUT |PDMA Output Data + * | | |This register is used for PSIO with PDMA single mode, and set PDMA with fixed address. + * | | |When PSIO in PDMA mode, setting PDMA to write data to this register. + * | | |The data in this register will be placed to corresponding PSIOn_OUTDAT register in order, when Output Data Empty Flag is 1 and PDMA mode enabled. + * @var PSIO_T::PIDAT + * Offset: 0x1C PSIO PDMA Input Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMAIN |PDMA Input Data + * | | |This register is used for PSIO with PDMA single mode, and set PDMA with fixed address. + * | | |When PSIO in PDMA mode, setting PDMA to read data from this register. + * | | |The data in this register will be updated from corresponding PSIOn_INDAT register in order, when Input Data Full Flag is 1 and PDMA mode enable. + */ + __IO uint32_t INTCTL; /*!< [0x0000] PSIO Interrupt Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] PSIO Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0008] PSIO Interrupt Status Register */ + __IO uint32_t TRANSTS; /*!< [0x000c] PSIO Transfer Status Register */ + __IO uint32_t ISSTS; /*!< [0x0010] PSIO Input Status State Register */ + __IO uint32_t PDMACTL; /*!< [0x0014] PSIO PDMA Control Register */ + __O uint32_t PODAT; /*!< [0x0018] PSIO PDMA Output Data Register */ + __IO uint32_t PIDAT; /*!< [0x001c] PSIO PDMA Input Data Register */ + SCCT_T SCCT[4]; /*!< [0x0020 ~ 0x0048] PSIO Slot Controller n Registers */ + GNCT_T GNCT[8]; /*!< [0x0040 ~ 0x0138] PSIOn Control Registers */ +} PSIO_T; + +/** + @addtogroup PSIO_CONST PSIO Bit Field Definition + Constant Definitions for PSIO Controller +@{ */ + +#define PSIO_INTCTL_CONI0SS_Pos (0) /*!< PSIO_T::INTCTL: INT0CSEL Position */ +#define PSIO_INTCTL_CONI0SS_Msk (0xful << PSIO_INTCTL_CONI0SS_Pos) /*!< PSIO_T::INTCTL: INT0CSEL Mask */ + +#define PSIO_INTCTL_CONI1SS_Pos (4) /*!< PSIO_T::INTCTL: INT1CSEL Position */ +#define PSIO_INTCTL_CONI1SS_Msk (0xful << PSIO_INTCTL_CONI1SS_Pos) /*!< PSIO_T::INTCTL: INT1CSEL Mask */ + +#define PSIO_INTCTL_CONI0SCS_Pos (8) /*!< PSIO_T::INTCTL: INT0SSEL Position */ +#define PSIO_INTCTL_CONI0SCS_Msk (0x3ul << PSIO_INTCTL_CONI0SCS_Pos) /*!< PSIO_T::INTCTL: INT0SSEL Mask */ + +#define PSIO_INTCTL_CONI1SCS_Pos (12) /*!< PSIO_T::INTCTL: INT1SSEL Position */ +#define PSIO_INTCTL_CONI1SCS_Msk (0x3ul << PSIO_INTCTL_CONI1SCS_Pos) /*!< PSIO_T::INTCTL: INT1SSEL Mask */ + +#define PSIO_INTEN_CON0IE_Pos (0) /*!< PSIO_T::INTEN: INTEN0 Position */ +#define PSIO_INTEN_CON0IE_Msk (0x1ul << PSIO_INTEN_CON0IE_Pos) /*!< PSIO_T::INTEN: INTEN0 Mask */ + +#define PSIO_INTEN_CON1IE_Pos (1) /*!< PSIO_T::INTEN: INTEN1 Position */ +#define PSIO_INTEN_CON1IE_Msk (0x1ul << PSIO_INTEN_CON1IE_Pos) /*!< PSIO_T::INTEN: INTEN1 Mask */ + +#define PSIO_INTEN_MISMATIE_Pos (2) /*!< PSIO_T::INTEN: MISMATIE Position */ +#define PSIO_INTEN_MISMATIE_Msk (0x1ul << PSIO_INTEN_MISMATIE_Pos) /*!< PSIO_T::INTEN: MISMATIE Mask */ + +#define PSIO_INTEN_TERRIE_Pos (3) /*!< PSIO_T::INTEN: TERRIE Position */ +#define PSIO_INTEN_TERRIE_Msk (0x1ul << PSIO_INTEN_TERRIE_Pos) /*!< PSIO_T::INTEN: TERRIE Mask */ + +#define PSIO_INTEN_SC0IE_Pos (4) /*!< PSIO_T::INTEN: SC0IE Position */ +#define PSIO_INTEN_SC0IE_Msk (0x1ul << PSIO_INTEN_SC0IE_Pos) /*!< PSIO_T::INTEN: SC0IE Mask */ + +#define PSIO_INTEN_SC1IE_Pos (5) /*!< PSIO_T::INTEN: SC1IE Position */ +#define PSIO_INTEN_SC1IE_Msk (0x1ul << PSIO_INTEN_SC1IE_Pos) /*!< PSIO_T::INTEN: SC1IE Mask */ + +#define PSIO_INTEN_SC2IE_Pos (6) /*!< PSIO_T::INTEN: SC2IE Position */ +#define PSIO_INTEN_SC2IE_Msk (0x1ul << PSIO_INTEN_SC2IE_Pos) /*!< PSIO_T::INTEN: SC2IE Mask */ + +#define PSIO_INTEN_SC3IE_Pos (7) /*!< PSIO_T::INTEN: SC3IE Position */ +#define PSIO_INTEN_SC3IE_Msk (0x1ul << PSIO_INTEN_SC3IE_Pos) /*!< PSIO_T::INTEN: SC3IE Mask */ + +#define PSIO_INTSTS_CON0IF_Pos (0) /*!< PSIO_T::INTSTS: INTIF0 Position */ +#define PSIO_INTSTS_CON0IF_Msk (0x1ul << PSIO_INTSTS_CON0IF_Pos) /*!< PSIO_T::INTSTS: INTIF0 Mask */ + +#define PSIO_INTSTS_CON1IF_Pos (1) /*!< PSIO_T::INTSTS: INTIF1 Position */ +#define PSIO_INTSTS_CON1IF_Msk (0x1ul << PSIO_INTSTS_CON1IF_Pos) /*!< PSIO_T::INTSTS: INTIF1 Mask */ + +#define PSIO_INTSTS_MISMATIF_Pos (2) /*!< PSIO_T::INTSTS: MISMATIF Position */ +#define PSIO_INTSTS_MISMATIF_Msk (0x1ul << PSIO_INTSTS_MISMATIF_Pos) /*!< PSIO_T::INTSTS: MISMATIF Mask */ + +#define PSIO_INTSTS_TERRIF_Pos (3) /*!< PSIO_T::INTSTS: TERRIF Position */ +#define PSIO_INTSTS_TERRIF_Msk (0x1ul << PSIO_INTSTS_TERRIF_Pos) /*!< PSIO_T::INTSTS: TERRIF Mask */ + +#define PSIO_INTSTS_SC0IF_Pos (4) /*!< PSIO_T::INTSTS: SC0IF Position */ +#define PSIO_INTSTS_SC0IF_Msk (0x1ul << PSIO_INTSTS_SC0IF_Pos) /*!< PSIO_T::INTSTS: SC0IF Mask */ + +#define PSIO_INTSTS_SC1IF_Pos (5) /*!< PSIO_T::INTSTS: SC1IF Position */ +#define PSIO_INTSTS_SC1IF_Msk (0x1ul << PSIO_INTSTS_SC1IF_Pos) /*!< PSIO_T::INTSTS: SC1IF Mask */ + +#define PSIO_INTSTS_SC2IF_Pos (6) /*!< PSIO_T::INTSTS: SC2IF Position */ +#define PSIO_INTSTS_SC2IF_Msk (0x1ul << PSIO_INTSTS_SC2IF_Pos) /*!< PSIO_T::INTSTS: SC2IF Mask */ + +#define PSIO_INTSTS_SC3IF_Pos (7) /*!< PSIO_T::INTSTS: SC3IF Position */ +#define PSIO_INTSTS_SC3IF_Msk (0x1ul << PSIO_INTSTS_SC3IF_Pos) /*!< PSIO_T::INTSTS: SC3IF Mask */ + +#define PSIO_TRANSTS_INFULL0_Pos (0) /*!< PSIO_T::TRANSTS: INFULL0 Position */ +#define PSIO_TRANSTS_INFULL0_Msk (0x1ul << PSIO_TRANSTS_INFULL0_Pos) /*!< PSIO_T::TRANSTS: INFULL0 Mask */ + +#define PSIO_TRANSTS_INOVER0_Pos (1) /*!< PSIO_T::TRANSTS: INOVER0 Position */ +#define PSIO_TRANSTS_INOVER0_Msk (0x1ul << PSIO_TRANSTS_INOVER0_Pos) /*!< PSIO_T::TRANSTS: INOVER0 Mask */ + +#define PSIO_TRANSTS_OUTEPY0_Pos (2) /*!< PSIO_T::TRANSTS: OUTEPY0 Position */ +#define PSIO_TRANSTS_OUTEPY0_Msk (0x1ul << PSIO_TRANSTS_OUTEPY0_Pos) /*!< PSIO_T::TRANSTS: OUTEPY0 Mask */ + +#define PSIO_TRANSTS_OUTUF0_Pos (3) /*!< PSIO_T::TRANSTS: OUTUF0 Position */ +#define PSIO_TRANSTS_OUTUF0_Msk (0x1ul << PSIO_TRANSTS_OUTUF0_Pos) /*!< PSIO_T::TRANSTS: OUTUF0 Mask */ + +#define PSIO_TRANSTS_INFULL1_Pos (4) /*!< PSIO_T::TRANSTS: INFULL1 Position */ +#define PSIO_TRANSTS_INFULL1_Msk (0x1ul << PSIO_TRANSTS_INFULL1_Pos) /*!< PSIO_T::TRANSTS: INFULL1 Mask */ + +#define PSIO_TRANSTS_INOVER1_Pos (5) /*!< PSIO_T::TRANSTS: INOVER1 Position */ +#define PSIO_TRANSTS_INOVER1_Msk (0x1ul << PSIO_TRANSTS_INOVER1_Pos) /*!< PSIO_T::TRANSTS: INOVER1 Mask */ + +#define PSIO_TRANSTS_OUTEPY1_Pos (6) /*!< PSIO_T::TRANSTS: OUTEPY1 Position */ +#define PSIO_TRANSTS_OUTEPY1_Msk (0x1ul << PSIO_TRANSTS_OUTEPY1_Pos) /*!< PSIO_T::TRANSTS: OUTEPY1 Mask */ + +#define PSIO_TRANSTS_OUTUF1_Pos (7) /*!< PSIO_T::TRANSTS: OUTUF1 Position */ +#define PSIO_TRANSTS_OUTUF1_Msk (0x1ul << PSIO_TRANSTS_OUTUF1_Pos) /*!< PSIO_T::TRANSTS: OUTUF1 Mask */ + +#define PSIO_TRANSTS_INFULL2_Pos (8) /*!< PSIO_T::TRANSTS: INFULL2 Position */ +#define PSIO_TRANSTS_INFULL2_Msk (0x1ul << PSIO_TRANSTS_INFULL2_Pos) /*!< PSIO_T::TRANSTS: INFULL2 Mask */ + +#define PSIO_TRANSTS_INOVER2_Pos (9) /*!< PSIO_T::TRANSTS: INOVER2 Position */ +#define PSIO_TRANSTS_INOVER2_Msk (0x1ul << PSIO_TRANSTS_INOVER2_Pos) /*!< PSIO_T::TRANSTS: INOVER2 Mask */ + +#define PSIO_TRANSTS_OUTEPY2_Pos (10) /*!< PSIO_T::TRANSTS: OUTEPY2 Position */ +#define PSIO_TRANSTS_OUTEPY2_Msk (0x1ul << PSIO_TRANSTS_OUTEPY2_Pos) /*!< PSIO_T::TRANSTS: OUTEPY2 Mask */ + +#define PSIO_TRANSTS_OUTUF2_Pos (11) /*!< PSIO_T::TRANSTS: OUTUF2 Position */ +#define PSIO_TRANSTS_OUTUF2_Msk (0x1ul << PSIO_TRANSTS_OUTUF2_Pos) /*!< PSIO_T::TRANSTS: OUTUF2 Mask */ + +#define PSIO_TRANSTS_INFULL3_Pos (12) /*!< PSIO_T::TRANSTS: INFULL3 Position */ +#define PSIO_TRANSTS_INFULL3_Msk (0x1ul << PSIO_TRANSTS_INFULL3_Pos) /*!< PSIO_T::TRANSTS: INFULL3 Mask */ + +#define PSIO_TRANSTS_INOVER3_Pos (13) /*!< PSIO_T::TRANSTS: INOVER3 Position */ +#define PSIO_TRANSTS_INOVER3_Msk (0x1ul << PSIO_TRANSTS_INOVER3_Pos) /*!< PSIO_T::TRANSTS: INOVER3 Mask */ + +#define PSIO_TRANSTS_OUTEPY3_Pos (14) /*!< PSIO_T::TRANSTS: OUTEPY3 Position */ +#define PSIO_TRANSTS_OUTEPY3_Msk (0x1ul << PSIO_TRANSTS_OUTEPY3_Pos) /*!< PSIO_T::TRANSTS: OUTEPY3 Mask */ + +#define PSIO_TRANSTS_OUTUF3_Pos (15) /*!< PSIO_T::TRANSTS: OUTUF3 Position */ +#define PSIO_TRANSTS_OUTUF3_Msk (0x1ul << PSIO_TRANSTS_OUTUF3_Pos) /*!< PSIO_T::TRANSTS: OUTUF3 Mask */ + +#define PSIO_TRANSTS_INFULL4_Pos (16) /*!< PSIO_T::TRANSTS: INFULL4 Position */ +#define PSIO_TRANSTS_INFULL4_Msk (0x1ul << PSIO_TRANSTS_INFULL4_Pos) /*!< PSIO_T::TRANSTS: INFULL4 Mask */ + +#define PSIO_TRANSTS_INOVER4_Pos (17) /*!< PSIO_T::TRANSTS: INOVER4 Position */ +#define PSIO_TRANSTS_INOVER4_Msk (0x1ul << PSIO_TRANSTS_INOVER4_Pos) /*!< PSIO_T::TRANSTS: INOVER4 Mask */ + +#define PSIO_TRANSTS_OUTEPY4_Pos (18) /*!< PSIO_T::TRANSTS: OUTEPY4 Position */ +#define PSIO_TRANSTS_OUTEPY4_Msk (0x1ul << PSIO_TRANSTS_OUTEPY4_Pos) /*!< PSIO_T::TRANSTS: OUTEPY4 Mask */ + +#define PSIO_TRANSTS_OUTUF4_Pos (19) /*!< PSIO_T::TRANSTS: OUTUF4 Position */ +#define PSIO_TRANSTS_OUTUF4_Msk (0x1ul << PSIO_TRANSTS_OUTUF4_Pos) /*!< PSIO_T::TRANSTS: OUTUF4 Mask */ + +#define PSIO_TRANSTS_INFULL5_Pos (20) /*!< PSIO_T::TRANSTS: INFULL5 Position */ +#define PSIO_TRANSTS_INFULL5_Msk (0x1ul << PSIO_TRANSTS_INFULL5_Pos) /*!< PSIO_T::TRANSTS: INFULL5 Mask */ + +#define PSIO_TRANSTS_INOVER5_Pos (21) /*!< PSIO_T::TRANSTS: INOVER5 Position */ +#define PSIO_TRANSTS_INOVER5_Msk (0x1ul << PSIO_TRANSTS_INOVER5_Pos) /*!< PSIO_T::TRANSTS: INOVER5 Mask */ + +#define PSIO_TRANSTS_OUTEPY5_Pos (22) /*!< PSIO_T::TRANSTS: OUTEPY5 Position */ +#define PSIO_TRANSTS_OUTEPY5_Msk (0x1ul << PSIO_TRANSTS_OUTEPY5_Pos) /*!< PSIO_T::TRANSTS: OUTEPY5 Mask */ + +#define PSIO_TRANSTS_OUTUF5_Pos (23) /*!< PSIO_T::TRANSTS: OUTUF5 Position */ +#define PSIO_TRANSTS_OUTUF5_Msk (0x1ul << PSIO_TRANSTS_OUTUF5_Pos) /*!< PSIO_T::TRANSTS: OUTUF5 Mask */ + +#define PSIO_TRANSTS_INFULL6_Pos (24) /*!< PSIO_T::TRANSTS: INFULL6 Position */ +#define PSIO_TRANSTS_INFULL6_Msk (0x1ul << PSIO_TRANSTS_INFULL6_Pos) /*!< PSIO_T::TRANSTS: INFULL6 Mask */ + +#define PSIO_TRANSTS_INOVER6_Pos (25) /*!< PSIO_T::TRANSTS: INOVER6 Position */ +#define PSIO_TRANSTS_INOVER6_Msk (0x1ul << PSIO_TRANSTS_INOVER6_Pos) /*!< PSIO_T::TRANSTS: INOVER6 Mask */ + +#define PSIO_TRANSTS_OUTEPY6_Pos (26) /*!< PSIO_T::TRANSTS: OUTEPY6 Position */ +#define PSIO_TRANSTS_OUTEPY6_Msk (0x1ul << PSIO_TRANSTS_OUTEPY6_Pos) /*!< PSIO_T::TRANSTS: OUTEPY6 Mask */ + +#define PSIO_TRANSTS_OUTUF6_Pos (27) /*!< PSIO_T::TRANSTS: OUTUF6 Position */ +#define PSIO_TRANSTS_OUTUF6_Msk (0x1ul << PSIO_TRANSTS_OUTUF6_Pos) /*!< PSIO_T::TRANSTS: OUTUF6 Mask */ + +#define PSIO_TRANSTS_INFULL7_Pos (28) /*!< PSIO_T::TRANSTS: INFULL7 Position */ +#define PSIO_TRANSTS_INFULL7_Msk (0x1ul << PSIO_TRANSTS_INFULL7_Pos) /*!< PSIO_T::TRANSTS: INFULL7 Mask */ + +#define PSIO_TRANSTS_INOVER7_Pos (29) /*!< PSIO_T::TRANSTS: INOVER7 Position */ +#define PSIO_TRANSTS_INOVER7_Msk (0x1ul << PSIO_TRANSTS_INOVER7_Pos) /*!< PSIO_T::TRANSTS: INOVER7 Mask */ + +#define PSIO_TRANSTS_OUTEPY7_Pos (30) /*!< PSIO_T::TRANSTS: OUTEPY7 Position */ +#define PSIO_TRANSTS_OUTEPY7_Msk (0x1ul << PSIO_TRANSTS_OUTEPY7_Pos) /*!< PSIO_T::TRANSTS: OUTEPY7 Mask */ + +#define PSIO_TRANSTS_OUTUF7_Pos (31) /*!< PSIO_T::TRANSTS: OUTUF7 Position */ +#define PSIO_TRANSTS_OUTUF7_Msk (0x1ul << PSIO_TRANSTS_OUTUF7_Pos) /*!< PSIO_T::TRANSTS: OUTUF7 Mask */ + +#define PSIO_ISSTS_VALID0_Pos (0) /*!< PSIO_T::ISSTS: VALID0 Position */ +#define PSIO_ISSTS_VALID0_Msk (0x1ul << PSIO_ISSTS_VALID0_Pos) /*!< PSIO_T::ISSTS: VALID0 Mask */ + +#define PSIO_ISSTS_INSTSOV0_Pos (1) /*!< PSIO_T::ISSTS: INSTSOV0 Position */ +#define PSIO_ISSTS_INSTSOV0_Msk (0x1ul << PSIO_ISSTS_INSTSOV0_Pos) /*!< PSIO_T::ISSTS: INSTSOV0 Mask */ + +#define PSIO_ISSTS_VALID1_Pos (2) /*!< PSIO_T::ISSTS: VALID1 Position */ +#define PSIO_ISSTS_VALID1_Msk (0x1ul << PSIO_ISSTS_VALID1_Pos) /*!< PSIO_T::ISSTS: VALID1 Mask */ + +#define PSIO_ISSTS_INSTSOV1_Pos (3) /*!< PSIO_T::ISSTS: INSTSOV1 Position */ +#define PSIO_ISSTS_INSTSOV1_Msk (0x1ul << PSIO_ISSTS_INSTSOV1_Pos) /*!< PSIO_T::ISSTS: INSTSOV1 Mask */ + +#define PSIO_ISSTS_VALID2_Pos (4) /*!< PSIO_T::ISSTS: VALID2 Position */ +#define PSIO_ISSTS_VALID2_Msk (0x1ul << PSIO_ISSTS_VALID2_Pos) /*!< PSIO_T::ISSTS: VALID2 Mask */ + +#define PSIO_ISSTS_INSTSOV2_Pos (5) /*!< PSIO_T::ISSTS: INSTSOV2 Position */ +#define PSIO_ISSTS_INSTSOV2_Msk (0x1ul << PSIO_ISSTS_INSTSOV2_Pos) /*!< PSIO_T::ISSTS: INSTSOV2 Mask */ + +#define PSIO_ISSTS_VALID3_Pos (6) /*!< PSIO_T::ISSTS: VALID3 Position */ +#define PSIO_ISSTS_VALID3_Msk (0x1ul << PSIO_ISSTS_VALID3_Pos) /*!< PSIO_T::ISSTS: VALID3 Mask */ + +#define PSIO_ISSTS_INSTSOV3_Pos (7) /*!< PSIO_T::ISSTS: INSTSOV3 Position */ +#define PSIO_ISSTS_INSTSOV3_Msk (0x1ul << PSIO_ISSTS_INSTSOV3_Pos) /*!< PSIO_T::ISSTS: INSTSOV3 Mask */ + +#define PSIO_ISSTS_VALID4_Pos (8) /*!< PSIO_T::ISSTS: VALID4 Position */ +#define PSIO_ISSTS_VALID4_Msk (0x1ul << PSIO_ISSTS_VALID4_Pos) /*!< PSIO_T::ISSTS: VALID4 Mask */ + +#define PSIO_ISSTS_INSTSOV4_Pos (9) /*!< PSIO_T::ISSTS: INSTSOV4 Position */ +#define PSIO_ISSTS_INSTSOV4_Msk (0x1ul << PSIO_ISSTS_INSTSOV4_Pos) /*!< PSIO_T::ISSTS: INSTSOV4 Mask */ + +#define PSIO_ISSTS_VALID5_Pos (10) /*!< PSIO_T::ISSTS: VALID5 Position */ +#define PSIO_ISSTS_VALID5_Msk (0x1ul << PSIO_ISSTS_VALID5_Pos) /*!< PSIO_T::ISSTS: VALID5 Mask */ + +#define PSIO_ISSTS_INSTSOV5_Pos (11) /*!< PSIO_T::ISSTS: INSTSOV5 Position */ +#define PSIO_ISSTS_INSTSOV5_Msk (0x1ul << PSIO_ISSTS_INSTSOV5_Pos) /*!< PSIO_T::ISSTS: INSTSOV5 Mask */ + +#define PSIO_ISSTS_VALID6_Pos (12) /*!< PSIO_T::ISSTS: VALID6 Position */ +#define PSIO_ISSTS_VALID6_Msk (0x1ul << PSIO_ISSTS_VALID6_Pos) /*!< PSIO_T::ISSTS: VALID6 Mask */ + +#define PSIO_ISSTS_INSTSOV6_Pos (13) /*!< PSIO_T::ISSTS: INSTSOV6 Position */ +#define PSIO_ISSTS_INSTSOV6_Msk (0x1ul << PSIO_ISSTS_INSTSOV6_Pos) /*!< PSIO_T::ISSTS: INSTSOV6 Mask */ + +#define PSIO_ISSTS_VALID7_Pos (14) /*!< PSIO_T::ISSTS: VALID7 Position */ +#define PSIO_ISSTS_VALID7_Msk (0x1ul << PSIO_ISSTS_VALID7_Pos) /*!< PSIO_T::ISSTS: VALID7 Mask */ + +#define PSIO_ISSTS_INSTSOV7_Pos (15) /*!< PSIO_T::ISSTS: INSTSOV7 Position */ +#define PSIO_ISSTS_INSTSOV7_Msk (0x1ul << PSIO_ISSTS_INSTSOV7_Pos) /*!< PSIO_T::ISSTS: INSTSOV7 Mask */ + +#define PSIO_PDMACTL_OPIN0EN_Pos (0) /*!< PSIO_T::PDMACTL: OPIN0EN Position */ +#define PSIO_PDMACTL_OPIN0EN_Msk (0x1ul << PSIO_PDMACTL_OPIN0EN_Pos) /*!< PSIO_T::PDMACTL: OPIN0EN Mask */ + +#define PSIO_PDMACTL_OPIN1EN_Pos (1) /*!< PSIO_T::PDMACTL: OPIN1EN Position */ +#define PSIO_PDMACTL_OPIN1EN_Msk (0x1ul << PSIO_PDMACTL_OPIN1EN_Pos) /*!< PSIO_T::PDMACTL: OPIN1EN Mask */ + +#define PSIO_PDMACTL_OPIN2EN_Pos (2) /*!< PSIO_T::PDMACTL: OPIN2EN Position */ +#define PSIO_PDMACTL_OPIN2EN_Msk (0x1ul << PSIO_PDMACTL_OPIN2EN_Pos) /*!< PSIO_T::PDMACTL: OPIN2EN Mask */ + +#define PSIO_PDMACTL_OPIN3EN_Pos (3) /*!< PSIO_T::PDMACTL: OPIN3EN Position */ +#define PSIO_PDMACTL_OPIN3EN_Msk (0x1ul << PSIO_PDMACTL_OPIN3EN_Pos) /*!< PSIO_T::PDMACTL: OPIN3EN Mask */ + +#define PSIO_PDMACTL_OPIN4EN_Pos (4) /*!< PSIO_T::PDMACTL: OPIN4EN Position */ +#define PSIO_PDMACTL_OPIN4EN_Msk (0x1ul << PSIO_PDMACTL_OPIN4EN_Pos) /*!< PSIO_T::PDMACTL: OPIN4EN Mask */ + +#define PSIO_PDMACTL_OPIN5EN_Pos (5) /*!< PSIO_T::PDMACTL: OPIN5EN Position */ +#define PSIO_PDMACTL_OPIN5EN_Msk (0x1ul << PSIO_PDMACTL_OPIN5EN_Pos) /*!< PSIO_T::PDMACTL: OPIN5EN Mask */ + +#define PSIO_PDMACTL_OPIN6EN_Pos (6) /*!< PSIO_T::PDMACTL: OPIN6EN Position */ +#define PSIO_PDMACTL_OPIN6EN_Msk (0x1ul << PSIO_PDMACTL_OPIN6EN_Pos) /*!< PSIO_T::PDMACTL: OPIN6EN Mask */ + +#define PSIO_PDMACTL_OPIN7EN_Pos (7) /*!< PSIO_T::PDMACTL: OPIN7EN Position */ +#define PSIO_PDMACTL_OPIN7EN_Msk (0x1ul << PSIO_PDMACTL_OPIN7EN_Pos) /*!< PSIO_T::PDMACTL: OPIN7EN Mask */ + +#define PSIO_PDMACTL_IPIN0EN_Pos (8) /*!< PSIO_T::PDMACTL: IPIN0EN Position */ +#define PSIO_PDMACTL_IPIN0EN_Msk (0x1ul << PSIO_PDMACTL_IPIN0EN_Pos) /*!< PSIO_T::PDMACTL: IPIN0EN Mask */ + +#define PSIO_PDMACTL_IPIN1EN_Pos (9) /*!< PSIO_T::PDMACTL: IPIN1EN Position */ +#define PSIO_PDMACTL_IPIN1EN_Msk (0x1ul << PSIO_PDMACTL_IPIN1EN_Pos) /*!< PSIO_T::PDMACTL: IPIN1EN Mask */ + +#define PSIO_PDMACTL_IPIN2EN_Pos (10) /*!< PSIO_T::PDMACTL: IPIN2EN Position */ +#define PSIO_PDMACTL_IPIN2EN_Msk (0x1ul << PSIO_PDMACTL_IPIN2EN_Pos) /*!< PSIO_T::PDMACTL: IPIN2EN Mask */ + +#define PSIO_PDMACTL_IPIN3EN_Pos (11) /*!< PSIO_T::PDMACTL: IPIN3EN Position */ +#define PSIO_PDMACTL_IPIN3EN_Msk (0x1ul << PSIO_PDMACTL_IPIN3EN_Pos) /*!< PSIO_T::PDMACTL: IPIN3EN Mask */ + +#define PSIO_PDMACTL_IPIN4EN_Pos (12) /*!< PSIO_T::PDMACTL: IPIN4EN Position */ +#define PSIO_PDMACTL_IPIN4EN_Msk (0x1ul << PSIO_PDMACTL_IPIN4EN_Pos) /*!< PSIO_T::PDMACTL: IPIN4EN Mask */ + +#define PSIO_PDMACTL_IPIN5EN_Pos (13) /*!< PSIO_T::PDMACTL: IPIN5EN Position */ +#define PSIO_PDMACTL_IPIN5EN_Msk (0x1ul << PSIO_PDMACTL_IPIN5EN_Pos) /*!< PSIO_T::PDMACTL: IPIN5EN Mask */ + +#define PSIO_PDMACTL_IPIN6EN_Pos (14) /*!< PSIO_T::PDMACTL: IPIN6EN Position */ +#define PSIO_PDMACTL_IPIN6EN_Msk (0x1ul << PSIO_PDMACTL_IPIN6EN_Pos) /*!< PSIO_T::PDMACTL: IPIN6EN Mask */ + +#define PSIO_PDMACTL_IPIN7EN_Pos (15) /*!< PSIO_T::PDMACTL: IPIN7EN Position */ +#define PSIO_PDMACTL_IPIN7EN_Msk (0x1ul << PSIO_PDMACTL_IPIN7EN_Pos) /*!< PSIO_T::PDMACTL: IPIN7EN Mask */ + +#define PSIO_PDMACTL_OUTNUM_Pos (16) /*!< PSIO_T::PDMACTL: OUTNUM Position */ +#define PSIO_PDMACTL_OUTNUM_Msk (0xful << PSIO_PDMACTL_OUTNUM_Pos) /*!< PSIO_T::PDMACTL: OUTNUM Mask */ + +#define PSIO_PDMACTL_OUTSCSEL_Pos (20) /*!< PSIO_T::PDMACTL: OUTSCSEL Position */ +#define PSIO_PDMACTL_OUTSCSEL_Msk (0x3ul << PSIO_PDMACTL_OUTSCSEL_Pos) /*!< PSIO_T::PDMACTL: OUTSCSEL Mask */ + +#define PSIO_PDMACTL_INNUM_Pos (24) /*!< PSIO_T::PDMACTL: INNUM Position */ +#define PSIO_PDMACTL_INNUM_Msk (0xful << PSIO_PDMACTL_INNUM_Pos) /*!< PSIO_T::PDMACTL: INNUM Mask */ + +#define PSIO_PDMACTL_INSCSEL_Pos (28) /*!< PSIO_T::PDMACTL: INSCSEL Position */ +#define PSIO_PDMACTL_INSCSEL_Msk (0x3ul << PSIO_PDMACTL_INSCSEL_Pos) /*!< PSIO_T::PDMACTL: INSCSEL Mask */ + +#define PSIO_PODAT_PDMAOUT_Pos (0) /*!< PSIO_T::PODAT: PDMAOUT Position */ +#define PSIO_PODAT_PDMAOUT_Msk (0xfffffffful << PSIO_PODAT_PDMAOUT_Pos) /*!< PSIO_T::PODAT: PDMAOUT Mask */ + +#define PSIO_PIDAT_PDMAIN_Pos (0) /*!< PSIO_T::PIDAT: PDMAIN Position */ +#define PSIO_PIDAT_PDMAIN_Msk (0xfffffffful << PSIO_PIDAT_PDMAIN_Pos) /*!< PSIO_T::PIDAT: PDMAIN Mask */ + +#define PSIO_SCCT_SCCTL_INISLOT_Pos (0) /*!< PSIO_T::SCCTL: INISLOT Position */ +#define PSIO_SCCT_SCCTL_INISLOT_Msk (0xful << PSIO_SCCT_SCCTL_INISLOT_Pos) /*!< PSIO_T::SCCTL: INISLOT Mask */ + +#define PSIO_SCCT_SCCTL_ENDSLOT_Pos (4) /*!< PSIO_T::SCCTL: ENDSLOT Position */ +#define PSIO_SCCT_SCCTL_ENDSLOT_Msk (0xful << PSIO_SCCT_SCCTL_ENDSLOT_Pos) /*!< PSIO_T::SCCTL: ENDSLOT Mask */ + +#define PSIO_SCCT_SCCTL_SPLCNT_Pos (8) /*!< PSIO_T::SCCTL: SPLCNT Position */ +#define PSIO_SCCT_SCCTL_SPLCNT_Msk (0x3ful << PSIO_SCCT_SCCTL_SPLCNT_Pos) /*!< PSIO_T::SCCTL: SPLCNT Mask */ + +#define PSIO_SCCT_SCCTL_TRIGSRC_Pos (14) /*!< PSIO_T::SCCTL: TRIGSRC Position */ +#define PSIO_SCCT_SCCTL_TRIGSRC_Msk (0x3ul << PSIO_SCCT_SCCTL_TRIGSRC_Pos) /*!< PSIO_T::SCCTL: TRIGSRC Mask */ + +#define PSIO_SCCT_SCCTL_START_Pos (16) /*!< PSIO_T::SCCTL: START Position */ +#define PSIO_SCCT_SCCTL_START_Msk (0x1ul << PSIO_SCCT_SCCTL_START_Pos) /*!< PSIO_T::SCCTL: START Mask */ + +#define PSIO_SCCT_SCCTL_REPEAT_Pos (17) /*!< PSIO_T::SCCTL: REPEAT Position */ +#define PSIO_SCCT_SCCTL_REPEAT_Msk (0x1ul << PSIO_SCCT_SCCTL_REPEAT_Pos) /*!< PSIO_T::SCCTL: REPEAT Mask */ + +#define PSIO_SCCT_SCCTL_STOP_Pos (18) /*!< PSIO_T::SCCTL: STOP Position */ +#define PSIO_SCCT_SCCTL_STOP_Msk (0x1ul << PSIO_SCCT_SCCTL_STOP_Pos) /*!< PSIO_T::SCCTL: STOP Mask */ + +#define PSIO_SCCT_SCCTL_BUSY_Pos (24) /*!< PSIO_T::SCCTL: BUSY Position */ +#define PSIO_SCCT_SCCTL_BUSY_Msk (0x1ul << PSIO_SCCT_SCCTL_BUSY_Pos) /*!< PSIO_T::SCCTL: BUSY Mask */ + +#define PSIO_SCCT_SCCTL_IDLE_Pos (25) /*!< PSIO_T::SCCTL: IDLE Position */ +#define PSIO_SCCT_SCCTL_IDLE_Msk (0x1ul << PSIO_SCCT_SCCTL_IDLE_Pos) /*!< PSIO_T::SCCTL: IDLE Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT0CNT_Pos (0) /*!< PSIO_T::SCSLOT: SLOT0CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT0CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT0CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT0CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT1CNT_Pos (4) /*!< PSIO_T::SCSLOT: SLOT1CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT1CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT1CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT1CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT2CNT_Pos (8) /*!< PSIO_T::SCSLOT: SLOT2CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT2CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT2CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT2CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT3CNT_Pos (12) /*!< PSIO_T::SCSLOT: SLOT3CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT3CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT3CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT3CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT4CNT_Pos (16) /*!< PSIO_T::SCSLOT: SLOT4CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT4CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT4CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT4CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT5CNT_Pos (20) /*!< PSIO_T::SCSLOT: SLOT5CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT5CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT5CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT5CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT6CNT_Pos (24) /*!< PSIO_T::SCSLOT: SLOT6CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT6CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT6CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT6CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT7CNT_Pos (28) /*!< PSIO_T::SCSLOT: SLOT7CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT7CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT7CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT7CNT Mask */ + +#define PSIO_GNCT_GENCTL_IOMODE_Pos (0) /*!< PSIO_T::GENCTL: IOMODE Position */ +#define PSIO_GNCT_GENCTL_IOMODE_Msk (0x3ul << PSIO_GNCT_GENCTL_IOMODE_Pos) /*!< PSIO_T::GENCTL: IOMODE Mask */ + +#define PSIO_GNCT_GENCTL_INITIAL_Pos (2) /*!< PSIO_T::GENCTL: INITIAL Position */ +#define PSIO_GNCT_GENCTL_INITIAL_Msk (0x3ul << PSIO_GNCT_GENCTL_INITIAL_Pos) /*!< PSIO_T::GENCTL: INITIAL Mask */ + +#define PSIO_GNCT_GENCTL_INTERVAL_Pos (4) /*!< PSIO_T::GENCTL: INTERVAL Position */ +#define PSIO_GNCT_GENCTL_INTERVAL_Msk (0x3ul << PSIO_GNCT_GENCTL_INTERVAL_Pos) /*!< PSIO_T::GENCTL: INTERVAL Mask */ + +#define PSIO_GNCT_GENCTL_SW0CP_Pos (8) /*!< PSIO_T::GENCTL: SW0CP Position */ +#define PSIO_GNCT_GENCTL_SW0CP_Msk (0xful << PSIO_GNCT_GENCTL_SW0CP_Pos) /*!< PSIO_T::GENCTL: SW0CP Mask */ + +#define PSIO_GNCT_GENCTL_SW1CP_Pos (12) /*!< PSIO_T::GENCTL: SW1CP Position */ +#define PSIO_GNCT_GENCTL_SW1CP_Msk (0xful << PSIO_GNCT_GENCTL_SW1CP_Pos) /*!< PSIO_T::GENCTL: SW1CP Mask */ + +#define PSIO_GNCT_GENCTL_MODESW0_Pos (16) /*!< PSIO_T::GENCTL: MODESW0 Position */ +#define PSIO_GNCT_GENCTL_MODESW0_Msk (0x3ul << PSIO_GNCT_GENCTL_MODESW0_Pos) /*!< PSIO_T::GENCTL: MODESW0 Mask */ + +#define PSIO_GNCT_GENCTL_MODESW1_Pos (18) /*!< PSIO_T::GENCTL: MODESW1 Position */ +#define PSIO_GNCT_GENCTL_MODESW1_Msk (0x3ul << PSIO_GNCT_GENCTL_MODESW1_Pos) /*!< PSIO_T::GENCTL: MODESW1 Mask */ + +#define PSIO_GNCT_GENCTL_SCSEL_Pos (24) /*!< PSIO_T::GENCTL: SCSEL Position */ +#define PSIO_GNCT_GENCTL_SCSEL_Msk (0x3ul << PSIO_GNCT_GENCTL_SCSEL_Pos) /*!< PSIO_T::GENCTL: SCSEL Mask */ + +#define PSIO_GNCT_GENCTL_PINEN_Pos (26) /*!< PSIO_T::GENCTL: PINEN Position */ +#define PSIO_GNCT_GENCTL_PINEN_Msk (0x1ul << PSIO_GNCT_GENCTL_PINEN_Pos) /*!< PSIO_T::GENCTL: PINEN Mask */ + +#define PSIO_GNCT_DATCTL_OUTDATWD_Pos (0) /*!< PSIO_T::DATCTL: OUTDATWD Position */ +#define PSIO_GNCT_DATCTL_OUTDATWD_Msk (0x1ful << PSIO_GNCT_DATCTL_OUTDATWD_Pos) /*!< PSIO_T::DATCTL: OUTDATWD Mask */ + +#define PSIO_GNCT_DATCTL_INDATWD_Pos (8) /*!< PSIO_T::DATCTL: INDATWD Position */ +#define PSIO_GNCT_DATCTL_INDATWD_Msk (0x1ful << PSIO_GNCT_DATCTL_INDATWD_Pos) /*!< PSIO_T::DATCTL: INDATWD Mask */ + +#define PSIO_GNCT_DATCTL_ORDER_Pos (16) /*!< PSIO_T::DATCTL: ORDER Position */ +#define PSIO_GNCT_DATCTL_ORDER_Msk (0x1ul << PSIO_GNCT_DATCTL_ORDER_Pos) /*!< PSIO_T::DATCTL: ORDER Mask */ + +#define PSIO_GNCT_DATCTL_OUTDEPTH_Pos (24) /*!< PSIO_T::DATCTL: OUTDEPTH Position */ +#define PSIO_GNCT_DATCTL_OUTDEPTH_Msk (0x3ul << PSIO_GNCT_DATCTL_OUTDEPTH_Pos) /*!< PSIO_T::DATCTL: OUTDEPTH Mask */ + +#define PSIO_GNCT_DATCTL_INDEPTH_Pos (28) /*!< PSIO_T::DATCTL: INDEPTH Position */ +#define PSIO_GNCT_DATCTL_INDEPTH_Msk (0x3ul << PSIO_GNCT_DATCTL_INDEPTH_Pos) /*!< PSIO_T::DATCTL: INDEPTH Mask */ + +#define PSIO_GNCT_INSTS_INSTS_Pos (0) /*!< PSIO_T::INSTS: INSTS Position */ +#define PSIO_GNCT_INSTS_INSTS_Msk (0xfful << PSIO_GNCT_INSTS_INSTS_Pos) /*!< PSIO_T::INSTS: INSTS Mask */ + +#define PSIO_GNCT_INDAT_INDAT_Pos (0) /*!< PSIO_T::INDAT: INDAT Position */ +#define PSIO_GNCT_INDAT_INDAT_Msk (0xfffffffful << PSIO_GNCT_INDAT_INDAT_Pos) /*!< PSIO_T::INDAT: INDAT Mask */ + +#define PSIO_GNCT_OUTDAT_OUTDAT_Pos (0) /*!< PSIO_T::OUTDAT: OUTDAT Position */ +#define PSIO_GNCT_OUTDAT_OUTDAT_Msk (0xfffffffful << PSIO_GNCT_OUTDAT_OUTDAT_Pos) /*!< PSIO_T::OUTDAT: OUTDAT Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT0_Pos (0) /*!< PSIO_T::CPCTL0: CKPT0 Position */ +#define PSIO_GNCT_CPCTL0_CKPT0_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT0_Pos) /*!< PSIO_T::CPCTL0: CKPT0 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT1_Pos (4) /*!< PSIO_T::CPCTL0: CKPT1 Position */ +#define PSIO_GNCT_CPCTL0_CKPT1_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT1_Pos) /*!< PSIO_T::CPCTL0: CKPT1 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT2_Pos (8) /*!< PSIO_T::CPCTL0: CKPT2 Position */ +#define PSIO_GNCT_CPCTL0_CKPT2_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT2_Pos) /*!< PSIO_T::CPCTL0: CKPT2 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT3_Pos (12) /*!< PSIO_T::CPCTL0: CKPT3 Position */ +#define PSIO_GNCT_CPCTL0_CKPT3_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT3_Pos) /*!< PSIO_T::CPCTL0: CKPT3 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT4_Pos (16) /*!< PSIO_T::CPCTL0: CKPT4 Position */ +#define PSIO_GNCT_CPCTL0_CKPT4_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT4_Pos) /*!< PSIO_T::CPCTL0: CKPT4 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT5_Pos (20) /*!< PSIO_T::CPCTL0: CKPT5 Position */ +#define PSIO_GNCT_CPCTL0_CKPT5_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT5_Pos) /*!< PSIO_T::CPCTL0: CKPT5 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT6_Pos (24) /*!< PSIO_T::CPCTL0: CKPT6 Position */ +#define PSIO_GNCT_CPCTL0_CKPT6_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT6_Pos) /*!< PSIO_T::CPCTL0: CKPT6 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT7_Pos (28) /*!< PSIO_T::CPCTL0: CKPT7 Position */ +#define PSIO_GNCT_CPCTL0_CKPT7_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT7_Pos) /*!< PSIO_T::CPCTL0: CKPT7 Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT0ACT_Pos (0) /*!< PSIO_T::CPCTL1: CKPT0ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT0ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT0ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT0ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT1ACT_Pos (4) /*!< PSIO_T::CPCTL1: CKPT1ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT1ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT1ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT1ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT2ACT_Pos (8) /*!< PSIO_T::CPCTL1: CKPT2ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT2ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT2ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT2ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT3ACT_Pos (12) /*!< PSIO_T::CPCTL1: CKPT3ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT3ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT3ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT3ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT4ACT_Pos (16) /*!< PSIO_T::CPCTL1: CKPT4ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT4ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT4ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT4ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT5ACT_Pos (20) /*!< PSIO_T::CPCTL1: CKPT5ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT5ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT5ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT5ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT6ACT_Pos (24) /*!< PSIO_T::CPCTL1: CKPT6ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT6ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT6ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT6ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT7ACT_Pos (28) /*!< PSIO_T::CPCTL1: CKPT7ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT7ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT7ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT7ACT Mask */ + +/**@}*/ /* PSIO_CONST */ +/**@}*/ /* end of PSIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __PSIO_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/qspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/qspi_reg.h new file mode 100644 index 0000000..bce44c1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/qspi_reg.h @@ -0,0 +1,619 @@ +/**************************************************************************//** + * @file qspi_reg.h + * @version V3.00 + * @brief QSPI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QSPI_REG_H__ +#define __QSPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QSPI Serial Peripheral Interface Controller(QSPI) + Memory Mapped Structure for QSPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var QSPI_T::CTL + * Offset: 0x00 QSPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |QSPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = QSPI bus clock is idle low. + * | | |1 = QSPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). + * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer + * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = QSPI operates in full-duplex transfer. + * | | |1 = QSPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit + * | | |0 = 2-Bit Transfer mode Disabled. + * | | |1 = 2-Bit Transfer mode Enabled. + * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = QSPI unit transfer interrupt Disabled. + * | | |1 = QSPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = QSPI data is input direction. + * | | |1 = QSPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * |[23] |TXDTREN |Transmit Double Transfer Rate Mode Enable Bit + * | | |0 = TX DTR mode Disabled. + * | | |1 = TX DTR mode Enabled. + * | | |Note: QSPI Master mode supports TXDTR (Transmit Double Transfer Rate) mode, and QSPI Slave mode does not support this mode. + * @var QSPI_T::CLKDIV + * Offset: 0x04 QSPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * @var QSPI_T::SSCTL + * Offset: 0x08 QSPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = Set the QSPIx_SS line to inactive state. + * | | |1 = Set the QSPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the QSPIx_SS line at inactive state. + * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). + * | | |0 = The slave selection signal QSPIx_SS is active low. + * | | |1 = The slave selection signal QSPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit + * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var QSPI_T::PDMACTL + * Offset: 0x0C QSPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. + * @var QSPI_T::FIFOCTL + * Offset: 0x10 QSPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error + * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in QSPI Slave mode. + * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in QSPI Slave mode + * | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. + * | | |Note: Slave mode only. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * @var QSPI_T::STATUS + * Offset: 0x14 QSPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = QSPI controller is in idle state. + * | | |1 = QSPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = QSPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag + * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |QSPI Enable Status (Read Only) + * | | |0 = The QSPI controller is disabled. + * | | |1 = The QSPI controller is enabled. + * | | |Note: The QSPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var QSPI_T::STATUS2 + * Offset: 0x18 QSPI Status2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data + * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI Slave mode + * | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled. + * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]). + * | | |Note 2: Slave mode only. + * @var QSPI_T::TX + * Offset: 0x20 QSPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in SPI mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. + * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var QSPI_T::RX + * Offset: 0x30 QSPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 8-level FIFO buffers in this controller + * | | |The data receive register holds the data received from QSPI data input pin + * | | |This is a read only register. + */ + __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ + __I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ + +} QSPI_T; + +/** + @addtogroup QSPI_CONST QSPI Bit Field Definition + Constant Definitions for QSPI Controller +@{ */ + +#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */ +#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */ + +#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ +#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ + +#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ +#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ + +#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ +#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ + +#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ +#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ + +#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ +#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ + +#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ +#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ + +#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ +#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ + +#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ +#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ + +#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ +#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ + +#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ +#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ + +#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ +#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ + +#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ +#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ + +#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ +#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ + +#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ +#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ + +#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ +#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ + +#define QSPI_CTL_TXDTREN_Pos (23) /*!< QSPI_T::CTL: TXDTREN Position */ +#define QSPI_CTL_TXDTREN_Msk (0x1ul << QSPI_CTL_TXDTREN_Pos) /*!< QSPI_T::CTL: TXDTREN Mask */ + +#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ +#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ + +#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ +#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ + +#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ +#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ + +#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ +#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ + +#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ +#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ + +#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ +#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ + +#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ +#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ + +#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ +#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ + +#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ +#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ + +#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ +#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ + +#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ +#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ + +#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ +#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ + +#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ +#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ + +#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ +#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ + +#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ +#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ + +#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ +#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ + +#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ +#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ + +#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ +#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ + +#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ +#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ + +#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ +#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ + +#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ +#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ + +#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ +#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ + +#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ +#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ + +#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ +#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ + +#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ +#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ + +#define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */ +#define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */ + +#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ +#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ + +#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ +#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ + +#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ +#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ + +#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ +#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ + +#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ +#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ + +#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ +#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ + +#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ +#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ + +#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ +#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ + +#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ +#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ + +#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ +#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ + +#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ +#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ + +#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ +#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ + +#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ +#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ + +#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ +#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ + +#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ +#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ + +#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */ +#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */ + +#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ +#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ + +#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ +#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ + +#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ +#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ + +#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ +#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ + +#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ +#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ + +#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ +#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ + +#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ +#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ + +#define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */ +#define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */ + +#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ +#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ + +#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ +#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ + + +/**@}*/ /* QSPI_CONST */ +/**@}*/ /* end of QSPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __QSPI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/rtc_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/rtc_reg.h new file mode 100644 index 0000000..d806b19 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/rtc_reg.h @@ -0,0 +1,1233 @@ +/**************************************************************************//** + * @file rtc_reg.h + * @version V3.00 + * @brief RTC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_REG_H__ +#define __RTC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Real Time Clock Controller -------------------------*/ +/** + @addtogroup RTC Real Time Clock Controller(RTC) + Memory Mapped Structure for RTC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var RTC_T::INIT + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIT |RTC Initiation (Write Only) + * | | |When RTC block is powered on, RTC is at reset state. + * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leave reset state. + * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIT is a write-only field and read value will be always 0. + * @var RTC_T::FREQADJ + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FRACTION |Fraction Part + * | | |Formula: FRACTION = (fraction part of detected value) X 64. + * | | |Note: Digit in FCR must be expressed as hexadecimal number. + * |[12:8] |INTEGER |Integer Part + * | | |00000 = Integer part of detected value is 32752. + * | | |00001 = Integer part of detected value is 32753. + * | | |00010 = Integer part of detected value is 32754. + * | | |00011 = Integer part of detected value is 32755. + * | | |00100 = Integer part of detected value is 32756. + * | | |00101 = Integer part of detected value is 32757. + * | | |00110 = Integer part of detected value is 32758. + * | | |00111 = Integer part of detected value is 32759. + * | | |01000 = Integer part of detected value is 32760. + * | | |01001 = Integer part of detected value is 32761. + * | | |01010 = Integer part of detected value is 32762. + * | | |01011 = Integer part of detected value is 32763. + * | | |01100 = Integer part of detected value is 32764. + * | | |01101 = Integer part of detected value is 32765. + * | | |01110 = Integer part of detected value is 32766. + * | | |01111 = Integer part of detected value is 32767. + * | | |10000 = Integer part of detected value is 32768. + * | | |10001 = Integer part of detected value is 32769. + * | | |10010 = Integer part of detected value is 32770. + * | | |10011 = Integer part of detected value is 32771. + * | | |10100 = Integer part of detected value is 32772. + * | | |10101 = Integer part of detected value is 32773. + * | | |10110 = Integer part of detected value is 32774. + * | | |10111 = Integer part of detected value is 32775. + * | | |11000 = Integer part of detected value is 32776. + * | | |11001 = Integer part of detected value is 32777. + * | | |11010 = Integer part of detected value is 32778. + * | | |11011 = Integer part of detected value is 32779. + * | | |11100 = Integer part of detected value is 32780. + * | | |11101 = Integer part of detected value is 32781. + * | | |11110 = Integer part of detected value is 32782. + * | | |11111 = Integer part of detected value is 32783. + * |[31] |FCRBUSY |Frequency Compensation Register Write Operation Busy (Read Only) + * | | |0 = The new register write operation is acceptable. + * | | |1 = The last write operation is in progress and new register write operation prohibited. + * | | |Note: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) is enabled. + * @var RTC_T::TIME + * Offset: 0x0C RTC Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit (0~5) + * |[11:8] |MIN |1-Min Time Digit (0~9) + * |[14:12] |TENMIN |10-Min Time Digit (0~5) + * |[19:16] |HR |1-Hour Time Digit (0~9) + * |[21:20] |TENHR |10-Hour Time Digit (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CAL + * Offset: 0x10 RTC Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) + * |[11:8] |MON |1-Month Calendar Digit (0~9) + * |[12] |TENMON |10-Month Calendar Digit (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::CLKFMT + * Offset: 0x14 RTC Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24HEN |24-hour / 12-hour Time Scale Selection + * | | |The RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale. + * | | |0 = 12-hour time scale with AM and PM indication selected. + * | | |1 = 24-hour time scale selected. + * |[16] |DCOMPEN |Dynamic Compensation Enable Bit + * | | |0 = Dynamic Compensation Disabled. + * | | |1 = Dynamic Compensation Enabled. + * @var RTC_T::WEEKDAY + * Offset: 0x18 RTC Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |WEEKDAY |Day of the Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TALM + * Offset: 0x1C RTC Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CALM + * Offset: 0x20 RTC Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LEAPYEAR + * Offset: 0x24 RTC Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEAPYEAR |Leap Year Indication (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is leap year. + * @var RTC_T::INTEN + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIEN |Alarm Interrupt Enable Bit + * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. + * | | |0 = RTC Alarm interrupt Disabled. + * | | |1 = RTC Alarm interrupt Enabled. + * |[1] |TICKIEN |Time Tick Interrupt Enable Bit + * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. + * | | |0 = RTC Time Tick interrupt Disabled. + * | | |1 = RTC Time Tick interrupt Enabled. + * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit + * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. + * | | |0 = Tamper 0 interrupt Disabled. + * | | |1 = Tamper 0 interrupt Enabled. + * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit + * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. + * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. + * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit + * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. + * | | |0 = Tamper 2 interrupt Disabled. + * | | |1 = Tamper 2 interrupt Enabled. + * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit + * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. + * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. + * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit + * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. + * | | |0 = Tamper 4 interrupt Disabled. + * | | |1 = Tamper 4 interrupt Enabled. + * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit + * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. + * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. + * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit + * | | |0 = LXT Frequency Fail interrupt Disabled. + * | | |1 = LXT Frequency Fail interrupt Enabled. + * |[25] |CLKSTIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit + * | | |0 = LXT Frequency Stop interrupt Disabled. + * | | |1 = LXT Frequency Stop interrupt Enabled. + * @var RTC_T::INTSTS + * Offset: 0x2C RTC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIF |RTC Alarm Interrupt Flag + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TICKIF |RTC Time Tick Interrupt Flag + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear this bit. + * |[8] |TAMP0IF |Tamper 0 Interrupt Flag + * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). + * | | |0 = No Tamper 0 interrupt flag is generated. + * | | |1 = Tamper 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag + * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. + * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. + * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[10] |TAMP2IF |Tamper 2 Interrupt Flag + * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). + * | | |0 = No Tamper 2 interrupt flag is generated. + * | | |1 = Tamper 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag + * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or + * | | |TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. + * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. + * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[12] |TAMP4IF |Tamper 4 Interrupt Flag + * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). + * | | |0 = No Tamper 4 interrupt flag is generated. + * | | |1 = Tamper 4 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag + * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or + * | | |TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. + * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. + * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is abnormal. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * |[25] |CLKSTIF |LXT Clock Frequency Monitor Stop Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is almost stop. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * @var RTC_T::TICK + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TICK |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/128 second. + * @var RTC_T::TAMSK + * Offset: 0x34 RTC Time Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) + * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) + * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) + * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) + * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) + * | | |Note: MHR function is only for 24-hour time scale mode. + * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) + * | | |Note: MTENHR function is only for 24-hour time scale mode. + * @var RTC_T::CAMSK + * Offset: 0x38 RTC Calendar Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) + * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) + * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) + * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) + * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) + * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |SPRRWEN |Spare Register Enable Bit + * | | |0 = Spare register Disabled. + * | | |1 = Spare register Enabled. + * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. + * |[5] |SPRCSTS |SPR Clear Flag + * | | |This bit indicates if the RTC_SPR0 ~ RTC_SPR19 content is cleared when specify tamper event is detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Note 1: Writes 1 to clear this bit. + * | | |Note 2: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero. + * |[16] |LXTFCLR |LXT Clock Fail/Stop to Clear Spare Enable Bit + * | | |0 = LXT Fail/Stop to clear Spare register content Disabled. + * | | |1 = LXT Fail/Stop to clear Spare register content Enabled. + * @var RTC_T::SPR[20] + * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |Spare Register + * | | |This field is used to store back-up information defined by user. + * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, + * | | |LXT clock fail/stop event occurs if LXTFCLR(RTC_SPRCTL[16]) is 1, or after Flash mass operation. + * @var RTC_T::LXTCTL + * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LIRC32KEN |Enable LIRC32K Source + * | | |0 = LIRC32K Disabled. + * | | |1 = LIRC32K Enabled. + * |[3:1] |GAIN |Oscillator Gain Option + * | | |User can select oscillator gain according to crystal external loading and operating temperature range. + * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. + * | | |000 = Reserved. + * | | |001 = L1 mode. + * | | |010 = L2 mode. + * | | |011 = L3 mode. + * | | |100 = L4 mode. + * | | |101 = L5 mode. + * | | |110 = L6 mode. + * | | |111 = L7 mode (Default). + * |[6] |C32KSEL |Clock 32K Source Selection + * | | |0 = Clock source from external low speed crystal oscillator (LXT). + * | | |1 = Clock source from internal low speed RC 32K oscillator (LIRC32K). + * |[7] |RTCCKSEL |RTC Clock Source Selection + * | | |0 = Clock source from external low speed crystal oscillator (LXT) or internal low speed RC 32K oscillator (LIRC32K) depended on C32KSEL value. + * | | |1 = Clock source from internal low speed RC oscillator (LIRC). + * |[8] |IOCTLSEL |IO Pin Backup Control Selection + * | | |When low speed 32 kHz oscillator is disabled or TAMPxEN is disabled, + * | | |PF.4 pin (X32KO pin), PF.5 pin (X32KI pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function. + * | | |User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register. + * | | |0 = PF.4~11 pin I/O function is controlled by GPIO module. + * | | |1 = PF.4~11 pin I/O function is controlled by VBAT power domain. + * | | |Note: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled. + * @var RTC_T::GPIOCTL0 + * Offset: 0x104 RTC GPIO Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE0 |IO Operation Mode + * | | |00 = PF.4 is input only mode. + * | | |01 = PF.4 is output push pull mode. + * | | |10 = PF.4 is open drain mode. + * | | |11 = PF.4 is quasi-bidirectional mod. + * |[2] |DOUT0 |IO Output Data + * | | |0 = PF.4 output low. + * | | |1 = PF.4 output high. + * |[3] |DINOFF0 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.4 digital input path Enabled. + * | | |1 = PF.4 digital input path Disabled (digital input tied to low). + * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.4 I/O pull-up or pull-down. + * | | |00 = PF.4 pull-up and pull-down Disabled. + * | | |01 = PF.4 pull-up Enabled. + * | | |10 = PF.4 pull-down Enabled. + * | | |11 = PF.4 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode. + * |[9:8] |OPMODE1 |IO Operation Mode + * | | |00 = PF.5 is input only mode. + * | | |01 = PF.5 is output push pull mode. + * | | |10 = PF.5 is open drain mode. + * | | |11 = PF.5 is quasi-bidirectional mod. + * |[10] |DOUT1 |IO Output Data + * | | |0 = PF.5 output low. + * | | |1 = PF.5 output high. + * |[11 |DINOFF1 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.5 digital input path Enabled. + * | | |1 = PF.5 digital input path Disabled (digital input tied to low). + * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.5 I/O pull-up or pull-down. + * | | |00 = PF.5 pull-up and pull-down Disabled. + * | | |01 = PF.5 pull-up Enabled. + * | | |10 = PF.5 pull-down Enabled. + * | | |11 = PF.5 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode. + * |[17:16] |OPMODE2 |IO Operation Mode + * | | |00 = PF.6 is input only mode. + * | | |01 = PF.6 is output push pull mode. + * | | |10 = PF.6 is open drain mode. + * | | |11 = PF.6 is quasi-bidirectional mod. + * |[18] |DOUT2 |IO Output Data + * | | |0 = PF.6 output low. + * | | |1 = PF.6 output high. + * |[19 |DINOFF2 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.6 digital input path Enabled. + * | | |1 = PF.6 digital input path Disabled (digital input tied to low). + * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.6 I/O pull-up or pull-down. + * | | |00 = PF.6 pull-up and pull-down Disabled. + * | | |01 = PF.6 pull-up Enabled. + * | | |10 = PF.6 pull-down Enabled. + * | | |11 = PF.6 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode. + * |[25:24] |OPMODE3 |IO Operation Mode + * | | |00 = PF.7 is input only mode. + * | | |01 = PF.7 is output push pull mode. + * | | |10 = PF.7 is open drain mode. + * | | |11 = PF.7 is quasi-bidirectional mod. + * |[26] |DOUT3 |IO Output Data + * | | |0 = PF.7 output low. + * | | |1 = PF.7 output high. + * |[27 |DINOFF3 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.7 digital input path Enabled. + * | | |1 = PF.7 digital input path Disabled (digital input tied to low). + * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.7 I/O pull-up or pull-down. + * | | |00 = PF.7 pull-up and pull-down Disabled. + * | | |01 = PF.7 pull-up Enabled. + * | | |10 = PF.7 pull-down Enabled. + * | | |11 = PF.7 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode. + * @var RTC_T::GPIOCTL1 + * Offset: 0x108 RTC GPIO Control 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE4 |IO Operation Mode + * | | |00 = PF.8 is input only mode. + * | | |01 = PF.8 is output push pull mode. + * | | |10 = PF.8 is open drain mode. + * | | |11 = PF.8 is quasi-bidirectional mod. + * |[2] |DOUT4 |IO Output Data + * | | |0 = PF.8 output low. + * | | |1 = PF.8 output high. + * |[3] |DINOFF4 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.8 digital input path Enabled. + * | | |1 = PF.8 digital input path Disabled (digital input tied to low). + * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.8 I/O pull-up or pull-down. + * | | |00 = PF.8 pull-up and pull-down Disabled. + * | | |01 = PF.8 pull-up Enabled. + * | | |10 = PF.8 pull-down Enabled. + * | | |11 = PF.8 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode. + * |[9:8] |OPMODE5 |IO Operation Mode + * | | |00 = PF.9 is input only mode. + * | | |01 = PF.9 is output push pull mode. + * | | |10 = PF.9 is open drain mode. + * | | |11 = PF.9 is quasi-bidirectional mod. + * |[10] |DOUT5 |IO Output Data + * | | |0 = PF.9 output low. + * | | |1 = PF.9 output high. + * |[11 |DINOFF5 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.9 digital input path Enabled. + * | | |1 = PF.9 digital input path Disabled (digital input tied to low). + * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.9 I/O pull-up or pull-down. + * | | |00 = PF.9 pull-up and pull-down Disabled. + * | | |01 = PF.9 pull-up Enabled. + * | | |10 = PF.9 pull-down Enabled. + * | | |11 = PF.9 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode. + * |[17:16] |OPMODE6 |IO Operation Mode + * | | |00 = PF.10 is input only mode. + * | | |01 = PF.10 is output push pull mode. + * | | |10 = PF.10 is open drain mode. + * | | |11 = PF.10 is quasi-bidirectional mod. + * |[18] |DOUT6 |IO Output Data + * | | |0 = PF.10 output low. + * | | |1 = PF.10 output high. + * |[19 |DINOFF6 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.10 digital input path Enabled. + * | | |1 = PF.10 digital input path Disabled (digital input tied to low). + * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.10 I/O pull-up or pull-down. + * | | |00 = PF.10 pull-up and pull-down Disabled. + * | | |01 = PF.10 pull-up Enabled. + * | | |10 = PF.10 pull-down Enabled. + * | | |11 = PF.10 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode. + * |[25:24] |OPMODE7 |IO Operation Mode + * | | |00 = PF.11 is input only mode. + * | | |01 = PF.11 is output push pull mode. + * | | |10 = PF.11 is open drain mode. + * | | |11 = PF.11 is quasi-bidirectional mod. + * |[26] |DOUT7 |IO Output Data + * | | |0 = PF.11 output low. + * | | |1 = PF.11 output high. + * |[27 |DINOFF7 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.11 digital input path Enabled. + * | | |1 = PF.11 digital input path Disabled (digital input tied to low). + * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.11 I/O pull-up or pull-down. + * | | |00 = PF.11 pull-up and pull-down Disabled. + * | | |01 = PF.11 pull-up Enabled. + * | | |10 = PF.11 pull-down Enabled. + * | | |11 = PF.11 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode. + * @var RTC_T::DSTCTL + * Offset: 0x110 RTC Daylight Saving Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADDHR |Add 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. + * |[1] |SUBHR |Subtract 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. + * |[2] |DSBAK |Daylight Saving Back + * | | |0 = Daylight Saving Change is not performed. + * | | |1 = Daylight Saving Change is performed. + * @var RTC_T::TAMPCTL + * Offset: 0x120 RTC Tamper Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[23]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR2EN (RTC_TAMPCTL[31]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. + * |[3] |DYNSRC |Dynamic Reference Pattern + * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reload. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. + * | | |Note 2: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 2^10 * RTC_CLK. + * | | |001 = 2^11 * RTC_CLK. + * | | |010 = 2^12 * RTC_CLK. + * | | |011 = 2^13 * RTC_CLK. + * | | |100 = 2^14 * RTC_CLK. + * | | |101 = 2^15 * RTC_CLK. + * | | |110 = 2^16 * RTC_CLK. + * | | |111 = 2^17 * RTC_CLK. + * | | |Note: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var RTC_T::TAMPSEED + * Offset: 0x128 RTC Tamper Dynamic Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed Value + * @var RTC_T::TAMPTIME + * Offset: 0x130 RTC Tamper Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) + * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) + * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) + * | | |Note: 24-hour time scale only. + * @var RTC_T::TAMPCAL + * Offset: 0x134 RTC Tamper Calendar Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) + * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) + * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) + */ + __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ + __I uint32_t RESERVE0[1]; /* 0x4 */ + __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ + __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ + __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ + __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ + __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ + __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ + __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ + __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ + __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ + __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ + __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ + __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ + __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ + __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008c] RTC Spare Register 0 ~ 19 */ + __I uint32_t RESERVE1[28]; /* 0x90 ~ 0xfc */ + __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ + __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ + __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ + __I uint32_t RESERVE2[1]; /* 0x10c */ + __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ + __I uint32_t RESERVE3[3]; /* 0x114 ~ 0x11c */ + __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ + __I uint32_t RESERVE4[1]; /* 0x124 */ + __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ + __I uint32_t RESERVE5[1]; /* 0x12c */ + __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ + __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ + +} RTC_T; + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller + @{ +*/ + +#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */ +#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */ + +#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ +#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ + +#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */ +#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */ + +#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */ +#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */ + +#define RTC_FREQADJ_FCRBUSY_Pos (31) /*!< RTC_T::FREQADJ: FCRBUSY Position */ +#define RTC_FREQADJ_FCRBUSY_Msk (0x1ul << RTC_FREQADJ_FCRBUSY_Pos) /*!< RTC_T::FREQADJ: FCRBUSY Mask */ + +#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ +#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ + +#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ +#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ + +#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ +#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ + +#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ +#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ + +#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ +#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ + +#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ +#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ + +#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ +#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ + +#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ +#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ + +#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ +#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ + +#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ +#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ + +#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ +#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ + +#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ +#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ + +#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ +#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ + +#define RTC_CLKFMT_DCOMPEN_Pos (16) /*!< RTC_T::CLKFMT: DCOMPEN Position */ +#define RTC_CLKFMT_DCOMPEN_Msk (0x1ul << RTC_CLKFMT_DCOMPEN_Pos) /*!< RTC_T::CLKFMT: DCOMPEN Mask */ + +#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ +#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ + +#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ +#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ + +#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ +#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ + +#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ +#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ + +#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ +#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ + +#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ +#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ + +#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ +#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ + +#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ +#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ + +#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ +#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ + +#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ +#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ + +#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ +#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ + +#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ +#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ + +#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ +#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ + +#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ +#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ + +#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ +#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ + +#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ +#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ + +#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ +#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ + +#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ +#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ + +#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ +#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ + +#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ +#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ + +#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ +#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ + +#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ +#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ + +#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ +#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ + +#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ +#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ + +#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ +#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ + +#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ +#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ + +#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ +#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ + +#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ +#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ + +#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ +#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ + +#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ +#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ + +#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ +#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ + +#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ +#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ + +#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ +#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ + +#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ +#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ + +#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ +#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ + +#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ +#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ + +#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ +#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ + +#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ +#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ + +#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ +#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ + +#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ +#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ + +#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ +#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ + +#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ +#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ + +#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ +#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ + +#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ +#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ + +#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ +#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ + +#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ +#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ + +#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ +#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ + +#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ +#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ + +#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ +#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ + +#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ +#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ + +#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ +#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ + +#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ +#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ + +#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ +#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ + +#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ +#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ + +#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ +#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ + +#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ +#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ + +#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ +#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ + +#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ +#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ + +#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ +#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ + +#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ +#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ + +#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ +#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ + +#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ +#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ + +#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ +#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ + +#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ +#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ + +#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ +#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ + +#define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */ +#define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */ + +#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ +#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ + +#define RTC_LXTCTL_C32KSEL_Pos (6) /*!< RTC_T::LXTCTL: C32KSEL Position */ +#define RTC_LXTCTL_C32KSEL_Msk (0x1ul << RTC_LXTCTL_C32KSEL_Pos) /*!< RTC_T::LXTCTL: C32KSEL Mask */ + +#define RTC_LXTCTL_RTCCKSEL_Pos (7) /*!< RTC_T::LXTCTL: RTCCKSEL Position */ +#define RTC_LXTCTL_RTCCKSEL_Msk (0x1ul << RTC_LXTCTL_RTCCKSEL_Pos) /*!< RTC_T::LXTCTL: RTCCKSEL Mask */ + +#define RTC_LXTCTL_IOCTLSEL_Pos (8) /*!< RTC_T::LXTCTL: IOCTLSEL Position */ +#define RTC_LXTCTL_IOCTLSEL_Msk (0x1ul << RTC_LXTCTL_IOCTLSEL_Pos) /*!< RTC_T::LXTCTL: IOCTLSEL Mask */ + +#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ +#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ + +#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ +#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ + +#define RTC_GPIOCTL0_DINOFF0_Pos (3) /*!< RTC_T::GPIOCTL0: DINOFF0 Position */ +#define RTC_GPIOCTL0_DINOFF0_Msk (0x1ul << RTC_GPIOCTL0_DINOFF0_Pos) /*!< RTC_T::GPIOCTL0: DINOFF0 Mask */ + +#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ +#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ + +#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ +#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ + +#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ +#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ + +#define RTC_GPIOCTL0_DINOFF1_Pos (11) /*!< RTC_T::GPIOCTL0: DINOFF1 Position */ +#define RTC_GPIOCTL0_DINOFF1_Msk (0x1ul << RTC_GPIOCTL0_DINOFF1_Pos) /*!< RTC_T::GPIOCTL0: DINOFF1 Mask */ + +#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ +#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ + +#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ +#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ + +#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ +#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ + +#define RTC_GPIOCTL0_DINOFF2_Pos (19) /*!< RTC_T::GPIOCTL0: DINOFF2 Position */ +#define RTC_GPIOCTL0_DINOFF2_Msk (0x1ul << RTC_GPIOCTL0_DINOFF2_Pos) /*!< RTC_T::GPIOCTL0: DINOFF2 Mask */ + +#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ +#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ + +#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ +#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ + +#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ +#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ + +#define RTC_GPIOCTL0_DINOFF3_Pos (27) /*!< RTC_T::GPIOCTL0: DINOFF3 Position */ +#define RTC_GPIOCTL0_DINOFF3_Msk (0x1ul << RTC_GPIOCTL0_DINOFF3_Pos) /*!< RTC_T::GPIOCTL0: DINOFF3 Mask */ + +#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ +#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ + +#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ +#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ + +#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ +#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ + +#define RTC_GPIOCTL0_DINOFF4_Pos (3) /*!< RTC_T::GPIOCTL1: DINOFF4 Position */ +#define RTC_GPIOCTL0_DINOFF4_Msk (0x1ul << RTC_GPIOCTL0_DINOFF4_Pos) /*!< RTC_T::GPIOCTL1: DINOFF4 Mask */ + +#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ +#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ + +#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ +#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ + +#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ +#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ + +#define RTC_GPIOCTL0_DINOFF5_Pos (11) /*!< RTC_T::GPIOCTL1: DINOFF5 Position */ +#define RTC_GPIOCTL0_DINOFF5_Msk (0x1ul << RTC_GPIOCTL0_DINOFF5_Pos) /*!< RTC_T::GPIOCTL1: DINOFF5 Mask */ + +#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ +#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ + +#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ +#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ + +#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ +#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ + +#define RTC_GPIOCTL0_DINOFF6_Pos (19) /*!< RTC_T::GPIOCTL1: DINOFF6 Position */ +#define RTC_GPIOCTL0_DINOFF6_Msk (0x1ul << RTC_GPIOCTL0_DINOFF6_Pos) /*!< RTC_T::GPIOCTL1: DINOFF6 Mask */ + +#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ +#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ + +#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ +#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ + +#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ +#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ + +#define RTC_GPIOCTL0_DINOFF7_Pos (27) /*!< RTC_T::GPIOCTL1: DINOFF7 Position */ +#define RTC_GPIOCTL0_DINOFF7_Msk (0x1ul << RTC_GPIOCTL0_DINOFF7_Pos) /*!< RTC_T::GPIOCTL1: DINOFF7 Mask */ + +#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ +#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ + +#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ +#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ + +#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ +#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ + +#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ +#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ + +#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ +#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ + +#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ +#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ + +#define RTC_TAMPCTL_DYNSRC_Pos (3) /*!< RTC_T::TAMPCTL: DYNSRC Position */ +#define RTC_TAMPCTL_DYNSRC_Msk (0x1ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ + +#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ +#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ + +#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ +#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ + +#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ +#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ + +#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ +#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ + +#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ +#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ + +#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ +#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ + +#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ +#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ + +#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ +#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ +#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ + +#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ +#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ + +#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ +#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ + +#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ +#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ + +#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ +#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ + +#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ +#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ + +#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ +#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ +#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ + +#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ +#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ + +#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ +#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ + +#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ +#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ + +#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ +#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ + +#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ +#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ + +#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ +#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ +#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ + +#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ +#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ + +#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ +#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ + +#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ +#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ + +#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ +#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ + +#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ +#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ + +#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ +#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ + +#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ +#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ + +#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ +#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ + +#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ +#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ + +#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ +#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ + +#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ +#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ + +#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ +#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ + +#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ +#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ + + +/**@}*/ /* RTC_CONST */ +/**@}*/ /* end of RTC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __RTC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sc_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sc_reg.h new file mode 100644 index 0000000..2f767cc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sc_reg.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file sc_reg.h + * @version V3.00 + * @brief SC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_REG_H__ +#define __SC_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Smart Card Host Interface Controller -------------------------*/ +/** + @addtogroup SC Smart Card Host Interface Controller(SC) + Memory Mapped Structure for SC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SC_T::DAT + * Offset: 0x00 SC Receive/Transmit Holding Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Receive/Transmit Holding Buffer + * | | |Write Operation: + * | | |By writing data to DAT, the SC will send out an 8-bit data. + * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. + * | | |Read Operation: + * | | |By reading DAT, the SC will return an 8-bit received data. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCEN |SC Controller Enable Bit + * | | |Set this bit to 1 to enable SC operation. If this bit is cleared, + * | | |0 = SC will force all transition to IDLE state. + * | | |1 = SC controller is enabled and all function can work correctly. + * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. + * |[1] |RXOFF |RX Transition Disable Control Bit + * | | |This bit is used for disable Rx transition function. + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[2] |TXOFF |TX Transition Disable Control Bit + * | | |This bit is used for disable Tx transition function. + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTOCEN |Auto Convention Enable Bit + * | | |This bit is used for enable auto convention function. + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) + * | | |state and the first data must be 0x3B or 0x3F. + * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and + * | | |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. + * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 + * | | |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. + * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an + * | | |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. + * |[5:4] |CONSEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[7:6] |RXTRGLV |Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set + * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. + * | | |00 = Rx Buffer Trigger Level with 01 bytes. + * | | |01 = Rx Buffer Trigger Level with 02 bytes. + * | | |10 = Rx Buffer Trigger Level with 03 bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters + * | | |between different transfer directions + * | | |This field indicates the counter for the bit length of block guard time + * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this + * | | |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. + * | | |Note: The real block guard time is BGT + 1. + * |[14:13] |TMRSEL |Timer Channel Selection + * | | |00 = All internal timer function Disabled. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled. + * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. + * | | |Other configurations are reserved. + * |[15] |NSB |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU. + * | | |1= The stop bit length is 1 ETU. + * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. + * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. + * |[18:16] |RXRTY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. + * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RXRTYEN enabled + * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. + * |[19] |RXRTYEN |RX Error Retry Enable Bit + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: User must fill in the RXRTY value before enabling this bit. + * |[22:20] |TXRTY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity + * | | |error has occurred. + * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TXRTYEN enabled + * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. + * |[23] |TXRTYEN |TX Error Retry Enable Bit + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CDDBSEL |Card Detect De-bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce + * | | |sample card removal once per 128 SC module clocks. + * | | |Other configurations are reserved. + * |[26] |CDLV |Card Detect Level Selection + * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. + * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. + * | | |Note: User must select card detect level before Smart Card controller enabled. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. + * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. + * | | |1 = Last value is synchronizing. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXRST |TX Software Reset + * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[1] |RXRST |Rx Software Reset + * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by deactivation sequence. + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and + * | | |the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACTEN |Activation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by activation sequence. + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data + * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. + * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by warm reset sequence. + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the + * | | |INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data + * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform + * | | |warm reset sequence. + * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit + * | | |This bit enables Timer 0 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit + * | | |This bit enables Timer 1 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only + * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit + * | | |This bit enables Timer 2 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only + * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will + * | | |be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INITSEL |Initial Timing Selection + * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. + * | | |The unit of initial timing is SC module clock. + * | | |Activation: refer to SC Activation Sequence in Figure 7.17-54. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5. + * | | |Deactivation: refer to Deactivation Sequence in Figure 7.17-56. + * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation + * | | |at most 128 SC module clock cycles. + * |[11] |ADACEN |Auto Deactivation When Card Removal + * | | |This bit is used for enable hardware auto deactivation when smart card is removed. + * | | |0 = Auto deactivation Disabled. + * | | |1 = Auto deactivation Enabled. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence + * | | |if this bit is set + * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. + * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit + * | | |This bit enables the receiver block guard time function. + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). + * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). + * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::EGT + * Offset: 0x0C SC Extra Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extra Guard Time + * | | |This field indicates the extra guard time value. + * | | |Note: The extra guard time unit is ETU base. + * @var SC_T::RXTOUT + * Offset: 0x10 SC Receive Buffer Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter + * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by + * | | |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will + * | | |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled. + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. + * | | |Note2: Filling in all 0 to this field indicates to disable this function. + * @var SC_T::ETUCTL + * Offset: 0x14 SC Element Time Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETURDIV |ETU Rate Divider + * | | |The field is used for ETU clock rate divider. + * | | |The real ETU is ETURDIV + 1. + * | | |Note: User can configure this field, but this field must be greater than 0x04. + * @var SC_T::INTEN + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit + * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit + * | | |This field is used to enable transmit buffer empty interrupt. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit + * | | |This field is used to enable Timer0 interrupt function. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit + * | | |This field is used to enable the Timer1 interrupt function. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit + * | | |This field is used to enable Timer2 interrupt function. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit + * | | |This field is used to enable block guard time interrupt in receive direction. + * | | |0 = Block guard time interrupt Disabled. + * | | |1 = Block guard time interrupt Enabled. + * | | |Note: This bit is valid only for receive direction block guard time. + * |[7] |CDIEN |Card Detect Interrupt Enable Bit + * | | |This field is used to enable card detect interrupt + * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INITIEN |Initial End Interrupt Enable Bit + * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation + * | | |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit + * | | |This field is used to enable receiver buffer time-out interrupt. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit + * | | |This field is used to enable auto-convention error interrupt. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::INTSTS + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. + * | | |0 = Number of receive buffer is less than RXTRGLV setting. + * | | |1 = Number of receive buffer data equals the RXTRGLV setting. + * | | |Note: This bit is read only + * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, + * | | |this bit will be cleared automatically. + * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * | | |Note: This bit is read only + * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit + * | | |will be cleared automatically. + * |[2] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error + * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive + * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), + * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error + * | | |TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |TMR0IF |Timer0 Interrupt Status Flag + * | | |This field is used for Timer0 interrupt status flag. + * | | |0 = Timer0 interrupt did not occur. + * | | |1 = Timer0 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |TMR1IF |Timer1 Interrupt Status Flag + * | | |This field is used for Timer1 interrupt status flag. + * | | |0 = Timer1 interrupt did not occur. + * | | |1 = Timer1 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |TMR2IF |Timer2 Interrupt Status Flag + * | | |This field is used for Timer2 interrupt status flag. + * | | |0 = Timer2 interrupt did not occur. + * | | |1 = Timer2 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BGTIF |Block Guard Time Interrupt Status Flag + * | | |This field is used for indicate block guard time interrupt status flag in receive direction. + * | | |0 = Block guard time interrupt did not occur. + * | | |1 = Block guard time interrupt occurred. + * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag + * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). + * | | |0 = Card detect event did not occur. + * | | |1 = Card detect event occurred. + * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. + * |[8] |INITIF |Initial End Interrupt Status Flag + * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) + * | | |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. + * | | |0 = Initial sequence is not complete. + * | | |1 = Initial sequence is completed. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) + * | | |This field is used for indicate receive buffer time-out interrupt status flag. + * | | |0 = Receive buffer time-out interrupt did not occur. + * | | |1 = Receive buffer time-out interrupt occurred. + * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT + * | | |register to clear it. + * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag + * | | |This field indicates auto convention sequence error. + * | | |0 = Received TS at ATR state is 0x3B or 0x3F. + * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. + * | | |Note: This bit can be cleared by writing 1 to it. + * @var SC_T::STATUS + * Offset: 0x20 SC Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOV |Receive Overflow Error Status Flag + * | | |This bit is set when Rx buffer overflow. + * | | |0 = Rx buffer is not overflow. + * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) + * | | |This bit indicates Rx buffer empty or not. + * | | |0 = Rx buffer is not empty. + * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. + * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) + * | | |This bit indicates Rx buffer full or not. + * | | |0 = Rx buffer count is less than 4. + * | | |1 = Rx buffer count equals to 4. + * |[4] |PEF |Receiver Parity Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = Receiver parity error flag did not occur. + * | | |1 = Receiver parity error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[5] |FEF |Receiver Frame Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, + * | | |the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = Receiver frame error flag did not occur. + * | | |1 = Receiver frame error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not + * | | |set this flag. + * |[6] |BEF |Receiver Break Error Status Flag + * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state + * | | |(logic 0) is longer than a full word transmission time (that is, the total time of start bit + + * | | |data bits + parity bit + stop bit). + * | | |0 = Receiver break error flag did not occur. + * | | |1 = Receiver break error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set + * | | |this flag. + * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag + * | | |This bit is set when Tx buffer overflow. + * | | |0 = Tx buffer is not overflow. + * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |0 = Tx buffer is not empty. + * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter + * | | |Shift Register. + * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). + * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates Tx buffer full or not. + * | | |0 = Tx buffer count is less than 4. + * | | |1 = Tx buffer count equals to 4. + * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin + * | | |This bit is set whenever card has been removal. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. + * |[12] |CINSERT |Card Insert Status of SCn_CD Pin + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. + * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) + * | | |This bit is the pin status of SCn_CD. + * | | |0 = The SCn_CD pin state at low. + * | | |1 = The SCn_CD pin state at high. + * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) + * | | |This field indicates the Rx buffer pointer status + * | | |When SC controller receives one byte from external device, RXPOINT increases one + * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. + * |[21] |RXRERR |Receiver Retry Error + * | | |This bit is used for receiver error retry and set by hardware. + * | | |0 = No Rx retry transfer. + * | | |1 = Rx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), + * | | |hardware will not set this flag. + * |[22] |RXOVERR |Receiver over Retry Error + * | | |This bit is used for receiver retry counts over than retry number limitation. + * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware + * | | |will not set this flag. + * |[23] |RXACT |Receiver in Active Status Flag (Read Only) + * | | |This bit indicates Rx transfer status. + * | | |0 = This bit is cleared automatically when Rx transfer is finished. + * | | |1 = This bit is set by hardware when Rx transfer is in active. + * | | |Note: This bit is read only. + * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) + * | | |This field indicates the Tx buffer pointer status + * | | |When CPU writes data into SCn_DAT, TXPOINT increases one + * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. + * |[29] |TXRERR |Transmitter Retry Error + * | | |This bit is used for indicate transmitter error retry and set by hardware. + * | | |0 = No Tx retry transfer. + * | | |1 = Tx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TXOVERR |Transmitter over Retry Error + * | | |This bit is used for transmitter retry counts over than retry number limitation. + * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[31] |TXACT |Transmit in Active Status Flag (Read Only) + * | | |This bit indicates Tx transmit status. + * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission + * | | |has completed. + * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP + * | | |bit of the last byte has not been transmitted. + * | | |Note: This bit is read only. + * @var SC_T::PINCTL + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWREN |SCn_PWR Pin Signal + * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. + * | | |Write this field to drive SCn_PWR pin + * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. + * | | |Read this field to get SCn_PWR signal status. + * | | |0 = SCn_PWR signal status is low. + * | | |1 = SCn_PWR signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[1] |RSTEN |SCn_RST Pin Signal + * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. + * | | |Write this field to drive SCn_RST pin. + * | | |0 = Drive SCn_RST pin to low. + * | | |1 = Drive SCn_RST pin to high. + * | | |Read this field to get SCn_RST signal status. + * | | |0 = SCn_RST signal status is low. + * | | |1 = SCn_RST signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[6] |CLKKEEP |SC Clock Enable Bit + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when operating in these modes. + * |[9] |SCDATA |SCn_DATA Pin Signal + * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. + * | | |0 = Drive SCn_DATA pin to low. + * | | |1 = Drive SCn_DATA pin to high. + * | | |Read this field to get SCn_DATA signal status. + * | | |0 = SCn_DATA signal status is low. + * | | |1 = SCn_DATA signal status is high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. + * | | |Thus, do not fill in this field when SC is in these modes. + * |[11] |PWRINV |SCn_PWR Pin Inverse + * | | |This bit is used for inverse the SCn_PWR pin. + * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). + * | | |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0. + * | | |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1. + * | | |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0. + * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). + * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) + * | | |This bit is the pin status of SCn_DATA. + * | | |0 = The SCn_DATA pin status is low. + * | | |1 = The SCn_DATA pin status is high. + * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) + * | | |This bit is the pin status of SCn_PWR. + * | | |0 = SCn_PWR pin to low. + * | | |1 = SCn_PWR pin to high. + * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) + * | | |This bit is the pin status of SCn_RST. + * | | |0 = SCn_RST pin is low. + * | | |1 = SCn_RST pin is high. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL0 + * Offset: 0x28 SC Internal Timer0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer0 Counter Value + * | | |This field indicates the internal Timer0 counter values. + * | | |Note: Unit of Timer0 counter is ETU base. + * |[27:24] |OPMODE |Timer0 Operation Mode Selection + * | | |This field indicates the internal 24-bit Timer0 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer0. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL1 + * Offset: 0x2C SC Internal Timer1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 1 Counter Value + * | | |This field indicates the internal Timer1 counter values. + * | | |Note: Unit of Timer1 counter is ETU base. + * |[27:24] |OPMODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer1 operation selection. + * | | |Refer to Table 7.17-3 for programming Timer1. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL2 + * Offset: 0x30 SC Internal Timer2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 2 Counter Value + * | | |This field indicates the internal Timer2 counter values. + * | | |Note: Unit of Timer2 counter is ETU base. + * |[27:24] |OPMODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer2 operation selection + * | | |Refer to Table 7.17-3 for programming Timer2. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::UARTCTL + * Offset: 0x34 SC UART Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UARTEN |UART Mode Enable Bit + * | | |Sets this bit to enable UART mode function. + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. + * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. + * |[5:4] |WLS |Word Length Selection + * | | |This field is used for select UART data length. + * | | |00 = Word length is 8 bits. + * | | |01 = Word length is 7 bits. + * | | |10 = Word length is 6 bits. + * | | |11 = Word length is 5 bits. + * | | |Note: In smart card mode, this WLS must be '00'. + * |[6] |PBOFF |Parity Bit Disable Control + * | | |Sets this bit is used for disable parity check function. + * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. + * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit). + * |[7] |OPE |Odd Parity Enable Bit + * | | |This is used for odd/even parity selection. + * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |Note: This bit has effect only when PBOFF bit is '0'. + * @var SC_T::ACTCTL + * Offset: 0x4C SC Activation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation + * | | |This field provide the configurable cycles to extend the activation time T1 period. + * | | |The cycle scaling factor is 2048. + * | | |Extend cycles = (filled value * 2048) cycles. + * | | |Refer to SC activation sequence in Figure 7.17-4. + * | | |For example, + * | | |SCLK = 4MHz, each cycle = 0.25us,. + * | | |Filled 20 to this field + * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. + * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 + */ + __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ + __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ + __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ + __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ + __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ + __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ + __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ + __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ + __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ + __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ + __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ + __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[5]; + /** @endcond */ + __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ + +} SC_T; + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller + @{ +*/ + +#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ +#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ + +#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ +#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ + +#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ +#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ + +#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ +#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ + +#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ +#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ + +#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ +#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ + +#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ +#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ + +#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ +#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ + +#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ +#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ + +#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ +#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ + +#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ +#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ + +#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ +#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ + +#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ +#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ + +#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ +#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ + +#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ +#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ + +#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ +#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ + +#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ +#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ + +#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ +#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ + +#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ +#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ + +#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ +#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ + +#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ +#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ + +#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ +#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ + +#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ +#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ + +#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ +#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ + +#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ +#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ + +#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ +#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ + +#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ +#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ + +#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ +#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ + +#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ +#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ + +#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ +#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ + +#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ +#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ + +#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ +#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ + +#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ +#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ + +#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ +#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ + +#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ +#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ + +#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ +#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ + +#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ +#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ + +#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ +#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ + +#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ +#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ + +#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ +#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ + +#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ +#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ + +#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ +#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ + +#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ +#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ + +#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ +#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ + +#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ +#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ + +#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ +#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ + +#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ +#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ + +#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ +#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ + +#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ +#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ + +#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ +#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ + +#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ +#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ + +#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ +#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ + +#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ +#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ + +#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ +#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ + +#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ +#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ + +#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ +#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ + +#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ +#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ + +#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ +#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ + +#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ +#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ + +#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ +#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ + +#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ +#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ + +#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ +#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ + +#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ +#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ + +#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ +#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ + +#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ +#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ + +#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ +#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ + +#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ +#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ + +#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ +#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ + +#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ +#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ + +#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ +#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ + +#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ +#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ + +#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ +#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ + +#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ +#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ + +#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ +#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ + +#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ +#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ + +#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ +#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ + +#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ +#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ + +#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ +#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ + +#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ +#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ + +#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ +#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ + +#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ +#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ + +#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ +#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ + +#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ +#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ + +#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ +#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ + +#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ +#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ + +#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ +#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ + +#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ +#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ + +#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ +#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ + +#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ +#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ + +#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ +#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ + +#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ +#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ + +#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ +#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ + +#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ +#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ + +#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ +#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ + +#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ +#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ + +#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ +#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ + +#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ +#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ + +#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ +#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ + + +/**@}*/ /* SC_CONST */ +/**@}*/ /* end of SC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sdh_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sdh_reg.h new file mode 100644 index 0000000..51181c2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sdh_reg.h @@ -0,0 +1,541 @@ +/**************************************************************************//** + * @file sdh_reg.h + * @version V1.00 + * @brief SDH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SDH_REG_H__ +#define __SDH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SDH SD Card Host Interface(SDH) + Memory Mapped Structure for SDH Controller +@{ */ + +typedef struct +{ + + /** + * @var SDH_T::FB + * Offset: 0x00~0x7C Shared Buffer (FIFO) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BUFFER |Shared Buffer + * | | |Buffer for DMA transfer + * @var SDH_T::DMACTL + * Offset: 0x400 DMA Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAEN |DMA Engine Enable Bit + * | | |0 = DMA Disabled. + * | | |1 = DMA Enabled. + * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. + * | | |Note: If target abort is occurred, DMAEN will be cleared. + * |[1] |DMARST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset internal state machine and pointers + * | | |The contents of control register will not be cleared + * | | |This bit will auto be cleared after few clock cycles. + * | | |Note: The software reset DMA related registers. + * |[3] |SGEN |Scatter-gather Function Enable Bit + * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). + * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table + * | | |The format of these Pads' will be described later). + * |[9] |DMABUSY |DMA Transfer Is in Progress + * | | |This bit indicates if SD Host is granted and doing DMA transfer or not. + * | | |0 = DMA transfer is not in progress. + * | | |1 = DMA transfer is in progress. + * @var SDH_T::DMASA + * Offset: 0x408 DMA Transfer Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order + * | | |0 = PAD table is fetched in order. + * | | |1 = PAD table is fetched out of order. + * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1. + * |[31:1] |DMASA |DMA Transfer Starting Address + * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. + * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. + * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. + * @var SDH_T::DMABCNT + * Offset: 0x40C DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) + * | | |This field indicates the remained byte count of DMA transfer + * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0. + * @var SDH_T::DMAINTEN + * Offset: 0x410 DMA Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit + * | | |0 = Target abort interrupt generation Disabled during DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during DMA transfer. + * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit + * | | |0 = Interrupt generation Disabled when wrong EOT is encountered. + * | | |1 = Interrupt generation Enabled when wrong EOT is encountered. + * @var SDH_T::DMAINTSTS + * Offset: 0x414 DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note1: This bit is read only, but can be cleared by writing '1' to it. + * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened + * | | |DMA will stop transfer and respond this event and then go to IDLE state + * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. + * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag + * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. + * | | |0 = No EOT encountered before DMA transfer finished. + * | | |1 = EOT encountered before DMA transfer finished. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::GCTL + * Offset: 0x800 Global Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset SD host + * | | |The contents of control register will not be cleared + * | | |This bit will auto cleared after reset complete. + * |[1] |SDEN |Secure Digital Functionality Enable Bit + * | | |0 = SD functionality disabled. + * | | |1 = SD functionality enabled. + * @var SDH_T::GINTEN + * Offset: 0x804 Global Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit + * | | |0 = DMA READ/WRITE target abort interrupt generation disabled. + * | | |1 = DMA READ/WRITE target abort interrupt generation enabled. + * @var SDH_T::GINTSTS + * Offset: 0x808 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation + * | | |When Target Abort is occurred, please reset all engine. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::CTL + * Offset: 0x820 SD Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |COEN |Command Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output a command to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[1] |RIEN |Response Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[2] |DIEN |Data Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[3] |DOEN |Data Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[4] |R2EN |Response R2 Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 74 clock cycles to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 8 clock cycles. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[7] |CLKKEEP |SD Clock Enable Control + * | | |0 = SD host decided when to output clock and when to disable clock output automatically. + * | | |1 = SD clock always keeps free running. + * |[13:8] |CMDCODE |SD Command Code + * | | |This register contains the SD command code (0x00 - 0x3F). + * |[14] |CTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine and counters + * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared) + * | | |This bit will be auto cleared after few clock cycles. + * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection) + * | | |0 = Data bus width is 1-bit. + * | | |1 = Data bus width is 4-bit. + * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received + * | | |This field contains the block counts for data-in and data-out transfer + * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance + * | | |Don't fill 0x0 to this field. + * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). + * |[27:24] |SDNWR |NWR Parameter for Block Write Operation + * | | |This value indicates the NWR parameter for data block write operation in SD clock counts + * | | |The actual clock cycle will be SDNWR+1. + * @var SDH_T::CMDARG + * Offset: 0x824 SD Command Argument Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARGUMENT |SD Command Argument + * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card + * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. + * @var SDH_T::INTEN + * Offset: 0x828 SD Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit + * | | |0 = BLKDIF (SDH_INTEN[0]) trigger interrupt Disable. + * | | |1 = BLKDIF (SDH_INTEN[0]) trigger interrupt Enabled. + * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit + * | | |0 = CRCIF (SDH_INTEN[1]) trigger interrupt Disable. + * | | |1 = CRCIF (SDH_INTEN[1]) trigger interrupt Enabled. + * |[8] |CDIEN |SD Card Detection Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when card is inserted or removed. + * | | |0 = CDIF (SDH_INTEN[8]) trigger interrupt Disable. + * | | |1 = CDIF (SDH_INTEN[8]) trigger interrupt Enabled. + * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = RTOIF (SDH_INTEN[12]) trigger interrupt Disabled. + * | | |1 = RTOIF (SDH_INTEN[12]) trigger interrupt Enabled. + * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when data input time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = DITOIF (SDH_INTEN[13]) trigger interrupt Disabled. + * | | |1 = DITOIF (SDH_INTEN[13]) trigger interrupt Enabled. + * |[14] |WKIEN |Wake-up Signal Generating Enable Bit + * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. + * | | |0 = SD Card interrupt to wake-up chip Disabled. + * | | |1 = SD Card interrupt to wake-up chip Enabled. + * |[30] |CDSRC |SD Card Detect Source Selection + * | | |0 = From SD card's DAT3 pin. + * | | |Host need clock to got data on pin DAT3 + * | | |Please make sure CLKKEEP (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. + * | | |1 = From GPIO pin. + * @var SDH_T::INTSTS + * Offset: 0x82C SD Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has finished all data-in or data-out block transfer + * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. + * | | |0 = Not finished yet. + * | | |1 = Done. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer + * | | |When CRC error is occurred, software should reset SD engine + * | | |Some response (ex + * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag + * | | |In this condition, software should ignore CRC error and clears this bit manually. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[2] |CRC7 |CRC7 Check Status (Read Only) + * | | |SD host will check CRC7 correctness during each response in + * | | |If that response does not contain CRC7 information (ex + * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. + * | | |0 = Fault. + * | | |1 = OK. + * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only) + * | | |SD host will check CRC16 correctness after data-in transfer. + * | | |0 = Fault. + * | | |1 = OK. + * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only) + * | | |SD host will record CRC status of data-out transfer + * | | |Software could use this value to identify what type of error is during data-out transfer. + * | | |010 = Positive CRC status. + * | | |101 = Negative CRC status. + * | | |111 = SD card programming error occurs. + * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only) + * | | |This bit is the DAT0 pin status of current selected SD port. + * |[8] |CDIF |SD Card Detection Interrupt Flag (Read Only) + * | | |This bit indicates that SD card is inserted or removed + * | | |Only when CDIEN (SDH_INTEN[8]) is set to 1, this bit is active. + * | | |0 = No card is inserted or removed. + * | | |1 = There is a card inserted in or removed from SD. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Response time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Data input time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[16] |CDSTS |Card Detect Status of SD (Read Only) + * | | |This bit indicates the card detect pin status of SD, and is used for card detection + * | | |When there is a card inserted in or removed from SD, software should check this bit to confirm if there is really a card insertion or removal. + * | | |If CDSRC (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. + * | | |0 = Card removed. + * | | |1 = Card inserted. + * | | |If CDSRC (SDH_INTEN[30]) = 1, to select GPIO for card detection:. + * | | |0 = Card inserted. + * | | |1 = Card removed. + * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only) + * | | |This bit indicates the DAT1 pin status of SD port. + * @var SDH_T::RESP0 + * Offset: 0x830 SD Receiving Response Token Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RESPTK0 |SD Receiving Response Token 0 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This field contains response bit 47-16 of the response token. + * @var SDH_T::RESP1 + * Offset: 0x834 SD Receiving Response Token Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RESPTK1 |SD Receiving Response Token 1 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This register contains the bit 15-8 of the response token. + * @var SDH_T::BLEN + * Offset: 0x838 SD Block Length Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit + * | | |An 11-bit value specifies the SD transfer byte count of a block + * | | |The actual byte count is equal to BLKLEN+1. + * | | |Note: The default SD block length is 512 bytes + * @var SDH_T::TOUT + * Offset: 0x83C SD Response/Data-in Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TOUT |SD Response/Data-in Time-out Value + * | | |A 24-bit value specifies the time-out counts of response and data input + * | | |SD host controller will wait start bit of response or data-in until this value reached + * | | |The time period depends on SD engine clock frequency + * | | |Do not write a small number into this field, or you may never get response or data due to time-out. + * | | |Note: Filling 0x0 into this field will disable hardware time-out function. + */ + + __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[224]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */ + __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */ + __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */ + __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[250]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */ + __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */ + __I uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[5]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */ + __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */ + __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */ + __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */ + __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */ + __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */ + __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */ + __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */ + +} SDH_T; + + +/** + @addtogroup SDH_CONST SDH Bit Field Definition + Constant Definitions for SDH Controller +@{ */ + +#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */ +#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */ + +#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */ +#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */ + +#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */ +#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */ + +#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */ +#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */ + +#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */ +#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */ + +#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */ +#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */ + +#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */ +#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */ + +#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */ +#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */ + +#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */ +#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */ + +#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */ +#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */ + +#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */ +#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */ + +#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */ +#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */ + +#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */ +#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */ + +#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */ +#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */ + +#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */ +#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */ + +#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */ +#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */ + +#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */ +#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */ + +#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */ +#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */ + +#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */ +#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */ + +#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */ +#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */ + +#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */ +#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */ + +#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */ +#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */ + +#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */ +#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */ + +#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */ +#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */ + +#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */ +#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */ + +#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */ +#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */ + +#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */ +#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */ + +#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */ +#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */ + +#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */ +#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */ + +#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */ +#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */ + +#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */ +#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */ + +#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */ +#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */ + +#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */ +#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */ + +#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */ +#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */ + +#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */ +#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */ + +#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */ +#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */ + +#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */ +#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */ + +#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */ +#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */ + +#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */ +#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */ + +#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */ +#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */ + +#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */ +#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */ + +#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */ +#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */ + +#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */ +#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */ + +#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */ +#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */ + +#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */ +#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */ + +#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */ +#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */ + +#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */ +#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */ + +#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */ +#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */ + +#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */ +#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */ + +#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */ +#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */ + +#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */ +#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */ + +/**@}*/ /* SDH_CONST */ +/**@}*/ /* end of SDH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SDH_REG_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/spi_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/spi_reg.h new file mode 100644 index 0000000..5aaec6a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/spi_reg.h @@ -0,0 +1,861 @@ +/**************************************************************************//** + * @file spi_reg.h + * @version V3.00 + * @brief SPI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPI Serial Peripheral Interface Controller(SPI) + Memory Mapped Structure for SPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPI_T::CTL + * Offset: 0x00 SPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |SPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 4 bits and can up to 32 bits. + * | | |DWIDTH = 0x04 .... 4 bits. + * | | |DWIDTH = 0x05 .... 5 bits. + * | | |DWIDTH = 0x06 .... 6 bits. + * | | |DWIDTH = 0x07 .... 7 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). + * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for SPI transfer + * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = SPI operates in full-duplex transfer. + * | | |1 = SPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = SPI data is input direction. + * | | |1 = SPI data is output direction. + * @var SPI_T::CLKDIV + * Offset: 0x04 SPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note: Not supported in I2S mode. + * @var SPI_T::SSCTL + * Offset: 0x08 SPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the SPIx_SS line to inactive state. + * | | |1 = set the SPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the SPIx_SS line at inactive state. + * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). + * | | |0 = The slave selection signal SPIx_SS is active low. + * | | |1 = The slave selection signal SPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit + * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * | | |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * @var SPI_T::PDMACTL + * Offset: 0x0C SPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. + * @var SPI_T::FIFOCTL + * Offset: 0x10 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. This bit should be set as 0 in I2S mode. + * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error + * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode. + * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode + * | | |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. + * | | |Note: Slave mode only. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length + * @var SPI_T::STATUS + * Offset: 0x14 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = SPI controller is in idle state. + * | | |1 = SPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |SPI Enable Status (Read Only) + * | | |0 = The SPI controller is disabled. + * | | |1 = The SPI controller is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var SPI_T::STATUS2 + * Offset: 0x18 SPI Status2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data + * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode + * | | |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled. + * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]). + * | | |Note 2: Slave mode only. + * @var SPI_T::TX + * Offset: 0x20 SPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. + * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section + * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var SPI_T::RX + * Offset: 0x30 SPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from SPI data input pin + * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register + * | | |This is a read only register. + * @var SPI_T::I2SCTL + * Offset: 0x60 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Bit + * | | |0 = Disabled I2S mode. + * | | |1 = Enabled I2S mode. + * | | |Note: + * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. + * | | |2 + * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. + * |[1] |TXEN |Transmit Enable Bit + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable Bit + * | | |0 = Data receive Disabled. + * | | |1 = Data receive Enabled. + * |[3] |MUTE |Transmit Mute Enable Bit + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Transmit channel zero. + * |[5:4] |WDWIDTH |Word Width + * | | |00 = data size is 8-bit. + * | | |01 = data size is 16-bit. + * | | |10 = data size is 24-bit. + * | | |11 = data size is 32-bit. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |0 = Left channel data at high byte. + * | | |1 = Left channel data at low byte. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave + * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip + * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[15] |MCLKEN |Master Clock Enable Bit + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Bit + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29:28] |FORMAT |Data Format Selection + * | | |00 = I2S data format. + * | | |01 = MSB justified data format. + * | | |10 = PCM mode A. + * | | |11 = PCM mode B. + * |[31] |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode + * | | |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var SPI_T::I2SCLK + * Offset: 0x64 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |MCLKDIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices + * | | |The frequency of master clock, fMCLK, is determined by the following expressions: + * | | |If MCLKDIV >= 1,. + * | | |If MCLKDIV = 0,. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2 + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |The clock frequency of bit clock , fBCLK, is determined by the following expression: + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode + * | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set. + * | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock is set to SPI mode. + * | | |1 = The frequency of peripheral clock is set to I2S mode. + * |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode + * | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. + * | | |I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock is set to I2S Master mode. + * | | |1 = The frequency of peripheral clock is set to I2S Slave mode. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic is disabled. + * | | |1 = The SPI/I2S control logic is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[22] |SLVERRIF |Bit Clock Loss Interrupt Flag for Slave Mode + * | | |0 = No bit clock loss event occurred. + * | | |1 = Bit clock loss event occurred. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + __I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[11]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller +@{ */ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */ +#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */ +#define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */ +#define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */ +#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */ +#define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */ + +#define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */ +#define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */ +#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/spim_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/spim_reg.h new file mode 100644 index 0000000..59a9a34 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/spim_reg.h @@ -0,0 +1,557 @@ +/**************************************************************************//** + * @file spim_reg.h + * @version V1.00 + * @brief SPIM register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPIM_REG_H__ +#define __SPIM_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPIM Serial Peripheral Interface Controller Master Mode (SPIM) + Memory Mapped Structure for SPIM Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPIM_T::CTL0 + * Offset: 0x00 Control and Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CIPHOFF |Cipher Disable Control + * | | |0 = Cipher function Enabled. + * | | |1 = Cipher function Disabled. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * | | |Note3 : When cipher encryption/decryption is enabled, please set DESELTIM (SPIM_DMMCTL[20:16]) >= 0x10. + * | | |When cipher encryption/decryption is disabled, please set DESELTIM(SPIM_DMMCTL[20:16]) >= 0x8. + * |[2] |BALEN |Balance the AHB Control Time Between Cipher Enable and Disable Control + * | | |When cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation + * | | |Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled. + * | | |Note: Only useful when cipher is disabled. + * |[5] |B4ADDREN |4-byte Address Mode Enable Control + * | | |0 = 4-byte address mode is disabled, and 3-byte address mode is enabled. + * | | |1 = 4-byte address mode is enabled. + * | | |Note: Used for DMA write mode, DMA read mode, and DMM mode. + * |[6] |IEN |Interrupt Enable Control + * | | |0 = SPIM Interrupt Disabled. + * | | |1 = SPIM Interrupt Enabled. + * |[7] |IF |Interrupt Flag + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Write 1 to clear. + * | | |(2) Read Operation : + * | | |0 = The transfer has not finished yet. + * | | |1 = The transfer has done. + * |[12:8] |DWIDTH |Transmit/Receive Bit Length + * | | |This specifies how many bits are transmitted/received in one transmit/receive transaction. + * | | |0x7 = 8 bits. + * | | |0xF = 16 bits. + * | | |0x17 = 24 bits. + * | | |0x1F = 32 bits. + * | | |Others = Incorrect transfer result. + * | | |Note1: Only used for normal I/O mode. + * | | |Note2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer. + * |[14:13] |BURSTNUM |Transmit/Receive Burst Number + * | | |This field specifies how many transmit/receive transactions should be executed continuously in one transfer. + * | | |0x0 = Only one transmit/receive transaction will be executed in one transfer. + * | | |0x1 = Two successive transmit/receive transactions will be executed in one transfer. + * | | |0x2 = Three successive transmit/receive transactions will be executed in one transfer. + * | | |0x3 = Four successive transmit/receive transactions will be executed in one transfer. + * | | |Note: Only used for normal I/O Mode. + * |[15] |QDIODIR |SPI Interface Direction Select for Quad/Dual Mode + * | | |0 = Interface signals are input. + * | | |1 = Interface signals are output. + * | | |Note: Only used for normal I/O mode. + * |[19:16] |SUSPITV |Suspend Interval + * | | |These four bits provide the configuration of suspend interval between two successive transmit/receive transactions in a transfer + * | | |The default value is 0x00 + * | | |When BURSTNUM = 00, setting this field has no effect on transfer + * | | |The desired interval is obtained according to the following equation (from the last falling edge of current SPI clock to the first rising edge of next SPI clock): + * | | | (SUSPITV+2)*period of AHB clock + * | | | 0x0 = 2 AHB clock cycles. + * | | | 0x1 = 3 AHB clock cycles. + * | | | ...... + * | | | 0xE = 16 AHB clock cycles. + * | | | 0xF = 17 AHB clock cycles. + * | | | Note: Only used for normal I/O mode. + * |[21:20] |BITMODE |SPI Interface Bit Mode + * | | |0x0 = Standard mode. + * | | |0x1 = Dual mode. + * | | |0x2 = Quad mode. + * | | |0x3 = Reserved. + * | | |Note: Only used for normal I/O mode. + * |[23:22] |OPMODE |SPI Function Operation Mode + * | | |0x0 = Normal I/O mode. (Note1) (Note3) + * | | |0x1 = DMA write mode. (Note2) (Note3) + * | | |0x2 = DMA read mode. (Note3) + * | | |0x3 = Direct Memory Mapping mode (DMM mode) (Default). (Note4) + * | | |Note1 : After user uses Normal I/O mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note2 : In DMA write mode, hardware will send just one page program command per operation + * | | |Users must take care of cross-page cases + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * | | |Note3 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x00000000 to 0x01FFFFFF when user uses Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * | | |Note4 : For external SPI flash with 32 MB, access address range of external SPI flash address is from 0x08000000 to 0x09FFFFFF when user uses Direct Memory mapping mode (DMM mode) to read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * |[31:24] |CMDCODE |Page Program Command Code (Note4) + * | | |(1) 0x02 = Page program (Used for DMA Write mode). + * | | |(2) 0x32 = Quad page program with TYPE_1 program flow (Used for DMA Write mode). (Note3) + * | | |(3) 0x38 = Quad page program with TYPE_2 program flow (Used for DMA Write mode). (Note3) + * | | |(4) 0x40 = Quad page program with TYPE_3 program flow (Used for DMA Write mode). (Note3) + * | | |The Others = Reserved. + * | | |Read Command Code : + * | | |(1) 0x03 = Standard Read (Used for DMA Read/DMM mode). + * | | |(2) 0x0B = Fast Read (Used for DMA Read/DMM mode). + * | | |The fast read command code "0x0B" is similar to command code of standard read "0x03" except it can operate at highest possible frequency + * | | |(Note2) + * | | |(3) 0x3B = Fast Read Dual Output (Used for DMA Read/DMM mode). + * | | |(4) 0xBB = Fast Read Dual I/O (Used for DMA Read/DMM mode). + * | | |The fast read dual I/O command code "0xBB" is similar to command code of fast read dual output "0x3B" but with capability to input the address bits two bits per clock + * | | |(Note2) + * | | |(5) 0xEB = Fast quad read (Used for DMA Read/DMM mode). + * | | |(6) 0xE7 = Word quad read (Used for DMA Read/DMM mode). + * | | |The command code of word quad read "0xE7" is similar to command code of fast quad read "0xEB" except that the lowest address bit must equal to 0 and the number of dummy cycles is less than fast quad read + * | | |(Note2) + * | | |(7) 0x0D = DTR/DDR Fast read (Used for DMA Read/DMM mode). + * | | |(8) 0xBD = DTR/DDR dual read (Used for DMA Read/DMM mode). + * | | |(9) 0xED = DTR/DDR quad read (Used for DMA Read/DMM mode). + * | | |The Others command codes are Reserved. + * | | |The DTR/DDR read commands "0x0D,0xBD,0xED" improves throughput by transferring address and data on both the falling and rising edge of SPI flash clock (SPIM_CLK) + * | | |It is similar to those commands "0x0B, 0xBB, 0xEB" but allows transfer of address and data on rising edge and falling edge of SPI flash output clock + * | | |(Note2) + * | | |Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands. + * | | |Note2: See SPI flash specifications for support items. + * | | |Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 7.19-3, Figure 7.19-4, and Figure 7.19-5. + * | | |Note4: Please disable "continuous read mode" and "burst wrap mode" before DMA write mode of SPI flash controller is used to program data of external SPI flash + * | | |After user uses DMA write mode of SPI flash controller to program the content of external SPI flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). + * @var SPIM_T::CTL1 + * Offset: 0x04 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIMEN |Go and Busy Status + * | | |(1) Write Operation : + * | | |0 = No effect. + * | | |1 = Start the transfer + * | | |This bit remains set during the transfer and is automatically cleared after transfer finished. + * | | |(2) Read Operation : + * | | |0 = The transfer has done. + * | | |1 = The transfer has not finished yet. + * | | |Note: All registers should be set before writing 1 to the SPIMEN bit + * | | |When a transfer is in progress, you should not write to any register of this peripheral. + * |[1] |CACHEOFF |Cache Memory Function Disable Control + * | | |0 = Cache memory function enable. (Default value) + * | | |1 = Cache memory function disable. + * | | |Note: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enable or disable by user. + * |[2] |CCMEN |CCM (Core Coupled Memory) Mode Enable Control + * | | |0 = CCM mode disable. (Default value) + * | | |1 = CCM mode enable. + * | | |Note1: When CCM mode is enabled, the cache function will be disable by hardware automatically + * | | |When CCM mode is disabled, the cache function can be enabled or disabled by user. + * | | |Note2: When CCM mode is disabled, user accesses the core coupled memory by bus master + * | | |In this case, the SPI flash controller will send error response via HRESP bus signal to bus master. + * | | |Note3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status + * | | |When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space. + * |[3] |CDINVAL |Cache Data Invalid Enable Control + * | | |(1) Write Operation: + * | | |0 = No effect. + * | | |1 = Set all cache data to be invalid. This bit is cleared by hardware automatically. + * | | |(2) Read Operation : No effect + * | | |Note: When SPI flash memory is page erasing or whole flash erasing, please set CDINVAL to 0x1 + * | | |After user uses normal I/O mode or DMA write mode of SPI flash controller to program or erase the content of external SPI flash, please set CDINVAL to 0x1. + * |[4] |SS |Slave Select Active Enable Control + * | | |0 = SPIM_SS is in active level. + * | | |1 = SPIM_SS is in inactive level (Default). + * | | |Note: This interface can only drive one device/slave at a given time + * | | |Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer + * | | |Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 2. + * |[5] |SSACTPOL |Slave Select Active Level + * | | |It defines the active level of device/slave select signal (SPIM_SS), and we show in Table 2. + * | | |0 = The SPIM_SS slave select signal is active low. + * | | |1 = The SPIM_SS slave select signal is active high. + * |[11:8] |IDLETIME |Idle Time Interval + * | | |In DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses. + * | | |Minimum idle time = (IDLETIME + 1) * AHB clock cycle time. + * | | |Note1: Only used for DMM mode. + * | | |Note2 : AHB clock cycle time = 1/AHB clock frequency. + * |[31:16] |DIVIDER |Clock Divider Register + * | | |The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock "SCLK" on the output SPIM_CLK pin + * | | |The desired frequency is obtained according to the following equation: + * | | |Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK. + * | | |Note2: SCLK is serial SPI output clock. + * | | |Note3: Please check the specification of the used SPI flash component to decide the frequency of SPI flash clock. + * | | |Note4: For DTR/DDR read commands "0x0D, 0xBD, 0xED", the setting values of DIVIDER are only 1,2,4,8,16,32,..., where n = 0,1,2,3,4, ... + * @var SPIM_T::RXCLKDLY + * Offset: 0x0C RX Clock Delay Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DWDELSEL |SPI flash deselect time interval of DMA write mode + * | | |For DMA write mode only + * | | |This register sets the deselect time interval of SPI flash (i.e. + * | | |time interval of inactive level of SPIM_SS) when SPI flash controller operates on DMA write mode + * | | |(Note1) + * | | |Deselect time interval of DMA write mode = (DWDELSEL + 1) * AHB clock cycle time (Note2). + * | | |Note1: Please user check the used external SPI flash component to set this register value + * | | |In general case, the deselect time interval of SPI flash is greater than 50 ns when SPI flash performs the program operation. + * | | |Note2: AHB clock cycle time = 1/AHB clock frequency. + * |[18:16] |RDDLYSEL |Sampling Clock Delay Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |Determine the number of inserted delay cycles + * | | |Used to adjust the sampling clock of received data to latch the correct data. + * | | |0x0 : No delay. (Default Value) + * | | |0x1 : Delay 1 SPI flash clock. + * | | |0x2 : Delay 2 SPI flash clocks. + * | | |0x3 : Delay 3 SPI flash clocks. + * | | |... + * | | |0x7 : Delay 7 SPI flash clocks + * | | |Note : We can use manufacturer id or device id of external SPI flash component to determine the correct setting value of RDDLYSEL, and we give example as follows. + * | | |For example, manufacturer id and device id of external SPI flash for some vendor are 0xEF and 0x1234 separately + * | | |Firstly, we set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example). + * | | |If manufacturer id which reads from external SPI flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1 + * | | |According to manufacturer id reads from external SPI flash, we need to set RDDLYSEL to 0x1 to receive SPI flash data correctly. + * |[20] |RDEDGE |Sampling Clock Edge Selection for Received Data + * | | |For Normal I/O mode, DMA read mode, DMA write mode, and direct memory mapping mode + * | | |0 : Use SPI input clock rising edge to sample received data. (Default Value) + * | | |1 : Use SPI input clock falling edge to sample received data. + * @var SPIM_T::RX[4] + * Offset: 0x10 ~ 0x1C Data Receive Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXDAT |Data Receive Register + * | | |The Data Receive Registers hold the received data of the last executed transfer. + * | | |Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, received data are held in the most significant RXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first. + * | | |In a byte, received data are held in the most significant bit of RXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, received data will be held in the order SPIM_RX3[23:0], SPIM_RX2[23:0], SPIM_RX1[23:0], SPIM_RX0[23:0]. + * | | |Example 2: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, received data will be held in the order SPIM_RX0[7:0], SPIM_RX0[15:8], SPIM_RX0[23:16]. + * | | |Example 3: If SPIM_CTL0[BURSTNUM = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, received data will be held in the order SPIM_RX0[7], SPIM_RX0[6], ..., + * | | |SPIM_RX0[0]. + * @var SPIM_T::TX[4] + * Offset: 0x20 ~ 0x2C Data Transmit Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXDAT |Data Transmit Register + * | | |The Data Transmit Registers hold the data to be transmitted in next transfer. + * | | |Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM] + * | | |If BURSTNUM > 0, data are transmitted in the most significant TXDAT register first. + * | | |Number of valid-bit is specified in SPIM_CTL0[DWIDTH] + * | | |If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first. + * | | |In a byte, data are transmitted in the most significant bit of TXDAT register first. + * | | |Example 1: If SPIM_CTL0[BURSTNUM] = 0x3 and SPIM_CTL1[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX3[23:0], SPIM_TX2[23:0], SPIM_TX1[23:0], SPIM_TX0[23:0] in next transfer. + * | | |Example 2: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x17, data will be transmitted in the order SPIM_TX0[7:0], SPIM_TX0[15:8], SPIM_TX0[23:16] in next transfer. + * | | |Example 3: If SPIM_CTL0[BURSTNUM] = 0x0 and SPIM_CTL0[DWIDTH] = 0x07, data will be transmitted in the order SPIM_TX0[7], SPIM_TX0[6], ..., + * | | |SPIM_TX0[0] in next transfer. + * @var SPIM_T::SRAMADDR + * Offset: 0x30 SRAM Memory Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SRAM Memory Address + * | | |For DMA Read mode, this is the destination address for DMA transfer. + * | | |For DMA Write mode, this is the source address for DMA transfer. + * | | |Note: This address must be word-aligned. + * @var SPIM_T::DMACNT + * Offset: 0x34 DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |DMACNT |DMA Transfer Byte Count Register + * | | |It indicates the transfer length for DMA process. + * | | |Note1: The unit for counting is byte. + * | | |Note2: The number must be the multiple of 4. + * | | |Note3: Please check specification of used SPI flash to know maximum byte length of page program. + * @var SPIM_T::FADDR + * Offset: 0x38 SPI Flash Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ADDR |SPI Flash Address Register + * | | |For DMA Read mode, this is the source address for DMA transfer. + * | | |For DMA Write mode, this is the destination address for DMA transfer. + * | | |Note 1 : This address must be word-aligned. + * | | |Note 2 : For external SPI flash with 32 MB, the value of this SPI flash address register "ADDR" is from 0x00000000 to 0x01FFFFFF when user uses DMA write mode and DMA read mode to write/read external SPI flash data + * | | |Please user check size of used SPI flash component to know access address range of external SPI flash. + * @var SPIM_T::KEY1 + * Offset: 0x3C Cipher Key1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY1 |Cipher Key1 Register + * | | |This is the KEY1 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::KEY2 + * Offset: 0x40 Cipher Key2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY2 |Cipher Key2 Register + * | | |This is the KEY2 data for cipher function. + * | | |Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. + * | | |Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. + * | | |KEY1 != 0x0000_0000 and KEY2 != 0x0000_0000), cipher encryption/decryption is enabled. + * @var SPIM_T::DMMCTL + * Offset: 0x44 Direct Memory Mapping Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:8] |CRMDAT |Mode bits data for Continuous Read Mode (or performance enhance mode) (Default value = 0) + * | | |Only for direct memory mapping mode + * | | |Set the mode bits data for continuous read mode (or performance enhance mode). + * | | |When we set this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active + * | | |(Note1) + * | | |Note1 : Please check the used SPI flash specification to know the setting value of this mode bits data, and different SPI flash vendor may use different setting values. + * | | |Note2 : CRMDAT needs to used with CREN(SPIM_DMMCTL[25]). + * |[20:16] |DESELTIM |SPI Flash Deselect Time + * | | |Only for direct memory mapping mode + * | | |Set the minimum time width of SPI flash deselect time (i.e. + * | | |Minimum SPIM_SS deselect time), and we show in Figure 7.19-8. + * | | |(1) Cache function disable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 1) * AHB clock cycle time. + * | | |(2) Cache function enable : + * | | |Minimum time width of SPIM_SS deselect time = (DESELTIM + 4) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : When cipher encryption/decryption is enabled, please set this register value >= 0x10 + * | | |When cipher encryption/decryption is disabled, please set this register value >= 0x8. + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * |[24] |BWEN |16 bytes Burst Wrap Mode Enable Control Register (Default value = 0) + * | | |Only for WINBOND SPI flash, direct memory mapping mode, Cache enable, and read command code "0xEB, and 0xE7" + * | | |0 = Burst Wrap Mode Disable. (Default) + * | | |1 = Burst Wrap Mode Enable. + * | | |In direct memory mapping mode, both of quad read commands "0xEB" and "0xE7" support burst wrap mode for cache application and performance enhance + * | | |For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI flash controller, we use cache data line with 16 bytes size) + * | | |For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI flash data quickly. + * |[25] |CREN |Continuous Read Mode Enable Control + * | | |Only for direct memory mapping mode, read command codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED (Note2) + * | | |0 = Continuous Read Mode Disable. (Default) + * | | |1 = Continuous Read Mode Enable. + * | | |For read operations of SPI flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7 in Winbond SPI flash), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the "continuous read mode" bits (8 bits) after the input address data. + * | | |Note: When user uses function of continuous read mode and sets USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI flash specifications + * | | |When user uses function of continuous read mode and sets USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set by default value of WINBOND SPI flash. + * |[26] |UACTSCLK |User Sets SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |0 = According to DIVIDER(SPIM_CTL1[31:16]), ACTSCLKT(SPIM_DMMCTL[31:28]) is set by hardware automatically + * | | |(Default value) + * | | |1 = Set ACTSCLKT(SPIM_DMMCTL[31:28]) by user manually. + * | | |When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1. + * |[31:28] |ACTSCLKT |SPI Flash Active SCLK Time + * | | |Only for direct memory mapping mode, DMA write mode, and DMA read mode + * | | |This register sets time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, and we show in Figure 7.19-8. + * | | |(1) ACTSCLKT = 0 (function disable) :. + * | | |Time interval = 1 AHB clock cycle time. + * | | |(2) ACTSCLKT != 0 (function enable) : + * | | |Time interval = (ACTSCLKT + 3) * AHB clock cycle time. + * | | |Note1 : AHB clock cycle time = 1/AHB clock frequency. + * | | |Note2 : SCLK is SPI output clock + * | | |Note3 : Please check the used SPI flash specification to know the setting value of this register, and different SPI flash vendor may use different setting values. + * @var SPIM_T::CTL2 + * Offset: 0x48 Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[16] |USETEN |User Set Value Enable Control + * | | |Only for direct memory mapping mode and DMA read mode with read commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7 + * | | |0 = Hardware circuit of SPI flash controller will use the following default values of DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations automatically. + * | | |Dummy cycle number (DCNUM) : + * | | |Dummy cycle number for read command 0x03 : 0x0 + * | | |Dummy cycle number for read command 0x0B : 0x8 + * | | |Dummy cycle number for read command 0x3B : 0x8 + * | | |Dummy cycle number for read command 0xBB : 0x0 + * | | |Dummy cycle number for read command 0xEB : 0x4 + * | | |Dummy cycle number for read command 0xE7 : 0x2 + * | | |Mode bits data for continuous read mode (CRMDAT) : 0x20 + * | | |1 = If DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) are not set as above default values, user must set USETEN to 0x1, DCNUM(SPIM_CTL2[28:24]) and CRMDAT(SPIM_DMMCTL[15:8]) to configure SPI flash operations manually. + * | | |For DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1. + * |[20] |DTRMPOFF |Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |0 = mode cycle number (or performance enhance cycle number) does not equal to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |1 = mode cycle number (or performance enhance cycle number) equals to 0x0 in DTR/DDR read command codes 0x0D, 0xBD, and 0xED. + * | | |Note1 : Please check the used SPI flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED. + * |[28:24] |DCNUM |Dummy Cycle Number + * | | |Only for direct memory mapping mode and DMA read mode (Note1) + * | | |Set number of dummy cycles + * | | |(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7 : + * | | |When read command code do not need any dummy cycles (i.e. + * | | |dummy cycle number = 0x0), user must set DCNUM to 0x0. + * | | |For command code 0xBB, if both mode cycle number (or performance enhance cycle number) and dummy cycle number do not equal to 0x0 simultaneously, user must set DCNUM to "mode cycle number + dummy cycle number" by used SPI flash specification. + * | | |For command code 0xBB, if there is only dummy cycle number (i.e. + * | | |dummy cycle number != 0x0 and mode cycle number = 0x0 (or performance enhance cycle number = 0x0)), user set DCNUM to dummy cycle number by used SPI flash specification. + * | | |For command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI flash specification. + * | | |(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED : + * | | |user sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI flash specification. + * | | |Note1 : Number of dummy cycles depends on the frequency of SPI output clock, SPI flash vendor, and read command types + * | | |Please check the used SPI flash specification to know the setting value of this number of dummy cycles. + */ + __IO uint32_t CTL0; /*!< [0x0000] Control and Status Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] Control Register 1 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t RXCLKDLY; /*!< [0x000c] RX Clock Delay Control Register */ + __I uint32_t RX[4]; /*!< [0x0010] ~ [0x001C] Data Receive Register 0~3 */ + __IO uint32_t TX[4]; /*!< [0x0020] ~ [0x002C] Data Transmit Register 0~3 */ + __IO uint32_t SRAMADDR; /*!< [0x0030] SRAM Memory Address Register */ + __IO uint32_t DMACNT; /*!< [0x0034] DMA Transfer Byte Count Register */ + __IO uint32_t FADDR; /*!< [0x0038] SPI Flash Address Register */ + __O uint32_t KEY1; /*!< [0x003c] Cipher Key1 Register */ + __O uint32_t KEY2; /*!< [0x0040] Cipher Key2 Register */ + __IO uint32_t DMMCTL; /*!< [0x0044] Direct Memory Mapping Mode Control Register */ + __IO uint32_t CTL2; /*!< [0x0048] Control Register 2 */ + +} SPIM_T; + +/** + @addtogroup SPIM_CONST SPIM Bit Field Definition + Constant Definitions for SPIM Controller +@{ */ + +#define SPIM_CTL0_CIPHOFF_Pos (0) /*!< SPIM_T::CTL0: CIPHOFF Position */ +#define SPIM_CTL0_CIPHOFF_Msk (0x1ul << SPIM_CTL0_CIPHOFF_Pos) /*!< SPIM_T::CTL0: CIPHOFF Mask */ + +#define SPIM_CTL0_BALEN_Pos (2) /*!< SPIM_T::CTL0: BALEN Position */ +#define SPIM_CTL0_BALEN_Msk (0x1ul << SPIM_CTL0_BALEN_Pos) /*!< SPIM_T::CTL0: BALEN Mask */ + +#define SPIM_CTL0_B4ADDREN_Pos (5) /*!< SPIM_T::CTL0: B4ADDREN Position */ +#define SPIM_CTL0_B4ADDREN_Msk (0x1ul << SPIM_CTL0_B4ADDREN_Pos) /*!< SPIM_T::CTL0: B4ADDREN Mask */ + +#define SPIM_CTL0_IEN_Pos (6) /*!< SPIM_T::CTL0: IEN Position */ +#define SPIM_CTL0_IEN_Msk (0x1ul << SPIM_CTL0_IEN_Pos) /*!< SPIM_T::CTL0: IEN Mask */ + +#define SPIM_CTL0_IF_Pos (7) /*!< SPIM_T::CTL0: IF Position */ +#define SPIM_CTL0_IF_Msk (0x1ul << SPIM_CTL0_IF_Pos) /*!< SPIM_T::CTL0: IF Mask */ + +#define SPIM_CTL0_DWIDTH_Pos (8) /*!< SPIM_T::CTL0: DWIDTH Position */ +#define SPIM_CTL0_DWIDTH_Msk (0x1ful << SPIM_CTL0_DWIDTH_Pos) /*!< SPIM_T::CTL0: DWIDTH Mask */ + +#define SPIM_CTL0_BURSTNUM_Pos (13) /*!< SPIM_T::CTL0: BURSTNUM Position */ +#define SPIM_CTL0_BURSTNUM_Msk (0x3ul << SPIM_CTL0_BURSTNUM_Pos) /*!< SPIM_T::CTL0: BURSTNUM Mask */ + +#define SPIM_CTL0_QDIODIR_Pos (15) /*!< SPIM_T::CTL0: QDIODIR Position */ +#define SPIM_CTL0_QDIODIR_Msk (0x1ul << SPIM_CTL0_QDIODIR_Pos) /*!< SPIM_T::CTL0: QDIODIR Mask */ + +#define SPIM_CTL0_SUSPITV_Pos (16) /*!< SPIM_T::CTL0: SUSPITV Position */ +#define SPIM_CTL0_SUSPITV_Msk (0xful << SPIM_CTL0_SUSPITV_Pos) /*!< SPIM_T::CTL0: SUSPITV Mask */ + +#define SPIM_CTL0_BITMODE_Pos (20) /*!< SPIM_T::CTL0: BITMODE Position */ +#define SPIM_CTL0_BITMODE_Msk (0x3ul << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_T::CTL0: BITMODE Mask */ + +#define SPIM_CTL0_OPMODE_Pos (22) /*!< SPIM_T::CTL0: OPMODE Position */ +#define SPIM_CTL0_OPMODE_Msk (0x3ul << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_T::CTL0: OPMODE Mask */ + +#define SPIM_CTL0_CMDCODE_Pos (24) /*!< SPIM_T::CTL0: CMDCODE Position */ +#define SPIM_CTL0_CMDCODE_Msk (0xfful << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_T::CTL0: CMDCODE Mask */ + +#define SPIM_CTL1_SPIMEN_Pos (0) /*!< SPIM_T::CTL1: SPIMEN Position */ +#define SPIM_CTL1_SPIMEN_Msk (0x1ul << SPIM_CTL1_SPIMEN_Pos) /*!< SPIM_T::CTL1: SPIMEN Mask */ + +#define SPIM_CTL1_CACHEOFF_Pos (1) /*!< SPIM_T::CTL1: CACHEOFF Position */ +#define SPIM_CTL1_CACHEOFF_Msk (0x1ul << SPIM_CTL1_CACHEOFF_Pos) /*!< SPIM_T::CTL1: CACHEOFF Mask */ + +#define SPIM_CTL1_CCMEN_Pos (2) /*!< SPIM_T::CTL1: CCMEN Position */ +#define SPIM_CTL1_CCMEN_Msk (0x1ul << SPIM_CTL1_CCMEN_Pos) /*!< SPIM_T::CTL1: CCMEN Mask */ + +#define SPIM_CTL1_CDINVAL_Pos (3) /*!< SPIM_T::CTL1: CDINVAL Position */ +#define SPIM_CTL1_CDINVAL_Msk (0x1ul << SPIM_CTL1_CDINVAL_Pos) /*!< SPIM_T::CTL1: CDINVAL Mask */ + +#define SPIM_CTL1_SS_Pos (4) /*!< SPIM_T::CTL1: SS Position */ +#define SPIM_CTL1_SS_Msk (0x1ul << SPIM_CTL1_SS_Pos) /*!< SPIM_T::CTL1: SS Mask */ + +#define SPIM_CTL1_SSACTPOL_Pos (5) /*!< SPIM_T::CTL1: SSACTPOL Position */ +#define SPIM_CTL1_SSACTPOL_Msk (0x1ul << SPIM_CTL1_SSACTPOL_Pos) /*!< SPIM_T::CTL1: SSACTPOL Mask */ + +#define SPIM_CTL1_IDLETIME_Pos (8) /*!< SPIM_T::CTL1: IDLETIME Position */ +#define SPIM_CTL1_IDLETIME_Msk (0xful << SPIM_CTL1_IDLETIME_Pos) /*!< SPIM_T::CTL1: IDLETIME Mask */ + +#define SPIM_CTL1_DIVIDER_Pos (16) /*!< SPIM_T::CTL1: DIVIDER Position */ +#define SPIM_CTL1_DIVIDER_Msk (0xfffful << SPIM_CTL1_DIVIDER_Pos) /*!< SPIM_T::CTL1: DIVIDER Mask */ + +#define SPIM_RXCLKDLY_DWDELSEL_Pos (0) /*!< SPIM_T::RXCLKDLY: DWDELSEL Position */ +#define SPIM_RXCLKDLY_DWDELSEL_Msk (0xfful << SPIM_RXCLKDLY_DWDELSEL_Pos) /*!< SPIM_T::RXCLKDLY: DWDELSEL Mask */ + +#define SPIM_RXCLKDLY_RDDLYSEL_Pos (16) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Position */ +#define SPIM_RXCLKDLY_RDDLYSEL_Msk (0x7ul << SPIM_RXCLKDLY_RDDLYSEL_Pos) /*!< SPIM_T::RXCLKDLY: RDDLYSEL Mask */ + +#define SPIM_RXCLKDLY_RDEDGE_Pos (20) /*!< SPIM_T::RXCLKDLY: RDEDGE Position */ +#define SPIM_RXCLKDLY_RDEDGE_Msk (0x1ul << SPIM_RXCLKDLY_RDEDGE_Pos) /*!< SPIM_T::RXCLKDLY: RDEDGE Mask */ + +#define SPIM_RX_RXDAT_Pos (0) /*!< SPIM_T::RX[4]: RXDAT Position */ +#define SPIM_RX_RXDAT_Msk (0xfffffffful << SPIM_RX_RXDAT_Pos) /*!< SPIM_T::RX[4]: RXDAT Mask */ + +#define SPIM_TX_TXDAT_Pos (0) /*!< SPIM_T::TX[4]: TXDAT Position */ +#define SPIM_TX_TXDAT_Msk (0xfffffffful << SPIM_TX_TXDAT_Pos) /*!< SPIM_T::TX[4]: TXDAT Mask */ + +#define SPIM_SRAMADDR_ADDR_Pos (0) /*!< SPIM_T::SRAMADDR: ADDR Position */ +#define SPIM_SRAMADDR_ADDR_Msk (0xfffffffful << SPIM_SRAMADDR_ADDR_Pos) /*!< SPIM_T::SRAMADDR: ADDR Mask */ + +#define SPIM_DMACNT_DMACNT_Pos (0) /*!< SPIM_T::DMACNT: DMACNT Position */ +#define SPIM_DMACNT_DMACNT_Msk (0xfffffful << SPIM_DMACNT_DMACNT_Pos) /*!< SPIM_T::DMACNT: DMACNT Mask */ + +#define SPIM_FADDR_ADDR_Pos (0) /*!< SPIM_T::FADDR: ADDR Position */ +#define SPIM_FADDR_ADDR_Msk (0xfffffffful << SPIM_FADDR_ADDR_Pos) /*!< SPIM_T::FADDR: ADDR Mask */ + +#define SPIM_KEY1_KEY1_Pos (0) /*!< SPIM_T::KEY1: KEY1 Position */ +#define SPIM_KEY1_KEY1_Msk (0xfffffffful << SPIM_KEY1_KEY1_Pos) /*!< SPIM_T::KEY1: KEY1 Mask */ + +#define SPIM_KEY2_KEY2_Pos (0) /*!< SPIM_T::KEY2: KEY2 Position */ +#define SPIM_KEY2_KEY2_Msk (0xfffffffful << SPIM_KEY2_KEY2_Pos) /*!< SPIM_T::KEY2: KEY2 Mask */ + +#define SPIM_DMMCTL_CRMDAT_Pos (8) /*!< SPIM_T::DMMCTL: CRMDAT Position */ +#define SPIM_DMMCTL_CRMDAT_Msk (0xfful << SPIM_DMMCTL_CRMDAT_Pos) /*!< SPIM_T::DMMCTL: CRMDAT Mask */ + +#define SPIM_DMMCTL_DESELTIM_Pos (16) /*!< SPIM_T::DMMCTL: DESELTIM Position */ +#define SPIM_DMMCTL_DESELTIM_Msk (0x1ful << SPIM_DMMCTL_DESELTIM_Pos) /*!< SPIM_T::DMMCTL: DESELTIM Mask */ + +#define SPIM_DMMCTL_BWEN_Pos (24) /*!< SPIM_T::DMMCTL: BWEN Position */ +#define SPIM_DMMCTL_BWEN_Msk (0x1ul << SPIM_DMMCTL_BWEN_Pos) /*!< SPIM_T::DMMCTL: BWEN Mask */ + +#define SPIM_DMMCTL_CREN_Pos (25) /*!< SPIM_T::DMMCTL: CREN Position */ +#define SPIM_DMMCTL_CREN_Msk (0x1ul << SPIM_DMMCTL_CREN_Pos) /*!< SPIM_T::DMMCTL: CREN Mask */ + +#define SPIM_DMMCTL_UACTSCLK_Pos (26) /*!< SPIM_T::DMMCTL: UACTSCLK Position */ +#define SPIM_DMMCTL_UACTSCLK_Msk (0x1ul << SPIM_DMMCTL_UACTSCLK_Pos) /*!< SPIM_T::DMMCTL: UACTSCLK Mask */ + +#define SPIM_DMMCTL_ACTSCLKT_Pos (28) /*!< SPIM_T::DMMCTL: ACTSCLKT Position */ +#define SPIM_DMMCTL_ACTSCLKT_Msk (0xful << SPIM_DMMCTL_ACTSCLKT_Pos) /*!< SPIM_T::DMMCTL: ACTSCLKT Mask */ + +#define SPIM_CTL2_USETEN_Pos (16) /*!< SPIM_T::CTL2: USETEN Position */ +#define SPIM_CTL2_USETEN_Msk (0x1ul << SPIM_CTL2_USETEN_Pos) /*!< SPIM_T::CTL2: USETEN Mask */ + +#define SPIM_CTL2_DTRMPOFF_Pos (20) /*!< SPIM_T::CTL2: DTRMPOFF Position */ +#define SPIM_CTL2_DTRMPOFF_Msk (0x1ul << SPIM_CTL2_DTRMPOFF_Pos) /*!< SPIM_T::CTL2: DTRMPOFF Mask */ + +#define SPIM_CTL2_DCNUM_Pos (24) /*!< SPIM_T::CTL2: DCNUM Position */ +#define SPIM_CTL2_DCNUM_Msk (0x1ful << SPIM_CTL2_DCNUM_Pos) /*!< SPIM_T::CTL2: DCNUM Mask */ + +/**@}*/ /* SPIM_CONST */ +/**@}*/ /* end of SPIM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SPIM_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sys_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sys_reg.h new file mode 100644 index 0000000..b6e18f8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/sys_reg.h @@ -0,0 +1,4826 @@ +/**************************************************************************//** + * @file sys_reg.h + * @version V3.00 + * @brief SYS register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + + +/*---------------------- System Manger Controller -------------------------*/ +/** + @addtogroup SYS System Manger Controller(SYS) + Memory Mapped Structure for SYS Controller +@{ */ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number (Read Only) + * | | |This register reflects device part number code. + * | | |Software can read this register to identify which device is used. + * @var SYS_T::RSTSTS + * Offset: 0x04 System Reset Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIPRST. + * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |nRESET Pin Reset Flag + * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. + * | | |0 = No reset from nRESET pin. + * | | |1 = Pin nRESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |BODRF |BOD Reset Flag + * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |MCURF |MCU Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M4. + * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |HRESETRF |HRESET Reset Flag + * | | |The HRESET reset flag is set by the "Reset Signal" from the HRESET. + * | | |0 = No reset from HRESET. + * | | |1 = Reset from HRESET. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: HRESET includes: POR, Reset Pin, LVR, BOD, WDT, WWDT, CPU lock up, CHIP and MCU reset. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |CPULKRF |CPU Lockup Reset Flag + * | | |0 = No reset from CPU lockup happened. + * | | |1 = The Cortex-M4 lockup happened and chip is reset. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset. + * @var SYS_T::IPRST0 + * Offset: 0x08 Peripheral Reset Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload. + * | | |0 = Chip normal operation. + * | | |1 = Chip one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) + * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. + * | | |0 = Processor core normal operation. + * | | |1 = Processor core one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 controller. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA0 controller normal operation. + * | | |1 = PDMA0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |EBIRST |EBI Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the EBI controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EBI controller normal operation. + * | | |1 = EBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |EMAC0RST |EMAC0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the EMAC0 controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EMAC0 controller normal operation. + * | | |1 = EMAC0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |SDH0RST |SDH0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDH0 controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDH0 controller normal operation. + * | | |1 = SDH0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRC calculation controller normal operation. + * | | |1 = CRC calculation controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |CCAPRST |CCAP Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CCAP controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CCAP controller normal operation. + * | | |1 = CCAP controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |HSUSBDRST |HSUSBD Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the HSUSBD controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = HSUSBD controller normal operation. + * | | |1 = HSUSBD controller reset. + * |[11] |HBIRST |HBI Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the HBI controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = HBI controller normal operation. + * | | |1 = HBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRYPTO controller normal operation. + * | | |1 = CRYPTO controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |KSRST |Key Store Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the Key Store controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = Key Store controller normal operation. + * | | |1 = Key Store controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |SPIMRST |SPIM Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SPIM controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SPIM controller normal operation. + * | | |1 = SPIM controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |HSUSBHRST |HSUSBH Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the HSUSBH controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = HSUSBH controller normal operation. + * | | |1 = HSUSBH controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |SDH1RST |SDH1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDH1 controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDH1 controller normal operation. + * | | |1 = SDH1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |PDMA1RST |PDMA1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA1 controller. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA1 controller normal operation. + * | | |1 = PDMA1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[20] |CANFD0RST |CANFD0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CANFD0 controller. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = CANFD0 controller normal operation. + * | | |1 = CANFD0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[21] |CANFD1RST |CANFD1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CANFD1 controller. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = CANFD1 controller normal operation. + * | | |1 = CANFD1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[22] |CANFD2RST |CANFD2 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CANFD2 controller. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = CANFD2 controller normal operation. + * | | |1 = CANFD2 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |CANFD3RST |CANFD3 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CANFD3 controller. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = CANFD3 controller normal operation. + * | | |1 = CANFD3 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[28] |BMCRST |BMC Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the BMC controller. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = BCM controller normal operation. + * | | |1 = BMC controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IPRST1 + * Offset: 0x0C Peripheral Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIORST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset + * | | |0 = Analog Comparator 0/1 controller normal operation. + * | | |1 = Analog Comparator 0/1 controller reset. + * |[8] |I2C0RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[10] |I2C2RST |I2C2 Controller Reset + * | | |0 = I2C2 controller normal operation. + * | | |1 = I2C2 controller reset. + * |[11] |I2C3RST |I2C3 Controller Reset + * | | |0 = I2C3 controller normal operation. + * | | |1 = I2C3 controller reset. + * |[12] |QSPI0RST |QSPI0 Controller Reset + * | | |0 = QSPI0 controller normal operation. + * | | |1 = QSPI0 controller reset. + * |[13] |SPI0RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[14] |SPI1RST |SPI1 Controller Reset + * | | |0 = SPI1 controller normal operation. + * | | |1 = SPI1 controller reset. + * |[15] |SPI2RST |SPI2 Controller Reset + * | | |0 = SPI2 controller normal operation. + * | | |1 = SPI2 controller reset. + * |[16] |UART0RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[19] |UART3RST |UART3 Controller Reset + * | | |0 = UART3 controller normal operation. + * | | |1 = UART3 controller reset. + * |[20] |UART4RST |UART4 Controller Reset + * | | |0 = UART4 controller normal operation. + * | | |1 = UART4 controller reset. + * |[21] |UART5RST |UART5 Controller Reset + * | | |0 = UART5 controller normal operation. + * | | |1 = UART5 controller reset. + * |[22] |UART6RST |UART6 Controller Reset + * | | |0 = UART6 controller normal operation. + * | | |1 = UART6 controller reset. + * |[23] |UART7RST |UART7 Controller Reset + * | | |0 = UART7 controller normal operation. + * | | |1 = UART7 controller reset. + * |[26] |OTGRST |OTG Controller Reset + * | | |0 = OTG controller normal operation. + * | | |1 = OTG controller reset. + * |[27] |USBDRST |USBD Controller Reset + * | | |0 = USBD controller normal operation. + * | | |1 = USBD controller reset. + * |[28] |EADC0RST |EADC0 Controller Reset + * | | |0 = EADC0 controller normal operation. + * | | |1 = EADC0 controller reset. + * |[29] |I2S0RST |I2S0 Controller Reset + * | | |0 = I2S0 controller normal operation. + * | | |1 = I2S0 controller reset. + * |[30] |HSOTGRST |HSOTG Controller Reset + * | | |0 = HSOTG controller normal operation. + * | | |1 = HSOTG controller reset. + * |[31] |TRNGRST |TRNG Controller Reset + * | | |0 = TRNG controller normal operation. + * | | |1 = TRNG controller reset. + * @var SYS_T::IPRST2 + * Offset: 0x10 Peripheral Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[1] |SC1RST |SC1 Controller Reset + * | | |0 = SC1 controller normal operation. + * | | |1 = SC1 controller reset. + * |[2] |SC2RST |SC2 Controller Reset + * | | |0 = SC2 controller normal operation. + * | | |1 = SC2 controller reset. + * |[3] |I2C4RST |I2C4 Controller Reset + * | | |0 = I2C4 controller normal operation. + * | | |1 = I2C4 controller reset. + * |[4] |QSPI1RST |QSPI1 Controller Reset + * | | |0 = QSPI1 controller normal operation. + * | | |1 = QSPI1 controller reset. + * |[6] |SPI3RST |SPI3 Controller Reset + * | | |0 = SPI3 controller normal operation. + * | | |1 = SPI3 controller reset. + * |[7] |SPI4RST |SPI4 Controller Reset + * | | |0 = SPI4 controller normal operation. + * | | |1 = SPI4 controller reset. + * |[8] |USCI0RST |USCI0 Controller Reset + * | | |0 = USCI0 controller normal operation. + * | | |1 = USCI0 controller reset. + * |[10] |PSIORST |PSIO Controller Reset + * | | |0 = PSIO controller normal operation. + * | | |1 = PSIO controller reset. + * |[12] |DACRST |DAC Controller Reset + * | | |0 = DAC controller normal operation. + * | | |1 = DAC controller reset. + * |[13] |ECAP2RST |ECAP2 Controller Reset + * | | |0 = ECAP2 controller normal operation. + * | | |1 = ECAP2 controller reset. + * |[14] |ECAP3RST |ECAP3 Controller Reset + * | | |0 = ECAP3 controller normal operation. + * | | |1 = ECAP3 controller reset. + * |[16] |EPWM0RST |EPWM0 Controller Reset + * | | |0 = EPWM0 controller normal operation. + * | | |1 = EPWM0 controller reset. + * |[17] |EPWM1RST |EPWM1 Controller Reset + * | | |0 = EPWM1 controller normal operation. + * | | |1 = EPWM1 controller reset. + * |[18] |BPWM0RST |BPWM0 Controller Reset + * | | |0 = BPWM0 controller normal operation. + * | | |1 = BPWM0 controller reset. + * |[19] |BPWM1RST |BPWM1 Controller Reset + * | | |0 = BPWM1 controller normal operation. + * | | |1 = BPWM1 controller reset. + * |[20] |EQEI2RST |EQEI2 Controller Reset + * | | |0 = EQEI2 controller normal operation. + * | | |1 = EQEI2 controller reset. + * |[21] |EQEI3RST |EQEI3 Controller Reset + * | | |0 = EQEI3 controller normal operation. + * | | |1 = EQEI3 controller reset. + * |[22] |EQEI0RST |EQEI0 Controller Reset + * | | |0 = EQEI0 controller normal operation. + * | | |1 = EQEI0 controller reset. + * |[23] |EQEI1RST |EQEI1 Controller Reset + * | | |0 = EQEI1 controller normal operation. + * | | |1 = EQEI1 controller reset. + * |[26] |ECAP0RST |ECAP0 Controller Reset + * | | |0 = ECAP0 controller normal operation. + * | | |1 = ECAP0 controller reset. + * |[27] |ECAP1RST |ECAP1 Controller Reset + * | | |0 = ECAP1 controller normal operation. + * | | |1 = ECAP1 controller reset. + * |[29] |I2S1RST |I2S1 Controller Reset + * | | |0 = I2S1 controller normal operation. + * | | |1 = I2S1 controller reset. + * |[31] |EADC1RST |EADC1 Controller Reset + * | | |0 = EADC1 controller normal operation. + * | | |1 = EADC1 controller reset. + * @var SYS_T::BODCTL + * Offset: 0x18 Brown-out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]). + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) + * | | |The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit. + * | | |0 = Brown-out "INTERRUPT" function Enabled. + * | | |1 = Brown-out "RESET" function Enabled. + * | | |Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). + * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high + * | | |BOD interrupt will keep till to the BODEN set to 0. + * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). + * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |BODIF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) + * | | |0 = BOD operate in normal mode (default). + * | | |1 = BOD Low Power mode Enabled. + * | | |Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. + * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |BODOUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. + * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. + * | | |1 = Brown-out Detector output status is 1. + * | | |It means the detected voltage is lower than BODVL setting + * | | |If the BODEN is 0, BOD function disabled, this bit always responds 0. + * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting + * | | |LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled. + * | | |Note 1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). + * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) + * | | |000 = BOD output is sampled by LIRC clock. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[15] |LVRRDY |Low Voltage Reset Ready Flag (Read Only) + * | | |When the LVR function first enable, need more HCLK to wait LVR ready. + * | | |0 = Low Voltage Reset function not ready. + * | | |1 = Low Voltage Reset function ready. + * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]). + * | | |000 = Brown-Out Detector threshold voltage is 1.6V. + * | | |001 = Brown-Out Detector threshold voltage is 1.8V. + * | | |010 = Brown-Out Detector threshold voltage is 2.0V. + * | | |011 = Brown-Out Detector threshold voltage is 2.2V. + * | | |100 = Brown-Out Detector threshold voltage is 2.4V. + * | | |101 = Brown-Out Detector threshold voltage is 2.6V. + * | | |110 = Brown-Out Detector threshold voltage is 2.8V. + * | | |111 = Brown-Out Detector threshold voltage is 3.0V. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IVSCTL + * Offset: 0x1C Internal Voltage Source Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMPEN |Temperature Sensor Enable Bit + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit + * | | |This bit is used to enable/disable VBAT unity gain buffer function. + * | | |0 = VBAT unity gain buffer function Disabled (default). + * | | |1 = VBAT unity gain buffer function Enabled. + * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result + * @var SYS_T::IPRST3 + * Offset: 0x20 Peripheral Reset Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KPIRST |KPI Controller Reset + * | | |0 = KPI controller normal operation. + * | | |1 = KPI controller reset. + * |[6] |EADC2RST |EADC2 Controller Reset + * | | |0 = EADC2 controller normal operation. + * | | |1 = EADC2 controller reset. + * |[7] |ACMP23RST |Analog Comparator 2/3 Controller Reset + * | | |0 = Analog Comparator 2/3 controller normal operation. + * | | |1 = Analog Comparator 2/3 controller reset. + * |[8] |SPI5RST |SPI5 Controller Reset + * | | |0 = SPI5 controller normal operation. + * | | |1 = SPI5 controller reset. + * |[9] |SPI6RST |SPI6 Controller Reset + * | | |0 = SPI6 controller normal operation. + * | | |1 = SPI6 controller reset. + * |[10] |SPI7RST |SPI7 Controller Reset + * | | |0 = SPI7 controller normal operation. + * | | |1 = SPI7 controller reset. + * |[11] |SPI8RST |SPI8 Controller Reset + * | | |0 = SPI8 controller normal operation. + * | | |1 = SPI8 controller reset. + * |[12] |SPI9RST |SPI9 Controller Reset + * | | |0 = SPI9 controller normal operation. + * | | |1 = SPI9 controller reset. + * |[13] |SPI10RST |SPI10 Controller Reset + * | | |0 = SPI10 controller normal operation. + * | | |1 = SPI10 controller reset. + * |[16] |UART8RST |UART8 Controller Reset + * | | |0 = UART8 controller normal operation. + * | | |1 = UART8 controller reset. + * |[17] |UART9RST |UART9 Controller Reset + * | | |0 = UART9 controller normal operation. + * | | |1 = UART9 controller reset. + * @var SYS_T::PORCTL + * Offset: 0x24 Power-On-reset Controller Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::VREFCTL + * Offset: 0x28 VREF Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) + * | | |00000 = VREF is from external pin. + * | | |00011 = VREF is internal 1.6V. + * | | |00111 = VREF is internal 2.0V. + * | | |01011 = VREF is internal 2.5V. + * | | |01111 = VREF is internal 3.0V. + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |PRELOADSEL|Pre-load Timing Selection (Write Protect) + * | | |00 = pre-load time is 60us for 0.1uF Capacitor. + * | | |01 = pre-load time is 310us for 1uF Capacitor. + * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. + * | | |11 = pre-load time is 2650us for 10uF Capacitor. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[24] |VBGFEN |Chip Internal Voltage Bandgap Force Enable Bit (Write Protect) + * | | |0 = Chip internal voltage bandgap controlled by ADC/ACMP if source selected. + * | | |1 = Chip internal voltage bandgap force enable. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[26:25] |VBGISEL |Chip Internal Voltage Bandgap Current Selection Bits (Write Protect) + * | | |00 = Bandgap voltage buffer current is 4.2uA. + * | | |01 = Bandgap voltage buffer current is 7.3uA. + * | | |10 = Bandgap voltage buffer current is 10.4uA. + * | | |11 = Bandgap voltage buffer current is 13.5uA. + * | | |Note 1: When ADC conversion source select bandgap voltage, suggest set VBGISEL as 10. + * | | |Note 2: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::USBPHY + * Offset: 0x2C USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |USBROLE |USB Role Option (Write Protect) + * | | |These two bits are used to select the role of USB. + * | | |00 = Standard USB Device mode. + * | | |01 = Standard USB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = On-The-Go device mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable. + * |[8] |USBEN |USB PHY Enable + * | | |This bit is used to enable/disable USB PHY. + * | | |0 = USB PHY Disabled. + * | | |1 = USB PHY Enabled. + * |[17:16] |HSUSBROLE |HSUSB Role Option (Write Protect) + * | | |These two bits are used to select the role of HSUSB. + * | | |00 = Standard HSUSB Device mode. + * | | |01 = Standard HSUSB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = On-The-Go device mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[24] |HSUSBEN |HSUSB PHY Enable + * | | |This bit is used to enable/disable HSUSB PHY. + * | | |0 = HSUSB PHY Disabled. + * | | |1 = HSUSB PHY Enabled. + * |[25] |HSUSBACT |HSUSB PHY Active Control + * | | |This bit is used to control HSUSB PHY at reset state or active state. + * | | |0 = HSUSB PHY at reset state. + * | | |1 = HSUSB PHY at active state. + * | | |Note: After setting HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10us before changing to active mode. + * @var SYS_T::GPA_MFOS + * Offset: 0x80-0xA4 GPIOA-GPIOJ Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |MFOSn |GPIOA-J Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin. + * | | |0 = Multiple function pin output mode type is Push-pull mode. + * | | |1 = Multiple function pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15 for port A/B/E/G/H. + * | | |Max. n=14 for port C/D. + * | | |Max. n=11 for port F. + * | | |n=6~15 for port I. + * | | |Max. n=13 for port J. + * @var SYS_T::SRAM_INTCTL + * Offset: 0xC0 System SRAM Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit + * | | |0 = SRAM parity check error interrupt Disabled. + * | | |1 = SRAM parity check error interrupt Enabled. + * @var SYS_T::SRAM_STATUS + * Offset: 0xC4 System SRAM Parity Error Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIF |SRAM Parity Check Error Flag + * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. + * | | |0 = No System SRAM parity error. + * | | |1 = System SRAM parity error occur. + * @var SYS_T::SRAM_ERRADDR + * Offset: 0xC8 System SRAM Parity Check Error Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ERRADDR |System SRAM Parity Error Address (Read Only) + * | | |This register shows system SRAM parity error byte address. + * @var SYS_T::SRAM_BISTCTL + * Offset: 0xD0 System SRAM BIST Test Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBIST0 |System SRAM Bank0 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for system SRAM bank0. + * | | |0 = System SRAM bank0 BIST Disabled. + * | | |1 = System SRAM bank0 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |SRBIST1 |System SRAM Bank1 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for system SRAM bank1. + * | | |0 = System SRAM bank1 BIST Disabled. + * | | |1 = System SRAM bank1 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |CRBIST |CACHE SRAM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CACHE SRAM. + * | | |0 = CACHE SRAM BIST Disabled. + * | | |1 = CACHE SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |CANBIST |CAN SRAM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CAN SRAM. + * | | |0 = CAN SRAM BIST Disabled. + * | | |1 = CAN SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for USB SRAM. + * | | |0 = USB SRAM BIST Disabled. + * | | |1 = USB SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |SPIMBIST |SPIM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SPIM SRAM. + * | | |0 = SPIM SRAM BIST Disabled. + * | | |1 = SPIM SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |EMAC0BIST |EMAC0 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for EMAC0 SRAM. + * | | |0 = EMAC0 SRAM BIST Disabled. + * | | |1 = EMAC0 SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |HSUSBDBIST|HSUSBD BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBD SRAM. + * | | |0 = HSUSBD SRAM BIST Disabled. + * | | |1 = HSUSBD SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |HSUSBHBIST|HSUSBH BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for HSUSBH SRAM. + * | | |0 = HSUSBH SRAM BIST Disabled. + * | | |1 = HSUSBH SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |SRBIST2 |System SRAM Bank2 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for system SRAM bank2. + * | | |0 = System SRAM bank2 BIST Disabled. + * | | |1 = System SRAM bank2 BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11] |KSBIST |Key Store SRAM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for Key Store SRAM. + * | | |0 = Key Store SRAM BIST Disabled. + * | | |1 = Key Store SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |CCAPBIST |CCAP SRAM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CCAP SRAM. + * | | |0 = CCAP SRAM BIST Disabled. + * | | |1 = CCAP SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |RSABIST |RSA SRAM BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for RSA SRAM. + * | | |0 = RSA SRAM BIST Disabled. + * | | |1 = RSA SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::SRAM_BISTSTS + * Offset: 0xD4 System SRAM BIST Test Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBISTEF0 |System SRAM Bank0 BIST Fail Flag (Read Only) + * | | |0 = System SRAM bank0 BIST test pass. + * | | |1 = System SRAM bank0 BIST test fail. + * |[1] |SRBISTEF1 |System System Bank1 SRAM BIST Fail Flag (Read Only) + * | | |0 = System SRAM bank1 BIST test pass. + * | | |1 = System SRAM bank1 BIST test fail. + * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag (Read Only) + * | | |0 = CACHE SRAM BIST test pass. + * | | |1 = CACHE SRAM BIST test fail. + * |[3] |CANBEF |CAN SRAM BIST Fail Flag (Read Only) + * | | |0 = CAN SRAM BIST test pass. + * | | |1 = CAN SRAM BIST test fail. + * | | |Note: Any of the CAN SRAM macros BIST fail, this flag is 1. + * |[4] |USBBEF |USB SRAM BIST Fail Flag (Read Only) + * | | |0 = USB SRAM BIST test pass. + * | | |1 = USB SRAM BIST test fail. + * |[5] |SPIMBEF |SPIM SRAM BIST Fail Flag (Read Only) + * | | |0 = SPIM SRAM BIST test pass. + * | | |1 = SPIM SRAM BIST test fail. + * |[6] |EMAC0BEF |EMAC0 SRAM BIST Fail Flag (Read Only) + * | | |0 = EMAC0 SRAM BIST test pass. + * | | |1 = EMAC0 SRAM BIST test fail. + * |[8] |HSUSBDBEF |HSUSBD SRAM BIST Fail Flag (Read Only) + * | | |0 = HSUSBD SRAM BIST test pass. + * | | |1 = HSUSBD SRAM BIST test fail. + * |[9] |HSUSBHBEF |HSUSBH BIST Fail Flag (Read Only) + * | | |0 = HSUSBH SRAM BIST test pass. + * | | |1 = HSUSBH SRAM BIST test fail. + * |[10] |SRBISTEF2 |System SRAM Bank2 BIST Fail Flag (Read Only) + * | | |0 = System SRAM bank2 BIST test pass. + * | | |1 = System SRAM bank2 BIST test fail. + * |[11] |KSBISTEF |Key Store SRAM BIST Fail Flag (Read Only) + * | | |0 = Key Store SRAM BIST test pass. + * | | |1 = Key Store SRAM BIST test fail. + * |[12] |CCAPBISTEF|CCAP BIST Fail Flag (Read Only) + * | | |0 = CCAP BIST test pass. + * | | |1 = CCAP BIST test fail. + * |[13] |RSABISTE |RSA SRAM BIST Fail Flag (Read Only) + * | | |0 = RSA SRAM BIST test pass. + * | | |1 = RSA SRAM BIST test fail. + * |[16] |SRBEND0 |System SRAM Bank0 BIST Test Finish (Read Only) + * | | |0 = System SRAM bank0 BIST active. + * | | |1 = System SRAM bank0 BIST finish. + * |[17] |SRBEND1 |System SRAM Bank1 BIST Test Finish (Read Only) + * | | |0 = System SRAM bank1 BIST is active. + * | | |1 = System SRAM bank1 BIST finish. + * |[18] |CRBEND |CACHE SRAM BIST Test Finish (Read Only) + * | | |0 = CACHE SRAM BIST is active. + * | | |1 = CACHE SRAM BIST test finish. + * |[19] |CANBEND |CAN SRAM BIST Test Finish (Read Only) + * | | |0 = CAN SRAM BIST is active. + * | | |1 = CAN SRAM BIST test finish. + * | | |Note: All of the CAN SRAM macros BIST finish, this flag is 1. + * |[20] |USBBEND |USB SRAM BIST Test Finish + * | | |0 = USB SRAM BIST is active. (Read Only) + * | | |1 = USB SRAM BIST test finish. + * |[21] |SPIMBEND |SPIM SRAM BIST Test Finish (Read Only) + * | | |0 = SPIM SRAM BIST is active. + * | | |1 = SPIM SRAM BIST test finish. + * |[22] |EMAC0BEND |EMAC0 SRAM BIST Test Finish (Read Only) + * | | |0 = EMAC0 SRAM BIST is active. + * | | |1 = EMAC0 SRAM BIST test finish. + * |[24] |HSUSBDBEND|HSUSBD BIST Test Finish (Read Only) + * | | |0 = HSUSBD SRAM BIST is active. + * | | |1 = HSUSBD SRAM BIST test finish. + * |[25] |HSUSBHBEND|HSUSBH BIST Test Finish (Read Only) + * | | |0 = HSUSBH SRAM BIST is active. + * | | |1 = HSUSBH SRAM BIST test finish. + * |[26] |SRBEND2 |System SRAM Bank2 BIST Test Finish (Read Only) + * | | |0 = System SRAM bank2 BIST is active. + * | | |1 = System SRAM bank2 BIST finish. + * |[27] |KSBEND |Key Store SRAM BIST Test Finish (Read Only) + * | | |0 = Key Store SRAM BIST is active. + * | | |1 = Key Store SRAM BIST test finish. + * |[28] |CCAPBEND |CCAP SRAM BIST Test Finish (Read Only) + * | | |0 = CCAP SRAM BIST is active. + * | | |1 = CCAP SRAM BIST test finish. + * |[29] |RSABEND |RSA SRAM BIST Test Finish (Read Only) + * | | |0 = RSA SRAM BIST is active. + * | | |1 = RSA SRAM BIST test finish. + * @var SYS_T::HIRCTCTL + * Offset: 0xE4 HIRC48M Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48M) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still does not lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[9] |BOUNDEN |Boundary Enable Bit + * | | |0 = Boundary function Disabled. + * | | |1 = Boundary function Enabled. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference clock is from LXT (32.768 kHz). + * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. + * | | |Note: HIRC trim reference clock is 20 kHz in test mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_HIRCTCTL[9]) is enabled. + * @var SYS_T::HIRCTIEN + * Offset: 0xE8 HIRC48M Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_HIRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_HIRCTISTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_HIRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_HIRCTISTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::HIRCTISTS + * Offset: 0xEC HIRC48M Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and does not trigger any interrupt. + * | | |Write 1 to clear this to 0. + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency does not lock at 48 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still does not be locked. + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_HIRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC48M) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary condition did not occur. + * | | |1 = Over boundary condition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::IRCTCTL + * Offset: 0xF0 HIRC Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still does not lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[9] |BOUNDEN |Boundary Enable Bit + * | | |0 = Boundary function Disabled. + * | | |1 = Boundary function Enabled. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference clock is from LXT (32.768 kHz). + * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. + * | | |Note: HIRC trim reference clock is 20 kHz in test mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_IRCTCTL[9]) is enabled. + * @var SYS_T::IRCTIEN + * Offset: 0xF4 HIRC Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::IRCTISTS + * Offset: 0xF8 HIRC Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and does not trigger any interrupt. + * | | |Write 1 to clear this to 0. + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency does not lock at 12 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still does not be locked. + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy. + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary condition did not occur. + * | | |1 = Over boundary condition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::REGLCTL + * Offset: 0x100 Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) + * | | |Some registers have write-protection function. + * | | |Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |REGLCTL[0] + * | | |Register Lock Control Disable Index (Read Only) + * | | |0 = Write-protection Enabled for writing protected registers. Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::PORDISAN + * Offset: 0x1EC Analog POR Disable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFFAN |Power-on Reset Enable Bit (Write Protect) + * | | |After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. + * | | |The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::CSERVER + * Offset: 0x1F4 Chip Series Version Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |VERSION |Chip Series Version (Read Only) + * | | |These bits indicate the series version of chip. + * | | |0x2 = M460HD. + * | | |0x3 = M460LD. + * | | |Others = Reserved. + * @var SYS_T::PLCTL + * Offset: 0x1F8 Power Level Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PLSEL |Power Level Select (Write Protect) + * | | |These bits indicate the status of power level. + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[21:16] |LVSSTEP |LDO Voltage Scaling Step (Write Protect) + * | | |The LVSSTEP value is LDO voltage rising step. + * | | |LDO voltage scaling step = (LVSSTEP + 1) * 10mV. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31:24] |LVSPRD |LDO Voltage Scaling Period (Write Protect) + * | | |The LVSPRD value is the period of each LDO voltage rising step. + * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PLSTS + * Offset: 0x1FC Power Level Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) + * | | |This bit is set by hardware when power level is changing. + * | | |After power level change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Core voltage change is completed. + * | | |1 = Core voltage change is ongoing. + * |[9:8] |PLSTATUS |Power Level Status (Read Only) + * | | |This bit indicates the status of power level. + * | | |00 = Power level is PL0. + * | | |01 = Power level is PL1. + * | | |Others = Reserved. + * @var SYS_T::AHBMCTL + * Offset: 0x400 AHB Bus Matrix Priority Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex-M4 Core Enable Bit (Write Protect) + * | | |Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix. + * | | |0 = Round-robin mode. + * | | |1 = Cortex-M4 CPU with highest bus priority when interrupt occurred. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::GPA_MFP0 + * Offset: 0x500 GPIOA Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PA0MFP |PA.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = SPIM_MOSI + * | | |03 = QSPI0_MOSI0 + * | | |04 = SPI0_MOSI + * | | |05 = SD1_DAT0 + * | | |06 = SC0_CLK + * | | |07 = UART0_RXD + * | | |08 = UART1_nRTS + * | | |09 = I2C2_SDA + * | | |10 = CCAP_DATA6 + * | | |12 = BPWM0_CH0 + * | | |13 = EPWM0_CH5 + * | | |14 = EQEI3_B + * | | |15 = DAC0_ST + * | | |17 = PSIO0_CH7 + * | | |20 = BMC19 + * |[12:8] |PA1MFP |PA.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = SPIM_MISO + * | | |03 = QSPI0_MISO0 + * | | |04 = SPI0_MISO + * | | |05 = SD1_DAT1 + * | | |06 = SC0_DAT + * | | |07 = UART0_TXD + * | | |08 = UART1_nCTS + * | | |09 = I2C2_SCL + * | | |10 = CCAP_DATA7 + * | | |12 = BPWM0_CH1 + * | | |13 = EPWM0_CH4 + * | | |14 = EQEI3_A + * | | |15 = DAC1_ST + * | | |17 = PSIO0_CH6 + * | | |20 = BMC18 + * |[20:16] |PA2MFP |PA.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = SPIM_CLK + * | | |03 = QSPI0_CLK + * | | |04 = SPI0_CLK + * | | |05 = SD1_DAT2 + * | | |06 = SC0_RST + * | | |07 = UART4_RXD + * | | |08 = UART1_RXD + * | | |09 = I2C1_SDA + * | | |10 = I2C0_SMBSUS + * | | |12 = BPWM0_CH2 + * | | |13 = EPWM0_CH3 + * | | |14 = EQEI3_INDEX + * | | |17 = PSIO0_CH5 + * | | |20 = BMC17 + * |[28:24] |PA3MFP |PA.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = SPIM_SS + * | | |03 = QSPI0_SS + * | | |04 = SPI0_SS + * | | |05 = SD1_DAT3 + * | | |06 = SC0_PWR + * | | |07 = UART4_TXD + * | | |08 = UART1_TXD + * | | |09 = I2C1_SCL + * | | |10 = I2C0_SMBAL + * | | |12 = BPWM0_CH3 + * | | |13 = EPWM0_CH2 + * | | |14 = EQEI0_B + * | | |15 = EPWM1_BRAKE1 + * | | |17 = PSIO0_CH4 + * | | |20 = BMC16 + * @var SYS_T::GPA_MFP1 + * Offset: 0x504 GPIOA Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PA4MFP |PA.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = SPIM_D3 + * | | |03 = QSPI0_MOSI1 + * | | |04 = SPI0_I2SMCLK + * | | |05 = SD1_CLK + * | | |06 = SC0_nCD + * | | |07 = UART0_nRTS + * | | |08 = UART5_RXD + * | | |09 = I2C0_SDA + * | | |10 = CAN0_RXD + * | | |11 = UART0_RXD + * | | |12 = BPWM0_CH4 + * | | |13 = EPWM0_CH1 + * | | |14 = EQEI0_A + * |[12:8] |PA5MFP |PA.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = SPIM_D2 + * | | |03 = QSPI0_MISO1 + * | | |04 = SPI1_I2SMCLK + * | | |05 = SD1_CMD + * | | |06 = SC2_nCD + * | | |07 = UART0_nCTS + * | | |08 = UART5_TXD + * | | |09 = I2C0_SCL + * | | |10 = CAN0_TXD + * | | |11 = UART0_TXD + * | | |12 = BPWM0_CH5 + * | | |13 = EPWM0_CH0 + * | | |14 = EQEI0_INDEX + * |[20:16] |PA6MFP |PA.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD6 + * | | |03 = EMAC0_RMII_RXERR + * | | |04 = SPI1_SS + * | | |05 = SD1_nCD + * | | |06 = SC2_CLK + * | | |07 = UART0_RXD + * | | |08 = I2C1_SDA + * | | |09 = QSPI1_MOSI1 + * | | |11 = EPWM1_CH5 + * | | |12 = BPWM1_CH3 + * | | |13 = ACMP1_WLAT + * | | |14 = TM3 + * | | |15 = INT0 + * | | |17 = SPI5_CLK + * | | |18 = KPI_COL0 + * | | |19 = SPI6_CLK + * | | |20 = BMC15 + * |[28:24] |PA7MFP |PA.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD7 + * | | |03 = EMAC0_RMII_CRSDV + * | | |04 = SPI1_CLK + * | | |06 = SC2_DAT + * | | |07 = UART0_TXD + * | | |08 = I2C1_SCL + * | | |09 = QSPI1_MISO1 + * | | |11 = EPWM1_CH4 + * | | |12 = BPWM1_CH2 + * | | |13 = ACMP0_WLAT + * | | |14 = TM2 + * | | |15 = INT1 + * | | |17 = SPI5_SS + * | | |18 = KPI_COL1 + * | | |19 = SPI6_SS + * | | |20 = BMC14 + * @var SYS_T::GPA_MFP2 + * Offset: 0x508 GPIOA Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PA8MFP |PA.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH4, EADC2_CH4 + * | | |02 = EBI_ALE + * | | |03 = SC2_CLK + * | | |04 = SPI2_MOSI + * | | |05 = SD1_DAT0 + * | | |06 = USCI0_CTL1 + * | | |07 = UART1_RXD + * | | |08 = UART7_RXD + * | | |09 = BPWM0_CH3 + * | | |10 = EQEI1_B + * | | |11 = ECAP0_IC2 + * | | |12 = I2S1_DO + * | | |13 = TM3_EXT + * | | |15 = INT4 + * | | |20 = BMC9 + * |[12:8] |PA9MFP |PA.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH5, EADC2_CH5 + * | | |02 = EBI_MCLK + * | | |03 = SC2_DAT + * | | |04 = SPI2_MISO + * | | |05 = SD1_DAT1 + * | | |06 = USCI0_DAT1 + * | | |07 = UART1_TXD + * | | |08 = UART7_TXD + * | | |09 = BPWM0_CH2 + * | | |10 = EQEI1_A + * | | |11 = ECAP0_IC1 + * | | |12 = I2S1_DI + * | | |13 = TM2_EXT + * | | |15 = SWDH_DAT (for M460HD) + * | | |20 = BMC8 + * |[20:16] |PA10MFP |PA.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH6, EADC2_CH6, ACMP1_P0 + * | | |02 = EBI_nWR + * | | |03 = SC2_RST + * | | |04 = SPI2_CLK + * | | |05 = SD1_DAT2 + * | | |06 = USCI0_DAT0 + * | | |07 = I2C2_SDA + * | | |08 = UART6_RXD + * | | |09 = BPWM0_CH1 + * | | |10 = EQEI1_INDEX + * | | |11 = ECAP0_IC0 + * | | |12 = I2S1_MCLK + * | | |13 = TM1_EXT + * | | |14 = DAC0_ST + * | | |15 = SWDH_CLK (for M460HD) + * | | |18 = KPI_ROW5 + * | | |20 = BMC7 + * |[28:24] |PA11MFP |PA.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH7, EADC2_CH7, ACMP0_P0 + * | | |02 = EBI_nRD + * | | |03 = SC2_PWR + * | | |04 = SPI2_SS + * | | |05 = SD1_DAT3 + * | | |06 = USCI0_CLK + * | | |07 = I2C2_SCL + * | | |08 = UART6_TXD + * | | |09 = BPWM0_CH0 + * | | |10 = EPWM0_SYNC_OUT + * | | |12 = I2S1_BCLK + * | | |13 = TM0_EXT + * | | |14 = DAC1_ST + * | | |18 = KPI_ROW4 + * | | |20 = BMC6 + * @var SYS_T::GPA_MFP3 + * Offset: 0x50C GPIOA Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PA12MFP |PA.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = I2S0_BCLK + * | | |03 = UART4_TXD + * | | |04 = I2C1_SCL + * | | |05 = SPI2_SS + * | | |06 = CAN0_TXD + * | | |07 = SC2_PWR + * | | |08 = SD1_nCD + * | | |09 = SPI0_SS (for M460LD) + * | | |10 = QSPI1_MISO0 + * | | |11 = BPWM1_CH2 + * | | |12 = EQEI1_INDEX + * | | |13 = ECAP3_IC0 + * | | |14 = USB_VBUS + * | | |17 = PSIO0_CH4 + * | | |19 = SPI10_SS + * | | |20 = BMC12 + * |[12:8] |PA13MFP |PA.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = I2S0_MCLK + * | | |03 = UART4_RXD + * | | |04 = I2C1_SDA + * | | |05 = SPI2_CLK + * | | |06 = CAN0_RXD + * | | |07 = SC2_RST + * | | |09 = SPI0_CLK (for M460LD) + * | | |10 = QSPI1_MOSI0 + * | | |11 = BPWM1_CH3 + * | | |12 = EQEI1_A + * | | |13 = ECAP3_IC1 + * | | |14 = USB_D- + * | | |17 = PSIO0_CH5 + * | | |19 = SPI10_CLK + * | | |20 = BMC13 + * |[20:16] |PA14MFP |PA.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = I2S0_DI + * | | |03 = UART0_TXD + * | | |04 = EBI_AD5 + * | | |05 = SPI2_MISO + * | | |06 = I2C2_SCL + * | | |07 = SC2_DAT + * | | |09 = SPI0_MISO (for M460LD) + * | | |11 = BPWM1_CH4 + * | | |12 = EQEI1_B + * | | |13 = ECAP3_IC2 + * | | |14 = USB_D+ + * | | |16 = I2C0_SCL (for M460LD) + * | | |17 = PSIO0_CH6 + * | | |19 = SPI10_MISO + * | | |20 = BMC14 + * |[28:24] |PA15MFP |PA.15 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = I2S0_DO + * | | |03 = UART0_RXD + * | | |04 = SPIM_MOSI + * | | |05 = SPI2_MOSI + * | | |06 = I2C2_SDA + * | | |07 = SC2_CLK + * | | |09 = SPI0_MOSI (for M460LD) + * | | |11 = BPWM1_CH5 + * | | |12 = EPWM0_SYNC_IN + * | | |13 = EQEI3_INDEX + * | | |14 = USB_OTG_ID + * | | |16 = I2C0_SDA (for M460LD) + * | | |17 = PSIO0_CH7 + * | | |19 = SPI10_MOSI + * | | |20 = BMC15 + * @var SYS_T::GPB_MFP0 + * Offset: 0x510 GPIOB Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PB0MFP |PB.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH0, EADC1_CH8, EADC2_CH8, ACMP3_N + * | | |02 = EBI_ADR9 + * | | |03 = SD0_CMD + * | | |04 = SPI2_I2SMCLK + * | | |06 = USCI0_CTL0 + * | | |07 = UART2_RXD + * | | |08 = SPI0_I2SMCLK + * | | |09 = I2C1_SDA + * | | |10 = I2S1_LRCK + * | | |11 = EPWM0_CH5 + * | | |12 = EPWM1_CH5 + * | | |13 = EPWM0_BRAKE1 + * | | |14 = ACMP3_O + * | | |15 = QSPI0_MOSI1 + * | | |18 = KPI_ROW3 + * | | |19 = SPI4_MOSI + * | | |20 = BMC5 + * |[12:8] |PB1MFP |PB.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH1, EADC1_CH9, EADC2_CH9, ACMP3_P0 + * | | |02 = EBI_ADR8 + * | | |03 = SD0_CLK + * | | |04 = EMAC_RMII_RXERR + * | | |05 = SPI1_I2SMCLK + * | | |06 = SPI3_I2SMCLK + * | | |07 = UART2_TXD + * | | |09 = I2C1_SCL + * | | |10 = I2S0_LRCK + * | | |11 = EPWM0_CH4 + * | | |12 = EPWM1_CH4 + * | | |13 = EPWM0_BRAKE0 + * | | |14 = ACMP2_O + * | | |15 = QSPI0_MISO1 + * | | |18 = KPI_ROW2 + * | | |19 = SPI4_MISO + * | | |20 = BMC4 + * |[20:16] |PB2MFP |PB.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH2, EADC1_CH10, ACMP0_P1 + * | | |02 = EBI_ADR3 + * | | |03 = SD0_DAT0 + * | | |04 = EMAC0_RMII_CRSDV + * | | |05 = SPI1_SS + * | | |06 = UART1_RXD + * | | |07 = UART5_nCTS + * | | |09 = SC0_PWR + * | | |10 = I2S0_DO + * | | |11 = EPWM0_CH3 + * | | |12 = I2C1_SDA + * | | |14 = TM3 + * | | |15 = INT3 + * | | |17 = PSIO0_CH7 + * | | |18 = KPI_ROW1 + * | | |19 = SPI4_CLK + * | | |20 = BMC3 + * |[28:24] |PB3MFP |PB.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH3, EADC1_CH11, ACMP0_N + * | | |02 = EBI_ADR2 + * | | |03 = SD0_DAT1 + * | | |04 = EMAC0_RMII_RXD1 + * | | |05 = SPI1_CLK + * | | |06 = UART1_TXD + * | | |07 = UART5_nRTS + * | | |09 = SC0_RST + * | | |10 = I2S0_DI + * | | |11 = EPWM0_CH2 + * | | |12 = I2C1_SCL + * | | |14 = TM2 + * | | |15 = INT2 + * | | |17 = PSIO0_CH6 + * | | |18 = KPI_ROW0 + * | | |19 = SPI4_SS + * | | |20 = BMC2 + * @var SYS_T::GPB_MFP1 + * Offset: 0x514 GPIOB Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PB4MFP |PB.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH4, ACMP1_P1 + * | | |02 = EBI_ADR1 + * | | |03 = SD0_DAT2 + * | | |04 = EMAC0_RMII_RXD0 + * | | |05 = SPI1_MOSI + * | | |06 = I2C0_SDA + * | | |07 = UART5_RXD + * | | |09 = SC0_DAT + * | | |10 = I2S0_MCLK + * | | |11 = EPWM0_CH1 + * | | |12 = UART2_RXD + * | | |14 = TM1 + * | | |15 = INT1 + * | | |17 = PSIO0_CH5 + * | | |18 = KPI_COL7 + * | | |20 = BMC1 + * |[12:8] |PB5MFP |PB.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH5, ACMP1_N + * | | |02 = EBI_ADR0 + * | | |03 = SD0_DAT3 + * | | |04 = EMAC0_RMII_REFCLK + * | | |05 = SPI1_MISO + * | | |06 = I2C0_SCL + * | | |07 = UART5_TXD + * | | |09 = SC0_CLK + * | | |10 = I2S0_BCLK + * | | |11 = EPWM0_CH0 + * | | |12 = UART2_TXD + * | | |14 = TM0 + * | | |15 = INT0 + * | | |17 = PSIO0_CH4 + * | | |18 = KPI_COL6 + * | | |20 = BMC0 + * |[20:16] |PB6MFP |PB.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH6, EADC2_CH14, ACMP2_N + * | | |02 = EBI_nWRH + * | | |03 = EMAC0_PPS + * | | |05 = CAN1_RXD + * | | |06 = UART1_RXD + * | | |07 = SD1_CLK + * | | |08 = EBI_nCS1 + * | | |10 = BPWM1_CH5 + * | | |11 = EPWM1_BRAKE1 + * | | |12 = EPWM1_CH5 + * | | |13 = INT4 + * | | |14 = USB_VBUS_EN + * | | |15 = ACMP1_O + * | | |16 = SPI3_MOSI (for M460LD) + * | | |18 = KPI_COL5 + * | | |19 = SPI1_SS + * | | |20 = BMC31 + * |[28:24] |PB7MFP |PB.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH7, EADC2_CH15, ACMP2_P0 + * | | |02 = EBI_nWRL + * | | |03 = EMAC0_RMII_TXEN + * | | |05 = CAN1_TXD + * | | |06 = UART1_TXD + * | | |07 = SD1_CMD + * | | |08 = EBI_nCS0 + * | | |10 = BPWM1_CH4 + * | | |11 = EPWM1_BRAKE0 + * | | |12 = EPWM1_CH4 + * | | |13 = INT5 + * | | |14 = USB_VBUS_ST + * | | |15 = ACMP0_O + * | | |16 = SPI3_MISO (for M460LD) + * | | |18 = KPI_COL4 + * | | |19 = SPI1_CLK (for M460LD) + * | | |20 = BMC30 + * @var SYS_T::GPB_MFP2 + * Offset: 0x518 GPIOB Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PB8MFP |PB.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH8, ACMP2_P1 + * | | |02 = EBI_ADR19 + * | | |03 = EMAC0_RMII_TXD1 + * | | |05 = UART0_RXD + * | | |06 = UART1_nRTS + * | | |07 = I2C1_SMBSUS + * | | |08 = UART7_RXD + * | | |09 = I2C0_SDA + * | | |10 = BPWM1_CH3 + * | | |11 = SPI3_MOSI + * | | |12 = CAN2_RXD + * | | |13 = INT6 + * | | |14 = EADC2_ST + * | | |20 = BMC23 + * |[12:8] |PB9MFP |PB.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH9, ACMP2_P2 + * | | |02 = EBI_ADR18 + * | | |03 = EMAC0_RMII_TXD0 + * | | |05 = UART0_TXD + * | | |06 = UART1_nCTS + * | | |07 = I2C1_SMBAL + * | | |08 = UART7_TXD + * | | |09 = I2C0_SCL + * | | |10 = BPWM1_CH2 + * | | |11 = SPI3_MISO + * | | |12 = CAN2_TXD + * | | |13 = INT7 + * | | |14 = CCAP_HSYNC + * | | |20 = BMC22 + * |[20:16] |PB10MFP |PB.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH10, ACMP2_P3 + * | | |02 = EBI_ADR17 + * | | |03 = EMAC0_RMII_MDIO + * | | |05 = UART0_nRTS + * | | |06 = UART4_RXD + * | | |07 = I2C1_SDA + * | | |08 = CAN0_RXD + * | | |10 = BPWM1_CH1 + * | | |11 = SPI3_SS + * | | |12 = CCAP_VSYNC + * | | |14 = HSUSB_VBUS_EN + * | | |20 = BMC21 + * |[28:24] |PB11MFP |PB.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH11 + * | | |02 = EBI_ADR16 + * | | |03 = EMAC0_RMII_MDC + * | | |05 = UART0_nCTS + * | | |06 = UART4_TXD + * | | |07 = I2C1_SCL + * | | |08 = CAN0_TXD + * | | |09 = SPI0_I2SMCLK + * | | |10 = BPWM1_CH0 + * | | |11 = SPI3_CLK + * | | |12 = CCAP_SFIELD + * | | |14 = HSUSB_VBUS_ST + * | | |20 = BMC20 + * @var SYS_T::GPB_MFP3 + * Offset: 0x51C GPIOB Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PB12MFP |PB.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH12, EADC1_CH12, DAC0_OUT, ACMP0_P2, ACMP1_P2 + * | | |02 = EBI_AD15 + * | | |03 = SC1_CLK + * | | |04 = SPI0_MOSI + * | | |05 = USCI0_CLK + * | | |06 = UART0_RXD + * | | |07 = UART3_nCTS + * | | |08 = I2C2_SDA + * | | |09 = SD0_nCD + * | | |10 = CCAP_SCLK + * | | |11 = EPWM1_CH3 + * | | |12 = ETMC_TRACE_DATA3 (for M460HD) + * | | |13 = TM3_EXT + * | | |14 = CAN3_RXD + * | | |16 = SPI3_SS (for M460LD) + * | | |17 = PSIO0_CH3 + * | | |18 = KPI_COL3 + * | | |20 = BMC29 + * |[12:8] |PB13MFP |PB.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH13, EADC1_CH13, DAC1_OUT, ACMP0_P3, ACMP1_P3 + * | | |02 = EBI_AD14 + * | | |03 = SC1_DAT + * | | |04 = SPI0_MISO + * | | |05 = USCI0_DAT0 + * | | |06 = UART0_TXD + * | | |07 = UART3_nRTS + * | | |08 = I2C2_SCL + * | | |10 = CCAP_PIXCLK + * | | |11 = EPWM1_CH2 + * | | |12 = ETMC_TRACE_DATA2 (for M460HD) + * | | |13 = TM2_EXT + * | | |14 = CAN3_TXD + * | | |16 = SPI3_CLK (for M460LD) + * | | |17 = PSIO0_CH2 + * | | |18 = KPI_COL2 + * | | |19 = SPI9_MISO + * | | |20 = BMC28 + * |[20:16] |PB14MFP |PB.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH14, EADC1_CH14 + * | | |02 = EBI_AD13 + * | | |03 = SC1_RST + * | | |04 = SPI0_CLK + * | | |05 = USCI0_DAT1 + * | | |06 = UART0_nRTS + * | | |07 = UART3_RXD + * | | |08 = I2C2_SMBSUS + * | | |09 = CCAP_DATA0 + * | | |11 = EPWM1_CH1 + * | | |12 = ETMC_TRACE_DATA1 (for M460HD) + * | | |13 = TM1_EXT + * | | |14 = CLKO + * | | |15 = USB_VBUS_ST + * | | |17 = PSIO0_CH1 + * | | |18 = KPI_COL1 + * | | |19 = SPI9_SS + * |[28:24] |PB15MFP |PB.15 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC0_CH15, EADC1_CH15 + * | | |02 = EBI_AD12 + * | | |03 = SC1_PWR + * | | |04 = SPI0_SS + * | | |05 = USCI0_CTL1 + * | | |06 = UART0_nCTS + * | | |07 = UART3_TXD + * | | |08 = I2C2_SMBAL + * | | |09 = CCAP_DATA1 + * | | |10 = EPWM0_BRAKE1 + * | | |11 = EPWM1_CH0 + * | | |12 = ETMC_TRACE_DATA0 (for M460HD) + * | | |13 = TM0_EXT + * | | |14 = USB_VBUS_EN + * | | |15 = HSUSB_VBUS_EN (for M460HD) + * | | |17 = PSIO0_CH0 + * | | |18 = KPI_COL0 + * | | |19 = SPI9_CLK + * | | |20 = BMC27 + * @var SYS_T::GPC_MFP0 + * Offset: 0x520 GPIOC Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PC0MFP |PC.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD0 + * | | |03 = SPIM_MOSI + * | | |04 = QSPI0_MOSI0 + * | | |05 = SC1_CLK + * | | |06 = I2S0_LRCK + * | | |07 = SPI1_SS + * | | |08 = UART2_RXD + * | | |09 = I2C0_SDA + * | | |10 = CAN2_RXD + * | | |12 = EPWM1_CH5 + * | | |13 = CCAP_DATA0 + * | | |14 = ACMP1_O + * | | |15 = EADC1_ST + * | | |16 = HBI_D2 + * | | |17 = QSPI1_CLK (for M460LD) + * | | |18 = KPI_ROW5 + * | | |19 = SPI7_MOSI + * | | |20 = BMC25 + * |[12:8] |PC1MFP |PC.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD1 + * | | |03 = SPIM_MISO + * | | |04 = QSPI0_MISO0 + * | | |05 = SC1_DAT + * | | |06 = I2S0_DO + * | | |07 = SPI1_CLK + * | | |08 = UART2_TXD + * | | |09 = I2C0_SCL + * | | |10 = CAN2_TXD + * | | |12 = EPWM1_CH4 + * | | |13 = CCAP_DATA1 + * | | |14 = ACMP0_O + * | | |15 = EADC0_ST + * | | |16 = HBI_RWDS + * | | |17 = QSPI1_SS (for M460LD) + * | | |18 = KPI_ROW4 + * | | |19 = SPI7_MISO + * | | |20 = BMC24 + * |[20:16] |PC2MFP |PC.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD2 + * | | |03 = SPIM_CLK + * | | |04 = QSPI0_CLK + * | | |05 = SC1_RST + * | | |06 = I2S0_DI + * | | |07 = SPI1_MOSI + * | | |08 = UART2_nCTS + * | | |09 = I2C0_SMBSUS + * | | |10 = CAN1_RXD + * | | |11 = UART3_RXD + * | | |12 = EPWM1_CH3 + * | | |13 = CCAP_DATA2 + * | | |14 = QSPI1_MOSI0 + * | | |15 = I2C3_SDA + * | | |16 = HBI_nRESET + * | | |17 = PSIO0_CH3 + * | | |18 = KPI_ROW3 + * | | |19 = SPI7_CLK + * | | |20 = BMC23 + * |[28:24] |PC3MFP |PC.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD3 + * | | |03 = SPIM_SS + * | | |04 = QSPI0_SS + * | | |05 = SC1_PWR + * | | |06 = I2S0_MCLK + * | | |07 = SPI1_MISO + * | | |08 = UART2_nRTS + * | | |09 = I2C0_SMBAL + * | | |10 = CAN1_TXD + * | | |11 = UART3_TXD + * | | |12 = EPWM1_CH2 + * | | |13 = CCAP_DATA3 + * | | |14 = QSPI1_MISO0 + * | | |15 = I2C3_SCL + * | | |16 = HBI_nCS + * | | |17 = PSIO0_CH2 + * | | |18 = KPI_ROW2 + * | | |19 = SPI7_SS + * | | |20 = BMC22 + * @var SYS_T::GPC_MFP1 + * Offset: 0x524 GPIOC Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PC4MFP |PC.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD4 + * | | |03 = SPIM_D3 + * | | |04 = QSPI0_MOSI1 + * | | |05 = SC1_nCD + * | | |06 = I2S0_BCLK + * | | |07 = SPI1_I2SMCLK + * | | |08 = UART2_RXD + * | | |09 = I2C1_SDA + * | | |10 = CAN0_RXD + * | | |11 = UART4_RXD + * | | |12 = EPWM1_CH1 + * | | |13 = CCAP_DATA4 + * | | |14 = QSPI1_CLK + * | | |15 = I2C3_SMBSUS + * | | |16 = HBI_CK + * | | |17 = PSIO0_CH1 + * | | |18 = KPI_ROW1 + * | | |20 = BMC21 + * |[12:8] |PC5MFP |PC.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD5 + * | | |03 = SPIM_D2 + * | | |04 = QSPI0_MISO1 + * | | |08 = UART2_TXD + * | | |09 = I2C1_SCL + * | | |10 = CAN0_TXD + * | | |11 = UART4_TXD + * | | |12 = EPWM1_CH0 + * | | |13 = CCAP_DATA5 + * | | |14 = QSPI1_SS + * | | |15 = I2C3_SMBAL + * | | |16 = HBI_nCK + * | | |17 = PSIO0_CH0 + * | | |18 = KPI_ROW0 + * | | |20 = BMC20 + * |[20:16] |PC6MFP |PC.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD8 + * | | |03 = EMAC0_RMII_RXD1 + * | | |04 = SPI1_MOSI + * | | |05 = UART4_RXD + * | | |06 = SC2_RST + * | | |07 = UART0_nRTS + * | | |08 = I2C1_SMBSUS + * | | |09 = UART6_RXD + * | | |10 = ACMP3_WLAT + * | | |11 = EPWM1_CH3 + * | | |12 = BPWM1_CH1 + * | | |13 = CAN3_RXD + * | | |14 = TM1 + * | | |15 = INT2 + * | | |18 = KPI_COL2 + * | | |19 = SPI6_MOSI + * | | |20 = BMC25 + * |[28:24] |PC7MFP |PC.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD9 + * | | |03 = EMAC0_RMII_RXD0 + * | | |04 = SPI1_MISO + * | | |05 = UART4_TXD + * | | |06 = SC2_PWR + * | | |07 = UART0_nCTS + * | | |08 = I2C1_SMBAL + * | | |09 = UART6_TXD + * | | |10 = ACMP2_WLAT + * | | |11 = EPWM1_CH2 + * | | |12 = BPWM1_CH0 + * | | |13 = CAN3_TXD + * | | |14 = TM0 + * | | |15 = INT3 + * | | |18 = KPI_COL3 + * | | |19 = SPI6_MISO + * | | |20 = BMC24 + * @var SYS_T::GPC_MFP2 + * Offset: 0x528 GPIOC Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PC8MFP |PC.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR16 + * | | |03 = EMAC0_RMII_REFCLK + * | | |04 = I2C0_SDA + * | | |05 = UART4_nCTS + * | | |08 = UART1_RXD + * | | |11 = EPWM1_CH1 + * | | |12 = BPWM1_CH4 + * | | |18 = KPI_COL4 + * |[12:8] |PC9MFP |PC.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC2_CH10, ACMP3_P1 + * | | |02 = EBI_ADR7 + * | | |05 = UART6_nCTS + * | | |06 = SPI3_SS + * | | |07 = UART3_RXD + * | | |09 = CAN1_RXD + * | | |10 = I2C4_SMBSUS + * | | |12 = EPWM1_CH3 + * | | |14 = EADC1_ST + * |[20:16] |PC10MFP |PC.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC2_CH11, ACMP3_P2 + * | | |02 = EBI_ADR6 + * | | |05 = UART6_nRTS + * | | |06 = SPI3_CLK + * | | |07 = UART3_TXD + * | | |09 = CAN1_TXD + * | | |10 = I2C4_SMBAL + * | | |11 = ECAP1_IC0 + * | | |12 = EPWM1_CH2 + * | | |14 = EADC1_ST + * |[28:24] |PC11MFP |PC.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC2_CH12, ACMP3_P3 + * | | |02 = EBI_ADR5 + * | | |03 = UART0_RXD + * | | |04 = I2C0_SDA + * | | |05 = UART6_RXD + * | | |06 = SPI3_MOSI + * | | |10 = I2C4_SDA + * | | |11 = ECAP1_IC1 + * | | |12 = EPWM1_CH1 + * | | |14 = ACMP1_O + * @var SYS_T::GPC_MFP3 + * Offset: 0x52C GPIOC Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PC12MFP |PC.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC2_CH13 + * | | |02 = EBI_ADR4 + * | | |03 = UART0_TXD + * | | |04 = I2C0_SCL + * | | |05 = UART6_TXD + * | | |06 = SPI3_MISO + * | | |09 = SC0_nCD + * | | |10 = I2C4_SCL + * | | |11 = ECAP1_IC2 + * | | |12 = EPWM1_CH0 + * | | |14 = ACMP0_O + * |[12:8] |PC13MFP |PC.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH3, EADC2_CH3 + * | | |02 = EBI_ADR10 + * | | |03 = SC2_nCD + * | | |04 = SPI2_I2SMCLK + * | | |05 = CAN1_TXD + * | | |06 = USCI0_CTL0 + * | | |07 = UART2_TXD + * | | |08 = UART8_nCTS + * | | |09 = BPWM0_CH4 + * | | |13 = CLKO + * | | |14 = EADC0_ST + * | | |19 = SPI9_SS + * |[20:16] |PC14MFP |PC.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD11 + * | | |03 = SC1_nCD + * | | |04 = SPI0_I2SMCLK + * | | |05 = USCI0_CTL0 + * | | |06 = QSPI0_CLK + * | | |10 = TRACE_SWO + * | | |11 = EPWM0_SYNC_IN + * | | |12 = ETMC_TRACE_CLK (for M460HD) + * | | |13 = TM1 + * | | |14 = USB_VBUS_ST + * | | |15 = HSUSB_VBUS_ST (for M460HD) + * | | |19 = SPI9_MOSI + * | | |20 = BMC26 + * |[28:24] |PC15MFP |PC.15 Multi-function Pin Selection + * @var SYS_T::GPD_MFP0 + * Offset: 0x530 GPIOD Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PD0MFP |PD.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD13 + * | | |03 = USCI0_CLK + * | | |04 = SPI0_MOSI + * | | |05 = UART3_RXD + * | | |06 = I2C2_SDA + * | | |07 = SC2_CLK + * | | |10 = I2S1_DO + * | | |12 = EQEI2_A + * | | |13 = ECAP2_IC1 + * | | |14 = TM2 + * |[12:8] |PD1MFP |PD.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD12 + * | | |03 = USCI0_DAT0 + * | | |04 = SPI0_MISO + * | | |05 = UART3_TXD + * | | |06 = I2C2_SCL + * | | |07 = SC2_DAT + * | | |10 = I2S1_DI + * | | |12 = EQEI2_INDEX + * | | |13 = ECAP2_IC0 + * |[20:16] |PD2MFP |PD.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD11 + * | | |03 = USCI0_DAT1 + * | | |04 = SPI0_CLK + * | | |05 = UART3_nCTS + * | | |07 = SC2_RST + * | | |09 = UART0_RXD + * | | |10 = I2S1_MCLK + * | | |13 = EQEI3_B + * |[28:24] |PD3MFP |PD.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD10 + * | | |03 = USCI0_CTL1 + * | | |04 = SPI0_SS + * | | |05 = UART3_nRTS + * | | |07 = SC2_PWR + * | | |08 = SC1_nCD + * | | |09 = UART0_TXD + * | | |10 = I2S1_BCLK + * | | |13 = EQEI3_A + * @var SYS_T::GPD_MFP1 + * Offset: 0x534 GPIOD Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PD4MFP |PD.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = USCI0_CTL0 + * | | |04 = I2C1_SDA + * | | |05 = SPI1_SS + * | | |08 = SC1_CLK + * | | |14 = USB_VBUS_ST + * | | |17 = PSIO0_CH7 + * |[12:8] |PD5MFP |PD.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |04 = I2C1_SCL + * | | |05 = SPI1_CLK + * | | |08 = SC1_DAT + * | | |14 = ACMP1_O + * | | |15 = EADC1_ST + * | | |16 = HBI_nRESET + * | | |17 = PSIO0_CH6 + * |[20:16] |PD6MFP |PD.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD5 + * | | |03 = UART1_RXD + * | | |04 = I2C0_SDA + * | | |05 = SPI1_MOSI + * | | |06 = QSPI1_MOSI0 + * | | |08 = SC1_RST + * | | |14 = ACMP0_O + * | | |15 = EADC0_ST + * | | |16 = HBI_D0 + * | | |17 = PSIO0_CH5 + * |[28:24] |PD7MFP |PD.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD4 + * | | |03 = UART1_TXD + * | | |04 = I2C0_SCL + * | | |05 = SPI1_MISO + * | | |06 = QSPI1_MISO0 + * | | |07 = CCAP_HSYNC + * | | |08 = SC1_PWR + * | | |16 = HBI_D1 + * | | |17 = PSIO0_CH4 + * @var SYS_T::GPD_MFP2 + * Offset: 0x538 GPIOD Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PD8MFP |PD.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD6 + * | | |03 = I2C2_SDA + * | | |04 = UART2_nRTS + * | | |05 = UART7_RXD + * | | |06 = CAN2_RXD + * | | |17 = PSIO0_CH3 + * |[12:8] |PD9MFP |PD.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD7 + * | | |03 = I2C2_SCL + * | | |04 = UART2_nCTS + * | | |05 = UART7_TXD + * | | |06 = CAN2_TXD + * | | |17 = PSIO0_CH2 + * |[20:16] |PD10MFP |PD.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH0, EADC2_CH0 + * | | |02 = EBI_nCS2 + * | | |03 = UART1_RXD + * | | |04 = CAN0_RXD + * | | |08 = UART8_RXD + * | | |10 = EQEI0_B + * | | |11 = ECAP3_IC2 + * | | |15 = INT7 + * | | |19 = SPI9_MOSI + * |[28:24] |PD11MFP |PD.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH1, EADC2_CH1 + * | | |02 = EBI_nCS1 + * | | |03 = UART1_TXD + * | | |04 = CAN0_TXD + * | | |08 = UART8_TXD + * | | |10 = EQEI0_A + * | | |11 = ECAP3_IC1 + * | | |15 = INT6 + * | | |19 = SPI9_MISO + * @var SYS_T::GPD_MFP3 + * Offset: 0x53C GPIOD Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PD12MFP |PD.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |01 = EADC1_CH2, EADC2_CH2 + * | | |02 = EBI_nCS0 + * | | |05 = CAN1_RXD + * | | |07 = UART2_RXD + * | | |08 = UART8_nRTS + * | | |09 = BPWM0_CH5 + * | | |10 = EQEI0_INDEX + * | | |11 = ECAP3_IC0 + * | | |13 = CLKO + * | | |14 = EADC0_ST + * | | |15 = INT5 + * | | |19 = SPI9_CLK + * |[12:8] |PD13MFP |PD.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD10 + * | | |03 = SD0_nCD + * | | |04 = SPI0_I2SMCLK + * | | |05 = SPI1_I2SMCLK + * | | |06 = QSPI1_MOSI0 + * | | |07 = SC2_nCD + * | | |08 = SD1_CLK + * | | |09 = UART6_RXD + * | | |10 = I2S1_LRCK + * | | |11 = BPWM0_CH0 + * | | |12 = EQEI2_B + * | | |13 = ECAP2_IC2 + * | | |14 = CLKO + * | | |15 = EADC0_ST + * | | |19 = QSPI1_MOSI1 (for M460LD) + * |[20:16] |PD14MFP |PD.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nCS0 + * | | |03 = SPI3_I2SMCLK + * | | |04 = SC1_nCD + * | | |05 = SPI0_I2SMCLK + * | | |10 = I2S1_BCLK + * | | |11 = EPWM0_CH4 + * |[28:24] |PD15MFP |PD.15 Multi-function Pin Selection + * @var SYS_T::GPE_MFP0 + * Offset: 0x540 GPIOE Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PE0MFP |PE.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD11 + * | | |03 = QSPI0_MOSI0 + * | | |04 = SC2_CLK + * | | |05 = I2S0_MCLK + * | | |06 = SPI1_MOSI + * | | |07 = UART3_RXD + * | | |08 = I2C1_SDA + * | | |09 = UART4_nRTS + * | | |10 = UART8_RXD + * |[12:8] |PE1MFP |PE.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD10 + * | | |03 = QSPI0_MISO0 + * | | |04 = SC2_DAT + * | | |05 = I2S0_BCLK + * | | |06 = SPI1_MISO + * | | |07 = UART3_TXD + * | | |08 = I2C1_SCL + * | | |09 = UART4_nCTS + * | | |10 = UART8_TXD + * |[20:16] |PE2MFP |PE.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ALE + * | | |03 = SD0_DAT0 + * | | |04 = SPIM_MOSI + * | | |05 = SPI3_MOSI + * | | |06 = SC0_CLK + * | | |07 = USCI0_CLK + * | | |08 = UART6_nCTS + * | | |09 = UART7_RXD + * | | |10 = UART8_nRTS + * | | |11 = EQEI0_B + * | | |12 = EPWM0_CH5 + * | | |13 = BPWM0_CH0 + * |[28:24] |PE3MFP |PE.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_MCLK + * | | |03 = SD0_DAT1 + * | | |04 = SPIM_MISO + * | | |05 = SPI3_MISO + * | | |06 = SC0_DAT + * | | |07 = USCI0_DAT0 + * | | |08 = UART6_nRTS + * | | |09 = UART7_TXD + * | | |10 = UART8_nCTS + * | | |11 = EQEI0_A + * | | |12 = EPWM0_CH4 + * | | |13 = BPWM0_CH1 + * @var SYS_T::GPE_MFP1 + * Offset: 0x544 GPIOE Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PE4MFP |PE.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nWR + * | | |03 = SD0_DAT2 + * | | |04 = SPIM_CLK + * | | |05 = SPI3_CLK + * | | |06 = SC0_RST + * | | |07 = USCI0_DAT1 + * | | |08 = UART6_RXD + * | | |09 = UART7_nCTS + * | | |10 = UART9_RXD + * | | |11 = EQEI0_INDEX + * | | |12 = EPWM0_CH3 + * | | |13 = BPWM0_CH2 + * | | |17 = PSIO0_CH3 + * |[12:8] |PE5MFP |PE.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nRD + * | | |03 = SD0_DAT3 + * | | |04 = SPIM_SS + * | | |05 = SPI3_SS + * | | |06 = SC0_PWR + * | | |07 = USCI0_CTL1 + * | | |08 = UART6_TXD + * | | |09 = UART7_nRTS + * | | |10 = UART9_TXD + * | | |11 = EQEI1_B + * | | |12 = EPWM0_CH2 + * | | |13 = BPWM0_CH3 + * | | |17 = PSIO0_CH2 + * |[20:16] |PE6MFP |PE.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SD0_CLK + * | | |04 = SPIM_D3 + * | | |05 = SPI3_I2SMCLK + * | | |06 = SC0_nCD + * | | |07 = USCI0_CTL0 + * | | |08 = UART5_RXD + * | | |09 = CAN1_RXD + * | | |10 = UART9_nRTS + * | | |11 = EQEI1_A + * | | |12 = EPWM0_CH1 + * | | |13 = BPWM0_CH4 + * | | |14 = ACMP3_O + * | | |17 = PSIO0_CH1 + * |[28:24] |PE7MFP |PE.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SD0_CMD + * | | |04 = SPIM_D2 + * | | |08 = UART5_TXD + * | | |09 = CAN1_TXD + * | | |10 = UART9_nCTS + * | | |11 = EQEI1_INDEX + * | | |12 = EPWM0_CH0 + * | | |13 = BPWM0_CH5 + * | | |14 = ACMP2_O + * | | |17 = PSIO0_CH0 + * @var SYS_T::GPE_MFP2 + * Offset: 0x548 GPIOE Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PE8MFP |PE.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR10 + * | | |03 = EMAC0_RMII_MDC + * | | |04 = I2S0_BCLK + * | | |05 = SPI2_CLK + * | | |07 = UART2_TXD + * | | |10 = EPWM0_CH0 + * | | |11 = EPWM0_BRAKE0 + * | | |12 = ECAP0_IC0 + * | | |13 = EQEI2_INDEX + * | | |14 = TRACE_DATA3 + * | | |15 = ECAP3_IC0 + * |[12:8] |PE9MFP |PE.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR11 + * | | |03 = EMAC0_RMII_MDIO + * | | |04 = I2S0_MCLK + * | | |05 = SPI2_MISO + * | | |07 = UART2_RXD + * | | |10 = EPWM0_CH1 + * | | |11 = EPWM0_BRAKE1 + * | | |12 = ECAP0_IC1 + * | | |13 = EQEI2_A + * | | |14 = TRACE_DATA2 + * | | |15 = ECAP3_IC1 + * |[20:16] |PE10MFP |PE.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR12 + * | | |03 = EMAC_RMII_TXD0 + * | | |04 = I2S0_DI + * | | |05 = SPI2_MOSI + * | | |07 = UART3_TXD + * | | |10 = EPWM0_CH2 + * | | |11 = EPWM1_BRAKE0 + * | | |12 = ECAP0_IC2 + * | | |13 = EQEI2_B + * | | |14 = TRACE_DATA1 + * | | |15 = ECAP3_IC2 + * |[28:24] |PE11MFP |PE.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR13 + * | | |03 = EMAC0_RMII_TXD1 + * | | |04 = I2S0_DO + * | | |05 = SPI2_SS + * | | |07 = UART3_RXD + * | | |08 = UART1_nCTS + * | | |10 = EPWM0_CH3 + * | | |11 = EPWM1_BRAKE1 + * | | |13 = ECAP1_IC2 + * | | |14 = TRACE_DATA0 + * | | |18 = KPI_COL7 + * @var SYS_T::GPE_MFP3 + * Offset: 0x54C GPIOE Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PE12MFP |PE.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR14 + * | | |03 = EMAC0_RMII_TXEN + * | | |04 = I2S0_LRCK + * | | |05 = SPI2_I2SMCLK + * | | |08 = UART1_nRTS + * | | |10 = EPWM0_CH4 + * | | |13 = ECAP1_IC1 + * | | |14 = TRACE_CLK + * | | |18 = KPI_COL6 + * |[12:8] |PE13MFP |PE.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR15 + * | | |03 = EMAC0_PPS + * | | |04 = I2C0_SCL + * | | |05 = UART4_nRTS + * | | |08 = UART1_TXD + * | | |10 = EPWM0_CH5 + * | | |11 = EPWM1_CH0 + * | | |12 = BPWM1_CH5 + * | | |13 = ECAP1_IC0 + * | | |14 = TRACE_SWO + * | | |18 = KPI_COL5 + * |[20:16] |PE14MFP |PE.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD8 + * | | |03 = UART2_TXD + * | | |04 = CAN0_TXD + * | | |05 = SD1_nCD + * | | |06 = UART6_TXD + * | | |17 = PSIO0_CH0 + * |[28:24] |PE15MFP |PE.15 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD9 + * | | |03 = UART2_RXD + * | | |04 = CAN0_RXD + * | | |06 = UART6_RXD + * | | |17 = PSIO0_CH1 + * @var SYS_T::GPF_MFP0 + * Offset: 0x550 GPIOF Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PF0MFP |PF.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = UART1_TXD + * | | |03 = I2C1_SCL + * | | |04 = UART0_TXD + * | | |05 = SC1_DAT + * | | |06 = I2S0_DO + * | | |08 = UART2_TXD + * | | |09 = I2C0_SCL + * | | |10 = CAN2_TXD + * | | |11 = EPWM1_CH4 + * | | |12 = BPWM1_CH0 + * | | |13 = ACMP0_O + * | | |14 = ICE_DAT + * | | |15 = EADC0_ST + * | | |19 = QSPI1_MISO0 (for M460LD) + * |[12:8] |PF1MFP |PF.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = UART1_RXD + * | | |03 = I2C1_SDA + * | | |04 = UART0_RXD + * | | |05 = SC1_CLK + * | | |06 = I2S0_LRCK + * | | |08 = UART2_RXD + * | | |09 = I2C0_SDA + * | | |10 = CAN2_RXD + * | | |11 = EPWM1_CH5 + * | | |12 = BPWM1_CH1 + * | | |13 = ACMP1_O + * | | |14 = ICE_CLK + * | | |15 = EADC1_ST + * | | |19 = QSPI1_MOSI0 (for M460LD) + * |[20:16] |PF2MFP |PF.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nCS1 + * | | |03 = UART0_RXD + * | | |04 = I2C0_SDA + * | | |05 = QSPI0_CLK + * | | |07 = UART9_RXD + * | | |10 = XT1_OUT + * | | |11 = BPWM1_CH1 + * | | |12 = I2C4_SMBSUS + * | | |13 = ACMP3_O + * | | |20 = BMC13 + * |[28:24] |PF3MFP |PF.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nCS0 + * | | |03 = UART0_TXD + * | | |04 = I2C0_SCL + * | | |07 = UART9_TXD + * | | |10 = XT1_IN + * | | |11 = BPWM1_CH0 + * | | |12 = I2C4_SMBAL + * | | |13 = ACMP2_O + * | | |15 = EADC2_ST + * | | |20 = BMC12 + * @var SYS_T::GPF_MFP1 + * Offset: 0x554 GPIOF Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PF4MFP |PF.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = UART2_TXD + * | | |03 = EBI_AD0 + * | | |04 = UART2_nRTS + * | | |07 = EPWM0_CH1 + * | | |08 = BPWM0_CH5 + * | | |10 = X32_OUT + * | | |11 = EADC1_ST + * | | |12 = I2C4_SDA + * | | |13 = EQEI2_B + * | | |19 = SPI5_MISO + * | | |20 = BMC11 + * |[12:8] |PF5MFP |PF.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = UART2_RXD + * | | |03 = EBI_AD1 + * | | |04 = UART2_nCTS + * | | |07 = EPWM0_CH0 + * | | |08 = BPWM0_CH4 + * | | |09 = EPWM0_SYNC_OUT + * | | |10 = X32_IN + * | | |11 = EADC0_ST + * | | |12 = I2C4_SCL + * | | |13 = EQEI2_A + * | | |19 = SPI5_MOSI + * | | |20 = BMC10 + * |[20:16] |PF6MFP |PF.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR19 + * | | |03 = SC0_CLK + * | | |04 = I2S0_LRCK + * | | |05 = SPI0_MOSI + * | | |06 = UART4_RXD + * | | |07 = EBI_nCS0 + * | | |08 = CAN2_RXD + * | | |09 = SPI3_I2SMCLK + * | | |10 = TAMPER0 + * | | |13 = EQEI2_INDEX + * | | |14 = TRACE_SWO + * | | |19 = SPI5_CLK + * |[28:24] |PF7MFP |PF.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR18 + * | | |03 = SC0_DAT + * | | |04 = I2S0_DO + * | | |05 = SPI0_MISO + * | | |06 = UART4_TXD + * | | |07 = CCAP_DATA0 + * | | |08 = CAN2_TXD + * | | |10 = TAMPER1 + * | | |19 = SPI5_SS + + * @var SYS_T::GPF_MFP2 + * Offset: 0x558 GPIOF Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PF8MFP |PF.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR17 + * | | |03 = SC0_RST + * | | |04 = I2S0_DI + * | | |05 = SPI0_CLK + * | | |06 = UART5_nCTS + * | | |07 = CCAP_DATA1 + * | | |08 = CAN1_RXD + * | | |10 = TAMPER2 + * | | |11 = UART9_RXD + * |[12:8] |PF9MFP |PF.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR16 + * | | |03 = SC0_PWR + * | | |04 = I2S0_MCLK + * | | |05 = SPI0_SS + * | | |06 = UART5_nRTS + * | | |07 = CCAP_DATA2 + * | | |08 = CAN1_TXD + * | | |10 = TAMPER3 + * | | |11 = UART9_TXD + * |[20:16] |PF10MFP |PF.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR15 + * | | |03 = SC0_nCD + * | | |04 = I2S0_BCLK + * | | |05 = SPI0_I2SMCLK + * | | |06 = UART5_RXD + * | | |07 = CCAP_DATA3 + * | | |08 = CAN3_RXD + * | | |10 = TAMPER4 + * | | |11 = UART9_nRTS + * |[28:24] |PF11MFP |PF.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR14 + * | | |03 = SPI2_MOSI + * | | |06 = UART5_TXD + * | | |07 = CCAP_DATA4 + * | | |08 = CAN3_TXD + * | | |10 = TAMPER5 + * | | |11 = UART9_nCTS + * | | |13 = TM3 + * @var SYS_T::GPF_MFP3 + * Offset: 0x55C GPIOF Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PF12MFP |PF.12 Multi-function Pin Selection + * |[12:8] |PF13MFP |PF.13 Multi-function Pin Selection + * |[20:16] |PF14MFP |PF.14 Multi-function Pin Selection + * |[28:24] |PF15MFP |PF.15 Multi-function Pin Selection + * @var SYS_T::GPG_MFP0 + * Offset: 0x560 GPIOG Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PG0MFP |PG.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR8 + * | | |04 = I2C0_SCL + * | | |05 = I2C1_SMBAL + * | | |06 = UART2_RXD + * | | |07 = CAN1_TXD + * | | |08 = UART1_TXD + * | | |09 = I2C3_SCL + * |[12:8] |PG1MFP |PG.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR9 + * | | |03 = SPI2_I2SMCLK + * | | |04 = I2C0_SDA + * | | |05 = I2C1_SMBSUS + * | | |06 = UART2_TXD + * | | |07 = CAN1_RXD + * | | |08 = UART1_RXD + * | | |09 = I2C3_SDA + * |[20:16] |PG2MFP |PG.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR11 + * | | |03 = SPI2_SS + * | | |04 = I2C0_SMBAL + * | | |05 = I2C1_SCL + * | | |07 = CCAP_DATA7 + * | | |09 = I2C3_SMBAL + * | | |13 = TM0 + * |[28:24] |PG3MFP |PG.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR12 + * | | |03 = SPI2_CLK + * | | |04 = I2C0_SMBSUS + * | | |05 = I2C1_SDA + * | | |07 = CCAP_DATA6 + * | | |09 = I2C3_SMBSUS + * | | |13 = TM1 + * @var SYS_T::GPG_MFP1 + * Offset: 0x564 GPIOG Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PG4MFP |PG.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR13 + * | | |03 = SPI2_MISO + * | | |07 = CCAP_DATA5 + * | | |13 = TM2 + * |[12:8] |PG5MFP |PG.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nCS1 + * | | |03 = SPI3_SS + * | | |04 = SC1_PWR + * | | |08 = I2C3_SMBAL + * | | |10 = I2S1_MCLK + * | | |11 = EPWM0_CH3 + * |[20:16] |PG6MFP |PG.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nCS2 + * | | |03 = SPI3_CLK + * | | |04 = SC1_RST + * | | |08 = I2C3_SMBSUS + * | | |10 = I2S1_DI + * | | |11 = EPWM0_CH2 + * |[28:24] |PG7MFP |PG.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nWRL + * | | |03 = SPI3_MISO + * | | |04 = SC1_DAT + * | | |08 = I2C3_SCL + * | | |10 = I2S1_DO + * | | |11 = EPWM0_CH1 + * @var SYS_T::GPG_MFP2 + * Offset: 0x568 GPIOG Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PG8MFP |PG.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nWRH + * | | |03 = SPI3_MOSI + * | | |04 = SC1_CLK + * | | |08 = I2C3_SDA + * | | |10 = I2S1_LRCK + * | | |11 = EPWM0_CH0 + * |[12:8] |PG9MFP |PG.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD0 + * | | |03 = SD1_DAT3 + * | | |04 = SPIM_D2 + * | | |05 = QSPI1_MISO1 + * | | |07 = CCAP_PIXCLK + * | | |08 = I2C4_SCL + * | | |09 = ECAP2_IC0 + * | | |12 = BPWM0_CH5 + * | | |16 = HBI_D4 + * | | |19 = SPI8_SS + * | | |20 = BMC16 + * |[20:16] |PG10MFP |PG.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD1 + * | | |03 = SD1_DAT2 + * | | |04 = SPIM_D3 + * | | |05 = QSPI1_MOSI1 + * | | |07 = CCAP_SCLK + * | | |08 = I2C4_SDA + * | | |09 = ECAP2_IC1 + * | | |12 = BPWM0_CH4 + * | | |16 = HBI_D3 + * | | |19 = SPI8_CLK + * | | |20 = BMC17 + * |[28:24] |PG11MFP |PG.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD2 + * | | |03 = SD1_DAT1 + * | | |04 = SPIM_SS + * | | |05 = QSPI1_SS + * | | |06 = UART7_TXD + * | | |07 = CCAP_SFIELD + * | | |08 = I2C4_SMBAL + * | | |09 = ECAP2_IC2 + * | | |12 = BPWM0_CH3 + * | | |16 = HBI_D0 + * | | |19 = SPI8_MOSI + * | | |20 = BMC18 + * @var SYS_T::GPG_MFP3 + * Offset: 0x56C GPIOG Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PG12MFP |PG.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD3 + * | | |03 = SD1_DAT0 + * | | |04 = SPIM_CLK + * | | |05 = QSPI1_CLK + * | | |06 = UART7_RXD + * | | |07 = CCAP_VSYNC + * | | |08 = I2C4_SMBSUS + * | | |12 = BPWM0_CH2 + * | | |16 = HBI_D1 + * | | |19 = SPI8_MISO + * | | |20 = BMC19 + * |[12:8] |PG13MFP |PG.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD4 + * | | |03 = SD1_CMD + * | | |04 = SPIM_MISO + * | | |05 = QSPI1_MISO0 + * | | |06 = UART6_TXD + * | | |07 = CCAP_HSYNC + * | | |12 = BPWM0_CH1 + * | | |16 = HBI_D5 + * |[20:16] |PG14MFP |PG.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD5 + * | | |03 = SD1_CLK + * | | |04 = SPIM_MOSI + * | | |05 = QSPI1_MOSI0 + * | | |06 = UART6_RXD + * | | |12 = BPWM0_CH0 + * | | |16 = HBI_D6 + * |[28:24] |PG15MFP |PG.15 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SD1_nCD + * | | |14 = CLKO + * | | |15 = EADC0_ST + * | | |16 = HBI_D7 + * | | |19 = QSPI1_MISO1 (for M460LD) + * @var SYS_T::GPH_MFP0 + * Offset: 0x570 GPIOH Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PH0MFP |PH.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR7 + * | | |04 = UART5_TXD + * | | |13 = TM0_EXT + * |[12:8] |PH1MFP |PH.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR6 + * | | |04 = UART5_RXD + * | | |13 = TM1_EXT + * |[20:16] |PH2MFP |PH.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR5 + * | | |04 = UART5_nRTS + * | | |05 = UART4_TXD + * | | |06 = I2C0_SCL + * | | |13 = TM2_EXT + * |[28:24] |PH3MFP |PH.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR4 + * | | |03 = SPI1_I2SMCLK + * | | |04 = UART5_nCTS + * | | |05 = UART4_RXD + * | | |06 = I2C0_SDA + * | | |13 = TM3_EXT + * @var SYS_T::GPH_MFP1 + * Offset: 0x574 GPIOH Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PH4MFP |PH.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR3 + * | | |03 = SPI1_MISO + * | | |04 = UART7_nRTS + * | | |05 = UART6_TXD + * |[12:8] |PH5MFP |PH.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR2 + * | | |03 = SPI1_MOSI + * | | |04 = UART7_nCTS + * | | |05 = UART6_RXD + * |[20:16] |PH6MFP |PH.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR1 + * | | |03 = SPI1_CLK + * | | |04 = UART7_TXD + * | | |07 = UART9_nCTS + * |[28:24] |PH7MFP |PH.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ADR0 + * | | |03 = SPI1_SS + * | | |04 = UART7_RXD + * | | |07 = UART9_nRTS + * @var SYS_T::GPH_MFP2 + * Offset: 0x578 GPIOH Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PH8MFP |PH.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD12 + * | | |03 = QSPI0_CLK + * | | |04 = SC2_PWR + * | | |05 = I2S0_DI + * | | |06 = SPI1_CLK + * | | |07 = UART3_nRTS + * | | |08 = I2C1_SMBAL + * | | |09 = I2C2_SCL + * | | |10 = UART1_TXD + * | | |13 = UART9_nCTS + * |[12:8] |PH9MFP |PH.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD13 + * | | |03 = QSPI0_SS + * | | |04 = SC2_RST + * | | |05 = I2S0_DO + * | | |06 = SPI1_SS + * | | |07 = UART3_nCTS + * | | |08 = I2C1_SMBSUS + * | | |09 = I2C2_SDA + * | | |10 = UART1_RXD + * | | |13 = UART9_nRTS + * |[20:16] |PH10MFP |PH.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD14 + * | | |03 = QSPI0_MISO1 + * | | |04 = SC2_nCD + * | | |05 = I2S0_LRCK + * | | |06 = SPI1_I2SMCLK + * | | |07 = UART4_TXD + * | | |08 = UART0_TXD + * | | |13 = UART9_TXD + * |[28:24] |PH11MFP |PH.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD15 + * | | |03 = QSPI0_MOSI1 + * | | |07 = UART4_RXD + * | | |08 = UART0_RXD + * | | |11 = EPWM0_CH5 + * | | |13 = UART9_RXD + * @var SYS_T::GPH_MFP3 + * Offset: 0x57C GPIOH Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PH12MFP |PH.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD0 + * | | |03 = UART9_TXD + * | | |06 = QSPI1_MISO1 + * | | |07 = CCAP_PIXCLK + * | | |10 = CAN3_TXD + * | | |16 = HBI_nCK + * |[12:8] |PH13MFP |PH.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD1 + * | | |03 = UART9_RXD + * | | |06 = QSPI1_MOSI1 + * | | |07 = CCAP_SCLK + * | | |10 = CAN3_RXD + * | | |16 = HBI_nCS + * |[20:16] |PH14MFP |PH.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD2 + * | | |06 = QSPI1_SS + * | | |07 = CCAP_SFIELD + * | | |16 = HBI_D3 + * |[28:24] |PH15MFP |PH.15 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD3 + * | | |06 = QSPI1_CLK + * | | |07 = CCAP_VSYNC + * | | |16 = HBI_D2 + * @var SYS_T::GPI_MFP0 + * Offset: 0x580 GPIOI Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PI0MFP |PI.0 Multi-function Pin Selection + * |[12:8] |PI1MFP |PI.1 Multi-function Pin Selection + * |[20:16] |PI2MFP |PI.2 Multi-function Pin Selection + * |[28:24] |PI3MFP |PI.3 Multi-function Pin Selection + * @var SYS_T::GPI_MFP1 + * Offset: 0x584 GPIOI Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PI4MFP |PI.4 Multi-function Pin Selection + * |[12:8] |PI5MFP |PI.5 Multi-function Pin Selection + * |[20:16] |PI6MFP |PI.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |05 = SC1_nCD + * | | |06 = I2S0_BCLK + * | | |07 = SPI1_I2SMCLK + * | | |08 = UART2_TXD + * | | |09 = I2C1_SCL + * | | |13 = CAN3_TXD + * | | |15 = USB_VBUS_ST + * |[28:24] |PI7MFP |PI.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |05 = SC1_PWR + * | | |06 = I2S0_MCLK + * | | |07 = SPI1_MISO + * | | |08 = UART2_RXD + * | | |09 = I2C1_SDA + * | | |13 = CAN3_RXD + * | | |15 = USB_VBUS_EN + * @var SYS_T::GPI_MFP2 + * Offset: 0x588 GPIOI Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PI8MFP |PI.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |05 = SC1_RST + * | | |06 = I2S0_DI + * | | |07 = SPI1_MOSI + * | | |08 = UART2_nRTS + * | | |09 = I2C0_SMBAL + * | | |13 = CAN2_TXD + * |[12:8] |PI9MFP |PI.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |05 = SC1_DAT + * | | |06 = I2S0_DO + * | | |07 = SPI1_CLK + * | | |08 = UART2_nCTS + * | | |09 = I2C0_SMBSUS + * | | |13 = CAN2_RXD + * |[20:16] |PI10MFP |PI.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |05 = SC1_CLK + * | | |06 = I2S0_LRCK + * | | |07 = SPI1_SS + * | | |08 = UART2_TXD + * | | |09 = I2C0_SCL + * | | |13 = CAN3_TXD + * |[28:24] |PI11MFP |PI.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |08 = UART2_RXD + * | | |09 = I2C0_SDA + * | | |13 = CAN3_RXD + * @var SYS_T::GPI_MFP3 + * Offset: 0x58C GPIOI Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PI12MFP |PI.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SPIM_SS + * | | |04 = QSPI0_MISO1 + * | | |10 = CAN0_TXD + * | | |11 = UART4_TXD + * | | |12 = EPWM1_CH0 + * | | |15 = I2C3_SMBAL + * |[12:8] |PI13MFP |PI.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SPIM_MISO + * | | |04 = QSPI0_MOSI1 + * | | |10 = CAN0_RXD + * | | |11 = UART4_RXD + * | | |12 = EPWM1_CH1 + * | | |15 = I2C3_SMBSUS + * |[20:16] |PI14MFP |PI.14 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SPIM_D2 + * | | |04 = QSPI0_SS + * | | |07 = UART8_nCTS + * | | |10 = CAN1_TXD + * | | |11 = UART3_TXD + * | | |12 = EPWM1_CH2 + * | | |15 = I2C3_SCL + * |[28:24] |PI15MFP |PI.15 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SPIM_D3 + * | | |04 = QSPI0_CLK + * | | |07 = UART8_nRTS + * | | |10 = CAN1_RXD + * | | |11 = UART3_RXD + * | | |12 = EPWM1_CH3 + * | | |15 = I2C3_SDA + * @var SYS_T::GPJ_MFP0 + * Offset: 0x590 GPIOJ Multiple Function Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PJ0MFP |PJ.0 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SPIM_CLK + * | | |04 = QSPI0_MISO0 + * | | |07 = UART8_TXD + * | | |10 = CAN2_TXD + * | | |12 = EPWM1_CH4 + * |[12:8] |PJ1MFP |PJ.1 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SPIM_MOSI + * | | |04 = QSPI0_MOSI0 + * | | |07 = UART8_RXD + * | | |10 = CAN2_RXD + * | | |12 = EPWM1_CH5 + * |[20:16] |PJ2MFP |PJ.2 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD5 + * | | |03 = UART8_nCTS + * | | |06 = QSPI1_SS + * | | |07 = CCAP_DATA5 + * | | |10 = CAN0_TXD + * | | |16 = HBI_RWDS + * |[28:24] |PJ3MFP |PJ.3 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD4 + * | | |03 = UART8_nRTS + * | | |06 = QSPI1_CLK + * | | |07 = CCAP_DATA4 + * | | |10 = CAN0_RXD + * | | |16 = HBI_D7 + * @var SYS_T::GPJ_MFP1 + * Offset: 0x594 GPIOJ Multiple Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PJ4MFP |PJ.4 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD3 + * | | |03 = UART8_TXD + * | | |06 = QSPI1_MISO0 + * | | |07 = CCAP_DATA3 + * | | |10 = CAN1_TXD + * | | |16 = HBI_D6 + * |[12:8] |PJ5MFP |PJ.5 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD2 + * | | |03 = UART8_RXD + * | | |06 = QSPI1_MOSI0 + * | | |07 = CCAP_DATA2 + * | | |10 = CAN1_RXD + * | | |16 = HBI_D5 + * |[20:16] |PJ6MFP |PJ.6 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD1 + * | | |03 = UART9_nCTS + * | | |07 = CCAP_DATA1 + * | | |10 = CAN2_TXD + * | | |16 = HBI_D4 + * |[28:24] |PJ7MFP |PJ.7 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_AD0 + * | | |03 = UART9_nRTS + * | | |07 = CCAP_DATA0 + * | | |10 = CAN2_RXD + * | | |16 = HBI_CK + * @var SYS_T::GPJ_MFP2 + * Offset: 0x598 GPIOJ Multiple Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PJ8MFP |PJ.8 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nRD + * | | |03 = SD1_DAT3 + * | | |04 = SPIM_SS + * | | |06 = UART7_TXD + * | | |11 = CAN2_TXD + * | | |12 = BPWM0_CH5 + * |[12:8] |PJ9MFP |PJ.9 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nWR + * | | |03 = SD1_DAT2 + * | | |04 = SPIM_MISO + * | | |06 = UART7_RXD + * | | |11 = CAN2_RXD + * | | |12 = BPWM0_CH4 + * |[20:16] |PJ10MFP |PJ.10 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_MCLK + * | | |03 = SD1_DAT1 + * | | |04 = SPIM_D2 + * | | |06 = UART6_TXD + * | | |08 = I2C4_SCL + * | | |09 = ECAP2_IC0 + * | | |11 = CAN0_TXD + * | | |12 = BPWM0_CH3 + * |[28:24] |PJ11MFP |PJ.11 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_ALE + * | | |03 = SD1_DAT0 + * | | |04 = SPIM_D3 + * | | |06 = UART6_RXD + * | | |08 = I2C4_SDA + * | | |09 = ECAP2_IC1 + * | | |11 = CAN0_RXD + * | | |12 = BPWM0_CH2 + * @var SYS_T::GPJ_MFP3 + * Offset: 0x59C GPIOJ Multiple Function Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |PJ12MFP |PJ.12 Multi-function Pin Selection + * | | |00 = GPIO + * | | |02 = EBI_nCS0 + * | | |03 = SD1_CMD + * | | |04 = SPIM_CLK + * | | |08 = I2C4_SMBAL + * | | |09 = ECAP2_IC2 + * | | |11 = CAN1_TXD + * | | |12 = BPWM0_CH1 + * | | |15 = HSUSB_VBUS_ST + * |[12:8] |PJ13MFP |PJ.13 Multi-function Pin Selection + * | | |00 = GPIO + * | | |03 = SD1_CLK + * | | |04 = SPIM_MOSI + * | | |08 = I2C4_SMBSUS + * | | |11 = CAN1_RXD + * | | |12 = BPWM0_CH0 + * | | |15 = HSUSB_VBUS_EN + */ + __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ + __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ + __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ + __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ + __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ + __I uint32_t RESERVE0[1]; + __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ + __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ + __IO uint32_t IPRST3; /*!< [0x0020] Peripheral Reset Control Register 3 */ + __IO uint32_t PORCTL; /*!< [0x0024] Power-On-reset Controller Register */ + __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ + __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ + __I uint32_t RESERVE1[20]; + __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ + __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ + __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ + __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ + __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ + __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ + __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ + __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ + __IO uint32_t GPI_MFOS; /*!< [0x00A0] GPIOI Multiple Function Output Select Register */ + __IO uint32_t GPJ_MFOS; /*!< [0x00A4] GPIOJ Multiple Function Output Select Register */ + __I uint32_t RESERVE2[2]; + __I uint32_t RESERVE3[4]; + __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ + __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ + __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ + __I uint32_t RESERVE4[1]; + __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ + __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ + __I uint32_t RESERVE5[3]; + __IO uint32_t HIRCTCTL; /*!< [0x00e4] HIRC48M Trim Control Register */ + __IO uint32_t HIRCTIEN; /*!< [0x00e8] HIRC48M Trim Interrupt Enable Register */ + __IO uint32_t HIRCTISTS; /*!< [0x00ec] HIRC48M Trim Interrupt Status Register */ + __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ + __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ + __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ + __I uint32_t RESERVE6[1]; + __O uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ + __I uint32_t RESERVE7[58]; + __IO uint32_t PORDISAN; /*!< [0x01ec] Analog POR Disable Control Register */ + __I uint32_t RESERVE8[1]; + __I uint32_t CSERVER; /*!< [0x01f4] Chip Series Version Register */ + __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ + __I uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ + __I uint32_t RESERVE9[128]; + __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ + __I uint32_t RESERVE10[63]; + __IO uint32_t GPA_MFP0; /*!< [0x0500] GPIOA Multiple Function Control Register 0 */ + __IO uint32_t GPA_MFP1; /*!< [0x0504] GPIOA Multiple Function Control Register 1 */ + __IO uint32_t GPA_MFP2; /*!< [0x0508] GPIOA Multiple Function Control Register 2 */ + __IO uint32_t GPA_MFP3; /*!< [0x050c] GPIOA Multiple Function Control Register 3 */ + __IO uint32_t GPB_MFP0; /*!< [0x0510] GPIOB Multiple Function Control Register 0 */ + __IO uint32_t GPB_MFP1; /*!< [0x0514] GPIOB Multiple Function Control Register 1 */ + __IO uint32_t GPB_MFP2; /*!< [0x0518] GPIOB Multiple Function Control Register 2 */ + __IO uint32_t GPB_MFP3; /*!< [0x051c] GPIOB Multiple Function Control Register 3 */ + __IO uint32_t GPC_MFP0; /*!< [0x0520] GPIOC Multiple Function Control Register 0 */ + __IO uint32_t GPC_MFP1; /*!< [0x0524] GPIOC Multiple Function Control Register 1 */ + __IO uint32_t GPC_MFP2; /*!< [0x0528] GPIOC Multiple Function Control Register 2 */ + __IO uint32_t GPC_MFP3; /*!< [0x052c] GPIOC Multiple Function Control Register 3 */ + __IO uint32_t GPD_MFP0; /*!< [0x0530] GPIOD Multiple Function Control Register 0 */ + __IO uint32_t GPD_MFP1; /*!< [0x0534] GPIOD Multiple Function Control Register 1 */ + __IO uint32_t GPD_MFP2; /*!< [0x0538] GPIOD Multiple Function Control Register 2 */ + __IO uint32_t GPD_MFP3; /*!< [0x053c] GPIOD Multiple Function Control Register 3 */ + __IO uint32_t GPE_MFP0; /*!< [0x0540] GPIOE Multiple Function Control Register 0 */ + __IO uint32_t GPE_MFP1; /*!< [0x0544] GPIOE Multiple Function Control Register 1 */ + __IO uint32_t GPE_MFP2; /*!< [0x0548] GPIOE Multiple Function Control Register 2 */ + __IO uint32_t GPE_MFP3; /*!< [0x054c] GPIOE Multiple Function Control Register 3 */ + __IO uint32_t GPF_MFP0; /*!< [0x0550] GPIOF Multiple Function Control Register 0 */ + __IO uint32_t GPF_MFP1; /*!< [0x0554] GPIOF Multiple Function Control Register 1 */ + __IO uint32_t GPF_MFP2; /*!< [0x0558] GPIOF Multiple Function Control Register 2 */ + __IO uint32_t GPF_MFP3; /*!< [0x055c] GPIOF Multiple Function Control Register 3 */ + __IO uint32_t GPG_MFP0; /*!< [0x0560] GPIOG Multiple Function Control Register 0 */ + __IO uint32_t GPG_MFP1; /*!< [0x0564] GPIOG Multiple Function Control Register 1 */ + __IO uint32_t GPG_MFP2; /*!< [0x0568] GPIOG Multiple Function Control Register 2 */ + __IO uint32_t GPG_MFP3; /*!< [0x056c] GPIOG Multiple Function Control Register 3 */ + __IO uint32_t GPH_MFP0; /*!< [0x0570] GPIOH Multiple Function Control Register 0 */ + __IO uint32_t GPH_MFP1; /*!< [0x0574] GPIOH Multiple Function Control Register 1 */ + __IO uint32_t GPH_MFP2; /*!< [0x0578] GPIOH Multiple Function Control Register 2 */ + __IO uint32_t GPH_MFP3; /*!< [0x057c] GPIOH Multiple Function Control Register 3 */ + __IO uint32_t GPI_MFP0; /*!< [0x0580] GPIOI Multiple Function Control Register 0 */ + __IO uint32_t GPI_MFP1; /*!< [0x0584] GPIOI Multiple Function Control Register 1 */ + __IO uint32_t GPI_MFP2; /*!< [0x0588] GPIOI Multiple Function Control Register 2 */ + __IO uint32_t GPI_MFP3; /*!< [0x058c] GPIOI Multiple Function Control Register 3 */ + __IO uint32_t GPJ_MFP0; /*!< [0x0590] GPIOJ Multiple Function Control Register 0 */ + __IO uint32_t GPJ_MFP1; /*!< [0x0594] GPIOJ Multiple Function Control Register 1 */ + __IO uint32_t GPJ_MFP2; /*!< [0x0598] GPIOJ Multiple Function Control Register 2 */ + __IO uint32_t GPJ_MFP3; /*!< [0x059c] GPIOJ Multiple Function Control Register 3 */ + +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller +@{ */ + +#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ +#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ +#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ +#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ + +#define SYS_RSTSTS_MCURF_Pos (5) /*!< SYS_T::RSTSTS: MCURF Position */ +#define SYS_RSTSTS_MCURF_Msk (0x1ul << SYS_RSTSTS_MCURF_Pos) /*!< SYS_T::RSTSTS: MCURF Mask */ + +#define SYS_RSTSTS_HRESETRF_Pos (6) /*!< SYS_T::RSTSTS: HRESETRF Position */ +#define SYS_RSTSTS_HRESETRF_Msk (0x1ul << SYS_RSTSTS_HRESETRF_Pos) /*!< SYS_T::RSTSTS: HRESETRF Mask */ + +#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ +#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ + +#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ +#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ +#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ + +#define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */ +#define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_EMAC0RST_Pos (5) /*!< SYS_T::IPRST0: EMAC0RST Position */ +#define SYS_IPRST0_EMAC0RST_Msk (0x1ul << SYS_IPRST0_EMAC0RST_Pos) /*!< SYS_T::IPRST0: EMAC0RST Mask */ + +#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ +#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ + +#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ +#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ + +#define SYS_IPRST0_CCAPRST_Pos (8) /*!< SYS_T::IPRST0: CCAPRST Position */ +#define SYS_IPRST0_CCAPRST_Msk (0x1ul << SYS_IPRST0_CCAPRST_Pos) /*!< SYS_T::IPRST0: CCAPRST Mask */ + +#define SYS_IPRST0_HSUSBDRST_Pos (10) /*!< SYS_T::IPRST0: HSUSBDRST Position */ +#define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) /*!< SYS_T::IPRST0: HSUSBDRST Mask */ + +#define SYS_IPRST0_HBIRST_Pos (11) /*!< SYS_T::IPRST0: HBIRST Position */ +#define SYS_IPRST0_HBIRST_Msk (0x1ul << SYS_IPRST0_HBIRST_Pos) /*!< SYS_T::IPRST0: HBIRST Mask */ + +#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ +#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ + +#define SYS_IPRST0_KSRST_Pos (13) /*!< SYS_T::IPRST0: KSRST Position */ +#define SYS_IPRST0_KSRST_Msk (0x1ul << SYS_IPRST0_KSRST_Pos) /*!< SYS_T::IPRST0: KSRST Mask */ + +#define SYS_IPRST0_SPIMRST_Pos (14) /*!< SYS_T::IPRST0: SPIMRST Position */ +#define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) /*!< SYS_T::IPRST0: SPIMRST Mask */ + +#define SYS_IPRST0_HSUSBHRST_Pos (16) /*!< SYS_T::IPRST0: HSUSBHRST Position */ +#define SYS_IPRST0_HSUSBHRST_Msk (0x1ul << SYS_IPRST0_HSUSBHRST_Pos) /*!< SYS_T::IPRST0: HSUSBHRST Mask */ + +#define SYS_IPRST0_SDH1RST_Pos (17) /*!< SYS_T::IPRST0: SDH1RST Position */ +#define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) /*!< SYS_T::IPRST0: SDH1RST Mask */ + +#define SYS_IPRST0_PDMA1RST_Pos (18) /*!< SYS_T::IPRST0: PDMA1RST Position */ +#define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */ + +#define SYS_IPRST0_CANFD0RST_Pos (20) /*!< SYS_T::IPRST0: CANFD0RST Position */ +#define SYS_IPRST0_CANFD0RST_Msk (0x1ul << SYS_IPRST0_CANFD0RST_Pos) /*!< SYS_T::IPRST0: CANFD0RST Mask */ + +#define SYS_IPRST0_CANFD1RST_Pos (21) /*!< SYS_T::IPRST0: CANFD1RST Position */ +#define SYS_IPRST0_CANFD1RST_Msk (0x1ul << SYS_IPRST0_CANFD1RST_Pos) /*!< SYS_T::IPRST0: CANFD1RST Mask */ + +#define SYS_IPRST0_CANFD2RST_Pos (22) /*!< SYS_T::IPRST0: CANFD2RST Position */ +#define SYS_IPRST0_CANFD2RST_Msk (0x1ul << SYS_IPRST0_CANFD2RST_Pos) /*!< SYS_T::IPRST0: CANFD2RST Mask */ + +#define SYS_IPRST0_CANFD3RST_Pos (23) /*!< SYS_T::IPRST0: CANFD3RST Position */ +#define SYS_IPRST0_CANFD3RST_Msk (0x1ul << SYS_IPRST0_CANFD3RST_Pos) /*!< SYS_T::IPRST0: CANFD3RST Mask */ + +#define SYS_IPRST0_BMCRST_Pos (28) /*!< SYS_T::IPRST0: BMCRST Position */ +#define SYS_IPRST0_BMCRST_Msk (0x1ul << SYS_IPRST0_BMCRST_Pos) /*!< SYS_T::IPRST0: BMCRST Mask */ + +#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ +#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ +#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ +#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ + +#define SYS_IPRST1_I2C3RST_Pos (11) /*!< SYS_T::IPRST1: I2C3RST Position */ +#define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) /*!< SYS_T::IPRST1: I2C3RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ +#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ + +#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ +#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ +#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ + +#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ +#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ + +#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ +#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ + +#define SYS_IPRST1_UART6RST_Pos (22) /*!< SYS_T::IPRST1: UART6RST Position */ +#define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) /*!< SYS_T::IPRST1: UART6RST Mask */ + +#define SYS_IPRST1_UART7RST_Pos (23) /*!< SYS_T::IPRST1: UART7RST Position */ +#define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) /*!< SYS_T::IPRST1: UART7RST Mask */ + +#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ +#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ + +#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ +#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ + +#define SYS_IPRST1_EADC0RST_Pos (28) /*!< SYS_T::IPRST1: EADC0RST Position */ +#define SYS_IPRST1_EADC0RST_Msk (0x1ul << SYS_IPRST1_EADC0RST_Pos) /*!< SYS_T::IPRST1: EADC0RST Mask */ + +#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ +#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ + +#define SYS_IPRST1_HSOTGRST_Pos (30) /*!< SYS_T::IPRST1: HSOTGRST Position */ +#define SYS_IPRST1_HSOTGRST_Msk (0x1ul << SYS_IPRST1_HSOTGRST_Pos) /*!< SYS_T::IPRST1: HSOTGRST Mask */ + +#define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ +#define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ +#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ + +#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ +#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ + +#define SYS_IPRST2_I2C4RST_Pos (3) /*!< SYS_T::IPRST2: I2C4RST Position */ +#define SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos) /*!< SYS_T::IPRST2: I2C4RST Mask */ + +#define SYS_IPRST2_QSPI1RST_Pos (4) /*!< SYS_T::IPRST2: QSPI1RST Position */ +#define SYS_IPRST2_QSPI1RST_Msk (0x1ul << SYS_IPRST2_QSPI1RST_Pos) /*!< SYS_T::IPRST2: QSPI1RST Mask */ + +#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ +#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ + +#define SYS_IPRST2_SPI4RST_Pos (7) /*!< SYS_T::IPRST2: SPI4RST Position */ +#define SYS_IPRST2_SPI4RST_Msk (0x1ul << SYS_IPRST2_SPI4RST_Pos) /*!< SYS_T::IPRST2: SPI4RST Mask */ + +#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ +#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ + +#define SYS_IPRST2_PSIORST_Pos (10) /*!< SYS_T::IPRST2: PSIORST Position */ +#define SYS_IPRST2_PSIORST_Msk (0x1ul << SYS_IPRST2_PSIORST_Pos) /*!< SYS_T::IPRST2: PSIORST Mask */ + +#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ +#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ + +#define SYS_IPRST2_ECAP2RST_Pos (13) /*!< SYS_T::IPRST2: ECAP2RST Position */ +#define SYS_IPRST2_ECAP2RST_Msk (0x1ul << SYS_IPRST2_ECAP2RST_Pos) /*!< SYS_T::IPRST2: ECAP2RST Mask */ + +#define SYS_IPRST2_ECAP3RST_Pos (14) /*!< SYS_T::IPRST2: ECAP3RST Position */ +#define SYS_IPRST2_ECAP3RST_Msk (0x1ul << SYS_IPRST2_ECAP3RST_Pos) /*!< SYS_T::IPRST2: ECAP3RST Mask */ + +#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ +#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ + +#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ +#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ + +#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ +#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ + +#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ +#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ + +#define SYS_IPRST2_EQEI2RST_Pos (20) /*!< SYS_T::IPRST2: EQEI2RST Position */ +#define SYS_IPRST2_EQEI2RST_Msk (0x1ul << SYS_IPRST2_EQEI2RST_Pos) /*!< SYS_T::IPRST2: EQEI2RST Mask */ + +#define SYS_IPRST2_EQEI3RST_Pos (21) /*!< SYS_T::IPRST2: EQEI3RST Position */ +#define SYS_IPRST2_EQEI3RST_Msk (0x1ul << SYS_IPRST2_EQEI3RST_Pos) /*!< SYS_T::IPRST2: EQEI3RST Mask */ + +#define SYS_IPRST2_EQEI0RST_Pos (22) /*!< SYS_T::IPRST2: EQEI0RST Position */ +#define SYS_IPRST2_EQEI0RST_Msk (0x1ul << SYS_IPRST2_EQEI0RST_Pos) /*!< SYS_T::IPRST2: EQEI0RST Mask */ + +#define SYS_IPRST2_EQEI1RST_Pos (23) /*!< SYS_T::IPRST2: EQEI1RST Position */ +#define SYS_IPRST2_EQEI1RST_Msk (0x1ul << SYS_IPRST2_EQEI1RST_Pos) /*!< SYS_T::IPRST2: EQEI1RST Mask */ + +#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ +#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ + +#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ +#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ + +#define SYS_IPRST2_I2S1RST_Pos (29) /*!< SYS_T::IPRST2: I2S1RST Position */ +#define SYS_IPRST2_I2S1RST_Msk (0x1ul << SYS_IPRST2_I2S1RST_Pos) /*!< SYS_T::IPRST2: I2S1RST Mask */ + +#define SYS_IPRST2_EADC1RST_Pos (31) /*!< SYS_T::IPRST2: EADC1RST Position */ +#define SYS_IPRST2_EADC1RST_Msk (0x1ul << SYS_IPRST2_EADC1RST_Pos) /*!< SYS_T::IPRST2: EADC1RST Mask */ + +#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ +#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ + +#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ +#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ + +#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ +#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ + +#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ +#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ + +#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ +#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ + +#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ +#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ + +#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ +#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ + +#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ +#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ + +#define SYS_BODCTL_LVRRDY_Pos (15) /*!< SYS_T::BODCTL: LVRRDY Position */ +#define SYS_BODCTL_LVRRDY_Msk (0x1ul << SYS_BODCTL_LVRRDY_Pos) /*!< SYS_T::BODCTL: LVRRDY Mask */ + +#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ +#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ + +#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ +#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ + +#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ +#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ + +#define SYS_IPRST3_KPIRST_Pos (0) /*!< SYS_T::IPRST3: KPIRST Position */ +#define SYS_IPRST3_KPIRST_Msk (0x1ul << SYS_IPRST3_KPIRST_Pos) /*!< SYS_T::IPRST3: KPIRST Mask */ + +#define SYS_IPRST3_EADC2RST_Pos (6) /*!< SYS_T::IPRST3: EADC2RST Position */ +#define SYS_IPRST3_EADC2RST_Msk (0x1ul << SYS_IPRST3_EADC2RST_Pos) /*!< SYS_T::IPRST3: EADC2RST Mask */ + +#define SYS_IPRST3_ACMP23RST_Pos (7) /*!< SYS_T::IPRST3: ACMP23RST Position */ +#define SYS_IPRST3_ACMP23RST_Msk (0x1ul << SYS_IPRST3_ACMP23RST_Pos) /*!< SYS_T::IPRST3: ACMP23RST Mask */ + +#define SYS_IPRST3_SPI5RST_Pos (8) /*!< SYS_T::IPRST3: SPI5RST Position */ +#define SYS_IPRST3_SPI5RST_Msk (0x1ul << SYS_IPRST3_SPI5RST_Pos) /*!< SYS_T::IPRST3: SPI5RST Mask */ + +#define SYS_IPRST3_SPI6RST_Pos (9) /*!< SYS_T::IPRST3: SPI6RST Position */ +#define SYS_IPRST3_SPI6RST_Msk (0x1ul << SYS_IPRST3_SPI6RST_Pos) /*!< SYS_T::IPRST3: SPI6RST Mask */ + +#define SYS_IPRST3_SPI7RST_Pos (10) /*!< SYS_T::IPRST3: SPI7RST Position */ +#define SYS_IPRST3_SPI7RST_Msk (0x1ul << SYS_IPRST3_SPI7RST_Pos) /*!< SYS_T::IPRST3: SPI7RST Mask */ + +#define SYS_IPRST3_SPI8RST_Pos (11) /*!< SYS_T::IPRST3: SPI8RST Position */ +#define SYS_IPRST3_SPI8RST_Msk (0x1ul << SYS_IPRST3_SPI8RST_Pos) /*!< SYS_T::IPRST3: SPI8RST Mask */ + +#define SYS_IPRST3_SPI9RST_Pos (12) /*!< SYS_T::IPRST3: SPI9RST Position */ +#define SYS_IPRST3_SPI9RST_Msk (0x1ul << SYS_IPRST3_SPI9RST_Pos) /*!< SYS_T::IPRST3: SPI9RST Mask */ + +#define SYS_IPRST3_SPI10RST_Pos (13) /*!< SYS_T::IPRST3: SPI10RST Position */ +#define SYS_IPRST3_SPI10RST_Msk (0x1ul << SYS_IPRST3_SPI10RST_Pos) /*!< SYS_T::IPRST3: SPI10RST Mask */ + +#define SYS_IPRST3_UART8RST_Pos (16) /*!< SYS_T::IPRST3: UART8RST Position */ +#define SYS_IPRST3_UART8RST_Msk (0x1ul << SYS_IPRST3_UART8RST_Pos) /*!< SYS_T::IPRST3: UART8RST Mask */ + +#define SYS_IPRST3_UART9RST_Pos (17) /*!< SYS_T::IPRST3: UART9RST Position */ +#define SYS_IPRST3_UART9RST_Msk (0x1ul << SYS_IPRST3_UART9RST_Pos) /*!< SYS_T::IPRST3: UART9RST Mask */ + +#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */ +#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */ + +#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ +#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ + +#define SYS_VREFCTL_PRELOADSEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOADSEL Position */ +#define SYS_VREFCTL_PRELOADSEL_Msk (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos) /*!< SYS_T::VREFCTL: PRELOADSEL Mask */ + +#define SYS_VREFCTL_VBGFEN_Pos (24) /*!< SYS_T::VREFCTL: VBGFEN Position */ +#define SYS_VREFCTL_VBGFEN_Msk (0x1ul << SYS_VREFCTL_VBGFEN_Pos) /*!< SYS_T::VREFCTL: VBGFEN Mask */ + +#define SYS_VREFCTL_VBGISEL_Pos (25) /*!< SYS_T::VREFCTL: VBGISEL Position */ +#define SYS_VREFCTL_VBGISEL_Msk (0x3ul << SYS_VREFCTL_VBGISEL_Pos) /*!< SYS_T::VREFCTL: VBGISEL Mask */ + +#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ +#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ + +#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ +#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ + +#define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ +#define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ + +#define SYS_USBPHY_HSUSBROLE_Pos (16) /*!< SYS_T::USBPHY: HSUSBROLE Position */ +#define SYS_USBPHY_HSUSBROLE_Msk (0x3ul << SYS_USBPHY_HSUSBROLE_Pos) /*!< SYS_T::USBPHY: HSUSBROLE Mask */ + +#define SYS_USBPHY_HSUSBEN_Pos (24) /*!< SYS_T::USBPHY: HSUSBEN Position */ +#define SYS_USBPHY_HSUSBEN_Msk (0x1ul << SYS_USBPHY_HSUSBEN_Pos) /*!< SYS_T::USBPHY: HSUSBEN Mask */ + +#define SYS_USBPHY_HSUSBACT_Pos (25) /*!< SYS_T::USBPHY: HSUSBACT Position */ +#define SYS_USBPHY_HSUSBACT_Msk (0x1ul << SYS_USBPHY_HSUSBACT_Pos) /*!< SYS_T::USBPHY: HSUSBACT Mask */ + +#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ +#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ + +#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ +#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ + +#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ +#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ + +#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ +#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ + +#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ +#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ + +#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ +#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ + +#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ +#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ + +#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ +#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ + +#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ +#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ + +#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ +#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ + +#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ +#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ + +#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ +#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ + +#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ +#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ + +#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ +#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ + +#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ +#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ + +#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ +#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ + +#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ +#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ + +#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ +#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ + +#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ +#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ + +#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ +#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ + +#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ +#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ + +#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ +#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ + +#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ +#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ + +#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ +#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ + +#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ +#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ + +#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ +#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ + +#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ +#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ + +#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ +#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ + +#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ +#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ + +#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ +#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ + +#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ +#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ + +#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ +#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ + +#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ +#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ + +#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ +#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ + +#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ +#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ + +#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ +#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ + +#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ +#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ + +#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ +#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ + +#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ +#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ + +#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ +#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ + +#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ +#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ + +#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ +#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ + +#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ +#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ + +#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ +#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ + +#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ +#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ + +#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ +#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ + +#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ +#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ + +#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ +#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ + +#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ +#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ + +#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ +#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ + +#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ +#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ + +#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ +#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ + +#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ +#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ + +#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ +#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ + +#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ +#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ + +#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ +#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ + +#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ +#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ + +#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ +#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ + +#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ +#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ + +#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ +#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ + +#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ +#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ + +#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ +#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ +#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ + +#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ +#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ + +#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ +#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ + +#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ +#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ + +#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ +#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ + +#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ +#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ + +#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ +#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ + +#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ +#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ + +#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ +#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ + +#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ +#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ + +#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ +#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ + +#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ +#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ + +#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ +#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ + +#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ +#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ + +#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ +#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ +#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ + +#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ +#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ + +#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ +#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ + +#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ +#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ + +#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ +#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ + +#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ +#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ + +#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ +#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ + +#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ +#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ + +#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ +#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ + +#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ +#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ + +#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ +#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ + +#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ +#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ + +#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ +#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ +#define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ + +#define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ +#define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ + +#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ +#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ + +#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ +#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ + +#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ +#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ + +#define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ +#define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ + +#define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ +#define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ + +#define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ +#define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ + +#define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ +#define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ + +#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ +#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ + +#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ +#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ + +#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ +#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ +#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ + +#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ +#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ + +#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ +#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ + +#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ +#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ + +#define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ +#define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ + +#define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ +#define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ + +#define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ +#define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ + +#define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ +#define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ + +#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ +#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ + +#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ +#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ + +#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ +#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ + +#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ +#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ + +#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ +#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ + +#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ +#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ + +#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ +#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ + +#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ +#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ + +#define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ +#define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ + +#define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ +#define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ + +#define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ +#define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ + +#define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ +#define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ + +#define SYS_GPI_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPI_MFOS: MFOS6 Position */ +#define SYS_GPI_MFOS_MFOS6_Msk (0x1ul << SYS_GPI_MFOS_MFOS6_Pos) /*!< SYS_T::GPI_MFOS: MFOS6 Mask */ + +#define SYS_GPI_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPI_MFOS: MFOS7 Position */ +#define SYS_GPI_MFOS_MFOS7_Msk (0x1ul << SYS_GPI_MFOS_MFOS7_Pos) /*!< SYS_T::GPI_MFOS: MFOS7 Mask */ + +#define SYS_GPI_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPI_MFOS: MFOS8 Position */ +#define SYS_GPI_MFOS_MFOS8_Msk (0x1ul << SYS_GPI_MFOS_MFOS8_Pos) /*!< SYS_T::GPI_MFOS: MFOS8 Mask */ + +#define SYS_GPI_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPI_MFOS: MFOS9 Position */ +#define SYS_GPI_MFOS_MFOS9_Msk (0x1ul << SYS_GPI_MFOS_MFOS9_Pos) /*!< SYS_T::GPI_MFOS: MFOS9 Mask */ + +#define SYS_GPI_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPI_MFOS: MFOS10 Position */ +#define SYS_GPI_MFOS_MFOS10_Msk (0x1ul << SYS_GPI_MFOS_MFOS10_Pos) /*!< SYS_T::GPI_MFOS: MFOS10 Mask */ + +#define SYS_GPI_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPI_MFOS: MFOS11 Position */ +#define SYS_GPI_MFOS_MFOS11_Msk (0x1ul << SYS_GPI_MFOS_MFOS11_Pos) /*!< SYS_T::GPI_MFOS: MFOS11 Mask */ + +#define SYS_GPI_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPI_MFOS: MFOS12 Position */ +#define SYS_GPI_MFOS_MFOS12_Msk (0x1ul << SYS_GPI_MFOS_MFOS12_Pos) /*!< SYS_T::GPI_MFOS: MFOS12 Mask */ + +#define SYS_GPI_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPI_MFOS: MFOS13 Position */ +#define SYS_GPI_MFOS_MFOS13_Msk (0x1ul << SYS_GPI_MFOS_MFOS13_Pos) /*!< SYS_T::GPI_MFOS: MFOS13 Mask */ + +#define SYS_GPI_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPI_MFOS: MFOS14 Position */ +#define SYS_GPI_MFOS_MFOS14_Msk (0x1ul << SYS_GPI_MFOS_MFOS14_Pos) /*!< SYS_T::GPI_MFOS: MFOS14 Mask */ + +#define SYS_GPI_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPI_MFOS: MFOS15 Position */ +#define SYS_GPI_MFOS_MFOS15_Msk (0x1ul << SYS_GPI_MFOS_MFOS15_Pos) /*!< SYS_T::GPI_MFOS: MFOS15 Mask */ + +#define SYS_GPJ_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPJ_MFOS: MFOS0 Position */ +#define SYS_GPJ_MFOS_MFOS0_Msk (0x1ul << SYS_GPJ_MFOS_MFOS0_Pos) /*!< SYS_T::GPJ_MFOS: MFOS0 Mask */ + +#define SYS_GPJ_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPJ_MFOS: MFOS1 Position */ +#define SYS_GPJ_MFOS_MFOS1_Msk (0x1ul << SYS_GPJ_MFOS_MFOS1_Pos) /*!< SYS_T::GPJ_MFOS: MFOS1 Mask */ + +#define SYS_GPJ_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPJ_MFOS: MFOS2 Position */ +#define SYS_GPJ_MFOS_MFOS2_Msk (0x1ul << SYS_GPJ_MFOS_MFOS2_Pos) /*!< SYS_T::GPJ_MFOS: MFOS2 Mask */ + +#define SYS_GPJ_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPJ_MFOS: MFOS3 Position */ +#define SYS_GPJ_MFOS_MFOS3_Msk (0x1ul << SYS_GPJ_MFOS_MFOS3_Pos) /*!< SYS_T::GPJ_MFOS: MFOS3 Mask */ + +#define SYS_GPJ_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPJ_MFOS: MFOS4 Position */ +#define SYS_GPJ_MFOS_MFOS4_Msk (0x1ul << SYS_GPJ_MFOS_MFOS4_Pos) /*!< SYS_T::GPJ_MFOS: MFOS4 Mask */ + +#define SYS_GPJ_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPJ_MFOS: MFOS5 Position */ +#define SYS_GPJ_MFOS_MFOS5_Msk (0x1ul << SYS_GPJ_MFOS_MFOS5_Pos) /*!< SYS_T::GPJ_MFOS: MFOS5 Mask */ + +#define SYS_GPJ_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPJ_MFOS: MFOS6 Position */ +#define SYS_GPJ_MFOS_MFOS6_Msk (0x1ul << SYS_GPJ_MFOS_MFOS6_Pos) /*!< SYS_T::GPJ_MFOS: MFOS6 Mask */ + +#define SYS_GPJ_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPJ_MFOS: MFOS7 Position */ +#define SYS_GPJ_MFOS_MFOS7_Msk (0x1ul << SYS_GPJ_MFOS_MFOS7_Pos) /*!< SYS_T::GPJ_MFOS: MFOS7 Mask */ + +#define SYS_GPJ_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPJ_MFOS: MFOS8 Position */ +#define SYS_GPJ_MFOS_MFOS8_Msk (0x1ul << SYS_GPJ_MFOS_MFOS8_Pos) /*!< SYS_T::GPJ_MFOS: MFOS8 Mask */ + +#define SYS_GPJ_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPJ_MFOS: MFOS9 Position */ +#define SYS_GPJ_MFOS_MFOS9_Msk (0x1ul << SYS_GPJ_MFOS_MFOS9_Pos) /*!< SYS_T::GPJ_MFOS: MFOS9 Mask */ + +#define SYS_GPJ_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPJ_MFOS: MFOS10 Position */ +#define SYS_GPJ_MFOS_MFOS10_Msk (0x1ul << SYS_GPJ_MFOS_MFOS10_Pos) /*!< SYS_T::GPJ_MFOS: MFOS10 Mask */ + +#define SYS_GPJ_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPJ_MFOS: MFOS11 Position */ +#define SYS_GPJ_MFOS_MFOS11_Msk (0x1ul << SYS_GPJ_MFOS_MFOS11_Pos) /*!< SYS_T::GPJ_MFOS: MFOS11 Mask */ + +#define SYS_GPJ_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPJ_MFOS: MFOS12 Position */ +#define SYS_GPJ_MFOS_MFOS12_Msk (0x1ul << SYS_GPJ_MFOS_MFOS12_Pos) /*!< SYS_T::GPJ_MFOS: MFOS12 Mask */ + +#define SYS_GPJ_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPJ_MFOS: MFOS13 Position */ +#define SYS_GPJ_MFOS_MFOS13_Msk (0x1ul << SYS_GPJ_MFOS_MFOS13_Pos) /*!< SYS_T::GPJ_MFOS: MFOS13 Mask */ + +#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ +#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ + +#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ +#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ + +#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ +#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ +#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ +#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ + +#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ +#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ + +#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */ +#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */ + +#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ +#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ + +#define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Position */ +#define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SPIMBIST Mask */ + +#define SYS_SRAM_BISTCTL_EMAC0BIST_Pos (6) /*!< SYS_T::SRAM_BISTCTL: EMAC0BIST Position*/ +#define SYS_SRAM_BISTCTL_EMAC0BIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMAC0BIST_Pos) /*!< SYS_T::SRAM_BISTCTL: EMAC0BIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Pos (8) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBDBIST Mask */ + +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Pos (9) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Position*/ +#define SYS_SRAM_BISTCTL_HSUSBHBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_HSUSBHBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: HSUSBHBIST Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST2_Pos (10) /*!< SYS_T::SRAM_BISTCTL: SRBIST2 Position */ +#define SYS_SRAM_BISTCTL_SRBIST2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST2_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST2 Mask */ + +#define SYS_SRAM_BISTCTL_KSBIST_Pos (11) /*!< SYS_T::SRAM_BISTCTL: KSBIST Position */ +#define SYS_SRAM_BISTCTL_KSBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_KSBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: KSBIST Mask */ + +#define SYS_SRAM_BISTCTL_CCAPBIST_Pos (12) /*!< SYS_T::SRAM_BISTCTL: CCAPBIST Position */ +#define SYS_SRAM_BISTCTL_CCAPBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CCAPBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CCAPBIST Mask */ + +#define SYS_SRAM_BISTCTL_RSABIST_Pos (13) /*!< SYS_T::SRAM_BISTCTL: RSABIST Position */ +#define SYS_SRAM_BISTCTL_RSABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_RSABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: RSABIST Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ +#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ + +#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ +#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ + +#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ +#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ + +#define SYS_SRAM_BISTSTS_SPIMBEF_Pos (5) /*!< SYS_T::SRAM_BISTSTS: SPIMBEF Position */ +#define SYS_SRAM_BISTSTS_SPIMBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_SPIMBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: SPIMBEF Mask */ + +#define SYS_SRAM_BISTSTS_EMAC0BEF_Pos (6) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEF Position */ +#define SYS_SRAM_BISTSTS_EMAC0BEF_Msk (0x1ul << SYS_SRAM_BISTSTS_EMAC0BEF_Pos) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEF Mask */ + +#define SYS_SRAM_BISTSTS_HSUSBDBEF_Pos (8) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEF Position*/ +#define SYS_SRAM_BISTSTS_HSUSBDBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBDBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEF Mask */ + +#define SYS_SRAM_BISTSTS_HSUSBHBEF_Pos (9) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEF Position*/ +#define SYS_SRAM_BISTSTS_HSUSBHBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBHBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEF Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF2_Pos (10) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF2 Position*/ +#define SYS_SRAM_BISTSTS_SRBISTEF2_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF2_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF2 Mask */ + +#define SYS_SRAM_BISTSTS_KSBISTEF_Pos (11) /*!< SYS_T::SRAM_BISTSTS: KSBISTEF Position */ +#define SYS_SRAM_BISTSTS_KSBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_KSBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: KSBISTEF Mask */ + +#define SYS_SRAM_BISTSTS_CCAPBISTEF_Pos (12) /*!< SYS_T::SRAM_BISTSTS: CCAPBISTEF Position*/ +#define SYS_SRAM_BISTSTS_CCAPBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CCAPBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CCAPBISTEF Mask */ + +#define SYS_SRAM_BISTSTS_RSABISTE_Pos (13) /*!< SYS_T::SRAM_BISTSTS: RSABISTE Position */ +#define SYS_SRAM_BISTSTS_RSABISTE_Msk (0x1ul << SYS_SRAM_BISTSTS_RSABISTE_Pos) /*!< SYS_T::SRAM_BISTSTS: RSABISTE Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ +#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ +#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ + +#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ +#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ + +#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ +#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ + +#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ +#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ + +#define SYS_SRAM_BISTSTS_SPIMBEND_Pos (21) /*!< SYS_T::SRAM_BISTSTS: SPIMBEND Position */ +#define SYS_SRAM_BISTSTS_SPIMBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_SPIMBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: SPIMBEND Mask */ + +#define SYS_SRAM_BISTSTS_EMAC0BEND_Pos (22) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEND Position*/ +#define SYS_SRAM_BISTSTS_EMAC0BEND_Msk (0x1ul << SYS_SRAM_BISTSTS_EMAC0BEND_Pos) /*!< SYS_T::SRAM_BISTSTS: EMAC0BEND Mask */ + +#define SYS_SRAM_BISTSTS_HSUSBDBEND_Pos (24) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEND Position*/ +#define SYS_SRAM_BISTSTS_HSUSBDBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBDBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBDBEND Mask */ + +#define SYS_SRAM_BISTSTS_HSUSBHBEND_Pos (25) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEND Position*/ +#define SYS_SRAM_BISTSTS_HSUSBHBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_HSUSBHBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: HSUSBHBEND Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND2_Pos (26) /*!< SYS_T::SRAM_BISTSTS: SRBEND2 Position */ +#define SYS_SRAM_BISTSTS_SRBEND2_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND2_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND2 Mask */ + +#define SYS_SRAM_BISTSTS_KSBEND_Pos (27) /*!< SYS_T::SRAM_BISTSTS: KSBEND Position */ +#define SYS_SRAM_BISTSTS_KSBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_KSBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: KSBEND Mask */ + +#define SYS_SRAM_BISTSTS_CCAPBEND_Pos (28) /*!< SYS_T::SRAM_BISTSTS: CCAPBEND Position */ +#define SYS_SRAM_BISTSTS_CCAPBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CCAPBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CCAPBEND Mask */ + +#define SYS_SRAM_BISTSTS_RSABEND_Pos (29) /*!< SYS_T::SRAM_BISTSTS: RSABEND Position */ +#define SYS_SRAM_BISTSTS_RSABEND_Msk (0x1ul << SYS_SRAM_BISTSTS_RSABEND_Pos) /*!< SYS_T::SRAM_BISTSTS: RSABEND Mask */ + +#define SYS_HIRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::HIRCTCTL: FREQSEL Position */ +#define SYS_HIRCTCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTCTL_FREQSEL_Pos) /*!< SYS_T::HIRCTCTL: FREQSEL Mask */ + +#define SYS_HIRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::HIRCTCTL: LOOPSEL Position */ +#define SYS_HIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTCTL_LOOPSEL_Pos) /*!< SYS_T::HIRCTCTL: LOOPSEL Mask */ + +#define SYS_HIRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::HIRCTCTL: RETRYCNT Position */ +#define SYS_HIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTCTL_RETRYCNT_Pos) /*!< SYS_T::HIRCTCTL: RETRYCNT Mask */ + +#define SYS_HIRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::HIRCTCTL: CESTOPEN Position */ +#define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTCTL: CESTOPEN Mask */ + +#define SYS_HIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTCTL: BOUNDEN Position */ +#define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */ + +#define SYS_HIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTCTL: REFCKSEL Position */ +#define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTCTL: REFCKSEL Mask */ + +#define SYS_HIRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::HIRCTCTL: BOUNDARY Position */ +#define SYS_HIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTCTL_BOUNDARY_Pos) /*!< SYS_T::HIRCTCTL: BOUNDARY Mask */ + +#define SYS_HIRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::HIRCTIEN: TFAILIEN Position */ +#define SYS_HIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_HIRCTIEN_TFAILIEN_Pos) /*!< SYS_T::HIRCTIEN: TFAILIEN Mask */ + +#define SYS_HIRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::HIRCTIEN: CLKEIEN Position */ +#define SYS_HIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTIEN_CLKEIEN_Pos) /*!< SYS_T::HIRCTIEN: CLKEIEN Mask */ + +#define SYS_HIRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::HIRCTISTS: FREQLOCK Position */ +#define SYS_HIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTISTS_FREQLOCK_Pos) /*!< SYS_T::HIRCTISTS: FREQLOCK Mask */ + +#define SYS_HIRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::HIRCTISTS: TFAILIF Position */ +#define SYS_HIRCTISTS_TFAILIF_Msk (0x1ul << SYS_HIRCTISTS_TFAILIF_Pos) /*!< SYS_T::HIRCTISTS: TFAILIF Mask */ + +#define SYS_HIRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::HIRCTISTS: CLKERRIF Position */ +#define SYS_HIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_HIRCTISTS_CLKERRIF_Pos) /*!< SYS_T::HIRCTISTS: CLKERRIF Mask */ + +#define SYS_HIRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::HIRCTISTS: OVBDIF Position */ +#define SYS_HIRCTISTS_OVBDIF_Msk (0x1ul << SYS_HIRCTISTS_OVBDIF_Pos) /*!< SYS_T::HIRCTISTS: OVBDIF Mask */ + +#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ +#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ + +#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ +#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ + +#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ +#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ + +#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ +#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ + +#define SYS_IRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::IRCTCTL: BOUNDEN Position */ +#define SYS_IRCTCTL_BOUNDEN_Msk (0x1ul << SYS_IRCTCTL_BOUNDEN_Pos) /*!< SYS_T::IRCTCTL: BOUNDEN Mask */ + +#define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ +#define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ + +#define SYS_IRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::IRCTCTL: BOUNDARY Position */ +#define SYS_IRCTCTL_BOUNDARY_Msk (0x1ful << SYS_IRCTCTL_BOUNDARY_Pos) /*!< SYS_T::IRCTCTL: BOUNDARY Mask */ + +#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ +#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ + +#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ +#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ + +#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ +#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ + +#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ +#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ + +#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ +#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ + +#define SYS_IRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::IRCTISTS: OVBDIF Position */ +#define SYS_IRCTISTS_OVBDIF_Msk (0x1ul << SYS_IRCTISTS_OVBDIF_Pos) /*!< SYS_T::IRCTISTS: OVBDIF Mask */ + +#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ +#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ + +#define SYS_PORDISAN_POROFFAN_Pos (0) /*!< SYS_T::PORDISAN: POROFFAN Position */ +#define SYS_PORDISAN_POROFFAN_Msk (0xfffful << SYS_PORDISAN_POROFFAN_Pos) /*!< SYS_T::PORDISAN: POROFFAN Mask */ + +#define SYS_CSERVER_VERSION_Pos (0) /*!< SYS_T::CSERVER: VERSION Position */ +#define SYS_CSERVER_VERSION_Msk (0xfful << SYS_CSERVER_VERSION_Pos) /*!< SYS_T::CSERVER: VERSION Mask */ + +#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ +#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ + +#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ +#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ + +#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ +#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ + +#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ +#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ + +#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ +#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ + +#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ +#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ + +#define SYS_GPA_MFP0_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFP0: PA0MFP Position */ +#define SYS_GPA_MFP0_PA0MFP_Msk (0x1ful << SYS_GPA_MFP0_PA0MFP_Pos) /*!< SYS_T::GPA_MFP0: PA0MFP Mask */ + +#define SYS_GPA_MFP0_PA1MFP_Pos (8) /*!< SYS_T::GPA_MFP0: PA1MFP Position */ +#define SYS_GPA_MFP0_PA1MFP_Msk (0x1ful << SYS_GPA_MFP0_PA1MFP_Pos) /*!< SYS_T::GPA_MFP0: PA1MFP Mask */ + +#define SYS_GPA_MFP0_PA2MFP_Pos (16) /*!< SYS_T::GPA_MFP0: PA2MFP Position */ +#define SYS_GPA_MFP0_PA2MFP_Msk (0x1ful << SYS_GPA_MFP0_PA2MFP_Pos) /*!< SYS_T::GPA_MFP0: PA2MFP Mask */ + +#define SYS_GPA_MFP0_PA3MFP_Pos (24) /*!< SYS_T::GPA_MFP0: PA3MFP Position */ +#define SYS_GPA_MFP0_PA3MFP_Msk (0x1ful << SYS_GPA_MFP0_PA3MFP_Pos) /*!< SYS_T::GPA_MFP0: PA3MFP Mask */ + +#define SYS_GPA_MFP1_PA4MFP_Pos (0) /*!< SYS_T::GPA_MFP1: PA4MFP Position */ +#define SYS_GPA_MFP1_PA4MFP_Msk (0x1ful << SYS_GPA_MFP1_PA4MFP_Pos) /*!< SYS_T::GPA_MFP1: PA4MFP Mask */ + +#define SYS_GPA_MFP1_PA5MFP_Pos (8) /*!< SYS_T::GPA_MFP1: PA5MFP Position */ +#define SYS_GPA_MFP1_PA5MFP_Msk (0x1ful << SYS_GPA_MFP1_PA5MFP_Pos) /*!< SYS_T::GPA_MFP1: PA5MFP Mask */ + +#define SYS_GPA_MFP1_PA6MFP_Pos (16) /*!< SYS_T::GPA_MFP1: PA6MFP Position */ +#define SYS_GPA_MFP1_PA6MFP_Msk (0x1ful << SYS_GPA_MFP1_PA6MFP_Pos) /*!< SYS_T::GPA_MFP1: PA6MFP Mask */ + +#define SYS_GPA_MFP1_PA7MFP_Pos (24) /*!< SYS_T::GPA_MFP1: PA7MFP Position */ +#define SYS_GPA_MFP1_PA7MFP_Msk (0x1ful << SYS_GPA_MFP1_PA7MFP_Pos) /*!< SYS_T::GPA_MFP1: PA7MFP Mask */ + +#define SYS_GPA_MFP2_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFP2: PA8MFP Position */ +#define SYS_GPA_MFP2_PA8MFP_Msk (0x1ful << SYS_GPA_MFP2_PA8MFP_Pos) /*!< SYS_T::GPA_MFP2: PA8MFP Mask */ + +#define SYS_GPA_MFP2_PA9MFP_Pos (8) /*!< SYS_T::GPA_MFP2: PA9MFP Position */ +#define SYS_GPA_MFP2_PA9MFP_Msk (0x1ful << SYS_GPA_MFP2_PA9MFP_Pos) /*!< SYS_T::GPA_MFP2: PA9MFP Mask */ + +#define SYS_GPA_MFP2_PA10MFP_Pos (16) /*!< SYS_T::GPA_MFP2: PA10MFP Position */ +#define SYS_GPA_MFP2_PA10MFP_Msk (0x1ful << SYS_GPA_MFP2_PA10MFP_Pos) /*!< SYS_T::GPA_MFP2: PA10MFP Mask */ + +#define SYS_GPA_MFP2_PA11MFP_Pos (24) /*!< SYS_T::GPA_MFP2: PA11MFP Position */ +#define SYS_GPA_MFP2_PA11MFP_Msk (0x1ful << SYS_GPA_MFP2_PA11MFP_Pos) /*!< SYS_T::GPA_MFP2: PA11MFP Mask */ + +#define SYS_GPA_MFP3_PA12MFP_Pos (0) /*!< SYS_T::GPA_MFP3: PA12MFP Position */ +#define SYS_GPA_MFP3_PA12MFP_Msk (0x1ful << SYS_GPA_MFP3_PA12MFP_Pos) /*!< SYS_T::GPA_MFP3: PA12MFP Mask */ + +#define SYS_GPA_MFP3_PA13MFP_Pos (8) /*!< SYS_T::GPA_MFP3: PA13MFP Position */ +#define SYS_GPA_MFP3_PA13MFP_Msk (0x1ful << SYS_GPA_MFP3_PA13MFP_Pos) /*!< SYS_T::GPA_MFP3: PA13MFP Mask */ + +#define SYS_GPA_MFP3_PA14MFP_Pos (16) /*!< SYS_T::GPA_MFP3: PA14MFP Position */ +#define SYS_GPA_MFP3_PA14MFP_Msk (0x1ful << SYS_GPA_MFP3_PA14MFP_Pos) /*!< SYS_T::GPA_MFP3: PA14MFP Mask */ + +#define SYS_GPA_MFP3_PA15MFP_Pos (24) /*!< SYS_T::GPA_MFP3: PA15MFP Position */ +#define SYS_GPA_MFP3_PA15MFP_Msk (0x1ful << SYS_GPA_MFP3_PA15MFP_Pos) /*!< SYS_T::GPA_MFP3: PA15MFP Mask */ + +#define SYS_GPB_MFP0_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFP0: PB0MFP Position */ +#define SYS_GPB_MFP0_PB0MFP_Msk (0x1ful << SYS_GPB_MFP0_PB0MFP_Pos) /*!< SYS_T::GPB_MFP0: PB0MFP Mask */ + +#define SYS_GPB_MFP0_PB1MFP_Pos (8) /*!< SYS_T::GPB_MFP0: PB1MFP Position */ +#define SYS_GPB_MFP0_PB1MFP_Msk (0x1ful << SYS_GPB_MFP0_PB1MFP_Pos) /*!< SYS_T::GPB_MFP0: PB1MFP Mask */ + +#define SYS_GPB_MFP0_PB2MFP_Pos (16) /*!< SYS_T::GPB_MFP0: PB2MFP Position */ +#define SYS_GPB_MFP0_PB2MFP_Msk (0x1ful << SYS_GPB_MFP0_PB2MFP_Pos) /*!< SYS_T::GPB_MFP0: PB2MFP Mask */ + +#define SYS_GPB_MFP0_PB3MFP_Pos (24) /*!< SYS_T::GPB_MFP0: PB3MFP Position */ +#define SYS_GPB_MFP0_PB3MFP_Msk (0x1ful << SYS_GPB_MFP0_PB3MFP_Pos) /*!< SYS_T::GPB_MFP0: PB3MFP Mask */ + +#define SYS_GPB_MFP1_PB4MFP_Pos (0) /*!< SYS_T::GPB_MFP1: PB4MFP Position */ +#define SYS_GPB_MFP1_PB4MFP_Msk (0x1ful << SYS_GPB_MFP1_PB4MFP_Pos) /*!< SYS_T::GPB_MFP1: PB4MFP Mask */ + +#define SYS_GPB_MFP1_PB5MFP_Pos (8) /*!< SYS_T::GPB_MFP1: PB5MFP Position */ +#define SYS_GPB_MFP1_PB5MFP_Msk (0x1ful << SYS_GPB_MFP1_PB5MFP_Pos) /*!< SYS_T::GPB_MFP1: PB5MFP Mask */ + +#define SYS_GPB_MFP1_PB6MFP_Pos (16) /*!< SYS_T::GPB_MFP1: PB6MFP Position */ +#define SYS_GPB_MFP1_PB6MFP_Msk (0x1ful << SYS_GPB_MFP1_PB6MFP_Pos) /*!< SYS_T::GPB_MFP1: PB6MFP Mask */ + +#define SYS_GPB_MFP1_PB7MFP_Pos (24) /*!< SYS_T::GPB_MFP1: PB7MFP Position */ +#define SYS_GPB_MFP1_PB7MFP_Msk (0x1ful << SYS_GPB_MFP1_PB7MFP_Pos) /*!< SYS_T::GPB_MFP1: PB7MFP Mask */ + +#define SYS_GPB_MFP2_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFP2: PB8MFP Position */ +#define SYS_GPB_MFP2_PB8MFP_Msk (0x1ful << SYS_GPB_MFP2_PB8MFP_Pos) /*!< SYS_T::GPB_MFP2: PB8MFP Mask */ + +#define SYS_GPB_MFP2_PB9MFP_Pos (8) /*!< SYS_T::GPB_MFP2: PB9MFP Position */ +#define SYS_GPB_MFP2_PB9MFP_Msk (0x1ful << SYS_GPB_MFP2_PB9MFP_Pos) /*!< SYS_T::GPB_MFP2: PB9MFP Mask */ + +#define SYS_GPB_MFP2_PB10MFP_Pos (16) /*!< SYS_T::GPB_MFP2: PB10MFP Position */ +#define SYS_GPB_MFP2_PB10MFP_Msk (0x1ful << SYS_GPB_MFP2_PB10MFP_Pos) /*!< SYS_T::GPB_MFP2: PB10MFP Mask */ + +#define SYS_GPB_MFP2_PB11MFP_Pos (24) /*!< SYS_T::GPB_MFP2: PB11MFP Position */ +#define SYS_GPB_MFP2_PB11MFP_Msk (0x1ful << SYS_GPB_MFP2_PB11MFP_Pos) /*!< SYS_T::GPB_MFP2: PB11MFP Mask */ + +#define SYS_GPB_MFP3_PB12MFP_Pos (0) /*!< SYS_T::GPB_MFP3: PB12MFP Position */ +#define SYS_GPB_MFP3_PB12MFP_Msk (0x1ful << SYS_GPB_MFP3_PB12MFP_Pos) /*!< SYS_T::GPB_MFP3: PB12MFP Mask */ + +#define SYS_GPB_MFP3_PB13MFP_Pos (8) /*!< SYS_T::GPB_MFP3: PB13MFP Position */ +#define SYS_GPB_MFP3_PB13MFP_Msk (0x1ful << SYS_GPB_MFP3_PB13MFP_Pos) /*!< SYS_T::GPB_MFP3: PB13MFP Mask */ + +#define SYS_GPB_MFP3_PB14MFP_Pos (16) /*!< SYS_T::GPB_MFP3: PB14MFP Position */ +#define SYS_GPB_MFP3_PB14MFP_Msk (0x1ful << SYS_GPB_MFP3_PB14MFP_Pos) /*!< SYS_T::GPB_MFP3: PB14MFP Mask */ + +#define SYS_GPB_MFP3_PB15MFP_Pos (24) /*!< SYS_T::GPB_MFP3: PB15MFP Position */ +#define SYS_GPB_MFP3_PB15MFP_Msk (0x1ful << SYS_GPB_MFP3_PB15MFP_Pos) /*!< SYS_T::GPB_MFP3: PB15MFP Mask */ + +#define SYS_GPC_MFP0_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFP0: PC0MFP Position */ +#define SYS_GPC_MFP0_PC0MFP_Msk (0x1ful << SYS_GPC_MFP0_PC0MFP_Pos) /*!< SYS_T::GPC_MFP0: PC0MFP Mask */ + +#define SYS_GPC_MFP0_PC1MFP_Pos (8) /*!< SYS_T::GPC_MFP0: PC1MFP Position */ +#define SYS_GPC_MFP0_PC1MFP_Msk (0x1ful << SYS_GPC_MFP0_PC1MFP_Pos) /*!< SYS_T::GPC_MFP0: PC1MFP Mask */ + +#define SYS_GPC_MFP0_PC2MFP_Pos (16) /*!< SYS_T::GPC_MFP0: PC2MFP Position */ +#define SYS_GPC_MFP0_PC2MFP_Msk (0x1ful << SYS_GPC_MFP0_PC2MFP_Pos) /*!< SYS_T::GPC_MFP0: PC2MFP Mask */ + +#define SYS_GPC_MFP0_PC3MFP_Pos (24) /*!< SYS_T::GPC_MFP0: PC3MFP Position */ +#define SYS_GPC_MFP0_PC3MFP_Msk (0x1ful << SYS_GPC_MFP0_PC3MFP_Pos) /*!< SYS_T::GPC_MFP0: PC3MFP Mask */ + +#define SYS_GPC_MFP1_PC4MFP_Pos (0) /*!< SYS_T::GPC_MFP1: PC4MFP Position */ +#define SYS_GPC_MFP1_PC4MFP_Msk (0x1ful << SYS_GPC_MFP1_PC4MFP_Pos) /*!< SYS_T::GPC_MFP1: PC4MFP Mask */ + +#define SYS_GPC_MFP1_PC5MFP_Pos (8) /*!< SYS_T::GPC_MFP1: PC5MFP Position */ +#define SYS_GPC_MFP1_PC5MFP_Msk (0x1ful << SYS_GPC_MFP1_PC5MFP_Pos) /*!< SYS_T::GPC_MFP1: PC5MFP Mask */ + +#define SYS_GPC_MFP1_PC6MFP_Pos (16) /*!< SYS_T::GPC_MFP1: PC6MFP Position */ +#define SYS_GPC_MFP1_PC6MFP_Msk (0x1ful << SYS_GPC_MFP1_PC6MFP_Pos) /*!< SYS_T::GPC_MFP1: PC6MFP Mask */ + +#define SYS_GPC_MFP1_PC7MFP_Pos (24) /*!< SYS_T::GPC_MFP1: PC7MFP Position */ +#define SYS_GPC_MFP1_PC7MFP_Msk (0x1ful << SYS_GPC_MFP1_PC7MFP_Pos) /*!< SYS_T::GPC_MFP1: PC7MFP Mask */ + +#define SYS_GPC_MFP2_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFP2: PC8MFP Position */ +#define SYS_GPC_MFP2_PC8MFP_Msk (0x1ful << SYS_GPC_MFP2_PC8MFP_Pos) /*!< SYS_T::GPC_MFP2: PC8MFP Mask */ + +#define SYS_GPC_MFP2_PC9MFP_Pos (8) /*!< SYS_T::GPC_MFP2: PC9MFP Position */ +#define SYS_GPC_MFP2_PC9MFP_Msk (0x1ful << SYS_GPC_MFP2_PC9MFP_Pos) /*!< SYS_T::GPC_MFP2: PC9MFP Mask */ + +#define SYS_GPC_MFP2_PC10MFP_Pos (16) /*!< SYS_T::GPC_MFP2: PC10MFP Position */ +#define SYS_GPC_MFP2_PC10MFP_Msk (0x1ful << SYS_GPC_MFP2_PC10MFP_Pos) /*!< SYS_T::GPC_MFP2: PC10MFP Mask */ + +#define SYS_GPC_MFP2_PC11MFP_Pos (24) /*!< SYS_T::GPC_MFP2: PC11MFP Position */ +#define SYS_GPC_MFP2_PC11MFP_Msk (0x1ful << SYS_GPC_MFP2_PC11MFP_Pos) /*!< SYS_T::GPC_MFP2: PC11MFP Mask */ + +#define SYS_GPC_MFP3_PC12MFP_Pos (0) /*!< SYS_T::GPC_MFP3: PC12MFP Position */ +#define SYS_GPC_MFP3_PC12MFP_Msk (0x1ful << SYS_GPC_MFP3_PC12MFP_Pos) /*!< SYS_T::GPC_MFP3: PC12MFP Mask */ + +#define SYS_GPC_MFP3_PC13MFP_Pos (8) /*!< SYS_T::GPC_MFP3: PC13MFP Position */ +#define SYS_GPC_MFP3_PC13MFP_Msk (0x1ful << SYS_GPC_MFP3_PC13MFP_Pos) /*!< SYS_T::GPC_MFP3: PC13MFP Mask */ + +#define SYS_GPC_MFP3_PC14MFP_Pos (16) /*!< SYS_T::GPC_MFP3: PC14MFP Position */ +#define SYS_GPC_MFP3_PC14MFP_Msk (0x1ful << SYS_GPC_MFP3_PC14MFP_Pos) /*!< SYS_T::GPC_MFP3: PC14MFP Mask */ + +#define SYS_GPD_MFP0_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFP0: PD0MFP Position */ +#define SYS_GPD_MFP0_PD0MFP_Msk (0x1ful << SYS_GPD_MFP0_PD0MFP_Pos) /*!< SYS_T::GPD_MFP0: PD0MFP Mask */ + +#define SYS_GPD_MFP0_PD1MFP_Pos (8) /*!< SYS_T::GPD_MFP0: PD1MFP Position */ +#define SYS_GPD_MFP0_PD1MFP_Msk (0x1ful << SYS_GPD_MFP0_PD1MFP_Pos) /*!< SYS_T::GPD_MFP0: PD1MFP Mask */ + +#define SYS_GPD_MFP0_PD2MFP_Pos (16) /*!< SYS_T::GPD_MFP0: PD2MFP Position */ +#define SYS_GPD_MFP0_PD2MFP_Msk (0x1ful << SYS_GPD_MFP0_PD2MFP_Pos) /*!< SYS_T::GPD_MFP0: PD2MFP Mask */ + +#define SYS_GPD_MFP0_PD3MFP_Pos (24) /*!< SYS_T::GPD_MFP0: PD3MFP Position */ +#define SYS_GPD_MFP0_PD3MFP_Msk (0x1ful << SYS_GPD_MFP0_PD3MFP_Pos) /*!< SYS_T::GPD_MFP0: PD3MFP Mask */ + +#define SYS_GPD_MFP1_PD4MFP_Pos (0) /*!< SYS_T::GPD_MFP1: PD4MFP Position */ +#define SYS_GPD_MFP1_PD4MFP_Msk (0x1ful << SYS_GPD_MFP1_PD4MFP_Pos) /*!< SYS_T::GPD_MFP1: PD4MFP Mask */ + +#define SYS_GPD_MFP1_PD5MFP_Pos (8) /*!< SYS_T::GPD_MFP1: PD5MFP Position */ +#define SYS_GPD_MFP1_PD5MFP_Msk (0x1ful << SYS_GPD_MFP1_PD5MFP_Pos) /*!< SYS_T::GPD_MFP1: PD5MFP Mask */ + +#define SYS_GPD_MFP1_PD6MFP_Pos (16) /*!< SYS_T::GPD_MFP1: PD6MFP Position */ +#define SYS_GPD_MFP1_PD6MFP_Msk (0x1ful << SYS_GPD_MFP1_PD6MFP_Pos) /*!< SYS_T::GPD_MFP1: PD6MFP Mask */ + +#define SYS_GPD_MFP1_PD7MFP_Pos (24) /*!< SYS_T::GPD_MFP1: PD7MFP Position */ +#define SYS_GPD_MFP1_PD7MFP_Msk (0x1ful << SYS_GPD_MFP1_PD7MFP_Pos) /*!< SYS_T::GPD_MFP1: PD7MFP Mask */ + +#define SYS_GPD_MFP2_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFP2: PD8MFP Position */ +#define SYS_GPD_MFP2_PD8MFP_Msk (0x1ful << SYS_GPD_MFP2_PD8MFP_Pos) /*!< SYS_T::GPD_MFP2: PD8MFP Mask */ + +#define SYS_GPD_MFP2_PD9MFP_Pos (8) /*!< SYS_T::GPD_MFP2: PD9MFP Position */ +#define SYS_GPD_MFP2_PD9MFP_Msk (0x1ful << SYS_GPD_MFP2_PD9MFP_Pos) /*!< SYS_T::GPD_MFP2: PD9MFP Mask */ + +#define SYS_GPD_MFP2_PD10MFP_Pos (16) /*!< SYS_T::GPD_MFP2: PD10MFP Position */ +#define SYS_GPD_MFP2_PD10MFP_Msk (0x1ful << SYS_GPD_MFP2_PD10MFP_Pos) /*!< SYS_T::GPD_MFP2: PD10MFP Mask */ + +#define SYS_GPD_MFP2_PD11MFP_Pos (24) /*!< SYS_T::GPD_MFP2: PD11MFP Position */ +#define SYS_GPD_MFP2_PD11MFP_Msk (0x1ful << SYS_GPD_MFP2_PD11MFP_Pos) /*!< SYS_T::GPD_MFP2: PD11MFP Mask */ + +#define SYS_GPD_MFP3_PD12MFP_Pos (0) /*!< SYS_T::GPD_MFP3: PD12MFP Position */ +#define SYS_GPD_MFP3_PD12MFP_Msk (0x1ful << SYS_GPD_MFP3_PD12MFP_Pos) /*!< SYS_T::GPD_MFP3: PD12MFP Mask */ + +#define SYS_GPD_MFP3_PD13MFP_Pos (8) /*!< SYS_T::GPD_MFP3: PD13MFP Position */ +#define SYS_GPD_MFP3_PD13MFP_Msk (0x1ful << SYS_GPD_MFP3_PD13MFP_Pos) /*!< SYS_T::GPD_MFP3: PD13MFP Mask */ + +#define SYS_GPD_MFP3_PD14MFP_Pos (16) /*!< SYS_T::GPD_MFP3: PD14MFP Position */ +#define SYS_GPD_MFP3_PD14MFP_Msk (0x1ful << SYS_GPD_MFP3_PD14MFP_Pos) /*!< SYS_T::GPD_MFP3: PD14MFP Mask */ + +#define SYS_GPE_MFP0_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFP0: PE0MFP Position */ +#define SYS_GPE_MFP0_PE0MFP_Msk (0x1ful << SYS_GPE_MFP0_PE0MFP_Pos) /*!< SYS_T::GPE_MFP0: PE0MFP Mask */ + +#define SYS_GPE_MFP0_PE1MFP_Pos (8) /*!< SYS_T::GPE_MFP0: PE1MFP Position */ +#define SYS_GPE_MFP0_PE1MFP_Msk (0x1ful << SYS_GPE_MFP0_PE1MFP_Pos) /*!< SYS_T::GPE_MFP0: PE1MFP Mask */ + +#define SYS_GPE_MFP0_PE2MFP_Pos (16) /*!< SYS_T::GPE_MFP0: PE2MFP Position */ +#define SYS_GPE_MFP0_PE2MFP_Msk (0x1ful << SYS_GPE_MFP0_PE2MFP_Pos) /*!< SYS_T::GPE_MFP0: PE2MFP Mask */ + +#define SYS_GPE_MFP0_PE3MFP_Pos (24) /*!< SYS_T::GPE_MFP0: PE3MFP Position */ +#define SYS_GPE_MFP0_PE3MFP_Msk (0x1ful << SYS_GPE_MFP0_PE3MFP_Pos) /*!< SYS_T::GPE_MFP0: PE3MFP Mask */ + +#define SYS_GPE_MFP1_PE4MFP_Pos (0) /*!< SYS_T::GPE_MFP1: PE4MFP Position */ +#define SYS_GPE_MFP1_PE4MFP_Msk (0x1ful << SYS_GPE_MFP1_PE4MFP_Pos) /*!< SYS_T::GPE_MFP1: PE4MFP Mask */ + +#define SYS_GPE_MFP1_PE5MFP_Pos (8) /*!< SYS_T::GPE_MFP1: PE5MFP Position */ +#define SYS_GPE_MFP1_PE5MFP_Msk (0x1ful << SYS_GPE_MFP1_PE5MFP_Pos) /*!< SYS_T::GPE_MFP1: PE5MFP Mask */ + +#define SYS_GPE_MFP1_PE6MFP_Pos (16) /*!< SYS_T::GPE_MFP1: PE6MFP Position */ +#define SYS_GPE_MFP1_PE6MFP_Msk (0x1ful << SYS_GPE_MFP1_PE6MFP_Pos) /*!< SYS_T::GPE_MFP1: PE6MFP Mask */ + +#define SYS_GPE_MFP1_PE7MFP_Pos (24) /*!< SYS_T::GPE_MFP1: PE7MFP Position */ +#define SYS_GPE_MFP1_PE7MFP_Msk (0x1ful << SYS_GPE_MFP1_PE7MFP_Pos) /*!< SYS_T::GPE_MFP1: PE7MFP Mask */ + +#define SYS_GPE_MFP2_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFP2: PE8MFP Position */ +#define SYS_GPE_MFP2_PE8MFP_Msk (0x1ful << SYS_GPE_MFP2_PE8MFP_Pos) /*!< SYS_T::GPE_MFP2: PE8MFP Mask */ + +#define SYS_GPE_MFP2_PE9MFP_Pos (8) /*!< SYS_T::GPE_MFP2: PE9MFP Position */ +#define SYS_GPE_MFP2_PE9MFP_Msk (0x1ful << SYS_GPE_MFP2_PE9MFP_Pos) /*!< SYS_T::GPE_MFP2: PE9MFP Mask */ + +#define SYS_GPE_MFP2_PE10MFP_Pos (16) /*!< SYS_T::GPE_MFP2: PE10MFP Position */ +#define SYS_GPE_MFP2_PE10MFP_Msk (0x1ful << SYS_GPE_MFP2_PE10MFP_Pos) /*!< SYS_T::GPE_MFP2: PE10MFP Mask */ + +#define SYS_GPE_MFP2_PE11MFP_Pos (24) /*!< SYS_T::GPE_MFP2: PE11MFP Position */ +#define SYS_GPE_MFP2_PE11MFP_Msk (0x1ful << SYS_GPE_MFP2_PE11MFP_Pos) /*!< SYS_T::GPE_MFP2: PE11MFP Mask */ + +#define SYS_GPE_MFP3_PE12MFP_Pos (0) /*!< SYS_T::GPE_MFP3: PE12MFP Position */ +#define SYS_GPE_MFP3_PE12MFP_Msk (0x1ful << SYS_GPE_MFP3_PE12MFP_Pos) /*!< SYS_T::GPE_MFP3: PE12MFP Mask */ + +#define SYS_GPE_MFP3_PE13MFP_Pos (8) /*!< SYS_T::GPE_MFP3: PE13MFP Position */ +#define SYS_GPE_MFP3_PE13MFP_Msk (0x1ful << SYS_GPE_MFP3_PE13MFP_Pos) /*!< SYS_T::GPE_MFP3: PE13MFP Mask */ + +#define SYS_GPE_MFP3_PE14MFP_Pos (16) /*!< SYS_T::GPE_MFP3: PE14MFP Position */ +#define SYS_GPE_MFP3_PE14MFP_Msk (0x1ful << SYS_GPE_MFP3_PE14MFP_Pos) /*!< SYS_T::GPE_MFP3: PE14MFP Mask */ + +#define SYS_GPE_MFP3_PE15MFP_Pos (24) /*!< SYS_T::GPE_MFP3: PE15MFP Position */ +#define SYS_GPE_MFP3_PE15MFP_Msk (0x1ful << SYS_GPE_MFP3_PE15MFP_Pos) /*!< SYS_T::GPE_MFP3: PE15MFP Mask */ + +#define SYS_GPF_MFP0_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFP0: PF0MFP Position */ +#define SYS_GPF_MFP0_PF0MFP_Msk (0x1ful << SYS_GPF_MFP0_PF0MFP_Pos) /*!< SYS_T::GPF_MFP0: PF0MFP Mask */ + +#define SYS_GPF_MFP0_PF1MFP_Pos (8) /*!< SYS_T::GPF_MFP0: PF1MFP Position */ +#define SYS_GPF_MFP0_PF1MFP_Msk (0x1ful << SYS_GPF_MFP0_PF1MFP_Pos) /*!< SYS_T::GPF_MFP0: PF1MFP Mask */ + +#define SYS_GPF_MFP0_PF2MFP_Pos (16) /*!< SYS_T::GPF_MFP0: PF2MFP Position */ +#define SYS_GPF_MFP0_PF2MFP_Msk (0x1ful << SYS_GPF_MFP0_PF2MFP_Pos) /*!< SYS_T::GPF_MFP0: PF2MFP Mask */ + +#define SYS_GPF_MFP0_PF3MFP_Pos (24) /*!< SYS_T::GPF_MFP0: PF3MFP Position */ +#define SYS_GPF_MFP0_PF3MFP_Msk (0x1ful << SYS_GPF_MFP0_PF3MFP_Pos) /*!< SYS_T::GPF_MFP0: PF3MFP Mask */ + +#define SYS_GPF_MFP1_PF4MFP_Pos (0) /*!< SYS_T::GPF_MFP1: PF4MFP Position */ +#define SYS_GPF_MFP1_PF4MFP_Msk (0x1ful << SYS_GPF_MFP1_PF4MFP_Pos) /*!< SYS_T::GPF_MFP1: PF4MFP Mask */ + +#define SYS_GPF_MFP1_PF5MFP_Pos (8) /*!< SYS_T::GPF_MFP1: PF5MFP Position */ +#define SYS_GPF_MFP1_PF5MFP_Msk (0x1ful << SYS_GPF_MFP1_PF5MFP_Pos) /*!< SYS_T::GPF_MFP1: PF5MFP Mask */ + +#define SYS_GPF_MFP1_PF6MFP_Pos (16) /*!< SYS_T::GPF_MFP1: PF6MFP Position */ +#define SYS_GPF_MFP1_PF6MFP_Msk (0x1ful << SYS_GPF_MFP1_PF6MFP_Pos) /*!< SYS_T::GPF_MFP1: PF6MFP Mask */ + +#define SYS_GPF_MFP1_PF7MFP_Pos (24) /*!< SYS_T::GPF_MFP1: PF7MFP Position */ +#define SYS_GPF_MFP1_PF7MFP_Msk (0x1ful << SYS_GPF_MFP1_PF7MFP_Pos) /*!< SYS_T::GPF_MFP1: PF7MFP Mask */ + +#define SYS_GPF_MFP2_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFP2: PF8MFP Position */ +#define SYS_GPF_MFP2_PF8MFP_Msk (0x1ful << SYS_GPF_MFP2_PF8MFP_Pos) /*!< SYS_T::GPF_MFP2: PF8MFP Mask */ + +#define SYS_GPF_MFP2_PF9MFP_Pos (8) /*!< SYS_T::GPF_MFP2: PF9MFP Position */ +#define SYS_GPF_MFP2_PF9MFP_Msk (0x1ful << SYS_GPF_MFP2_PF9MFP_Pos) /*!< SYS_T::GPF_MFP2: PF9MFP Mask */ + +#define SYS_GPF_MFP2_PF10MFP_Pos (16) /*!< SYS_T::GPF_MFP2: PF10MFP Position */ +#define SYS_GPF_MFP2_PF10MFP_Msk (0x1ful << SYS_GPF_MFP2_PF10MFP_Pos) /*!< SYS_T::GPF_MFP2: PF10MFP Mask */ + +#define SYS_GPF_MFP2_PF11MFP_Pos (24) /*!< SYS_T::GPF_MFP2: PF11MFP Position */ +#define SYS_GPF_MFP2_PF11MFP_Msk (0x1ful << SYS_GPF_MFP2_PF11MFP_Pos) /*!< SYS_T::GPF_MFP2: PF11MFP Mask */ + +#define SYS_GPG_MFP0_PG0MFP_Pos (0) /*!< SYS_T::GPG_MFP0: PG0MFP Position */ +#define SYS_GPG_MFP0_PG0MFP_Msk (0x1ful << SYS_GPG_MFP0_PG0MFP_Pos) /*!< SYS_T::GPG_MFP0: PG0MFP Mask */ + +#define SYS_GPG_MFP0_PG1MFP_Pos (8) /*!< SYS_T::GPG_MFP0: PG1MFP Position */ +#define SYS_GPG_MFP0_PG1MFP_Msk (0x1ful << SYS_GPG_MFP0_PG1MFP_Pos) /*!< SYS_T::GPG_MFP0: PG1MFP Mask */ + +#define SYS_GPG_MFP0_PG2MFP_Pos (16) /*!< SYS_T::GPG_MFP0: PG2MFP Position */ +#define SYS_GPG_MFP0_PG2MFP_Msk (0x1ful << SYS_GPG_MFP0_PG2MFP_Pos) /*!< SYS_T::GPG_MFP0: PG2MFP Mask */ + +#define SYS_GPG_MFP0_PG3MFP_Pos (24) /*!< SYS_T::GPG_MFP0: PG3MFP Position */ +#define SYS_GPG_MFP0_PG3MFP_Msk (0x1ful << SYS_GPG_MFP0_PG3MFP_Pos) /*!< SYS_T::GPG_MFP0: PG3MFP Mask */ + +#define SYS_GPG_MFP1_PG4MFP_Pos (0) /*!< SYS_T::GPG_MFP1: PG4MFP Position */ +#define SYS_GPG_MFP1_PG4MFP_Msk (0x1ful << SYS_GPG_MFP1_PG4MFP_Pos) /*!< SYS_T::GPG_MFP1: PG4MFP Mask */ + +#define SYS_GPG_MFP1_PG5MFP_Pos (8) /*!< SYS_T::GPG_MFP1: PG5MFP Position */ +#define SYS_GPG_MFP1_PG5MFP_Msk (0x1ful << SYS_GPG_MFP1_PG5MFP_Pos) /*!< SYS_T::GPG_MFP1: PG5MFP Mask */ + +#define SYS_GPG_MFP1_PG6MFP_Pos (16) /*!< SYS_T::GPG_MFP1: PG6MFP Position */ +#define SYS_GPG_MFP1_PG6MFP_Msk (0x1ful << SYS_GPG_MFP1_PG6MFP_Pos) /*!< SYS_T::GPG_MFP1: PG6MFP Mask */ + +#define SYS_GPG_MFP1_PG7MFP_Pos (24) /*!< SYS_T::GPG_MFP1: PG7MFP Position */ +#define SYS_GPG_MFP1_PG7MFP_Msk (0x1ful << SYS_GPG_MFP1_PG7MFP_Pos) /*!< SYS_T::GPG_MFP1: PG7MFP Mask */ + +#define SYS_GPG_MFP2_PG8MFP_Pos (0) /*!< SYS_T::GPG_MFP2: PG8MFP Position */ +#define SYS_GPG_MFP2_PG8MFP_Msk (0x1ful << SYS_GPG_MFP2_PG8MFP_Pos) /*!< SYS_T::GPG_MFP2: PG8MFP Mask */ + +#define SYS_GPG_MFP2_PG9MFP_Pos (8) /*!< SYS_T::GPG_MFP2: PG9MFP Position */ +#define SYS_GPG_MFP2_PG9MFP_Msk (0x1ful << SYS_GPG_MFP2_PG9MFP_Pos) /*!< SYS_T::GPG_MFP2: PG9MFP Mask */ + +#define SYS_GPG_MFP2_PG10MFP_Pos (16) /*!< SYS_T::GPG_MFP2: PG10MFP Position */ +#define SYS_GPG_MFP2_PG10MFP_Msk (0x1ful << SYS_GPG_MFP2_PG10MFP_Pos) /*!< SYS_T::GPG_MFP2: PG10MFP Mask */ + +#define SYS_GPG_MFP2_PG11MFP_Pos (24) /*!< SYS_T::GPG_MFP2: PG11MFP Position */ +#define SYS_GPG_MFP2_PG11MFP_Msk (0x1ful << SYS_GPG_MFP2_PG11MFP_Pos) /*!< SYS_T::GPG_MFP2: PG11MFP Mask */ + +#define SYS_GPG_MFP3_PG12MFP_Pos (0) /*!< SYS_T::GPG_MFP3: PG12MFP Position */ +#define SYS_GPG_MFP3_PG12MFP_Msk (0x1ful << SYS_GPG_MFP3_PG12MFP_Pos) /*!< SYS_T::GPG_MFP3: PG12MFP Mask */ + +#define SYS_GPG_MFP3_PG13MFP_Pos (8) /*!< SYS_T::GPG_MFP3: PG13MFP Position */ +#define SYS_GPG_MFP3_PG13MFP_Msk (0x1ful << SYS_GPG_MFP3_PG13MFP_Pos) /*!< SYS_T::GPG_MFP3: PG13MFP Mask */ + +#define SYS_GPG_MFP3_PG14MFP_Pos (16) /*!< SYS_T::GPG_MFP3: PG14MFP Position */ +#define SYS_GPG_MFP3_PG14MFP_Msk (0x1ful << SYS_GPG_MFP3_PG14MFP_Pos) /*!< SYS_T::GPG_MFP3: PG14MFP Mask */ + +#define SYS_GPG_MFP3_PG15MFP_Pos (24) /*!< SYS_T::GPG_MFP3: PG15MFP Position */ +#define SYS_GPG_MFP3_PG15MFP_Msk (0x1ful << SYS_GPG_MFP3_PG15MFP_Pos) /*!< SYS_T::GPG_MFP3: PG15MFP Mask */ + +#define SYS_GPH_MFP0_PH0MFP_Pos (0) /*!< SYS_T::GPH_MFP0: PH0MFP Position */ +#define SYS_GPH_MFP0_PH0MFP_Msk (0x1ful << SYS_GPH_MFP0_PH0MFP_Pos) /*!< SYS_T::GPH_MFP0: PH0MFP Mask */ + +#define SYS_GPH_MFP0_PH1MFP_Pos (8) /*!< SYS_T::GPH_MFP0: PH1MFP Position */ +#define SYS_GPH_MFP0_PH1MFP_Msk (0x1ful << SYS_GPH_MFP0_PH1MFP_Pos) /*!< SYS_T::GPH_MFP0: PH1MFP Mask */ + +#define SYS_GPH_MFP0_PH2MFP_Pos (16) /*!< SYS_T::GPH_MFP0: PH2MFP Position */ +#define SYS_GPH_MFP0_PH2MFP_Msk (0x1ful << SYS_GPH_MFP0_PH2MFP_Pos) /*!< SYS_T::GPH_MFP0: PH2MFP Mask */ + +#define SYS_GPH_MFP0_PH3MFP_Pos (24) /*!< SYS_T::GPH_MFP0: PH3MFP Position */ +#define SYS_GPH_MFP0_PH3MFP_Msk (0x1ful << SYS_GPH_MFP0_PH3MFP_Pos) /*!< SYS_T::GPH_MFP0: PH3MFP Mask */ + +#define SYS_GPH_MFP1_PH4MFP_Pos (0) /*!< SYS_T::GPH_MFP1: PH4MFP Position */ +#define SYS_GPH_MFP1_PH4MFP_Msk (0x1ful << SYS_GPH_MFP1_PH4MFP_Pos) /*!< SYS_T::GPH_MFP1: PH4MFP Mask */ + +#define SYS_GPH_MFP1_PH5MFP_Pos (8) /*!< SYS_T::GPH_MFP1: PH5MFP Position */ +#define SYS_GPH_MFP1_PH5MFP_Msk (0x1ful << SYS_GPH_MFP1_PH5MFP_Pos) /*!< SYS_T::GPH_MFP1: PH5MFP Mask */ + +#define SYS_GPH_MFP1_PH6MFP_Pos (16) /*!< SYS_T::GPH_MFP1: PH6MFP Position */ +#define SYS_GPH_MFP1_PH6MFP_Msk (0x1ful << SYS_GPH_MFP1_PH6MFP_Pos) /*!< SYS_T::GPH_MFP1: PH6MFP Mask */ + +#define SYS_GPH_MFP1_PH7MFP_Pos (24) /*!< SYS_T::GPH_MFP1: PH7MFP Position */ +#define SYS_GPH_MFP1_PH7MFP_Msk (0x1ful << SYS_GPH_MFP1_PH7MFP_Pos) /*!< SYS_T::GPH_MFP1: PH7MFP Mask */ + +#define SYS_GPH_MFP2_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFP2: PH8MFP Position */ +#define SYS_GPH_MFP2_PH8MFP_Msk (0x1ful << SYS_GPH_MFP2_PH8MFP_Pos) /*!< SYS_T::GPH_MFP2: PH8MFP Mask */ + +#define SYS_GPH_MFP2_PH9MFP_Pos (8) /*!< SYS_T::GPH_MFP2: PH9MFP Position */ +#define SYS_GPH_MFP2_PH9MFP_Msk (0x1ful << SYS_GPH_MFP2_PH9MFP_Pos) /*!< SYS_T::GPH_MFP2: PH9MFP Mask */ + +#define SYS_GPH_MFP2_PH10MFP_Pos (16) /*!< SYS_T::GPH_MFP2: PH10MFP Position */ +#define SYS_GPH_MFP2_PH10MFP_Msk (0x1ful << SYS_GPH_MFP2_PH10MFP_Pos) /*!< SYS_T::GPH_MFP2: PH10MFP Mask */ + +#define SYS_GPH_MFP2_PH11MFP_Pos (24) /*!< SYS_T::GPH_MFP2: PH11MFP Position */ +#define SYS_GPH_MFP2_PH11MFP_Msk (0x1ful << SYS_GPH_MFP2_PH11MFP_Pos) /*!< SYS_T::GPH_MFP2: PH11MFP Mask */ + +#define SYS_GPH_MFP3_PH12MFP_Pos (0) /*!< SYS_T::GPH_MFP3: PH12MFP Position */ +#define SYS_GPH_MFP3_PH12MFP_Msk (0x1ful << SYS_GPH_MFP3_PH12MFP_Pos) /*!< SYS_T::GPH_MFP3: PH12MFP Mask */ + +#define SYS_GPH_MFP3_PH13MFP_Pos (8) /*!< SYS_T::GPH_MFP3: PH13MFP Position */ +#define SYS_GPH_MFP3_PH13MFP_Msk (0x1ful << SYS_GPH_MFP3_PH13MFP_Pos) /*!< SYS_T::GPH_MFP3: PH13MFP Mask */ + +#define SYS_GPH_MFP3_PH14MFP_Pos (16) /*!< SYS_T::GPH_MFP3: PH14MFP Position */ +#define SYS_GPH_MFP3_PH14MFP_Msk (0x1ful << SYS_GPH_MFP3_PH14MFP_Pos) /*!< SYS_T::GPH_MFP3: PH14MFP Mask */ + +#define SYS_GPH_MFP3_PH15MFP_Pos (24) /*!< SYS_T::GPH_MFP3: PH15MFP Position */ +#define SYS_GPH_MFP3_PH15MFP_Msk (0x1ful << SYS_GPH_MFP3_PH15MFP_Pos) /*!< SYS_T::GPH_MFP3: PH15MFP Mask */ + +#define SYS_GPI_MFP1_PI6MFP_Pos (16) /*!< SYS_T::GPI_MFP1: PI6MFP Position */ +#define SYS_GPI_MFP1_PI6MFP_Msk (0x1ful << SYS_GPI_MFP1_PI6MFP_Pos) /*!< SYS_T::GPI_MFP1: PI6MFP Mask */ + +#define SYS_GPI_MFP1_PI7MFP_Pos (24) /*!< SYS_T::GPI_MFP1: PI7MFP Position */ +#define SYS_GPI_MFP1_PI7MFP_Msk (0x1ful << SYS_GPI_MFP1_PI7MFP_Pos) /*!< SYS_T::GPI_MFP1: PI7MFP Mask */ + +#define SYS_GPI_MFP2_PI8MFP_Pos (0) /*!< SYS_T::GPI_MFP2: PI8MFP Position */ +#define SYS_GPI_MFP2_PI8MFP_Msk (0x1ful << SYS_GPI_MFP2_PI8MFP_Pos) /*!< SYS_T::GPI_MFP2: PI8MFP Mask */ + +#define SYS_GPI_MFP2_PI9MFP_Pos (8) /*!< SYS_T::GPI_MFP2: PI9MFP Position */ +#define SYS_GPI_MFP2_PI9MFP_Msk (0x1ful << SYS_GPI_MFP2_PI9MFP_Pos) /*!< SYS_T::GPI_MFP2: PI9MFP Mask */ + +#define SYS_GPI_MFP2_PI10MFP_Pos (16) /*!< SYS_T::GPI_MFP2: PI10MFP Position */ +#define SYS_GPI_MFP2_PI10MFP_Msk (0x1ful << SYS_GPI_MFP2_PI10MFP_Pos) /*!< SYS_T::GPI_MFP2: PI10MFP Mask */ + +#define SYS_GPI_MFP2_PI11MFP_Pos (24) /*!< SYS_T::GPI_MFP2: PI11MFP Position */ +#define SYS_GPI_MFP2_PI11MFP_Msk (0x1ful << SYS_GPI_MFP2_PI11MFP_Pos) /*!< SYS_T::GPI_MFP2: PI11MFP Mask */ + +#define SYS_GPI_MFP3_PI12MFP_Pos (0) /*!< SYS_T::GPI_MFP3: PI12MFP Position */ +#define SYS_GPI_MFP3_PI12MFP_Msk (0x1ful << SYS_GPI_MFP3_PI12MFP_Pos) /*!< SYS_T::GPI_MFP3: PI12MFP Mask */ + +#define SYS_GPI_MFP3_PI13MFP_Pos (8) /*!< SYS_T::GPI_MFP3: PI13MFP Position */ +#define SYS_GPI_MFP3_PI13MFP_Msk (0x1ful << SYS_GPI_MFP3_PI13MFP_Pos) /*!< SYS_T::GPI_MFP3: PI13MFP Mask */ + +#define SYS_GPI_MFP3_PI14MFP_Pos (16) /*!< SYS_T::GPI_MFP3: PI14MFP Position */ +#define SYS_GPI_MFP3_PI14MFP_Msk (0x1ful << SYS_GPI_MFP3_PI14MFP_Pos) /*!< SYS_T::GPI_MFP3: PI14MFP Mask */ + +#define SYS_GPI_MFP3_PI15MFP_Pos (24) /*!< SYS_T::GPI_MFP3: PI15MFP Position */ +#define SYS_GPI_MFP3_PI15MFP_Msk (0x1ful << SYS_GPI_MFP3_PI15MFP_Pos) /*!< SYS_T::GPI_MFP3: PI15MFP Mask */ + +#define SYS_GPJ_MFP0_PJ0MFP_Pos (0) /*!< SYS_T::GPJ_MFP0: PJ0MFP Position */ +#define SYS_GPJ_MFP0_PJ0MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ0MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ0MFP Mask */ + +#define SYS_GPJ_MFP0_PJ1MFP_Pos (8) /*!< SYS_T::GPJ_MFP0: PJ1MFP Position */ +#define SYS_GPJ_MFP0_PJ1MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ1MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ1MFP Mask */ + +#define SYS_GPJ_MFP0_PJ2MFP_Pos (16) /*!< SYS_T::GPJ_MFP0: PJ2MFP Position */ +#define SYS_GPJ_MFP0_PJ2MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ2MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ2MFP Mask */ + +#define SYS_GPJ_MFP0_PJ3MFP_Pos (24) /*!< SYS_T::GPJ_MFP0: PJ3MFP Position */ +#define SYS_GPJ_MFP0_PJ3MFP_Msk (0x1ful << SYS_GPJ_MFP0_PJ3MFP_Pos) /*!< SYS_T::GPJ_MFP0: PJ3MFP Mask */ + +#define SYS_GPJ_MFP1_PJ4MFP_Pos (0) /*!< SYS_T::GPJ_MFP1: PJ4MFP Position */ +#define SYS_GPJ_MFP1_PJ4MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ4MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ4MFP Mask */ + +#define SYS_GPJ_MFP1_PJ5MFP_Pos (8) /*!< SYS_T::GPJ_MFP1: PJ5MFP Position */ +#define SYS_GPJ_MFP1_PJ5MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ5MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ5MFP Mask */ + +#define SYS_GPJ_MFP1_PJ6MFP_Pos (16) /*!< SYS_T::GPJ_MFP1: PJ6MFP Position */ +#define SYS_GPJ_MFP1_PJ6MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ6MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ6MFP Mask */ + +#define SYS_GPJ_MFP1_PJ7MFP_Pos (24) /*!< SYS_T::GPJ_MFP1: PJ7MFP Position */ +#define SYS_GPJ_MFP1_PJ7MFP_Msk (0x1ful << SYS_GPJ_MFP1_PJ7MFP_Pos) /*!< SYS_T::GPJ_MFP1: PJ7MFP Mask */ + +#define SYS_GPJ_MFP2_PJ8MFP_Pos (0) /*!< SYS_T::GPJ_MFP2: PJ8MFP Position */ +#define SYS_GPJ_MFP2_PJ8MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ8MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ8MFP Mask */ + +#define SYS_GPJ_MFP2_PJ9MFP_Pos (8) /*!< SYS_T::GPJ_MFP2: PJ9MFP Position */ +#define SYS_GPJ_MFP2_PJ9MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ9MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ9MFP Mask */ + +#define SYS_GPJ_MFP2_PJ10MFP_Pos (16) /*!< SYS_T::GPJ_MFP2: PJ10MFP Position */ +#define SYS_GPJ_MFP2_PJ10MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ10MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ10MFP Mask */ + +#define SYS_GPJ_MFP2_PJ11MFP_Pos (24) /*!< SYS_T::GPJ_MFP2: PJ11MFP Position */ +#define SYS_GPJ_MFP2_PJ11MFP_Msk (0x1ful << SYS_GPJ_MFP2_PJ11MFP_Pos) /*!< SYS_T::GPJ_MFP2: PJ11MFP Mask */ + +#define SYS_GPJ_MFP3_PJ12MFP_Pos (0) /*!< SYS_T::GPJ_MFP3: PJ12MFP Position */ +#define SYS_GPJ_MFP3_PJ12MFP_Msk (0x1ful << SYS_GPJ_MFP3_PJ12MFP_Pos) /*!< SYS_T::GPJ_MFP3: PJ12MFP Mask */ + +#define SYS_GPJ_MFP3_PJ13MFP_Pos (8) /*!< SYS_T::GPJ_MFP3: PJ13MFP Position */ +#define SYS_GPJ_MFP3_PJ13MFP_Msk (0x1ful << SYS_GPJ_MFP3_PJ13MFP_Pos) /*!< SYS_T::GPJ_MFP3: PJ13MFP Mask */ + +/**@}*/ /* SYS_CONST */ +/**@}*/ /* end of SYS register group */ + +/** + @addtogroup NMI NMI Controller (NMI) + Memory Mapped Structure for NMI Controller +@{ */ + +typedef struct +{ + + + /** + * @var NMI_T::NMIEN + * Offset: 0x00 NMI Source Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) + * | | |0 = BOD NMI source Disabled. + * | | |1 = BOD NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |IRCINT |IRC TRIM NMI Source Enable (Write Protect) + * | | |0 = IRC TRIM NMI source Disabled. + * | | |1 = IRC TRIM NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PWRWUINT |Power-down Mode Wake-up NMI Source Enable (Write Protect) + * | | |0 = Power-down mode wake-up NMI source Disabled. + * | | |1 = Power-down mode wake-up NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |SRAMPERR |SRAM Parity Check NMI Source Enable (Write Protect) + * | | |0 = SRAM parity check error NMI source Disabled. + * | | |1 = SRAM parity check error NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CLKFAIL |Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect) + * | | |0 = Clock fail detected interrupt NMI source Disabled. + * | | |1 = Clock fail detected interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |RTCINT |RTC NMI Source Enable (Write Protect) + * | | |0 = RTC NMI source Disabled. + * | | |1 = RTC NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |TAMPERINT |TAMPER NMI Source Enable (Write Protect) + * | | |0 = Backup register tamper detected NMI source Disabled. + * | | |1 = Backup register tamper detected NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |EINT0 |External Interrupt from INT0 Pins NMI Source Enable (Write Protect) + * | | |0 = External interrupt from INT0 pins NMI source Disabled. + * | | |1 = External interrupt from INT0 pins NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |EINT1 |External Interrupt from INT1 Pins NMI Source Enable (Write Protect) + * | | |0 = External interrupt from INT1 pins NMI source Disabled. + * | | |1 = External interrupt from INT1 pins NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |EINT2 |External Interrupt rrom INT2 Pins NMI Source Enable (Write Protect) + * | | |0 = External interrupt from INT2 pins NMI source Disabled. + * | | |1 = External interrupt from INT2 pins NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11] |EINT3 |External Interrupt from INT3 Pins NMI Source Enable (Write Protect) + * | | |0 = External interrupt from INT3 pins NMI source Disabled. + * | | |1 = External interrupt from INT3 pins pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |EINT4 |External Interrupt from INT4 Pins NMI Source Enable (Write Protect) + * | | |0 = External interrupt from INT4 pins NMI source Disabled. + * | | |1 = External interrupt from INT4 pins NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |EINT5 |External Interrupt from INT5 Pins NMI Source Enable (Write Protect) + * | | |0 = External interrupt from INT5 pins NMI source Disabled. + * | | |1 = External interrupt from INT5 pins NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |UART0INT |UART0 NMI Source Enable (Write Protect) + * | | |0 = UART0 NMI source Disabled. + * | | |1 = UART0 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15] |UART1INT |UART1 NMI Source Enable (Write Protect) + * | | |0 = UART1 NMI source Disabled. + * | | |1 = UART1 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var NMI_T::NMISTS + * Offset: 0x04 NMI Source Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD Interrupt Flag (Read Only) + * | | |0 = BOD interrupt is deasserted. + * | | |1 = BOD interrupt is asserted. + * |[1] |IRCINT |IRC TRIM Interrupt Flag (Read Only) + * | | |0 = IRC TRIM interrupt is deasserted. + * | | |1 = IRC TRIM interrupt is asserted. + * |[2] |PWRWUINT |Power-down Mode Wake-up Interrupt Flag (Read Only) + * | | |0 = Power-down mode wake-up interrupt is deasserted. + * | | |1 = Power-down mode wake-up interrupt is asserted. + * |[3] |SRAMPERR |SRAM Parity Check Error Interrupt Flag (Read Only) + * | | |0 = SRAM parity check error interrupt is deasserted. + * | | |1 = SRAM parity check error interrupt is asserted. + * |[4] |CLKFAIL |Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only) + * | | |0 = Clock fail detected interrupt is deasserted. + * | | |1 = Clock fail detected interrupt is asserted. + * |[6] |RTCINT |RTC Interrupt Flag (Read Only) + * | | |0 = RTC interrupt is deasserted. + * | | |1 = RTC interrupt is asserted. + * |[7] |TAMPERINT |TAMPER Interrupt Flag (Read Only) + * | | |0 = Backup register tamper detected interrupt is deasserted. + * | | |1 = Backup register tamper detected interrupt is asserted. + * |[8] |EINT0 |External Interrupt from INT0 Pins Interrupt Flag (Read Only) + * | | |0 = External Interrupt from INT0 interrupt is deasserted. + * | | |1 = External Interrupt from INT0 interrupt is asserted. + * |[9] |EINT1 |External Interrupt from INT1 Pins Interrupt Flag (Read Only) + * | | |0 = External Interrupt from INT1 interrupt is deasserted. + * | | |1 = External Interrupt from INT1 interrupt is asserted. + * |[10] |EINT2 |External Interrupt from INT2 Pins Interrupt Flag (Read Only) + * | | |0 = External Interrupt from INT2 interrupt is deasserted. + * | | |1 = External Interrupt from INT2 interrupt is asserted. + * |[11] |EINT3 |External Interrupt from INT3 Pins Interrupt Flag (Read Only) + * | | |0 = External Interrupt from INT3 interrupt is deasserted. + * | | |1 = External Interrupt from INT3 interrupt is asserted. + * |[12] |EINT4 |External Interrupt from INT4 Pins Interrupt Flag (Read Only) + * | | |0 = External Interrupt from INT4 interrupt is deasserted. + * | | |1 = External Interrupt from INT4 interrupt is asserted. + * |[13] |EINT5 |External Interrupt from INT5 Pins Interrupt Flag (Read Only) + * | | |0 = External Interrupt from INT5 interrupt is deasserted. + * | | |1 = External Interrupt from INT5 interrupt is asserted. + * |[14] |UART0INT |UART0 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + * |[15] |UART1INT |UART1 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is deasserted. + * | | |1 = UART1 interrupt is asserted. + */ + __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ + __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ + +} NMI_T; + +/** + @addtogroup NMI_CONST NMI Bit Field Definition + Constant Definitions for NMI Controller +@{ */ + +#define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ +#define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ + +#define NMI_NMIEN_IRCINT_Pos (1) /*!< NMI_T::NMIEN: IRCINT Position */ +#define NMI_NMIEN_IRCINT_Msk (0x1ul << NMI_NMIEN_IRCINT_Pos) /*!< NMI_T::NMIEN: IRCINT Mask */ + +#define NMI_NMIEN_PWRWUINT_Pos (2) /*!< NMI_T::NMIEN: PWRWUINT Position */ +#define NMI_NMIEN_PWRWUINT_Msk (0x1ul << NMI_NMIEN_PWRWUINT_Pos) /*!< NMI_T::NMIEN: PWRWUINT Mask */ + +#define NMI_NMIEN_SRAMPERR_Pos (3) /*!< NMI_T::NMIEN: SRAMPERR Position */ +#define NMI_NMIEN_SRAMPERR_Msk (0x1ul << NMI_NMIEN_SRAMPERR_Pos) /*!< NMI_T::NMIEN: SRAMPERR Mask */ + +#define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ +#define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ + +#define NMI_NMIEN_RTCINT_Pos (6) /*!< NMI_T::NMIEN: RTCINT Position */ +#define NMI_NMIEN_RTCINT_Msk (0x1ul << NMI_NMIEN_RTCINT_Pos) /*!< NMI_T::NMIEN: RTCINT Mask */ + +#define NMI_NMIEN_TAMPERINT_Pos (7) /*!< NMI_T::NMIEN: TAMPERINT Position */ +#define NMI_NMIEN_TAMPERINT_Msk (0x1ul << NMI_NMIEN_TAMPERINT_Pos) /*!< NMI_T::NMIEN: TAMPERINT Mask */ + +#define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ +#define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ + +#define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ +#define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ + +#define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ +#define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ + +#define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ +#define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ + +#define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ +#define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ + +#define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ +#define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ + +#define NMI_NMIEN_UART0INT_Pos (14) /*!< NMI_T::NMIEN: UART0INT Position */ +#define NMI_NMIEN_UART0INT_Msk (0x1ul << NMI_NMIEN_UART0INT_Pos) /*!< NMI_T::NMIEN: UART0INT Mask */ + +#define NMI_NMIEN_UART1INT_Pos (15) /*!< NMI_T::NMIEN: UART1INT Position */ +#define NMI_NMIEN_UART1INT_Msk (0x1ul << NMI_NMIEN_UART1INT_Pos) /*!< NMI_T::NMIEN: UART1INT Mask */ + +#define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ +#define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ + +#define NMI_NMISTS_IRCINT_Pos (1) /*!< NMI_T::NMISTS: IRCINT Position */ +#define NMI_NMISTS_IRCINT_Msk (0x1ul << NMI_NMISTS_IRC_NT_Pos) /*!< NMI_T::NMISTS: IRCINT Mask */ + +#define NMI_NMISTS_PWRWUINT_Pos (2) /*!< NMI_T::NMISTS: PWRWUINT Position */ +#define NMI_NMISTS_PWRWUINT_Msk (0x1ul << NMI_NMISTS_PWRWUINT_Pos) /*!< NMI_T::NMISTS: PWRWUINT Mask */ + +#define NMI_NMISTS_SRAMPERR_Pos (3) /*!< NMI_T::NMISTS: SRAMPERR Position */ +#define NMI_NMISTS_SRAMPERR_Msk (0x1ul << NMI_NMISTS_SRAMPERR_Pos) /*!< NMI_T::NMISTS: SRAMPERR Mask */ + +#define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ +#define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ + +#define NMI_NMISTS_RTCINT_Pos (6) /*!< NMI_T::NMISTS: RTCINT Position */ +#define NMI_NMISTS_RTCINT_Msk (0x1ul << NMI_NMISTS_RTCINT_Pos) /*!< NMI_T::NMISTS: RTCINT Mask */ + +#define NMI_NMISTS_TAMPERINT_Pos (7) /*!< NMI_T::NMISTS: TAMPERINT Position */ +#define NMI_NMISTS_TAMPERINT_Msk (0x1ul << NMI_NMISTS_TAMPERINT_Pos) /*!< NMI_T::NMISTS: TAMPERINT Mask */ + +#define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ +#define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ + +#define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ +#define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ + +#define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ +#define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ + +#define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ +#define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ + +#define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ +#define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ + +#define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ +#define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ + +#define NMI_NMISTS_UART0INT_Pos (14) /*!< NMI_T::NMISTS: UART0INT Position */ +#define NMI_NMISTS_UART0INT_Msk (0x1ul << NMI_NMISTS_UART0INT_Pos) /*!< NMI_T::NMISTS: UART0INT Mask */ + +#define NMI_NMISTS_UART1INT_Pos (15) /*!< NMI_T::NMISTS: UART1INT Position */ +#define NMI_NMISTS_UART1INT_Msk (0x1ul << NMI_NMISTS_UART1INT_Pos) /*!< NMI_T::NMISTS: UART1INT Mask */ + +/**@}*/ /* NMI_CONST */ +/**@}*/ /* end of NMI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __SYS_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/timer_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/timer_reg.h new file mode 100644 index 0000000..af68ddf --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/timer_reg.h @@ -0,0 +1,1231 @@ +/**************************************************************************//** + * @file timer_reg.h + * @version V1.00 + * @brief TIMER register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Timer Controller -------------------------*/ +/** + @addtogroup TIMER Timer Controller(TIMER) + Memory Mapped Structure for CRC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, + * | | |CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. + * | | |1 = Capture Function source is from internal ACMP output signal + * | | |User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * | | |Note: This bit is read only. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer External Capture Pin Enable Bit + * | | |This bit enables the TMx_EXT capture pin input function. + * | | |0 =TMx_EXT (x= 0~3) pin Disabled. + * | | |1 =TMx_EXT (x= 0~3) pin Enabled. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = External Capture Mode Enabled. + * | | |1 = External Reset Mode Enabled. + * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. + * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer external interrupt + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[8:10] |ICAPSEL |Internal Capture Source Select + * | | |000 = Capture Function source is from internal ACMP0 output signal. + * | | |001 = Capture Function source is from internal ACMP1 output signal. + * | | |010 = Capture Function source is from HXT. + * | | |011 = Capture Function source is from LXT. + * | | |100 = Capture Function source is from HIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |110 = Reserved. + * | | |111 = Reserved. + * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |100, 101 = Reserved. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~3) pin. + * | | |1 = Event Counter input source is from USB internal SOF output signal. + * |[31:28] |CAPDIVSCL |Timer Capture Source Divider + * | | |This bits indicate the divide scale for capture source divider + * | | |0000 = Capture source/1. + * | | |0001 = Capture source/2. + * | | |0010 = Capture source/4. + * | | |0011 = Capture source/8. + * | | |0100 = Capture source/16. + * | | |0101 = Capture source/32. + * | | |0110 = Capture source/64. + * | | |0111 = Capture source/128. + * | | |1000 = Capture source/256. + * | | |1001~1111 = Reserved. + * | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer External Capture Interrupt Flag + * | | |This bit indicates the timer external capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. + * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status + * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or + * | | |capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. + * | | |1 = Capture interrupt signal is used to internal trigger EPWM, BPWM, PDMA, DAC, and EADC. + * |[1] |TRGPWM |Trigger EPWM and BPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source. + * | | |0 = Timer interrupt trigger EPWM and BPWM Disabled. + * | | |1 = Timer interrupt trigger EPWM and BPWM Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM and BPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. + * |[3] |TRGDAC |Trigger DAC Enable Bit + * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. + * | | |0 = Timer interrupt trigger DAC Disabled. + * | | |1 = Timer interrupt trigger DAC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::ALTCTL + * Offset: 0x20 Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FUNCSEL |Function Selection + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * @var TIMER_T::CAPNF + * Offset: 0x24 Timer Capture Input Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPNFEN |Capture Noise Filter Enable + * | | |0 = Capture Noise Filter function Disabled. + * | | |1 = Capture Noise Filter function Enabled. + * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count + * | | |These bits control the capture filter counter to count from 0 to CAPNFCNT. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[2:1] |CNTTYPE |PWM Counter Behavior Type + * | | |00 = Up count type. + * | | |01 = Down count type. + * | | |10 = Up-down count type. + * | | |11 = Reserved. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[8] |CTRLD |Center Re-load + * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. + * |[9] |IMMLDEN |Immediately Load Enable Bit + * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled + * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. + * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. + * | | |Note: If IMMLDEN is enabled, CTRLD will be invalid. + * |[16] |OUTMODE |PWM Output Mode + * | | |This bit controls the output mode of corresponding PWM channel. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCLKSRC + * Offset: 0x44 Timer PWM Counter Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CLKSRC |PWM Counter Clock Source Select + * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event. + * | | |000 = TMRx_CLK. + * | | |001 = Internal TIMER0 time-out or capture event. + * | | |010 = Internal TIMER1 time-out or capture event. + * | | |011 = Internal TIMER2 time-out or capture event. + * | | |100 = Internal TIMER3 time-out or capture event. + * | | |Others = Reserved. + * | | |Note: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x4C Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. + * @var TIMER_T::PWMPERIOD + * Offset: 0x50 Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |In up and down count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * | | |In up-down count type: + * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. + * | | |Note: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x54 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert. + * @var TIMER_T::PWMDTCTL + * Offset: 0x58 Timer PWM Dead-Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following two formulas: + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) + * | | |Dead-time insertion function is only active when PWM complementary mode is enabled + * | | |If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. + * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCNT + * Offset: 0x5C Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) + * | | |0 = Counter is active in down count. + * | | |1 = Counter is active up count. + * @var TIMER_T::PWMMSKEN + * Offset: 0x60 Timer PWM Output Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit + * | | |The PWMx_CH0 output signal will be masked when this bit is enabled + * | | |The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data. + * | | |0 = PWMx_CH0 output signal is non-masked. + * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit + * | | |The PWMx_CH1 output signal will be masked when this bit is enabled + * | | |The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data. + * | | |0 = PWMx_CH1 output signal is non-masked. + * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. + * @var TIMER_T::PWMMSK + * Offset: 0x64 Timer PWM Output Mask Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). + * | | |0 = Output logic Low to PWMx_CH0. + * | | |1 = Output logic High to PWMx_CH0. + * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). + * | | |0 = Output logic Low to PWMx_CH1. + * | | |1 = Output logic High to PWMx_CH1. + * @var TIMER_T::PWMBNF + * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit + * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. + * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. + * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count + * | | |The fields is used to control the active noise filter sample time. + * | | |Once noise filter sample time = (Period time of BRKDBCS) * BRKFCNT. + * |[7] |BRKPINV |Brake Pin Detection Control Bit + * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . + * |[17:16] |BKPINSRC |Brake Pin Source Select + * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. + * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. + * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. + * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. + * @var TIMER_T::PWMFAILBRK + * Offset: 0x6C Timer PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by clock fail detection Disabled. + * | | |1 = Brake Function triggered by clock fail detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by BOD event Disabled. + * | | |1 = Brake Function triggered by BOD event Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by core lockup event Disabled. + * | | |1 = Brake Function triggered by core lockup event Enabled. + * @var TIMER_T::PWMBRKCTL + * Offset: 0x70 Timer PWM Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System fail condition as edge-detect brake source Disabled. + * | | |1 = System fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System fail condition as level-detect brake source Disabled. + * | | |1 = System fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. + * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. + * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMPOLCTL + * Offset: 0x74 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH0 output pin. + * | | |0 = PWMx_CH0 output pin polar inverse Disabled. + * | | |1 = PWMx_CH0 output pin polar inverse Enabled. + * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH1 output pin. + * | | |0 = PWMx_CH1 output pin polar inverse Disabled. + * | | |1 = PWMx_CH1 output pin polar inverse Enabled. + * @var TIMER_T::PWMPOEN + * Offset: 0x78 Timer PWM Pin Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit + * | | |0 = PWMx_CH0 pin at tri-state mode. + * | | |1 = PWMx_CH0 pin in output mode. + * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit + * | | |0 = PWMx_CH1 pin at tri-state mode. + * | | |1 = PWMx_CH1 pin in output mode. + * @var TIMER_T::PWMSWBRK + * Offset: 0x7C Timer PWM Software Trigger Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTEN0 + * Offset: 0x80 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When in up-down count type, period point means the center point of current PWM period. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var TIMER_T::PWMINTEN1 + * Offset: 0x84 Timer PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM edge-detect brake interrupt Disabled. + * | | |1 = PWM edge-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM level-detect brake interrupt Disabled. + * | | |1 = PWM level-detect brake interrupt Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x88 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF |PWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note1: When in up-down count type, PIF flag means the center point flag of current PWM period. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMINTSTS1 + * Offset: 0x8C Timer PWM Interrupt Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 edge-detect brake event do not happened. + * | | |1 = PWMx_CH0 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 edge-detect brake event do not happened. + * | | |1 = PWMx_CH1 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 level-detect brake event do not happened. + * | | |1 = PWMx_CH0 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 level-detect brake event do not happened. + * | | |1 = PWMx_CH1 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This register is write protected. Refer toSYS_REGLCTL register. + * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 edge-detect brake state is released. + * | | |1 = PWMx_CH0 at edge-detect brake state. + * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. + * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 edge-detect brake state is released. + * | | |1 = PWMx_CH1 at edge-detect brake state. + * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. + * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 level-detect brake state is released. + * | | |1 = PWMx_CH0 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 level-detect brake state is released. + * | | |1 = PWMx_CH1 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * @var TIMER_T::PWMTRGCTL + * Offset: 0x90 Timer PWM Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger Conversion + * | | |000 = Trigger conversion at zero point (ZIF). + * | | |001 = Trigger conversion at period point (PIF). + * | | |010 = Trigger conversion at zero or period point (ZIF or PIF). + * | | |011 = Trigger conversion at compare up count point (CMPUIF). + * | | |100 = Trigger conversion at compare down count point (CMPDIF). + * | | |Others = Reserved. + * |[7] |TRGEADC |PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * @var TIMER_T::PWMSCTL + * Offset: 0x94 Timer PWM Synchronous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select + * | | |00 = PWM synchronous function Disabled. + * | | |01 = PWM synchronous counter start function Enabled. + * | | |10 = Reserved. + * | | |11 = PWM synchronous counter clear function Enabled. + * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select + * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. + * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. + * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. + * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. + * @var TIMER_T::PWMSTRG + * Offset: 0x98 Timer PWM Synchronous Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) + * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. + * | | |Note: This bit is only available in TIMER0 and TIMER2. + * @var TIMER_T::PWMSTATUS + * Offset: 0x9C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = Indicates the PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = Indicates the PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0xA0 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0xA4 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + * @var TIMER_T::PWMIFA + * Offset: 0xA8 Timer PWM Interrupt Flag Accumulator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |PWM Interrupt Flag Accumulator Counter + * | | |This field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. + * | | |PWM accumulator flag (IFAIF) will be set in every (IFACNT+1) times during the the PWM counter operation. + * |[24] |STPMOD |PWM Accumulator Stop Mode Enable Bit + * | | |0 = PWM interrupt accumulator event to stop counting Disabled. + * | | |1 = PWM interrupt accumulator event to stop counting Enabled. + * |[29:28] |IFASEL |PWM Interrupt Flag Accumulator Source Select + * | | |00 = Accumulate at each PWM zero point. + * | | |01 = Accumulate at each PWM period point. + * | | |10 = Accumulate at each PWM up-count compared point. + * | | |11 = Accumulate at each PWM down-count compared point. + * |[31] |IFAEN |PWM Interrupt Flag Accumulator Enable Bit + * | | |0 = PWM interrupt flag accumulator function Disabled. + * | | |1 = PWM interrupt flag accumulator function Enabled. + * @var TIMER_T::PWMAINTSTS + * Offset: 0xAC Timer PWM Accumulator Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF |PWM Interrupt Flag Accumulator Interrupt Flag + * | | |This bit is set by hardware when the accumulator value reaches (IFACNT+1). + * | | |Note 1: This bit is cleared by writing 1 to it. + * | | |Note 2: If APDMAEN (TIMERx_PWMAPDMACTL[0]) is set, this bit will be auto clear after PDMA transfer done. + * @var TIMER_T::PWMAINTEN + * Offset: 0xB0 Timer PWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN |PWM Interrupt Flag Accumulator Interrupt Enable Bit + * | | |0 = Interrupt Flag Accumulator interrupt Disabled. + * | | |1 = Interrupt Flag Accumulator interrupt Enabled. + * @var TIMER_T::PWMAPDMACTL + * Offset: 0xB4 Timer PWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN |PWM Accumulator PDMA Enable Bit + * | | |0 = PWM interrupt accumulator event to trigger PDMA transfer Disabled. + * | | |1 = PWM interrupt accumulator event to trigger PDMA transfer Enabled. + * @var TIMER_T::PWMEXTETCTL + * Offset: 0xB8 Timer PWM External Event Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EXTETEN |External Pin Event Trigger Enable Bit + * | | |0 = External pin event trigger function Disabled. + * | | |1 = External pin event trigger function Enabled. + * |[5:4] |CNTACTS |Counter Action Selection + * | | |00 = External pin event to trigger PWM counter reset. + * | | |01 = External pin event to trigger PWM counter start. + * | | |10 = External pin event to trigger PWM counter reset and start. + * | | |11 = Reserved. + * |[11:8] |EXTTRGS |External Trigger Pin Selection + * | | |0000 = Trigger source form INT0 pin. + * | | |0001 = Trigger source form INT1 pin. + * | | |0010 = Trigger source form INT2 pin. + * | | |0011 = Trigger source form INT3 pin. + * | | |0100 = Trigger source form INT4 pin. + * | | |0101 = Trigger source form INT5 pin. + * | | |0110 = Trigger source form INT6 pin. + * | | |0111 = Trigger source form INT7 pin. + * | | |Other = Reserved. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ + __IO uint32_t CAPNF; /*!< [0x0024] Timer Capture Input Noise Filter Register */ + /** @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[6]; + /** @endcond */ + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ + __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ + __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ + __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ + __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ + __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ + __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ + __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ + __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ + __IO uint32_t PWMTRGCTL; /*!< [0x0090] Timer PWM Trigger Control Register */ + __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ + __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ + __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ + __IO uint32_t PWMIFA; /*!< [0x00a8] Timer PWM Interrupt Flag Accumulator Register */ + __IO uint32_t PWMAINTSTS; /*!< [0x00ac] Timer PWM Accumulator Interrupt Flag Register */ + __IO uint32_t PWMAINTEN; /*!< [0x00b0] Timer PWM Accumulator Interrupt Enable Register */ + __IO uint32_t PWMAPDMACTL; /*!< [0x00b4] Timer PWM Accumulator PDMA Control Register */ + __IO uint32_t PWMEXTETCTL; /*!< [0x00b8] Timer PWM External Event Trigger Control Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller +@{ */ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_ICAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: ICAPSEL Position */ +#define TIMER_EXTCTL_ICAPSEL_Msk (0x7ul << TIMER_EXTCTL_ICAPSEL_Pos) /*!< TIMER_T::EXTCTL: ICAPSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x3ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */ +#define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_EINTSTS_CAPIFOV_Pos (1) /*!< TIMER_T::EINTSTS: CAPIFOV Position */ +#define TIMER_EINTSTS_CAPIFOV_Msk (0x1ul << TIMER_EINTSTS_CAPIFOV_Pos) /*!< TIMER_T::EINTSTS: CAPIFOV Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGPWM Position */ +#define TIMER_TRGCTL_TRGPWM_Msk (0x1ul << TIMER_TRGCTL_TRGPWM_Pos) /*!< TIMER_T::TRGCTL: TRGPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ +#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ +#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ + +#define TIMER_CAPNF_CAPNFEN_Pos (0) /*!< TIMER_T::CAPNF: CAPNFEN Position */ +#define TIMER_CAPNF_CAPNFEN_Msk (0x1ul << TIMER_CAPNF_CAPNFEN_Pos) /*!< TIMER_T::CAPNF: CAPNFEN Mask */ + +#define TIMER_CAPNF_CAPNFSEL_Pos (4) /*!< TIMER_T::CAPNF: CAPNFSEL Position */ +#define TIMER_CAPNF_CAPNFSEL_Msk (0x7ul << TIMER_CAPNF_CAPNFSEL_Pos) /*!< TIMER_T::CAPNF: CAPNFSEL Mask */ + +#define TIMER_CAPNF_CAPNFCNT_Pos (8) /*!< TIMER_T::CAPNF: CAPNFCNT Position */ +#define TIMER_CAPNF_CAPNFCNT_Msk (0x7ul << TIMER_CAPNF_CAPNFCNT_Pos) /*!< TIMER_T::CAPNF: CAPNFCNT Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ +#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ +#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ + +#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ +#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ + +#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ +#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ +#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ +#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ + +#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ +#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ + +#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ +#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ +#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ + +#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ +#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ + +#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ +#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ + +#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ +#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ + +#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ +#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ + +#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ +#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ + +#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ +#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ + +#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ +#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ + +#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ +#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ + +#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ +#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ + +#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ +#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ + +#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ +#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ + +#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ +#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ + +#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ +#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ +#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ +#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ +#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ + +#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ +#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ +#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ +#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ +#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ + +#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ +#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ +#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ +#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ + +#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ +#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ + +#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ +#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ + +#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ +#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ + +#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ +#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ + +#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ +#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ + +#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ +#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ + +#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ +#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ +#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ + +#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ +#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ + +#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ +#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ + +#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ +#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ +#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ +#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ +#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ +#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ +#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ +#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ +#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ + +#define TIMER_PWMTRGCTL_TRGSEL_Pos (0) /*!< TIMER_T::PWMTRGCTL: TRGSEL Position */ +#define TIMER_PWMTRGCTL_TRGSEL_Msk (0x7ul << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< TIMER_T::PWMTRGCTL: TRGSEL Mask */ + +#define TIMER_PWMTRGCTL_TRGEADC_Pos (7) /*!< TIMER_T::PWMTRGCTL: TRGEADC Position */ +#define TIMER_PWMTRGCTL_TRGEADC_Msk (0x1ul << TIMER_PWMTRGCTL_TRGEADC_Pos) /*!< TIMER_T::PWMTRGCTL: TRGEADC Mask */ + +#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ +#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ + +#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ +#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ + +#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ +#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +#define TIMER_PWMIFA_IFACNT_Pos (0) /*!< TIMER_T::PWMIFA: IFACNT Position */ +#define TIMER_PWMIFA_IFACNT_Msk (0xfffful << TIMER_PWMIFA_IFACNT_Pos) /*!< TIMER_T::PWMIFA: IFACNT Mask */ + +#define TIMER_PWMIFA_STPMOD_Pos (24) /*!< TIMER_T::PWMIFA: STPMOD Position */ +#define TIMER_PWMIFA_STPMOD_Msk (0x1ul << TIMER_PWMIFA_STPMOD_Pos) /*!< TIMER_T::PWMIFA: STPMOD Mask */ + +#define TIMER_PWMIFA_IFASEL_Pos (28) /*!< TIMER_T::PWMIFA: IFASEL Position */ +#define TIMER_PWMIFA_IFASEL_Msk (0x3ul << TIMER_PWMIFA_IFASEL_Pos) /*!< TIMER_T::PWMIFA: IFASEL Mask */ + +#define TIMER_PWMIFA_IFAEN_Pos (31) /*!< TIMER_T::PWMIFA: IFAEN Position */ +#define TIMER_PWMIFA_IFAEN_Msk (0x1ul << TIMER_PWMIFA_IFAEN_Pos) /*!< TIMER_T::PWMIFA: IFAEN Mask */ + +#define TIMER_PWMAINTSTS_IFAIF_Pos (0) /*!< TIMER_T::PWMAINTSTS: IFAIF Position */ +#define TIMER_PWMAINTSTS_IFAIF_Msk (0x1ul << TIMER_PWMAINTSTS_IFAIF_Pos) /*!< TIMER_T::PWMAINTSTS: IFAIF Mask */ + +#define TIMER_PWMAINTEN_IFAIEN_Pos (0) /*!< TIMER_T::PWMAINTEN: IFAIEN Position */ +#define TIMER_PWMAINTEN_IFAIEN_Msk (0x1ul << TIMER_PWMAINTEN_IFAIEN_Pos) /*!< TIMER_T::PWMAINTEN: IFAIEN Mask */ + +#define TIMER_PWMAPDMACTL_APDMAEN_Pos (0) /*!< TIMER_T::PWMAPDMACTL: APDMAEN Position */ +#define TIMER_PWMAPDMACTL_APDMAEN_Msk (0x1ul << TIMER_PWMAPDMACTL_APDMAEN_Pos) /*!< TIMER_T::PWMAPDMACTL: APDMAEN Mask */ + +#define TIMER_PWMEXTETCTL_EXTETEN_Pos (0) /*!< TIMER_T::PWMEXTETCTL: EXTETEN Position */ +#define TIMER_PWMEXTETCTL_EXTETEN_Msk (0x1ul << TIMER_PWMEXTETCTL_EXTETEN_Pos) /*!< TIMER_T::PWMEXTETCTL: EXTETEN Mask */ + +#define TIMER_PWMEXTETCTL_CNTACTS_Pos (4) /*!< TIMER_T::PWMEXTETCTL: CNTACTS Position */ +#define TIMER_PWMEXTETCTL_CNTACTS_Msk (0x3ul << TIMER_PWMEXTETCTL_CNTACTS_Pos) /*!< TIMER_T::PWMEXTETCTL: CNTACTS Mask */ + +#define TIMER_PWMEXTETCTL_EXTTRGS_Pos (8) /*!< TIMER_T::PWMEXTETCTL: EXTTRGS Position */ +#define TIMER_PWMEXTETCTL_EXTTRGS_Msk (0xful << TIMER_PWMEXTETCTL_EXTTRGS_Pos) /*!< TIMER_T::PWMEXTETCTL: EXTTRGS Mask */ + + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __TIMER_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/trng_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/trng_reg.h new file mode 100644 index 0000000..55f6234 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/trng_reg.h @@ -0,0 +1,138 @@ +/**************************************************************************//** + * @file trng_reg.h + * @version V1.00 + * @brief TRNG register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TRNG_REG_H__ +#define __TRNG_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- True Random Number Generator -------------------------*/ +/** + @addtogroup TRNG True Random Number Generator(TRNG) + Memory Mapped Structure for TRNG Controller +@{ */ + +typedef struct +{ + + + /** + * @var TRNG_T::CTL + * Offset: 0x00 TRNG Control Register and Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRNGEN |Random Number Generator Enable Bit + * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1. + * | | |0 = TRNG disabled. + * | | |1 = TRNG enabled. + * | | |Note: TRNGEN is an enable bit of digital part + * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption. + * |[1] |DVIF |Data Valid (Read Only) + * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000. + * | | |1 = Data is valid. A valid random number can be read form RNGD. + * | | |This bit is cleared to u20180u2019 by read TRNG_DATA. + * |[5:2] |CLKP |Clock Prescaler + * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation) + * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module. + * | | |0000 = 80 ~ 100 MHz. + * | | |0001 = 60 ~ 80 MHz. + * | | |0010 = 50 ~60 MHz. + * | | |0011 = 40 ~50 MHz. + * | | |0100 = 30 ~40 MHz. + * | | |0101 = 25 ~30 MHz. + * | | |0110 = 20 ~25 MHz. + * | | |0111 = 15 ~20 MHz. + * | | |1000 = 12 ~15 MHz. + * | | |1001 = 9 ~12 MHz. + * | | |1010 = 7 ~9 MHz. + * | | |1011 = 6 ~7 MHz. + * | | |1100 = 5 ~6 MHz. + * | | |1101 = 4 ~5 MHz. + * | | |1111 = Reserved. + * |[6] |DVIEN |Data Valid Interrupt Enable Bit + * | | |0 = Interrupt disabled.. + * | | |1 = Interrupt enabled. + * |[7] |READY |Random Number Generator Ready (Read Only) + * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us. + * | | |0 = RNG is not ready or was not activated. + * | | |1 = RNG is ready to be enabled.. + * |[31:8] |Reversed |Reversed + * @var TRNG_T::DATA + * Offset: 0x04 TRNG Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DATA |Random Number Generator Data (Read Only) + * | | |The DATA store the random number generated by TRNG and can be read only once. + * @var TRNG_T::ACT + * Offset: 0x0C TRNG Activation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |VER |TRNG Version + * | | |TRNG version number is dependent on TRNG module. + * | | |0x02:(Current Version Number) + * |[7] |ACT |Random Number Generator Activation + * | | |After enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1. + * | | |0 = TRNG inactive. + * | | |1 = TRNG active. + * | | |Note: ACT is an enable bit of analog part + * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption. + */ + __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */ + __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */ + +} TRNG_T; + +/** + @addtogroup TRNG_CONST TRNG Bit Field Definition + Constant Definitions for TRNG Controller +@{ */ + +#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */ +#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */ + +#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */ +#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */ + +#define TRNG_CTL_CLKPSC_Pos (2) /*!< TRNG_T::CTL: CLKPSC Position */ +#define TRNG_CTL_CLKPSC_Msk (0xful << TRNG_CTL_CLKP_Pos) /*!< TRNG_T::CTL: CLKPSC Mask */ + +#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */ +#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */ + +#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */ +#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */ + +#define TRNG_CTL_Reversed_Pos (8) /*!< TRNG_T::CTL: Reversed Position */ +#define TRNG_CTL_Reversed_Msk (0xfffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */ + +#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */ +#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */ + +#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */ +#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */ + +#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */ +#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */ + +/**@}*/ /* TRNG_CONST */ +/**@}*/ /* end of TRNG register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __TRNG_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uart_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uart_reg.h new file mode 100644 index 0000000..f365b52 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uart_reg.h @@ -0,0 +1,1317 @@ +/**************************************************************************//** + * @file uart_reg.h + * @version V3.00 + * @brief UART register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) + Memory Mapped Structure for UART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO. + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO. + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |LINIEN |LIN Bus Interrupt Enable Bit + * | | |0 = LIN bus interrupt Disabled. + * | | |1 = LIN bus interrupt Enabled. + * | | |Note: This bit is used for LIN function mode. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |This bit can enable or disable TX PDMA service. + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[16] |SWBEIEN |Single-wire Bit Error Detection Interrupt Enable Bit + * | | |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set. + * | | |0 = Single-wire Bit Error Detect Interrupt Disabled. + * | | |1 = Single-wire Bit Error Detect Interrupt Enabled. + * | | |Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set. + * | | |TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note 2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note 2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode. + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of 'STOP Bit' + * | | |0 = One 'STOP bit' is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data. + * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = Parity bit generated Disabled. + * | | |1 = Parity bit generated Enabled. + * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic '1's is transmitted and checked in each word. + * | | |1 = Even number of logic '1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0). + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |Parity Bit Source Selection + * | | |The parity bit can be selected to be generated and checked automatically or by software. + * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = Parity bit generated and checked by software. + * | | |Note 1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note 2: If PSS is 0, the parity bit is transmitted and checked automatically. + * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART, LIN or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS Signal Control + * | | |This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note 1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note 2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * | | |Note 3: Single-wire mode is support this feature. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic '1' when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' + * | | |(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) + * | | |for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer + * | | |When UART receives one byte from external device, RXPTR increases one. + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15. + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one. + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.. + * | | |The Maximum value shown in TXPTR is 15. + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. + * | | |The UART controller can not transmit or receive data at this moment. + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only) + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only) + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note 1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = '1') bit". + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note 2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[7] |LINIF |LIN Bus Interrupt Flag + * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] = 1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])). + * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7]). + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[16] |SWBEIF |Single-wire Bit Error Detection Interrupt Flag + * | | |This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. + * | | |0 = No single-wire bit error detection interrupt flag is generated. + * | | |1 = Single-wire bit error detection interrupt flag is generated. + * | | |Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note 1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = '1') bit". + * | | |Note 2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)) + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag (Read Only) + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[24] |SWBEINT |Single-wire Bit Error Detect Interrupt Indicator (Read Only) + * | | |Single-wire Bit Error Detect Interrupt Indicator (Read Only) + * | | |This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. + * | | |0 = No Single-wire Bit Error Detection Interrupt generated. + * | | |1 = Single-wire Bit Error Detection Interrupt generated. + * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]). + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled. + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]). + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit. + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider. + * | | |This filed is used in baud rate calculation. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0 + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1 + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note 1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note 2: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note 1: This break field length is BRKFL + 1. + * | | |Note 2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LINRXEN |LIN RX Enable Bit + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LINTXEN |LIN TX Break Mode Enable Bit + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNCSEL |Function Select + * | | |000 = UART function. + * | | |001 = LIN function. + * | | |010 = IrDA function. + * | | |011 = RS-485 function. + * | | |100 = UART Single-wire function. + * | | |Others = Reserved. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not disable immediately when this bit is set. + * | | |The TX and RX complete current task before disable TX and RX are disabled. + * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * |[6] |DGE |Deglitch Enable Bit + * | | |0 = Deglitch Disabled. + * | | |1 = Deglitch Enabled. + * | | |Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). + * | | |This bit acts only on RX line and has no effect on the transmitter logic. + * | | |Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps. + * |[7] |TXRXSWP |TX and RX Swap Enable Bit + * | | |Setting this bit Swaps TX pin and RX pin. + * | | |0 = TX and RX Swap Disabled. + * | | |1 = TX and RX Swap Enabled. + * @var UART_T::LINCTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVEN |LIN Slave Mode Enable Bit + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note 1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note 2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted. + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note 1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note 2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). + * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit + * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UART_BAUD is updated at the next received character. User must set the bit before checksum reception. + * | | |Note 1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note 2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) + * |[4] |MUTE |LIN Mute Mode Enable Bit + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * |[8] |SENDH |LIN TX Send Header Enable Bit + * | | |The LIN TX header can be break field or 'break and sync field' or 'break, sync and frame ID field', it is depend on setting HSEL (UART_LINCTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note 1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). + * | | |Note 2: When transmitter header field (it may be 'break' or 'break + sync' or 'break + sync + frame ID' selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |IDPEN |LIN ID Parity Enable Bit + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note 1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. + * | | |Note 2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10. + * |[10] |BRKDETEN |LIN Break Detection Enable Bit + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field. + * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled. + * | | |1 = LIN break detection Enabled. + * |[11] |LINRXOFF |LIN Receiver Disable Bit + * | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[2:0]) = 001). + * |[12] |BITERREN |Bit Error Detect Enable Bit + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection function Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[19:16] |BRKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note 1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). + * | | |Note 2: This break field length is BRKFL + 1. + * | | |Note 3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |BSL |LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1-bit time. + * | | |01 = The LIN break/sync delimiter length is 2-bit time. + * | | |10 = The LIN break/sync delimiter length is 3-bit time. + * | | |11 = The LIN break/sync delimiter length is 4-bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |HSEL |LIN Header Select + * | | |00 = The LIN header includes 'break field'. + * | | |01 = The LIN header includes 'break field' and 'sync field'. + * | | |10 = The LIN header includes 'break field', 'sync field' and 'frame ID field'. + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). + * |[31:24] |PID |LIN PID Bits + * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note 1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note 2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LINSTS + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVHDETF |LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note 1: This bit can be cleared by writing 1 to it. + * | | |Note 2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * | | |Note 3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ('break + sync + frame ID'), the SLVHDETF will be set whether the frame ID correct or not. + * |[1] |SLVHEF |LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |The header errors include 'break delimiter is too short (less than 0.5 bit time)', 'frame error in sync field or Identifier field', + * | | |'sync field data is not 0x55 in Non-Automatic Resynchronization mode', 'sync field deviation error with Automatic Resynchronization mode', + * | | |'sync field measure time-out with Automatic Resynchronization mode' and 'LIN header reception time-out'. + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note 1: This bit can be cleared by writing 1 to it. + * | | |Note 2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note 1: This bit can be cleared by writing 1 to it. + * | | |Note 2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). + * |[3] |SLVSYNCF |LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note 1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). + * | | |Note 2: This bit can be cleared by writing 1 to it. + * | | |Note 3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |BRKDETF |LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note 1: This bit can be cleared by writing 1 to it. + * | | |Note 2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10])=1). + * |[9] |BITEF |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. + * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * | | |0 = Bit error not detected. + * | | |1 = Bit error detected. + * | | |Note 1: This bit can be cleared by writing 1 to it. + * | | |Note 2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOMP[8] is used to define PARITY (UART_DAT[8]). + * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled. + * | | |Note: When the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled. + * | | |Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled. + * | | |Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. + * |[3] |WKRS485EN |RS-485 Address Match Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled. + * | | |Note 1: When the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. + * | | |Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled. + * | | |Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. + * | | |Note 2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to '1'. + * | | |Note2: This bit can be cleared by writing '1' to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. + * | | |Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to '1'. + * | | |Note 2: This bit can be cleared by writing '1' to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + * @var UART_T::RS485DD + * Offset: 0x4C UART RS485 Transceiver Deactivate Delay Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RTSDDLY |RS485 Transceiver Deactivate Delay Value + * | | |These bits field indicate how many clock cycles selected by UART_CLK do the UART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state. + * | | |These bits field have no effect when the state trancing of RS485 transceiver is from RX to TX state. + * | | |Note: It is valid only when RS485AUD (UART_ALTCTL[10]) is set. + */ + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ + __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + __IO uint32_t RS485DD; /*!< [0x004C] UART RS485 Transceiver Deactivate Delay Register */ + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller +@{ */ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ +#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ +#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_SWBEIEN_Pos (16) /*!< UART_T::INTEN: SWBEIEN Position */ +#define UART_INTEN_SWBEIEN_Msk (0x1ul << UART_INTEN_SWBEIEN_Pos) /*!< UART_T::INTEN: SWBEIEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ +#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ +#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ +#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ +#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ + +#define UART_INTSTS_SWBEIF_Pos (16) /*!< UART_T::INTSTS: SWBEIF Position */ +#define UART_INTSTS_SWBEIF_Msk (0x1ul << UART_INTSTS_SWBEIF_Pos) /*!< UART_T::INTSTS: SWBEIF Mask */ + +#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ +#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ + +#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ +#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ + +#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ +#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ + +#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ +#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_SWBEINT_Pos (24) /*!< UART_T::INTSTS: SWBEINT Position */ +#define UART_INTSTS_SWBEINT_Msk (0x1ul << UART_INTSTS_SWBEINT_Pos) /*!< UART_T::INTSTS: SWBEINT Mask */ + +#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ +#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ + +#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ +#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ + +#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ +#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ + +#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ +#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ +#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ + +#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ +#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ + +#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ +#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_FUNCSEL_DGE_Pos (6) /*!< UART_T::FUNCSEL: DGE Position */ +#define UART_FUNCSEL_DGE_Msk (0x1ul << UART_FUNCSEL_DGE_Pos) /*!< UART_T::FUNCSEL: DGE Mask */ + +#define UART_FUNCSEL_TXRXSWP_Pos (7) /*!< UART_T::FUNCSEL: TXRXSWP Position */ +#define UART_FUNCSEL_TXRXSWP_Msk (0x1ul << UART_FUNCSEL_TXRXSWP_Pos) /*!< UART_T::FUNCSEL: TXRXSWP Mask */ + +#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ +#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ + +#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ +#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ + +#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ +#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ + +#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ +#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ + +#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ +#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ + +#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ +#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ + +#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ +#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ + +#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ +#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ + +#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ +#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ + +#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ +#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ + +#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ +#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ + +#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ +#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ + +#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ +#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ + +#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ +#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ + +#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ +#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ + +#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ +#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ + +#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ +#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ + +#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ +#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ + +#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ +#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ + +#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ +#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ +#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ +#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + +#define UART_RS485DD_RTSDDLY_Pos (0) /*!< UART_T::RS485DD: RTSDDLY Position */ +#define UART_RS485DD_RTSDDLY_Msk (0xfffful << UART_RS485DD_RTSDDLY_Pos) /*!< UART_T::RS485DD: RTSDDLY Mask */ + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UART_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ui2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ui2c_reg.h new file mode 100644 index 0000000..04222bc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/ui2c_reg.h @@ -0,0 +1,583 @@ +/**************************************************************************//** + * @file ui2c_reg.h + * @version V1.00 + * @brief UI2C register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UI2C_REG_H__ +#define __UI2C_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UI2C I2C Mode of USCI Controller(UI2C) + Memory Mapped Structure for UI2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var UI2C_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UI2C_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USCI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UI2C_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits + * | | |And in I2C protocol, the length fixed as 8 bits. + * @var UI2C_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UI2C_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. + * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UI2C_T::DEVADDR0 + * Offset: 0x44 USCI Device Address Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::DEVADDR1 + * Offset: 0x48 USCI Device Address Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::ADDRMSK0 + * Offset: 0x4C USCI Device Address Mask Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::ADDRMSK1 + * Offset: 0x50 USCI Device Address Mask Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * @var UI2C_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UI2C_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCFUNC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[1] |AA |Assert Acknowledge Control + * | | |When AA=1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. + * |[2] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically + * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (USCI_PROTSTS.ERRIF = 1). + * |[3] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[4] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10 bit function is disabled. + * | | |1 = Address match 10 bit function is enabled. + * |[5] |PTRG |I2C Protocol Trigger (Write Only) + * | | |When a new state is present in the USCI_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested + * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. + * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. + * | | |1 = I2C's stretch active. + * |[8] |SCLOUTEN |SCL Output Enable Bit + * | | |This bit enables monitor pulling SCL to low + * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. + * | | |0 = SCL output will be forced high due to open drain mechanism. + * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. + * |[9] |MONEN |Monitor Mode Enable Bit + * | | |This bit enables monitor mode + * | | |In monitor mode the SDA output will be put in high impedance mode + * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. + * | | |0 = The monitor mode is disabled. + * | | |1 = The monitor mode is enabled. + * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. + * |[25:16] |TOCNT |Time-out Clock Cycle + * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (USCI_BRGEN [5]) when each interrupt flags are clear + * | | |The time-out is enable when TOCNT bigger than 0. + * | | |Note: The TMCNTSRC (USCI_BRGEN [5]) must be set zero on I2C mode. + * |[31] |PROTEN |I2C Protocol Enable Bit + * | | |0 = I2C Protocol disable. + * | | |1 = I2C Protocol enable. + * @var UI2C_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIEN |Time-out Interrupt Enable Control + * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. + * | | |0 = The time-out interrupt is disabled. + * | | |1 = The time-out interrupt is enabled. + * |[1] |STARIEN |Start Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. + * | | |0 = The start condition interrupt is disabled. + * | | |1 = The start condition interrupt is enabled. + * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. + * | | |0 = The stop condition interrupt is disabled. + * | | |1 = The stop condition interrupt is enabled. + * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. + * | | |0 = The non - acknowledge interrupt is disabled. + * | | |1 = The non - acknowledge interrupt is enabled. + * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. + * | | |0 = The arbitration lost interrupt is disabled. + * | | |1 = The arbitration lost interrupt is enabled. + * |[5] |ERRIEN |Error Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (USCI_PROTSTS [16])). + * | | |0 = The error interrupt is disabled. + * | | |1 = The error interrupt is enabled. + * |[6] |ACKIEN |Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. + * | | |0 = The acknowledge interrupt is disabled. + * | | |1 = The acknowledge interrupt is enabled. + * @var UI2C_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5] |TOIF |Time-out Interrupt Flag + * | | |0 = A time-out interrupt status has not occurred. + * | | |1 = A time-out interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit + * |[6] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[8] |STARIF |Start Condition Received Interrupt Flag + * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode + * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STARIEN = 1. + * | | |0 = A start condition has not yet been detected. + * | | |1 = A start condition has been detected. + * | | |It is cleared by software writing one into this bit + * |[9] |STORIF |Stop Condition Received Interrupt Flag + * | | |This bit indicates that a stop condition has been detected on the I2C bus lines + * | | |A protocol interrupt can be generated if USCI_PROTCTL.STORIEN = 1. + * | | |0 = A stop condition has not yet been detected. + * | | |1 = A stop condition has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave RX mode. + * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag + * | | |This bit indicates that a non - acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.NACKIEN = 1. + * | | |0 = A non - acknowledge has not been received. + * | | |1 = A non - acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag + * | | |This bit indicates that an arbitration has been lost + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ARBLOIEN = 1. + * | | |0 = An arbitration has not been lost. + * | | |1 = An arbitration has been lost. + * | | |It is cleared by software writing one into this bit + * |[12] |ERRIF |Error Interrupt Flag + * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ERRIEN = 1. + * | | |0 = An I2C error has not been detected. + * | | |1 = An I2C error has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode. + * |[13] |ACKIF |Acknowledge Received Interrupt Flag + * | | |This bit indicates that an acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if USCI_PROTCTL.ACKIEN = 1. + * | | |0 = An acknowledge has not been received. + * | | |1 = An acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[14] |SLASEL |Slave Select Status + * | | |This bit indicates that this device has been selected as slave. + * | | |0 = The device is not selected as slave. + * | | |1 = The device is selected as slave. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[15] |SLAREAD |Slave Read Request Status + * | | |This bit indicates that a slave read request has been detected. + * | | |0 = A slave R/W bit is 1 has not been detected. + * | | |1 = A slave R/W bit is 1 has been detected. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release when WKUPIF is set. + * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * |[18] |BUSHANG |Bus Hang-up + * | | |This bit indicates bus hang-up status + * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK + * | | |The hang-up counter will count to overflow and set this bit when SDA is low + * | | |The counter will be reset by falling edge of SCL signal. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is hang-up status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * |[19] |ERRARBLO |Error Arbitration Lost + * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor + * | | |The I2C can send start condition when ERRARBLO is set + * | | |Thus this bit doesn't be cared on slave mode. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is error arbitration lost status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * @var UI2C_T::ADMAT + * Offset: 0x88 I2C Slave Match Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |USCI Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |USCI Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * @var UI2C_T::TMCTL + * Offset: 0x8C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in + * | | |transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ + __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ + __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[8]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ + __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ + +} UI2C_T; + +/** + @addtogroup UI2C_CONST UI2C Bit Field Definition + Constant Definitions for UI2C Controller +@{ */ + +#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ +#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ + +#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ +#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ + +#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ +#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ + +#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ +#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ + +#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ +#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ + +#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ +#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ + +#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ +#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ + +#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ +#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ + +#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ +#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ + +#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ +#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ + +#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ +#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ + +#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ +#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ + +#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ +#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ + +#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ +#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ + +#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ +#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ + +#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ +#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ +#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ +#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ + +#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ +#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ + +#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ +#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ + +#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ +#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ + +#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ +#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ + +#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ +#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ + +#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ +#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ + +#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ +#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ + +#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ +#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ + +#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ +#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ + +#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ +#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ + +#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ +#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ + +#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ +#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ + +#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ +#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ + +#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ +#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ + +#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ +#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ + +#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ +#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ + +#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ +#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ + +#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ +#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ + +#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ +#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ + +#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ +#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ + +#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ +#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ + +#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ +#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ + +#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ +#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ + +#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ +#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ + +#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ +#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ + +#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ +#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ + +#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ +#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ + +#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ +#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ + +#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ +#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ + +#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ +#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ + +#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ +#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ + +#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ +#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ + +#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ +#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ + +#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ +#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ + +#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ +#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ + +#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ +#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ + +#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ +#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ + +/**@}*/ /* UI2C_CONST */ +/**@}*/ /* end of UI2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UI2C_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/usbd_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/usbd_reg.h new file mode 100644 index 0000000..543b466 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/usbd_reg.h @@ -0,0 +1,772 @@ +/**************************************************************************//** + * @file usbd_reg.h + * @version V3.00 + * @brief USBD register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBD_REG_H__ +#define __USBD_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBD USB Device Controller(USBD) + Memory Mapped Structure for USBD Controller +@{ */ + +typedef struct +{ + + /** + * @var USBD_EP_T::BUFSEG + * Offset: 0x000 Endpoint n Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is + * | | |USBD_SRAM address + { BUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 7.29.5.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x004 Endpoint n Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x008 Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint STATE + * | | |00 = Endpoint is Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQSYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction + * | | |hardware will toggle automatically in IN token base on the bit. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * @var USBD_EP_T::CFGP + * Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data + * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is write 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */ + __IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */ + __IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */ + __IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + +typedef struct +{ + + + /** + * @var USBD_T::INTEN + * Offset: 0x00 USB Device Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIEN |Bus Event Interrupt Enable Bit + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USBIEN |USB Event Interrupt Enable Bit + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit + * | | |0 = VBUS detection Interrupt Disabled. + * | | |1 = VBUS detection Interrupt Enabled. + * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit + * | | |0 = No-event-wake-up Interrupt Disabled. + * | | |1 = No-event-wake-up Interrupt Enabled. + * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit + * | | |0 = SOF Interrupt Disabled. + * | | |1 = SOF Interrupt Enabled. + * |[8] |WKEN |Wake-up Function Enable Bit + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Device Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIF |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]. + * |[1] |USBIF |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). + * |[2] |VBDETIF |VBUS Detection Interrupt Status + * | | |0 = There is not attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]. + * |[3] |NEVWKIF |No-event-wake-up Interrupt Status + * | | |0 = NEVWK event does not occur. + * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]. + * |[4] |SOFIF |Start of Frame Interrupt Status + * | | |0 = SOF event does not occur. + * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred in endpoint 0. + * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred in endpoint 1. + * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred in endpoint 2. + * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred in endpoint 3. + * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred in endpoint 4. + * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred in endpoint 5. + * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred in endpoint 6. + * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred in endpoint 7. + * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. + * |[24] |EPEVT8 |Endpoint 8's USB Event Status + * | | |0 = No event occurred in endpoint 8. + * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. + * |[25] |EPEVT9 |Endpoint 9's USB Event Status + * | | |0 = No event occurred in endpoint 9. + * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. + * |[26] |EPEVT10 |Endpoint 10's USB Event Status + * | | |0 = No event occurred in endpoint 10. + * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. + * |[27] |EPEVT11 |Endpoint 11's USB Event Status + * | | |0 = No event occurred in endpoint 11. + * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Device Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OV |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes. + * @var USBD_T::ATTR + * Offset: 0x10 USB Device Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. + * | | |Note: This bit is read only. + * |[1] |SUSPEND |Suspend Status + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. + * | | |Note: This bit is read only. + * |[2] |RESUME |Resume Status + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * | | |Note: This bit is read only. + * |[3] |TOUT |Time-out Status + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time. + * | | |Note: This bit is read only. + * |[4] |PHYEN |PHY Transceiver Function Enable Bit + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. + * |[7] |USBEN |USB Controller Enable Bit + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit + * | | |0 = Pull-up resistor in USB_D+ bus Disabled. + * | | |1 = Pull-up resistor in USB_D+ bus Active. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * |[11] |LPMACK |LPM Token Acknowledge Enable Bit + * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. + * | | |0= the valid LPM Token will be NYET. + * | | |1= the valid LPM Token will be ACK. + * |[12] |L1SUSPEND |LPM L1 Suspend + * | | |0 = Bus no L1 state suspend. + * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. + * | | |Note: This bit is read only. + * |[13] |L1RESUME |LPM L1 Resume + * | | |0 = Bus no LPM L1 state resume. + * | | |1 = LPM L1 state Resume from LPM L1 state suspend. + * | | |Note: This bit is read only. + * @var USBD_T::VBUSDET + * Offset: 0x14 USB Device VBUS Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDET |Device VBUS Detection + * | | |0 = Controller is not attached to the USB host. + * | | |1 = Controller is attached to the USB host. + * @var USBD_T::STBUFSEG + * Offset: 0x18 SETUP Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is + * | | |USBD_SRAM address + {STBUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::EPSTS0 + * Offset: 0x20 USB Device Endpoint Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[03:00] |EPSTS0 |Endpoint 0 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[07:04] |EPSTS1 |Endpoint 1 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:08] |EPSTS2 |Endpoint 2 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS3 |Endpoint 3 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[19:16] |EPSTS4 |Endpoint 4 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[23:20] |EPSTS5 |Endpoint 5 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[27:24] |EPSTS6 |Endpoint 6 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[31:28] |EPSTS7 |Endpoint 7 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::EPSTS1 + * Offset: 0x24 USB Device Endpoint Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS8 |Endpoint 8 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS9 |Endpoint 9 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS10 |Endpoint 10 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS11 |Endpoint 11 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::LPMATTR + * Offset: 0x88 USB LPM Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LPMLINKSTS|LPM Link State + * | | |These bits contain the bLinkState received with last ACK LPM Token + * |[7:4] |LPMBESL |LPM Best Effort Service Latency + * | | |These bits contain the BESL value received with last ACK LPM Token + * |[8] |LPMRWAKUP |LPM Remote Wakeup + * | | |This bit contains the bRemoteWake value received with last ACK LPM Token + * @var USBD_T::FN + * Offset: 0x8C USB Frame number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FN |Frame Number + * | | |These bits contain the 11-bits frame number in the last received SOF packet. + * @var USBD_T::SE0 + * Offset: 0x90 USB Device Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SE0 |Drive Single Ended Zero in USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = Normal operation. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + + __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ + __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ + __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ + __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ + __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ + __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ + __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ + __I uint32_t EPSTS2; /*!< [0x0028] USB Device Endpoint Status Register 2 */ + __I uint32_t EPSTS3; /*!< [0x002c] USB Device Endpoint Status Register 3 */ + __IO uint32_t EPINTSTS; /*!< [0x0030] USB Device Endpoint Interrupt Event Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[21]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ + __I uint32_t FN; /*!< [0x008c] USB Frame number Register */ + __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[283]; + /// @endcond //HIDDEN_SYMBOLS + USBD_EP_T EP[25]; /*!< [0x500~0x68c] USB End Point 0 ~ 24 Configuration Register */ + +} USBD_T; + + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller +@{ */ + +#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ +#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ + +#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ +#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ + +#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ +#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ + +#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ +#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ + +#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ +#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ + +#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ +#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ + +#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ +#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ + +#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ +#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ + +#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ +#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ + +#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ +#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ + +#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ +#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ + +#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ +#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ + +#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ +#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ + +#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ +#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ + +#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ +#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ + +#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ +#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ + +#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ +#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ + +#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ +#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ + +#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ +#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ + +#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ +#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ + +#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ +#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ + +#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ +#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ + +#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ +#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ + +#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ +#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ + +#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ +#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ + +#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ +#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ + +#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ +#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ +#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ + +#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ +#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ + +#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ +#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ + +#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ +#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ + +#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ +#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ + +#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ +#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ + +#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ +#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ + +#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ +#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ + +#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ +#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ + +#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ +#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ + +#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ +#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ + +#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ +#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ + +#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ +#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ + +#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ +#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ + +#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ +#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ + +#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ +#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ + +#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ +#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ + +#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ +#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ + +#define USBD_EPSTS1_EPSTS12_Pos (16) /*!< USBD_T::EPSTS1: EPSTS12 Position */ +#define USBD_EPSTS1_EPSTS12_Msk (0xful << USBD_EPSTS1_EPSTS12_Pos) /*!< USBD_T::EPSTS1: EPSTS12 Mask */ + +#define USBD_EPSTS1_EPSTS13_Pos (20) /*!< USBD_T::EPSTS1: EPSTS13 Position */ +#define USBD_EPSTS1_EPSTS13_Msk (0xful << USBD_EPSTS1_EPSTS13_Pos) /*!< USBD_T::EPSTS1: EPSTS13 Mask */ + +#define USBD_EPSTS1_EPSTS14_Pos (24) /*!< USBD_T::EPSTS1: EPSTS14 Position */ +#define USBD_EPSTS1_EPSTS14_Msk (0xful << USBD_EPSTS1_EPSTS14_Pos) /*!< USBD_T::EPSTS1: EPSTS14 Mask */ + +#define USBD_EPSTS1_EPSTS15_Pos (28) /*!< USBD_T::EPSTS1: EPSTS15 Position */ +#define USBD_EPSTS1_EPSTS15_Msk (0xful << USBD_EPSTS1_EPSTS15_Pos) /*!< USBD_T::EPSTS1: EPSTS15 Mask */ + +#define USBD_EPSTS2_EPSTS16_Pos (0) /*!< USBD_T::EPSTS2: EPSTS16 Position */ +#define USBD_EPSTS2_EPSTS16_Msk (0xful << USBD_EPSTS2_EPSTS16_Pos) /*!< USBD_T::EPSTS2: EPSTS16 Mask */ + +#define USBD_EPSTS2_EPSTS17_Pos (4) /*!< USBD_T::EPSTS2: EPSTS17 Position */ +#define USBD_EPSTS2_EPSTS17_Msk (0xful << USBD_EPSTS2_EPSTS17_Pos) /*!< USBD_T::EPSTS2: EPSTS17 Mask */ + +#define USBD_EPSTS2_EPSTS18_Pos (8) /*!< USBD_T::EPSTS2: EPSTS18 Position */ +#define USBD_EPSTS2_EPSTS18_Msk (0xful << USBD_EPSTS2_EPSTS18_Pos) /*!< USBD_T::EPSTS2: EPSTS18 Mask */ + +#define USBD_EPSTS2_EPSTS19_Pos (12) /*!< USBD_T::EPSTS2: EPSTS19 Position */ +#define USBD_EPSTS2_EPSTS19_Msk (0xful << USBD_EPSTS2_EPSTS19_Pos) /*!< USBD_T::EPSTS2: EPSTS19 Mask */ + +#define USBD_EPSTS2_EPSTS20_Pos (16) /*!< USBD_T::EPSTS2: EPSTS20 Position */ +#define USBD_EPSTS2_EPSTS20_Msk (0xful << USBD_EPSTS2_EPSTS20_Pos) /*!< USBD_T::EPSTS2: EPSTS20 Mask */ + +#define USBD_EPSTS2_EPSTS21_Pos (20) /*!< USBD_T::EPSTS2: EPSTS21 Position */ +#define USBD_EPSTS2_EPSTS21_Msk (0xful << USBD_EPSTS2_EPSTS21_Pos) /*!< USBD_T::EPSTS2: EPSTS21 Mask */ + +#define USBD_EPSTS2_EPSTS22_Pos (24) /*!< USBD_T::EPSTS2: EPSTS22 Position */ +#define USBD_EPSTS2_EPSTS22_Msk (0xful << USBD_EPSTS2_EPSTS22_Pos) /*!< USBD_T::EPSTS2: EPSTS22 Mask */ + +#define USBD_EPSTS2_EPSTS23_Pos (28) /*!< USBD_T::EPSTS2: EPSTS23 Position */ +#define USBD_EPSTS2_EPSTS23_Msk (0xful << USBD_EPSTS2_EPSTS23_Pos) /*!< USBD_T::EPSTS2: EPSTS23 Mask */ + +#define USBD_EPSTS3_EPSTS24_Pos (0) /*!< USBD_T::EPSTS3: EPSTS24 Position */ +#define USBD_EPSTS3_EPSTS24_Msk (0xful << USBD_EPSTS3_EPSTS24_Pos) /*!< USBD_T::EPSTS3: EPSTS24 Mask */ + +#define USBD_EPINTSTS_EPEVT0_Pos (0) /*!< USBD_T::EPINTSTS: EPEVT0 Position */ +#define USBD_EPINTSTS_EPEVT0_Msk (0x1ul << USBD_EPINTSTS_EPEVT0_Pos) /*!< USBD_T::EPINTSTS: EPEVT0 Mask */ + +#define USBD_EPINTSTS_EPEVT1_Pos (1) /*!< USBD_T::EPINTSTS: EPEVT1 Position */ +#define USBD_EPINTSTS_EPEVT1_Msk (0x1ul << USBD_EPINTSTS_EPEVT1_Pos) /*!< USBD_T::EPINTSTS: EPEVT1 Mask */ + +#define USBD_EPINTSTS_EPEVT2_Pos (2) /*!< USBD_T::EPINTSTS: EPEVT2 Position */ +#define USBD_EPINTSTS_EPEVT2_Msk (0x1ul << USBD_EPINTSTS_EPEVT2_Pos) /*!< USBD_T::EPINTSTS: EPEVT2 Mask */ + +#define USBD_EPINTSTS_EPEVT3_Pos (3) /*!< USBD_T::EPINTSTS: EPEVT3 Position */ +#define USBD_EPINTSTS_EPEVT3_Msk (0x1ul << USBD_EPINTSTS_EPEVT3_Pos) /*!< USBD_T::EPINTSTS: EPEVT3 Mask */ + +#define USBD_EPINTSTS_EPEVT4_Pos (4) /*!< USBD_T::EPINTSTS: EPEVT4 Position */ +#define USBD_EPINTSTS_EPEVT4_Msk (0x1ul << USBD_EPINTSTS_EPEVT4_Pos) /*!< USBD_T::EPINTSTS: EPEVT4 Mask */ + +#define USBD_EPINTSTS_EPEVT5_Pos (5) /*!< USBD_T::EPINTSTS: EPEVT5 Position */ +#define USBD_EPINTSTS_EPEVT5_Msk (0x1ul << USBD_EPINTSTS_EPEVT5_Pos) /*!< USBD_T::EPINTSTS: EPEVT5 Mask */ + +#define USBD_EPINTSTS_EPEVT6_Pos (6) /*!< USBD_T::EPINTSTS: EPEVT6 Position */ +#define USBD_EPINTSTS_EPEVT6_Msk (0x1ul << USBD_EPINTSTS_EPEVT6_Pos) /*!< USBD_T::EPINTSTS: EPEVT6 Mask */ + +#define USBD_EPINTSTS_EPEVT7_Pos (7) /*!< USBD_T::EPINTSTS: EPEVT7 Position */ +#define USBD_EPINTSTS_EPEVT7_Msk (0x1ul << USBD_EPINTSTS_EPEVT7_Pos) /*!< USBD_T::EPINTSTS: EPEVT7 Mask */ + +#define USBD_EPINTSTS_EPEVT8_Pos (8) /*!< USBD_T::EPINTSTS: EPEVT8 Position */ +#define USBD_EPINTSTS_EPEVT8_Msk (0x1ul << USBD_EPINTSTS_EPEVT8_Pos) /*!< USBD_T::EPINTSTS: EPEVT8 Mask */ + +#define USBD_EPINTSTS_EPEVT9_Pos (9) /*!< USBD_T::EPINTSTS: EPEVT9 Position */ +#define USBD_EPINTSTS_EPEVT9_Msk (0x1ul << USBD_EPINTSTS_EPEVT9_Pos) /*!< USBD_T::EPINTSTS: EPEVT9 Mask */ + +#define USBD_EPINTSTS_EPEVT10_Pos (10) /*!< USBD_T::EPINTSTS: EPEVT10 Position */ +#define USBD_EPINTSTS_EPEVT10_Msk (0x1ul << USBD_EPINTSTS_EPEVT10_Pos) /*!< USBD_T::EPINTSTS: EPEVT10 Mask */ + +#define USBD_EPINTSTS_EPEVT11_Pos (11) /*!< USBD_T::EPINTSTS: EPEVT11 Position */ +#define USBD_EPINTSTS_EPEVT11_Msk (0x1ul << USBD_EPINTSTS_EPEVT11_Pos) /*!< USBD_T::EPINTSTS: EPEVT11 Mask */ + +#define USBD_EPINTSTS_EPEVT12_Pos (12) /*!< USBD_T::EPINTSTS: EPEVT12 Position */ +#define USBD_EPINTSTS_EPEVT12_Msk (0x1ul << USBD_EPINTSTS_EPEVT12_Pos) /*!< USBD_T::EPINTSTS: EPEVT12 Mask */ + +#define USBD_EPINTSTS_EPEVT13_Pos (13) /*!< USBD_T::EPINTSTS: EPEVT13 Position */ +#define USBD_EPINTSTS_EPEVT13_Msk (0x1ul << USBD_EPINTSTS_EPEVT13_Pos) /*!< USBD_T::EPINTSTS: EPEVT13 Mask */ + +#define USBD_EPINTSTS_EPEVT14_Pos (14) /*!< USBD_T::EPINTSTS: EPEVT14 Position */ +#define USBD_EPINTSTS_EPEVT14_Msk (0x1ul << USBD_EPINTSTS_EPEVT14_Pos) /*!< USBD_T::EPINTSTS: EPEVT14 Mask */ + +#define USBD_EPINTSTS_EPEVT15_Pos (15) /*!< USBD_T::EPINTSTS: EPEVT15 Position */ +#define USBD_EPINTSTS_EPEVT15_Msk (0x1ul << USBD_EPINTSTS_EPEVT15_Pos) /*!< USBD_T::EPINTSTS: EPEVT15 Mask */ + +#define USBD_EPINTSTS_EPEVT16_Pos (16) /*!< USBD_T::EPINTSTS: EPEVT16 Position */ +#define USBD_EPINTSTS_EPEVT16_Msk (0x1ul << USBD_EPINTSTS_EPEVT16_Pos) /*!< USBD_T::EPINTSTS: EPEVT16 Mask */ + +#define USBD_EPINTSTS_EPEVT17_Pos (17) /*!< USBD_T::EPINTSTS: EPEVT17 Position */ +#define USBD_EPINTSTS_EPEVT17_Msk (0x1ul << USBD_EPINTSTS_EPEVT17_Pos) /*!< USBD_T::EPINTSTS: EPEVT17 Mask */ + +#define USBD_EPINTSTS_EPEVT18_Pos (18) /*!< USBD_T::EPINTSTS: EPEVT18 Position */ +#define USBD_EPINTSTS_EPEVT18_Msk (0x1ul << USBD_EPINTSTS_EPEVT18_Pos) /*!< USBD_T::EPINTSTS: EPEVT18 Mask */ + +#define USBD_EPINTSTS_EPEVT19_Pos (19) /*!< USBD_T::EPINTSTS: EPEVT19 Position */ +#define USBD_EPINTSTS_EPEVT19_Msk (0x1ul << USBD_EPINTSTS_EPEVT19_Pos) /*!< USBD_T::EPINTSTS: EPEVT19 Mask */ + +#define USBD_EPINTSTS_EPEVT20_Pos (20) /*!< USBD_T::EPINTSTS: EPEVT20 Position */ +#define USBD_EPINTSTS_EPEVT20_Msk (0x1ul << USBD_EPINTSTS_EPEVT20_Pos) /*!< USBD_T::EPINTSTS: EPEVT20 Mask */ + +#define USBD_EPINTSTS_EPEVT21_Pos (21) /*!< USBD_T::EPINTSTS: EPEVT21 Position */ +#define USBD_EPINTSTS_EPEVT21_Msk (0x1ul << USBD_EPINTSTS_EPEVT21_Pos) /*!< USBD_T::EPINTSTS: EPEVT21 Mask */ + +#define USBD_EPINTSTS_EPEVT22_Pos (22) /*!< USBD_T::EPINTSTS: EPEVT22 Position */ +#define USBD_EPINTSTS_EPEVT22_Msk (0x1ul << USBD_EPINTSTS_EPEVT22_Pos) /*!< USBD_T::EPINTSTS: EPEVT22 Mask */ + +#define USBD_EPINTSTS_EPEVT23_Pos (23) /*!< USBD_T::EPINTSTS: EPEVT23 Position */ +#define USBD_EPINTSTS_EPEVT23_Msk (0x1ul << USBD_EPINTSTS_EPEVT23_Pos) /*!< USBD_T::EPINTSTS: EPEVT23 Mask */ + +#define USBD_EPINTSTS_EPEVT24_Pos (24) /*!< USBD_T::EPINTSTS: EPEVT24 Position */ +#define USBD_EPINTSTS_EPEVT24_Msk (0x1ul << USBD_EPINTSTS_EPEVT24_Pos) /*!< USBD_T::EPINTSTS: EPEVT24 Mask */ + +#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ +#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ + +#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ +#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ + +#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ +#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ + +#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ +#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ + +#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ +#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ + +#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ +#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ + +#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ +#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ + +#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFG_DBTGACTIVE_Pos (10) /*!< USBD_EP_T::CFG: DBTGACTIVE Position */ +#define USBD_CFG_DBTGACTIVE_Msk (0x1ul << USBD_CFG_DBTGACTIVE_Pos) /*!< USBD_EP_T::CFG: DBTGACTIVE Mask */ + +#define USBD_CFG_DBEN_Pos (11) /*!< USBD_EP_T::CFG: DBEN Position */ +#define USBD_CFG_DBEN_Msk (0x1ul << USBD_CFG_DBEN_Pos) /*!< USBD_EP_T::CFG: DBEN Mask */ + +#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +/**@}*/ /* USBD_CONST */ +/**@}*/ /* end of USBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBD_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/usbh_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/usbh_reg.h new file mode 100644 index 0000000..01dcffe --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/usbh_reg.h @@ -0,0 +1,797 @@ +/**************************************************************************//** + * @file usbh_reg.h + * @version V1.00 + * @brief USBH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBH_REG_H__ +#define __USBH_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBH USB Host Controller(USBH) + Memory Mapped Structure for USBH Controller +@{ */ + +typedef struct +{ + + /** + * @var USBH_T::HcRevision + * Offset: 0x00 Host Controller Revision Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REV |Revision Number + * | | |Indicates the Open HCI Specification revision number implemented by the Hardware + * | | |Host Controller supports 1.1 specification. + * | | |(X.Y = XYh). + * @var USBH_T::HcControl + * Offset: 0x04 Host Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CBSR |Control Bulk Service Ratio + * | | |This specifies the service ratio between Control and Bulk EDs + * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs + * | | |The internal count will be retained when crossing the frame boundary + * | | |In case of reset, HCD is responsible for restoring this + * | | |Value. + * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. + * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. + * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. + * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. + * |[2] |PLE |Periodic List Enable Bit + * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list + * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. + * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. + * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. + * |[3] |IE |Isochronous List Enable Bit + * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list + * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. + * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. + * |[4] |CLE |Control List Enable Bit + * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Control list in the next frame Enabled. + * |[5] |BLE |Bulk List Enable Bit + * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Bulk list in the next frame Enabled. + * |[7:6] |HCFS |Host Controller Functional State + * | | |This field sets the Host Controller state + * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port + * | | |States are: + * | | |00 = USBSUSPEND. + * | | |01 = USBOPERATIONAL. + * | | |10 = USBRESUME. + * | | |11 = USBRESET. + * @var USBH_T::HcCommandStatus + * Offset: 0x08 Host Controller Command Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HCR |Host Controller Reset + * | | |This bit is set to initiate the software reset of Host Controller + * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. + * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. + * | | |0 = Host Controller is not in software reset state. + * | | |1 = Host Controller is in software reset state. + * |[1] |CLF |Control List Filled + * | | |Set high to indicate there is an active TD on the Control List + * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. + * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. + * | | |1 = An active TD added or found on the Control list. + * |[2] |BLF |Bulk List Filled + * | | |Set high to indicate there is an active TD on the Bulk list + * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. + * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. + * | | |1 = An active TD added or found on the Bulk list. + * |[17:16] |SOC |Schedule Overrun Count + * | | |These bits are incremented on each scheduling overrun error + * | | |It is initialized to 00b and wraps around at 11b + * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. + * @var USBH_T::HcInterruptStatus + * Offset: 0x0C Host Controller Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun + * | | |Set when the List Processor determines a Schedule Overrun has occurred. + * | | |0 = Schedule Overrun didn't occur. + * | | |1 = Schedule Overrun has occurred. + * |[1] |WDH |Write Back Done Head + * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead + * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. + * | | |0 =.Host Controller didn't update HccaDoneHead. + * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead. + * |[2] |SF |Start of Frame + * | | |Set when the Frame Management functional block signals a 'Start of Frame' event + * | | |Host Control generates a SOF token at the same time. + * | | |0 =.Not the start of a frame. + * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token. + * |[3] |RD |Resume Detected + * | | |Set when Host Controller detects resume signaling on a downstream port. + * | | |0 = No resume signaling detected on a downstream port. + * | | |1 = Resume signaling detected on a downstream port. + * |[5] |FNO |Frame Number Overflow + * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |0 = The bit 15 of Frame Number didn't change. + * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * |[6] |RHSC |Root Hub Status Change + * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. + * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. + * @var USBH_T::HcInterruptEnable + * Offset: 0x10 Host Controller Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Enable Bit + * | | |This bit is a global interrupt enable + * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcInterruptDisable + * Offset: 0x14 Host Controller Interrupt Disable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Disable Bit + * | | |Global interrupt disable. Writing '1' to disable all interrupts. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcHCCA + * Offset: 0x18 Host Controller Communication Area Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:8] |HCCA |Host Controller Communication Area + * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA). + * @var USBH_T::HcPeriodCurrentED + * Offset: 0x1C Host Controller Period Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |PCED |Periodic Current ED + * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor. + * @var USBH_T::HcControlHeadED + * Offset: 0x20 Host Controller Control Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CHED |Control Head ED + * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list. + * @var USBH_T::HcControlCurrentED + * Offset: 0x24 Host Controller Control Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CCED |Control Current Head ED + * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. + * @var USBH_T::HcBulkHeadED + * Offset: 0x28 Host Controller Bulk Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BHED |Bulk Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. + * @var USBH_T::HcBulkCurrentED + * Offset: 0x2C Host Controller Bulk Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BCED |Bulk Current Head ED + * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. + * @var USBH_T::HcDoneHead + * Offset: 0x30 Host Controller Done Head Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |DH |Done Head + * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. + * @var USBH_T::HcFmInterval + * Offset: 0x34 Host Controller Frame Interval Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Interval + * | | |This field specifies the length of a frame as (bit times - 1) + * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. + * |[30:16] |FSMPS |FS Largest Data Packet + * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. + * |[31] |FIT |Frame Interval Toggle + * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). + * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). + * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). + * @var USBH_T::HcFmRemaining + * Offset: 0x38 Host Controller Frame Remaining Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FR |Frame Remaining + * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period + * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval + * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. + * |[31] |FRT |Frame Remaining Toggle + * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. + * @var USBH_T::HcFmNumber + * Offset: 0x3C Host Controller Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FN |Frame Number + * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) + * | | |The count rolls over from 'FFFFh' to '0h.' + * @var USBH_T::HcPeriodicStart + * Offset: 0x40 Host Controller Periodic Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PS |Periodic Start + * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. + * @var USBH_T::HcLSThreshold + * Offset: 0x44 Host Controller Low-speed Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |LST |Low-speed Threshold + * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction + * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field + * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. + * @var USBH_T::HcRhDescriptorA + * Offset: 0x48 Host Controller Root Hub Descriptor A Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NDP |Number Downstream Ports + * | | |USB host control supports two downstream ports and only one port is available in this series of chip. + * |[8] |PSM |Power Switching Mode + * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. + * | | |0 = Global Switching. + * | | |1 = Individual Switching. + * |[11] |OCPM |over Current Protection Mode + * | | |This bit describes how the over current status for the Root Hub ports reported + * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. + * | | |0 = Global Over current. + * | | |1 = Individual Over current. + * |[12] |NOCP |No over Current Protection + * | | |This bit describes how the over current status for the Root Hub ports reported. + * | | |0 = Over current status is reported. + * | | |1 = Over current status is not reported. + * @var USBH_T::HcRhDescriptorB + * Offset: 0x4C Host Controller Root Hub Descriptor B Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |PPCM |Port Power Control Mask + * | | |Global power switching + * | | |This field is only valid if PowerSwitchingMode is set (individual port switching) + * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower) + * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower). + * | | |0 = Port power controlled by global power switching. + * | | |1 = Port power controlled by port power switching. + * | | |Note: PPCM[15:2] and PPCM[0] are reserved. + * @var USBH_T::HcRhStatus + * Offset: 0x50 Host Controller Root Hub Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPS |Clear Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear global power. + * |[1] |OCI |over Current Indicator + * | | |This bit reflects the state of the over current status pin + * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared. + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[15] |DRWE |Device Remote Wakeup Enable Bit + * | | |This bit controls if port's Connect Status Change as a remote wake-up event. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * | | |Read Operation: + * | | |0 = Connect Status Change as a remote wake-up event Disabled. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * |[16] |LPSC |Set Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set global power. + * |[17] |OCIC |over Current Indicator Change + * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). + * | | |Write 1 to clear this bit to zero. + * | | |0 = OCI (HcRhStatus[1]) didn't change. + * | | |1 = OCI (HcRhStatus[1]) change. + * |[31] |CRWE |Clear Remote Wake-up Enable Bit + * | | |This bit is use to clear DRWE (HcRhStatus[15]). + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear DRWE (HcRhStatus[15]). + * @var USBH_T::HcRhPortStatus[2] + * Offset: 0x54 Host Controller Root Hub Port Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |CurrentConnectStatus (Read) or ClearPortEnable Bit (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port enable. + * | | |Read Operation: + * | | |0 = No device connected. + * | | |1 = Device connected. + * |[1] |PES |Port Enable Status + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port enable. + * | | |Read Operation: + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[2] |PSS |Port Suspend Status + * | | |This bit indicates the port is suspended + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port suspend. + * | | |Read Operation: + * | | |0 = Port is not suspended. + * | | |1 = Port is selectively suspended. + * |[3] |POCI |Port over Current Indicator (Read) or Clear Port Suspend (Write) + * | | |This bit reflects the state of the over current status pin dedicated to this port + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. + * | | |This bit is also used to initiate the selective result sequence for the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port suspend. + * | | |Read Operation: + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[4] |PRS |Port Reset Status + * | | |This bit reflects the reset state of the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port reset. + * | | |Read Operation + * | | |0 = Port reset signal is not active. + * | | |1 = Port reset signal is active. + * |[8] |PPS |Port Power Status + * | | |This bit reflects the power state of the port regardless of the power switching mode. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Port Power Enabled. + * | | |Read Operation: + * | | |0 = Port power is Disabled. + * | | |1 = Port power is Enabled. + * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) + * | | |This bit defines the speed (and bud idle) of the attached device + * | | |It is only valid when CCS (HcRhPortStatus1[0]) is set. + * | | |This bit is also used to clear port power. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear PPS (HcRhPortStatus1[8]). + * | | |Read Operation: + * | | |0 = Full Speed device. + * | | |1 = Low-speed device. + * |[16] |CSC |Connect Status Change + * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed). + * | | |Write 1 to clear this bit to zero. + * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change). + * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed). + * |[17] |PESC |Port Enable Status Change + * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event. + * | | |Write 1 to clear this bit to zero. + * | | |0 = PES (HcRhPortStatus1[1]) didn't change. + * | | |1 = PES (HcRhPortStatus1[1]) changed. + * |[18] |PSSC |Port Suspend Status Change + * | | |This bit indicates the completion of the selective resume sequence for the port. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port resume is not completed. + * | | |1 = Port resume completed. + * |[19] |OCIC |Port over Current Indicator Change + * | | |This bit is set when POCI (HcRhPortStatus1[3]) changes. + * | | |Write 1 to clear this bit to zero. + * | | |0 = POCI (HcRhPortStatus1[3]) didn't change. + * | | |1 = POCI (HcRhPortStatus1[3]) changes. + * |[20] |PRSC |Port Reset Status Change + * | | |This bit indicates that the port reset signal has completed. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port reset is not complete. + * | | |1 = Port reset is complete. + * @var USBH_T::HcPhyControl + * Offset: 0x200 Host Controller PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |STBYEN |USB Transceiver Standby Enable Bit + * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. + * | | |0 = The USB transceiver would never enter the standby mode. + * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). + * @var USBH_T::HcMiscControl + * Offset: 0x204 Host Controller Miscellaneous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABORT |AHB Bus ERROR Response + * | | |This bit indicates there is an ERROR response received in AHB bus. + * | | |0 = No ERROR response received. + * | | |1 = ERROR response received. + * |[3] |OCAL |over Current Active Low + * | | |This bit controls the polarity of over current flag from external power IC. + * | | |0 = Over current flag is high active. + * | | |1 = Over current flag is low active. + * |[16] |DPRT1 |Disable Port 1 + * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled + * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. + * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. + * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. + * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. + */ + __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ + __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ + __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ + __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ + __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ + __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ + __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ + __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ + __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ + __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ + __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ + __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ + __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ + __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ + __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ + __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ + __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ + __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ + __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ + __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ + __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ + __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status [1] */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[105]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ + __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ + +} USBH_T; + +/** + @addtogroup USBH_CONST USBH Bit Field Definition + Constant Definitions for USBH Controller +@{ */ + +#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ +#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ + +#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ +#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ + +#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ +#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ + +#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ +#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ + +#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ +#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ + +#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ +#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ + +#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ +#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ + +#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ +#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ + +#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ +#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ + +#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ +#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ + +#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ +#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ + +#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ +#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ + +#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ +#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ + +#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ +#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ + +#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ +#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ + +#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ +#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ + +#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ +#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ + +#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ +#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ + +#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ +#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ + +#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ +#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ + +#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ +#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ + +#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ +#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ + +#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ +#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ + +#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ +#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ + +#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ +#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ + +#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ +#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ + +#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ +#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ + +#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ +#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ + +#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ +#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ + +#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ +#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ + +#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ +#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ + +#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ +#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ + +#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ +#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ + +#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ +#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ + +#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ +#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ + +#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ +#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ + +#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ +#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ + +#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ +#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ + +#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ +#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ + +#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ +#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ + +#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ +#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ + +#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ +#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ + +#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ +#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ + +#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ +#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ + +#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ +#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ + +#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ +#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ + +#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ +#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ + +#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ +#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ + +#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ +#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ + +#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ +#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ + +#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ +#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ + +#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ +#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ + +#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ +#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ + +#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ +#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ + +#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ +#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ + +#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ +#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ + +#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ +#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ + +#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */ +#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */ + +#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */ +#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */ + +#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */ +#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */ + +#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */ +#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */ + +#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */ +#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */ + +#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */ +#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */ + +#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */ +#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */ + +#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */ +#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */ + +#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */ +#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */ + +#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */ +#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */ + +#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */ +#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */ + +#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */ +#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */ + +#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ +#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ + +#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ +#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ + +#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ +#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ + +#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ +#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ + +/**@}*/ /* USBH_CONST */ +/**@}*/ /* end of USBH register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USBH_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uspi_reg.h new file mode 100644 index 0000000..d9a2d30 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uspi_reg.h @@ -0,0 +1,677 @@ +/**************************************************************************//** + * @file uspi_reg.h + * @version V1.00 + * @brief USPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USPI_REG_H__ +#define __USPI_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USPI SPI Mode of USCI Controller(USPI) + Memory Mapped Structure for USPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var USPI_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var USPI_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var USPI_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fDIV_CLK. + * | | |01 = fPROT_CLK. + * | | |10 = fSCLK. + * | | |11 = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var USPI_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var USPI_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. + * | | |0 = Data output level is not inverted. + * | | |1 = Data output level is inverted. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: The control signal has different definitions in different protocol + * | | |In SPI protocol, the control signal means slave select signal + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * @var USPI_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission + * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. + * |[16] |PORTDIR |Port Direction Control + * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer + * | | |It is used to define the direction of the data port pin + * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. + * | | |0 = The data pin is configured as output mode. + * | | |1 = The data pin is configured as input mode. + * @var USPI_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * @var USPI_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit + * | | |0 = Transmit under-run interrupt Disabled. + * | | |1 = Transmit under-run interrupt Enabled. + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * @var USPI_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status + * | | |This bit indicates that a receive buffer overrun event has been detected + * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun event has not been detected. + * | | |1 = A receive buffer overrun event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty and available for the next transmission datum. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status + * | | |This bit indicates that a transmit buffer under-run event has been detected + * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run event has not been detected. + * | | |1 = A transmit buffer under-run event has been detected. + * @var USPI_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * | | |Notice: The I2C is not supporting PDMA function. + * @var USPI_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var USPI_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var USPI_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLAVE |Slave Mode Selection + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) + * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[2] |SS |Slave Select Control (Master Only) + * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. + * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. + * | | |Note: In SPI protocol, the internal slave select signal is active high. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. + * | | |1 = Slave select signal will be generated automatically + * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. + * |[7:6] |SCLKMODE |Serial Bus Clock Mode + * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. + * | | |MODE0 = The idle state of SPI clock is low level + * | | |Data is transmitted with falling edge and received with rising edge. + * | | |MODE1 = The idle state of SPI clock is low level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE2 = The idle state of SPI clock is high level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE3 = The idle state of SPI clock is high level + * | | |Data is transmitted with falling edge and received with rising edge. + * |[11:8] |SUSPITV |Suspend Interval (Master Only) + * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle. + * |[14:12] |TSMSEL |Transmit Data Mode Selection + * | | |This bit field describes how receive and transmit data is shifted in and out. + * | | |TSMSEL = 000b: Full-duplex SPI. + * | | |TSMSEL = 100b: Half-duplex SPI. + * | | |Other values are reserved. + * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. + * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) + * | | |In Slave mode, this bit field is used for Slave time-out period + * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event + * | | |Writing 0x0 into this bit field will disable the Slave time-out function. + * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. + * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave) + * | | |This bit defines the transmitting data level when no data is available for transferring. + * | | |0 = The output data level is 0 if TX under run event occurs. + * | | |1 = The output data level is 1 if TX under run event occurs. + * |[31] |PROTEN |SPI Protocol Enable Bit + * | | |0 = SPI Protocol Disabled. + * | | |1 = SPI Protocol Enabled. + * @var USPI_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. + * | | |0 = Slave select inactive interrupt generation Disabled. + * | | |1 = Slave select inactive interrupt generation Enabled. + * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. + * | | |0 = Slave select active interrupt generation Disabled. + * | | |1 = Slave select active interrupt generation Enabled. + * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control + * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. + * | | |0 = The Slave time-out interrupt Disabled. + * | | |1 = The Slave time-out interrupt Enabled. + * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control + * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) + * | | |Bit count error event occurs. + * | | |0 = The Slave mode bit count error interrupt Disabled. + * | | |1 = The Slave mode bit count error interrupt Enabled. + * @var USPI_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = Transmit start event does not occur. + * | | |1 = Transmit start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = Transmit end event does not occur. + * | | |1 = Transmit end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = Receive start event does not occur. + * | | |1 = Receive start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = Receive end event does not occur. + * | | |1 = Receive end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only) + * | | |0 = Slave time-out event does not occur. + * | | |1 = Slave time-out event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only) + * | | |0 = Slave bit count error event does not occur. + * | | |1 = Slave bit count error event occurs. + * | | |Note: It is cleared by software writes 1 to this bit. + * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to inactive + * | | |It is cleared by software writes 1 to this bit + * | | |0 = The slave select signal has not changed to inactive. + * | | |1 = The slave select signal has changed to inactive. + * | | |Note: The internal slave select signal is active high. + * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to active + * | | |It is cleared by software writes one to this bit + * | | |0 = The slave select signal has not changed to active. + * | | |1 = The slave select signal has changed to active. + * | | |Note: The internal slave select signal is active high. + * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |This bit is only available in Slave mode + * | | |It used to monitor the current status of the input slave select signal on the bus. + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * |[17] |BUSY |Busy Status (Read Only) + * | | |0 = SPI is in idle state. + * | | |1 = SPI is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. + * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) + * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 + * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. + * | | |0 = Slave transmit under-run event does not occur. + * | | |1 = Slave transmit under-run event occurs. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} USPI_T; + +/** + @addtogroup USPI_CONST USPI Bit Field Definition + Constant Definitions for USPI Controller +@{ */ + +#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ +#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ + +#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ +#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ + +#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ +#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ + +#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ +#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ + +#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ +#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ + +#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ +#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ + +#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ +#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ + +#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ +#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ + +#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ +#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ + +#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ +#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ + +#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ +#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ + +#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ +#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ + +#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ +#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ + +#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ +#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ + +#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ +#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ + +#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ +#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ + +#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ +#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ + +#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ +#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ + +#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ +#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ + +#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ +#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ + +#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ +#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ + +#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ +#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ + +#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ +#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ + +#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ +#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ + +#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ +#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ + +#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ +#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ + +#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ +#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ + +#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ +#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ + +#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ +#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ + +#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ +#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ + +#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ +#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ + +#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ +#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ + +#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ +#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ + +#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ +#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ + +#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ +#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ + +#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ +#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ + +#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ +#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ + +#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ +#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ + +#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ +#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ + +#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ +#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ + +#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ +#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ + +#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ +#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ + +#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ +#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ + +#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ +#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ + +#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ +#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ + +#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ +#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ + +#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ +#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ + +#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ +#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ + +#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ +#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ + +#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ +#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ + +#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ +#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ + +#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ +#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ + +#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ +#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ + +#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ +#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ + +#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ +#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ + +#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ +#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ + +#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ +#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ + +#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ +#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ + +#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ +#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ + +#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ +#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ + +#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ +#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ + +#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ +#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ + +#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ +#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ + +#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ +#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ + +#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ +#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ + +#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ +#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ + +#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ +#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ + +#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ +#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ + +/**@}*/ /* USPI_CONST */ +/**@}*/ /* end of USPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __USPI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uuart_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uuart_reg.h new file mode 100644 index 0000000..bc53c5d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/uuart_reg.h @@ -0,0 +1,689 @@ +/**************************************************************************//** + * @file uuart_reg.h + * @version V3.00 + * @brief UUART register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UUART_REG_H__ +#define __UUART_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UUART UART Mode of USCI Controller(UUART) + Memory Mapped Structure for UUART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UUART_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller. + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI. + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol. + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Others = Reserved. + * @var UUART_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var UUART_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK is selected to fDIV_CLK. + * | | |01 = fSAMP_CLK is selected to fPROT_CLK. + * | | |10 = fSAMP_CLK is selected to fSCLK. + * | | |11 = fSAMP_CLK is selected to fREF_CLK. + * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Timing measurement counter is Disabled. + * | | |1 = Timing measurement counter is Enabled. + * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection + * | | |0 = Timing measurement counter with fPROT_CLK. + * | | |1 = Timing measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK. + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USCI_PROTCTL[6])) is enabled. + * | | |The revised value is the average bit time between bit 5 and bit 6. + * | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UUART_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * |[4:3] |EDGEDET |Input Signal Edge Detection Mode + * | | |This bit field selects which edge actives the trigger event of input data signal. + * | | |00 = The trigger event activation is disabled. + * | | |01 = A rising edge activates the trigger event of input data signal. + * | | |10 = A falling edge activates the trigger event of input data signal. + * | | |11 = Both edges activate the trigger event of input data signal. + * | | |Note: In UART function mode, it is suggested to set this bit field as 0x2. + * @var UUART_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var UUART_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * @var UUART_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. + * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. + * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: In UART protocol, the control signal means nRTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission. + * | | |The data word is always right-aligned in the data buffer. + * | | |USCI support word length from 4 to 16 bits. + * | | |0000 = The data word contains 16 bits located at bit positions [15:0]. + * | | |0001 = Reserved. + * | | |0010 = Reserved. + * | | |0011 = Reserved. + * | | |0100 = The data word contains 4 bits located at bit positions [3:0]. + * | | |0101 = The data word contains 5 bits located at bit positions [4:0]. + * | | |0110 = The data word contains 6 bits located at bit positions [5:0]. + * | | |0111 = The data word contains 7 bits located at bit positions [6:0]. + * | | |1000 = The data word contains 8 bits located at bit positions [7:0]. + * | | |1001 = The data word contains 9 bits located at bit positions [8:0]. + * | | |1010 = The data word contains 10 bits located at bit positions [9:0]. + * | | |1011 = The data word contains 11 bits located at bit positions [10:0]. + * | | |1100 = The data word contains 12 bits located at bit positions [11:0]. + * | | |1101 = The data word contains 13 bits located at bit positions [12:0]. + * | | |1110 = The data word contains 14 bits located at bit positions [13:0]. + * | | |1111 = The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UUART_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UUART_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (USCI_PROTSTS[7:5]). + * @var UUART_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note 1: It is cleared automatically after one PCLK cycle. + * | | |Note 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. + * @var UUART_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status + * | | |This bit indicates that a receive buffer overrun error event has been detected. + * | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun error event has not been detected. + * | | |1 = A receive buffer overrun error event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * @var UUART_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * @var UUART_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var UUART_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1. + * | | |Software can write 1 to clear this bit. + * @var UUART_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STOPB |Stop Bits + * | | |This bit defines the number of stop bits in an UART frame. + * | | |0 = The number of stop bits is 1. + * | | |1 = The number of stop bits is 2. + * |[1] |PARITYEN |Parity Enable Bit + * | | |This bit defines the parity bit is enabled in an UART frame. + * | | |0 = The parity bit Disabled. + * | | |1 = The parity bit Enabled. + * |[2] |EVENPARITY|Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PARITYEN is set. + * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit + * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal. + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: This bit has effect only when the RTSAUDIREN is not set. + * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit + * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit + * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. + * | | |0 = nRTS auto direction control Disabled. + * | | |1 = nRTS auto direction control Enabled. + * | | |Note 1: This bit is used for nRTS auto direction control for RS485. + * | | |Note 2: This bit has effect only when the RTSAUTOEN is not set. + * |[6] |ABREN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note: When the auto-baud rate detect operation finishes, hardware will clear this bit. + * | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). + * |[9] |DATWKEN |Data Wake-up Mode Enable Bit + * | | |0 = Data wake-up mode Disabled. + * | | |1 = Data wake-up mode Enabled. + * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit + * | | |0 = nCTS wake-up mode Disabled. + * | | |1 = nCTS wake-up mode Enabled. + * |[14:11] |WAKECNT |Wake-up Counter + * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. + * |[24:16] |BRDETITV |Baud Rate Detection Interval + * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. + * | | |The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). + * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. + * | | |Note: This bit can be cleared to 0 by software writing '0' to the BRDETITV. + * |[26] |STICKEN |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: Refer to RS-485 Support section for detail information. + * |[29] |BCEN |Transmit Break Control Enable Bit + * | | |0 = Transmit Break Control Disabled. + * | | |1 = Transmit Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[30] |DGE |Deglitch Enable Bit + * | | |0 = Deglitch Disabled. + * | | |1 = Deglitch Enabled. + * | | |Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). + * | | |This bit acts only on RX line and has no effect on the transmitter logic. + * | | |Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps. + * |[31] |PROTEN |UART Protocol Enable Bit + * | | |0 = UART Protocol Disabled. + * | | |1 = UART Protocol Enabled. + * @var UUART_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive line status interrupt Disabled. + * | | |1 = Receive line status interrupt Enabled. + * | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. + * @var UUART_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = A transmit start interrupt status has not occurred. + * | | |1 = A transmit start interrupt status has occurred. + * | | |Note 1: It is cleared by software writing one into this bit. + * | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer. + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = A transmit end interrupt status has not occurred. + * | | |1 = A transmit end interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = A receive start interrupt status has not occurred. + * | | |1 = A receive start interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = A receive finish interrupt status has not occurred. + * | | |1 = A receive finish interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[5] |PARITYERR |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[6] |FRMERR |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid 'stop bit'(that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[7] |BREAK |Break Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' + * | | |(logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break is generated. + * | | |1 = Break is generated in the receiver bus. + * | | |Note: This bit can be cleared by write '1' among the BREAK, FRMERR and PARITYERR bits. + * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag + * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data. + * | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. + * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. + * | | |0 = Auto-baud rate detect function is not done. + * | | |1 = One Bit auto-baud rate detect function is done. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[10] |RXBUSY |RX Bus Status Flag (Read Only) + * | | |This bit indicates the busy status of the receiver. + * | | |0 = The receiver is Idle. + * | | |1 = The receiver is BUSY. + * |[11] |ABERRSTS |Auto-baud Rate Error Status + * | | |This bit is set when auto-baud rate detection counter overrun + * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. + * | | |0 = Auto-baud rate detect counter is not overrun. + * | | |1 = Auto-baud rate detect counter is overrun. + * | | |Note 1: This bit is set at the same time of ABRDETIF. + * | | |Note 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS. + * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) + * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. + * | | |0 = The internal synchronized nCTS is low. + * | | |1 = The internal synchronized nCTS is high. + * |[17] |CTSLV |nCTS Pin Status (Read Only) + * | | |This bit used to monitor the current status of nCTS pin input. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE2[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __IO uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __IO uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE3[4]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} UUART_T; + +/** + @addtogroup UUART_CONST UUART Bit Field Definition + Constant Definitions for UUART Controller +@{ */ + +#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ +#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ + +#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ +#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ + +#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ +#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ + +#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ +#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ + +#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ +#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ + +#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ +#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ + +#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ +#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ + +#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ +#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ + +#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ +#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ + +#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ +#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ + +#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ +#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ + +#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ +#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ + +#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ +#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ + +#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ +#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ + +#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ +#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ + +#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ +#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ + +#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ +#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ + +#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ +#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ + +#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ +#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ + +#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ +#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ + +#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ +#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ + +#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ +#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ + +#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ +#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ + +#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ +#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ + +#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ +#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ + +#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ +#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ + +#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ +#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ + +#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ +#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ + +#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ +#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ + +#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ +#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ + +#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ +#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ + +#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ +#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ + +#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ +#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ + +#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ +#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ + +#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ +#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ + +#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ +#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ + +#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ +#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ + +#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ +#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ + +#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ +#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ + +#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ +#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ + +#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ +#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ + +#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ +#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ + +#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ +#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ + +#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ +#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ + +#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ +#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ + +#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ +#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ + +#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ +#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ + +#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ +#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ + +#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ +#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ + +#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ +#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ + +#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ +#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ + +#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ +#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ + +#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ +#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ + +#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ +#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ + +#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ +#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ + +#define UUART_PROTCTL_DGE_Pos (30) /*!< UUART_T::PROTCTL: DGE Position */ +#define UUART_PROTCTL_DGE_Msk (0x1ul << UUART_PROTCTL_DGE_Pos) /*!< UUART_T::PROTCTL: DGE Mask */ + +#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ +#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ + +#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ +#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ + +#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ +#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ + +#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ +#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ + +#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ +#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ + +#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ +#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ + +#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ +#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ + +#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ +#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ + +#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ +#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ + +#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ +#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ + +#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ +#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ + +#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ +#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ + +#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ +#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ + +#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ +#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ + +#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ +#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ + +/**@}*/ /* UUART_CONST */ +/**@}*/ /* end of UUART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __UUART_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/wdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/wdt_reg.h new file mode 100644 index 0000000..330b16e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/wdt_reg.h @@ -0,0 +1,176 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @version V3.00 + * @brief WDT register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Watch Dog Timer Controller -------------------------*/ +/** + @addtogroup WDT Watch Dog Timer Controller(WDT) + Memory Mapped Structure for WDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset function Disabled. + * | | |1 = WDT time-out reset function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset or not. + * | | |0 = WDT time-out reset did not occur. + * | | |1 = WDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval + * | | |0 = WDT time-out interrupt did not occur. + * | | |1 = WDT time-out interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. + * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. + * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the interrupt wake-up flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Bit (Write Protect) + * | | |0 = WDT Disabled (This action will reset the internal up counter value). + * | | |1 = WDT Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. + * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period for the WDT. + * | | |000 = 2^4 * WDT_CLK. + * | | |001 = 2^6 * WDT_CLK. + * | | |010 = 2^8 * WDT_CLK. + * | | |011 = 2^10 * WDT_CLK. + * | | |100 = 2^12 * WDT_CLK. + * | | |101 = 2^14 * WDT_CLK. + * | | |110 = 2^16 * WDT_CLK. + * | | |111 = 2^18 * WDT_CLK. + * | | |111 = 2^20 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) + * | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. + * | | |0 = Setting WDTEN bit is completed and WDT is ready. + * | | |1 = Setting WDTEN bit is synchronizing and not become active yet. + * | | |Note: Perform enable or disable WDTEN bit needs 4 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) + * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to prevent WDT time-out reset happened. + * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ + +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller + @{ +*/ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ +#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ + + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WDT_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/wwdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/wwdt_reg.h new file mode 100644 index 0000000..fc13fc9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/Reg/wwdt_reg.h @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @version V3.00 + * @brief WWDT register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/** @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Window Watchdog Timer -------------------------*/ +/** + @addtogroup WWDT Window Watchdog Timer(WWDT) + Memory Mapped Structure for WWDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]). + * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Bit + * | | |0 = Indicates WWDT counter is stopped. + * | | |1 = Enable WWDT counter starts counting. + * |[1] |INTEN |WWDT Interrupt Enable Bit + * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare + * | | |Set this register to adjust the valid reload window. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. + * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit + * | | |0 = ICE debug mode acknowledgement effects WWDT counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WWDT down counter will keep going no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT counter value matches CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset Flag + * | | |This bit indicates the system has been reset by WWDT time-out reset or not. + * | | |0 = WWDT time-out reset did not occur. + * | | |1 = WWDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ + +} WWDT_T; + + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller + @{ +*/ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +#endif /* __WWDT_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_acmp.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_acmp.h new file mode 100644 index 0000000..26bd213 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_acmp.h @@ -0,0 +1,421 @@ +/**************************************************************************//** + * @file ACMP.h + * @version V1.00 + * @brief M480 Series ACMP Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __ACMP_H__ +#define __ACMP_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRV0SSEL_VDDA (0UL << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV0 source voltage \hideinitializer */ +#define ACMP_VREF_CRV0SSEL_INTVREF (1UL << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV0 source voltage \hideinitializer */ +#define ACMP_VREF_CRV1SSEL_VDDA (0UL << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV1 source voltage \hideinitializer */ +#define ACMP_VREF_CRV1SSEL_INTVREF (1UL << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV1 source voltage \hideinitializer */ +#define ACMP_VREF_CRV2SSEL_VDDA (0UL << ACMP_VREF_CRV2SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV2 source voltage \hideinitializer */ +#define ACMP_VREF_CRV2SSEL_INTVREF (1UL << ACMP_VREF_CRV2SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV2 source voltage \hideinitializer */ +#define ACMP_VREF_CRV3SSEL_VDDA (0UL << ACMP_VREF_CRV3SSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV3 source voltage \hideinitializer */ +#define ACMP_VREF_CRV3SSEL_INTVREF (1UL << ACMP_VREF_CRV3SSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV3 source voltage \hideinitializer */ + + +/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + * \hideinitializer + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + * \hideinitializer + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + * \hideinitializer + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function and set hysteresis to 30mV + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * \hideinitializer + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function. + * \hideinitializer + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * \hideinitializer + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + * \hideinitializer + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + * \hideinitializer + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + * \hideinitializer + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + * \hideinitializer + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + * \hideinitializer + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + * \hideinitializer + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + * \hideinitializer + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + * \hideinitializer + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + * \hideinitializer + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + * \hideinitializer + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRV0SEL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRV0SSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + * \hideinitializer + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __ACMP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_bmc.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_bmc.h new file mode 100644 index 0000000..a64c2f2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_bmc.h @@ -0,0 +1,228 @@ +/**************************************************************************//** + * @file bmc.h + * @version V1.00 + * @brief M460 series BMC driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BMC_H__ +#define __BMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BMC_Driver BMC Driver + @{ +*/ + +/** @addtogroup BMC_EXPORTED_CONSTANTS BMC Exported Constants + @{ +*/ +#define BMC_BITWIDTH_1 (0UL) /*!< The bit time period of logic 0 is same as logic 1 \hideinitializer */ +#define BMC_BITWIDTH_15 (BMC_CTL_BWADJ_Msk) /*!< The bit time period of logic 0 is 1.5 times logic 1 \hideinitializer */ + +#define BMC_PREAMBLE_64 (0UL) /*!< BMC preamble is 64 bits \hideinitializer */ +#define BMC_PREAMBLE_32 (BMC_CTL_PREAM32_Msk) /*!< BMC preamble is 32 bits \hideinitializer */ + +#define BMC_DUM_LVL_LOW (0UL) /*!< BMC dummy level is low \hideinitializer */ +#define BMC_DUM_LVL_HIGH (BMC_CTL_DUMLVL_Msk) /*!< BMC dummy level is high \hideinitializer */ + +#define BMC_GROUP_0 (0UL) /*!< BMC group 0 mask \hideinitializer */ +#define BMC_GROUP_1 (4UL) /*!< BMC group 1 mask \hideinitializer */ +#define BMC_GROUP_2 (8UL) /*!< BMC group 2 mask \hideinitializer */ +#define BMC_GROUP_3 (12UL) /*!< BMC group 3 mask \hideinitializer */ +#define BMC_GROUP_4 (16UL) /*!< BMC group 4 mask \hideinitializer */ +#define BMC_GROUP_5 (20UL) /*!< BMC group 5 mask \hideinitializer */ +#define BMC_GROUP_6 (24UL) /*!< BMC group 6 mask \hideinitializer */ +#define BMC_GROUP_7 (28UL) /*!< BMC group 7 mask \hideinitializer */ + +#define BMC_CHANNEL_NUM (32UL) /*!< BMC total channel number \hideinitializer */ + +#define BMC_FTXD_INT_MASK (0x1UL) /*!< Frame transmit done interrupt mask \hideinitializer */ +#define BMC_TXUND_INT_MASK (0x2UL) /*!< Transmit data under run interrupt mask \hideinitializer */ + +#define BMC_G0TXUND_MASK (0x01UL) /*!< BMC group 0 transmit data under run mask \hideinitializer */ +#define BMC_G1TXUND_MASK (0x02UL) /*!< BMC group 1 transmit data under run mask \hideinitializer */ +#define BMC_G2TXUND_MASK (0x04UL) /*!< BMC group 2 transmit data under run mask \hideinitializer */ +#define BMC_G3TXUND_MASK (0x08UL) /*!< BMC group 3 transmit data under run mask \hideinitializer */ +#define BMC_G4TXUND_MASK (0x10UL) /*!< BMC group 4 transmit data under run mask \hideinitializer */ +#define BMC_G5TXUND_MASK (0x20UL) /*!< BMC group 5 transmit data under run mask \hideinitializer */ +#define BMC_G6TXUND_MASK (0x40UL) /*!< BMC group 6 transmit data under run mask \hideinitializer */ +#define BMC_G7TXUND_MASK (0x80UL) /*!< BMC group 7 transmit data under run mask \hideinitializer */ + + +/*@}*/ /* end of group BMC_EXPORTED_CONSTANTS */ + + +/** @addtogroup BMC_EXPORTED_FUNCTIONS BMC Exported Functions + @{ +*/ + +/** + * @brief Enable BMC controller + * @return None + * @details This macro is used to enable Biphase Mask Coding function. + * \hideinitializer + */ +#define BMC_ENABLE() (BMC->CTL |= BMC_CTL_BMCEN_Msk) + +/** + * @brief Disable BMC controller + * @return None + * @details This macro is used to disable Biphase Mask Coding function. + * \hideinitializer + */ +#define BMC_DISABLE() (BMC->CTL &= ~BMC_CTL_BMCEN_Msk) + +/** + * @brief Set the bit width adjustment + * @param[in] u32BitAdj BMC bit time period adjustment selection, valid values are: + * - \ref BMC_BITWIDTH_1 + * - \ref BMC_BITWIDTH_15 + * @return None + * @details This macro is used to set bit width adjustment. + * \hideinitializer + */ +#define BMC_BITWIDTH_ADJUST(u32BitAdj) (BMC->CTL = (BMC->CTL & ~BMC_CTL_BWADJ_Msk) | (u32BitAdj)) + +/** + * @brief Set the bit number of preamble + * @param[in] u32PreamBit BMC preamble bit number selection, valid values are: + * - \ref BMC_PREAMBLE_64 + * - \ref BMC_PREAMBLE_32 + * @return None + * @details This macro is used to set the bit number of preamble. + * \hideinitializer + */ +#define BMC_PREAMBLE_BIT(u32PreamBit) (BMC->CTL = (BMC->CTL & ~BMC_CTL_PREAM32_Msk) | (u32PreamBit)) + +/** + * @brief Set the dummy bit level + * @param[in] u32DumLvl BMC dummy bit level selection, valid values are: + * - \ref BMC_DUM_LVL_LOW + * - \ref BMC_DUM_LVL_HIGH + * @return None + * @details This macro is used to set dummy bit level. + * \hideinitializer + */ +#define BMC_DUMMY_LEVEL(u32DumLvl) (BMC->CTL = (BMC->CTL & ~BMC_CTL_DUMLVL_Msk) | (u32DumLvl)) + +/** + * @brief Enable PDMA function + * @return None + * @details This macro is used to enable PDMA function. + * \hideinitializer + */ +#define BMC_ENABLE_DMA() (BMC->CTL |= BMC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA function + * @return None + * @details This macro is used to disable PDMA function. + * \hideinitializer + */ +#define BMC_DISABLE_DMA() (BMC->CTL &= ~BMC_CTL_DMAEN_Msk) + +/** + * @brief Enable BMC group 0 channels + * @return None + * @details This macro is used to enable BMC channel 0~3. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP0() (BMC->CTL |= BMC_CTL_G0CHEN_Msk) + +/** + * @brief Enable BMC group 1 channels + * @return None + * @details This macro is used to enable BMC channel 4~7. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP1() (BMC->CTL |= BMC_CTL_G1CHEN_Msk) + +/** + * @brief Enable BMC group 2 channels + * @return None + * @details This macro is used to enable BMC channel 8~11. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP2() (BMC->CTL |= BMC_CTL_G2CHEN_Msk) + +/** + * @brief Enable BMC group 3 channels + * @return None + * @details This macro is used to enable BMC channel 12~15. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP3() (BMC->CTL |= BMC_CTL_G3CHEN_Msk) + +/** + * @brief Enable BMC group 4 channels + * @return None + * @details This macro is used to enable BMC channel 16~19. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP4() (BMC->CTL |= BMC_CTL_G4CHEN_Msk) + +/** + * @brief Enable BMC group 5 channels + * @return None + * @details This macro is used to enable BMC channel 20~23. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP5() (BMC->CTL |= BMC_CTL_G5CHEN_Msk) + +/** + * @brief Enable BMC group 6 channels + * @return None + * @details This macro is used to enable BMC channel 24~27. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP6() (BMC->CTL |= BMC_CTL_G6CHEN_Msk) + +/** + * @brief Enable BMC group 7 channels + * @return None + * @details This macro is used to enable BMC channel 28~31. + * \hideinitializer + */ +#define BMC_ENABLE_GROUP7() (BMC->CTL |= BMC_CTL_G7CHEN_Msk) + +/** + * @brief Get channel's FIFO empty flag + * @return Which channel's FIFO is empty + * @details This macro will return which channel's FIFO is empty. + * \hideinitializer + */ +#define BMC_GET_CH_EMPTY_FLAG() (BMC->CHEMPTY) + + +uint32_t BMC_SetBitClock(uint32_t u32BitClock); +uint32_t BMC_GetBitClock(void); +uint32_t BMC_SetDummyDelayPeriod(uint32_t u32ChGroup, uint32_t u32DumDelay); +void BMC_EnableInt(uint32_t u32Mask); +void BMC_DisableInt(uint32_t u32Mask); +uint32_t BMC_GetIntFlag(uint32_t u32Mask); +void BMC_ClearIntFlag(uint32_t u32Mask); +uint32_t BMC_GetStatus(uint32_t u32Mask); +void BMC_ClearStatus(uint32_t u32Mask); + + +/*@}*/ /* end of group BMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BMC_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_bpwm.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_bpwm.h new file mode 100644 index 0000000..bf2e725 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_bpwm.h @@ -0,0 +1,360 @@ +/**************************************************************************//** + * @file bpwm.h + * @version V1.00 + * @brief BPWM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_H__ +#define __BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) \hideinitializer */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing \hideinitializer */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low \hideinitializer */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high \hideinitializer */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_EDGE_ALIGNED + * - \ref BPWM_CENTER_ALIGNED + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BPWM_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_canfd.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_canfd.h new file mode 100644 index 0000000..941c3c9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_canfd.h @@ -0,0 +1,409 @@ +/**************************************************************************** + * @file canfd.h + * @version V1.00 + * @brief CAN FD driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef __CANFD_H__ +#define __CANFD_H__ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CANFD_Driver CAN_FD Driver + @{ +*/ + +/** @addtogroup CANFD_EXPORTED_CONSTANTS CAN_FD Exported Constants + @{ +*/ + +#define CANFD_OP_CAN_MODE 0 +#define CANFD_OP_CAN_FD_MODE 1 + +/* Reserved number of elements in Message RAM - used for calculation of start addresses within RAM Configuration + some element_numbers set to less than max, to stay altogether below 256 words of MessageRAM requirement*/ +#define CANFD_MAX_11_BIT_FTR_ELEMS 128ul /*!< maximum is 128 11-bit Filter */ +#define CANFD_MAX_29_BIT_FTR_ELEMS 64ul /*!< maximum is 64 29-bit Filter */ +#define CANFD_MAX_RX_FIFO0_ELEMS 64ul /*!< maximum is 64 Rx FIFO 0 elements */ +#define CANFD_MAX_RX_FIFO1_ELEMS 64ul /*!< maximum is 64 Rx FIFO 1 elements */ +#define CANFD_MAX_RX_BUF_ELEMS 64ul /*!< maximum is 64 Rx Buffers */ +#define CANFD_MAX_TX_BUF_ELEMS 32ul /*!< maximum is 32 Tx Buffers */ +#define CANFD_MAX_TX_EVNT_FIFO_ELEMS 32ul /*!< maximum is 32 Tx Event FIFO elements */ + +/* CAN FD sram size */ +#define CANFD_SRAM_SIZE 0x1800ul + +/* CAN FD sram address */ +#define CANFD0_SRAM_BASE_ADDR CANFD0_BASE + 0x200ul +#define CANFD1_SRAM_BASE_ADDR CANFD1_BASE + 0x200ul +#define CANFD2_SRAM_BASE_ADDR CANFD2_BASE + 0x200ul +#define CANFD3_SRAM_BASE_ADDR CANFD3_BASE + 0x200ul + +/* CAN FD Mask all interrupt */ +#define CANFD_INT_ALL_SIGNALS 0x3FFFFFFFul + +/* Maximum size of a CAN FD frame. Must be a valid CAN FD value */ +#define CANFD_MAX_MESSAGE_BYTES 64 + +/* Maximum size of a CAN FD frame. Must be a valid CAN FD value */ +#define CANFD_MAX_MESSAGE_WORDS CANFD_MAX_MESSAGE_BYTES/4 + +/* Receive message buffer helper macro */ +#define CANFD_RX_BUFFER_STD(id, mbIdx) (7UL << 27) | ((id & 0x7FF) << 16) | (mbIdx & 0x3F) + +/* Receive message buffer extended helper macro - low */ +#define CANFD_RX_BUFFER_EXT_LOW(id, mbIdx) (7UL << 29) | (id & 0x1FFFFFFFUL) + +/* Receive message buffer extended helper macro - high */ +#define CANFD_RX_BUFFER_EXT_HIGH(id, mbIdx) (mbIdx & 0x3FUL) + +/* CAN FD Rx FIFO 0 Mask helper macro. */ +#define CANFD_RX_FIFO0_STD_MASK(match, mask) (2UL << 30) | (1UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF) + +/* CAN FD Rx FIFO 0 extended Mask helper macro - low. */ +#define CANFD_RX_FIFO0_EXT_MASK_LOW(match) (1UL << 29) | ((match & 0x1FFFFFFF)) + +/* CAN FD Rx FIFO 0 extended Mask helper macro - high. */ +#define CANFD_RX_FIFO0_EXT_MASK_HIGH(mask) (2UL << 30) | ((mask & 0x1FFFFFFF)) + +/* CAN FD Rx FIFO 1 Mask helper macro. */ +#define CANFD_RX_FIFO1_STD_MASK(match, mask) (2UL << 30) | (2UL << 27) | ((match & 0x7FF) << 16) | (mask & 0x7FF) + +/* CANFD Rx FIFO 1 extended Mask helper macro - low. */ +#define CANFD_RX_FIFO1_EXT_MASK_LOW(match) (2UL << 29) | ((match & 0x1FFFFFFF)) + +/* CANFD Rx FIFO 1 extended Mask helper macro - high. */ +#define CANFD_RX_FIFO1_EXT_MASK_HIGH(mask) (2UL << 30) | ((mask & 0x1FFFFFFF)) + + +/* CAN FD frame data field size. */ +typedef enum +{ + eCANFD_BYTE8 = 0, /*!< 8 byte data field. */ + eCANFD_BYTE12 = 1, /*!< 12 byte data field. */ + eCANFD_BYTE16 = 2, /*!< 16 byte data field. */ + eCANFD_BYTE20 = 3, /*!< 20 byte data field. */ + eCANFD_BYTE24 = 4, /*!< 24 byte data field. */ + eCANFD_BYTE32 = 5, /*!< 32 byte data field. */ + eCANFD_BYTE48 = 6, /*!< 48 byte data field. */ + eCANFD_BYTE64 = 7 /*!< 64 byte data field. */ +} E_CANFD_DATA_FIELD_SIZE; + +/* CAN FD Tx FIFO/Queue Mode. */ +typedef enum +{ + eCANFD_QUEUE_MODE = 0, /*!< Tx FIFO operation. */ + eCANFD_FIFO_MODE = 1 /*!< Tx Queue operation. */ +} E_CANFD_MODE; + +/* TX Buffer Configuration Parameters */ +typedef struct +{ + E_CANFD_DATA_FIELD_SIZE eDataFieldSize; /*!< TX Buffer Data Field Size (8byte .. 64byte) */ + E_CANFD_MODE eModeSel; /*!< select: CANFD_QUEUE_MODE/CANFD_FIFO_MODE */ + uint32_t u32ElemCnt; /*!< Elements in FIFO/Queue */ + uint32_t u32DBufNumber; /*!< Number of dedicated TX buffers */ +} CANFD_TX_BUF_CONFIG_T; + + +/* Nominal Bit Timing Parameters */ +typedef struct +{ + uint32_t u32BitRate; /*!< Transceiver baud rate in bps */ + uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */ + uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */ + uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */ +} CANFD_NBT_CONFIG_T; + + +/* Data Bit Timing Parameters */ +typedef struct +{ + uint32_t u32BitRate; /*!< Transceiver baud rate in bps */ + uint16_t u16TDCOffset; /*!< Transceiver Delay Compensation Offset */ + uint16_t u16TDCFltrWin; /*!< Transceiver Delay Compensation Filter Window Length */ + uint8_t u8TDC; /*!< Transceiver Delay Compensation (1:Yes, 0:No) */ +} CANFD_DBT_CONFIG_T; + +/*! CAN FD protocol timing characteristic configuration structure. */ +typedef struct +{ + uint8_t u8PreDivider; /*!< Global Clock Division Factor. */ + uint16_t u16NominalPrescaler; /*!< Nominal clock prescaler. */ + uint8_t u8NominalRJumpwidth; /*!< Nominal Re-sync Jump Width. */ + uint8_t u8NominalPhaseSeg1; /*!< Nominal Phase Segment 1. */ + uint8_t u8NominalPhaseSeg2; /*!< Nominal Phase Segment 2. */ + uint8_t u8NominalPropSeg; /*!< Nominal Propagation Segment. */ + uint8_t u8DataPrescaler; /*!< Data clock prescaler. */ + uint8_t u8DataRJumpwidth; /*!< Data Re-sync Jump Width. */ + uint8_t u8DataPhaseSeg1; /*!< Data Phase Segment 1. */ + uint8_t u8DataPhaseSeg2; /*!< Data Phase Segment 2. */ + uint8_t u8DataPropSeg; /*!< Data Propagation Segment. */ + +} CANFD_TIMEING_CONFIG_T; + +/* CAN FD module configuration structure. */ +typedef struct +{ + CANFD_NBT_CONFIG_T sNormBitRate; /*!< Normal bit rate. */ + CANFD_DBT_CONFIG_T sDataBitRate; /*!< Data bit rate. */ + CANFD_TIMEING_CONFIG_T sConfigBitTing; /*!< Bit timing config*/ + uint8_t bFDEn; /*!< 1 == FD Operation enabled. */ + uint8_t bBitRateSwitch; /*!< 1 == Bit Rate Switch enabled (only evaluated in HW, if FD operation enabled). */ + uint8_t bEnableLoopBack; /*!< 1 == Bit Rate Switch enabled (only evaluated in HW, if FD operation enabled). */ +} CANFD_FD_BT_CONFIG_T; + +/* CAN FD Message RAM Partitioning - i.e. Start Addresses (BYTE) */ +typedef struct +{ + uint32_t u32SIDFC_FLSSA; /*! EFID1), XIDAM not applied */ +} E_CANFD_XID_FLTR_ELEM_TYPE; + +/* Filter Element Configuration - Can be used for SFEC(Standard Id filter configuration) and EFEC(Extended Id filter configuration) */ +typedef enum +{ + eCANFD_FLTR_ELEM_DIS = 0x0, /*!< Filter Element Disable */ + eCANFD_FLTR_ELEM_STO_FIFO0 = 0x1, /*!< Filter Element Store In Fifo0 */ + eCANFD_FLTR_ELEM_STO_FIFO1 = 0x2, /*!< Filter Element Store In Fifo1 */ + eCANFD_FLTR_ELEM_REJ_ID = 0x3, /*!< Filter Element RejectId */ + eCANFD_FLTR_ELEM_SET_PRI = 0x4, /*!< Filter Element Set Priority */ + eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO0 = 0x5, /*!< Filter Element Set Priority And Store In Fifo0 */ + eCANFD_FLTR_ELEM_SET_PRI_STO_FIFO1 = 0x6, /*!< Filter Element Set Priority And Store In Fifo1 */ + eCANFD_FLTR_ELEM_STO_RX_BUF_OR_DBG_MSG = 0x7 /*!< Filter Element Store In Rx Buf Or Debug Msg */ +} E_CANFD_FLTR_CONFIG; + +/* TX Event FIFO Element Struct */ +typedef struct +{ + E_CANFD_ID_TYPE eIdType; /*!< Standard ID or Extended ID */ + uint32_t u32Id; /*!< Standard ID (11bits) or Extended ID (29bits) */ + uint32_t u32DLC; /*!< Data Length Code used in the frame on the bus */ + uint32_t u32TxTs; /*!< Tx Timestamp */ + uint32_t u32MsgMarker; /*!< Message marker */ + uint8_t bErrStaInd; /*!< Error State Indicator */ + uint8_t bRemote; /*!< Remote transmission request */ + uint8_t bFDFormat; /*!< FD Format */ + uint8_t bBitRateSwitch; /*!< Bit Rate Switch */ +} CANFD_TX_EVNT_ELEM_T; + + +#define CANFD_TIMEOUT SystemCoreClock /* 1 second time-out */ +#define CANFD_TIMEOUT_ERR (-1L) /*!< CANFD operation abort due to timeout error \hideinitializer */ +extern int32_t g_CANFD_i32ErrCode; + +void CANFD_Open(CANFD_T *canfd, CANFD_FD_T *psCanfdStr); +void CANFD_Close(CANFD_T *canfd); +void CANFD_EnableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE); +void CANFD_DisableInt(CANFD_T *canfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE); +uint32_t CANFD_TransmitTxMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg); +uint32_t CANFD_TransmitDMsg(CANFD_T *canfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg); +void CANFD_SetGFC(CANFD_T *canfd, E_CANFD_ACC_NON_MATCH_FRM eNMStdFrm, E_CANFD_ACC_NON_MATCH_FRM eEMExtFrm, uint32_t u32RejRmtStdFrm, uint32_t u32RejRmtExtFrm); +void CANFD_InitRxFifo(CANFD_T *canfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize); +void CANFD_InitRxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize); +void CANFD_InitTxDBuf(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize); +void CANFD_InitTxEvntFifo(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl); +void CANFD_ConfigSIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); +void CANFD_ConfigXIDFC(CANFD_T *canfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize); +void CANFD_SetSIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32Filter); +void CANFD_SetXIDFltr(CANFD_T *canfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh); +uint32_t CANFD_ReadRxBufMsg(CANFD_T *canfd, uint8_t u8MbIdx, CANFD_FD_MSG_T *psMsgBuf); +uint32_t CANFD_ReadRxFifoMsg(CANFD_T *canfd, uint8_t u8FifoIdx, CANFD_FD_MSG_T *psMsgBuf); +void CANFD_CopyDBufToMsgBuf(CANFD_BUF_T *psRxBuffer, CANFD_FD_MSG_T *psMsgBuf); +void CANFD_CopyRxFifoToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf); +uint32_t CANFD_GetRxFifoWaterLvl(CANFD_T *canfd, uint32_t u32RxFifoNum); +void CANFD_TxBufCancelReq(CANFD_T *canfd, uint32_t u32TxBufIdx); +uint32_t CANFD_IsTxBufCancelFin(CANFD_T *canfd, uint32_t u32TxBufIdx); +uint32_t CANFD_IsTxBufTransmitOccur(CANFD_T *canfd, uint32_t u32TxBufIdx); +uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *canfd); +void CANFD_CopyTxEvntFifoToUsrBuf(CANFD_T *canfd, uint32_t u32TxEvntNum, CANFD_TX_EVNT_ELEM_T *psTxEvntElem); +void CANFD_GetBusErrCount(CANFD_T *canfd, uint8_t *pu8TxErrBuf, uint8_t *pu8RxErrBuf); +void CANFD_RunToNormal(CANFD_T *canfd, uint8_t u8Enable); +void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode); +void CANFD_ClearStatusFlag(CANFD_T *canfd, uint32_t u32InterruptFlag); +uint32_t CANFD_GetStatusFlag(CANFD_T *canfd, uint32_t u32IntTypeFlag); + +/*@}*/ /* end of group CANFD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CANFD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CANFD_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ccap.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ccap.h new file mode 100644 index 0000000..53a43a2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ccap.h @@ -0,0 +1,162 @@ +/**************************************************************************//** + * @file ccap.h + * @version V3.00 + * @brief M460 Series CCAP Driver Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CCAP_H__ +#define __CCAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CCAP_Driver CCAP Driver + @{ +*/ + +/** @addtogroup CCAP_EXPORTED_CONSTANTS CCAP Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CCAP_CTL_CCAPEN (1ul<CTL & CCAP_CTL_CCAPEN_Msk)?0:1) + +/** + * @brief Clear CCAP flag + * + * @param[in] u32IntMask interrupt flags settings. It could be + * - \ref CCAP_INT_VINTF_Msk + * - \ref CCAP_INT_MEINTF_Msk + * - \ref CCAP_INT_ADDRMINTF_Msk + * - \ref CCAP_INT_MDINTF_Msk + * + * @return None + * + * @details Clear Camera Capture Interface interrupt flag + * \hideinitializer + */ +#define CCAP_CLR_INT_FLAG(u32IntMask) (CCAP->INT |= (u32IntMask)) + +/** + * @brief Get CCAP Interrupt status + * + * @param None + * + * @return CCAP Interrupt Register + * + * @details Get Camera Capture Interface interrupt status. + * \hideinitializer + */ +#define CCAP_GET_INT_STS() (CCAP->INT) + + +void CCAP_Open(uint32_t u32InFormat, uint32_t u32OutFormat); +void CCAP_SetCroppingWindow(uint32_t u32VStart, uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width); +void CCAP_SetPacketBuf(uint32_t u32Address); +void CCAP_Close(void); +void CCAP_EnableInt(uint32_t u32IntMask); +void CCAP_DisableInt(uint32_t u32IntMask); +void CCAP_Start(void); +void CCAP_Stop(uint32_t u32FrameComplete); +void CCAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator); +void CCAP_SetPacketStride(uint32_t u32Stride); +void CCAP_EnableMono(uint32_t u32Interface); +void CCAP_DisableMono(void); +void CCAP_EnableLumaYOne(uint32_t u32th); +void CCAP_DisableLumaYOne(void); + +/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CCAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__CCAP_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_clk.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_clk.h new file mode 100644 index 0000000..51ad362 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_clk.h @@ -0,0 +1,1280 @@ +/**************************************************************************//** + * @file CLK.h + * @version V3.00 + * @brief M460 Series CLK Driver Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_1MHZ 1000000UL /*!< 1 MHz \hideinitializer */ +#define FREQ_4MHZ 4000000UL /*!< 4 MHz \hideinitializer */ +#define FREQ_8MHZ 8000000UL /*!< 8 MHz \hideinitializer */ +#define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */ +#define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */ +#define FREQ_75MHZ 75000000UL /*!< 75 MHz \hideinitializer */ +#define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */ +#define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */ +#define FREQ_150MHZ 150000000UL /*!< 50 MHz \hideinitializer */ +#define FREQ_175MHZ 175000000UL /*!< 175 MHz \hideinitializer */ +#define FREQ_180MHZ 180000000UL /*!< 180 MHz \hideinitializer */ +#define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */ +#define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */ +#define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. (Write-protection) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */ +#define CLK_CLKSEL0_STCLKSEL_HCLK (0x1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_USBSEL_HIRC48M (0x0UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from HIRC48M \hideinitializer */ +#define CLK_CLKSEL0_USBSEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from PLL/2 \hideinitializer */ + +#define CLK_CLKSEL0_EADC0SEL_PLLFN_DIV2 (0x0UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from PLLFN/2 \hideinitializer */ +#define CLK_CLKSEL0_EADC0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_EADC0SEL_HCLK (0x2UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_EADC1SEL_PLLFN_DIV2 (0x0UL << CLK_CLKSEL0_EADC1SEL_Pos) /*!< Select EADC1 clock source from PLLFN/2 \hideinitializer */ +#define CLK_CLKSEL0_EADC1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_EADC1SEL_Pos) /*!< Select EADC1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_EADC1SEL_HCLK (0x2UL << CLK_CLKSEL0_EADC1SEL_Pos) /*!< Select EADC1 clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_EADC2SEL_PLLFN_DIV2 (0x0UL << CLK_CLKSEL0_EADC2SEL_Pos) /*!< Select EADC2 clock source from PLLFN/2 \hideinitializer */ +#define CLK_CLKSEL0_EADC2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_EADC2SEL_Pos) /*!< Select EADC2 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_EADC2SEL_HCLK (0x2UL << CLK_CLKSEL0_EADC2SEL_Pos) /*!< Select EADC2 clock source from HCLK \hideinitializer */ + +#define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from HXT \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL0_CANFD0SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_CANFD0SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_CANFD0SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL0_CANFD1SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL0_CANFD1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_CANFD1SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_CANFD1SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL0_CANFD2SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL0_CANFD2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_CANFD2SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_CANFD2SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL0_CANFD3SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL0_CANFD3SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL0_CANFD3SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL0_CANFD3SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from HIRC \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL1 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */ +#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HXT \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from LXT \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HIRC \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_LIRC (0x4UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from LIRC \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from PLLFN/2 \hideinitializer */ +#define CLK_CLKSEL1_CLKOSEL_PLL_DIV2 (0x6UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from PLL/2 \hideinitializer */ + +#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */ +#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL2 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL2_EPWM0SEL_HCLK (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_EPWM1SEL_HCLK (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_HIRC48M (0x4UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from HIRC48M \hideinitializer */ +#define CLK_CLKSEL2_SPI0SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLLFN/2 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM0SEL_HCLK (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */ + +#define CLK_CLKSEL2_BPWM1SEL_HCLK (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from HCLK \hideinitializer */ +#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */ + +#define CLK_CLKSEL2_QSPI1SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_QSPI1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_QSPI1SEL_PCLK1 (0x2UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL2_QSPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_HIRC48M (0x4UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from HIRC48M \hideinitializer */ +#define CLK_CLKSEL2_SPI1SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLLFN/2 \hideinitializer */ + +#define CLK_CLKSEL2_I2S1SEL_HXT (0x0UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL2_I2S1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_I2S1SEL_PCLK1 (0x2UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL2_I2S1SEL_HIRC (0x3UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from HIRC \hideinitializer */ +#define CLK_CLKSEL2_I2S1SEL_HIRC48M (0x4UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from HIRC48M \hideinitializer */ +#define CLK_CLKSEL2_I2S1SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from PLLFN/2 \hideinitializer */ + +#define CLK_CLKSEL2_UART8SEL_HXT (0x0UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL2_UART8SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_UART8SEL_LXT (0x2UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from LXT \hideinitializer */ +#define CLK_CLKSEL2_UART8SEL_HIRC (0x3UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL2_UART9SEL_HXT (0x0UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL2_UART9SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_UART9SEL_LXT (0x2UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from LXT \hideinitializer */ +#define CLK_CLKSEL2_UART9SEL_HIRC (0x3UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL2_TRNGSEL_LXT (0x0UL << CLK_CLKSEL2_TRNGSEL_Pos) /*!< Select TRNG clock source from LXT \hideinitializer */ +#define CLK_CLKSEL2_TRNGSEL_LIRC (0x1UL << CLK_CLKSEL2_TRNGSEL_Pos) /*!< Select TRNG clock source from LIRC \hideinitializer */ + +#define CLK_CLKSEL2_PSIOSEL_HXT (0x0UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from LXT \hideinitializer */ +#define CLK_CLKSEL2_PSIOSEL_LXT (0x1UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from LIRC \hideinitializer */ +#define CLK_CLKSEL2_PSIOSEL_PCLK1 (0x2UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL2_PSIOSEL_PLL_DIV2 (0x3UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL2_PSIOSEL_LIRC (0x4UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from LIRC \hideinitializer */ +#define CLK_CLKSEL2_PSIOSEL_HIRC (0x5UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from HIRC \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL3 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_KPISEL_HXT (0x0UL << CLK_CLKSEL3_KPISEL_Pos) /*!< Select KPI clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_KPISEL_LIRC (0x1UL << CLK_CLKSEL3_KPISEL_Pos) /*!< Select KPI clock source from low speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_KPISEL_HIRC (0x2UL << CLK_CLKSEL3_KPISEL_Pos) /*!< Select KPI clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_SPI2SEL_HXT (0x0UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SPI2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL3_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SPI2SEL_HIRC48M (0x4UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from HIRC48M \hideinitializer */ +#define CLK_CLKSEL3_SPI2SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLLFN/2 \hideinitializer */ + +#define CLK_CLKSEL3_SPI3SEL_HXT (0x0UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_SPI3SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL3_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_SPI3SEL_HIRC48M (0x4UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from HIRC48M \hideinitializer */ +#define CLK_CLKSEL3_SPI3SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLLFN/2 \hideinitializer */ + +#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_HIRC48M (0x4UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from HIRC48M \hideinitializer */ +#define CLK_CLKSEL3_I2S0SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLLFN/2 \hideinitializer */ + +#define CLK_CLKSEL3_UART6SEL_HXT (0x0UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL3_UART6SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_UART6SEL_LXT (0x2UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from LXT \hideinitializer */ +#define CLK_CLKSEL3_UART6SEL_HIRC (0x3UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL3_UART7SEL_HXT (0x0UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from HXT \hideinitializer */ +#define CLK_CLKSEL3_UART7SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_UART7SEL_LXT (0x2UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from LXT \hideinitializer */ +#define CLK_CLKSEL3_UART7SEL_HIRC (0x3UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from HIRC \hideinitializer */ + +#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */ +#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL4 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL4_SPI4SEL_HXT (0x0UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL4_SPI4SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL4_SPI4SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL4_SPI4SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL4_SPI5SEL_HXT (0x0UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL4_SPI5SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL4_SPI5SEL_PCLK0 (0x2UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL4_SPI5SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL4_SPI6SEL_HXT (0x0UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL4_SPI6SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL4_SPI6SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL4_SPI6SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL4_SPI7SEL_HXT (0x0UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL4_SPI7SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL4_SPI7SEL_PCLK0 (0x2UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL4_SPI7SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL4_SPI8SEL_HXT (0x0UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL4_SPI8SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL4_SPI8SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL4_SPI8SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL4_SPI9SEL_HXT (0x0UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL4_SPI9SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL4_SPI9SEL_PCLK0 (0x2UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from PCLK0 \hideinitializer */ +#define CLK_CLKSEL4_SPI9SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from high speed oscillator \hideinitializer */ + +#define CLK_CLKSEL4_SPI10SEL_HXT (0x0UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from high speed crystal \hideinitializer */ +#define CLK_CLKSEL4_SPI10SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from PLL/2 \hideinitializer */ +#define CLK_CLKSEL4_SPI10SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from PCLK1 \hideinitializer */ +#define CLK_CLKSEL4_SPI10SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from high speed oscillator \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC clock source constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_LXTCTL_RTCCKSEL_LXT (0x0UL<>29) & 0x07UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1 \hideinitializer */ +#define MODULE_CLKSEL(x) (((x) >>26) & 0x07UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4 \hideinitializer */ +#define MODULE_CLKSEL_Msk(x) (((x) >>22) & 0x0fUL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos(x) (((x) >>17) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV(x) (((x) >>14) & 0x07UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4, 0x5:CLKDIV5 \hideinitializer */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0x0fUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */ +#define NA MODULE_NoMsk /*!< Not Available \hideinitializer */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x07UL) << 29) /*!< MODULE index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2 0x4:AHBCLK1 \hideinitializer */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x07UL) << 26) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4, 0x5:CLKSEL5 \hideinitializer */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0fUL) << 22) /*!< CLKSEL mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 17) /*!< CLKSEL position offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x07UL) << 14) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4, 0x4:CLKDIV5 \hideinitializer */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0x0fUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */ + +/* AHBCLK0 */ +#define PDMA0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_PDMA0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA0 Module */ + +#define ISP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_ISPCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */ + +#define EBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_EBICKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */ + +#define ST_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_STCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ST Module */ + +#define EMAC0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_EMAC0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EMAC0 Module */ + +#define SDH0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SDH0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< SDH0 Module */ + +#define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CRCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */ + +#define CCAP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CCAPCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CCAP Module */ + +#define SEN_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SENCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SEN Module */ + +#define HSUSBD_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_HSUSBDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< HSUSBD Module */ + +#define HBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_HBICKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< HBI Module */ + +#define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CRPTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */ + +#define KS_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_KSCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< KS Module */ + +#define SPIM_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SPIMCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPIM Module */ + +#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_FMCIDLE_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */ + +#define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_USBHCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */ + +#define SDH1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SDH1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< SDH1 Module */ + +#define PDMA1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_PDMA1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA1 Module */ + +#define TRACE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_TRACECKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRACE Module */ + +#define GPA_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPACKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPA Module */ + +#define GPB_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPBCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPB Module */ + +#define GPC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPC Module */ + +#define GPD_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPD Module */ + +#define GPE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPECKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPE Module */ + +#define GPF_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPFCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPF Module */ + +#define GPG_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPG Module */ + +#define GPH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPHCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPH Module */ + +/* AHBCLK1 */ +#define CANFD0_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< CANFD0 Module */ + +#define CANFD1_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\ + MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< CANFD1 Module */ + +#define CANFD2_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< CANFD2 Module */ + +#define CANFD3_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ + MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< CANFD3 Module */ + +#define GPI_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_GPICKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPI Module */ + +#define GPJ_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_GPJCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPJ Module */ + +#define BMC_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_BMCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BMC Module */ + +/* APBCLK0 */ +#define WDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WDT Module */ + +#define WWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WWDT Module */ + +#define RTC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */ + +#define TMR0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR0 Module */ + +#define TMR1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR1 Module */ + +#define TMR2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR2 Module */ + +#define TMR3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR3 Module */ + +#define CLKO_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< CLKO Module */ + +#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */ + +#define I2C0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */ + +#define I2C1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */ + +#define I2C2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */ + +#define I2C3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C3 Module */ + +#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< QSPI0 Module */ + +#define SPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI0 Module */ + +#define SPI1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI1 Module */ + +#define SPI2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 9UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI2 Module */ + +#define UART0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART0 Module */ + +#define UART1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART1 Module */ + +#define UART2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< UART2 Module */ + +#define UART3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\ + MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< UART3 Module */ + +#define UART4_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART4 Module */ + +#define UART5_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ + MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */ + +#define UART6_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART6CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< UART6 Module */ + +#define UART7_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART7CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\ + MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(20UL)) /*!< UART7 Module */ + +#define OTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< OTG Module */ + +#define USBD_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBD Module */ + +#define EADC0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADC0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EADC0 Module */ + +#define I2S0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< I2S0 Module */ + +#define HSOTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_HSOTGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< HSOTG Module */ + +/* APBCLK1 */ +#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< SC0 Module */ + +#define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SC1 Module */ + +#define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< SC2 Module */ + +#define I2C4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_I2C4CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C4 Module */ + +#define QSPI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QSPI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QSPI1 Module */ + +#define SPI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */ + +#define SPI4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI4CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI4 Module */ + +#define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */ + +#define PSIO_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_PSIOCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< PSIO Module */ + +#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */ + +#define ECAP2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP2 Module */ + +#define ECAP3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP3 Module */ + +#define EPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM0 Module */ + +#define EPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 1UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM1 Module */ + +#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */ + +#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 9UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */ + +#define EQEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI0 Module */ + +#define EQEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI1 Module */ + +#define EQEI2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI2 Module */ + +#define EQEI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI3 Module */ + +#define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC(27UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */ + +#define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */ + +#define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */ + +#define I2S1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_I2S1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< I2S1 Module */ + +#define EADC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EADC1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EADC1 Module */ + +/* APBCLK2 */ +#define KPI_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_KPICKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\ + MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< KPI Module */ + +#define EADC2_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_EADC2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(14UL)|\ + MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< EADC2 Module */ + +#define ACMP23_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_ACMP23CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP23 Module */ + +#define SPI5_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI5CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI5 Module */ + +#define SPI6_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI6CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI6 Module */ + +#define SPI7_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI7CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI7 Module */ + +#define SPI8_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI8CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI8 Module */ + +#define SPI9_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI9CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI9 Module */ + +#define SPI10_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI10CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI10 Module */ + +#define UART8_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_UART8CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< UART8 Module */ + +#define UART9_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_UART9CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\ + MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(20UL)) /*!< UART9 Module */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode \hideinitializer */ +#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WKTMRIS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_131072 (0x8UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 131072 OSC10K clocks (13107.2 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_262144 (0x9UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 262144 OSC10K clocks (26214.4 ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_524288 (0xaUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 524288 OSC10K clocks (52428.8ms) \hideinitializer */ +#define CLK_PMUCTL_WKTMRIS_1048576 (0xbUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1048576 OSC10K clocks (104857.6ms) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SWKDBCLKSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */ +#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */ +#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */ +#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */ + +#define CLK_SPDSRETSEL_NO (0x0UL << CLK_PMUCTL_SRETSEL_Pos) /*!< No SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_16K (0x1UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 16K SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_32K (0x2UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 32K SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_64K (0x3UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 64K SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_128K (0x4UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 128K SRAM retention when chip enter SPD mode \hideinitializer */ +#define CLK_SPDSRETSEL_256K (0x5UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 256K SRAM retention when chip enter SPD mode \hideinitializer */ + +#define CLK_TIMEOUT_ERR (-1) /*!< Clock timeout error value \hideinitializer */ + +/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +extern int32_t g_CLK_i32ErrCode; + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable Wake-up Timer + * @param None + * @return None + * @details This macro disables Wake-up timer at Standby or Deep Power-down mode. + */ +#define CLK_DISABLE_WKTMR() (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) + +/** + * @brief Enable Wake-up Timer + * @param None + * @return None + * @details This macro enables Wake-up timer at Standby or Deep Power-down mode. + */ +#define CLK_ENABLE_WKTMR() (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) + +/** + * @brief Disable DPD Mode Wake-up Pin 0 + * @param None + * @return None + * @details This macro disables Wake-up pin 0 (GPC.0) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN0() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN0_Msk) + +/** + * @brief Disable DPD Mode Wake-up Pin 1 + * @param None + * @return None + * @details This macro disables Wake-up pin 1 (GPB.0) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN1() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk) + +/** + * @brief Disable DPD Mode Wake-up Pin 2 + * @param None + * @return None + * @details This macro disables Wake-up pin 2 (GPB.2) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN2() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk) + +/** + * @brief Disable DPD Mode Wake-up Pin 3 + * @param None + * @return None + * @details This macro disables Wake-up pin 3 (GPB.12) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN3() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk) + +/** + * @brief Disable DPD Mode Wake-up Pin 4 + * @param None + * @return None + * @details This macro disables Wake-up pin 4 (GPF.6) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN4() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk) + +/** + * @brief Disable SPD Mode ACMP Wake-up + * @param None + * @return None + * @details This macro disables ACMP wake-up at Standby Power-down mode. + */ +#define CLK_DISABLE_SPDACMP() (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) + +/** + * @brief Enable SPD Mode ACMP Wake-up + * @param None + * @return None + * @details This macro enables ACMP wake-up at Standby Power-down mode. + */ +#define CLK_ENABLE_SPDACMP() (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) + +/** + * @brief Disable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro disables RTC Wake-up at Standby or Deep Power-down mode. + */ +#define CLK_DISABLE_RTCWK() (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) + +/** + * @brief Enable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro enables RTC Wake-up at Standby or Deep Power-down mode. + */ +#define CLK_ENABLE_RTCWK() (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_128 + * - \ref CLK_PMUCTL_WKTMRIS_256 + * - \ref CLK_PMUCTL_WKTMRIS_512 + * - \ref CLK_PMUCTL_WKTMRIS_1024 + * - \ref CLK_PMUCTL_WKTMRIS_4096 + * - \ref CLK_PMUCTL_WKTMRIS_8192 + * - \ref CLK_PMUCTL_WKTMRIS_16384 + * - \ref CLK_PMUCTL_WKTMRIS_65536 + * - \ref CLK_PMUCTL_WKTMRIS_131072 + * - \ref CLK_PMUCTL_WKTMRIS_262144 + * - \ref CLK_PMUCTL_WKTMRIS_524288 + * - \ref CLK_PMUCTL_WKTMRIS_1048576 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * \hideinitializer + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256 + * + * @return None + * + * @details This function set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up. + * + * \hideinitializer + */ +#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE int32_t CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE int32_t CLK_SysTickLongDelay(uint32_t us); + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 200MHz => 83886us, 180MHz => 93206us ... + * @retval 0 Delay success. Target delay time reached. + * @retval CLK_TIMEOUT_ERR Delay function execute failed due to SysTick stop working. + * @details Use the SysTick to generate the delay time and the unit is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE int32_t CLK_SysTickDelay(uint32_t us) +{ + /* The u32TimeOutCnt value must be greater than the max delay time of 1398ms if HCLK=12MHz */ + uint32_t u32TimeOutCnt = SystemCoreClock<<1; + + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = (0x00); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) + { + if(--u32TimeOutCnt == 0) + { + break; + } + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0; + + if(u32TimeOutCnt == 0) + return CLK_TIMEOUT_ERR; + else + return 0; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @retval 0 Delay success. Target delay time reached. + * @retval CLK_TIMEOUT_ERR Delay function execute failed due to SysTick stop working. + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE int32_t CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t u32Delay; + uint32_t u32TimeOutCnt = 0; + + /* It should <= 65536us for each delay loop */ + u32Delay = 65536UL; + + do + { + if(us > u32Delay) + { + us -= u32Delay; + } + else + { + u32Delay = us; + us = 0UL; + } + + SysTick->LOAD = u32Delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + u32TimeOutCnt = SystemCoreClock<<1; + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + if(--u32TimeOutCnt == 0) + { + return CLK_TIMEOUT_ERR; + } + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + } + while(us > 0UL); + + return 0; +} + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); +void CLK_DisablePLLFN(void); +uint32_t CLK_EnablePLLFN(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +uint32_t CLK_GetPLLFNClockFreq(void); + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CLK_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_crc.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_crc.h new file mode 100644 index 0000000..5f36c4c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_crc.h @@ -0,0 +1,112 @@ +/**************************************************************************//** + * @file crc.h + * @version V3.00 + * @brief Cyclic Redundancy Check(CRC) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0) + +/** + * @brief Get CRC Seed Value + * + * @param None + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + * \hideinitializer + */ +#define CRC_GET_SEED() (CRC->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + * \hideinitializer + */ +#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data)) + + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_crypto.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_crypto.h new file mode 100644 index 0000000..0a945df --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_crypto.h @@ -0,0 +1,563 @@ +/**************************************************************************//** + * @file crypto.h + * @version V3.00 + * @brief Cryptographic Accelerator driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + + +#define PRNG_KEY_SIZE_128 ( 0UL) /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_163 ( 1UL) /*!< Select to generate 163-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 ( 2UL) /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_224 ( 3UL) /*!< Select to generate 224-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_255 ( 4UL) /*!< Select to generate 255-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 ( 6UL) /*!< Select to generate 256-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_283 ( 7UL) /*!< Select to generate 283-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_384 ( 8UL) /*!< Select to generate 384-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_409 ( 9UL) /*!< Select to generate 409-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_512 (10UL) /*!< Select to generate 512-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_521 (11UL) /*!< Select to generate 521-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_571 (12UL) /*!< Select to generate 571-bit random key (Key Store Only) \hideinitializer */ + +#define PRNG_SEED_CONT (0UL) /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD (1UL) /*!< PRNG reload new seed \hideinitializer */ + +#define PRNG_CTL_SEEDSRC_TRNG (0UL) /*!< PRNG seed from TRNG \hideinitializer */ +#define PRNG_CTL_SEEDSRC_SEEDREG (CRPT_PRNG_CTL_SEEDSRC_Msk) /*!< PRNG seed from PRNG seed register \hideinitializer */ + + +#define AES_KEY_SIZE_128 (0UL) /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 (1UL) /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 (2UL) /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB (0UL) /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC (1UL) /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB (2UL) /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB (3UL) /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR (4UL) /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 (0x10UL) /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 (0x11UL) /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 (0x12UL) /*!< AES select CBC CS3 mode \hideinitializer */ +#define AES_MODE_GCM (0x20UL) +#define AES_MODE_GHASH (0x21UL) +#define AES_MODE_CCM (0x22UL) + +#define SM4_MODE_ECB (0x200UL) /*!< SM4 select ECB mode \hideinitializer */ +#define SM4_MODE_CBC (0x201UL) /*!< SM4 select CBC mode \hideinitializer */ +#define SM4_MODE_CFB (0x202UL) /*!< SM4 select CFB mode \hideinitializer */ +#define SM4_MODE_OFB (0x203UL) /*!< SM4 select OFB mode \hideinitializer */ +#define SM4_MODE_CTR (0x204UL) /*!< SM4 select CTR mode \hideinitializer */ +#define SM4_MODE_CBC_CS1 (0x210UL) /*!< SM4 select CBC CS1 mode \hideinitializer */ +#define SM4_MODE_CBC_CS2 (0x211UL) /*!< SM4 select CBC CS2 mode \hideinitializer */ +#define SM4_MODE_CBC_CS3 (0x212UL) /*!< SM4 select CBC CS3 mode \hideinitializer */ +#define SM4_MODE_GCM (0x220UL) +#define SM4_MODE_GHASH (0x221UL) +#define SM4_MODE_CCM (0x222UL) + + +#define AES_NO_SWAP (0UL) /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP (1UL) /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP (2UL) /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP (3UL) /*!< AES swap both input and output data \hideinitializer */ + +#define DES_MODE_ECB (0x000UL) /*!< DES select ECB mode \hideinitializer */ +#define DES_MODE_CBC (0x100UL) /*!< DES select CBC mode \hideinitializer */ +#define DES_MODE_CFB (0x200UL) /*!< DES select CFB mode \hideinitializer */ +#define DES_MODE_OFB (0x300UL) /*!< DES select OFB mode \hideinitializer */ +#define DES_MODE_CTR (0x400UL) /*!< DES select CTR mode \hideinitializer */ +#define TDES_MODE_ECB (0x004UL) /*!< TDES select ECB mode \hideinitializer */ +#define TDES_MODE_CBC (0x104UL) /*!< TDES select CBC mode \hideinitializer */ +#define TDES_MODE_CFB (0x204UL) /*!< TDES select CFB mode \hideinitializer */ +#define TDES_MODE_OFB (0x304UL) /*!< TDES select OFB mode \hideinitializer */ +#define TDES_MODE_CTR (0x404UL) /*!< TDES select CTR mode \hideinitializer */ + +#define TDES_NO_SWAP (0UL) /*!< TDES do not swap data \hideinitializer */ +#define TDES_WHL_SWAP (1UL) /*!< TDES swap high-low word \hideinitializer */ +#define TDES_OUT_SWAP (2UL) /*!< TDES swap output data \hideinitializer */ +#define TDES_OUT_WHL_SWAP (3UL) /*!< TDES swap output data and high-low word \hideinitializer */ +#define TDES_IN_SWAP (4UL) /*!< TDES swap input data \hideinitializer */ +#define TDES_IN_WHL_SWAP (5UL) /*!< TDES swap input data and high-low word \hideinitializer */ +#define TDES_IN_OUT_SWAP (6UL) /*!< TDES swap both input and output data \hideinitializer */ +#define TDES_IN_OUT_WHL_SWAP (7UL) /*!< TDES swap input, output and high-low word \hideinitializer */ + +#define SHA_MODE_SHA1 (0UL) /*!< SHA select SHA-1 160-bit \hideinitializer */ +#define SHA_MODE_SHA224 (5UL) /*!< SHA select SHA-224 224-bit \hideinitializer */ +#define SHA_MODE_SHA256 (4UL) /*!< SHA select SHA-256 256-bit \hideinitializer */ +#define SHA_MODE_SHA384 (7UL) /*!< SHA select SHA-384 384-bit \hideinitializer */ +#define SHA_MODE_SHA512 (6UL) /*!< SHA select SHA-512 512-bit \hideinitializer */ + +#define HMAC_MODE_SHA1 (8UL) /*!< HMAC select SHA-1 160-bit \hideinitializer */ +#define HMAC_MODE_SHA224 (13UL) /*!< HMAC select SHA-224 224-bit \hideinitializer */ +#define HMAC_MODE_SHA256 (12UL) /*!< HMAC select SHA-256 256-bit \hideinitializer */ +#define HMAC_MODE_SHA384 (15UL) /*!< HMAC select SHA-384 384-bit \hideinitializer */ +#define HMAC_MODE_SHA512 (14UL) /*!< HMAC select SHA-512 512-bit \hideinitializer */ + + +#define SHA_NO_SWAP (0UL) /*!< SHA do not swap input and output data \hideinitializer */ +#define SHA_OUT_SWAP (1UL) /*!< SHA swap output data \hideinitializer */ +#define SHA_IN_SWAP (2UL) /*!< SHA swap input data \hideinitializer */ +#define SHA_IN_OUT_SWAP (3UL) /*!< SHA swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST (0x4UL) /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT (0x5UL) /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE (0x6UL) /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST (0x7UL) /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + +//--------------------------------------------------- + +#define RSA_MAX_KLEN (4096) +#define RSA_KBUF_HLEN (RSA_MAX_KLEN/4 + 8) +#define RSA_KBUF_BLEN (RSA_MAX_KLEN + 32) + +#define RSA_KEY_SIZE_1024 (0UL) /*!< RSA select 1024-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_2048 (1UL) /*!< RSA select 2048-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_3072 (2UL) /*!< RSA select 3072-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_4096 (3UL) /*!< RSA select 4096-bit key length \hideinitializer */ + +#define RSA_MODE_NORMAL (0x000UL) /*!< RSA select normal mode \hideinitializer */ +#define RSA_MODE_CRT (0x004UL) /*!< RSA select CRT mode \hideinitializer */ +#define RSA_MODE_CRTBYPASS (0x00CUL) /*!< RSA select CRT bypass mode \hideinitializer */ +#define RSA_MODE_SCAP (0x100UL) /*!< RSA select SCAP mode \hideinitializer */ +#define RSA_MODE_CRT_SCAP (0x104UL) /*!< RSA select CRT SCAP mode \hideinitializer */ +#define RSA_MODE_CRTBYPASS_SCAP (0x10CUL) /*!< RSA select CRT bypass SCAP mode \hideinitializer */ + + +typedef enum +{ + /*!< ECC curve \hideinitializer */ + CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */ + CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */ + CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */ + CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */ + CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */ + CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */ + CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */ + CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */ + CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */ + CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */ + CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */ + CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */ + CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */ + CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */ + CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_25519, /*!< ECC curve-25519 \hideinitializer */ + CURVE_SM2_256, /*!< SM2 \hideinitializer */ + CURVE_UNDEF = -0x7fffffff, /*!< Invalid curve \hideinitializer */ +} +E_ECC_CURVE; + + + +typedef struct e_curve_t +{ + E_ECC_CURVE curve_id; + int32_t Echar; + char Ea[144]; + char Eb[144]; + char Px[144]; + char Py[144]; + int32_t Epl; + char Pp[176]; + int32_t Eol; + char Eorder[176]; + int32_t key_len; + int32_t irreducible_k1; + int32_t irreducible_k2; + int32_t irreducible_k3; + int32_t GF; +} ECC_CURVE; + + +/* RSA working buffer for normal mode */ +typedef struct +{ + __attribute__((aligned(16))) uint32_t au32RsaOutput[128]; /* The RSA answer. */ + __attribute__((aligned(16))) uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + __attribute__((aligned(16))) uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + __attribute__((aligned(16))) uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ +} RSA_BUF_NORMAL_T; + +/* RSA working buffer for CRT ( + CRT bypass) mode */ +typedef struct +{ + __attribute__((aligned(16))) uint32_t au32RsaOutput[128]; /* The RSA answer. */ + __attribute__((aligned(16))) uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + __attribute__((aligned(16))) uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + __attribute__((aligned(16))) uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + __attribute__((aligned(16))) uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + __attribute__((aligned(16))) uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */ +} RSA_BUF_CRT_T; + +/* RSA working buffer for SCAP mode */ +typedef struct +{ + __attribute__((aligned(16))) uint32_t au32RsaOutput[128]; /* The RSA answer. */ + __attribute__((aligned(16))) uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + __attribute__((aligned(16))) uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + __attribute__((aligned(16))) uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + __attribute__((aligned(16))) uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + __attribute__((aligned(16))) uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpBlindKey[128+4]; /* The Temporary Value(blind key) of RSA SCAP. */ +} RSA_BUF_SCAP_T; + +/* RSA working buffer for CRT ( + CRT bypass ) + SCAP mode */ +typedef struct +{ + __attribute__((aligned(16))) uint32_t au32RsaOutput[128]; /* The RSA answer. */ + __attribute__((aligned(16))) uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + __attribute__((aligned(16))) uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + __attribute__((aligned(16))) uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + __attribute__((aligned(16))) uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + __attribute__((aligned(16))) uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */ + __attribute__((aligned(16))) uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */ +} RSA_BUF_CRT_SCAP_T; + +/* RSA working buffer for using key store */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ +} RSA_BUF_KS_T; + +/**@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified crypto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified crypto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro disables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro gets TDES interrupt flag. + * @param crpt Specified crypto module + * @return TDES interrupt flag. + * \hideinitializer + */ +#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro clears TDES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro enables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro disables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro gets SHA interrupt flag. + * @param crpt Specified crypto module + * @return SHA interrupt flag. + * \hideinitializer + */ +#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro clears SHA interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro enables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro disables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro gets ECC interrupt flag. + * @param crpt Specified crypto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro clears ECC interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro enables RSA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk)) + +/** + * @brief This macro disables RSA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk)) + +/** + * @brief This macro gets RSA interrupt flag. + * @param crpt Specified crypto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define RSA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk)) + +/** + * @brief This macro clears RSA interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk)) + + +/**@}*/ /* end of group CRYPTO_EXPORTED_MACROS */ + + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +int32_t PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len); +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode); +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt); +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]); +void ECC_DriverISR(CRPT_T *crpt); +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]); +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]); +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]); +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S); +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S); + + +int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS); +int32_t RSA_SetKey(CRPT_T *crpt, char *Key); +int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q); +void RSA_Start(CRPT_T *crpt); +int32_t RSA_Read(CRPT_T *crpt, char * Output); +int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum); +int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum, + uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum, + uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum); +int32_t ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp); +int32_t ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_d, int32_t i32KeyIdx_d, KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S); +int32_t ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1, KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S); +int32_t ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[]); + +void CRPT_Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +void CRPT_Hex2Reg(char input[], uint32_t volatile reg[]); +int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve); + +/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRYPTO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRYPTO_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_dac.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_dac.h new file mode 100644 index 0000000..17130aa --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_dac.h @@ -0,0 +1,270 @@ +/**************************************************************************//** + * @file dac.h + * @version V1.00 + * @brief DAC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + * \hideinitializer + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + * \hideinitializer + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @return None + * @details This macro is used to enable DAC interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @return None + * @details This macro is used to disable DAC interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + * \hideinitializer + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA mode. + * \hideinitializer + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * \hideinitializer + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + * \hideinitializer + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + * \hideinitializer + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + * \hideinitializer + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + * \hideinitializer + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + + +/** + * @brief Enable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_eadc.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_eadc.h new file mode 100644 index 0000000..1832b52 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_eadc.h @@ -0,0 +1,726 @@ +/**************************************************************************//** + * @file eadc.h + * @version V0.10 + * @brief EADC driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EADC_H__ +#define __EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) + +/** + * @brief Disable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details This macro is used to disable sample module PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The EADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + * \hideinitializer + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + * \hideinitializer + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + * \hideinitializer + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + * \hideinitializer + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + * \hideinitializer + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + * \hideinitializer + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= (uint32_t)(~(u32ModuleMask))) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + * \hideinitializer + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start EADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + * \hideinitializer + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * \hideinitializer + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + * \hideinitializer + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + * \hideinitializer + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + * \hideinitializer + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + * \hideinitializer + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + * \hideinitializer + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + * \hideinitializer + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + * \hideinitializer + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + * \hideinitializer + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * \hideinitializer + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * \hideinitializer + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + * \hideinitializer + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ + (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk))) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + * \hideinitializer + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + * \hideinitializer + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + * \hideinitializer + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + * \hideinitializer + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL) + +/** + * @brief Enable conversion result left alignment. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 23. + * @return None + * @details The 12-bit conversion result will be left aligned and stored in EADC_DATn[15:4] (n=0~23). + * \hideinitializer + */ +#define EADC_ENABLE_LEFT_ALIGN(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) |= EADC_MCTL1_ALIGN_Msk) + +/** + * @brief Disable conversion result left alignment. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 23. + * @return None + * @details The 12-bit conversion result will be right aligned and stored in EADC_DATn[11:0] (n=0~23). + * \hideinitializer + */ +#define EADC_DISABLE_LEFT_ALIGN(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_ALIGN_Msk)) + +/** + * @brief Enable average mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 23. + * @return None + * @details Conversion results in data register will be averaged. + * @note This average mode needs to work with accumulated mode that configured by ACU (EADC_MnCTL1[7:4], n=0~23) bit field. + * \hideinitializer + */ +#define EADC_ENABLE_AVG(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) |= EADC_MCTL1_AVG_Msk) + +/** + * @brief Disable average mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 23. + * @return None + * @details Conversion results in data register will not be averaged. + * \hideinitializer + */ +#define EADC_DISABLE_AVG(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_AVG_Msk)) + +/** + * @brief Configure the Accumulation feature and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 23. + * @param[in] u16ACUNum specifies the number of accumulation, valid values are + * - \ref EADC_MCTL1_ACU_1 : 1 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_2 : 2 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_4 : 4 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_8 : 8 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_16 : 16 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_32 : 32 conversion result will be accumulated. The result is right shift 1 bit to fit within the available 16-bit register size. + * - \ref EADC_MCTL1_ACU_64 : 64 conversion result will be accumulated. The result is right shift 2 bits to fit within the available 16-bit register size. + * - \ref EADC_MCTL1_ACU_128 : 128 conversion result will be accumulated. The result is right shift 3 bits to fit within the available 16-bit register size. + * - \ref EADC_MCTL1_ACU_256 : 256 conversion result will be accumulated. The result is right shift 4 bits to fit within the available 16-bit register size. + * @return None + * @details When accumulating more than 16 samples, the result will be too large to match the + * 16-bit RESULT register size (EADC_DATn[15:0]. To avoid overflow, the result is + * right shifted automatically to fit within the available 16-bit register size. + * The number of automatic right shifts is specified in parameter list above. + * \hideinitializer + */ +#define EADC_ENABLE_ACU(eadc,\ + u32ModuleNum,\ + u16ACUNum) ((((eadc)->MCTL1[(u32ModuleNum)])) = (((((eadc)->MCTL1[(u32ModuleNum)])) & (~EADC_MCTL1_ACU_Msk)) |\ + (u16ACUNum))) + +/** + * @brief Disable the Accumulation feature. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 23. + * @return None + * \hideinitializer + */ +#define EADC_DISABLE_ACU(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_ACU_Msk)) + +/** + * @brief Set start of conversion interrupt delay cycle. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32DelayCycle Decides the interrupt delay cycle, valid value are from 0 to 15. + * @return None + * @details Select EADC start of conversion interrupt ADINT0 to ADINT3 delay cycle(s). + * @note This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. + * \hideinitializer + */ +#define EADC_SET_INT_DELAY(eadc, u32IntSel, u32DelayCycle) ((eadc)->CTL = ((eadc)->CTL & ~(0xFUL << (EADC_CTL_INTDELAY0_Pos + ((u32IntSel) << 2)))) | \ + ((u32DelayCycle) << (EADC_CTL_INTDELAY0_Pos + ((u32IntSel) << 2)))) + +/** + * @brief Enable comparetor to trigger EPWM brake. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CmpSel Decides which comparator will be used, valid value are from 0 to 3. + * @return None + * @details Enable EADC comparator 0 to 3 can trigger EPWM brake. + * \hideinitializer + */ +#define EADC_ENABLE_CMP_TRIGGER_BRAKE(eadc, u32CmpSel) ((eadc)->CTL1 |= (1UL << (EADC_CTL1_CMP0TRG_Pos + (u32CmpSel)))) + +/** + * @brief Disable comparetor to trigger EPWM brake. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CmpSel Decides which comparator will be disabled, valid value are from 0 to 3. + * @return None + * @details Disable EADC comparator 0 to 3 trigger EPWM brake. + * \hideinitializer + */ +#define EADC_DISABLE_CMP_TRIGGER_BRAKE(eadc, u32CmpSel) ((eadc)->CTL1 &= (~(1UL << (EADC_CTL1_CMP0TRG_Pos + (u32CmpSel))))) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EADC_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ebi.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ebi.h new file mode 100644 index 0000000..43947d0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ebi.h @@ -0,0 +1,350 @@ +/**************************************************************************//** + * @file ebi.h + * @version V3.00 + * @brief External Bus Interface(EBI) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_H__ +#define __EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/**@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk); + +/** + * @brief Disable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk); + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/**@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EBI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EBI_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ecap.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ecap.h new file mode 100644 index 0000000..e6741a3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_ecap.h @@ -0,0 +1,458 @@ +/**************************************************************************//** + * @file ecap.h + * @version V3.00 + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL0_CMPCLREN_Msk + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00) | ((u32Event) & 0xF00); \ + }while(0); + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T* ecap); +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask); +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ECAP_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_epwm.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_epwm.h new file mode 100644 index 0000000..e0c7063 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_epwm.h @@ -0,0 +1,657 @@ +/**************************************************************************//** + * @file epwm.h + * @version V1.00 + * @brief EPWM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_H__ +#define __EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ +#define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ +#define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ +#define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ +#define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ +#define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ +#define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ +#define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0U<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + { \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum)] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum)]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + int i; \ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1 << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + ((epwm)->DTCTL = (((epwm)->DTCTL & ~(1UL << (EPWM_DTCTL_DTCKSEL0_Pos + ((u32ChannelNum) >> 1U)))) | \ + ((u32AfterPrescaler) << (EPWM_DTCTL_DTCKSEL0_Pos + ((u32ChannelNum) >> 1U))))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, + uint32_t u32ChannelNum, + uint32_t u32Frequency, + uint32_t u32HighDutyCycle, + uint32_t u32Frequency2); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EPWM_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_eqei.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_eqei.h new file mode 100644 index 0000000..abcca85 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_eqei.h @@ -0,0 +1,434 @@ +/**************************************************************************//** + * @file eqei.h + * @version V3.00 + * @brief Enhanced Quadrature Encoder Interface (EQEI) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EQEI_H__ +#define __EQEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EQEI_Driver EQEI Driver + @{ +*/ + +/** @addtogroup EQEI_EXPORTED_CONSTANTS EQEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EQEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EQEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~EQEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable EQEI compare function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This macro enable EQEI counter compare function. + * \hideinitializer + */ +#define EQEI_ENABLE_CNT_CMP(eqei) ((eqei)->CTL |= EQEI_CTL_CMPEN_Msk) + +/** + * @brief Disable EQEI index latch function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This macro disable EQEI index trigger counter latch function. + * \hideinitializer + */ +#define EQEI_DISABLE_INDEX_LATCH(eqei) ((eqei)->CTL &= (~EQEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable EQEI index latch function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This macro enable EQEI index trigger counter latch function. + * \hideinitializer + */ +#define EQEI_ENABLE_INDEX_LATCH(eqei) ((eqei)->CTL |= EQEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable EQEI index reload function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This macro disable EQEI index trigger counter reload function. + * \hideinitializer + */ +#define EQEI_DISABLE_INDEX_RELOAD(eqei) ((eqei)->CTL &= (~EQEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable EQEI index reload function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This macro enable EQEI index trigger counter reload function. + * \hideinitializer + */ +#define EQEI_ENABLE_INDEX_RELOAD(eqei) ((eqei)->CTL |= EQEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable EQEI input + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32InputType Input signal type. + * - \ref EQEI_CTL_CHAEN_Msk : QEA input + * - \ref EQEI_CTL_CHAEN_Msk : QEB input + * - \ref EQEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified EQEI signal input. + * \hideinitializer + */ +#define EQEI_DISABLE_INPUT(eqei, u32InputType) ((eqei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable EQEI input + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32InputType Input signal type . + * - \ref EQEI_CTL_CHAEN_Msk : QEA input + * - \ref EQEI_CTL_CHBEN_Msk : QEB input + * - \ref EQEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified EQEI signal input. + * \hideinitializer + */ +#define EQEI_ENABLE_INPUT(eqei, u32InputType) ((eqei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32InputType Input signal type . + * - \ref EQEI_CTL_CHAINV_Msk : QEA Input + * - \ref EQEI_CTL_CHBINV_Msk : QEB Input + * - \ref EQEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified EQEI signal inverted input polarity. + * \hideinitializer + */ +#define EQEI_DISABLE_INPUT_INV(eqei, u32InputType) ((eqei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32InputType Input signal type. + * - \ref EQEI_CTL_CHAINV_Msk : QEA Input + * - \ref EQEI_CTL_CHBINV_Msk : QEB Input + * - \ref EQEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified EQEI signal input polarity. + * \hideinitializer + */ +#define EQEI_ENABLE_INPUT_INV(eqei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable EQEI interrupt + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref EQEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref EQEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref EQEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref EQEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified EQEI interrupt. + * \hideinitializer + */ +#define EQEI_DISABLE_INT(eqei, u32IntSel) ((eqei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable EQEI interrupt + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref EQEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref EQEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref EQEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref EQEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified EQEI interrupt. + * \hideinitializer + */ +#define EQEI_ENABLE_INT(eqei, u32IntSel) ((eqei)->CTL |= (u32IntSel)) + +/** + * @brief Disable EQEI noise filter + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This macro disable EQEI noise filter function. + * \hideinitializer + */ +#define EQEI_DISABLE_NOISE_FILTER(eqei) ((eqei)->CTL |= EQEI_CTL_NFDIS_Msk) + +/** + * @brief Enable EQEI noise filter + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref EQEI_CTL_NFCLKSEL_DIV1 + * - \ref EQEI_CTL_NFCLKSEL_DIV2 + * - \ref EQEI_CTL_NFCLKSEL_DIV4 + * - \ref EQEI_CTL_NFCLKSEL_DIV16 + * - \ref EQEI_CTL_NFCLKSEL_DIV32 + * - \ref EQEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable EQEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define EQEI_ENABLE_NOISE_FILTER(eqei, u32ClkSel) ((eqei)->CTL = ((eqei)->CTL & (~(EQEI_CTL_NFDIS_Msk|EQEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get EQEI counter value + * @param[in] eqei The pointer of the specified EQEI module. + * @return EQEI pulse counter register value. + * @details This macro get EQEI pulse counter value. + * \hideinitializer + */ +#define EQEI_GET_CNT_VALUE(eqei) ((eqei)->CNT) + +/** + * @brief Get EQEI counting direction + * @param[in] eqei The pointer of the specified EQEI module. + * @retval 0 EQEI counter is in down-counting. + * @retval 1 EQEI counter is in up-counting. + * @details This macro get EQEI counting direction. + * \hideinitializer + */ +#define EQEI_GET_DIR(eqei) (((eqei)->STATUS & (EQEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get EQEI counter hold value + * @param[in] eqei The pointer of the specified EQEI module. + * @return EQEI pulse counter hold register value. + * @details This macro get EQEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define EQEI_GET_HOLD_VALUE(eqei) ((eqei)->CNTHOLD) + +/** + * @brief Get EQEI counter index latch value + * @param[in] eqei The pointer of the specified EQEI module. + * @return EQEI pulse counter index latch value + * @details This macro get EQEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define EQEI_GET_INDEX_LATCH_VALUE(eqei) ((eqei)->CNTLATCH) + +/** + * @brief Set EQEI counter index latch value + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Val The latch value. + * @return EQEI pulse counter index latch value + * @details This macro set EQEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define EQEI_SET_INDEX_LATCH_VALUE(eqei,u32Val) ((eqei)->CNTLATCH = (u32Val)) + +/** + * @brief Get EQEI interrupt flag status + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref EQEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref EQEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref EQEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref EQEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref EQEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 EQEI specified interrupt flag is not set. + * @retval 1 EQEI specified interrupt flag is set. + * @details This macro get EQEI specified interrupt flag status. + * \hideinitializer + */ +#define EQEI_GET_INT_FLAG(eqei, u32IntSel) (((eqei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear EQEI interrupt flag + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref EQEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref EQEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref EQEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref EQEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear EQEI specified interrupt flag. + * \hideinitializer + */ +#define EQEI_CLR_INT_FLAG(eqei, u32IntSel) ((eqei)->STATUS = (u32IntSel)) + +/** + * @brief Set EQEI counter compare value + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set EQEI pulse counter compare value. + * \hideinitializer + */ +#define EQEI_SET_CNT_CMP(eqei, u32Value) ((eqei)->CNTCMP = (u32Value)) + +/** + * @brief Set EQEI counter value + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set EQEI pulse counter value. + * \hideinitializer + */ +#define EQEI_SET_CNT_VALUE(eqei, u32Value) ((eqei)->CNT = (u32Value)) + +/** + * @brief Enable EQEI counter hold mode + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Type The triggered type. + * - \ref EQEI_CTL_HOLDCNT_Msk : Hold EQEI_CNT control + * - \ref EQEI_CTL_HOLDTMR0_Msk : Hold EQEI_CNT by Timer0 + * - \ref EQEI_CTL_HOLDTMR1_Msk : Hold EQEI_CNT by Timer1 + * - \ref EQEI_CTL_HOLDTMR2_Msk : Hold EQEI_CNT by Timer2 + * - \ref EQEI_CTL_HOLDTMR3_Msk : Hold EQEI_CNT by Timer3 + * @return None + * @details This macro enable EQEI counter hold mode. + * \hideinitializer + */ +#define EQEI_ENABLE_HOLD_TRG_SRC(eqei, u32Type) ((eqei)->CTL |= (u32Type)) + +/** + * @brief Disable EQEI counter hold mode + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Type The triggered type. + * - \ref EQEI_CTL_HOLDCNT_Msk : Hold EQEI_CNT control + * - \ref EQEI_CTL_HOLDTMR0_Msk : Hold EQEI_CNT by Timer0 + * - \ref EQEI_CTL_HOLDTMR1_Msk : Hold EQEI_CNT by Timer1 + * - \ref EQEI_CTL_HOLDTMR2_Msk : Hold EQEI_CNT by Timer2 + * - \ref EQEI_CTL_HOLDTMR3_Msk : Hold EQEI_CNT by Timer3 + * @return None + * @details This macro disable EQEI counter hold mode. + * \hideinitializer + */ +#define EQEI_DISABLE_HOLD_TRG_SRC(eqei, u32Type) ((eqei)->CTL &= ~(u32Type)) + +/** + * @brief Set EQEI maximum count value + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Value The counter maximum value. + * @return EQEI maximum count value + * @details This macro set EQEI maximum count value. + * \hideinitializer + */ +#define EQEI_SET_CNT_MAX(eqei, u32Value) ((eqei)->CNTMAX = (u32Value)) + +/** + * @brief Set EQEI counting mode + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Mode EQEI counting mode. + * - \ref EQEI_CTL_X4_FREE_COUNTING_MODE + * - \ref EQEI_CTL_X2_FREE_COUNTING_MODE + * - \ref EQEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref EQEI_CTL_X2_COMPARE_COUNTING_MODE + * - \ref EQEI_CTL_PHASE_COUNTING_MODE_TYPE1 + * - \ref EQEI_CTL_PHASE_COUNTING_MODE_TYPE2 + * - \ref EQEI_CTL_DIRECTIONAL_COUNTING_MODE + * @return None + * @details This macro set EQEI counting mode. + * \hideinitializer + */ +#define EQEI_SET_CNT_MODE(eqei, u32Mode) ((eqei)->CTL = ((eqei)->CTL & (~EQEI_CTL_MODE_Msk)) | (u32Mode)) + +/** + * @brief Set EQEI clock rate setting without quadrature mode + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Mode EQEI clock rate setting without quadrature mode. + * - \ref EQEI_CTL2_X1_COUNT_FALLING + * - \ref EQEI_CTL2_X1_COUNT_RISING + * - \ref EQEI_CTL2_X2_COUNT_FALLING_AND_RISING + * @return None + * @details This macro set EQEI clock rate setting without quadrature mode. + * \hideinitializer + */ +#define EQEI_SET_CRS_MODE(eqei, u32Mode) ((eqei)->CTL2 = ((eqei)->CTL2 & (~EQEI_CTL2_CRS_Msk)) | (u32Mode)) + +/** + * @brief Set EQEI direction signal source select + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Mode EQEI direction signal source select. + * - \ref EQEI_CTL2_DIRCTION_FROM_EQEI_CALC + * - \ref EQEI_CTL2_DIRCTION_TIED_HIGH + * - \ref EQEI_CTL2_DIRCTION_TIED_LOW + * @return None + * @details This macro set EQEI direction signal source select. + * \hideinitializer + */ +#define EQEI_SET_DIRSRC_MODE(eqei, u32Mode) ((eqei)->CTL2 = ((eqei)->CTL2 & (~EQEI_CTL2_DIRSRC_Msk)) | (u32Mode)) + + + +void EQEI_Close(EQEI_T* eqei); +void EQEI_DisableInt(EQEI_T* eqei, uint32_t u32IntSel); +void EQEI_EnableInt(EQEI_T* eqei, uint32_t u32IntSel); +void EQEI_Open(EQEI_T* eqei, uint32_t u32Mode, uint32_t u32Value); +void EQEI_Start(EQEI_T* eqei); +void EQEI_Stop(EQEI_T* eqei); + + +/*@}*/ /* end of group EQEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EQEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EQEI_H__ */ + +/*** (C) COPYRIGHT 2021 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_fmc.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_fmc.h new file mode 100644 index 0000000..7880f93 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_fmc.h @@ -0,0 +1,378 @@ +/**************************************************************************//** + * @file fmc.h + * @version V3.00 + * @brief M460 Series Flash Memory Controller Driver Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM base address \hideinitializer */ +#define FMC_APROM_END 0x00100000UL /*!< APROM end address \hideinitializer */ +#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address \hideinitializer */ +#define FMC_LDROM_BASE 0x0F100000UL /*!< LDROM base address \hideinitializer */ +#define FMC_LDROM_END 0x0F102000UL /*!< LDROM end address \hideinitializer */ +#define FMC_XOM_BASE 0x0F200000UL /*!< XOM Base Address \hideinitializer */ +#define FMC_XOMR0_BASE 0x0F200000UL /*!< XOMR 0 Base Address \hideinitializer */ +#define FMC_XOMR1_BASE 0x0F200010UL /*!< XOMR 1 Base Address \hideinitializer */ +#define FMC_XOMR2_BASE 0x0F200020UL /*!< XOMR 2 Base Address \hideinitializer */ +#define FMC_XOMR3_BASE 0x0F200030UL /*!< XOMR 3 Base Address \hideinitializer */ +#define FMC_CONFIG_BASE 0x0F300000UL /*!< User Configuration address \hideinitializer */ +#define FMC_USER_CONFIG_0 0x0F300000UL /*!< User Config 0 address \hideinitializer */ +#define FMC_USER_CONFIG_1 0x0F300004UL /*!< User Config 1 address \hideinitializer */ +#define FMC_USER_CONFIG_2 0x0F300008UL /*!< User Config 2 address \hideinitializer */ +#define FMC_USER_CONFIG_3 0x0F30000CUL /*!< User Config 2 address \hideinitializer */ +#define FMC_OTP_BASE 0x0F310000UL /*!< OTP flash base address \hideinitializer */ +#define FMC_REMAPCFG_BASE 0x0F320000UL /*!< User Configuration address \hideinitializer */ + +#define FMC_FLASH_PAGE_SIZE 0x1000UL /*!< Flash Page Size (4K bytes) \hideinitializer */ +#define FMC_PAGE_ADDR_MASK 0xFFFFF000UL /*!< Flash page address mask \hideinitializer */ +#define FMC_MULTI_WORD_PROG_LEN 512 /*!< The maximum length of a multi-word program. */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size \hideinitializer */ +#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size \hideinitializer */ +#define FMC_LDROM_SIZE 0x2000UL /*!< LDROM Size (4 Kbytes) \hideinitializer */ +#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* XOM region number constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define XOMR0 0UL /*!< XOM region 0 */ +#define XOMR1 1UL /*!< XOM region 1 */ +#define XOMR2 2UL /*!< XOM region 2 */ +#define XOMR3 3UL /*!< XOM region 3 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define IS_BOOT_FROM_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */ +#define IS_BOOT_FROM_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read flash word \hideinitializer */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID \hideinitializer */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result \hideinitializer */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID \hideinitializer */ +#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID \hideinitializer */ +#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read checksum \hideinitializer */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: Write flash word \hideinitializer */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash \hideinitializer */ +#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Multuple word program \hideinitializer */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification \hideinitializer */ +#define FMC_ISPCMD_BANK_REMAP 0x2CUL /*!< ISP Command: Bank Remap \hideinitializer */ +#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run checksum calculation \hideinitializer */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Vector Page Remap \hideinitializer */ +#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: Read double flash word \hideinitializer */ +#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: Write double flash word \hideinitializer */ + + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. \hideinitializer */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. \hideinitializer */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. \hideinitializer */ + +#define FMC_TIMEOUT_READ (SystemCoreClock>>3) /*!< Read command time-out 125 ms \hideinitializer */ +#define FMC_TIMEOUT_WRITE (SystemCoreClock>>3) /*!< Write command time-out 125 ms \hideinitializer */ +#define FMC_TIMEOUT_ERASE (SystemCoreClock>>2) /*!< Erase command time-out 250 ms \hideinitializer */ +#define FMC_TIMEOUT_CHKSUM (SystemCoreClock<<1) /*!< Get checksum command time-out 2 s \hideinitializer */ +#define FMC_TIMEOUT_CHKALLONE (SystemCoreClock<<1) /*!< Check-all-one command time-out 2 s \hideinitializer */ + +/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FMC_EXPORTED_MACROS FMC Exported Macros + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macros */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM \hideinitializer */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM \hideinitializer */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update \hideinitializer */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update \hideinitializer */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update \hideinitializer */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update \hideinitializer */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update \hideinitializer */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update \hideinitializer */ +#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function \hideinitializer */ +#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag \hideinitializer */ +#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */ + +/*@}*/ /* end of group FMC_EXPORTED_MACROS */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global variables */ +/*---------------------------------------------------------------------------------------------------------*/ +extern int32_t g_FMC_i32ErrCode; + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +__STATIC_INLINE uint32_t FMC_ReadCID(void); +__STATIC_INLINE uint32_t FMC_ReadPID(void); +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +__STATIC_INLINE int32_t FMC_SetVectorPageAddr(uint32_t u32PageAddr); +__STATIC_INLINE uint32_t FMC_GetVECMAP(void); + +/** + * @brief Get current vector mapping address. + * @param None + * @return The current vector mapping address. + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + */ +__STATIC_INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Read company ID + * @param None + * @return The company ID (32-bit). 0xFFFFFFFF means read failed. + * @details The company ID of Nuvoton is fixed to be 0xDA + * + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +__STATIC_INLINE uint32_t FMC_ReadCID(void) +{ + int32_t i32TimeOutCnt = FMC_TIMEOUT_READ; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) /* Waiting for ISP Done */ + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + } + + return FMC->ISPDAT; +} + +/** + * @brief Read product ID + * @param None + * @return The product ID (32-bit). 0xFFFFFFFF means read failed. + * @details This function is used to read product ID. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +__STATIC_INLINE uint32_t FMC_ReadPID(void) +{ + int32_t i32TimeOutCnt = FMC_TIMEOUT_READ; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) /* Waiting for ISP Done */ + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + } + + return FMC->ISPDAT; +} + +/** + * @brief Read Unique ID + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * @return The 32-bit unique ID data of specified UID index. 0xFFFFFFFF means read failed. + * @details To read out 96-bit Unique ID. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + int32_t i32TimeOutCnt = FMC_TIMEOUT_READ; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADDR = ((uint32_t)u8Index << 2u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) /* Waiting for ISP Done */ + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + } + + return FMC->ISPDAT; +} + +/** + * @brief To read UCID + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * @return The UCID of specified index + * @details This function is used to read unique chip ID (UCID). 0xFFFFFFFF means read failed. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + int32_t i32TimeOutCnt = FMC_TIMEOUT_READ; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) /* Waiting for ISP Done */ + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + } + + return FMC->ISPDAT; +} + +/** + * @brief Set vector mapping address + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * @return To set VECMAP to remap specified page address to 0x0. + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + * @retval 0 Success + * @retval -1 Failed + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + * + * @note Global error code g_FMC_i32ErrCode + * -1 Command time-out + */ +__STATIC_INLINE int32_t FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + int32_t i32TimeOutCnt = FMC_TIMEOUT_WRITE; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG) /* Waiting for ISP Done */ + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return -1; + } + } + + return 0; +} + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern void FMC_Close(void); +extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr); +extern int32_t FMC_EraseXOM(uint32_t xom_num); +extern int32_t FMC_GetXOMState(uint32_t xom_num); +extern int32_t FMC_GetBootSource(void); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1); +extern uint32_t FMC_ReadDataFlashBaseAddr(void); +extern void FMC_SetBootSource(int32_t i32BootSrc); +extern int32_t FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); +extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_WriteOTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); +extern int32_t FMC_ReadOTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word); +extern int32_t FMC_LockOTP(uint32_t otp_num); +extern int32_t FMC_IsOTPLocked(uint32_t otp_num); +extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count); +extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +extern int32_t FMC_RemapBank(uint32_t u32Bank); + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FMC_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_gpio.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_gpio.h new file mode 100644 index 0000000..6f663a5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_gpio.h @@ -0,0 +1,564 @@ +/**************************************************************************//** + * @file gpio.h + * @version V3.00 + * @brief M460 series GPIO driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode \hideinitializer */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode \hideinitializer */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode \hideinitializer */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge \hideinitializer */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge \hideinitializer */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge \hideinitializer */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High \hideinitializer */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode \hideinitializer */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode \hideinitializer */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode \hideinitializer */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode \hideinitializer */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset \hideinitializer */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz \hideinitializer */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK \hideinitializer */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks \hideinitializer */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks \hideinitializer */ + + +/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + Example 1: + + PA0 = 1; + + It is used to set GPIO PA.0 to high; + + Example 2: + + if (PA0) + PA0 = 0; + + If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low. + */ +#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) /*!< Pin Data Input/Output \hideinitializer */ +#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output \hideinitializer */ +#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output \hideinitializer */ +#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output \hideinitializer */ +#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output \hideinitializer */ +#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output \hideinitializer */ +#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output \hideinitializer */ +#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output \hideinitializer */ +#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output \hideinitializer */ +#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output \hideinitializer */ +#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output \hideinitializer */ +#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output \hideinitializer */ +#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output \hideinitializer */ +#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output \hideinitializer */ +#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output \hideinitializer */ +#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output \hideinitializer */ +#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output \hideinitializer */ +#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output \hideinitializer */ +#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output \hideinitializer */ +#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output \hideinitializer */ +#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output \hideinitializer */ +#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output \hideinitializer */ +#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output \hideinitializer */ +#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output \hideinitializer */ +#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output \hideinitializer */ +#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output \hideinitializer */ +#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output \hideinitializer */ +#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output \hideinitializer */ +#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output \hideinitializer */ +#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output \hideinitializer */ +#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output \hideinitializer */ +#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output \hideinitializer */ +#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output \hideinitializer */ +#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output \hideinitializer */ +#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output \hideinitializer */ +#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output \hideinitializer */ +#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output \hideinitializer */ +#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output \hideinitializer */ +#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output \hideinitializer */ +#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output \hideinitializer */ +#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output \hideinitializer */ +#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output \hideinitializer */ +#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output \hideinitializer */ +#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output \hideinitializer */ +#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output \hideinitializer */ +#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output \hideinitializer */ +#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output \hideinitializer */ +#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output \hideinitializer */ +#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output \hideinitializer */ +#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output \hideinitializer */ +#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output \hideinitializer */ +#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output \hideinitializer */ +#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output \hideinitializer */ +#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output \hideinitializer */ +#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output \hideinitializer */ +#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output \hideinitializer */ +#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output \hideinitializer */ +#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output \hideinitializer */ +#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output \hideinitializer */ +#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output \hideinitializer */ +#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output \hideinitializer */ +#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output \hideinitializer */ +#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output \hideinitializer */ +#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output \hideinitializer */ +#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output \hideinitializer */ +#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output \hideinitializer */ +#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output \hideinitializer */ +#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output \hideinitializer */ +#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output \hideinitializer */ +#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output \hideinitializer */ +#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output \hideinitializer */ +#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output \hideinitializer */ +#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output \hideinitializer */ +#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output \hideinitializer */ +#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output \hideinitializer */ +#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output \hideinitializer */ +#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output \hideinitializer */ +#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output \hideinitializer */ +#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output \hideinitializer */ +#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output \hideinitializer */ +#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output \hideinitializer */ +#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output \hideinitializer */ +#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output \hideinitializer */ +#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output \hideinitializer */ +#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output \hideinitializer */ +#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output \hideinitializer */ +#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output \hideinitializer */ +#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output \hideinitializer */ +#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output \hideinitializer */ +#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output \hideinitializer */ +#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output \hideinitializer */ +#define PG0 GPIO_PIN_DATA(6, 0 ) /*!< Specify PG.0 Pin Data Input/Output \hideinitializer */ +#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output \hideinitializer */ +#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output \hideinitializer */ +#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output \hideinitializer */ +#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output \hideinitializer */ +#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output \hideinitializer */ +#define PG6 GPIO_PIN_DATA(6, 6 ) /*!< Specify PG.6 Pin Data Input/Output \hideinitializer */ +#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output \hideinitializer */ +#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output \hideinitializer */ +#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output \hideinitializer */ +#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output \hideinitializer */ +#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output \hideinitializer */ +#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output \hideinitializer */ +#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output \hideinitializer */ +#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output \hideinitializer */ +#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output \hideinitializer */ +#define PH0 GPIO_PIN_DATA(7, 0 ) /*!< Specify PH.0 Pin Data Input/Output \hideinitializer */ +#define PH1 GPIO_PIN_DATA(7, 1 ) /*!< Specify PH.1 Pin Data Input/Output \hideinitializer */ +#define PH2 GPIO_PIN_DATA(7, 2 ) /*!< Specify PH.2 Pin Data Input/Output \hideinitializer */ +#define PH3 GPIO_PIN_DATA(7, 3 ) /*!< Specify PH.3 Pin Data Input/Output \hideinitializer */ +#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output \hideinitializer */ +#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output \hideinitializer */ +#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output \hideinitializer */ +#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output \hideinitializer */ +#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output \hideinitializer */ +#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output \hideinitializer */ +#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output \hideinitializer */ +#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output \hideinitializer */ +#define PH12 GPIO_PIN_DATA(7, 12) /*!< Specify PH.12 Pin Data Input/Output \hideinitializer */ +#define PH13 GPIO_PIN_DATA(7, 13) /*!< Specify PH.13 Pin Data Input/Output \hideinitializer */ +#define PH14 GPIO_PIN_DATA(7, 14) /*!< Specify PH.14 Pin Data Input/Output \hideinitializer */ +#define PH15 GPIO_PIN_DATA(7, 15) /*!< Specify PH.15 Pin Data Input/Output \hideinitializer */ +#define PI6 GPIO_PIN_DATA(8, 6 ) /*!< Specify PI.6 Pin Data Input/Output \hideinitializer */ +#define PI7 GPIO_PIN_DATA(8, 7 ) /*!< Specify PI.7 Pin Data Input/Output \hideinitializer */ +#define PI8 GPIO_PIN_DATA(8, 8 ) /*!< Specify PI.8 Pin Data Input/Output \hideinitializer */ +#define PI9 GPIO_PIN_DATA(8, 9 ) /*!< Specify PI.9 Pin Data Input/Output \hideinitializer */ +#define PI10 GPIO_PIN_DATA(8, 10) /*!< Specify PI.10 Pin Data Input/Output \hideinitializer */ +#define PI11 GPIO_PIN_DATA(8, 11) /*!< Specify PI.11 Pin Data Input/Output \hideinitializer */ +#define PI12 GPIO_PIN_DATA(8, 12) /*!< Specify PI.12 Pin Data Input/Output \hideinitializer */ +#define PI13 GPIO_PIN_DATA(8, 13) /*!< Specify PI.13 Pin Data Input/Output \hideinitializer */ +#define PI14 GPIO_PIN_DATA(8, 14) /*!< Specify PI.14 Pin Data Input/Output \hideinitializer */ +#define PI15 GPIO_PIN_DATA(8, 15) /*!< Specify PI.15 Pin Data Input/Output \hideinitializer */ +#define PJ0 GPIO_PIN_DATA(9, 0 ) /*!< Specify PJ.0 Pin Data Input/Output \hideinitializer */ +#define PJ1 GPIO_PIN_DATA(9, 1 ) /*!< Specify PJ.1 Pin Data Input/Output \hideinitializer */ +#define PJ2 GPIO_PIN_DATA(9, 2 ) /*!< Specify PJ.2 Pin Data Input/Output \hideinitializer */ +#define PJ3 GPIO_PIN_DATA(9, 3 ) /*!< Specify PJ.3 Pin Data Input/Output \hideinitializer */ +#define PJ4 GPIO_PIN_DATA(9, 4 ) /*!< Specify PJ.4 Pin Data Input/Output \hideinitializer */ +#define PJ5 GPIO_PIN_DATA(9, 5 ) /*!< Specify PJ.5 Pin Data Input/Output \hideinitializer */ +#define PJ6 GPIO_PIN_DATA(9, 6 ) /*!< Specify PJ.6 Pin Data Input/Output \hideinitializer */ +#define PJ7 GPIO_PIN_DATA(9, 7 ) /*!< Specify PJ.7 Pin Data Input/Output \hideinitializer */ +#define PJ8 GPIO_PIN_DATA(9, 8 ) /*!< Specify PJ.8 Pin Data Input/Output \hideinitializer */ +#define PJ9 GPIO_PIN_DATA(9, 9 ) /*!< Specify PJ.9 Pin Data Input/Output \hideinitializer */ +#define PJ10 GPIO_PIN_DATA(9, 10) /*!< Specify PJ.10 Pin Data Input/Output \hideinitializer */ +#define PJ11 GPIO_PIN_DATA(9, 11) /*!< Specify PJ.11 Pin Data Input/Output \hideinitializer */ +#define PJ12 GPIO_PIN_DATA(9, 12) /*!< Specify PJ.12 Pin Data Input/Output \hideinitializer */ +#define PJ13 GPIO_PIN_DATA(9, 13) /*!< Specify PJ.13 Pin Data Input/Output \hideinitializer */ + +/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + * \hideinitializer + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be + * - \ref GPIO_DBCTL_DBCLKSRC_HCLK + * - \ref GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: GPIO_SET_DEBOUNCE_TIME(PA, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 400 us. + */ +#define GPIO_SET_DEBOUNCE_TIME(port, u32ClkSrc, u32ClkSel) ((port)->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Set GPIO Interrupt Clock on bit + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @return None + * @details Set the I/O pins edge detection circuit always active after reset for specified port. + */ +#define GPIO_SET_DEBOUNCE_ICLKON(port) ((port)->DBCTL |= GPIO_DBCTL_ICLKON_Msk) + +/** + * @brief Clear GPIO Interrupt Clock on bit + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @return None + * @details Set edge detection circuit active only if I/O pin edge interrupt enabled for specified port. + */ +#define GPIO_CLR_DEBOUNCE_ICLKON(port) ((port)->DBCTL &= ~(GPIO_DBCTL_ICLKON_Msk)) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + * \hideinitializer + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + * \hideinitializer + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + * \hideinitializer + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be 0 ~ 14 for PC and PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 6 ~ 15 for PI GPIO port. \n + * It could be 0 ~ 13 for PJ GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * - \ref GPIO_INT_RISING + * - \ref GPIO_INT_FALLING + * - \ref GPIO_INT_BOTH_EDGE + * - \ref GPIO_INT_HIGH + * - \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be 0 ~ 14 for PC and PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 6 ~ 15 for PI GPIO port. \n + * It could be 0 ~ 13 for PJ GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + * \hideinitializer + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hbi.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hbi.h new file mode 100644 index 0000000..b7e0b86 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hbi.h @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file hbi.h + * @version V1.00 + * @brief M460 series HBI driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __HBI_H__ +#define __HBI_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HyperBus Interface Driver + @{ +*/ + + +/** @addtogroup HBI_EXPORTED_CONSTANTS HBI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* HyperRAM Register Space constant definitions +Register Space Range: + 0x0000_0000 = Identification Register 0 + 0x0000_0002 = Identification Register 1 + 0x0000_1000 = Configuration Register 0 + 0x0000_1002 = Configuration Register 1 +*/ +#define HYPERRAM_ID_REG0 0x00000000 +#define HYPERRAM_ID_REG1 0x00000002 +#define HYPERRAM_CONFIG_REG0 0x00001000 +#define HYPERRAM_CONFIG_REG1 0x00001002 +/*---------------------------------------------------------------------------------------------------------*/ +/* HBI_CMD constant definitions +0001 = Reset HyperRAM +0010 = Read HyperRAM regsiter (16-Bit, Read Data[15:0] +0101 = Exit From Hybrid Sleep and deep power down +0111 = Write HyperRAM regsiter (16-Bit, Write Data[15:0] +1000 = Read 1 word (Read Data[15:0]) from HyperRAM +1001 = Read 2 word (Read Data[31:0]) from HyperRAM +1100 = Write 1 Byte (Write Data[7:0]) to HyperRAM +1101 = Write 2 Bytes (Write Data[15:0]) to HyperRAM +1110 = Write 3 Byte (Write Data[23:0]) to HyperRAM +1111 = Write 4 Byte (Write Data[31:0]) to HyperRAM +*/ +/*---------------------------------------------------------------------------------------------------------*/ +#define HBI_CMD_RESET_HRAM 0x1 +#define HBI_CMD_READ_HRAM_REGISTER 0x2 +#define HBI_CMD_EXIT_HS_PD 0x5 +#define HBI_CMD_WRITE_HRAM_REGISTER 0x7 +#define HBI_CMD_READ_HRAM_1_WORD 0x8 +#define HBI_CMD_READ_HRAM_2_WORD 0x9 +#define HBI_CMD_WRITE_HRAM_1_BYTE 0xC +#define HBI_CMD_WRITE_HRAM_2_BYTE 0xD +#define HBI_CMD_WRITE_HRAM_3_BYTE 0xE +#define HBI_CMD_WRITE_HRAM_4_BYTE 0xF +#define HBI_CMD_HRAM_IDLE 0x0 +/*---------------------------------------------------------------------------------------------------------*/ +/* HBI_CONFIG: Chip Select Setup Time to Next CK Rising Edge constant definitions +00 = 1.5 HCLK cycles. +01 = 2.5 HCLK cycles. +10 = 3.5 HCLK cycles. +11 = 4.5 HCLK cycles. +*/ +/*---------------------------------------------------------------------------------------------------------*/ +#define HBI_CONFIG_CSST_1_5_HCLK (0x0 << HBI_CONFIG_CSST_Pos) +#define HBI_CONFIG_CSST_2_5_HCLK (0x1 << HBI_CONFIG_CSST_Pos) +#define HBI_CONFIG_CSST_3_5_HCLK (0x2 << HBI_CONFIG_CSST_Pos) +#define HBI_CONFIG_CSST_4_5_HCLK (0x3 << HBI_CONFIG_CSST_Pos) +/*---------------------------------------------------------------------------------------------------------*/ +/* HBI_CONFIG: Initial Access Time constant definitions +0000 = 5 HCLK cycles. +0001 = 6 HCLK cycles. +0010 = 7 HCLK cycles. +1110 = 3 HCLK cycles. +1111 = 4 HCLK cycles. +*/ +/*---------------------------------------------------------------------------------------------------------*/ +#define HBI_CONFIG_ACCT_5_CK (0x0 << HBI_CONFIG_ACCT_Pos) +#define HBI_CONFIG_ACCT_6_CK (0x1 << HBI_CONFIG_ACCT_Pos) +#define HBI_CONFIG_ACCT_7_CK (0x2 << HBI_CONFIG_ACCT_Pos) +#define HBI_CONFIG_ACCT_3_CK (0xE << HBI_CONFIG_ACCT_Pos) +#define HBI_CONFIG_ACCT_4_CK (0xF << HBI_CONFIG_ACCT_Pos) +/*---------------------------------------------------------------------------------------------------------*/ +/* HBI_CONFIG: Chip Select Hold Time After CK Falling Edge constant definitions +00 = 0.5 HCLK cycles. +01 = 1.5 HCLK cycles. +10 = 2.5 HCLK cycles. +11 = 3.5 HCLK cycles. +*/ +/*---------------------------------------------------------------------------------------------------------*/ +#define HBI_CONFIG_CSH_0_5_HCLK (0x0 << HBI_CONFIG_CSH_Pos) +#define HBI_CONFIG_CSH_1_5_HCLK (0x1 << HBI_CONFIG_CSH_Pos) +#define HBI_CONFIG_CSH_2_5_HCLK (0x2 << HBI_CONFIG_CSH_Pos) +#define HBI_CONFIG_CSH_3_5_HCLK (0x3 << HBI_CONFIG_CSH_Pos) +/*---------------------------------------------------------------------------------------------------------*/ +/* HBI_CONFIG: Burst Group Size constant definitions +00 = 128 Bytes. +01 = 64 Bytes. +10 = 16 Bytes. +11 = 32 Bytes. +*/ +/*---------------------------------------------------------------------------------------------------------*/ +#define HBI_CONFIG_BGSIZE_128 (0x0 << HBI_CONFIG_BGSIZE_Pos) +#define HBI_CONFIG_BGSIZE_64 (0x1 << HBI_CONFIG_BGSIZE_Pos) +#define HBI_CONFIG_BGSIZE_16 (0x2 << HBI_CONFIG_BGSIZE_Pos) +#define HBI_CONFIG_BGSIZE_32 (0x3 << HBI_CONFIG_BGSIZE_Pos) +/*---------------------------------------------------------------------------------------------------------*/ +/* HBI_CONFIG: Endian Condition on the Hyper Bus Data Pipe constant definitions +0 = Little-Endian. +1 = Big-Endian. +*/ +/*---------------------------------------------------------------------------------------------------------*/ +#define HBI_CONFIG_LITTLE_ENDIAN (0x0 << HBI_CONFIG_ENDIAN_Pos) +#define HBI_CONFIG_BIG_ENDIAN (0x1 << HBI_CONFIG_ENDIAN_Pos) +/*---------------------------------------------------------------------------------------------------------*/ +/* HBI_CONFIG: Hyper Bus Clock Divider constant definitions +0 = Hyper Bus Clock rate is HCLK/2. +1 = Hyper Bus Clock rate is HCLK/4. +*/ +/*---------------------------------------------------------------------------------------------------------*/ +#define HBI_CONFIG_CKDIV_HCLK_DIV2 (0x0 << HBI_CONFIG_CKDIV_Pos) +#define HBI_CONFIG_CKDIV_HCLK_DIV4 (0x1 << HBI_CONFIG_CKDIV_Pos) +/*---------------------------------------------------------------------------------------------------------*/ + +#define HBI_TIMEOUT SystemCoreClock /*!< 1 second time-out \hideinitializer */ +#define HBI_TIMEOUT_ERR (-2L) /*!< HBI operation abort due to timeout error \hideinitializer */ +extern int32_t g_HBI_i32ErrCode; + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Set HBI Chip Select Setup Time to Next CK Rising Edge + * @param[in] u8Value Chip Select Setup Time to Next CK Rising Edge. + * - \ref HBI_CONFIG_CSST_1_5_HCLK : 1.5 HCLK cycles + * - \ref HBI_CONFIG_CSST_2_5_HCLK : 2.5 HCLK cycles + * - \ref HBI_CONFIG_CSST_3_5_HCLK : 3.5 HCLK cycles + * - \ref HBI_CONFIG_CSST_4_5_HCLK : 4.5 HCLK cycles + * @return None + * @details This macro set HBI Chip Select Setup Time to Next CK Rising Edge + * \hideinitializer + */ +#define HBI_CONFIG_SET_CSST(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSST_Msk))) | u8Value) + +/** + * @brief Set HBI Initial Access Time + * @param[in] u8Value Initial Access Time. + * - \ref HBI_CONFIG_ACCT_5_CK : 5 CK cycles + * - \ref HBI_CONFIG_ACCT_6_CK : 6 CK cycles + * - \ref HBI_CONFIG_ACCT_7_CK : 7 CK cycles + * - \ref HBI_CONFIG_ACCT_3_CK : 3 CK cycles + * - \ref HBI_CONFIG_ACCT_4_CK : 4 CK cycles + * @return None + * @details This macro set HBI Initial Access Time + * \hideinitializer + */ +#define HBI_CONFIG_SET_ACCT(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_ACCT_Msk))) | u8Value) + +/** + * @brief Set HBI Chip Select Hold Time After CK Falling Edge + * @param[in] u8Value Chip Select Hold Time After CK Falling Edge. + * - \ref HBI_CONFIG_CSH_0_5_HCLK : 0.5 HCLK cycles + * - \ref HBI_CONFIG_CSH_1_5_HCLK : 1.5 HCLK cycles + * - \ref HBI_CONFIG_CSH_2_5_HCLK : 2.5 HCLK cycles + * - \ref HBI_CONFIG_CSH_3_5_HCLK : 3.5 HCLK cycles + * @return None + * @details This macro set HBI Chip Select Hold Time After CK Falling Edge + * \hideinitializer + */ +#define HBI_CONFIG_SET_CSH(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSH_Msk))) | u8Value) + +/** + * @brief Set HBI Chip Select High between Transaction + * @param[in] u8Value Set Chip Select High between Transaction as u8Value HCLK cycles + u8Value must be 1 ~ 16 + * @return None + * @details This macro set HBI Chip Select High between Transaction. + * \hideinitializer + */ +#define HBI_CONFIG_SET_CSHI(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSHI_Msk))) | ((u8Value-1) << HBI_CONFIG_CSHI_Pos)) + +/** + * @brief Set HBI Burst Group Size + * @param[in] u8Value Burst Group Size. + * - \ref HBI_CONFIG_BGSIZE_128 : 128 Bytes + * - \ref HBI_CONFIG_BGSIZE_64 : 64 Bytes + * - \ref HBI_CONFIG_BGSIZE_16 : 16 Bytes + * - \ref HBI_CONFIG_BGSIZE_32 : 32 Bytes + * @return None + * @details This macro set HBI Burst Group Size + * \hideinitializer + */ +#define HBI_CONFIG_SET_BGSIZE(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_BGSIZE_Msk))) | u8Value) + +/** + * @brief Set HBI Endian Condition on the Hyper Bus Data Pipe + * @param[in] u8Value Endian Condition on the Hyper Bus Data Pipe. + * - \ref HBI_CONFIG_LITTLE_ENDIAN : Little-Endian + * - \ref HBI_CONFIG_BIG_ENDIAN : Big-Endian + * @return None + * @details This macro set HBI Endian Condition on the Hyper Bus Data Pipe + * \hideinitializer + */ +#define HBI_CONFIG_SET_ENDIAN(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_ENDIAN_Msk))) | u8Value) + +/** + * @brief Set HBI Hyper Bus Clock Divider + * @param[in] u8Value Hyper Bus Clock Divider. + * - \ref HBI_CONFIG_CKDIV_HCLK_DIV2 : HCLK/2 + * - \ref HBI_CONFIG_CKDIV_HCLK_DIV4 : HCLK/4 + * @return None + * @details This macro set Hyper Bus Clock Divider + * \hideinitializer + */ +#define HBI_CONFIG_SET_CKDIV(u8Value) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CKDIV_Msk))) | u8Value) + +/** + * @brief Set HBI Chip Select Maximum Low Time + * @param[in] u32CsMaxLT Set HBI Chip Select Maximum Low Time as u32CsMaxLT HCLK cycles. + u32CsMaxLT must be 1 ~ 2048 + * @return None + * @details This macro set HBI Chip Select Maximum Low Time. + * \hideinitializer + */ +#define HBI_CONFIG_SET_CSMAXLT(u32CsMaxLT) (HBI->CONFIG = (HBI->CONFIG & (~(HBI_CONFIG_CSMAXLT_Msk))) | ((u32CsMaxLT-1) << HBI_CONFIG_CSMAXLT_Pos)) + +/** + * @brief Enable HyperBus Operation Done Interrupt + * @param[in] None + * @return None + * @details This macro enable HyperBus Operation Done Interrupt. + * \hideinitializer + */ +#define HBI_ENABLE_INT (HBI->INTEN |= HBI_INTEN_OPINTEN_Msk) + +/** + * @brief Disable HyperBus Operation Done Interrupt + * @param[in] None + * @return None + * @details This macro disable HyperBus Operation Done Interrupt. + * \hideinitializer + */ +#define HBI_DISABLE_INT (HBI->INTEN &= ~HBI_INTEN_OPINTEN_Msk) + +/////////////////// +/** + * @brief Get HyperBus Operation Done Interrupt + * @param[in] None + * @return 0 = HyperBus operation is busy. + * 1 = HyperBus operation is done. + * @details This macro Get HyperBus Operation Done Interrupt. + * \hideinitializer + */ +#define HBI_GET_INTSTS ((HBI->INTSTS & HBI_INTSTS_OPDONE_Msk)? 1:0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Function Prototypes */ +/*---------------------------------------------------------------------------------------------------------*/ +void HBI_ResetHyperRAM(void); +void HBI_ExitHSAndDPD(void); +int32_t HBI_ReadHyperRAMReg(uint32_t u32Addr); +int32_t HBI_WriteHyperRAMReg(uint32_t u32Addr, uint32_t u32Value); +uint32_t HBI_Read1Word(uint32_t u32Addr); +uint32_t HBI_Read2Word(uint32_t u32Addr); +void HBI_Write1Byte(uint32_t u32Addr, uint8_t u8Data); +void HBI_Write2Byte(uint32_t u32Addr, uint16_t u16Data); +void HBI_Write3Byte(uint32_t u32Addr, uint32_t u32Data); +void HBI_Write4Byte(uint32_t u32Addr, uint32_t u32Data); + +/*@}*/ /* end of group HBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HBI_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hsotg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hsotg.h new file mode 100644 index 0000000..96b28f3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hsotg.h @@ -0,0 +1,290 @@ +/**************************************************************************//** + * @file hsotg.h + * @version V3.00 + * @brief M460 series HSOTG driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ****************************************************************************/ +#ifndef __HSOTG_H__ +#define __HSOTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSOTG_Driver HSOTG Driver + @{ +*/ + + +/** @addtogroup HSOTG_EXPORTED_CONSTANTS HSOTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* HSOTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define HSOTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define HSOTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define HSOTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + +#define HSOTG_PHYCTL_FSEL_9_6M (0UL << HSOTG_PHYCTL_FSEL_Pos) /*!< Setting OTG PHY reference clock frequency as 9.6 MHz. \hideinitializer */ +#define HSOTG_PHYCTL_FSEL_10_0M (1UL << HSOTG_PHYCTL_FSEL_Pos) /*!< Setting OTG PHY reference clock frequency as 10 MHz. \hideinitializer */ +#define HSOTG_PHYCTL_FSEL_12_0M (2UL << HSOTG_PHYCTL_FSEL_Pos) /*!< Setting OTG PHY reference clock frequency as 12 MHz. \hideinitializer */ +#define HSOTG_PHYCTL_FSEL_19_2M (3UL << HSOTG_PHYCTL_FSEL_Pos) /*!< Setting OTG PHY reference clock frequency as 19.2 MHz. \hideinitializer */ +#define HSOTG_PHYCTL_FSEL_20_0M (4UL << HSOTG_PHYCTL_FSEL_Pos) /*!< Setting OTG PHY reference clock frequency as 20 MHz. \hideinitializer */ +#define HSOTG_PHYCTL_FSEL_24_0M (5UL << HSOTG_PHYCTL_FSEL_Pos) /*!< Setting OTG PHY reference clock frequency as 24 MHz. \hideinitializer */ +#define HSOTG_PHYCTL_FSEL_50_0M (7UL << HSOTG_PHYCTL_FSEL_Pos) /*!< Setting OTG PHY reference clock frequency as 50 MHz. \hideinitializer */ + + +/*@}*/ /* end of group HSOTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup HSOTG_EXPORTED_FUNCTIONS HSOTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable HSOTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of HSOTG_CTL register to enable HSOTG function. + * \hideinitializer + */ +#define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable HSOTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of HSOTG_CTL register to disable HSOTG function. + * \hideinitializer + */ +#define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as HSOTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of HSOTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define HSOTG_ENABLE_PHY() (HSOTG->PHYCTL |= HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of HSOTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define HSOTG_DISABLE_PHY() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of HSOTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define HSOTG_ENABLE_ID_DETECT() (HSOTG->PHYCTL |= HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of HSOTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define HSOTG_DISABLE_ID_DETECT() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable HSOTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of HSOTG_CTL register to enable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable HSOTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of HSOTG_CTL register to disable HSOTG wake-up function. + * \hideinitializer + */ +#define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref HSOTG_VBUS_EN_ACTIVE_HIGH + * - \ref HSOTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define HSOTG_SET_VBUS_EN_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol) << HSOTG_PHYCTL_VBENPOL_Pos)) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_ST pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref HSOTG_VBUS_ST_VALID_HIGH + * - \ref HSOTG_VBUS_ST_VALID_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch status signal. + * \hideinitializer + */ +#define HSOTG_SET_VBUS_STS_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol) << HSOTG_PHYCTL_VBSTSPOL_Pos)) + +/** + * @brief This macro is used to enable HSOTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTEN_ROLECHGIEN_Msk + * - \ref HSOTG_INTEN_VBEIEN_Msk + * - \ref HSOTG_INTEN_SRPFIEN_Msk + * - \ref HSOTG_INTEN_HNPFIEN_Msk + * - \ref HSOTG_INTEN_GOIDLEIEN_Msk + * - \ref HSOTG_INTEN_IDCHGIEN_Msk + * - \ref HSOTG_INTEN_PDEVIEN_Msk + * - \ref HSOTG_INTEN_HOSTIEN_Msk + * - \ref HSOTG_INTEN_BVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_AVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_VBCHGIEN_Msk + * - \ref HSOTG_INTEN_SECHGIEN_Msk + * - \ref HSOTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will enable HSOTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_ENABLE_INT(u32Mask) (HSOTG->INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable HSOTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTEN_ROLECHGIEN_Msk + * - \ref HSOTG_INTEN_VBEIEN_Msk + * - \ref HSOTG_INTEN_SRPFIEN_Msk + * - \ref HSOTG_INTEN_HNPFIEN_Msk + * - \ref HSOTG_INTEN_GOIDLEIEN_Msk + * - \ref HSOTG_INTEN_IDCHGIEN_Msk + * - \ref HSOTG_INTEN_PDEVIEN_Msk + * - \ref HSOTG_INTEN_HOSTIEN_Msk + * - \ref HSOTG_INTEN_BVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_AVLDCHGIEN_Msk + * - \ref HSOTG_INTEN_VBCHGIEN_Msk + * - \ref HSOTG_INTEN_SECHGIEN_Msk + * - \ref HSOTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable HSOTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear HSOTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref HSOTG_INTSTS_ROLECHGIF_Msk + * - \ref HSOTG_INTSTS_VBEIF_Msk + * - \ref HSOTG_INTSTS_SRPFIF_Msk + * - \ref HSOTG_INTSTS_HNPFIF_Msk + * - \ref HSOTG_INTSTS_GOIDLEIF_Msk + * - \ref HSOTG_INTSTS_IDCHGIF_Msk + * - \ref HSOTG_INTSTS_PDEVIF_Msk + * - \ref HSOTG_INTSTS_HOSTIF_Msk + * - \ref HSOTG_INTSTS_BVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_AVLDCHGIF_Msk + * - \ref HSOTG_INTSTS_VBCHGIF_Msk + * - \ref HSOTG_INTSTS_SECHGIF_Msk + * - \ref HSOTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear HSOTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get HSOTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref HSOTG_STATUS_OVERCUR_Msk + * - \ref HSOTG_STATUS_IDSTS_Msk + * - \ref HSOTG_STATUS_SESSEND_Msk + * - \ref HSOTG_STATUS_BVLD_Msk + * - \ref HSOTG_STATUS_AVLD_Msk + * - \ref HSOTG_STATUS_VBUSVLD_Msk + * - \ref HSOTG_STATUS_ASPERI_Msk + * - \ref HSOTG_STATUS_ASHOST_Msk + * @return The user specified status. + * @details This macro will return HSOTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask)) + +/** + * @brief Set OTG PHY reference clock frequency + * @param[in] u32RefClock The reference clock selection. Valid values are listed below. + * - \ref HSOTG_PHYCTL_FSEL_9_6M + * - \ref HSOTG_PHYCTL_FSEL_10_0M + * - \ref HSOTG_PHYCTL_FSEL_12_0M + * - \ref HSOTG_PHYCTL_FSEL_19_2M + * - \ref HSOTG_PHYCTL_FSEL_20_0M + * - \ref HSOTG_PHYCTL_FSEL_24_0M + * - \ref HSOTG_PHYCTL_FSEL_50_0M + * @return None + * @details This macro set OTG PHY reference clock frequency. + * \hideinitializer + */ +#define HSOTG_SET_PHY_REF_CLK(u32RefClock) (HSOTG->PHYCTL = (HSOTG->PHYCTL & ~HSOTG_PHYCTL_FSEL_Msk) | (u32RefClock)) + + + +/*@}*/ /* end of group HSOTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSOTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HSOTG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hsusbd.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hsusbd.h new file mode 100644 index 0000000..2c56c01 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_hsusbd.h @@ -0,0 +1,404 @@ +/**************************************************************************//** + * @file hsusbd.h + * @version V3.00 + * @brief M460 series HSUSBD driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ****************************************************************************/ +#ifndef __HSUSBD_H__ +#define __HSUSBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + +/** @addtogroup HSUSBD_EXPORTED_CONSTANTS HSUSBD Exported Constants + @{ +*/ +/** @cond HIDDEN_SYMBOLS */ +#define HSUSBD_MAX_EP 12ul + +#define Maximum(a,b) (a)>(b) ? (a) : (b) +#define Minimum(a,b) (((a)<(b)) ? (a) : (b)) + + +#define CEP 0xfful /*!< Control Endpoint \hideinitializer */ +#define EPA 0ul /*!< Endpoint A \hideinitializer */ +#define EPB 1ul /*!< Endpoint B \hideinitializer */ +#define EPC 2ul /*!< Endpoint C \hideinitializer */ +#define EPD 3ul /*!< Endpoint D \hideinitializer */ +#define EPE 4ul /*!< Endpoint E \hideinitializer */ +#define EPF 5ul /*!< Endpoint F \hideinitializer */ +#define EPG 6ul /*!< Endpoint G \hideinitializer */ +#define EPH 7ul /*!< Endpoint H \hideinitializer */ +#define EPI 8ul /*!< Endpoint I \hideinitializer */ +#define EPJ 9ul /*!< Endpoint J \hideinitializer */ +#define EPK 10ul /*!< Endpoint K \hideinitializer */ +#define EPL 11ul /*!< Endpoint L \hideinitializer */ + +/** @endcond HIDDEN_SYMBOLS */ +/********************* Bit definition of CEPCTL register **********************/ +#define HSUSBD_CEPCTL_NAKCLR ((uint32_t)0x00000000ul) /*!PHYCTL |= (HSUSBD_PHYCTL_PHYEN_Msk|HSUSBD_PHYCTL_DPPUEN_Msk))) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_PHYEN_Msk)) /*!PHYCTL &= ~HSUSBD_PHYCTL_DPPUEN_Msk)) /*!PHYCTL |= HSUSBD_PHYCTL_DPPUEN_Msk)) /*!FADDR = (addr)) /*!FADDR)) /*!GINTEN = (intr)) /*!BUSINTEN = (intr)) /*!BUSINTSTS) /*!BUSINTSTS = (flag)) /*!CEPINTEN = (intr)) /*!CEPINTSTS = (flag)) /*!CEPCTL = (flag)) /*!CEPTXCNT = (size)) /*!EP[(ep)].EPMPS = (size)) /*!EP[(ep)].EPINTEN = (intr)) /*!EP[(ep)].EPINTSTS) /*!EP[(ep)].EPINTSTS = (flag)) /*!DMACNT = (len)) /*!DMAADDR = (addr)) /*!DMACTL = (HSUSBD->DMACTL & ~HSUSBD_DMACTL_EPNUM_Msk) | HSUSBD_DMACTL_DMARD_Msk | (epnum) | 0x100) /*!DMACTL = (HSUSBD->DMACTL & ~(HSUSBD_DMACTL_EPNUM_Msk | HSUSBD_DMACTL_DMARD_Msk | 0x100)) | (epnum)) /*!DMACTL |= HSUSBD_DMACTL_DMAEN_Msk) /*!PHYCTL & HSUSBD_PHYCTL_VBUSDET_Msk)) /*!BCDC |= HSUSBD_BCDC_BCDEN_Msk)) /*!BCDC &= ~HSUSBD_BCDC_BCDEN_Msk)) /*!LPMCSR |= HSUSBD_LPMCSR_LPMEN_Msk)) /*!LPMCSR &= ~HSUSBD_LPMCSR_LPMEN_Msk)) /*!DMACNT = 0ul; + HSUSBD->DMACTL = 0x80ul; + HSUSBD->DMACTL = 0x00ul; +} +/** + * @brief HSUSBD_SetEpBufAddr, Set Endpoint buffer address + * @param[in] u32Ep Endpoint Number + * @param[in] u32Base Buffer Start Address + * @param[in] u32Len Buffer length + * @retval None. + */ +__STATIC_INLINE void HSUSBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len) +{ + if (u32Ep == CEP) + { + HSUSBD->CEPBUFST = u32Base; + HSUSBD->CEPBUFEND = u32Base + u32Len - 1ul; + } + else + { + HSUSBD->EP[u32Ep].EPBUFST = u32Base; + HSUSBD->EP[u32Ep].EPBUFEND = u32Base + u32Len - 1ul; + } +} + +/** + * @brief HSUSBD_ConfigEp, Config Endpoint + * @param[in] u32Ep USB endpoint + * @param[in] u32EpNum Endpoint number + * @param[in] u32EpType Endpoint type + * @param[in] u32EpDir Endpoint direction + * @retval None. + */ +__STATIC_INLINE void HSUSBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir) +{ + if (u32EpType == HSUSBD_EP_CFG_TYPE_BULK) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_AUTO); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_INT) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_MANUAL); + } + else if (u32EpType == HSUSBD_EP_CFG_TYPE_ISO) + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD_EP_RSPCTL_FLUSH|HSUSBD_EP_RSPCTL_MODE_FLY); + } + + HSUSBD->EP[u32Ep].EPCFG = (u32EpType|u32EpDir|HSUSBD_EP_CFG_VALID|(u32EpNum << 4)); +} + +/** + * @brief Set USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + */ +__STATIC_INLINE void HSUSBD_SetEpStall(uint32_t u32Ep) +{ + if (u32Ep == CEP) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + HSUSBD->EP[u32Ep].EPRSPCTL = (HSUSBD->EP[u32Ep].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Set USB endpoint stall state, endpoint will return STALL token. + */ +__STATIC_INLINE void HSUSBD_SetStall(uint32_t u32EpNum) +{ + uint32_t i; + + if (u32EpNum == 0ul) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALL); + } + else + { + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xf7ul) | HSUSBD_EP_RSPCTL_HALT; + } + } + } +} + +/** + * @brief Clear USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @return None + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearEpStall(uint32_t u32Ep) +{ + HSUSBD->EP[u32Ep].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @return None + * + * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token. + */ +__STATIC_INLINE void HSUSBD_ClearStall(uint32_t u32EpNum) +{ + uint32_t i; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } +} + +/** + * @brief Get USB endpoint stall state + * @param[in] u32Ep The USB endpoint ID. + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * @details Get USB endpoint stall state of the specified endpoint ID. + */ +__STATIC_INLINE uint32_t HSUSBD_GetEpStall(uint32_t u32Ep) +{ + return (HSUSBD->EP[u32Ep].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] u32EpNum USB endpoint + * @retval 0: USB endpoint is not stalled. + * @retval non-0: USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + */ +__STATIC_INLINE uint32_t HSUSBD_GetStall(uint32_t u32EpNum) +{ + uint32_t i; + uint32_t val = 0ul; + + for (i=0ul; iEP[i].EPCFG & 0xf0ul) >> 4) == u32EpNum) + { + val = (HSUSBD->EP[i].EPRSPCTL & HSUSBD_EP_RSPCTL_HALT); + break; + } + } + return val; +} + + +/*-------------------------------------------------------------------------------------------*/ +typedef void (*HSUSBD_VENDOR_REQ)(void); /*!CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + * \hideinitializer + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + * \hideinitializer + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + * \hideinitializer + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + * \hideinitializer + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + * \hideinitializer + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + * \hideinitializer + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 ) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + * \hideinitializer + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 ) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * \hideinitializer + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * \hideinitializer + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * \hideinitializer + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * \hideinitializer + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * \hideinitializer + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * \hideinitializer + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * \hideinitializer + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * \hideinitializer + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + * \hideinitializer + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C will send STOP after PDMA transfers done automatically. + * \hideinitializer + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + * \hideinitializer + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c) +{ + uint32_t u32TimeOutCount = I2C_TIMEOUT; + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + while(i2c->CTL0 & I2C_CTL0_STO_Msk) + { + if(--u32TimeOutCount == 0) break; + } +} + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_i2s.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_i2s.h new file mode 100644 index 0000000..3506af5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_i2s.h @@ -0,0 +1,354 @@ +/**************************************************************************//** + * @file i2s.h + * @version V3.00 + * @brief M460 series I2S driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __I2S_H__ +#define __I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ + +#define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_STEREO (0U) /*!< Stereo channel \hideinitializer */ +#define I2S_ENABLE_MONO I2S_MONO +#define I2S_DISABLE_MONO I2S_STEREO + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER (0U) /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */ +#define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */ + +/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0U) && (u32ChMask < 9U)) + { + i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); + + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2S_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_keystore.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_keystore.h new file mode 100644 index 0000000..7eebd54 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_keystore.h @@ -0,0 +1,138 @@ +/**************************************************************************//** + * @file keystore.h + * @version V3.00 + * @brief Key Store Driver Header + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KEYSTORE_H__ +#define __KEYSTORE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KS_Driver Key Store Driver + @{ +*/ + +/** @addtogroup KS_EXPORTED_CONSTANTS Key Store Exported Constants + @{ +*/ + +#define KS_TOMETAKEY(x) (((uint32_t)(x) << KS_METADATA_NUMBER_Pos) & KS_METADATA_NUMBER_Msk) +#define KS_TOKEYIDX(x) (((uint32_t)(x) & KS_METADATA_NUMBER_Msk) >> KS_METADATA_NUMBER_Pos) + +typedef enum KSMEM +{ + KS_SRAM = 0, /*!< Volatile Memory */ + KS_FLASH = 1, /*!< Non-volatile Memory */ + KS_OTP = 2 /*!< One-Time Programming Memory */ +} KS_MEM_Type; + +#define KS_OP_READ (0 << KS_CTL_OPMODE_Pos) +#define KS_OP_WRITE (1 << KS_CTL_OPMODE_Pos) +#define KS_OP_ERASE (2 << KS_CTL_OPMODE_Pos) +#define KS_OP_ERASE_ALL (3 << KS_CTL_OPMODE_Pos) +#define KS_OP_REVOKE (4 << KS_CTL_OPMODE_Pos) +#define KS_OP_REMAN (5 << KS_CTL_OPMODE_Pos) +#define KS_OP_LOCK (7 << KS_CTL_OPMODE_Pos) + +#define KS_OWNER_AES (0ul) +#define KS_OWNER_HMAC (1ul) +#define KS_OWNER_RSA_EXP (2ul) +#define KS_OWNER_RSA_MID (3ul) +#define KS_OWNER_ECC (4ul) +#define KS_OWNER_CPU (5ul) + +#define KS_META_AES (0ul << KS_METADATA_OWNER_Pos) /*!< AES Access Only */ +#define KS_META_HMAC (1ul << KS_METADATA_OWNER_Pos) /*!< HMAC Access Only */ +#define KS_META_RSA_EXP (2ul << KS_METADATA_OWNER_Pos) /*!< RSA_EXP Access Only */ +#define KS_META_RSA_MID (3ul << KS_METADATA_OWNER_Pos) /*!< RSA_MID Access Only */ +#define KS_META_ECC (4ul << KS_METADATA_OWNER_Pos) /*!< ECC Access Only */ +#define KS_META_CPU (5ul << KS_METADATA_OWNER_Pos) /*!< CPU Access Only */ + +#define KS_META_128 ( 0ul << KS_METADATA_SIZE_Pos) /*!< Key size 128 bits */ +#define KS_META_163 ( 1ul << KS_METADATA_SIZE_Pos) /*!< Key size 163 bits */ +#define KS_META_192 ( 2ul << KS_METADATA_SIZE_Pos) /*!< Key size 192 bits */ +#define KS_META_224 ( 3ul << KS_METADATA_SIZE_Pos) /*!< Key size 224 bits */ +#define KS_META_233 ( 4ul << KS_METADATA_SIZE_Pos) /*!< Key size 233 bits */ +#define KS_META_255 ( 5ul << KS_METADATA_SIZE_Pos) /*!< Key size 255 bits */ +#define KS_META_256 ( 6ul << KS_METADATA_SIZE_Pos) /*!< Key size 256 bits */ +#define KS_META_283 ( 7ul << KS_METADATA_SIZE_Pos) /*!< Key size 283 bits */ +#define KS_META_384 ( 8ul << KS_METADATA_SIZE_Pos) /*!< Key size 384 bits */ +#define KS_META_409 ( 9ul << KS_METADATA_SIZE_Pos) /*!< Key size 409 bits */ +#define KS_META_512 (10ul << KS_METADATA_SIZE_Pos) /*!< Key size 512 bits */ +#define KS_META_521 (11ul << KS_METADATA_SIZE_Pos) /*!< Key size 521 bits */ +#define KS_META_571 (12ul << KS_METADATA_SIZE_Pos) /*!< Key size 571 bits */ +#define KS_META_1024 (16ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_1536 (17ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_2048 (18ul << KS_METADATA_SIZE_Pos) /*!< Key size 2048 bits */ +#define KS_META_3072 (19ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_4096 (20ul << KS_METADATA_SIZE_Pos) /*!< Key size 4096 bits */ + +#define KS_META_BOOT ( 1ul << KS_METADATA_BS_Pos) /*!< Key only used for boot ROM only */ + +#define KS_META_READABLE (1ul << KS_METADATA_READABLE_Pos) /*!< Allow the key to be read by software */ + +#define KS_META_PRIV (1ul << KS_METADATA_PRIV_Pos) /*!< Privilege key */ +#define KS_META_NONPRIV (0ul << KS_METADATA_PRIV_Pos) /*!< Non-privilege key */ + +#define KS_META_SECURE (1ul << KS_METADATA_SEC_Pos) /*!< Secure key */ +#define KS_META_NONSECURE (0ul << KS_METADATA_SEC_Pos) /*!< Non-secure key */ + +#define KS_TIMEOUT SystemCoreClock /*!< 1 second time-out \hideinitializer */ +#define KS_TIMEOUT_ERR (-1L) /*!< KS operation abort due to timeout error \hideinitializer */ + +/** + * @brief Enable scramble function + * @details This function is used to enable scramle function of Key Store. + */ + +#define KS_SCRAMBLING() KS->CTL |= KS_CTL_SCMB_Msk + + + + +/**@}*/ /* end of group KS_EXPORTED_CONSTANTS */ + +extern int32_t g_KS_i32ErrCode; + +/** @addtogroup KS_EXPORTED_FUNCTIONS Key Store Exported Functions + @{ +*/ + +void KS_Open(void); +int32_t KS_Read(KS_MEM_Type type, int32_t i32KeyIdx, uint32_t au32Key[], uint32_t u32WordCnt); +int32_t KS_Write(KS_MEM_Type eType, uint32_t u32Meta, uint32_t au32Key[]); +int32_t KS_WriteOTP(int32_t i32KeyIdx, uint32_t u32Meta, uint32_t au32Key[]); +int32_t KS_EraseKey(int32_t i32KeyIdx); +int32_t KS_EraseOTPKey(int32_t i32KeyIdx); +int32_t KS_LockOTPKey(int32_t i32KeyIdx); +int32_t KS_EraseAll(KS_MEM_Type eType); +int32_t KS_RevokeKey(KS_MEM_Type eType, int32_t i32KeyIdx); +uint32_t KS_GetRemainSize(KS_MEM_Type eType); +int32_t KS_ToggleSRAM(void); +uint32_t KS_GetKeyWordCnt(uint32_t u32Meta); +uint32_t KS_GetRemainKeyCount(KS_MEM_Type mem); + +/**@}*/ /* end of group KS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group KS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __KEYSTORE_H__ */ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_kpi.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_kpi.h new file mode 100644 index 0000000..48798b7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_kpi.h @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file kpi.h + * @version V3.00 + * @brief Keypad interface driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KPI_H__ +#define __KPI_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KPI_Driver KPI Driver + @{ +*/ + +/** @addtogroup KPI_EXPORTED_CONSTANTS KPI Exported Constants + @{ +*/ + +#define KPI_MAX_ROW 6 +#define KPI_MAX_COL 8 +#define KPI_MAX_KEYS (KPI_MAX_ROW * KPI_MAX_COL) + +#define KPI_PRESS 0 +#define KPI_RELEASE 1 + +typedef struct { + uint8_t x; + uint8_t y; + uint16_t st; +} KPI_KEY_T; + +/**@}*/ /* end of group KPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup KPI_EXPORTED_FUNCTIONS KPI Exported Functions + @{ +*/ + +int32_t KPI_Open(uint32_t u32Rows, uint32_t u32Columns, KPI_KEY_T *pkeyQueue, uint32_t u32MaxKeyCnt); +void KPI_Close(void); +int32_t KPI_kbhit(void); +KPI_KEY_T KPI_GetKey(void); +void KPI_SetSampleTime(uint32_t ms); + +/**@}*/ /* end of group KPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group KPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __KPI_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_otg.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_otg.h new file mode 100644 index 0000000..5ff1b5e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_otg.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file otg.h + * @version V3.00 + * @brief M460 series OTG driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ****************************************************************************/ +#ifndef __OTG_H__ +#define __OTG_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OTG_Driver OTG Driver + @{ +*/ + + +/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* OTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */ +#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */ +#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */ +#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */ + + +/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable OTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function. + * \hideinitializer + */ +#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to disable OTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. + * \hideinitializer + */ +#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as OTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. + * \hideinitializer + */ +#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. + * \hideinitializer + */ +#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. + * \hideinitializer + */ +#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. + * \hideinitializer + */ +#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk) + +/** + * @brief This macro is used to enable OTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. + * \hideinitializer + */ +#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable OTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. + * \hideinitializer + */ +#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_EN_ACTIVE_HIGH + * - \ref OTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + * \hideinitializer + */ +#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol) << OTG_PHYCTL_VBENPOL_Pos)) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_ST pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_ST_VALID_HIGH + * - \ref OTG_VBUS_ST_VALID_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch status signal. + * \hideinitializer + */ +#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol) << OTG_PHYCTL_VBSTSPOL_Pos)) + +/** + * @brief This macro is used to enable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will enable OTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask)) + +/** + * @brief This macro is used to disable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable OTG related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) + +/** + * @brief This macro is used to get OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) + +/** + * @brief This macro is used to clear OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) + +/** + * @brief This macro is used to get OTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref OTG_STATUS_OVERCUR_Msk + * - \ref OTG_STATUS_IDSTS_Msk + * - \ref OTG_STATUS_SESSEND_Msk + * - \ref OTG_STATUS_BVLD_Msk + * - \ref OTG_STATUS_AVLD_Msk + * - \ref OTG_STATUS_VBUSVLD_Msk + * - \ref OTG_STATUS_ASPERI_Msk + * - \ref OTG_STATUS_ASHOST_Msk + * @return The user specified status. + * @details This macro will return OTG related status specified by u32Mask parameter. + * \hideinitializer + */ +#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) + + + +/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__OTG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_pdma.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_pdma.h new file mode 100644 index 0000000..aa941a1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_pdma.h @@ -0,0 +1,446 @@ +/**************************************************************************//** + * @file pdma.h + * @version V1.00 + * @brief PDMA driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 16UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask))) + +/** + * @brief Get Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN)) + +/** + * @brief Clear Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + * \hideinitializer + */ +#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + * \hideinitializer + */ +#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + * \hideinitializer + */ +#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + * \hideinitializer + */ +#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + * \hideinitializer + */ +#define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + */ +#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Reset the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro reset the selected channel. + */ +#define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PDMA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_Close(PDMA_T * pdma); +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T * pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); +void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount); + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDMA_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_psio.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_psio.h new file mode 100644 index 0000000..4024f9d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_psio.h @@ -0,0 +1,1191 @@ +/**************************************************************************//** + * @file psio.h + * @version V3.00 + * @brief M460 series PSIO driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + + +#ifndef __PSIO_H__ +#define __PSIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PSIO_Driver PSIO Driver + @{ +*/ + +/** @addtogroup PSIO_EXPORTED_CONSTANTS PSIO Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PSIO_SC0 0x00000000UL /*!INTEN |= (u32IntSel)) + +/** + * @brief Disable specified PSIO interrupt + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32IntSel Interrupt type select + * - \ref PSIO_INTEN_CON0IE_Msk + * - \ref PSIO_INTEN_CON1IE_Msk + * - \ref PSIO_INTEN_MISMATIE_Msk + * - \ref PSIO_INTEN_TERRIE_Msk + * - \ref PSIO_INTEN_SC0IE_Msk + * - \ref PSIO_INTEN_SC1IE_Msk + * - \ref PSIO_INTEN_SC2IE_Msk + * - \ref PSIO_INTEN_SC3IE_Msk + * + * @return None + * + * @details This macro disable specified PSIO interrupt. + * \hideinitializer + */ +#define PSIO_DISABLE_INT(psio, u32IntSel) ((psio)->INTEN &= ~(u32IntSel)) + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32IntTypeFlag Interrupt Type Flag, Valid values are + * - \ref PSIO_INTSTS_CON0IF_Msk + * - \ref PSIO_INTSTS_CON1IF_Msk + * - \ref PSIO_INTSTS_MISMATIF_Msk + * - \ref PSIO_INTSTS_TERRIF_Msk + * - \ref PSIO_INTSTS_SC0IF_Msk + * - \ref PSIO_INTSTS_SC1IF_Msk + * - \ref PSIO_INTSTS_SC2IF_Msk + * - \ref PSIO_INTSTS_SC3IF_Msk + * + * @return 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define PSIO_GET_INT_FLAG(psio, u32IntTypeFlag) (((psio)->INTSTS & (u32IntTypeFlag))?1:0) + +/** + * @brief Clear specified interrupt flag/status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32IntTypeFlag Interrupt Type Flag, Valid values are + * - \ref PSIO_INTSTS_CON0IF_Msk + * - \ref PSIO_INTSTS_CON1IF_Msk + * - \ref PSIO_INTSTS_MISMATIF_Msk + * - \ref PSIO_INTSTS_TERRIF_Msk + * - \ref PSIO_INTSTS_SC0IF_Msk + * - \ref PSIO_INTSTS_SC1IF_Msk + * - \ref PSIO_INTSTS_SC2IF_Msk + * - \ref PSIO_INTSTS_SC3IF_Msk + * + * @return None + * + * @details This macro clear specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define PSIO_CLEAR_INT_FLAG(psio, u32IntTypeFlag) ((psio)->INTSTS = u32IntTypeFlag) + +/** + * @brief Get specified transfer status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer status, Valid values are + * - \ref PSIO_TRANSTS_INFULL0_Msk + * - \ref PSIO_TRANSTS_INOVER0_Msk + * - \ref PSIO_TRANSTS_OUTEPY0_Msk + * - \ref PSIO_TRANSTS_OUTUF0_Msk + * - \ref PSIO_TRANSTS_INFULL1_Msk + * - \ref PSIO_TRANSTS_INOVER1_Msk + * - \ref PSIO_TRANSTS_OUTEPY1_Msk + * - \ref PSIO_TRANSTS_OUTUF1_Msk + * - \ref PSIO_TRANSTS_INFULL2_Msk + * - \ref PSIO_TRANSTS_INOVER2_Msk + * - \ref PSIO_TRANSTS_OUTEPY2_Msk + * - \ref PSIO_TRANSTS_OUTUF2_Msk + * - \ref PSIO_TRANSTS_INFULL3_Msk + * - \ref PSIO_TRANSTS_INOVER3_Msk + * - \ref PSIO_TRANSTS_OUTEPY3_Msk + * - \ref PSIO_TRANSTS_OUTUF3_Msk + * - \ref PSIO_TRANSTS_INFULL4_Msk + * - \ref PSIO_TRANSTS_INOVER4_Msk + * - \ref PSIO_TRANSTS_OUTEPY4_Msk + * - \ref PSIO_TRANSTS_OUTUF4_Msk + * - \ref PSIO_TRANSTS_INFULL5_Msk + * - \ref PSIO_TRANSTS_INOVER5_Msk + * - \ref PSIO_TRANSTS_OUTEPY5_Msk + * - \ref PSIO_TRANSTS_OUTUF5_Msk + * - \ref PSIO_TRANSTS_INFULL6_Msk + * - \ref PSIO_TRANSTS_INOVER6_Msk + * - \ref PSIO_TRANSTS_OUTEPY6_Msk + * - \ref PSIO_TRANSTS_OUTUF6_Msk + * - \ref PSIO_TRANSTS_INFULL7_Msk + * - \ref PSIO_TRANSTS_INOVER7_Msk + * - \ref PSIO_TRANSTS_OUTEPY7_Msk + * - \ref PSIO_TRANSTS_OUTUF7_Msk + * + * @return 0 The specified status is not happened. + * 1 The specified status is happened. + * + * @details This macro get specified transfer status. + * \hideinitializer + */ +#define PSIO_GET_TRANSFER_STATUS(psio, u32Status) (((psio)->TRANSTS & (u32Status))?1:0) + +/** + * @brief Clear specified transfer status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer status, Valid values are + * - \ref PSIO_TRANSTS_INOVER0_Msk + * - \ref PSIO_TRANSTS_OUTUF0_Msk + * - \ref PSIO_TRANSTS_INOVER1_Msk + * - \ref PSIO_TRANSTS_OUTUF1_Msk + * - \ref PSIO_TRANSTS_INOVER2_Msk + * - \ref PSIO_TRANSTS_OUTUF2_Msk + * - \ref PSIO_TRANSTS_INOVER3_Msk + * - \ref PSIO_TRANSTS_OUTUF3_Msk + * - \ref PSIO_TRANSTS_INOVER4_Msk + * - \ref PSIO_TRANSTS_OUTUF4_Msk + * - \ref PSIO_TRANSTS_INOVER5_Msk + * - \ref PSIO_TRANSTS_OUTUF5_Msk + * - \ref PSIO_TRANSTS_INOVER6_Msk + * - \ref PSIO_TRANSTS_OUTUF6_Msk + * - \ref PSIO_TRANSTS_INOVER7_Msk + * - \ref PSIO_TRANSTS_OUTUF7_Msk + * + * @return None + * + * @details This macro clear specified transfer status. + * \hideinitializer + */ +#define PSIO_CLEAR_TRANSFER_STATUS(psio, u32Status) ((psio)->TRANSTS = u32Status) + +/** + * @brief Get specified input status state + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer input status state, Valid values are + * - \ref PSIO_ISSTS_VALID0_Msk + * - \ref PSIO_ISSTS_INSTSOV0_Msk + * - \ref PSIO_ISSTS_VALID1_Msk + * - \ref PSIO_ISSTS_INSTSOV1_Msk + * - \ref PSIO_ISSTS_VALID2_Msk + * - \ref PSIO_ISSTS_INSTSOV2_Msk + * - \ref PSIO_ISSTS_VALID3_Msk + * - \ref PSIO_ISSTS_INSTSOV3_Msk + * - \ref PSIO_ISSTS_VALID4_Msk + * - \ref PSIO_ISSTS_INSTSOV4_Msk + * - \ref PSIO_ISSTS_VALID5_Msk + * - \ref PSIO_ISSTS_INSTSOV5_Msk + * - \ref PSIO_ISSTS_VALID6_Msk + * - \ref PSIO_ISSTS_INSTSOV6_Msk + * - \ref PSIO_ISSTS_VALID7_Msk + * - \ref PSIO_ISSTS_INSTSOV7_Msk + * + * @return 0 The specified status is not happened. + * 1 The specified status is happened. + * + * @details This macro get input status state. + * \hideinitializer + */ +#define PSIO_GET_INPUT_STATUS_STATE(psio, u32Status) (((psio)->ISSTS & (u32Status))?1:0) + +/** + * @brief Clear specified input status state + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer input status state, Valid values are + * - \ref PSIO_ISSTS_INSTSOV0_Msk + * - \ref PSIO_ISSTS_INSTSOV1_Msk + * - \ref PSIO_ISSTS_INSTSOV2_Msk + * - \ref PSIO_ISSTS_INSTSOV3_Msk + * - \ref PSIO_ISSTS_INSTSOV4_Msk + * - \ref PSIO_ISSTS_INSTSOV5_Msk + * - \ref PSIO_ISSTS_INSTSOV6_Msk + * - \ref PSIO_ISSTS_INSTSOV7_Msk + * + * @return None + * + * @details This macro clear input status state. + * \hideinitializer + */ +#define PSIO_CLEAR_INPUT_STATUS_STATE(psio, u32Status) ((psio)->ISSTS = u32Status) + +/** + * @brief Set PSIO PDMA control input + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32InPin The selected input pin + * - \ref PSIO_PDMACTL_IPIN0EN_Msk + * - \ref PSIO_PDMACTL_IPIN1EN_Msk + * - \ref PSIO_PDMACTL_IPIN2EN_Msk + * - \ref PSIO_PDMACTL_IPIN3EN_Msk + * - \ref PSIO_PDMACTL_IPIN4EN_Msk + * - \ref PSIO_PDMACTL_IPIN5EN_Msk + * - \ref PSIO_PDMACTL_IPIN6EN_Msk + * - \ref PSIO_PDMACTL_IPIN7EN_Msk + * + * @return None + * + * @details This macro set PSIO input with PDMA. + * \hideinitializer + */ +#define PSIO_SET_PDMA_INPUT(psio, u32SC, u32InPin) ((psio)->PDMACTL = ((psio)->PDMACTL & ~PSIO_PDMACTL_INSCSEL_Msk) \ + |((u32SC)<PDMACTL = (psio)->PDMACTL & ~PSIO_PDMACTL_INSCSEL_Msk & ~(u32InPin)) + +/** + * @brief Set PSIO PDMA control output + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32OutPin The selected output pin + * - \ref PSIO_PDMACTL_OPIN0EN_Msk + * - \ref PSIO_PDMACTL_OPIN1EN_Msk + * - \ref PSIO_PDMACTL_OPIN2EN_Msk + * - \ref PSIO_PDMACTL_OPIN3EN_Msk + * - \ref PSIO_PDMACTL_OPIN4EN_Msk + * - \ref PSIO_PDMACTL_OPIN5EN_Msk + * - \ref PSIO_PDMACTL_OPIN6EN_Msk + * - \ref PSIO_PDMACTL_OPIN7EN_Msk + * + * @return None + * + * @details This macro set PSIO output with PDMA. + * \hideinitializer + */ +#define PSIO_SET_PDMA_OUTPUT(psio, u32SC, u32OutPin) ((psio)->PDMACTL = ((psio)->PDMACTL & ~PSIO_PDMACTL_OUTSCSEL_Msk) \ + |((u32SC)<PDMACTL = (psio)->PDMACTL & ~PSIO_PDMACTL_OUTSCSEL_Msk & ~(u32OutPin)) + +/** + * @brief Set slot controller trigger source + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32SrcType The selected trigger source type + * - \ref PSIO_SW_TRIGGER + * - \ref PSIO_FALLING_TRIGGER + * - \ref PSIO_RISING_TRIGGER + * - \ref PSIO_BOTH_EDGE_TRIGGER + * + * @return None + * + * @details This macro set slot controller trigger source. + * \hideinitializer + */ +#define PSIO_SET_TRIGSRC(psio, u32SC, u32SrcType) ((psio)->SCCT[(u32SC)].SCCTL=((psio)->SCCT[(u32SC)].SCCTL & ~PSIO_SCCT_SCCTL_TRIGSRC_Msk)|(u32SrcType)) + +/** + * @brief Start PSIO slot controller + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return None + * + * @details This macro start PSIO slot controller. + * \hideinitializer + */ +#define PSIO_START_SC(psio, u32SC) ((psio)->SCCT[(u32SC)].SCCTL |= PSIO_SCCT_SCCTL_START_Msk) + +/** + * @brief Stop PSIO slot controller + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return None + * + * @details This macro stop PSIO slot controller. + * \hideinitializer + */ +#define PSIO_STOP_SC(psio, u32SC) ((psio)->SCCT[(u32SC)].SCCTL |= PSIO_SCCT_SCCTL_STOP_Msk) + +/** + * @brief Get PSIO busy flag + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return 0 The busy flag is not happened. + * 1 The busy flag is happened. + * + * @details This macro get PSIO busy flag. + * \hideinitializer + */ +#define PSIO_GET_BUSY_FLAG(psio, u32SC) (((psio)->SCCT[(u32SC)].SCCTL & PSIO_SCCT_SCCTL_BUSY_Msk)?1:0) + +/** + * @brief Get PSIO idle flag + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return 0 The idle flag is not happened. + * 1 The idle flag is happened. + * + * @details This macro get PSIO idle flag. + * \hideinitializer + */ +#define PSIO_GET_IDLE_FLAG(psio, u32SC) (((psio)->SCCT[(u32SC)].SCCTL & PSIO_SCCT_SCCTL_IDLE_Msk)?1:0) + +/** +* @brief Clear PSIO idle flag +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32SC The selected slot controller. Valid values are +* - \ref PSIO_SC0 +* - \ref PSIO_SC1 +* - \ref PSIO_SC2 +* - \ref PSIO_SC3 +* +* @return None +* +* @details This macro clear PSIO idle flag. +* \hideinitializer +*/ +#define PSIO_SET_IDLE_FLAG(psio, u32SC) ((psio)->SCCT[(u32SC)].SCCTL |= PSIO_SCCT_SCCTL_IDLE_Msk) + +/** +* @brief Set PSIO slot tick count +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32SC The selected slot controller. Valid values are +* - \ref PSIO_SC0 +* - \ref PSIO_SC1 +* - \ref PSIO_SC2 +* - \ref PSIO_SC3 +* @param[in] u32Slot The selected slot. Valid values are +* - \ref PSIO_SLOT0 +* - \ref PSIO_SLOT1 +* - \ref PSIO_SLOT2 +* - \ref PSIO_SLOT3 +* - \ref PSIO_SLOT4 +* - \ref PSIO_SLOT5 +* - \ref PSIO_SLOT6 +* - \ref PSIO_SLOT7 +* @param[in] u32Cnt The slot tick count. Valid values are 0x0~0xF +* +* @return None +* +* @details This macro set PSIO slot tick count. +* \hideinitializer +*/ +#define PSIO_SCSLOT_SET_SLOT(psio, u32SC, u32Slot, u32Cnt) ((psio)->SCCT[(u32SC)].SCSLOT= \ + ((psio)->SCCT[(u32SC)].SCSLOT & ~(PSIO_SCCT_SCSLOT_SLOT0CNT_Msk<<((u32Slot-1)*PSIO_SCCT_SCSLOT_SLOT1CNT_Pos)))|((u32Cnt&0xF)<<((u32Slot-1)*PSIO_SCCT_SCSLOT_SLOT1CNT_Pos))) + +/** + * @brief Set PSIO all slot tick count + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32Cnt The slot tick count. Valid values are 0x0~0xF + * + * @return None + * + * @details This macro set PSIO all slot tick count. + * \hideinitializer + */ +#define PSIO_SCSLOT_SET_ALL_SLOT(psio, u32SC, u32Cnt) ((psio)->SCCT[(u32SC)].SCSLOT= \ + ((u32Cnt&0xF)<GNCT[(u32Pin)].GENCTL = \ + ((psio)->GNCT[(u32Pin)].GENCTL & ~PSIO_GNCT_GENCTL_PINEN_Msk)|PSIO_GNCT_GENCTL_PINEN_Msk) + +/** + * @brief Disable Pin function + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * + * @return None + * + * @details This function is used to disable this Pin. + * \hideinitializer + */ +#define PSIO_DISABLE_PIN(psio, u32Pin) ((psio)->GNCT[(u32Pin)].GENCTL = \ + ((psio)->GNCT[(u32Pin)].GENCTL & ~PSIO_GNCT_GENCTL_PINEN_Msk)) + +/** + * @brief Set specified pin data width + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32InWidth The input data width. Valid values are 0~32 + * @param[in] u32OutWidth The output data width. Valid values are 0~32 + * + * @return None + * + * @details This macro set in/out data width. + * \hideinitializer + */ +#define PSIO_SET_WIDTH(psio, u32Pin, u32InWidth, u32OutWidth) (((psio)->GNCT[(u32Pin)].DATCTL)= \ + ((psio)->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_INDATWD_Msk & ~PSIO_GNCT_DATCTL_OUTDATWD_Msk) \ + |((u32InWidth==0?0:(u32InWidth-1))<GNCT[(u32Pin)].DATCTL)= \ + (PSIO->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_ORDER_Msk)|(u32Order)) + +/** + * @brief Set specified pin output data depth + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32Depth The data depth. Valid values are + * - \ref PSIO_DEPTH1 + * - \ref PSIO_DEPTH2 + * - \ref PSIO_DEPTH3 + * - \ref PSIO_DEPTH4 + * + * @return None + * + * @details This macro set output data order. + * \hideinitializer + */ +#define PSIO_SET_OUTPUT_DEPTH(psio, u32Pin, u32Depth) ((psio)->GNCT[(u32Pin)].DATCTL= \ + (PSIO->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_OUTDEPTH_Msk)|((u32Depth)<GNCT[(u32Pin)].DATCTL= \ + (PSIO->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_INDEPTH_Msk)|((u32Depth)<GNCT[u32Pin].INSTS&0xFF) + +/** + * @brief Get specified pin input data + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * + * @return The specified pin input data + * + * @details This macro get specified pin input data. + * \hideinitializer + */ +#define PSIO_GET_INPUT_DATA(psio, u32Pin) (psio->GNCT[u32Pin].INDAT) + +/** +* @brief Set specified pin output data +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32Pin The selected Pin. Valid values are +* - \ref PSIO_PIN0 +* - \ref PSIO_PIN1 +* - \ref PSIO_PIN2 +* - \ref PSIO_PIN3 +* - \ref PSIO_PIN4 +* - \ref PSIO_PIN5 +* - \ref PSIO_PIN6 +* - \ref PSIO_PIN7 +* @param[in] u32Data The output data +* +* @return None +* +* @details This macro set specified pin output data. +* \hideinitializer +*/ +#define PSIO_SET_OUTPUT_DATA(psio, u32Pin, u32Data) (psio->GNCT[u32Pin].OUTDAT = (u32Data)) + +/** +* @brief Set specified pin check point and slot link +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32Pin The selected Pin. Valid values are +* - \ref PSIO_PIN0 +* - \ref PSIO_PIN1 +* - \ref PSIO_PIN2 +* - \ref PSIO_PIN3 +* - \ref PSIO_PIN4 +* - \ref PSIO_PIN5 +* - \ref PSIO_PIN6 +* - \ref PSIO_PIN7 +* @param[in] u32CheckPoint The selected check point. Valid values are +* - \ref PSIO_CP0 +* - \ref PSIO_CP1 +* - \ref PSIO_CP2 +* - \ref PSIO_CP3 +* - \ref PSIO_CP4 +* - \ref PSIO_CP5 +* - \ref PSIO_CP6 +* - \ref PSIO_CP7 +* @param[in] u32Slot The selected slot. Valid values are +* - \ref PSIO_SLOT0 +* - \ref PSIO_SLOT1 +* - \ref PSIO_SLOT2 +* - \ref PSIO_SLOT3 +* - \ref PSIO_SLOT4 +* - \ref PSIO_SLOT5 +* - \ref PSIO_SLOT6 +* - \ref PSIO_SLOT7 +* +* @return None +* +* @details This macro used to link check point and slot. +* \hideinitializer +*/ +#define PSIO_SET_CHECKPOINT(psio, u32Pin, u32CheckPoint, u32Slot) (psio->GNCT[(u32Pin)].CPCTL0= \ + (psio->GNCT[(u32Pin)].CPCTL0 & ~(PSIO_GNCT_CPCTL0_CKPT0_Msk<<((u32CheckPoint)*PSIO_GNCT_CPCTL0_CKPT1_Pos))) \ + |((u32Slot)<<((u32CheckPoint)*PSIO_GNCT_CPCTL0_CKPT1_Pos))) + +/** + * @brief Clear specified pin check point and slot link + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32CheckPoint The selected check point. Valid values are + * - \ref PSIO_CP0 + * - \ref PSIO_CP1 + * - \ref PSIO_CP2 + * - \ref PSIO_CP3 + * - \ref PSIO_CP4 + * - \ref PSIO_CP5 + * - \ref PSIO_CP6 + * - \ref PSIO_CP7 + * + * @return None + * + * @details This macro used to clear the link of check point and slot. + * \hideinitializer + */ +#define PSIO_CLEAR_CHECKPOINT(psio, u32Pin, u32CheckPoint) (psio->GNCT[(u32Pin)].CPCTL0= \ + psio->GNCT[(u32Pin)].CPCTL0 & ~(PSIO_GNCT_CPCTL0_CKPT0_Msk<<((u32CheckPoint)*PSIO_GNCT_CPCTL0_CKPT1_Pos))) + +/** + * @brief Set specified pin action of check point + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32CheckPoint The selected check point. Valid values are + * - \ref PSIO_CP0 + * - \ref PSIO_CP1 + * - \ref PSIO_CP2 + * - \ref PSIO_CP3 + * - \ref PSIO_CP4 + * - \ref PSIO_CP5 + * - \ref PSIO_CP6 + * - \ref PSIO_CP7 + * @param[in] u32Action The selected action. Valid values are + * - \ref PSIO_OUT_LOW + * - \ref PSIO_OUT_HIGH + * - \ref PSIO_OUT_BUFFER + * - \ref PSIO_OUT_TOGGLE + * - \ref PSIO_IN_BUFFER + * - \ref PSIO_IN_STATUS + * - \ref PSIO_IN_STATUS_UPDATE + * + * @return None + * + * @details This macro used to set specified pin action of check point. + * \hideinitializer + */ +#define PSIO_SET_ACTION(psio, u32Pin, u32CheckPoint, u32Action) (psio->GNCT[(u32Pin)].CPCTL1= \ + (psio->GNCT[(u32Pin)].CPCTL1 & ~(PSIO_GNCT_CPCTL1_CKPT0ACT_Msk<<((u32CheckPoint)*PSIO_GNCT_CPCTL1_CKPT1ACT_Pos))) \ + |((u32Action)<<((u32CheckPoint)*PSIO_GNCT_CPCTL1_CKPT1ACT_Pos))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Set interrupt control + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller + * @param[in] u32Int The interrupt type. Valid values are + * - \ref PSIO_INT0 + * - \ref PSIO_INT1 + * @param[in] u32Slot The selected slot. Valid values are + * - \ref PSIO_SLOT0 + * - \ref PSIO_SLOT1 + * - \ref PSIO_SLOT2 + * - \ref PSIO_SLOT3 + * - \ref PSIO_SLOT4 + * - \ref PSIO_SLOT5 + * - \ref PSIO_SLOT6 + * - \ref PSIO_SLOT7 + * + * @return None + * + * @details This function is used to set the selected slot controller, interrupt type and slot. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SET_INTCTL(PSIO_T *psio, uint32_t u32SC, uint32_t u32Int, uint32_t u32Slot) +{ + if (u32Int == PSIO_INT0) + { + (psio)->INTCTL = (((psio)->INTCTL & ~PSIO_INTCTL_CONI0SS_Msk & ~PSIO_INTCTL_CONI0SCS_Msk) + | ((u32SC) << PSIO_INTCTL_CONI0SCS_Pos) + | ((u32Slot) << PSIO_INTCTL_CONI0SS_Pos)); + } + else if (u32Int == PSIO_INT1) + { + (psio)->INTCTL = (((psio)->INTCTL & ~PSIO_INTCTL_CONI1SS_Msk & ~PSIO_INTCTL_CONI1SCS_Msk) + | ((u32SC) << PSIO_INTCTL_CONI1SCS_Pos) + | ((u32Slot) << PSIO_INTCTL_CONI1SS_Pos)); + } +} + +/** + * @brief Clear interrupt control setting + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Int The interrupt type. Valid values are + * - \ref PSIO_INT0 + * - \ref PSIO_INT1 + * + * @return None + * + * @details This function is used to clear the selected slot controller, interrupt type and slot. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_CLEAR_INTCTL(PSIO_T *psio, uint32_t u32Int) +{ + if (u32Int == PSIO_INT0) + { + (psio)->INTCTL = ((psio)->INTCTL & ~PSIO_INTCTL_CONI0SS_Msk & ~PSIO_INTCTL_CONI0SCS_Msk); + } + else if (u32Int == PSIO_INT1) + { + (psio)->INTCTL = ((psio)->INTCTL & ~PSIO_INTCTL_CONI1SS_Msk & ~PSIO_INTCTL_CONI1SCS_Msk); + } +} + +/** + * @brief Set Slot controller control + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller + * @param[in] u32InitSlot The selected initial slot of the repeat period. Valid values are + * - \ref PSIO_SLOT0 + * - \ref PSIO_SLOT1 + * - \ref PSIO_SLOT2 + * - \ref PSIO_SLOT3 + * - \ref PSIO_SLOT4 + * - \ref PSIO_SLOT5 + * - \ref PSIO_SLOT6 + * - \ref PSIO_SLOT7 + * @param[in] u32EndSlot The selected end slot of the repeat period. Valid values are + * - \ref PSIO_SLOT0 + * - \ref PSIO_SLOT1 + * - \ref PSIO_SLOT2 + * - \ref PSIO_SLOT3 + * - \ref PSIO_SLOT4 + * - \ref PSIO_SLOT5 + * - \ref PSIO_SLOT6 + * - \ref PSIO_SLOT7 + * @param[in] u32LoopCnt The slot period loop count. Valid values are + * - 0x0 : Disable + * - 0x1~0x3E : Repeat slot 0x2~0x3F times + * - 0x3F : Loop until stop PSIO slot controller + * @param[in] u32Repeat Repeat mode Enable/Disable. Valid values are + * - \ref PSIO_REPEAT_ENABLE + * - \ref PSIO_REPEAT_DISABLE + * + * @return None + * + * @details This function is used to set the slot controller loop and repeat configuration. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SET_SCCTL(PSIO_T *psio, uint32_t u32SC, uint32_t u32InitSlot, uint32_t u32EndSlot, uint32_t u32LoopCnt, uint32_t u32Repeat) +{ + (psio)->SCCT[u32SC].SCCTL = ((psio)->SCCT[u32SC].SCCTL & ~PSIO_SCCT_SCCTL_INISLOT_Msk & ~PSIO_SCCT_SCCTL_ENDSLOT_Msk & ~PSIO_SCCT_SCCTL_SPLCNT_Msk) + | ((u32InitSlot) << PSIO_SCCT_SCCTL_INISLOT_Pos) + | ((u32EndSlot) << PSIO_SCCT_SCCTL_ENDSLOT_Pos) + | ((u32LoopCnt & 0x3F) << PSIO_SCCT_SCCTL_SPLCNT_Pos); + + if (u32Repeat == PSIO_REPEAT_ENABLE) + (psio)->SCCT[u32SC].SCCTL |= PSIO_SCCT_SCCTL_REPEAT_Msk; + else if (u32Repeat == PSIO_REPEAT_DISABLE) + (psio)->SCCT[u32SC].SCCTL &= ~PSIO_SCCT_SCCTL_REPEAT_Msk; +} + +/** + * @brief Set Pin general control + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32PinEn The selected Pin enable/disable. Valid values are + * - \ref PSIO_PIN_ENABLE + * - \ref PSIO_PIN_DISABLE + * @param[in] u32SC The selected slot controller for check point. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32IOMode The pin I/O mode. Valid values are + * - \ref PSIO_INPUT_MODE + * - \ref PSIO_OUTPUT_MODE + * - \ref PSIO_OPENDRAIN_MODE + * - \ref PSIO_QUASI_MODE + * @param[in] u32PinInit The pin initial status. Valid values are + * - \ref PSIO_LOW_LEVEL + * - \ref PSIO_HIGH_LEVEL + * - \ref PSIO_LAST_OUTPUT + * - \ref PSIO_Toggle + * @param[in] u32PinInterval The pin interval status. Valid values are + * - \ref PSIO_LOW_LEVEL + * - \ref PSIO_HIGH_LEVEL + * - \ref PSIO_LAST_OUTPUT + * - \ref PSIO_Toggle + * + * @return None + * + * @details This function is used to set the general control. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SET_GENCTL(PSIO_T *psio, uint32_t u32Pin, uint32_t u32PinEn, uint32_t u32SC, uint32_t u32IOMode, uint32_t u32PinInit, uint32_t u32PinInterval) +{ + (psio)->GNCT[u32Pin].GENCTL = ((psio)->GNCT[u32Pin].GENCTL & ~PSIO_GNCT_GENCTL_SCSEL_Msk & ~PSIO_GNCT_GENCTL_IOMODE_Msk + & ~PSIO_GNCT_GENCTL_INITIAL_Msk & ~PSIO_GNCT_GENCTL_INTERVAL_Msk) + | ((u32SC) << PSIO_GNCT_GENCTL_SCSEL_Pos) | ((u32IOMode) << PSIO_GNCT_GENCTL_IOMODE_Pos) + | ((u32PinInit) << PSIO_GNCT_GENCTL_INITIAL_Pos) | ((u32PinInterval) << PSIO_GNCT_GENCTL_INTERVAL_Pos); + + if (u32PinEn == PSIO_PIN_ENABLE) + (psio)->GNCT[u32Pin].GENCTL |= PSIO_GNCT_GENCTL_PINEN_Msk; + else if (u32PinEn == PSIO_PIN_DISABLE) + (psio)->GNCT[u32Pin].GENCTL &= ~PSIO_GNCT_GENCTL_PINEN_Msk; +} + +/** + * @brief Set Pin mode switch + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32SwPoint The switch point. Valid values are + * - \ref PSIO_SWITCH_P0 + * - \ref PSIO_SWITCH_P1 + * @param[in] u32SwMode The switch mode. Valid values are + * - \ref PSIO_INPUT_MODE + * - \ref PSIO_OUTPUT_MODE + * - \ref PSIO_OPENDRAIN_MODE + * - \ref PSIO_QUASI_MODE + * @param[in] u32SwCP The switch I/O mode at which point. Valid values are + * - \ref PSIO_CP0 + * - \ref PSIO_CP1 + * - \ref PSIO_CP2 + * - \ref PSIO_CP3 + * - \ref PSIO_CP4 + * - \ref PSIO_CP5 + * - \ref PSIO_CP6 + * - \ref PSIO_CP7 + * @return None + * + * @details This function is used to set the pin mode switch. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SWITCH_MODE(PSIO_T *psio, uint32_t u32Pin, uint32_t u32SwPoint, uint32_t u32SwMode, uint32_t u32SwCP) +{ + if (u32SwPoint == PSIO_SWITCH_P0) + { + (psio)->GNCT[u32Pin].GENCTL = ((psio)->GNCT[u32Pin].GENCTL & ~PSIO_GNCT_GENCTL_MODESW0_Msk & ~PSIO_GNCT_GENCTL_SW0CP_Msk) + | ((u32SwMode) << PSIO_GNCT_GENCTL_MODESW0_Pos) | ((u32SwCP + 1) << PSIO_GNCT_GENCTL_SW0CP_Pos); + } + else if (u32SwPoint == PSIO_SWITCH_P1) + { + (psio)->GNCT[u32Pin].GENCTL = ((psio)->GNCT[u32Pin].GENCTL & ~PSIO_GNCT_GENCTL_MODESW1_Msk & ~PSIO_GNCT_GENCTL_SW1CP_Msk) + | ((u32SwMode) << PSIO_GNCT_GENCTL_MODESW1_Pos) | ((u32SwCP + 1) << PSIO_GNCT_GENCTL_SW1CP_Pos); + } +} + +/** +* @brief Set specified pin check point and slot link, and pin action of check point +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32Pin The selected Pin. Valid values are +* - \ref PSIO_PIN0 +* - \ref PSIO_PIN1 +* - \ref PSIO_PIN2 +* - \ref PSIO_PIN3 +* - \ref PSIO_PIN4 +* - \ref PSIO_PIN5 +* - \ref PSIO_PIN6 +* - \ref PSIO_PIN7 +* @param[in] sConfig The selected check point configurations. +* +* @return None +* +* @details This macro used to link check point and slot, and set pin action of check point. +* \hideinitializer +*/ +__STATIC_INLINE void PSIO_SET_CP_CONFIG(PSIO_T *psio, uint32_t u32Pin, const S_PSIO_CP_CONFIG *sConfig) +{ + psio->GNCT[u32Pin].CPCTL0 = *(uint32_t *)sConfig; + psio->GNCT[u32Pin].CPCTL1 = *((uint32_t *)sConfig + 1); +} + +/*@}*/ /* end of group PSIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PSIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PSIO_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_qspi.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_qspi.h new file mode 100644 index 0000000..cb7d2c7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_qspi.h @@ -0,0 +1,437 @@ +/**************************************************************************//** + * @file qspi.h + * @version V3.00 + * @brief M460 series QSPI driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QSPI_H__ +#define __QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define QSPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define QSPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define QSPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define QSPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define QSPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define QSPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define QSPI_SLVTO_INT_MASK (0x020U) /*!< Slave mode time-out interrupt mask \hideinitializer */ +#define QSPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define QSPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define QSPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define QSPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define QSPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define QSPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define QSPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */ +#define QSPI_SSLINE_STS_MASK (0x80U) /*!< QSPIx_SS line status mask \hideinitializer */ + +/* QSPI Status2 Mask */ +#define QSPI_SLVBENUM_MASK (0x01U) /*!< Effective bit number of uncompleted RX data status mask \hideinitializer */ + +/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + * \hideinitializer + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ( (qspi)->STATUS = QSPI_STATUS_UNITIF_Msk ) + +/** + * @brief Disable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode. + * \hideinitializer + */ +#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode. + * \hideinitializer + */ +#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Disable Dual I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DUALIOEN bit of QSPI_CTL register to disable Dual I/O mode. + * \hideinitializer + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable Quad I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QUADIOEN bit of QSPI_CTL register to disable Quad I/O mode. + * \hideinitializer + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Disable TX DTR mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXDTREN bit of QSPI_CTL register to disable TX DTR mode. + * \hideinitializer + */ +#define QSPI_DISABLE_TXDTR_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TXDTREN_Msk ) + +/** + * @brief Enable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode. + * \hideinitializer + */ +#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode. + * \hideinitializer + */ +#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Dual input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set DUALIOEN bit of QSPI_CTL register to enable Dual input mode. + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and DUALIOEN bit of QSPI_CTL register to enable Dual output mode. + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk) ) + +/** + * @brief Enable Quad input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set QUADIOEN bit of QSPI_CTL register to enable Quad input mode. + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Enable Quad output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and QUADIOEN bit of QSPI_CTL register to enable Quad output mode. + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk) ) + +/** + * @brief Enable TX DTR mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXDTREN bit of QSPI_CTL register to enable TX DTR mode. + * \hideinitializer + */ +#define QSPI_ENABLE_TXDTR_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TXDTREN_Msk ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk) >> QSPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk) >> QSPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk) >> QSPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + * \hideinitializer + */ +#define QSPI_READ_RX(qspi) ( (qspi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + * \hideinitializer + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ( (qspi)->TX = (u32TxData) ) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + * \hideinitializer + */ +#define QSPI_SET_SS_HIGH(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk) ) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + * \hideinitializer + */ +#define QSPI_SET_SS_LOW(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + * \hideinitializer + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ( (qspi)->CTL |= QSPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ( (qspi)->CTL &= ~QSPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + * \hideinitializer + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + * \hideinitializer + */ +#define QSPI_SET_LSB_FIRST(qspi) ( (qspi)->CTL |= QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + * \hideinitializer + */ +#define QSPI_SET_MSB_FIRST(qspi) ( (qspi)->CTL &= ~QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << QSPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + * \hideinitializer + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk) >> QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SPIEN (QSPI_CTL[0]) to enable QSPI controller. + * \hideinitializer + */ +#define QSPI_ENABLE(qspi) ( (qspi)->CTL |= QSPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller. + * \hideinitializer + */ +#define QSPI_DISABLE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk ) + + + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask); + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_rng.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_rng.h new file mode 100644 index 0000000..c48d28c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_rng.h @@ -0,0 +1,57 @@ +/**************************************************************************//** + * @file rng.h + * @version V3.00 + * @brief Random Number Generator Interface Controller (rng) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RNG_H__ +#define __RNG_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RNG_Driver RNG Driver + @{ +*/ + +/** @addtogroup RNG_EXPORTED_CONSTANTS RNG Exported Constants + @{ +*/ + +/**@}*/ /* end of group RNG_EXPORTED_CONSTANTS */ + + +/** @addtogroup RNG_EXPORTED_FUNCTIONS RNG Exported Functions + @{ +*/ + +int32_t RNG_Open(void); +int32_t RNG_Random(uint32_t *pu32Buf, int32_t nWords); + +int32_t RNG_ECDSA_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]); +int32_t RNG_ECDSA(uint32_t u32KeySize); +int32_t RNG_ECDH_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]); +int32_t RNG_ECDH(uint32_t u32KeySize); + +/**@}*/ /* end of group RNG_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RNG_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RNG_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_rtc.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_rtc.h new file mode 100644 index 0000000..35e576c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_rtc.h @@ -0,0 +1,411 @@ +/**************************************************************************//** + * @file rtc.h + * @version V3.00 + * @brief Real Time Clock(RTC) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ +#define RTC_FCR_REFERENCE 32752 /*!< RTC Reference for frequency compensation */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tamper Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TAMPER0_SELECT (0x1UL << 0) /*!< Select Tamper 0 \hideinitializer */ +#define RTC_TAMPER1_SELECT (0x1UL << 1) /*!< Select Tamper 1 \hideinitializer */ +#define RTC_TAMPER2_SELECT (0x1UL << 2) /*!< Select Tamper 2 \hideinitializer */ +#define RTC_TAMPER3_SELECT (0x1UL << 3) /*!< Select Tamper 3 \hideinitializer */ +#define RTC_TAMPER4_SELECT (0x1UL << 4) /*!< Select Tamper 4 \hideinitializer */ +#define RTC_TAMPER5_SELECT (0x1UL << 5) /*!< Select Tamper 5 \hideinitializer */ +#define RTC_MAX_TAMPER_PIN_NUM 6UL /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_LOW_LEVEL_DETECT 0UL /*!< Tamper pin detect voltage level is low \hideinitializer */ +#define RTC_TAMPER_HIGH_LEVEL_DETECT 1UL /*!< Tamper pin detect voltage level is high \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_DISABLE 0UL /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_ENABLE 1UL /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ + +#define RTC_PAIR0_SELECT (0x1UL << 0) /*!< Select Pair 0 \hideinitializer */ +#define RTC_PAIR1_SELECT (0x1UL << 1) /*!< Select Pair 1 \hideinitializer */ +#define RTC_PAIR2_SELECT (0x1UL << 2) /*!< Select Pair 2 \hideinitializer */ +#define RTC_MAX_PAIR_NUM 3UL /*!< Pair number \hideinitializer */ + +#define RTC_2POW10_CLK (0x0UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */ +#define RTC_2POW11_CLK (0x1UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */ +#define RTC_2POW12_CLK (0x2UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */ +#define RTC_2POW13_CLK (0x3UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */ +#define RTC_2POW14_CLK (0x4UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */ +#define RTC_2POW15_CLK (0x5UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */ +#define RTC_2POW16_CLK (0x6UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */ +#define RTC_2POW17_CLK (0x7UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */ + +#define RTC_REF_RANDOM_PATTERN 0x0UL /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */ +#define RTC_REF_SEED_VALUE 0x1UL /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Clock Source Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_SOURCE_LXT 0UL /*!< Set RTC clock source as external LXT \hideinitializer */ +#define RTC_CLOCK_SOURCE_LIRC 1UL /*!< Set RTC clock source as LIRC \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_IO_MODE_INPUT 0x0UL /*!< Input Mode */ +#define RTC_IO_MODE_OUTPUT 0x1UL /*!< Output Mode */ +#define RTC_IO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define RTC_IO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + +#define RTC_IO_DIGITAL_ENABLE 0UL /*!< I/O digital path is enabled */ +#define RTC_IO_DIGITAL_DISABLE 1UL /*!< I/O digital path is disabled */ + +#define RTC_IO_PULL_UP_DOWN_DISABLE 0x0UL /*!< I/O pull-up and pull-down is disabled */ +#define RTC_IO_PULL_UP_ENABLE 0x1UL /*!< I/O pull-up is enabled */ +#define RTC_IO_PULL_DOWN_ENABLE 0x2UL /*!< I/O pull-down is enabled */ + +#define RTC_TIMEOUT_ERR (-1L) /*!< RTC operation abort due to timeout error \hideinitializer */ + +/**@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/**@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + +extern int32_t g_RTC_i32ErrCode; + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param None + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR() ((RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk)? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk \n + * - \ref RTC_INTSTS_TAMP1IF_Msk \n + * - \ref RTC_INTSTS_TAMP2IF_Msk \n + * - \ref RTC_INTSTS_TAMP3IF_Msk \n + * - \ref RTC_INTSTS_TAMP4IF_Msk \n + * - \ref RTC_INTSTS_TAMP5IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC snooper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param None + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param None + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Set I/O Control By GPIO Module + * + * @param None + * + * @return None + * + * @details This macro sets the PF.4~11 pin I/O is controlled by GPIO module. + * \hideinitializer + */ +#define RTC_SET_IOCTL_BY_GPIO() (RTC->LXTCTL &= ~RTC_LXTCTL_IOCTLSEL_Msk) + +/** + * @brief Set I/O Control By RTC Module + * + * @param None + * + * @return None + * + * @details This macro sets the PF.4~11 pin I/O is controlled by RTC module. + * \hideinitializer + */ +#define RTC_SET_IOCTL_BY_RTC() (RTC->LXTCTL |= RTC_LXTCTL_IOCTLSEL_Msk) + +/** + * @brief Get I/O Control Property + * + * @param None + * + * @retval 0 PF.4~11 pin I/O is controlled by GPIO module + * @retval 1 PF.4~11 pin I/O is controlled by RTC module + * + * @details This macro indicates the PF.4~11 pin I/O control property. + * \hideinitializer + */ +#define RTC_GET_IOCTL_PROPERTY() ((RTC->LXTCTL & RTC_LXTCTL_IOCTLSEL_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param None + * + * @retval 0 RTC tamper event interrupt did not occur + * @retval 1 RTC tamper event interrupt occurred + * + * @details This macro indicates RTC tamper event occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x3F00))? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Status + * + * @param None + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated + * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated + * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated + * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated + * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated + * + * @details This macro indicates RTC tamper interrupt status. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x3F00))) + +/** + * @brief Enable RTC Tick Wake-up Function + * + * @param None + * + * @return None + * + * @details This macro is used to enable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_ENABLE_TICK_WAKEUP() (RTC->INTEN |= RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Disable RTC Tick Wake-up Function + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to disable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_DISABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN &= ~RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Read Spare Register + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +static __INLINE void RTC_WaitAccessEnable(void); + +/** + * @brief Wait RTC Access Enable + * + * @param None + * + * @return None + * + * @details This function is used to enable the maximum RTC read/write accessible time. + */ +static __INLINE void RTC_WaitAccessEnable(void) +{ + /* Dummy for M460 */ +} + +int32_t RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk); +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void RTC_DynamicTamperDisable(uint32_t u32PairSel); +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); +uint32_t RTC_SetClockSource(uint32_t u32ClkSrc); +void RTC_SetGPIOMode(uint32_t u32PFPin, uint32_t u32Mode, uint32_t u32DigitalCtl, uint32_t u32PullCtl, uint32_t u32OutputLevel); +void RTC_SetGPIOLevel(uint32_t u32PFPin, uint32_t u32OutputLevel); + +/**@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RTC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sc.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sc.h new file mode 100644 index 0000000..f291df8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sc.h @@ -0,0 +1,333 @@ +/**************************************************************************//** + * @file sc.h + * @version V3.00 + * @brief Smartcard(SC) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM (3UL) /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH (1UL) /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW (0UL) /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE (0xFFFFFFFFUL) /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON (1UL) /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF (0UL) /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0UL << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level. + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + uint32_t u32TimeOutCount = SystemCoreClock;\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk)\ + if(--u32TimeOutCount == 0) break;\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF. + * + * @return None + * + * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not. + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + uint32_t u32TimeOutCount = SystemCoreClock;\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk)\ + if(--u32TimeOutCount == 0) break;\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low. + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + uint32_t u32TimeOutCount = SystemCoreClock;\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(--u32TimeOutCount == 0) break;\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low. + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + uint32_t u32TimeOutCount = SystemCoreClock;\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(--u32TimeOutCount == 0) break;\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * + * @param[in] sc The pointer of smartcard module. + * + * @return One byte read from receive FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data to write to transmit FIFO. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Len Stop bit length, ether 1 or 2. + * + * @return None + * + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry. + * + * @return None + * + * @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + uint32_t u32TimeOutCount = 0; + + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if((u32Count) != 0UL) + { + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry. + * + * @return None + * + * @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + uint32_t u32TimeOutCount = 0; + + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if((u32Count) != 0UL) + { + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + +/**@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SC_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_scuart.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_scuart.h new file mode 100644 index 0000000..99287e3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_scuart.h @@ -0,0 +1,356 @@ +/**************************************************************************//** + * @file scuart.h + * @version V3.00 + * @brief Smartcard UART mode (SCUART) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCUART_H__ +#define __SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + +#define SCUART_TIMEOUT_ERR (-1L) /*!< SCUART operation abort due to timeout error \hideinitializer */ + +/**@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + +extern int32_t g_SCUART_i32ErrCode; + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get Tx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * + * @details When the last byte of Tx buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY (SC_STATUS[9]) high. + * It will be cleared when writing data into DAT (SC_DAT[7:0]). + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get Tx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details TXACT (SC_STATUS[31]) is cleared automatically when Tx transfer is finished or the last byte transmission has completed. + * + * @note This macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while(((sc)->STATUS & SC_STATUS_TXACT_Msk) == SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) indicates Tx buffer full or not. + * This bit is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) (((sc)->STATUS & SC_STATUS_TXFULL_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * + * @details TXACT (SC_STATUS[31]) indicates Tx Transmit is complete or not. + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 0 : 1) + +/** + * @brief Check specified smartcard port transmit FIFO empty status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval 1 Transmit FIFO is empty + * + * @details TXEMPTY (SC_STATUS[9]) is set by hardware when the last byte of Tx buffer has been transferred to Transmitter Shift Register. + * \hideinitializer + */ +#define SCUART_IS_TX_FIFO_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)? 1 : 0) + +/** + * @brief Check specified Smartcard port Transmission Status + * + * @param[in] sc The pointer of smartcard module. + * + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + + +/* RX Macros */ +/** + * @brief Read Rx data register + * + * @param[in] sc The pointer of smartcard module. + * + * @return The oldest data byte in RX FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get Rx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * + * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY (SC_STATUS[1]) high. + * It will be cleared when SC receives any new data. + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + +/** + * @brief Get Rx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full + * + * @details RXFULL (SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * + * @details RDAIF (SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. + * + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO. + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) (((sc)->INTSTS & SC_INTSTS_RDAIF_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * + * @details RXFULLF( SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) (((sc)->STATUS & SC_STATUS_RXFULL_Msk)? 1 : 0) + + +/* Interrupt Macros */ +/** + * @brief Enable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * + * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status, + * transmit buffer empty interrupt status or receive data reach interrupt status. + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) (((sc)->INTSTS & (u32Type))? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to clear, only \ref SC_INTSTS_TERRIF_Msk valid for this macro. + * + * @return None + * + * @details The macro is used to clear transfer error interrupt flag. + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * + * @details The macro is used to get receiver parity error status, frame error status or break error status. + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * + * @return None + * + * @details The macro is used to clear receiver parity error flag, frame error flag or break error flag. + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +uint32_t SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/**@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SCUART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCUART_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sdh.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sdh.h new file mode 100644 index 0000000..2b025e1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sdh.h @@ -0,0 +1,206 @@ +/**************************************************************************//** + * @file sdh.h + * @version V1.00 + * @brief SDH driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include + +#ifndef __SDH_H__ +#define __SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_ERR_ID 0xFFFF0100ul /*!< SDH error ID \hideinitializer */ + +#define SDH_TIMEOUT (SDH_ERR_ID|0x01ul) /*!< Timeout \hideinitializer */ +#define SDH_NO_MEMORY (SDH_ERR_ID|0x02ul) /*!< OOM \hideinitializer */ + +/*-- function return value */ +#define Successful 0ul /*!< Success \hideinitializer */ +#define Fail 1ul /*!< Failed \hideinitializer */ + +/*--- define type of SD card or MMC */ +#define SDH_TYPE_UNKNOWN 0ul /*!< Unknown card type \hideinitializer */ +#define SDH_TYPE_SD_HIGH 1ul /*!< SDHC card \hideinitializer */ +#define SDH_TYPE_SD_LOW 2ul /*!< SD card \hideinitializer */ +#define SDH_TYPE_MMC 3ul /*!< MMC card \hideinitializer */ +#define SDH_TYPE_EMMC 4ul /*!< eMMC card \hideinitializer */ + +/* SD error */ +#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10ul) /*!< Card removed \hideinitializer */ +#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11ul) /*!< Device error \hideinitializer */ +#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12ul) /*!< Card init timeout \hideinitializer */ +#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13ul) /*!< Card select error \hideinitializer */ +#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14ul) /*!< Card write protect \hideinitializer */ +#define SDH_INIT_ERROR (SDH_ERR_ID|0x15ul) /*!< Card init error \hideinitializer */ +#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16ul) /*!< CRC 7 error \hideinitializer */ +#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17ul) /*!< CRC 16 error \hideinitializer */ +#define SDH_CRC_ERROR (SDH_ERR_ID|0x18ul) /*!< CRC error \hideinitializer */ +#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19ul) /*!< Command 8 error \hideinitializer */ + +#define MMC_FREQ 20000ul /*!< output 20MHz to MMC \hideinitializer */ +#define SD_FREQ 25000ul /*!< output 25MHz to SD \hideinitializer */ +#define SDHC_FREQ 50000ul /*!< output 50MHz to SDH \hideinitializer */ + +#define SD_PORT0 (1 << 0) /*!< Card select SD0 \hideinitializer */ +#define SD_PORT1 (1 << 2) /*!< Card select SD1 \hideinitializer */ +#define CardDetect_From_GPIO (1ul << 8) /*!< Card detection pin is GPIO \hideinitializer */ +#define CardDetect_From_DAT3 (1ul << 9) /*!< Card detection pin is DAT3 \hideinitializer */ + +#define TIMEOUT_SDH SystemCoreClock /* 1 second time-out */ +#define SDH_TIMEOUT_ERR (-1L) /*!< SDH operation abort due to timeout error \hideinitializer */ + +/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines + @{ +*/ +typedef struct SDH_info_t +{ + unsigned char IsCardInsert; /*!< Card insert state */ + unsigned char R3Flag; + unsigned char R7Flag; + unsigned char volatile DataReadyFlag; + unsigned int CardType; /*!< SDHC, SD, or MMC */ + unsigned int RCA; /*!< Relative card address */ + unsigned int totalSectorN; /*!< Total sector number */ + unsigned int diskSize; /*!< Disk size in K bytes */ + int sectorSize; /*!< Sector size in bytes */ + unsigned char *dmabuf; +} SDH_INFO_T; /*!< Structure holds SD card info */ + +/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */ + +/** @cond HIDDEN_SYMBOLS */ +extern SDH_INFO_T SD0, SD1; +extern int32_t g_SDH_i32ErrCode; +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +/** + * @brief Enable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_CDSRC_Msk \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / + * \ref SDH_INTEN_WKIEN_Msk + * + * @return None. + * \hideinitializer + */ +#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask)) + +/** + * @brief Disable specified interrupt. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk / + * + * @return None. + * \hideinitializer + */ +#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask)) + +/** + * @brief Get specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / + * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / + * \ref SDH_INTSTS_CDIF_Msk \ref SDH_INTSTS_RTOIF_Msk / + * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / + * \ref SDH_INTSTS_DAT1STS_Msk + * + * + * @return 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + * \hideinitializer + */ +#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0) + + +/** + * @brief Clear specified interrupt flag/status. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk / + * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk + * + * + * @return None. + * \hideinitializer + */ +#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask)) + + +/** + * @brief Check SD Card inserted or removed. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return 1: Card inserted. + * 0: Card removed. + * \hideinitializer + */ +#define SDH_IS_CARD_PRESENT(sdh) (((sdh) == SDH0)? SD0.IsCardInsert : SD1.IsCardInsert) + +/** + * @brief Get SD Card capacity. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return SD Card capacity. (unit: KByte) + * \hideinitializer + */ +#define SDH_GET_CARD_CAPACITY(sdh) (((sdh) == SDH0)? SD0.diskSize : SD1.diskSize) + + +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); +uint32_t SDH_Probe(SDH_T *sdh); +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); + +uint32_t SDH_CardDetection(SDH_T *sdh); +void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc); +void SDH_Close_Disk(SDH_T *sdh); + + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDH_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_spi.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_spi.h new file mode 100644 index 0000000..30623a5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_spi.h @@ -0,0 +1,617 @@ +/**************************************************************************//** + * @file spi.h + * @version V3.00 + * @brief M460 series SPI driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define SPI_MASTER (0x0U) /*!< Set as master \hideinitializer */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define SPI_SS_ACTIVE_LOW (0x0U) /*!< SS active low \hideinitializer */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001U) /*!< Unit transfer interrupt mask \hideinitializer */ +#define SPI_SSACT_INT_MASK (0x002U) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define SPI_SSINACT_INT_MASK (0x004U) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define SPI_SLVUR_INT_MASK (0x008U) /*!< Slave under run interrupt mask \hideinitializer */ +#define SPI_SLVBE_INT_MASK (0x010U) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define SPI_TXUF_INT_MASK (0x040U) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define SPI_FIFO_TXTH_INT_MASK (0x080U) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTH_INT_MASK (0x100U) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXOV_INT_MASK (0x200U) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTO_INT_MASK (0x400U) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01U) /*!< Busy status mask \hideinitializer */ +#define SPI_RX_EMPTY_MASK (0x02U) /*!< RX empty status mask \hideinitializer */ +#define SPI_RX_FULL_MASK (0x04U) /*!< RX full status mask \hideinitializer */ +#define SPI_TX_EMPTY_MASK (0x08U) /*!< TX empty status mask \hideinitializer */ +#define SPI_TX_FULL_MASK (0x10U) /*!< TX full status mask \hideinitializer */ +#define SPI_TXRX_RESET_MASK (0x20U) /*!< TX or RX reset status mask \hideinitializer */ +#define SPI_SPIEN_STS_MASK (0x40U) /*!< SPIEN status mask \hideinitializer */ +#define SPI_SSLINE_STS_MASK (0x80U) /*!< SPIx_SS line status mask \hideinitializer */ + +/* SPI Status2 Mask */ +#define SPI_SLVBENUM_MASK (0x01U) /*!< Effective bit number of uncompleted RX data status mask \hideinitializer */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define SPII2S_DATABIT_16 (1U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define SPII2S_DATABIT_24 (2U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define SPII2S_DATABIT_32 (3U << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */ +#define SPII2S_STEREO (0U) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0U<STATUS = SPI_STATUS_UNITIF_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode. + * \hideinitializer + */ +#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode. + * \hideinitializer + */ +#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_RX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_COUNT(spi) ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + * \hideinitializer + */ +#define SPI_READ_RX(spi) ( (spi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + * \hideinitializer + */ +#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) ) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + * \hideinitializer + */ +#define SPI_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) ) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + * \hideinitializer + */ +#define SPI_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + * \hideinitializer + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + * \hideinitializer + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + * \hideinitializer + */ +#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk ) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + * \hideinitializer + */ +#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 4 ~ 32 bits. + * \hideinitializer + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + * \hideinitializer + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + * \hideinitializer + */ +#define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + * \hideinitializer + */ +#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk ) + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + * \hideinitializer + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + * \hideinitializer + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + * \hideinitializer + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + * \hideinitializer + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + * \hideinitializer + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + + + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_spim.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_spim.h new file mode 100644 index 0000000..a47d87b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_spim.h @@ -0,0 +1,634 @@ +/**************************************************************************//** + * @file spim.h + * @version V1.00 + * @brief M480 series SPIM driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPIM_H__ +#define __SPIM_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + + +/** @addtogroup SPIM_EXPORTED_CONSTANTS SPIM Exported Constants + @{ +*/ + +#define SPIM_DMM_MAP_ADDR 0x100000UL /*!< DMM mode memory map base address \hideinitializer */ +#define SPIM_DMM_SIZE 0x100000UL /*!< DMM mode memory mapping size \hideinitializer */ +#define SPIM_CCM_ADDR 0x20020000UL /*!< CCM mode memory map base address \hideinitializer */ +#define SPIM_CCM_SIZE 0x8000UL /*!< CCM mode memory size \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPIM_CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SPIM_CTL0_RW_IN(x) ((x) ? 0UL : (0x1UL << SPIM_CTL0_QDIODIR_Pos)) /*!< SPIM_CTL0: SPI Interface Direction Select \hideinitializer */ +#define SPIM_CTL0_BITMODE_SING (0UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: One bit mode (SPI Interface including DO, DI, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_DUAL (1UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Two bits mode (SPI Interface including D0, D1, HOLD, WP) \hideinitializer */ +#define SPIM_CTL0_BITMODE_QUAD (2UL << SPIM_CTL0_BITMODE_Pos) /*!< SPIM_CTL0: Four bits mode (SPI Interface including D0, D1, D2, D3) \hideinitializer */ +#define SPIM_CTL0_OPMODE_IO (0UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: I/O Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEWRITE (1UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Write Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_PAGEREAD (2UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Page Read Mode \hideinitializer */ +#define SPIM_CTL0_OPMODE_DIRECTMAP (3UL << SPIM_CTL0_OPMODE_Pos) /*!< SPIM_CTL0: Direct Map Mode \hideinitializer */ + +#define CMD_NORMAL_PAGE_PROGRAM (0x02UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_NORMAL_PAGE_PROGRAM_4B (0x12UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Page Program (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_WINBOND (0x32UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for Winbond) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_MXIC (0x38UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page program (for MXIC) (Page Write Mode Use) \hideinitializer */ +#define CMD_QUAD_PAGE_PROGRAM_EON (0x40UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Quad Page Program (for EON) (Page Write Mode Use) \hideinitializer */ + +#define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ +#define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ + +typedef enum +{ + MFGID_UNKNOW = 0x00U, + MFGID_SPANSION = 0x01U, + MFGID_EON = 0x1CU, + MFGID_ISSI = 0x7FU, + MFGID_MXIC = 0xC2U, + MFGID_WINBOND = 0xEFU +} +E_MFGID; + +/* Flash opcodes. */ +#define OPCODE_WREN 0x06U /* Write enable */ +#define OPCODE_RDSR 0x05U /* Read status register #1*/ +#define OPCODE_WRSR 0x01U /* Write status register #1 */ +#define OPCODE_RDSR2 0x35U /* Read status register #2*/ +#define OPCODE_WRSR2 0x31U /* Write status register #2 */ +#define OPCODE_RDSR3 0x15U /* Read status register #3*/ +#define OPCODE_WRSR3 0x11U /* Write status register #3 */ +#define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */ +#define OPCODE_SE_4K 0x20U /* Erase 4KB sector */ +#define OPCODE_BE_32K 0x52U /* Erase 32KB block */ +#define OPCODE_CHIP_ERASE 0xc7U /* Erase whole flash chip */ +#define OPCODE_BE_64K 0xd8U /* Erase 64KB block */ +#define OPCODE_READ_ID 0x90U /* Read ID */ +#define OPCODE_RDID 0x9fU /* Read JEDEC ID */ +#define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */ +#define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */ +#define OPCODE_NORM_READ 0x03U /* Read data bytes */ +#define OPCODE_FAST_READ 0x0bU /* Read data bytes */ +#define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */ +#define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */ + +/* Used for SST flashes only. */ +#define OPCODE_BP 0x02U /* Byte program */ +#define OPCODE_WRDI 0x04U /* Write disable */ +#define OPCODE_AAI_WP 0xadU /* Auto u32Address increment word program */ + +/* Used for Macronix flashes only. */ +#define OPCODE_EN4B 0xb7U /* Enter 4-byte mode */ +#define OPCODE_EX4B 0xe9U /* Exit 4-byte mode */ + +#define OPCODE_RDSCUR 0x2bU +#define OPCODE_WRSCUR 0x2fU + +#define OPCODE_RSTEN 0x66U +#define OPCODE_RST 0x99U + +#define OPCODE_ENQPI 0x38U +#define OPCODE_EXQPI 0xFFU + +/* Status Register bits. */ +#define SR_WIP 0x1U /* Write in progress */ +#define SR_WEL 0x2U /* Write enable latch */ +#define SR_QE 0x40U /* Quad Enable for MXIC */ +/* Status Register #2 bits. */ +#define SR2_QE 0x2U /* Quad Enable for Winbond */ +/* meaning of other SR_* bits may differ between vendors */ +#define SR_BP0 0x4U /* Block protect 0 */ +#define SR_BP1 0x8U /* Block protect 1 */ +#define SR_BP2 0x10U /* Block protect 2 */ +#define SR_SRWD 0x80U /* SR write protect */ +#define SR3_ADR 0x01U /* 4-byte u32Address mode */ + +#define SCUR_4BYTE 0x04U /* 4-byte u32Address mode */ + +/** @endcond HIDDEN_SYMBOLS */ + +#define SPIM_TIMEOUT_ERR (-1L) /*!< SPIM operation abort due to timeout error \hideinitializer */ + +/*@}*/ /* end of group SPIM_EXPORTED_CONSTANTS */ + +extern int32_t g_SPIM_i32ErrCode; + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/** + * @details Enable cipher. + * \hideinitializer + */ +#define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Disable cipher. + * \hideinitializer + */ +#define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk) + +/** + * @details Enable cipher balance + * \hideinitializer + */ +#define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk) + +/** + * @details Disable cipher balance + * \hideinitializer + */ +#define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk) + +/** + * @details Set 4-byte address to be enabled/disabled. + * \hideinitializer + */ +#define SPIM_SET_4BYTE_ADDR_EN(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \ + } while (0) + +/** + * @details Enable SPIM interrupt + * \hideinitializer + */ +#define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk) + +/** + * @details Disable SPIM interrupt + * \hideinitializer + */ +#define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk) + +/** + * @details Is interrupt flag on. + * \hideinitializer + */ +#define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL) + +/** + * @details Clear interrupt flag. + * \hideinitializer + */ +#define SPIM_CLR_INT() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \ + } while (0) + +/** + * @details Set transmit/receive bit length + * \hideinitializer + */ +#define SPIM_SET_DATA_WIDTH(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive bit length setting + * \hideinitializer + */ +#define SPIM_GET_DATA_WIDTH() \ + (((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U) + +/** + * @details Set data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_SET_DATA_NUM(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \ + } while (0) + +/** + * @details Get data transmit/receive burst number + * \hideinitializer + */ +#define SPIM_GET_DATA_NUM() \ + (((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U) + +/** + * @details Enable Single Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \ + } while (0) + +/** + * @details Enable Single Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_SING_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \ + } while (0) + +/** + * @details Enable Dual Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Dual Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_DUAL_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Enable Quad Input mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_INPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \ + } while (0) + +/** + * @details Enable Quad Output mode. + * \hideinitializer + */ +#define SPIM_ENABLE_QUAD_OUTPUT_MODE() \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \ + } while (0) + +/** + * @details Set suspend interval which ranges between 0 and 15. + * \hideinitializer + */ +#define SPIM_SET_SUSP_INTVL(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \ + } while (0) + +/** + * @details Get suspend interval setting + * \hideinitializer + */ +#define SPIM_GET_SUSP_INTVL() \ + ((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos) + +/** + * @details Set operation mode. + * \hideinitializer + */ +#define SPIM_SET_OPMODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get operation mode. + * \hideinitializer + */ +#define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk) + +/** + * @details Set SPIM mode. + * \hideinitializer + */ +#define SPIM_SET_SPIM_MODE(x) \ + do { \ + SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \ + } while (0) + +/** + * @details Get SPIM mode. + * \hideinitializer + */ +#define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk) + +/** + * @details Start operation. + * \hideinitializer + */ +#define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Is engine busy. + * \hideinitializer + */ +#define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Wait for free. + * \hideinitializer + */ +#define SPIM_WAIT_FREE() while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) + +/** + * @details Enable cache. + * \hideinitializer + */ +#define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Disable cache. + * \hideinitializer + */ +#define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk) + +/** + * @details Is cache enabled. + * \hideinitializer + */ +#define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1) + +/** + * @details Enable CCM + * \hideinitializer + */ +#define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk) + +/** + * @details Disable CCM. + * \hideinitializer + */ +#define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk) + +/** + * @details Is CCM enabled. + * \hideinitializer + */ +#define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos) + +/** + * @details Invalidate cache. + * \hideinitializer + */ +#define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk) + +/** + * @details Set SS(Select Active) to active level. + * \hideinitializer + */ +#define SPIM_SET_SS_EN(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \ + } while (0) + +/** + * @details Is SS(Select Active) in active level. + * \hideinitializer + */ +#define SPIM_GET_SS_EN() \ + (!(SPIM->CTL1 & SPIM_CTL1_SS_Msk)) + +/** + * @details Set active level of slave select to be high/low. + * \hideinitializer + */ +#define SPIM_SET_SS_ACTLVL(x) \ + do { \ + (SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \ + } while (0) + +/** + * @details Set idle time interval + * \hideinitializer + */ +#define SPIM_SET_IDL_INTVL(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \ + } while (0) + +/** + * @details Get idle time interval setting + * \hideinitializer + */ +#define SPIM_GET_IDL_INTVL() \ + ((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos) + +/** + * @details Set SPIM clock divider + * \hideinitializer + */ +#define SPIM_SET_CLOCK_DIVIDER(x) \ + do { \ + SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \ + } while (0) + +/** + * @details Get SPIM current clock divider setting + * \hideinitializer + */ +#define SPIM_GET_CLOCK_DIVIDER() \ + ((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos) + +/** + * @details Set SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_DWDELSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \ + } while (0) + +/** + * @details Get SPI flash deselect time interval of DMA write mode + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_DWDELSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos) + +/** + * @details Set sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \ + do { \ + (SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \ + } while (0) + +/** + * @details Get sampling clock delay selection for received data + * \hideinitializer + */ +#define SPIM_GET_RXCLKDLY_RDDLYSEL() \ + ((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos) + +/** + * @details Set sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_SET_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \ + +/** + * @details Get sampling clock edge selection for received data + * \hideinitializer + */ +#define SPIM_CLR_RXCLKDLY_RDEDGE() \ + (SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk) + +/** + * @details Set mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_SET_DMMCTL_CRMDAT(x) \ + do { \ + (SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \ + } while (0) + +/** + * @details Get mode bits data for continuous read mode + * \hideinitializer + */ +#define SPIM_GET_DMMCTL_CRMDAT() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos) + +/** + * @details Set DMM mode SPI flash deselect time + * \hideinitializer + */ +#define SPIM_DMM_SET_DESELTIM(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \ + } while (0) + +/** + * @details Get current DMM mode SPI flash deselect time setting + * \hideinitializer + */ +#define SPIM_DMM_GET_DESELTIM() \ + ((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos) + +/** + * @details Enable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Disable DMM mode burst wrap mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk) + +/** + * @details Enable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk) + +/** + * @details Disable DMM mode continuous read mode + * \hideinitializer + */ +#define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk) + +/** + * @details Set DMM mode SPI flash active SCLK time + * \hideinitializer + */ +#define SPIM_DMM_SET_ACTSCLKT(x) \ + do { \ + SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \ + } while (0) + +/** + * @details Set SPI flash active SCLK time as SPIM default + * \hideinitializer + */ +#define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) + * \hideinitializer + */ +#define SPIM_SET_DCNUM(x) \ + do { \ + SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \ + } while (0) + +/** + * @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default + * \hideinitializer + */ +#define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk) + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Function Prototypes */ +/*---------------------------------------------------------------------------------------------------------*/ + + +int SPIM_InitFlash(int clrWP); +uint32_t SPIM_GetSClkFreq(void); +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit); +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit); +int SPIM_Is4ByteModeEnable(uint32_t u32NBit); + +void SPIM_ChipErase(uint32_t u32NBit, int isSync); +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync); + +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat); +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy); + +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd); +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync); + +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl); +void SPIM_ExitDirectMapMode(void); + +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit); + +void SPIM_WinbondUnlock(uint32_t u32NBit); + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPIM_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sys.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sys.h new file mode 100644 index 0000000..80e7afe --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_sys.h @@ -0,0 +1,7092 @@ +/**************************************************************************//** + * @file SYS.h + * @version V3.0 + * @brief M460 Series SYS Driver Header File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef __SYS_H__ +#define __SYS_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + +#define SYS_TIMEOUT_ERR (-1L) /*!< SYS operation abort due to timeout error \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA0_RST ((0UL<<24) | SYS_IPRST0_PDMA0RST_Pos) /*!< Reset PDMA0 \hideinitializer*/ +#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer*/ +#define EMAC0_RST ((0UL<<24) | SYS_IPRST0_EMAC0RST_Pos) /*!< Reset EMAC0 \hideinitializer */ +#define SDH0_RST ((0UL<<24) | SYS_IPRST0_SDH0RST_Pos) /*!< Reset SDH0 \hideinitializer */ +#define CRC_RST ((0UL<<24) | SYS_IPRST0_CRCRST_Pos) /*!< Reset CRC \hideinitializer */ +#define CCAP_RST ((0UL<<24) | SYS_IPRST0_CCAPRST_Pos) /*!< Reset CCAP \hideinitializer */ +#define HSUSBD_RST ((0UL<<24) | SYS_IPRST0_HSUSBDRST_Pos) /*!< Reset HSUSBD \hideinitializer */ +#define HBI_RST ((0UL<<24) | SYS_IPRST0_HBIRST_Pos) /*!< Reset HBI \hideinitializer */ +#define CRPT_RST ((0UL<<24) | SYS_IPRST0_CRPTRST_Pos) /*!< Reset CRPT \hideinitializer */ +#define KS_RST ((0UL<<24) | SYS_IPRST0_KSRST_Pos) /*!< Reset KS \hideinitializer */ +#define SPIM_RST ((0UL<<24) | SYS_IPRST0_SPIMRST_Pos) /*!< Reset SPIM \hideinitializer */ +#define HSUSBH_RST ((0UL<<24) | SYS_IPRST0_HSUSBHRST_Pos) /*!< Reset HSUSBH \hideinitializer */ +#define SDH1_RST ((0UL<<24) | SYS_IPRST0_SDH1RST_Pos) /*!< Reset SDH1 \hideinitializer */ +#define PDMA1_RST ((0UL<<24) | SYS_IPRST0_PDMA1RST_Pos) /*!< Reset PDMA1 \hideinitializer */ +#define CANFD0_RST ((0UL<<24) | SYS_IPRST0_CANFD0RST_Pos) /*!< Reset CANFD0 \hideinitializer */ +#define CANFD1_RST ((0UL<<24) | SYS_IPRST0_CANFD1RST_Pos) /*!< Reset CANFD1 \hideinitializer */ +#define CANFD2_RST ((0UL<<24) | SYS_IPRST0_CANFD2RST_Pos) /*!< Reset CANFD2 \hideinitializer */ +#define CANFD3_RST ((0UL<<24) | SYS_IPRST0_CANFD3RST_Pos) /*!< Reset CANFD3 \hideinitializer */ + +#define GPIO_RST ((4UL<<24) | SYS_IPRST1_GPIORST_Pos) /*!< Reset GPIO \hideinitializer */ +#define TMR0_RST ((4UL<<24) | SYS_IPRST1_TMR0RST_Pos) /*!< Reset TMR0 \hideinitializer */ +#define TMR1_RST ((4UL<<24) | SYS_IPRST1_TMR1RST_Pos) /*!< Reset TMR1 \hideinitializer */ +#define TMR2_RST ((4UL<<24) | SYS_IPRST1_TMR2RST_Pos) /*!< Reset TMR2 \hideinitializer */ +#define TMR3_RST ((4UL<<24) | SYS_IPRST1_TMR3RST_Pos) /*!< Reset TMR3 \hideinitializer */ +#define ACMP01_RST ((4UL<<24) | SYS_IPRST1_ACMP01RST_Pos) /*!< Reset ACMP01 \hideinitializer */ +#define I2C0_RST ((4UL<<24) | SYS_IPRST1_I2C0RST_Pos) /*!< Reset I2C0 \hideinitializer */ +#define I2C1_RST ((4UL<<24) | SYS_IPRST1_I2C1RST_Pos) /*!< Reset I2C1 \hideinitializer */ +#define I2C2_RST ((4UL<<24) | SYS_IPRST1_I2C2RST_Pos) /*!< Reset I2C2 \hideinitializer */ +#define I2C3_RST ((4UL<<24) | SYS_IPRST1_I2C3RST_Pos) /*!< Reset I2C3 \hideinitializer */ +#define QSPI0_RST ((4UL<<24) | SYS_IPRST1_QSPI0RST_Pos) /*!< Reset QSPI0 \hideinitializer */ +#define SPI0_RST ((4UL<<24) | SYS_IPRST1_SPI0RST_Pos) /*!< Reset SPI0 \hideinitializer */ +#define SPI1_RST ((4UL<<24) | SYS_IPRST1_SPI1RST_Pos) /*!< Reset SPI1 \hideinitializer */ +#define SPI2_RST ((4UL<<24) | SYS_IPRST1_SPI2RST_Pos) /*!< Reset SPI2 \hideinitializer */ +#define UART0_RST ((4UL<<24) | SYS_IPRST1_UART0RST_Pos) /*!< Reset UART0 \hideinitializer */ +#define UART1_RST ((4UL<<24) | SYS_IPRST1_UART1RST_Pos) /*!< Reset UART1 \hideinitializer */ +#define UART2_RST ((4UL<<24) | SYS_IPRST1_UART2RST_Pos) /*!< Reset UART2 \hideinitializer */ +#define UART3_RST ((4UL<<24) | SYS_IPRST1_UART3RST_Pos) /*!< Reset UART3 \hideinitializer */ +#define UART4_RST ((4UL<<24) | SYS_IPRST1_UART4RST_Pos) /*!< Reset UART4 \hideinitializer */ +#define UART5_RST ((4UL<<24) | SYS_IPRST1_UART5RST_Pos) /*!< Reset UART5 \hideinitializer */ +#define UART6_RST ((4UL<<24) | SYS_IPRST1_UART6RST_Pos) /*!< Reset UART6 \hideinitializer */ +#define UART7_RST ((4UL<<24) | SYS_IPRST1_UART7RST_Pos) /*!< Reset UART7 \hideinitializer */ +#define OTG_RST ((4UL<<24) | SYS_IPRST1_OTGRST_Pos) /*!< Reset OTG \hideinitializer */ +#define USBD_RST ((4UL<<24) | SYS_IPRST1_USBDRST_Pos) /*!< Reset USBD \hideinitializer */ +#define EADC0_RST ((4UL<<24) | SYS_IPRST1_EADC0RST_Pos) /*!< Reset EADC0 \hideinitializer */ +#define I2S0_RST ((4UL<<24) | SYS_IPRST1_I2S0RST_Pos) /*!< Reset I2S0 \hideinitializer */ +#define HSOTG_RST ((4UL<<24) | SYS_IPRST1_HSOTGRST_Pos) /*!< Reset HSOTG \hideinitializer */ +#define TRNG_RST ((4UL<<24) | SYS_IPRST1_TRNGRST_Pos) /*!< Reset TRNG \hideinitializer */ + +#define SC0_RST ((8UL<<24) | SYS_IPRST2_SC0RST_Pos) /*!< Reset SC0 \hideinitializer */ +#define SC1_RST ((8UL<<24) | SYS_IPRST2_SC1RST_Pos) /*!< Reset SC1 \hideinitializer */ +#define SC2_RST ((8UL<<24) | SYS_IPRST2_SC2RST_Pos) /*!< Reset SC2 \hideinitializer */ +#define I2C4_RST ((8UL<<24) | SYS_IPRST2_I2C4RST_Pos) /*!< Reset I2C4 \hideinitializer */ +#define QSPI1_RST ((8UL<<24) | SYS_IPRST2_QSPI1RST_Pos) /*!< Reset QSPI1 \hideinitializer */ +#define SPI3_RST ((8UL<<24) | SYS_IPRST2_SPI3RST_Pos) /*!< Reset SPI3 \hideinitializer */ +#define SPI4_RST ((8UL<<24) | SYS_IPRST2_SPI4RST_Pos) /*!< Reset SPI4 \hideinitializer */ +#define USCI0_RST ((8UL<<24) | SYS_IPRST2_USCI0RST_Pos) /*!< Reset USCI0 \hideinitializer */ +#define PSIO_RST ((8UL<<24) | SYS_IPRST2_PSIORST_Pos) /*!< Reset PSIO \hideinitializer */ +#define DAC_RST ((8UL<<24) | SYS_IPRST2_DACRST_Pos) /*!< Reset DAC \hideinitializer */ +#define EPWM0_RST ((8UL<<24) | SYS_IPRST2_EPWM0RST_Pos) /*!< Reset EPWM0 \hideinitializer */ +#define EPWM1_RST ((8UL<<24) | SYS_IPRST2_EPWM1RST_Pos) /*!< Reset EPWM1 \hideinitializer */ +#define BPWM0_RST ((8UL<<24) | SYS_IPRST2_BPWM0RST_Pos) /*!< Reset BPWM0 \hideinitializer */ +#define BPWM1_RST ((8UL<<24) | SYS_IPRST2_BPWM1RST_Pos) /*!< Reset BPWM1 \hideinitializer */ +#define EQEI0_RST ((8UL<<24) | SYS_IPRST2_EQEI0RST_Pos) /*!< Reset EQEI0 \hideinitializer */ +#define EQEI1_RST ((8UL<<24) | SYS_IPRST2_EQEI1RST_Pos) /*!< Reset EQEI1 \hideinitializer */ +#define EQEI2_RST ((8UL<<24) | SYS_IPRST2_EQEI2RST_Pos) /*!< Reset EQEI2 \hideinitializer */ +#define EQEI3_RST ((8UL<<24) | SYS_IPRST2_EQEI3RST_Pos) /*!< Reset EQEI3 \hideinitializer */ +#define ECAP0_RST ((8UL<<24) | SYS_IPRST2_ECAP0RST_Pos) /*!< Reset ECAP0 \hideinitializer */ +#define ECAP1_RST ((8UL<<24) | SYS_IPRST2_ECAP1RST_Pos) /*!< Reset ECAP1 \hideinitializer */ +#define ECAP2_RST ((8UL<<24) | SYS_IPRST2_ECAP2RST_Pos) /*!< Reset ECAP2 \hideinitializer */ +#define ECAP3_RST ((8UL<<24) | SYS_IPRST2_ECAP3RST_Pos) /*!< Reset ECAP3 \hideinitializer */ +#define I2S1_RST ((8UL<<24) | SYS_IPRST2_I2S1RST_Pos) /*!< Reset I2S1 \hideinitializer */ +#define EADC1_RST ((8UL<<24) | SYS_IPRST2_EADC1RST_Pos) /*!< Reset EADC1 \hideinitializer */ + +#define KPI_RST ((0x18UL<<24) | SYS_IPRST3_KPIRST_Pos) /*!< Reset KPI \hideinitializer */ +#define EADC2_RST ((0x18UL<<24) | SYS_IPRST3_EADC2RST_Pos) /*!< Reset EADC2 \hideinitializer */ +#define ACMP23_RST ((0x18UL<<24) | SYS_IPRST3_ACMP23RST_Pos) /*!< Reset ACMP23 \hideinitializer */ +#define SPI5_RST ((0x18UL<<24) | SYS_IPRST3_SPI5RST_Pos) /*!< Reset SPI5 \hideinitializer */ +#define SPI6_RST ((0x18UL<<24) | SYS_IPRST3_SPI6RST_Pos) /*!< Reset SPI6 \hideinitializer */ +#define SPI7_RST ((0x18UL<<24) | SYS_IPRST3_SPI7RST_Pos) /*!< Reset SPI7 \hideinitializer */ +#define SPI8_RST ((0x18UL<<24) | SYS_IPRST3_SPI8RST_Pos) /*!< Reset SPI8 \hideinitializer */ +#define SPI9_RST ((0x18UL<<24) | SYS_IPRST3_SPI9RST_Pos) /*!< Reset SPI9 \hideinitializer */ +#define SPI10_RST ((0x18UL<<24) | SYS_IPRST3_SPI10RST_Pos) /*!< Reset SPI10 \hideinitializer */ +#define UART8_RST ((0x18UL<<24) | SYS_IPRST3_UART8RST_Pos) /*!< Reset UART8 \hideinitializer */ +#define UART9_RST ((0x18UL<<24) | SYS_IPRST3_UART9RST_Pos) /*!< Reset UART9 \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable \hideinitializer */ +#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL << SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable \hideinitializer */ +#define SYS_BODCTL_BODVL_3_0V (7UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_8V (6UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_6V (5UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_4V (4UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_2V (3UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V \hideinitializer */ +#define SYS_BODCTL_BODVL_2_0V (2UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_8V (1UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V \hideinitializer */ +#define SYS_BODCTL_BODVL_1_6V (0UL << SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* VREFCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_VREFCTL_VREF_PIN (0x0UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin \hideinitializer */ +#define SYS_VREFCTL_VREF_1_6V (0x3UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_0V (0x7UL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V \hideinitializer */ +#define SYS_VREFCTL_VREF_2_5V (0xBUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V \hideinitializer */ +#define SYS_VREFCTL_VREF_3_0V (0xFUL << SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* USBPHY constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */ +#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL << SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */ +#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL << SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */ +#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBD (0x0UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_STD_USBH (0x1UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< Standard HSUSB host \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_ID_DEPH (0x2UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< ID dependent device \hideinitializer */ +#define SYS_USBPHY_HSUSBROLE_ON_THE_GO (0x3UL << SYS_USBPHY_HSUSBROLE_Pos) /*!< On-The-Go device \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* PLCTL constant definitions. (Write-Protection Register) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_PLCTL_PLSEL_PL0 (0x0UL<GPA_MFP0 = (SYS->GPA_MFP0 & (~SYS_GPA_MFP0_PA0MFP_Msk) ) | SYS_GPA_MFP0_PA0_MFP_SC0_CLK; +*/ + + +/* PA.0 MFP */ +#define SYS_GPA_MFP0_PA0MFP_GPIO (0x00UL<GPB_MFP0 = (SYS->GPB_MFP0 & (~ACMP0_N_PB3_Msk)) | ACMP0_N_PB3 /*!< Set PB3 function to ACMP0_N */ +#define SET_ACMP0_O_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~ACMP0_O_PB7_Msk)) | ACMP0_O_PB7 /*!< Set PB7 function to ACMP0_O */ +#define SET_ACMP0_O_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~ACMP0_O_PC1_Msk)) | ACMP0_O_PC1 /*!< Set PC1 function to ACMP0_O */ +#define SET_ACMP0_O_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~ACMP0_O_PC12_Msk)) | ACMP0_O_PC12 /*!< Set PC12 function to ACMP0_O */ +#define SET_ACMP0_O_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~ACMP0_O_PD6_Msk)) | ACMP0_O_PD6 /*!< Set PD6 function to ACMP0_O */ +#define SET_ACMP0_O_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~ACMP0_O_PF0_Msk)) | ACMP0_O_PF0 /*!< Set PF0 function to ACMP0_O */ +#define SET_ACMP0_P0_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~ACMP0_P0_PA11_Msk)) | ACMP0_P0_PA11 /*!< Set PA11 function to ACMP0_P0 */ +#define SET_ACMP0_P1_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~ACMP0_P1_PB2_Msk)) | ACMP0_P1_PB2 /*!< Set PB2 function to ACMP0_P1 */ +#define SET_ACMP0_P2_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ACMP0_P2_PB12_Msk)) | ACMP0_P2_PB12 /*!< Set PB12 function to ACMP0_P2 */ +#define SET_ACMP0_P3_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ACMP0_P3_PB13_Msk)) | ACMP0_P3_PB13 /*!< Set PB13 function to ACMP0_P3 */ +#define SET_ACMP0_WLAT_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~ACMP0_WLAT_PA7_Msk)) | ACMP0_WLAT_PA7 /*!< Set PA7 function to ACMP0_WLAT */ +#define SET_ACMP1_N_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~ACMP1_N_PB5_Msk)) | ACMP1_N_PB5 /*!< Set PB5 function to ACMP1_N */ +#define SET_ACMP1_O_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~ACMP1_O_PC0_Msk)) | ACMP1_O_PC0 /*!< Set PC0 function to ACMP1_O */ +#define SET_ACMP1_O_PD5() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~ACMP1_O_PD5_Msk)) | ACMP1_O_PD5 /*!< Set PD5 function to ACMP1_O */ +#define SET_ACMP1_O_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~ACMP1_O_PB6_Msk)) | ACMP1_O_PB6 /*!< Set PB6 function to ACMP1_O */ +#define SET_ACMP1_O_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~ACMP1_O_PC11_Msk)) | ACMP1_O_PC11 /*!< Set PC11 function to ACMP1_O */ +#define SET_ACMP1_O_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~ACMP1_O_PF1_Msk)) | ACMP1_O_PF1 /*!< Set PF1 function to ACMP1_O */ +#define SET_ACMP1_P0_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~ACMP1_P0_PA10_Msk)) | ACMP1_P0_PA10 /*!< Set PA10 function to ACMP1_P0 */ +#define SET_ACMP1_P1_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~ACMP1_P1_PB4_Msk)) | ACMP1_P1_PB4 /*!< Set PB4 function to ACMP1_P1 */ +#define SET_ACMP1_P2_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ACMP1_P2_PB12_Msk)) | ACMP1_P2_PB12 /*!< Set PB12 function to ACMP1_P2 */ +#define SET_ACMP1_P3_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ACMP1_P3_PB13_Msk)) | ACMP1_P3_PB13 /*!< Set PB13 function to ACMP1_P3 */ +#define SET_ACMP1_WLAT_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~ACMP1_WLAT_PA6_Msk)) | ACMP1_WLAT_PA6 /*!< Set PA6 function to ACMP1_WLAT */ +#define SET_ACMP2_N_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~ACMP2_N_PB6_Msk)) | ACMP2_N_PB6 /*!< Set PB6 function to ACMP2_N */ +#define SET_ACMP2_O_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~ACMP2_O_PB1_Msk)) | ACMP2_O_PB1 /*!< Set PB1 function to ACMP2_O */ +#define SET_ACMP2_O_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~ACMP2_O_PE7_Msk)) | ACMP2_O_PE7 /*!< Set PE7 function to ACMP2_O */ +#define SET_ACMP2_O_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~ACMP2_O_PF3_Msk)) | ACMP2_O_PF3 /*!< Set PF3 function to ACMP2_O */ +#define SET_ACMP2_P0_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~ACMP2_P0_PB7_Msk)) | ACMP2_P0_PB7 /*!< Set PB7 function to ACMP2_P0 */ +#define SET_ACMP2_P1_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~ACMP2_P1_PB8_Msk)) | ACMP2_P1_PB8 /*!< Set PB8 function to ACMP2_P1 */ +#define SET_ACMP2_P2_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~ACMP2_P2_PB9_Msk)) | ACMP2_P2_PB9 /*!< Set PB9 function to ACMP2_P2 */ +#define SET_ACMP2_P3_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~ACMP2_P3_PB10_Msk)) | ACMP2_P3_PB10 /*!< Set PB10 function to ACMP2_P3 */ +#define SET_ACMP2_WLAT_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~ACMP2_WLAT_PC7_Msk)) | ACMP2_WLAT_PC7 /*!< Set PC7 function to ACMP2_WLAT */ +#define SET_ACMP3_N_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~ACMP3_N_PB0_Msk)) | ACMP3_N_PB0 /*!< Set PB0 function to ACMP3_N */ +#define SET_ACMP3_O_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~ACMP3_O_PB0_Msk)) | ACMP3_O_PB0 /*!< Set PB0 function to ACMP3_O */ +#define SET_ACMP3_O_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~ACMP3_O_PF2_Msk)) | ACMP3_O_PF2 /*!< Set PF2 function to ACMP3_O */ +#define SET_ACMP3_O_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~ACMP3_O_PE6_Msk)) | ACMP3_O_PE6 /*!< Set PE6 function to ACMP3_O */ +#define SET_ACMP3_P0_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~ACMP3_P0_PB1_Msk)) | ACMP3_P0_PB1 /*!< Set PB1 function to ACMP3_P0 */ +#define SET_ACMP3_P1_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~ACMP3_P1_PC9_Msk)) | ACMP3_P1_PC9 /*!< Set PC9 function to ACMP3_P1 */ +#define SET_ACMP3_P2_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~ACMP3_P2_PC10_Msk)) | ACMP3_P2_PC10 /*!< Set PC10 function to ACMP3_P2 */ +#define SET_ACMP3_P3_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~ACMP3_P3_PC11_Msk)) | ACMP3_P3_PC11 /*!< Set PC11 function to ACMP3_P3 */ +#define SET_ACMP3_WLAT_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~ACMP3_WLAT_PC6_Msk)) | ACMP3_WLAT_PC6 /*!< Set PC6 function to ACMP3_WLAT */ +#define SET_BMC0_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~BMC0_PB5_Msk)) | BMC0_PB5 /*!< Set PB5 function to BMC0 */ +#define SET_BMC1_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~BMC1_PB4_Msk)) | BMC1_PB4 /*!< Set PB4 function to BMC1 */ +#define SET_BMC10_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~BMC10_PF5_Msk)) | BMC10_PF5 /*!< Set PF5 function to BMC10 */ +#define SET_BMC11_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~BMC11_PF4_Msk)) | BMC11_PF4 /*!< Set PF4 function to BMC11 */ +#define SET_BMC12_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BMC12_PA12_Msk)) | BMC12_PA12 /*!< Set PA12 function to BMC12 */ +#define SET_BMC12_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~BMC12_PF3_Msk)) | BMC12_PF3 /*!< Set PF3 function to BMC12 */ +#define SET_BMC13_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~BMC13_PF2_Msk)) | BMC13_PF2 /*!< Set PF2 function to BMC13 */ +#define SET_BMC13_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BMC13_PA13_Msk)) | BMC13_PA13 /*!< Set PA13 function to BMC13 */ +#define SET_BMC14_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~BMC14_PA7_Msk)) | BMC14_PA7 /*!< Set PA7 function to BMC14 */ +#define SET_BMC14_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BMC14_PA14_Msk)) | BMC14_PA14 /*!< Set PA14 function to BMC14 */ +#define SET_BMC15_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~BMC15_PA6_Msk)) | BMC15_PA6 /*!< Set PA6 function to BMC15 */ +#define SET_BMC15_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BMC15_PA15_Msk)) | BMC15_PA15 /*!< Set PA15 function to BMC15 */ +#define SET_BMC16_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BMC16_PA3_Msk)) | BMC16_PA3 /*!< Set PA3 function to BMC16 */ +#define SET_BMC16_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~BMC16_PG9_Msk)) | BMC16_PG9 /*!< Set PG9 function to BMC16 */ +#define SET_BMC17_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BMC17_PA2_Msk)) | BMC17_PA2 /*!< Set PA2 function to BMC17 */ +#define SET_BMC17_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~BMC17_PG10_Msk)) | BMC17_PG10 /*!< Set PG10 function to BMC17 */ +#define SET_BMC18_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BMC18_PA1_Msk)) | BMC18_PA1 /*!< Set PA1 function to BMC18 */ +#define SET_BMC18_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~BMC18_PG11_Msk)) | BMC18_PG11 /*!< Set PG11 function to BMC18 */ +#define SET_BMC19_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BMC19_PA0_Msk)) | BMC19_PA0 /*!< Set PA0 function to BMC19 */ +#define SET_BMC19_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~BMC19_PG12_Msk)) | BMC19_PG12 /*!< Set PG12 function to BMC19 */ +#define SET_BMC2_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~BMC2_PB3_Msk)) | BMC2_PB3 /*!< Set PB3 function to BMC2 */ +#define SET_BMC20_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BMC20_PB11_Msk)) | BMC20_PB11 /*!< Set PB11 function to BMC20 */ +#define SET_BMC20_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~BMC20_PC5_Msk)) | BMC20_PC5 /*!< Set PC5 function to BMC20 */ +#define SET_BMC21_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~BMC21_PC4_Msk)) | BMC21_PC4 /*!< Set PC4 function to BMC21 */ +#define SET_BMC21_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BMC21_PB10_Msk)) | BMC21_PB10 /*!< Set PB10 function to BMC21 */ +#define SET_BMC22_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BMC22_PB9_Msk)) | BMC22_PB9 /*!< Set PB9 function to BMC22 */ +#define SET_BMC22_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~BMC22_PC3_Msk)) | BMC22_PC3 /*!< Set PC3 function to BMC22 */ +#define SET_BMC23_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~BMC23_PC2_Msk)) | BMC23_PC2 /*!< Set PC2 function to BMC23 */ +#define SET_BMC23_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BMC23_PB8_Msk)) | BMC23_PB8 /*!< Set PB8 function to BMC23 */ +#define SET_BMC24_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~BMC24_PC1_Msk)) | BMC24_PC1 /*!< Set PC1 function to BMC24 */ +#define SET_BMC24_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~BMC24_PC7_Msk)) | BMC24_PC7 /*!< Set PC7 function to BMC24 */ +#define SET_BMC25_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~BMC25_PC6_Msk)) | BMC25_PC6 /*!< Set PC6 function to BMC25 */ +#define SET_BMC25_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~BMC25_PC0_Msk)) | BMC25_PC0 /*!< Set PC0 function to BMC25 */ +#define SET_BMC26_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~BMC26_PC14_Msk)) | BMC26_PC14 /*!< Set PC14 function to BMC26 */ +#define SET_BMC27_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~BMC27_PB15_Msk)) | BMC27_PB15 /*!< Set PB15 function to BMC27 */ +#define SET_BMC28_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~BMC28_PB13_Msk)) | BMC28_PB13 /*!< Set PB13 function to BMC28 */ +#define SET_BMC29_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~BMC29_PB12_Msk)) | BMC29_PB12 /*!< Set PB12 function to BMC29 */ +#define SET_BMC3_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~BMC3_PB2_Msk)) | BMC3_PB2 /*!< Set PB2 function to BMC3 */ +#define SET_BMC30_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~BMC30_PB7_Msk)) | BMC30_PB7 /*!< Set PB7 function to BMC30 */ +#define SET_BMC31_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~BMC31_PB6_Msk)) | BMC31_PB6 /*!< Set PB6 function to BMC31 */ +#define SET_BMC4_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~BMC4_PB1_Msk)) | BMC4_PB1 /*!< Set PB1 function to BMC4 */ +#define SET_BMC5_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~BMC5_PB0_Msk)) | BMC5_PB0 /*!< Set PB0 function to BMC5 */ +#define SET_BMC6_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BMC6_PA11_Msk)) | BMC6_PA11 /*!< Set PA11 function to BMC6 */ +#define SET_BMC7_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BMC7_PA10_Msk)) | BMC7_PA10 /*!< Set PA10 function to BMC7 */ +#define SET_BMC8_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BMC8_PA9_Msk)) | BMC8_PA9 /*!< Set PA9 function to BMC8 */ +#define SET_BMC9_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BMC9_PA8_Msk)) | BMC9_PA8 /*!< Set PA8 function to BMC9 */ +#define SET_BPWM0_CH0_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~BPWM0_CH0_PD13_Msk)) | BPWM0_CH0_PD13 /*!< Set PD13 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~BPWM0_CH0_PE2_Msk)) | BPWM0_CH0_PE2 /*!< Set PE2 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BPWM0_CH0_PA0_Msk)) | BPWM0_CH0_PA0 /*!< Set PA0 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BPWM0_CH0_PA11_Msk)) | BPWM0_CH0_PA11 /*!< Set PA11 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PG14() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~BPWM0_CH0_PG14_Msk)) | BPWM0_CH0_PG14 /*!< Set PG14 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PJ13() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~BPWM0_CH0_PJ13_Msk)) | BPWM0_CH0_PJ13 /*!< Set PJ13 function to BPWM0_CH0 */ +#define SET_BPWM0_CH1_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~BPWM0_CH1_PE3_Msk)) | BPWM0_CH1_PE3 /*!< Set PE3 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~BPWM0_CH1_PG13_Msk)) | BPWM0_CH1_PG13 /*!< Set PG13 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BPWM0_CH1_PA1_Msk)) | BPWM0_CH1_PA1 /*!< Set PA1 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~BPWM0_CH1_PJ12_Msk)) | BPWM0_CH1_PJ12 /*!< Set PJ12 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BPWM0_CH1_PA10_Msk)) | BPWM0_CH1_PA10 /*!< Set PA10 function to BPWM0_CH1 */ +#define SET_BPWM0_CH2_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BPWM0_CH2_PA9_Msk)) | BPWM0_CH2_PA9 /*!< Set PA9 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BPWM0_CH2_PA2_Msk)) | BPWM0_CH2_PA2 /*!< Set PA2 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~BPWM0_CH2_PJ11_Msk)) | BPWM0_CH2_PJ11 /*!< Set PJ11 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~BPWM0_CH2_PE4_Msk)) | BPWM0_CH2_PE4 /*!< Set PE4 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~BPWM0_CH2_PG12_Msk)) | BPWM0_CH2_PG12 /*!< Set PG12 function to BPWM0_CH2 */ +#define SET_BPWM0_CH3_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~BPWM0_CH3_PE5_Msk)) | BPWM0_CH3_PE5 /*!< Set PE5 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~BPWM0_CH3_PJ10_Msk)) | BPWM0_CH3_PJ10 /*!< Set PJ10 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~BPWM0_CH3_PG11_Msk)) | BPWM0_CH3_PG11 /*!< Set PG11 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~BPWM0_CH3_PA8_Msk)) | BPWM0_CH3_PA8 /*!< Set PA8 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~BPWM0_CH3_PA3_Msk)) | BPWM0_CH3_PA3 /*!< Set PA3 function to BPWM0_CH3 */ +#define SET_BPWM0_CH4_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~BPWM0_CH4_PF5_Msk)) | BPWM0_CH4_PF5 /*!< Set PF5 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PJ9() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~BPWM0_CH4_PJ9_Msk)) | BPWM0_CH4_PJ9 /*!< Set PJ9 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~BPWM0_CH4_PG10_Msk)) | BPWM0_CH4_PG10 /*!< Set PG10 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~BPWM0_CH4_PC13_Msk)) | BPWM0_CH4_PC13 /*!< Set PC13 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~BPWM0_CH4_PA4_Msk)) | BPWM0_CH4_PA4 /*!< Set PA4 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~BPWM0_CH4_PE6_Msk)) | BPWM0_CH4_PE6 /*!< Set PE6 function to BPWM0_CH4 */ +#define SET_BPWM0_CH5_PJ8() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~BPWM0_CH5_PJ8_Msk)) | BPWM0_CH5_PJ8 /*!< Set PJ8 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~BPWM0_CH5_PD12_Msk)) | BPWM0_CH5_PD12 /*!< Set PD12 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~BPWM0_CH5_PA5_Msk)) | BPWM0_CH5_PA5 /*!< Set PA5 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~BPWM0_CH5_PF4_Msk)) | BPWM0_CH5_PF4 /*!< Set PF4 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~BPWM0_CH5_PE7_Msk)) | BPWM0_CH5_PE7 /*!< Set PE7 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~BPWM0_CH5_PG9_Msk)) | BPWM0_CH5_PG9 /*!< Set PG9 function to BPWM0_CH5 */ +#define SET_BPWM1_CH0_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~BPWM1_CH0_PF3_Msk)) | BPWM1_CH0_PF3 /*!< Set PF3 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BPWM1_CH0_PB11_Msk)) | BPWM1_CH0_PB11 /*!< Set PB11 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~BPWM1_CH0_PC7_Msk)) | BPWM1_CH0_PC7 /*!< Set PC7 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~BPWM1_CH0_PF0_Msk)) | BPWM1_CH0_PF0 /*!< Set PF0 function to BPWM1_CH0 */ +#define SET_BPWM1_CH1_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~BPWM1_CH1_PF1_Msk)) | BPWM1_CH1_PF1 /*!< Set PF1 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BPWM1_CH1_PB10_Msk)) | BPWM1_CH1_PB10 /*!< Set PB10 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~BPWM1_CH1_PF2_Msk)) | BPWM1_CH1_PF2 /*!< Set PF2 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~BPWM1_CH1_PC6_Msk)) | BPWM1_CH1_PC6 /*!< Set PC6 function to BPWM1_CH1 */ +#define SET_BPWM1_CH2_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BPWM1_CH2_PB9_Msk)) | BPWM1_CH2_PB9 /*!< Set PB9 function to BPWM1_CH2 */ +#define SET_BPWM1_CH2_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~BPWM1_CH2_PA7_Msk)) | BPWM1_CH2_PA7 /*!< Set PA7 function to BPWM1_CH2 */ +#define SET_BPWM1_CH2_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BPWM1_CH2_PA12_Msk)) | BPWM1_CH2_PA12 /*!< Set PA12 function to BPWM1_CH2 */ +#define SET_BPWM1_CH3_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~BPWM1_CH3_PA6_Msk)) | BPWM1_CH3_PA6 /*!< Set PA6 function to BPWM1_CH3 */ +#define SET_BPWM1_CH3_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~BPWM1_CH3_PB8_Msk)) | BPWM1_CH3_PB8 /*!< Set PB8 function to BPWM1_CH3 */ +#define SET_BPWM1_CH3_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BPWM1_CH3_PA13_Msk)) | BPWM1_CH3_PA13 /*!< Set PA13 function to BPWM1_CH3 */ +#define SET_BPWM1_CH4_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~BPWM1_CH4_PB7_Msk)) | BPWM1_CH4_PB7 /*!< Set PB7 function to BPWM1_CH4 */ +#define SET_BPWM1_CH4_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~BPWM1_CH4_PC8_Msk)) | BPWM1_CH4_PC8 /*!< Set PC8 function to BPWM1_CH4 */ +#define SET_BPWM1_CH4_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BPWM1_CH4_PA14_Msk)) | BPWM1_CH4_PA14 /*!< Set PA14 function to BPWM1_CH4 */ +#define SET_BPWM1_CH5_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~BPWM1_CH5_PB6_Msk)) | BPWM1_CH5_PB6 /*!< Set PB6 function to BPWM1_CH5 */ +#define SET_BPWM1_CH5_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~BPWM1_CH5_PE13_Msk)) | BPWM1_CH5_PE13 /*!< Set PE13 function to BPWM1_CH5 */ +#define SET_BPWM1_CH5_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~BPWM1_CH5_PA15_Msk)) | BPWM1_CH5_PA15 /*!< Set PA15 function to BPWM1_CH5 */ +#define SET_CAN0_RXD_PI13() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~CAN0_RXD_PI13_Msk)) | CAN0_RXD_PI13 /*!< Set PI13 function to CAN0_RXD */ +#define SET_CAN0_RXD_PJ3() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~CAN0_RXD_PJ3_Msk)) | CAN0_RXD_PJ3 /*!< Set PJ3 function to CAN0_RXD */ +#define SET_CAN0_RXD_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~CAN0_RXD_PA4_Msk)) | CAN0_RXD_PA4 /*!< Set PA4 function to CAN0_RXD */ +#define SET_CAN0_RXD_PE15() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~CAN0_RXD_PE15_Msk)) | CAN0_RXD_PE15 /*!< Set PE15 function to CAN0_RXD */ +#define SET_CAN0_RXD_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~CAN0_RXD_PA13_Msk)) | CAN0_RXD_PA13 /*!< Set PA13 function to CAN0_RXD */ +#define SET_CAN0_RXD_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~CAN0_RXD_PJ11_Msk)) | CAN0_RXD_PJ11 /*!< Set PJ11 function to CAN0_RXD */ +#define SET_CAN0_RXD_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~CAN0_RXD_PC4_Msk)) | CAN0_RXD_PC4 /*!< Set PC4 function to CAN0_RXD */ +#define SET_CAN0_RXD_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~CAN0_RXD_PB10_Msk)) | CAN0_RXD_PB10 /*!< Set PB10 function to CAN0_RXD */ +#define SET_CAN0_RXD_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~CAN0_RXD_PD10_Msk)) | CAN0_RXD_PD10 /*!< Set PD10 function to CAN0_RXD */ +#define SET_CAN0_TXD_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~CAN0_TXD_PC5_Msk)) | CAN0_TXD_PC5 /*!< Set PC5 function to CAN0_TXD */ +#define SET_CAN0_TXD_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~CAN0_TXD_PB11_Msk)) | CAN0_TXD_PB11 /*!< Set PB11 function to CAN0_TXD */ +#define SET_CAN0_TXD_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~CAN0_TXD_PA5_Msk)) | CAN0_TXD_PA5 /*!< Set PA5 function to CAN0_TXD */ +#define SET_CAN0_TXD_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~CAN0_TXD_PJ10_Msk)) | CAN0_TXD_PJ10 /*!< Set PJ10 function to CAN0_TXD */ +#define SET_CAN0_TXD_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~CAN0_TXD_PD11_Msk)) | CAN0_TXD_PD11 /*!< Set PD11 function to CAN0_TXD */ +#define SET_CAN0_TXD_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~CAN0_TXD_PA12_Msk)) | CAN0_TXD_PA12 /*!< Set PA12 function to CAN0_TXD */ +#define SET_CAN0_TXD_PI12() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~CAN0_TXD_PI12_Msk)) | CAN0_TXD_PI12 /*!< Set PI12 function to CAN0_TXD */ +#define SET_CAN0_TXD_PE14() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~CAN0_TXD_PE14_Msk)) | CAN0_TXD_PE14 /*!< Set PE14 function to CAN0_TXD */ +#define SET_CAN0_TXD_PJ2() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~CAN0_TXD_PJ2_Msk)) | CAN0_TXD_PJ2 /*!< Set PJ2 function to CAN0_TXD */ +#define SET_CAN1_RXD_PJ5() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CAN1_RXD_PJ5_Msk)) | CAN1_RXD_PJ5 /*!< Set PJ5 function to CAN1_RXD */ +#define SET_CAN1_RXD_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~CAN1_RXD_PC9_Msk)) | CAN1_RXD_PC9 /*!< Set PC9 function to CAN1_RXD */ +#define SET_CAN1_RXD_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~CAN1_RXD_PD12_Msk)) | CAN1_RXD_PD12 /*!< Set PD12 function to CAN1_RXD */ +#define SET_CAN1_RXD_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CAN1_RXD_PF8_Msk)) | CAN1_RXD_PF8 /*!< Set PF8 function to CAN1_RXD */ +#define SET_CAN1_RXD_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~CAN1_RXD_PG1_Msk)) | CAN1_RXD_PG1 /*!< Set PG1 function to CAN1_RXD */ +#define SET_CAN1_RXD_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~CAN1_RXD_PB6_Msk)) | CAN1_RXD_PB6 /*!< Set PB6 function to CAN1_RXD */ +#define SET_CAN1_RXD_PI15() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~CAN1_RXD_PI15_Msk)) | CAN1_RXD_PI15 /*!< Set PI15 function to CAN1_RXD */ +#define SET_CAN1_RXD_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CAN1_RXD_PC2_Msk)) | CAN1_RXD_PC2 /*!< Set PC2 function to CAN1_RXD */ +#define SET_CAN1_RXD_PJ13() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~CAN1_RXD_PJ13_Msk)) | CAN1_RXD_PJ13 /*!< Set PJ13 function to CAN1_RXD */ +#define SET_CAN1_RXD_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~CAN1_RXD_PE6_Msk)) | CAN1_RXD_PE6 /*!< Set PE6 function to CAN1_RXD */ +#define SET_CAN1_TXD_PG0() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~CAN1_TXD_PG0_Msk)) | CAN1_TXD_PG0 /*!< Set PG0 function to CAN1_TXD */ +#define SET_CAN1_TXD_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~CAN1_TXD_PB7_Msk)) | CAN1_TXD_PB7 /*!< Set PB7 function to CAN1_TXD */ +#define SET_CAN1_TXD_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CAN1_TXD_PC3_Msk)) | CAN1_TXD_PC3 /*!< Set PC3 function to CAN1_TXD */ +#define SET_CAN1_TXD_PI14() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~CAN1_TXD_PI14_Msk)) | CAN1_TXD_PI14 /*!< Set PI14 function to CAN1_TXD */ +#define SET_CAN1_TXD_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~CAN1_TXD_PC10_Msk)) | CAN1_TXD_PC10 /*!< Set PC10 function to CAN1_TXD */ +#define SET_CAN1_TXD_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~CAN1_TXD_PE7_Msk)) | CAN1_TXD_PE7 /*!< Set PE7 function to CAN1_TXD */ +#define SET_CAN1_TXD_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~CAN1_TXD_PJ12_Msk)) | CAN1_TXD_PJ12 /*!< Set PJ12 function to CAN1_TXD */ +#define SET_CAN1_TXD_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~CAN1_TXD_PC13_Msk)) | CAN1_TXD_PC13 /*!< Set PC13 function to CAN1_TXD */ +#define SET_CAN1_TXD_PJ4() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CAN1_TXD_PJ4_Msk)) | CAN1_TXD_PJ4 /*!< Set PJ4 function to CAN1_TXD */ +#define SET_CAN1_TXD_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CAN1_TXD_PF9_Msk)) | CAN1_TXD_PF9 /*!< Set PF9 function to CAN1_TXD */ +#define SET_CAN2_RXD_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~CAN2_RXD_PF1_Msk)) | CAN2_RXD_PF1 /*!< Set PF1 function to CAN2_RXD */ +#define SET_CAN2_RXD_PJ1() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~CAN2_RXD_PJ1_Msk)) | CAN2_RXD_PJ1 /*!< Set PJ1 function to CAN2_RXD */ +#define SET_CAN2_RXD_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~CAN2_RXD_PF6_Msk)) | CAN2_RXD_PF6 /*!< Set PF6 function to CAN2_RXD */ +#define SET_CAN2_RXD_PI9() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~CAN2_RXD_PI9_Msk)) | CAN2_RXD_PI9 /*!< Set PI9 function to CAN2_RXD */ +#define SET_CAN2_RXD_PD8() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~CAN2_RXD_PD8_Msk)) | CAN2_RXD_PD8 /*!< Set PD8 function to CAN2_RXD */ +#define SET_CAN2_RXD_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~CAN2_RXD_PB8_Msk)) | CAN2_RXD_PB8 /*!< Set PB8 function to CAN2_RXD */ +#define SET_CAN2_RXD_PJ7() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CAN2_RXD_PJ7_Msk)) | CAN2_RXD_PJ7 /*!< Set PJ7 function to CAN2_RXD */ +#define SET_CAN2_RXD_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CAN2_RXD_PC0_Msk)) | CAN2_RXD_PC0 /*!< Set PC0 function to CAN2_RXD */ +#define SET_CAN2_RXD_PJ9() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~CAN2_RXD_PJ9_Msk)) | CAN2_RXD_PJ9 /*!< Set PJ9 function to CAN2_RXD */ +#define SET_CAN2_TXD_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~CAN2_TXD_PB9_Msk)) | CAN2_TXD_PB9 /*!< Set PB9 function to CAN2_TXD */ +#define SET_CAN2_TXD_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CAN2_TXD_PC1_Msk)) | CAN2_TXD_PC1 /*!< Set PC1 function to CAN2_TXD */ +#define SET_CAN2_TXD_PD9() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~CAN2_TXD_PD9_Msk)) | CAN2_TXD_PD9 /*!< Set PD9 function to CAN2_TXD */ +#define SET_CAN2_TXD_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~CAN2_TXD_PF0_Msk)) | CAN2_TXD_PF0 /*!< Set PF0 function to CAN2_TXD */ +#define SET_CAN2_TXD_PJ6() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CAN2_TXD_PJ6_Msk)) | CAN2_TXD_PJ6 /*!< Set PJ6 function to CAN2_TXD */ +#define SET_CAN2_TXD_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~CAN2_TXD_PF7_Msk)) | CAN2_TXD_PF7 /*!< Set PF7 function to CAN2_TXD */ +#define SET_CAN2_TXD_PJ8() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~CAN2_TXD_PJ8_Msk)) | CAN2_TXD_PJ8 /*!< Set PJ8 function to CAN2_TXD */ +#define SET_CAN2_TXD_PJ0() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~CAN2_TXD_PJ0_Msk)) | CAN2_TXD_PJ0 /*!< Set PJ0 function to CAN2_TXD */ +#define SET_CAN2_TXD_PI8() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~CAN2_TXD_PI8_Msk)) | CAN2_TXD_PI8 /*!< Set PI8 function to CAN2_TXD */ +#define SET_CAN3_RXD_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~CAN3_RXD_PC6_Msk)) | CAN3_RXD_PC6 /*!< Set PC6 function to CAN3_RXD */ +#define SET_CAN3_RXD_PH13() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~CAN3_RXD_PH13_Msk)) | CAN3_RXD_PH13 /*!< Set PH13 function to CAN3_RXD */ +#define SET_CAN3_RXD_PI7() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~CAN3_RXD_PI7_Msk)) | CAN3_RXD_PI7 /*!< Set PI7 function to CAN3_RXD */ +#define SET_CAN3_RXD_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CAN3_RXD_PF10_Msk)) | CAN3_RXD_PF10 /*!< Set PF10 function to CAN3_RXD */ +#define SET_CAN3_RXD_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~CAN3_RXD_PB12_Msk)) | CAN3_RXD_PB12 /*!< Set PB12 function to CAN3_RXD */ +#define SET_CAN3_RXD_PI11() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~CAN3_RXD_PI11_Msk)) | CAN3_RXD_PI11 /*!< Set PI11 function to CAN3_RXD */ +#define SET_CAN3_TXD_PI6() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~CAN3_TXD_PI6_Msk)) | CAN3_TXD_PI6 /*!< Set PI6 function to CAN3_TXD */ +#define SET_CAN3_TXD_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~CAN3_TXD_PC7_Msk)) | CAN3_TXD_PC7 /*!< Set PC7 function to CAN3_TXD */ +#define SET_CAN3_TXD_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~CAN3_TXD_PB13_Msk)) | CAN3_TXD_PB13 /*!< Set PB13 function to CAN3_TXD */ +#define SET_CAN3_TXD_PH12() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~CAN3_TXD_PH12_Msk)) | CAN3_TXD_PH12 /*!< Set PH12 function to CAN3_TXD */ +#define SET_CAN3_TXD_PI10() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~CAN3_TXD_PI10_Msk)) | CAN3_TXD_PI10 /*!< Set PI10 function to CAN3_TXD */ +#define SET_CAN3_TXD_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CAN3_TXD_PF11_Msk)) | CAN3_TXD_PF11 /*!< Set PF11 function to CAN3_TXD */ +#define SET_CCAP_DATA0_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~CCAP_DATA0_PB14_Msk)) | CCAP_DATA0_PB14 /*!< Set PB14 function to CCAP_DATA0 */ +#define SET_CCAP_DATA0_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CCAP_DATA0_PC0_Msk)) | CCAP_DATA0_PC0 /*!< Set PC0 function to CCAP_DATA0 */ +#define SET_CCAP_DATA0_PJ7() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CCAP_DATA0_PJ7_Msk)) | CCAP_DATA0_PJ7 /*!< Set PJ7 function to CCAP_DATA0 */ +#define SET_CCAP_DATA0_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~CCAP_DATA0_PF7_Msk)) | CCAP_DATA0_PF7 /*!< Set PF7 function to CCAP_DATA0 */ +#define SET_CCAP_DATA1_PJ6() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CCAP_DATA1_PJ6_Msk)) | CCAP_DATA1_PJ6 /*!< Set PJ6 function to CCAP_DATA1 */ +#define SET_CCAP_DATA1_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~CCAP_DATA1_PB15_Msk)) | CCAP_DATA1_PB15 /*!< Set PB15 function to CCAP_DATA1 */ +#define SET_CCAP_DATA1_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CCAP_DATA1_PC1_Msk)) | CCAP_DATA1_PC1 /*!< Set PC1 function to CCAP_DATA1 */ +#define SET_CCAP_DATA1_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CCAP_DATA1_PF8_Msk)) | CCAP_DATA1_PF8 /*!< Set PF8 function to CCAP_DATA1 */ +#define SET_CCAP_DATA2_PJ5() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CCAP_DATA2_PJ5_Msk)) | CCAP_DATA2_PJ5 /*!< Set PJ5 function to CCAP_DATA2 */ +#define SET_CCAP_DATA2_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CCAP_DATA2_PC2_Msk)) | CCAP_DATA2_PC2 /*!< Set PC2 function to CCAP_DATA2 */ +#define SET_CCAP_DATA2_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CCAP_DATA2_PF9_Msk)) | CCAP_DATA2_PF9 /*!< Set PF9 function to CCAP_DATA2 */ +#define SET_CCAP_DATA3_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CCAP_DATA3_PF10_Msk)) | CCAP_DATA3_PF10 /*!< Set PF10 function to CCAP_DATA3 */ +#define SET_CCAP_DATA3_PJ4() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~CCAP_DATA3_PJ4_Msk)) | CCAP_DATA3_PJ4 /*!< Set PJ4 function to CCAP_DATA3 */ +#define SET_CCAP_DATA3_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~CCAP_DATA3_PC3_Msk)) | CCAP_DATA3_PC3 /*!< Set PC3 function to CCAP_DATA3 */ +#define SET_CCAP_DATA4_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~CCAP_DATA4_PC4_Msk)) | CCAP_DATA4_PC4 /*!< Set PC4 function to CCAP_DATA4 */ +#define SET_CCAP_DATA4_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~CCAP_DATA4_PF11_Msk)) | CCAP_DATA4_PF11 /*!< Set PF11 function to CCAP_DATA4 */ +#define SET_CCAP_DATA4_PJ3() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~CCAP_DATA4_PJ3_Msk)) | CCAP_DATA4_PJ3 /*!< Set PJ3 function to CCAP_DATA4 */ +#define SET_CCAP_DATA5_PJ2() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~CCAP_DATA5_PJ2_Msk)) | CCAP_DATA5_PJ2 /*!< Set PJ2 function to CCAP_DATA5 */ +#define SET_CCAP_DATA5_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~CCAP_DATA5_PC5_Msk)) | CCAP_DATA5_PC5 /*!< Set PC5 function to CCAP_DATA5 */ +#define SET_CCAP_DATA5_PG4() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~CCAP_DATA5_PG4_Msk)) | CCAP_DATA5_PG4 /*!< Set PG4 function to CCAP_DATA5 */ +#define SET_CCAP_DATA6_PG3() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~CCAP_DATA6_PG3_Msk)) | CCAP_DATA6_PG3 /*!< Set PG3 function to CCAP_DATA6 */ +#define SET_CCAP_DATA6_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~CCAP_DATA6_PA0_Msk)) | CCAP_DATA6_PA0 /*!< Set PA0 function to CCAP_DATA6 */ +#define SET_CCAP_DATA7_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~CCAP_DATA7_PA1_Msk)) | CCAP_DATA7_PA1 /*!< Set PA1 function to CCAP_DATA7 */ +#define SET_CCAP_DATA7_PG2() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~CCAP_DATA7_PG2_Msk)) | CCAP_DATA7_PG2 /*!< Set PG2 function to CCAP_DATA7 */ +#define SET_CCAP_HSYNC_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~CCAP_HSYNC_PD7_Msk)) | CCAP_HSYNC_PD7 /*!< Set PD7 function to CCAP_HSYNC */ +#define SET_CCAP_HSYNC_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~CCAP_HSYNC_PG13_Msk)) | CCAP_HSYNC_PG13 /*!< Set PG13 function to CCAP_HSYNC */ +#define SET_CCAP_HSYNC_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~CCAP_HSYNC_PB9_Msk)) | CCAP_HSYNC_PB9 /*!< Set PB9 function to CCAP_HSYNC */ +#define SET_CCAP_PIXCLK_PH12() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~CCAP_PIXCLK_PH12_Msk)) | CCAP_PIXCLK_PH12 /*!< Set PH12 function to CCAP_PIXCLK */ +#define SET_CCAP_PIXCLK_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~CCAP_PIXCLK_PG9_Msk)) | CCAP_PIXCLK_PG9 /*!< Set PG9 function to CCAP_PIXCLK */ +#define SET_CCAP_PIXCLK_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~CCAP_PIXCLK_PB13_Msk)) | CCAP_PIXCLK_PB13 /*!< Set PB13 function to CCAP_PIXCLK */ +#define SET_CCAP_SCLK_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~CCAP_SCLK_PG10_Msk)) | CCAP_SCLK_PG10 /*!< Set PG10 function to CCAP_SCLK */ +#define SET_CCAP_SCLK_PH13() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~CCAP_SCLK_PH13_Msk)) | CCAP_SCLK_PH13 /*!< Set PH13 function to CCAP_SCLK */ +#define SET_CCAP_SCLK_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~CCAP_SCLK_PB12_Msk)) | CCAP_SCLK_PB12 /*!< Set PB12 function to CCAP_SCLK */ +#define SET_CCAP_SFIELD_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~CCAP_SFIELD_PG11_Msk)) | CCAP_SFIELD_PG11 /*!< Set PG11 function to CCAP_SFIELD */ +#define SET_CCAP_SFIELD_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~CCAP_SFIELD_PB11_Msk)) | CCAP_SFIELD_PB11 /*!< Set PB11 function to CCAP_SFIELD */ +#define SET_CCAP_SFIELD_PH14() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~CCAP_SFIELD_PH14_Msk)) | CCAP_SFIELD_PH14 /*!< Set PH14 function to CCAP_SFIELD */ +#define SET_CCAP_VSYNC_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~CCAP_VSYNC_PG12_Msk)) | CCAP_VSYNC_PG12 /*!< Set PG12 function to CCAP_VSYNC */ +#define SET_CCAP_VSYNC_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~CCAP_VSYNC_PB10_Msk)) | CCAP_VSYNC_PB10 /*!< Set PB10 function to CCAP_VSYNC */ +#define SET_CCAP_VSYNC_PH15() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~CCAP_VSYNC_PH15_Msk)) | CCAP_VSYNC_PH15 /*!< Set PH15 function to CCAP_VSYNC */ +#define SET_CLKO_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~CLKO_PC13_Msk)) | CLKO_PC13 /*!< Set PC13 function to CLKO */ +#define SET_CLKO_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~CLKO_PD13_Msk)) | CLKO_PD13 /*!< Set PD13 function to CLKO */ +#define SET_CLKO_PG15() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~CLKO_PG15_Msk)) | CLKO_PG15 /*!< Set PG15 function to CLKO */ +#define SET_CLKO_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~CLKO_PB14_Msk)) | CLKO_PB14 /*!< Set PB14 function to CLKO */ +#define SET_CLKO_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~CLKO_PD12_Msk)) | CLKO_PD12 /*!< Set PD12 function to CLKO */ +#define SET_DAC0_OUT_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12 /*!< Set PB12 function to DAC0_OUT */ +#define SET_DAC0_ST_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~DAC0_ST_PA0_Msk)) | DAC0_ST_PA0 /*!< Set PA0 function to DAC0_ST */ +#define SET_DAC0_ST_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~DAC0_ST_PA10_Msk)) | DAC0_ST_PA10 /*!< Set PA10 function to DAC0_ST */ +#define SET_DAC1_OUT_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13 /*!< Set PB13 function to DAC1_OUT */ +#define SET_DAC1_ST_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~DAC1_ST_PA11_Msk)) | DAC1_ST_PA11 /*!< Set PA11 function to DAC1_ST */ +#define SET_DAC1_ST_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~DAC1_ST_PA1_Msk)) | DAC1_ST_PA1 /*!< Set PA1 function to DAC1_ST */ +#define SET_EADC0_CH0_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC0_CH0_PB0_Msk)) | EADC0_CH0_PB0 /*!< Set PB0 function to EADC0_CH0 */ +#define SET_EADC0_CH1_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC0_CH1_PB1_Msk)) | EADC0_CH1_PB1 /*!< Set PB1 function to EADC0_CH1 */ +#define SET_EADC0_CH10_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EADC0_CH10_PB10_Msk)) | EADC0_CH10_PB10 /*!< Set PB10 function to EADC0_CH10 */ +#define SET_EADC0_CH11_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EADC0_CH11_PB11_Msk)) | EADC0_CH11_PB11 /*!< Set PB11 function to EADC0_CH11 */ +#define SET_EADC0_CH12_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC0_CH12_PB12_Msk)) | EADC0_CH12_PB12 /*!< Set PB12 function to EADC0_CH12 */ +#define SET_EADC0_CH13_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC0_CH13_PB13_Msk)) | EADC0_CH13_PB13 /*!< Set PB13 function to EADC0_CH13 */ +#define SET_EADC0_CH14_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC0_CH14_PB14_Msk)) | EADC0_CH14_PB14 /*!< Set PB14 function to EADC0_CH14 */ +#define SET_EADC0_CH15_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC0_CH15_PB15_Msk)) | EADC0_CH15_PB15 /*!< Set PB15 function to EADC0_CH15 */ +#define SET_EADC0_CH2_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC0_CH2_PB2_Msk)) | EADC0_CH2_PB2 /*!< Set PB2 function to EADC0_CH2 */ +#define SET_EADC0_CH3_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC0_CH3_PB3_Msk)) | EADC0_CH3_PB3 /*!< Set PB3 function to EADC0_CH3 */ +#define SET_EADC0_CH4_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EADC0_CH4_PB4_Msk)) | EADC0_CH4_PB4 /*!< Set PB4 function to EADC0_CH4 */ +#define SET_EADC0_CH5_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EADC0_CH5_PB5_Msk)) | EADC0_CH5_PB5 /*!< Set PB5 function to EADC0_CH5 */ +#define SET_EADC0_CH6_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EADC0_CH6_PB6_Msk)) | EADC0_CH6_PB6 /*!< Set PB6 function to EADC0_CH6 */ +#define SET_EADC0_CH7_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EADC0_CH7_PB7_Msk)) | EADC0_CH7_PB7 /*!< Set PB7 function to EADC0_CH7 */ +#define SET_EADC0_CH8_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EADC0_CH8_PB8_Msk)) | EADC0_CH8_PB8 /*!< Set PB8 function to EADC0_CH8 */ +#define SET_EADC0_CH9_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EADC0_CH9_PB9_Msk)) | EADC0_CH9_PB9 /*!< Set PB9 function to EADC0_CH9 */ +#define SET_EADC0_ST_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~EADC0_ST_PF0_Msk)) | EADC0_ST_PF0 /*!< Set PF0 function to EADC0_ST */ +#define SET_EADC0_ST_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EADC0_ST_PD12_Msk)) | EADC0_ST_PD12 /*!< Set PD12 function to EADC0_ST */ +#define SET_EADC0_ST_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~EADC0_ST_PD6_Msk)) | EADC0_ST_PD6 /*!< Set PD6 function to EADC0_ST */ +#define SET_EADC0_ST_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EADC0_ST_PC1_Msk)) | EADC0_ST_PC1 /*!< Set PC1 function to EADC0_ST */ +#define SET_EADC0_ST_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EADC0_ST_PF5_Msk)) | EADC0_ST_PF5 /*!< Set PF5 function to EADC0_ST */ +#define SET_EADC0_ST_PG15() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~EADC0_ST_PG15_Msk)) | EADC0_ST_PG15 /*!< Set PG15 function to EADC0_ST */ +#define SET_EADC0_ST_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EADC0_ST_PD13_Msk)) | EADC0_ST_PD13 /*!< Set PD13 function to EADC0_ST */ +#define SET_EADC0_ST_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EADC0_ST_PC13_Msk)) | EADC0_ST_PC13 /*!< Set PC13 function to EADC0_ST */ +#define SET_EADC1_CH0_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EADC1_CH0_PD10_Msk)) | EADC1_CH0_PD10 /*!< Set PD10 function to EADC1_CH0 */ +#define SET_EADC1_CH1_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EADC1_CH1_PD11_Msk)) | EADC1_CH1_PD11 /*!< Set PD11 function to EADC1_CH1 */ +#define SET_EADC1_CH10_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC1_CH10_PB2_Msk)) | EADC1_CH10_PB2 /*!< Set PB2 function to EADC1_CH10 */ +#define SET_EADC1_CH11_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC1_CH11_PB3_Msk)) | EADC1_CH11_PB3 /*!< Set PB3 function to EADC1_CH11 */ +#define SET_EADC1_CH12_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC1_CH12_PB12_Msk)) | EADC1_CH12_PB12 /*!< Set PB12 function to EADC1_CH12 */ +#define SET_EADC1_CH13_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC1_CH13_PB13_Msk)) | EADC1_CH13_PB13 /*!< Set PB13 function to EADC1_CH13 */ +#define SET_EADC1_CH14_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC1_CH14_PB14_Msk)) | EADC1_CH14_PB14 /*!< Set PB14 function to EADC1_CH14 */ +#define SET_EADC1_CH15_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EADC1_CH15_PB15_Msk)) | EADC1_CH15_PB15 /*!< Set PB15 function to EADC1_CH15 */ +#define SET_EADC1_CH2_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EADC1_CH2_PD12_Msk)) | EADC1_CH2_PD12 /*!< Set PD12 function to EADC1_CH2 */ +#define SET_EADC1_CH3_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EADC1_CH3_PC13_Msk)) | EADC1_CH3_PC13 /*!< Set PC13 function to EADC1_CH3 */ +#define SET_EADC1_CH4_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC1_CH4_PA8_Msk)) | EADC1_CH4_PA8 /*!< Set PA8 function to EADC1_CH4 */ +#define SET_EADC1_CH5_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC1_CH5_PA9_Msk)) | EADC1_CH5_PA9 /*!< Set PA9 function to EADC1_CH5 */ +#define SET_EADC1_CH6_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC1_CH6_PA10_Msk)) | EADC1_CH6_PA10 /*!< Set PA10 function to EADC1_CH6 */ +#define SET_EADC1_CH7_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC1_CH7_PA11_Msk)) | EADC1_CH7_PA11 /*!< Set PA11 function to EADC1_CH7 */ +#define SET_EADC1_CH8_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC1_CH8_PB0_Msk)) | EADC1_CH8_PB0 /*!< Set PB0 function to EADC1_CH8 */ +#define SET_EADC1_CH9_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC1_CH9_PB1_Msk)) | EADC1_CH9_PB1 /*!< Set PB1 function to EADC1_CH9 */ +#define SET_EADC1_ST_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EADC1_ST_PC10_Msk)) | EADC1_ST_PC10 /*!< Set PC10 function to EADC1_ST */ +#define SET_EADC1_ST_PD5() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~EADC1_ST_PD5_Msk)) | EADC1_ST_PD5 /*!< Set PD5 function to EADC1_ST */ +#define SET_EADC1_ST_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EADC1_ST_PC0_Msk)) | EADC1_ST_PC0 /*!< Set PC0 function to EADC1_ST */ +#define SET_EADC1_ST_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~EADC1_ST_PF1_Msk)) | EADC1_ST_PF1 /*!< Set PF1 function to EADC1_ST */ +#define SET_EADC1_ST_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EADC1_ST_PF4_Msk)) | EADC1_ST_PF4 /*!< Set PF4 function to EADC1_ST */ +#define SET_EADC1_ST_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EADC1_ST_PC9_Msk)) | EADC1_ST_PC9 /*!< Set PC9 function to EADC1_ST */ +#define SET_EADC2_CH0_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EADC2_CH0_PD10_Msk)) | EADC2_CH0_PD10 /*!< Set PD10 function to EADC2_CH0 */ +#define SET_EADC2_CH1_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EADC2_CH1_PD11_Msk)) | EADC2_CH1_PD11 /*!< Set PD11 function to EADC2_CH1 */ +#define SET_EADC2_CH10_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EADC2_CH10_PC9_Msk)) | EADC2_CH10_PC9 /*!< Set PC9 function to EADC2_CH10 */ +#define SET_EADC2_CH11_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EADC2_CH11_PC10_Msk)) | EADC2_CH11_PC10 /*!< Set PC10 function to EADC2_CH11 */ +#define SET_EADC2_CH12_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EADC2_CH12_PC11_Msk)) | EADC2_CH12_PC11 /*!< Set PC11 function to EADC2_CH12 */ +#define SET_EADC2_CH13_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EADC2_CH13_PC12_Msk)) | EADC2_CH13_PC12 /*!< Set PC12 function to EADC2_CH13 */ +#define SET_EADC2_CH14_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EADC2_CH14_PB6_Msk)) | EADC2_CH14_PB6 /*!< Set PB6 function to EADC2_CH14 */ +#define SET_EADC2_CH15_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EADC2_CH15_PB7_Msk)) | EADC2_CH15_PB7 /*!< Set PB7 function to EADC2_CH15 */ +#define SET_EADC2_CH2_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EADC2_CH2_PD12_Msk)) | EADC2_CH2_PD12 /*!< Set PD12 function to EADC2_CH2 */ +#define SET_EADC2_CH3_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EADC2_CH3_PC13_Msk)) | EADC2_CH3_PC13 /*!< Set PC13 function to EADC2_CH3 */ +#define SET_EADC2_CH4_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC2_CH4_PA8_Msk)) | EADC2_CH4_PA8 /*!< Set PA8 function to EADC2_CH4 */ +#define SET_EADC2_CH5_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC2_CH5_PA9_Msk)) | EADC2_CH5_PA9 /*!< Set PA9 function to EADC2_CH5 */ +#define SET_EADC2_CH6_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC2_CH6_PA10_Msk)) | EADC2_CH6_PA10 /*!< Set PA10 function to EADC2_CH6 */ +#define SET_EADC2_CH7_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EADC2_CH7_PA11_Msk)) | EADC2_CH7_PA11 /*!< Set PA11 function to EADC2_CH7 */ +#define SET_EADC2_CH8_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC2_CH8_PB0_Msk)) | EADC2_CH8_PB0 /*!< Set PB0 function to EADC2_CH8 */ +#define SET_EADC2_CH9_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EADC2_CH9_PB1_Msk)) | EADC2_CH9_PB1 /*!< Set PB1 function to EADC2_CH9 */ +#define SET_EADC2_ST_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~EADC2_ST_PF3_Msk)) | EADC2_ST_PF3 /*!< Set PF3 function to EADC2_ST */ +#define SET_EADC2_ST_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EADC2_ST_PB8_Msk)) | EADC2_ST_PB8 /*!< Set PB8 function to EADC2_ST */ +#define SET_EBI_AD0_PJ7() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~EBI_AD0_PJ7_Msk)) | EBI_AD0_PJ7 /*!< Set PJ7 function to EBI_AD0 */ +#define SET_EBI_AD0_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EBI_AD0_PF4_Msk)) | EBI_AD0_PF4 /*!< Set PF4 function to EBI_AD0 */ +#define SET_EBI_AD0_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~EBI_AD0_PG9_Msk)) | EBI_AD0_PG9 /*!< Set PG9 function to EBI_AD0 */ +#define SET_EBI_AD0_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EBI_AD0_PC0_Msk)) | EBI_AD0_PC0 /*!< Set PC0 function to EBI_AD0 */ +#define SET_EBI_AD0_PH12() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~EBI_AD0_PH12_Msk)) | EBI_AD0_PH12 /*!< Set PH12 function to EBI_AD0 */ +#define SET_EBI_AD1_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EBI_AD1_PC1_Msk)) | EBI_AD1_PC1 /*!< Set PC1 function to EBI_AD1 */ +#define SET_EBI_AD1_PH13() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~EBI_AD1_PH13_Msk)) | EBI_AD1_PH13 /*!< Set PH13 function to EBI_AD1 */ +#define SET_EBI_AD1_PJ6() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~EBI_AD1_PJ6_Msk)) | EBI_AD1_PJ6 /*!< Set PJ6 function to EBI_AD1 */ +#define SET_EBI_AD1_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~EBI_AD1_PG10_Msk)) | EBI_AD1_PG10 /*!< Set PG10 function to EBI_AD1 */ +#define SET_EBI_AD1_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EBI_AD1_PF5_Msk)) | EBI_AD1_PF5 /*!< Set PF5 function to EBI_AD1 */ +#define SET_EBI_AD10_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EBI_AD10_PD3_Msk)) | EBI_AD10_PD3 /*!< Set PD3 function to EBI_AD10 */ +#define SET_EBI_AD10_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EBI_AD10_PE1_Msk)) | EBI_AD10_PE1 /*!< Set PE1 function to EBI_AD10 */ +#define SET_EBI_AD10_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EBI_AD10_PD13_Msk)) | EBI_AD10_PD13 /*!< Set PD13 function to EBI_AD10 */ +#define SET_EBI_AD11_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EBI_AD11_PE0_Msk)) | EBI_AD11_PE0 /*!< Set PE0 function to EBI_AD11 */ +#define SET_EBI_AD11_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EBI_AD11_PC14_Msk)) | EBI_AD11_PC14 /*!< Set PC14 function to EBI_AD11 */ +#define SET_EBI_AD11_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EBI_AD11_PD2_Msk)) | EBI_AD11_PD2 /*!< Set PD2 function to EBI_AD11 */ +#define SET_EBI_AD12_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EBI_AD12_PD1_Msk)) | EBI_AD12_PD1 /*!< Set PD1 function to EBI_AD12 */ +#define SET_EBI_AD12_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~EBI_AD12_PH8_Msk)) | EBI_AD12_PH8 /*!< Set PH8 function to EBI_AD12 */ +#define SET_EBI_AD12_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EBI_AD12_PB15_Msk)) | EBI_AD12_PB15 /*!< Set PB15 function to EBI_AD12 */ +#define SET_EBI_AD13_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EBI_AD13_PD0_Msk)) | EBI_AD13_PD0 /*!< Set PD0 function to EBI_AD13 */ +#define SET_EBI_AD13_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~EBI_AD13_PH9_Msk)) | EBI_AD13_PH9 /*!< Set PH9 function to EBI_AD13 */ +#define SET_EBI_AD13_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EBI_AD13_PB14_Msk)) | EBI_AD13_PB14 /*!< Set PB14 function to EBI_AD13 */ +#define SET_EBI_AD14_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EBI_AD14_PB13_Msk)) | EBI_AD14_PB13 /*!< Set PB13 function to EBI_AD14 */ +#define SET_EBI_AD14_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~EBI_AD14_PH10_Msk)) | EBI_AD14_PH10 /*!< Set PH10 function to EBI_AD14 */ +#define SET_EBI_AD15_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EBI_AD15_PB12_Msk)) | EBI_AD15_PB12 /*!< Set PB12 function to EBI_AD15 */ +#define SET_EBI_AD15_PH11() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~EBI_AD15_PH11_Msk)) | EBI_AD15_PH11 /*!< Set PH11 function to EBI_AD15 */ +#define SET_EBI_AD2_PH14() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~EBI_AD2_PH14_Msk)) | EBI_AD2_PH14 /*!< Set PH14 function to EBI_AD2 */ +#define SET_EBI_AD2_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~EBI_AD2_PG11_Msk)) | EBI_AD2_PG11 /*!< Set PG11 function to EBI_AD2 */ +#define SET_EBI_AD2_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EBI_AD2_PC2_Msk)) | EBI_AD2_PC2 /*!< Set PC2 function to EBI_AD2 */ +#define SET_EBI_AD2_PJ5() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~EBI_AD2_PJ5_Msk)) | EBI_AD2_PJ5 /*!< Set PJ5 function to EBI_AD2 */ +#define SET_EBI_AD3_PJ4() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~EBI_AD3_PJ4_Msk)) | EBI_AD3_PJ4 /*!< Set PJ4 function to EBI_AD3 */ +#define SET_EBI_AD3_PH15() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~EBI_AD3_PH15_Msk)) | EBI_AD3_PH15 /*!< Set PH15 function to EBI_AD3 */ +#define SET_EBI_AD3_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~EBI_AD3_PG12_Msk)) | EBI_AD3_PG12 /*!< Set PG12 function to EBI_AD3 */ +#define SET_EBI_AD3_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EBI_AD3_PC3_Msk)) | EBI_AD3_PC3 /*!< Set PC3 function to EBI_AD3 */ +#define SET_EBI_AD4_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~EBI_AD4_PG13_Msk)) | EBI_AD4_PG13 /*!< Set PG13 function to EBI_AD4 */ +#define SET_EBI_AD4_PJ3() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~EBI_AD4_PJ3_Msk)) | EBI_AD4_PJ3 /*!< Set PJ3 function to EBI_AD4 */ +#define SET_EBI_AD4_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~EBI_AD4_PD7_Msk)) | EBI_AD4_PD7 /*!< Set PD7 function to EBI_AD4 */ +#define SET_EBI_AD4_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EBI_AD4_PC4_Msk)) | EBI_AD4_PC4 /*!< Set PC4 function to EBI_AD4 */ +#define SET_EBI_AD5_PJ2() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~EBI_AD5_PJ2_Msk)) | EBI_AD5_PJ2 /*!< Set PJ2 function to EBI_AD5 */ +#define SET_EBI_AD5_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~EBI_AD5_PA14_Msk)) | EBI_AD5_PA14 /*!< Set PA14 function to EBI_AD5 */ +#define SET_EBI_AD5_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~EBI_AD5_PD6_Msk)) | EBI_AD5_PD6 /*!< Set PD6 function to EBI_AD5 */ +#define SET_EBI_AD5_PG14() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~EBI_AD5_PG14_Msk)) | EBI_AD5_PG14 /*!< Set PG14 function to EBI_AD5 */ +#define SET_EBI_AD5_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EBI_AD5_PC5_Msk)) | EBI_AD5_PC5 /*!< Set PC5 function to EBI_AD5 */ +#define SET_EBI_AD6_PD8() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EBI_AD6_PD8_Msk)) | EBI_AD6_PD8 /*!< Set PD8 function to EBI_AD6 */ +#define SET_EBI_AD6_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EBI_AD6_PA6_Msk)) | EBI_AD6_PA6 /*!< Set PA6 function to EBI_AD6 */ +#define SET_EBI_AD7_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EBI_AD7_PA7_Msk)) | EBI_AD7_PA7 /*!< Set PA7 function to EBI_AD7 */ +#define SET_EBI_AD7_PD9() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EBI_AD7_PD9_Msk)) | EBI_AD7_PD9 /*!< Set PD9 function to EBI_AD7 */ +#define SET_EBI_AD8_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EBI_AD8_PC6_Msk)) | EBI_AD8_PC6 /*!< Set PC6 function to EBI_AD8 */ +#define SET_EBI_AD8_PE14() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EBI_AD8_PE14_Msk)) | EBI_AD8_PE14 /*!< Set PE14 function to EBI_AD8 */ +#define SET_EBI_AD9_PE15() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EBI_AD9_PE15_Msk)) | EBI_AD9_PE15 /*!< Set PE15 function to EBI_AD9 */ +#define SET_EBI_AD9_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EBI_AD9_PC7_Msk)) | EBI_AD9_PC7 /*!< Set PC7 function to EBI_AD9 */ +#define SET_EBI_ADR0_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EBI_ADR0_PB5_Msk)) | EBI_ADR0_PB5 /*!< Set PB5 function to EBI_ADR0 */ +#define SET_EBI_ADR0_PH7() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~EBI_ADR0_PH7_Msk)) | EBI_ADR0_PH7 /*!< Set PH7 function to EBI_ADR0 */ +#define SET_EBI_ADR1_PH6() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~EBI_ADR1_PH6_Msk)) | EBI_ADR1_PH6 /*!< Set PH6 function to EBI_ADR1 */ +#define SET_EBI_ADR1_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EBI_ADR1_PB4_Msk)) | EBI_ADR1_PB4 /*!< Set PB4 function to EBI_ADR1 */ +#define SET_EBI_ADR10_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EBI_ADR10_PE8_Msk)) | EBI_ADR10_PE8 /*!< Set PE8 function to EBI_ADR10 */ +#define SET_EBI_ADR10_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EBI_ADR10_PC13_Msk)) | EBI_ADR10_PC13 /*!< Set PC13 function to EBI_ADR10 */ +#define SET_EBI_ADR11_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EBI_ADR11_PE9_Msk)) | EBI_ADR11_PE9 /*!< Set PE9 function to EBI_ADR11 */ +#define SET_EBI_ADR11_PG2() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~EBI_ADR11_PG2_Msk)) | EBI_ADR11_PG2 /*!< Set PG2 function to EBI_ADR11 */ +#define SET_EBI_ADR12_PG3() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~EBI_ADR12_PG3_Msk)) | EBI_ADR12_PG3 /*!< Set PG3 function to EBI_ADR12 */ +#define SET_EBI_ADR12_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EBI_ADR12_PE10_Msk)) | EBI_ADR12_PE10 /*!< Set PE10 function to EBI_ADR12 */ +#define SET_EBI_ADR13_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EBI_ADR13_PE11_Msk)) | EBI_ADR13_PE11 /*!< Set PE11 function to EBI_ADR13 */ +#define SET_EBI_ADR13_PG4() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~EBI_ADR13_PG4_Msk)) | EBI_ADR13_PG4 /*!< Set PG4 function to EBI_ADR13 */ +#define SET_EBI_ADR14_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~EBI_ADR14_PF11_Msk)) | EBI_ADR14_PF11 /*!< Set PF11 function to EBI_ADR14 */ +#define SET_EBI_ADR14_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EBI_ADR14_PE12_Msk)) | EBI_ADR14_PE12 /*!< Set PE12 function to EBI_ADR14 */ +#define SET_EBI_ADR15_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EBI_ADR15_PE13_Msk)) | EBI_ADR15_PE13 /*!< Set PE13 function to EBI_ADR15 */ +#define SET_EBI_ADR15_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~EBI_ADR15_PF10_Msk)) | EBI_ADR15_PF10 /*!< Set PF10 function to EBI_ADR15 */ +#define SET_EBI_ADR16_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EBI_ADR16_PB11_Msk)) | EBI_ADR16_PB11 /*!< Set PB11 function to EBI_ADR16 */ +#define SET_EBI_ADR16_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EBI_ADR16_PC8_Msk)) | EBI_ADR16_PC8 /*!< Set PC8 function to EBI_ADR16 */ +#define SET_EBI_ADR16_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~EBI_ADR16_PF9_Msk)) | EBI_ADR16_PF9 /*!< Set PF9 function to EBI_ADR16 */ +#define SET_EBI_ADR17_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EBI_ADR17_PB10_Msk)) | EBI_ADR17_PB10 /*!< Set PB10 function to EBI_ADR17 */ +#define SET_EBI_ADR17_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~EBI_ADR17_PF8_Msk)) | EBI_ADR17_PF8 /*!< Set PF8 function to EBI_ADR17 */ +#define SET_EBI_ADR18_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EBI_ADR18_PF7_Msk)) | EBI_ADR18_PF7 /*!< Set PF7 function to EBI_ADR18 */ +#define SET_EBI_ADR18_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EBI_ADR18_PB9_Msk)) | EBI_ADR18_PB9 /*!< Set PB9 function to EBI_ADR18 */ +#define SET_EBI_ADR19_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EBI_ADR19_PF6_Msk)) | EBI_ADR19_PF6 /*!< Set PF6 function to EBI_ADR19 */ +#define SET_EBI_ADR19_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EBI_ADR19_PB8_Msk)) | EBI_ADR19_PB8 /*!< Set PB8 function to EBI_ADR19 */ +#define SET_EBI_ADR2_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EBI_ADR2_PB3_Msk)) | EBI_ADR2_PB3 /*!< Set PB3 function to EBI_ADR2 */ +#define SET_EBI_ADR2_PH5() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~EBI_ADR2_PH5_Msk)) | EBI_ADR2_PH5 /*!< Set PH5 function to EBI_ADR2 */ +#define SET_EBI_ADR3_PH4() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~EBI_ADR3_PH4_Msk)) | EBI_ADR3_PH4 /*!< Set PH4 function to EBI_ADR3 */ +#define SET_EBI_ADR3_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EBI_ADR3_PB2_Msk)) | EBI_ADR3_PB2 /*!< Set PB2 function to EBI_ADR3 */ +#define SET_EBI_ADR4_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EBI_ADR4_PC12_Msk)) | EBI_ADR4_PC12 /*!< Set PC12 function to EBI_ADR4 */ +#define SET_EBI_ADR4_PH3() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~EBI_ADR4_PH3_Msk)) | EBI_ADR4_PH3 /*!< Set PH3 function to EBI_ADR4 */ +#define SET_EBI_ADR5_PH2() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~EBI_ADR5_PH2_Msk)) | EBI_ADR5_PH2 /*!< Set PH2 function to EBI_ADR5 */ +#define SET_EBI_ADR5_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EBI_ADR5_PC11_Msk)) | EBI_ADR5_PC11 /*!< Set PC11 function to EBI_ADR5 */ +#define SET_EBI_ADR6_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EBI_ADR6_PC10_Msk)) | EBI_ADR6_PC10 /*!< Set PC10 function to EBI_ADR6 */ +#define SET_EBI_ADR6_PH1() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~EBI_ADR6_PH1_Msk)) | EBI_ADR6_PH1 /*!< Set PH1 function to EBI_ADR6 */ +#define SET_EBI_ADR7_PH0() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~EBI_ADR7_PH0_Msk)) | EBI_ADR7_PH0 /*!< Set PH0 function to EBI_ADR7 */ +#define SET_EBI_ADR7_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EBI_ADR7_PC9_Msk)) | EBI_ADR7_PC9 /*!< Set PC9 function to EBI_ADR7 */ +#define SET_EBI_ADR8_PG0() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~EBI_ADR8_PG0_Msk)) | EBI_ADR8_PG0 /*!< Set PG0 function to EBI_ADR8 */ +#define SET_EBI_ADR8_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EBI_ADR8_PB1_Msk)) | EBI_ADR8_PB1 /*!< Set PB1 function to EBI_ADR8 */ +#define SET_EBI_ADR9_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EBI_ADR9_PB0_Msk)) | EBI_ADR9_PB0 /*!< Set PB0 function to EBI_ADR9 */ +#define SET_EBI_ADR9_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~EBI_ADR9_PG1_Msk)) | EBI_ADR9_PG1 /*!< Set PG1 function to EBI_ADR9 */ +#define SET_EBI_ALE_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EBI_ALE_PA8_Msk)) | EBI_ALE_PA8 /*!< Set PA8 function to EBI_ALE */ +#define SET_EBI_ALE_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EBI_ALE_PE2_Msk)) | EBI_ALE_PE2 /*!< Set PE2 function to EBI_ALE */ +#define SET_EBI_ALE_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~EBI_ALE_PJ11_Msk)) | EBI_ALE_PJ11 /*!< Set PJ11 function to EBI_ALE */ +#define SET_EBI_MCLK_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EBI_MCLK_PE3_Msk)) | EBI_MCLK_PE3 /*!< Set PE3 function to EBI_MCLK */ +#define SET_EBI_MCLK_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EBI_MCLK_PA9_Msk)) | EBI_MCLK_PA9 /*!< Set PA9 function to EBI_MCLK */ +#define SET_EBI_MCLK_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~EBI_MCLK_PJ10_Msk)) | EBI_MCLK_PJ10 /*!< Set PJ10 function to EBI_MCLK */ +#define SET_EBI_nCS0_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~EBI_nCS0_PF3_Msk)) | EBI_nCS0_PF3 /*!< Set PF3 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~EBI_nCS0_PJ12_Msk)) | EBI_nCS0_PJ12 /*!< Set PJ12 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PD14() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EBI_nCS0_PD14_Msk)) | EBI_nCS0_PD14 /*!< Set PD14 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EBI_nCS0_PB7_Msk)) | EBI_nCS0_PB7 /*!< Set PB7 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EBI_nCS0_PF6_Msk)) | EBI_nCS0_PF6 /*!< Set PF6 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EBI_nCS0_PD12_Msk)) | EBI_nCS0_PD12 /*!< Set PD12 function to EBI_nCS0 */ +#define SET_EBI_nCS1_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EBI_nCS1_PB6_Msk)) | EBI_nCS1_PB6 /*!< Set PB6 function to EBI_nCS1 */ +#define SET_EBI_nCS1_PG5() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~EBI_nCS1_PG5_Msk)) | EBI_nCS1_PG5 /*!< Set PG5 function to EBI_nCS1 */ +#define SET_EBI_nCS1_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EBI_nCS1_PD11_Msk)) | EBI_nCS1_PD11 /*!< Set PD11 function to EBI_nCS1 */ +#define SET_EBI_nCS1_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~EBI_nCS1_PF2_Msk)) | EBI_nCS1_PF2 /*!< Set PF2 function to EBI_nCS1 */ +#define SET_EBI_nCS2_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EBI_nCS2_PD10_Msk)) | EBI_nCS2_PD10 /*!< Set PD10 function to EBI_nCS2 */ +#define SET_EBI_nCS2_PG6() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~EBI_nCS2_PG6_Msk)) | EBI_nCS2_PG6 /*!< Set PG6 function to EBI_nCS2 */ +#define SET_EBI_nRD_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EBI_nRD_PA11_Msk)) | EBI_nRD_PA11 /*!< Set PA11 function to EBI_nRD */ +#define SET_EBI_nRD_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EBI_nRD_PE5_Msk)) | EBI_nRD_PE5 /*!< Set PE5 function to EBI_nRD */ +#define SET_EBI_nRD_PJ8() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~EBI_nRD_PJ8_Msk)) | EBI_nRD_PJ8 /*!< Set PJ8 function to EBI_nRD */ +#define SET_EBI_nWR_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EBI_nWR_PA10_Msk)) | EBI_nWR_PA10 /*!< Set PA10 function to EBI_nWR */ +#define SET_EBI_nWR_PJ9() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~EBI_nWR_PJ9_Msk)) | EBI_nWR_PJ9 /*!< Set PJ9 function to EBI_nWR */ +#define SET_EBI_nWR_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EBI_nWR_PE4_Msk)) | EBI_nWR_PE4 /*!< Set PE4 function to EBI_nWR */ +#define SET_EBI_nWRH_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EBI_nWRH_PB6_Msk)) | EBI_nWRH_PB6 /*!< Set PB6 function to EBI_nWRH */ +#define SET_EBI_nWRH_PG8() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~EBI_nWRH_PG8_Msk)) | EBI_nWRH_PG8 /*!< Set PG8 function to EBI_nWRH */ +#define SET_EBI_nWRL_PG7() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~EBI_nWRL_PG7_Msk)) | EBI_nWRL_PG7 /*!< Set PG7 function to EBI_nWRL */ +#define SET_EBI_nWRL_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EBI_nWRL_PB7_Msk)) | EBI_nWRL_PB7 /*!< Set PB7 function to EBI_nWRL */ +#define SET_ECAP0_IC0_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~ECAP0_IC0_PE8_Msk)) | ECAP0_IC0_PE8 /*!< Set PE8 function to ECAP0_IC0 */ +#define SET_ECAP0_IC0_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~ECAP0_IC0_PA10_Msk)) | ECAP0_IC0_PA10 /*!< Set PA10 function to ECAP0_IC0 */ +#define SET_ECAP0_IC1_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~ECAP0_IC1_PA9_Msk)) | ECAP0_IC1_PA9 /*!< Set PA9 function to ECAP0_IC1 */ +#define SET_ECAP0_IC1_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~ECAP0_IC1_PE9_Msk)) | ECAP0_IC1_PE9 /*!< Set PE9 function to ECAP0_IC1 */ +#define SET_ECAP0_IC2_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~ECAP0_IC2_PE10_Msk)) | ECAP0_IC2_PE10 /*!< Set PE10 function to ECAP0_IC2 */ +#define SET_ECAP0_IC2_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~ECAP0_IC2_PA8_Msk)) | ECAP0_IC2_PA8 /*!< Set PA8 function to ECAP0_IC2 */ +#define SET_ECAP1_IC0_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~ECAP1_IC0_PE13_Msk)) | ECAP1_IC0_PE13 /*!< Set PE13 function to ECAP1_IC0 */ +#define SET_ECAP1_IC0_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~ECAP1_IC0_PC10_Msk)) | ECAP1_IC0_PC10 /*!< Set PC10 function to ECAP1_IC0 */ +#define SET_ECAP1_IC1_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~ECAP1_IC1_PC11_Msk)) | ECAP1_IC1_PC11 /*!< Set PC11 function to ECAP1_IC1 */ +#define SET_ECAP1_IC1_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~ECAP1_IC1_PE12_Msk)) | ECAP1_IC1_PE12 /*!< Set PE12 function to ECAP1_IC1 */ +#define SET_ECAP1_IC2_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~ECAP1_IC2_PC12_Msk)) | ECAP1_IC2_PC12 /*!< Set PC12 function to ECAP1_IC2 */ +#define SET_ECAP1_IC2_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~ECAP1_IC2_PE11_Msk)) | ECAP1_IC2_PE11 /*!< Set PE11 function to ECAP1_IC2 */ +#define SET_ECAP2_IC0_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~ECAP2_IC0_PG9_Msk)) | ECAP2_IC0_PG9 /*!< Set PG9 function to ECAP2_IC0 */ +#define SET_ECAP2_IC0_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~ECAP2_IC0_PJ10_Msk)) | ECAP2_IC0_PJ10 /*!< Set PJ10 function to ECAP2_IC0 */ +#define SET_ECAP2_IC0_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~ECAP2_IC0_PD1_Msk)) | ECAP2_IC0_PD1 /*!< Set PD1 function to ECAP2_IC0 */ +#define SET_ECAP2_IC1_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~ECAP2_IC1_PD0_Msk)) | ECAP2_IC1_PD0 /*!< Set PD0 function to ECAP2_IC1 */ +#define SET_ECAP2_IC1_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~ECAP2_IC1_PJ11_Msk)) | ECAP2_IC1_PJ11 /*!< Set PJ11 function to ECAP2_IC1 */ +#define SET_ECAP2_IC1_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~ECAP2_IC1_PG10_Msk)) | ECAP2_IC1_PG10 /*!< Set PG10 function to ECAP2_IC1 */ +#define SET_ECAP2_IC2_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~ECAP2_IC2_PG11_Msk)) | ECAP2_IC2_PG11 /*!< Set PG11 function to ECAP2_IC2 */ +#define SET_ECAP2_IC2_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~ECAP2_IC2_PJ12_Msk)) | ECAP2_IC2_PJ12 /*!< Set PJ12 function to ECAP2_IC2 */ +#define SET_ECAP2_IC2_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~ECAP2_IC2_PD13_Msk)) | ECAP2_IC2_PD13 /*!< Set PD13 function to ECAP2_IC2 */ +#define SET_ECAP3_IC0_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~ECAP3_IC0_PA12_Msk)) | ECAP3_IC0_PA12 /*!< Set PA12 function to ECAP3_IC0 */ +#define SET_ECAP3_IC0_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~ECAP3_IC0_PD12_Msk)) | ECAP3_IC0_PD12 /*!< Set PD12 function to ECAP3_IC0 */ +#define SET_ECAP3_IC0_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~ECAP3_IC0_PE8_Msk)) | ECAP3_IC0_PE8 /*!< Set PE8 function to ECAP3_IC0 */ +#define SET_ECAP3_IC1_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~ECAP3_IC1_PA13_Msk)) | ECAP3_IC1_PA13 /*!< Set PA13 function to ECAP3_IC1 */ +#define SET_ECAP3_IC1_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~ECAP3_IC1_PE9_Msk)) | ECAP3_IC1_PE9 /*!< Set PE9 function to ECAP3_IC1 */ +#define SET_ECAP3_IC1_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~ECAP3_IC1_PD11_Msk)) | ECAP3_IC1_PD11 /*!< Set PD11 function to ECAP3_IC1 */ +#define SET_ECAP3_IC2_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~ECAP3_IC2_PE10_Msk)) | ECAP3_IC2_PE10 /*!< Set PE10 function to ECAP3_IC2 */ +#define SET_ECAP3_IC2_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~ECAP3_IC2_PD10_Msk)) | ECAP3_IC2_PD10 /*!< Set PD10 function to ECAP3_IC2 */ +#define SET_ECAP3_IC2_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~ECAP3_IC2_PA14_Msk)) | ECAP3_IC2_PA14 /*!< Set PA14 function to ECAP3_IC2 */ +#define SET_EMAC0_PPS_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EMAC0_PPS_PE13_Msk)) | EMAC0_PPS_PE13 /*!< Set PE13 function to EMAC0_PPS */ +#define SET_EMAC0_PPS_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EMAC0_PPS_PB6_Msk)) | EMAC0_PPS_PB6 /*!< Set PB6 function to EMAC0_PPS */ +#define SET_EMAC0_RMII_CRSDV_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EMAC0_RMII_CRSDV_PA7_Msk)) | EMAC0_RMII_CRSDV_PA7 /*!< Set PA7 function to EMAC0_RMII_CRSDV */ +#define SET_EMAC0_RMII_CRSDV_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EMAC0_RMII_CRSDV_PB2_Msk)) | EMAC0_RMII_CRSDV_PB2 /*!< Set PB2 function to EMAC0_RMII_CRSDV */ +#define SET_EMAC0_RMII_MDC_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EMAC0_RMII_MDC_PE8_Msk)) | EMAC0_RMII_MDC_PE8 /*!< Set PE8 function to EMAC0_RMII_MDC */ +#define SET_EMAC0_RMII_MDC_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EMAC0_RMII_MDC_PB11_Msk)) | EMAC0_RMII_MDC_PB11 /*!< Set PB11 function to EMAC0_RMII_MDC */ +#define SET_EMAC0_RMII_MDIO_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EMAC0_RMII_MDIO_PB10_Msk)) | EMAC0_RMII_MDIO_PB10 /*!< Set PB10 function to EMAC0_RMII_MDIO */ +#define SET_EMAC0_RMII_MDIO_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EMAC0_RMII_MDIO_PE9_Msk)) | EMAC0_RMII_MDIO_PE9 /*!< Set PE9 function to EMAC0_RMII_MDIO */ +#define SET_EMAC0_RMII_REFCLK_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EMAC0_RMII_REFCLK_PB5_Msk)) | EMAC0_RMII_REFCLK_PB5 /*!< Set PB5 function to EMAC0_RMII_REFCLK */ +#define SET_EMAC0_RMII_REFCLK_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EMAC0_RMII_REFCLK_PC8_Msk)) | EMAC0_RMII_REFCLK_PC8 /*!< Set PC8 function to EMAC0_RMII_REFCLK */ +#define SET_EMAC0_RMII_RXD0_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EMAC0_RMII_RXD0_PC7_Msk)) | EMAC0_RMII_RXD0_PC7 /*!< Set PC7 function to EMAC0_RMII_RXD0 */ +#define SET_EMAC0_RMII_RXD0_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EMAC0_RMII_RXD0_PB4_Msk)) | EMAC0_RMII_RXD0_PB4 /*!< Set PB4 function to EMAC0_RMII_RXD0 */ +#define SET_EMAC0_RMII_RXD1_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EMAC0_RMII_RXD1_PB3_Msk)) | EMAC0_RMII_RXD1_PB3 /*!< Set PB3 function to EMAC0_RMII_RXD1 */ +#define SET_EMAC0_RMII_RXD1_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EMAC0_RMII_RXD1_PC6_Msk)) | EMAC0_RMII_RXD1_PC6 /*!< Set PC6 function to EMAC0_RMII_RXD1 */ +#define SET_EMAC0_RMII_RXERR_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EMAC0_RMII_RXERR_PA6_Msk)) | EMAC0_RMII_RXERR_PA6 /*!< Set PA6 function to EMAC0_RMII_RXERR */ +#define SET_EMAC0_RMII_RXERR_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EMAC0_RMII_RXERR_PB1_Msk)) | EMAC0_RMII_RXERR_PB1 /*!< Set PB1 function to EMAC0_RMII_RXERR */ +#define SET_EMAC0_RMII_TXD0_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EMAC0_RMII_TXD0_PE10_Msk)) | EMAC0_RMII_TXD0_PE10 /*!< Set PE10 function to EMAC0_RMII_TXD0 */ +#define SET_EMAC0_RMII_TXD0_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EMAC0_RMII_TXD0_PB9_Msk)) | EMAC0_RMII_TXD0_PB9 /*!< Set PB9 function to EMAC0_RMII_TXD0 */ +#define SET_EMAC0_RMII_TXD1_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~EMAC0_RMII_TXD1_PB8_Msk)) | EMAC0_RMII_TXD1_PB8 /*!< Set PB8 function to EMAC0_RMII_TXD1 */ +#define SET_EMAC0_RMII_TXD1_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EMAC0_RMII_TXD1_PE11_Msk)) | EMAC0_RMII_TXD1_PE11 /*!< Set PE11 function to EMAC0_RMII_TXD1 */ +#define SET_EMAC0_RMII_TXEN_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EMAC0_RMII_TXEN_PB7_Msk)) | EMAC0_RMII_TXEN_PB7 /*!< Set PB7 function to EMAC0_RMII_TXEN */ +#define SET_EMAC0_RMII_TXEN_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EMAC0_RMII_TXEN_PE12_Msk)) | EMAC0_RMII_TXEN_PE12 /*!< Set PE12 function to EMAC0_RMII_TXEN */ +#define SET_EPWM0_BRAKE0_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM0_BRAKE0_PE8_Msk)) | EPWM0_BRAKE0_PE8 /*!< Set PE8 function to EPWM0_BRAKE0 */ +#define SET_EPWM0_BRAKE0_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM0_BRAKE0_PB1_Msk)) | EPWM0_BRAKE0_PB1 /*!< Set PB1 function to EPWM0_BRAKE0 */ +#define SET_EPWM0_BRAKE1_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM0_BRAKE1_PE9_Msk)) | EPWM0_BRAKE1_PE9 /*!< Set PE9 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_BRAKE1_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EPWM0_BRAKE1_PB15_Msk)) | EPWM0_BRAKE1_PB15 /*!< Set PB15 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_BRAKE1_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM0_BRAKE1_PB0_Msk)) | EPWM0_BRAKE1_PB0 /*!< Set PB0 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_CH0_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EPWM0_CH0_PA5_Msk)) | EPWM0_CH0_PA5 /*!< Set PA5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PG8() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~EPWM0_CH0_PG8_Msk)) | EPWM0_CH0_PG8 /*!< Set PG8 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EPWM0_CH0_PF5_Msk)) | EPWM0_CH0_PF5 /*!< Set PF5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EPWM0_CH0_PE7_Msk)) | EPWM0_CH0_PE7 /*!< Set PE7 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EPWM0_CH0_PB5_Msk)) | EPWM0_CH0_PB5 /*!< Set PB5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM0_CH0_PE8_Msk)) | EPWM0_CH0_PE8 /*!< Set PE8 function to EPWM0_CH0 */ +#define SET_EPWM0_CH1_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM0_CH1_PE9_Msk)) | EPWM0_CH1_PE9 /*!< Set PE9 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EPWM0_CH1_PE6_Msk)) | EPWM0_CH1_PE6 /*!< Set PE6 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EPWM0_CH1_PF4_Msk)) | EPWM0_CH1_PF4 /*!< Set PF4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EPWM0_CH1_PB4_Msk)) | EPWM0_CH1_PB4 /*!< Set PB4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EPWM0_CH1_PA4_Msk)) | EPWM0_CH1_PA4 /*!< Set PA4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PG7() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~EPWM0_CH1_PG7_Msk)) | EPWM0_CH1_PG7 /*!< Set PG7 function to EPWM0_CH1 */ +#define SET_EPWM0_CH2_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EPWM0_CH2_PE5_Msk)) | EPWM0_CH2_PE5 /*!< Set PE5 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PG6() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~EPWM0_CH2_PG6_Msk)) | EPWM0_CH2_PG6 /*!< Set PG6 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EPWM0_CH2_PA3_Msk)) | EPWM0_CH2_PA3 /*!< Set PA3 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM0_CH2_PB3_Msk)) | EPWM0_CH2_PB3 /*!< Set PB3 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM0_CH2_PE10_Msk)) | EPWM0_CH2_PE10 /*!< Set PE10 function to EPWM0_CH2 */ +#define SET_EPWM0_CH3_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM0_CH3_PB2_Msk)) | EPWM0_CH3_PB2 /*!< Set PB2 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EPWM0_CH3_PE4_Msk)) | EPWM0_CH3_PE4 /*!< Set PE4 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EPWM0_CH3_PA2_Msk)) | EPWM0_CH3_PA2 /*!< Set PA2 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM0_CH3_PE11_Msk)) | EPWM0_CH3_PE11 /*!< Set PE11 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PG5() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~EPWM0_CH3_PG5_Msk)) | EPWM0_CH3_PG5 /*!< Set PG5 function to EPWM0_CH3 */ +#define SET_EPWM0_CH4_PD14() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EPWM0_CH4_PD14_Msk)) | EPWM0_CH4_PD14 /*!< Set PD14 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM0_CH4_PB1_Msk)) | EPWM0_CH4_PB1 /*!< Set PB1 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EPWM0_CH4_PE12_Msk)) | EPWM0_CH4_PE12 /*!< Set PE12 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EPWM0_CH4_PA1_Msk)) | EPWM0_CH4_PA1 /*!< Set PA1 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EPWM0_CH4_PE3_Msk)) | EPWM0_CH4_PE3 /*!< Set PE3 function to EPWM0_CH4 */ +#define SET_EPWM0_CH5_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EPWM0_CH5_PE13_Msk)) | EPWM0_CH5_PE13 /*!< Set PE13 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EPWM0_CH5_PA0_Msk)) | EPWM0_CH5_PA0 /*!< Set PA0 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM0_CH5_PB0_Msk)) | EPWM0_CH5_PB0 /*!< Set PB0 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EPWM0_CH5_PE2_Msk)) | EPWM0_CH5_PE2 /*!< Set PE2 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PH11() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~EPWM0_CH5_PH11_Msk)) | EPWM0_CH5_PH11 /*!< Set PH11 function to EPWM0_CH5 */ +#define SET_EPWM0_SYNC_IN_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~EPWM0_SYNC_IN_PA15_Msk)) | EPWM0_SYNC_IN_PA15/*!< Set PA15 function to EPWM0_SYNC_IN */ +#define SET_EPWM0_SYNC_IN_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EPWM0_SYNC_IN_PC14_Msk)) | EPWM0_SYNC_IN_PC14/*!< Set PC14 function to EPWM0_SYNC_IN */ +#define SET_EPWM0_SYNC_OUT_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EPWM0_SYNC_OUT_PA11_Msk)) | EPWM0_SYNC_OUT_PA11/*!< Set PA11 function to EPWM0_SYNC_OUT */ +#define SET_EPWM0_SYNC_OUT_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EPWM0_SYNC_OUT_PF5_Msk)) | EPWM0_SYNC_OUT_PF5/*!< Set PF5 function to EPWM0_SYNC_OUT */ +#define SET_EPWM1_BRAKE0_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EPWM1_BRAKE0_PB7_Msk)) | EPWM1_BRAKE0_PB7 /*!< Set PB7 function to EPWM1_BRAKE0 */ +#define SET_EPWM1_BRAKE0_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM1_BRAKE0_PE10_Msk)) | EPWM1_BRAKE0_PE10 /*!< Set PE10 function to EPWM1_BRAKE0 */ +#define SET_EPWM1_BRAKE1_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EPWM1_BRAKE1_PA3_Msk)) | EPWM1_BRAKE1_PA3 /*!< Set PA3 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_BRAKE1_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EPWM1_BRAKE1_PE11_Msk)) | EPWM1_BRAKE1_PE11 /*!< Set PE11 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_BRAKE1_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EPWM1_BRAKE1_PB6_Msk)) | EPWM1_BRAKE1_PB6 /*!< Set PB6 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_CH0_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EPWM1_CH0_PC5_Msk)) | EPWM1_CH0_PC5 /*!< Set PC5 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PI12() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~EPWM1_CH0_PI12_Msk)) | EPWM1_CH0_PI12 /*!< Set PI12 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EPWM1_CH0_PB15_Msk)) | EPWM1_CH0_PB15 /*!< Set PB15 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~EPWM1_CH0_PE13_Msk)) | EPWM1_CH0_PE13 /*!< Set PE13 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~EPWM1_CH0_PC12_Msk)) | EPWM1_CH0_PC12 /*!< Set PC12 function to EPWM1_CH0 */ +#define SET_EPWM1_CH1_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EPWM1_CH1_PB14_Msk)) | EPWM1_CH1_PB14 /*!< Set PB14 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EPWM1_CH1_PC8_Msk)) | EPWM1_CH1_PC8 /*!< Set PC8 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PI13() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~EPWM1_CH1_PI13_Msk)) | EPWM1_CH1_PI13 /*!< Set PI13 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EPWM1_CH1_PC4_Msk)) | EPWM1_CH1_PC4 /*!< Set PC4 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EPWM1_CH1_PC11_Msk)) | EPWM1_CH1_PC11 /*!< Set PC11 function to EPWM1_CH1 */ +#define SET_EPWM1_CH2_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EPWM1_CH2_PC10_Msk)) | EPWM1_CH2_PC10 /*!< Set PC10 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EPWM1_CH2_PB13_Msk)) | EPWM1_CH2_PB13 /*!< Set PB13 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EPWM1_CH2_PC7_Msk)) | EPWM1_CH2_PC7 /*!< Set PC7 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PI14() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~EPWM1_CH2_PI14_Msk)) | EPWM1_CH2_PI14 /*!< Set PI14 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EPWM1_CH2_PC3_Msk)) | EPWM1_CH2_PC3 /*!< Set PC3 function to EPWM1_CH2 */ +#define SET_EPWM1_CH3_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~EPWM1_CH3_PC9_Msk)) | EPWM1_CH3_PC9 /*!< Set PC9 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EPWM1_CH3_PC2_Msk)) | EPWM1_CH3_PC2 /*!< Set PC2 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~EPWM1_CH3_PC6_Msk)) | EPWM1_CH3_PC6 /*!< Set PC6 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~EPWM1_CH3_PB12_Msk)) | EPWM1_CH3_PB12 /*!< Set PB12 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PI15() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~EPWM1_CH3_PI15_Msk)) | EPWM1_CH3_PI15 /*!< Set PI15 function to EPWM1_CH3 */ +#define SET_EPWM1_CH4_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EPWM1_CH4_PB7_Msk)) | EPWM1_CH4_PB7 /*!< Set PB7 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM1_CH4_PB1_Msk)) | EPWM1_CH4_PB1 /*!< Set PB1 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PJ0() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~EPWM1_CH4_PJ0_Msk)) | EPWM1_CH4_PJ0 /*!< Set PJ0 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~EPWM1_CH4_PF0_Msk)) | EPWM1_CH4_PF0 /*!< Set PF0 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EPWM1_CH4_PA7_Msk)) | EPWM1_CH4_PA7 /*!< Set PA7 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EPWM1_CH4_PC1_Msk)) | EPWM1_CH4_PC1 /*!< Set PC1 function to EPWM1_CH4 */ +#define SET_EPWM1_CH5_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~EPWM1_CH5_PF1_Msk)) | EPWM1_CH5_PF1 /*!< Set PF1 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~EPWM1_CH5_PB0_Msk)) | EPWM1_CH5_PB0 /*!< Set PB0 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EPWM1_CH5_PA6_Msk)) | EPWM1_CH5_PA6 /*!< Set PA6 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PJ1() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~EPWM1_CH5_PJ1_Msk)) | EPWM1_CH5_PJ1 /*!< Set PJ1 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~EPWM1_CH5_PC0_Msk)) | EPWM1_CH5_PC0 /*!< Set PC0 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~EPWM1_CH5_PB6_Msk)) | EPWM1_CH5_PB6 /*!< Set PB6 function to EPWM1_CH5 */ +#define SET_ETMC_TRACE_CLK_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~ETMC_TRACE_CLK_PC14_Msk)) | ETMC_TRACE_CLK_PC14 /*!< Set PC14 function to ETMC_TRACE_CLK */ +#define SET_ETMC_TRACE_DATA0_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ETMC_TRACE_DATA0_PB15_Msk)) | ETMC_TRACE_DATA0_PB15 /*!< Set PB15 function to ETMC_TRACE_DATA0 */ +#define SET_ETMC_TRACE_DATA1_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ETMC_TRACE_DATA1_PB14_Msk)) | ETMC_TRACE_DATA1_PB14 /*!< Set PB14 function to ETMC_TRACE_DATA1 */ +#define SET_ETMC_TRACE_DATA2_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ETMC_TRACE_DATA2_PB13_Msk)) | ETMC_TRACE_DATA2_PB13 /*!< Set PB13 function to ETMC_TRACE_DATA2 */ +#define SET_ETMC_TRACE_DATA3_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~ETMC_TRACE_DATA3_PB12_Msk)) | ETMC_TRACE_DATA3_PB12 /*!< Set PB12 function to ETMC_TRACE_DATA3 */ +#define SET_HBI_CK_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~HBI_CK_PC4_Msk)) | HBI_CK_PC4 /*!< Set PC4 function to HBI_CK */ +#define SET_HBI_CK_PJ7() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~HBI_CK_PJ7_Msk)) | HBI_CK_PJ7 /*!< Set PJ7 function to HBI_CK */ +#define SET_HBI_D0_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~HBI_D0_PD6_Msk)) | HBI_D0_PD6 /*!< Set PD6 function to HBI_D0 */ +#define SET_HBI_D0_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~HBI_D0_PG11_Msk)) | HBI_D0_PG11 /*!< Set PG11 function to HBI_D0 */ +#define SET_HBI_D1_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~HBI_D1_PG12_Msk)) | HBI_D1_PG12 /*!< Set PG12 function to HBI_D1 */ +#define SET_HBI_D1_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~HBI_D1_PD7_Msk)) | HBI_D1_PD7 /*!< Set PD7 function to HBI_D1 */ +#define SET_HBI_D2_PH15() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~HBI_D2_PH15_Msk)) | HBI_D2_PH15 /*!< Set PH15 function to HBI_D2 */ +#define SET_HBI_D2_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~HBI_D2_PC0_Msk)) | HBI_D2_PC0 /*!< Set PC0 function to HBI_D2 */ +#define SET_HBI_D3_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~HBI_D3_PG10_Msk)) | HBI_D3_PG10 /*!< Set PG10 function to HBI_D3 */ +#define SET_HBI_D3_PH14() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~HBI_D3_PH14_Msk)) | HBI_D3_PH14 /*!< Set PH14 function to HBI_D3 */ +#define SET_HBI_D4_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~HBI_D4_PG9_Msk)) | HBI_D4_PG9 /*!< Set PG9 function to HBI_D4 */ +#define SET_HBI_D4_PJ6() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~HBI_D4_PJ6_Msk)) | HBI_D4_PJ6 /*!< Set PJ6 function to HBI_D4 */ +#define SET_HBI_D5_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~HBI_D5_PG13_Msk)) | HBI_D5_PG13 /*!< Set PG13 function to HBI_D5 */ +#define SET_HBI_D5_PJ5() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~HBI_D5_PJ5_Msk)) | HBI_D5_PJ5 /*!< Set PJ5 function to HBI_D5 */ +#define SET_HBI_D6_PG14() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~HBI_D6_PG14_Msk)) | HBI_D6_PG14 /*!< Set PG14 function to HBI_D6 */ +#define SET_HBI_D6_PJ4() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~HBI_D6_PJ4_Msk)) | HBI_D6_PJ4 /*!< Set PJ4 function to HBI_D6 */ +#define SET_HBI_D7_PG15() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~HBI_D7_PG15_Msk)) | HBI_D7_PG15 /*!< Set PG15 function to HBI_D7 */ +#define SET_HBI_D7_PJ3() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~HBI_D7_PJ3_Msk)) | HBI_D7_PJ3 /*!< Set PJ3 function to HBI_D7 */ +#define SET_HBI_RWDS_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~HBI_RWDS_PC1_Msk)) | HBI_RWDS_PC1 /*!< Set PC1 function to HBI_RWDS */ +#define SET_HBI_RWDS_PJ2() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~HBI_RWDS_PJ2_Msk)) | HBI_RWDS_PJ2 /*!< Set PJ2 function to HBI_RWDS */ +#define SET_HBI_nCK_PH12() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~HBI_nCK_PH12_Msk)) | HBI_nCK_PH12 /*!< Set PH12 function to HBI_nCK */ +#define SET_HBI_nCK_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~HBI_nCK_PC5_Msk)) | HBI_nCK_PC5 /*!< Set PC5 function to HBI_nCK */ +#define SET_HBI_nCS_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~HBI_nCS_PC3_Msk)) | HBI_nCS_PC3 /*!< Set PC3 function to HBI_nCS */ +#define SET_HBI_nCS_PH13() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~HBI_nCS_PH13_Msk)) | HBI_nCS_PH13 /*!< Set PH13 function to HBI_nCS */ +#define SET_HBI_nRESET_PD5() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~HBI_nRESET_PD5_Msk)) | HBI_nRESET_PD5 /*!< Set PD5 function to HBI_nRESET */ +#define SET_HBI_nRESET_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~HBI_nRESET_PC2_Msk)) | HBI_nRESET_PC2 /*!< Set PC2 function to HBI_nRESET */ +#define SET_HSUSB_VBUS_EN_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~HSUSB_VBUS_EN_PB10_Msk)) | HSUSB_VBUS_EN_PB10/*!< Set PB10 function to HSUSB_VBUS_EN */ +#define SET_HSUSB_VBUS_EN_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~HSUSB_VBUS_EN_PB15_Msk)) | HSUSB_VBUS_EN_PB15/*!< Set PB15 function to HSUSB_VBUS_EN */ +#define SET_HSUSB_VBUS_EN_PJ13() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~HSUSB_VBUS_EN_PJ13_Msk)) | HSUSB_VBUS_EN_PJ13/*!< Set PJ13 function to HSUSB_VBUS_EN */ +#define SET_HSUSB_VBUS_ST_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~HSUSB_VBUS_ST_PB11_Msk)) | HSUSB_VBUS_ST_PB11/*!< Set PB11 function to HSUSB_VBUS_ST */ +#define SET_HSUSB_VBUS_ST_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~HSUSB_VBUS_ST_PC14_Msk)) | HSUSB_VBUS_ST_PC14/*!< Set PC14 function to HSUSB_VBUS_ST */ +#define SET_HSUSB_VBUS_ST_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~HSUSB_VBUS_ST_PJ12_Msk)) | HSUSB_VBUS_ST_PJ12/*!< Set PJ12 function to HSUSB_VBUS_ST */ +#define SET_I2C0_SCL_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~I2C0_SCL_PB9_Msk)) | I2C0_SCL_PB9 /*!< Set PB9 function to I2C0_SCL */ +#define SET_I2C0_SCL_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C0_SCL_PF0_Msk)) | I2C0_SCL_PF0 /*!< Set PF0 function to I2C0_SCL */ +#define SET_I2C0_SCL_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~I2C0_SCL_PD7_Msk)) | I2C0_SCL_PD7 /*!< Set PD7 function to I2C0_SCL */ +#define SET_I2C0_SCL_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~I2C0_SCL_PA5_Msk)) | I2C0_SCL_PA5 /*!< Set PA5 function to I2C0_SCL */ +#define SET_I2C0_SCL_PH2() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~I2C0_SCL_PH2_Msk)) | I2C0_SCL_PH2 /*!< Set PH2 function to I2C0_SCL */ +#define SET_I2C0_SCL_PG0() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C0_SCL_PG0_Msk)) | I2C0_SCL_PG0 /*!< Set PG0 function to I2C0_SCL */ +#define SET_I2C0_SCL_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~I2C0_SCL_PC12_Msk)) | I2C0_SCL_PC12 /*!< Set PC12 function to I2C0_SCL */ +#define SET_I2C0_SCL_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2C0_SCL_PC1_Msk)) | I2C0_SCL_PC1 /*!< Set PC1 function to I2C0_SCL */ +#define SET_I2C0_SCL_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~I2C0_SCL_PB5_Msk)) | I2C0_SCL_PB5 /*!< Set PB5 function to I2C0_SCL */ +#define SET_I2C0_SCL_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~I2C0_SCL_PE13_Msk)) | I2C0_SCL_PE13 /*!< Set PE13 function to I2C0_SCL */ +#define SET_I2C0_SCL_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C0_SCL_PF3_Msk)) | I2C0_SCL_PF3 /*!< Set PF3 function to I2C0_SCL */ +#define SET_I2C0_SCL_PI10() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~I2C0_SCL_PI10_Msk)) | I2C0_SCL_PI10 /*!< Set PI10 function to I2C0_SCL */ +#define SET_I2C0_SCL_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2C0_SCL_PA14_Msk)) | I2C0_SCL_PA14 /*!< Set PA14 function to I2C0_SCL */ +#define SET_I2C0_SDA_PI11() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~I2C0_SDA_PI11_Msk)) | I2C0_SDA_PI11 /*!< Set PI11 function to I2C0_SDA */ +#define SET_I2C0_SDA_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C0_SDA_PF2_Msk)) | I2C0_SDA_PF2 /*!< Set PF2 function to I2C0_SDA */ +#define SET_I2C0_SDA_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~I2C0_SDA_PB4_Msk)) | I2C0_SDA_PB4 /*!< Set PB4 function to I2C0_SDA */ +#define SET_I2C0_SDA_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C0_SDA_PF1_Msk)) | I2C0_SDA_PF1 /*!< Set PF1 function to I2C0_SDA */ +#define SET_I2C0_SDA_PH3() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~I2C0_SDA_PH3_Msk)) | I2C0_SDA_PH3 /*!< Set PH3 function to I2C0_SDA */ +#define SET_I2C0_SDA_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C0_SDA_PG1_Msk)) | I2C0_SDA_PG1 /*!< Set PG1 function to I2C0_SDA */ +#define SET_I2C0_SDA_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~I2C0_SDA_PA4_Msk)) | I2C0_SDA_PA4 /*!< Set PA4 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~I2C0_SDA_PC11_Msk)) | I2C0_SDA_PC11 /*!< Set PC11 function to I2C0_SDA */ +#define SET_I2C0_SDA_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~I2C0_SDA_PD6_Msk)) | I2C0_SDA_PD6 /*!< Set PD6 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2C0_SDA_PC0_Msk)) | I2C0_SDA_PC0 /*!< Set PC0 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~I2C0_SDA_PC8_Msk)) | I2C0_SDA_PC8 /*!< Set PC8 function to I2C0_SDA */ +#define SET_I2C0_SDA_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~I2C0_SDA_PB8_Msk)) | I2C0_SDA_PB8 /*!< Set PB8 function to I2C0_SDA */ +#define SET_I2C0_SDA_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2C0_SDA_PA15_Msk)) | I2C0_SDA_PA15 /*!< Set PA15 function to I2C0_SDA */ +#define SET_I2C0_SMBAL_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2C0_SMBAL_PC3_Msk)) | I2C0_SMBAL_PC3 /*!< Set PC3 function to I2C0_SMBAL */ +#define SET_I2C0_SMBAL_PG2() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C0_SMBAL_PG2_Msk)) | I2C0_SMBAL_PG2 /*!< Set PG2 function to I2C0_SMBAL */ +#define SET_I2C0_SMBAL_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~I2C0_SMBAL_PA3_Msk)) | I2C0_SMBAL_PA3 /*!< Set PA3 function to I2C0_SMBAL */ +#define SET_I2C0_SMBAL_PI8() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~I2C0_SMBAL_PI8_Msk)) | I2C0_SMBAL_PI8 /*!< Set PI8 function to I2C0_SMBAL */ +#define SET_I2C0_SMBSUS_PI9() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~I2C0_SMBSUS_PI9_Msk)) | I2C0_SMBSUS_PI9 /*!< Set PI9 function to I2C0_SMBSUS */ +#define SET_I2C0_SMBSUS_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~I2C0_SMBSUS_PA2_Msk)) | I2C0_SMBSUS_PA2 /*!< Set PA2 function to I2C0_SMBSUS */ +#define SET_I2C0_SMBSUS_PG3() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C0_SMBSUS_PG3_Msk)) | I2C0_SMBSUS_PG3 /*!< Set PG3 function to I2C0_SMBSUS */ +#define SET_I2C0_SMBSUS_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2C0_SMBSUS_PC2_Msk)) | I2C0_SMBSUS_PC2 /*!< Set PC2 function to I2C0_SMBSUS */ +#define SET_I2C1_SCL_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C1_SCL_PF0_Msk)) | I2C1_SCL_PF0 /*!< Set PF0 function to I2C1_SCL */ +#define SET_I2C1_SCL_PD5() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~I2C1_SCL_PD5_Msk)) | I2C1_SCL_PD5 /*!< Set PD5 function to I2C1_SCL */ +#define SET_I2C1_SCL_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2C1_SCL_PB1_Msk)) | I2C1_SCL_PB1 /*!< Set PB1 function to I2C1_SCL */ +#define SET_I2C1_SCL_PI6() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~I2C1_SCL_PI6_Msk)) | I2C1_SCL_PI6 /*!< Set PI6 function to I2C1_SCL */ +#define SET_I2C1_SCL_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2C1_SCL_PB3_Msk)) | I2C1_SCL_PB3 /*!< Set PB3 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2C1_SCL_PA12_Msk)) | I2C1_SCL_PA12 /*!< Set PA12 function to I2C1_SCL */ +#define SET_I2C1_SCL_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~I2C1_SCL_PE1_Msk)) | I2C1_SCL_PE1 /*!< Set PE1 function to I2C1_SCL */ +#define SET_I2C1_SCL_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~I2C1_SCL_PB11_Msk)) | I2C1_SCL_PB11 /*!< Set PB11 function to I2C1_SCL */ +#define SET_I2C1_SCL_PG2() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C1_SCL_PG2_Msk)) | I2C1_SCL_PG2 /*!< Set PG2 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~I2C1_SCL_PA7_Msk)) | I2C1_SCL_PA7 /*!< Set PA7 function to I2C1_SCL */ +#define SET_I2C1_SCL_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~I2C1_SCL_PC5_Msk)) | I2C1_SCL_PC5 /*!< Set PC5 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~I2C1_SCL_PA3_Msk)) | I2C1_SCL_PA3 /*!< Set PA3 function to I2C1_SCL */ +#define SET_I2C1_SDA_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2C1_SDA_PB0_Msk)) | I2C1_SDA_PB0 /*!< Set PB0 function to I2C1_SDA */ +#define SET_I2C1_SDA_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~I2C1_SDA_PA2_Msk)) | I2C1_SDA_PA2 /*!< Set PA2 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2C1_SDA_PB2_Msk)) | I2C1_SDA_PB2 /*!< Set PB2 function to I2C1_SDA */ +#define SET_I2C1_SDA_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~I2C1_SDA_PC4_Msk)) | I2C1_SDA_PC4 /*!< Set PC4 function to I2C1_SDA */ +#define SET_I2C1_SDA_PI7() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~I2C1_SDA_PI7_Msk)) | I2C1_SDA_PI7 /*!< Set PI7 function to I2C1_SDA */ +#define SET_I2C1_SDA_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C1_SDA_PF1_Msk)) | I2C1_SDA_PF1 /*!< Set PF1 function to I2C1_SDA */ +#define SET_I2C1_SDA_PD4() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~I2C1_SDA_PD4_Msk)) | I2C1_SDA_PD4 /*!< Set PD4 function to I2C1_SDA */ +#define SET_I2C1_SDA_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2C1_SDA_PA13_Msk)) | I2C1_SDA_PA13 /*!< Set PA13 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~I2C1_SDA_PB10_Msk)) | I2C1_SDA_PB10 /*!< Set PB10 function to I2C1_SDA */ +#define SET_I2C1_SDA_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~I2C1_SDA_PA6_Msk)) | I2C1_SDA_PA6 /*!< Set PA6 function to I2C1_SDA */ +#define SET_I2C1_SDA_PG3() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C1_SDA_PG3_Msk)) | I2C1_SDA_PG3 /*!< Set PG3 function to I2C1_SDA */ +#define SET_I2C1_SDA_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~I2C1_SDA_PE0_Msk)) | I2C1_SDA_PE0 /*!< Set PE0 function to I2C1_SDA */ +#define SET_I2C1_SMBAL_PG0() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C1_SMBAL_PG0_Msk)) | I2C1_SMBAL_PG0 /*!< Set PG0 function to I2C1_SMBAL */ +#define SET_I2C1_SMBAL_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~I2C1_SMBAL_PC7_Msk)) | I2C1_SMBAL_PC7 /*!< Set PC7 function to I2C1_SMBAL */ +#define SET_I2C1_SMBAL_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~I2C1_SMBAL_PB9_Msk)) | I2C1_SMBAL_PB9 /*!< Set PB9 function to I2C1_SMBAL */ +#define SET_I2C1_SMBAL_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~I2C1_SMBAL_PH8_Msk)) | I2C1_SMBAL_PH8 /*!< Set PH8 function to I2C1_SMBAL */ +#define SET_I2C1_SMBSUS_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~I2C1_SMBSUS_PH9_Msk)) | I2C1_SMBSUS_PH9 /*!< Set PH9 function to I2C1_SMBSUS */ +#define SET_I2C1_SMBSUS_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~I2C1_SMBSUS_PC6_Msk)) | I2C1_SMBSUS_PC6 /*!< Set PC6 function to I2C1_SMBSUS */ +#define SET_I2C1_SMBSUS_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C1_SMBSUS_PG1_Msk)) | I2C1_SMBSUS_PG1 /*!< Set PG1 function to I2C1_SMBSUS */ +#define SET_I2C1_SMBSUS_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~I2C1_SMBSUS_PB8_Msk)) | I2C1_SMBSUS_PB8 /*!< Set PB8 function to I2C1_SMBSUS */ +#define SET_I2C2_SCL_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~I2C2_SCL_PA1_Msk)) | I2C2_SCL_PA1 /*!< Set PA1 function to I2C2_SCL */ +#define SET_I2C2_SCL_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~I2C2_SCL_PH8_Msk)) | I2C2_SCL_PH8 /*!< Set PH8 function to I2C2_SCL */ +#define SET_I2C2_SCL_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~I2C2_SCL_PB13_Msk)) | I2C2_SCL_PB13 /*!< Set PB13 function to I2C2_SCL */ +#define SET_I2C2_SCL_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~I2C2_SCL_PA11_Msk)) | I2C2_SCL_PA11 /*!< Set PA11 function to I2C2_SCL */ +#define SET_I2C2_SCL_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2C2_SCL_PA14_Msk)) | I2C2_SCL_PA14 /*!< Set PA14 function to I2C2_SCL */ +#define SET_I2C2_SCL_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~I2C2_SCL_PD1_Msk)) | I2C2_SCL_PD1 /*!< Set PD1 function to I2C2_SCL */ +#define SET_I2C2_SCL_PD9() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~I2C2_SCL_PD9_Msk)) | I2C2_SCL_PD9 /*!< Set PD9 function to I2C2_SCL */ +#define SET_I2C2_SDA_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~I2C2_SDA_PB12_Msk)) | I2C2_SDA_PB12 /*!< Set PB12 function to I2C2_SDA */ +#define SET_I2C2_SDA_PD8() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~I2C2_SDA_PD8_Msk)) | I2C2_SDA_PD8 /*!< Set PD8 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~I2C2_SDA_PA0_Msk)) | I2C2_SDA_PA0 /*!< Set PA0 function to I2C2_SDA */ +#define SET_I2C2_SDA_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~I2C2_SDA_PH9_Msk)) | I2C2_SDA_PH9 /*!< Set PH9 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2C2_SDA_PA15_Msk)) | I2C2_SDA_PA15 /*!< Set PA15 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~I2C2_SDA_PA10_Msk)) | I2C2_SDA_PA10 /*!< Set PA10 function to I2C2_SDA */ +#define SET_I2C2_SDA_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~I2C2_SDA_PD0_Msk)) | I2C2_SDA_PD0 /*!< Set PD0 function to I2C2_SDA */ +#define SET_I2C2_SMBAL_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~I2C2_SMBAL_PB15_Msk)) | I2C2_SMBAL_PB15 /*!< Set PB15 function to I2C2_SMBAL */ +#define SET_I2C2_SMBSUS_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~I2C2_SMBSUS_PB14_Msk)) | I2C2_SMBSUS_PB14 /*!< Set PB14 function to I2C2_SMBSUS */ +#define SET_I2C3_SCL_PG7() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~I2C3_SCL_PG7_Msk)) | I2C3_SCL_PG7 /*!< Set PG7 function to I2C3_SCL */ +#define SET_I2C3_SCL_PG0() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C3_SCL_PG0_Msk)) | I2C3_SCL_PG0 /*!< Set PG0 function to I2C3_SCL */ +#define SET_I2C3_SCL_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2C3_SCL_PC3_Msk)) | I2C3_SCL_PC3 /*!< Set PC3 function to I2C3_SCL */ +#define SET_I2C3_SCL_PI14() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~I2C3_SCL_PI14_Msk)) | I2C3_SCL_PI14 /*!< Set PI14 function to I2C3_SCL */ +#define SET_I2C3_SDA_PG8() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~I2C3_SDA_PG8_Msk)) | I2C3_SDA_PG8 /*!< Set PG8 function to I2C3_SDA */ +#define SET_I2C3_SDA_PI15() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~I2C3_SDA_PI15_Msk)) | I2C3_SDA_PI15 /*!< Set PI15 function to I2C3_SDA */ +#define SET_I2C3_SDA_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2C3_SDA_PC2_Msk)) | I2C3_SDA_PC2 /*!< Set PC2 function to I2C3_SDA */ +#define SET_I2C3_SDA_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C3_SDA_PG1_Msk)) | I2C3_SDA_PG1 /*!< Set PG1 function to I2C3_SDA */ +#define SET_I2C3_SMBAL_PG2() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C3_SMBAL_PG2_Msk)) | I2C3_SMBAL_PG2 /*!< Set PG2 function to I2C3_SMBAL */ +#define SET_I2C3_SMBAL_PI12() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~I2C3_SMBAL_PI12_Msk)) | I2C3_SMBAL_PI12 /*!< Set PI12 function to I2C3_SMBAL */ +#define SET_I2C3_SMBAL_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~I2C3_SMBAL_PC5_Msk)) | I2C3_SMBAL_PC5 /*!< Set PC5 function to I2C3_SMBAL */ +#define SET_I2C3_SMBAL_PG5() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~I2C3_SMBAL_PG5_Msk)) | I2C3_SMBAL_PG5 /*!< Set PG5 function to I2C3_SMBAL */ +#define SET_I2C3_SMBSUS_PG6() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~I2C3_SMBSUS_PG6_Msk)) | I2C3_SMBSUS_PG6 /*!< Set PG6 function to I2C3_SMBSUS */ +#define SET_I2C3_SMBSUS_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~I2C3_SMBSUS_PC4_Msk)) | I2C3_SMBSUS_PC4 /*!< Set PC4 function to I2C3_SMBSUS */ +#define SET_I2C3_SMBSUS_PG3() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~I2C3_SMBSUS_PG3_Msk)) | I2C3_SMBSUS_PG3 /*!< Set PG3 function to I2C3_SMBSUS */ +#define SET_I2C3_SMBSUS_PI13() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~I2C3_SMBSUS_PI13_Msk)) | I2C3_SMBSUS_PI13 /*!< Set PI13 function to I2C3_SMBSUS */ +#define SET_I2C4_SCL_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~I2C4_SCL_PJ10_Msk)) | I2C4_SCL_PJ10 /*!< Set PJ10 function to I2C4_SCL */ +#define SET_I2C4_SCL_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~I2C4_SCL_PG9_Msk)) | I2C4_SCL_PG9 /*!< Set PG9 function to I2C4_SCL */ +#define SET_I2C4_SCL_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~I2C4_SCL_PC12_Msk)) | I2C4_SCL_PC12 /*!< Set PC12 function to I2C4_SCL */ +#define SET_I2C4_SCL_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~I2C4_SCL_PF5_Msk)) | I2C4_SCL_PF5 /*!< Set PF5 function to I2C4_SCL */ +#define SET_I2C4_SDA_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~I2C4_SDA_PJ11_Msk)) | I2C4_SDA_PJ11 /*!< Set PJ11 function to I2C4_SDA */ +#define SET_I2C4_SDA_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~I2C4_SDA_PG10_Msk)) | I2C4_SDA_PG10 /*!< Set PG10 function to I2C4_SDA */ +#define SET_I2C4_SDA_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~I2C4_SDA_PC11_Msk)) | I2C4_SDA_PC11 /*!< Set PC11 function to I2C4_SDA */ +#define SET_I2C4_SDA_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~I2C4_SDA_PF4_Msk)) | I2C4_SDA_PF4 /*!< Set PF4 function to I2C4_SDA */ +#define SET_I2C4_SMBAL_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~I2C4_SMBAL_PJ12_Msk)) | I2C4_SMBAL_PJ12 /*!< Set PJ12 function to I2C4_SMBAL */ +#define SET_I2C4_SMBAL_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~I2C4_SMBAL_PG11_Msk)) | I2C4_SMBAL_PG11 /*!< Set PG11 function to I2C4_SMBAL */ +#define SET_I2C4_SMBAL_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C4_SMBAL_PF3_Msk)) | I2C4_SMBAL_PF3 /*!< Set PF3 function to I2C4_SMBAL */ +#define SET_I2C4_SMBAL_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~I2C4_SMBAL_PC10_Msk)) | I2C4_SMBAL_PC10 /*!< Set PC10 function to I2C4_SMBAL */ +#define SET_I2C4_SMBSUS_PJ13() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~I2C4_SMBSUS_PJ13_Msk)) | I2C4_SMBSUS_PJ13 /*!< Set PJ13 function to I2C4_SMBSUS */ +#define SET_I2C4_SMBSUS_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~I2C4_SMBSUS_PG12_Msk)) | I2C4_SMBSUS_PG12 /*!< Set PG12 function to I2C4_SMBSUS */ +#define SET_I2C4_SMBSUS_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~I2C4_SMBSUS_PC9_Msk)) | I2C4_SMBSUS_PC9 /*!< Set PC9 function to I2C4_SMBSUS */ +#define SET_I2C4_SMBSUS_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2C4_SMBSUS_PF2_Msk)) | I2C4_SMBSUS_PF2 /*!< Set PF2 function to I2C4_SMBSUS */ +#define SET_I2S0_BCLK_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~I2S0_BCLK_PE8_Msk)) | I2S0_BCLK_PE8 /*!< Set PE8 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~I2S0_BCLK_PF10_Msk)) | I2S0_BCLK_PF10 /*!< Set PF10 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~I2S0_BCLK_PE1_Msk)) | I2S0_BCLK_PE1 /*!< Set PE1 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2S0_BCLK_PA12_Msk)) | I2S0_BCLK_PA12 /*!< Set PA12 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~I2S0_BCLK_PB5_Msk)) | I2S0_BCLK_PB5 /*!< Set PB5 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PI6() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~I2S0_BCLK_PI6_Msk)) | I2S0_BCLK_PI6 /*!< Set PI6 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~I2S0_BCLK_PC4_Msk)) | I2S0_BCLK_PC4 /*!< Set PC4 function to I2S0_BCLK */ +#define SET_I2S0_DI_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2S0_DI_PB3_Msk)) | I2S0_DI_PB3 /*!< Set PB3 function to I2S0_DI */ +#define SET_I2S0_DI_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2S0_DI_PC2_Msk)) | I2S0_DI_PC2 /*!< Set PC2 function to I2S0_DI */ +#define SET_I2S0_DI_PI8() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~I2S0_DI_PI8_Msk)) | I2S0_DI_PI8 /*!< Set PI8 function to I2S0_DI */ +#define SET_I2S0_DI_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2S0_DI_PA14_Msk)) | I2S0_DI_PA14 /*!< Set PA14 function to I2S0_DI */ +#define SET_I2S0_DI_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~I2S0_DI_PF8_Msk)) | I2S0_DI_PF8 /*!< Set PF8 function to I2S0_DI */ +#define SET_I2S0_DI_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~I2S0_DI_PH8_Msk)) | I2S0_DI_PH8 /*!< Set PH8 function to I2S0_DI */ +#define SET_I2S0_DI_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~I2S0_DI_PE10_Msk)) | I2S0_DI_PE10 /*!< Set PE10 function to I2S0_DI */ +#define SET_I2S0_DO_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~I2S0_DO_PH9_Msk)) | I2S0_DO_PH9 /*!< Set PH9 function to I2S0_DO */ +#define SET_I2S0_DO_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2S0_DO_PC1_Msk)) | I2S0_DO_PC1 /*!< Set PC1 function to I2S0_DO */ +#define SET_I2S0_DO_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2S0_DO_PA15_Msk)) | I2S0_DO_PA15 /*!< Set PA15 function to I2S0_DO */ +#define SET_I2S0_DO_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2S0_DO_PB2_Msk)) | I2S0_DO_PB2 /*!< Set PB2 function to I2S0_DO */ +#define SET_I2S0_DO_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~I2S0_DO_PF7_Msk)) | I2S0_DO_PF7 /*!< Set PF7 function to I2S0_DO */ +#define SET_I2S0_DO_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2S0_DO_PF0_Msk)) | I2S0_DO_PF0 /*!< Set PF0 function to I2S0_DO */ +#define SET_I2S0_DO_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~I2S0_DO_PE11_Msk)) | I2S0_DO_PE11 /*!< Set PE11 function to I2S0_DO */ +#define SET_I2S0_DO_PI9() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~I2S0_DO_PI9_Msk)) | I2S0_DO_PI9 /*!< Set PI9 function to I2S0_DO */ +#define SET_I2S0_LRCK_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~I2S0_LRCK_PF6_Msk)) | I2S0_LRCK_PF6 /*!< Set PF6 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~I2S0_LRCK_PE12_Msk)) | I2S0_LRCK_PE12 /*!< Set PE12 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~I2S0_LRCK_PH10_Msk)) | I2S0_LRCK_PH10 /*!< Set PH10 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2S0_LRCK_PB1_Msk)) | I2S0_LRCK_PB1 /*!< Set PB1 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~I2S0_LRCK_PF1_Msk)) | I2S0_LRCK_PF1 /*!< Set PF1 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2S0_LRCK_PC0_Msk)) | I2S0_LRCK_PC0 /*!< Set PC0 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PI10() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~I2S0_LRCK_PI10_Msk)) | I2S0_LRCK_PI10 /*!< Set PI10 function to I2S0_LRCK */ +#define SET_I2S0_MCLK_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~I2S0_MCLK_PE0_Msk)) | I2S0_MCLK_PE0 /*!< Set PE0 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~I2S0_MCLK_PB4_Msk)) | I2S0_MCLK_PB4 /*!< Set PB4 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~I2S0_MCLK_PF9_Msk)) | I2S0_MCLK_PF9 /*!< Set PF9 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~I2S0_MCLK_PE9_Msk)) | I2S0_MCLK_PE9 /*!< Set PE9 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PI7() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~I2S0_MCLK_PI7_Msk)) | I2S0_MCLK_PI7 /*!< Set PI7 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~I2S0_MCLK_PA13_Msk)) | I2S0_MCLK_PA13 /*!< Set PA13 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~I2S0_MCLK_PC3_Msk)) | I2S0_MCLK_PC3 /*!< Set PC3 function to I2S0_MCLK */ +#define SET_I2S1_BCLK_PD14() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~I2S1_BCLK_PD14_Msk)) | I2S1_BCLK_PD14 /*!< Set PD14 function to I2S1_BCLK */ +#define SET_I2S1_BCLK_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~I2S1_BCLK_PA11_Msk)) | I2S1_BCLK_PA11 /*!< Set PA11 function to I2S1_BCLK */ +#define SET_I2S1_BCLK_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~I2S1_BCLK_PD3_Msk)) | I2S1_BCLK_PD3 /*!< Set PD3 function to I2S1_BCLK */ +#define SET_I2S1_DI_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~I2S1_DI_PD1_Msk)) | I2S1_DI_PD1 /*!< Set PD1 function to I2S1_DI */ +#define SET_I2S1_DI_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~I2S1_DI_PA9_Msk)) | I2S1_DI_PA9 /*!< Set PA9 function to I2S1_DI */ +#define SET_I2S1_DI_PG6() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~I2S1_DI_PG6_Msk)) | I2S1_DI_PG6 /*!< Set PG6 function to I2S1_DI */ +#define SET_I2S1_DO_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~I2S1_DO_PD0_Msk)) | I2S1_DO_PD0 /*!< Set PD0 function to I2S1_DO */ +#define SET_I2S1_DO_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~I2S1_DO_PA8_Msk)) | I2S1_DO_PA8 /*!< Set PA8 function to I2S1_DO */ +#define SET_I2S1_DO_PG7() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~I2S1_DO_PG7_Msk)) | I2S1_DO_PG7 /*!< Set PG7 function to I2S1_DO */ +#define SET_I2S1_LRCK_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~I2S1_LRCK_PB0_Msk)) | I2S1_LRCK_PB0 /*!< Set PB0 function to I2S1_LRCK */ +#define SET_I2S1_LRCK_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~I2S1_LRCK_PD13_Msk)) | I2S1_LRCK_PD13 /*!< Set PD13 function to I2S1_LRCK */ +#define SET_I2S1_LRCK_PG8() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~I2S1_LRCK_PG8_Msk)) | I2S1_LRCK_PG8 /*!< Set PG8 function to I2S1_LRCK */ +#define SET_I2S1_MCLK_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~I2S1_MCLK_PD2_Msk)) | I2S1_MCLK_PD2 /*!< Set PD2 function to I2S1_MCLK */ +#define SET_I2S1_MCLK_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~I2S1_MCLK_PA10_Msk)) | I2S1_MCLK_PA10 /*!< Set PA10 function to I2S1_MCLK */ +#define SET_I2S1_MCLK_PG5() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~I2S1_MCLK_PG5_Msk)) | I2S1_MCLK_PG5 /*!< Set PG5 function to I2S1_MCLK */ +#define SET_ICE_CLK_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~ICE_CLK_PF1_Msk)) | ICE_CLK_PF1 /*!< Set PF1 function to ICE_CLK */ +#define SET_ICE_DAT_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~ICE_DAT_PF0_Msk)) | ICE_DAT_PF0 /*!< Set PF0 function to ICE_DAT */ +#define SET_INT0_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~INT0_PA6_Msk)) | INT0_PA6 /*!< Set PA6 function to INT0 */ +#define SET_INT0_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~INT0_PB5_Msk)) | INT0_PB5 /*!< Set PB5 function to INT0 */ +#define SET_INT1_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~INT1_PA7_Msk)) | INT1_PA7 /*!< Set PA7 function to INT1 */ +#define SET_INT1_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~INT1_PB4_Msk)) | INT1_PB4 /*!< Set PB4 function to INT1 */ +#define SET_INT2_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~INT2_PB3_Msk)) | INT2_PB3 /*!< Set PB3 function to INT2 */ +#define SET_INT2_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~INT2_PC6_Msk)) | INT2_PC6 /*!< Set PC6 function to INT2 */ +#define SET_INT3_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~INT3_PC7_Msk)) | INT3_PC7 /*!< Set PC7 function to INT3 */ +#define SET_INT3_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~INT3_PB2_Msk)) | INT3_PB2 /*!< Set PB2 function to INT3 */ +#define SET_INT4_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~INT4_PA8_Msk)) | INT4_PA8 /*!< Set PA8 function to INT4 */ +#define SET_INT4_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~INT4_PB6_Msk)) | INT4_PB6 /*!< Set PB6 function to INT4 */ +#define SET_INT5_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~INT5_PD12_Msk)) | INT5_PD12 /*!< Set PD12 function to INT5 */ +#define SET_INT5_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~INT5_PB7_Msk)) | INT5_PB7 /*!< Set PB7 function to INT5 */ +#define SET_INT6_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~INT6_PB8_Msk)) | INT6_PB8 /*!< Set PB8 function to INT6 */ +#define SET_INT6_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~INT6_PD11_Msk)) | INT6_PD11 /*!< Set PD11 function to INT6 */ +#define SET_INT7_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~INT7_PB9_Msk)) | INT7_PB9 /*!< Set PB9 function to INT7 */ +#define SET_INT7_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~INT7_PD10_Msk)) | INT7_PD10 /*!< Set PD10 function to INT7 */ +#define SET_TRACE_SWO_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~TRACE_SWO_PF6_Msk)) | TRACE_SWO_PF6 /*!< Set PF6 function to TRACE_SWO */ +#define SET_TRACE_SWO_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~TRACE_SWO_PC14_Msk)) | TRACE_SWO_PC14 /*!< Set PC14 function to TRACE_SWO */ +#define SET_TRACE_SWO_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~TRACE_SWO_PE13_Msk)) | TRACE_SWO_PE13 /*!< Set PE13 function to TRACE_SWO */ +#define SET_KPI_COL0_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~KPI_COL0_PA6_Msk)) | KPI_COL0_PA6 /*!< Set PA6 function to KPI_COL0 */ +#define SET_KPI_COL0_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~KPI_COL0_PB15_Msk)) | KPI_COL0_PB15 /*!< Set PB15 function to KPI_COL0 */ +#define SET_KPI_COL1_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~KPI_COL1_PA7_Msk)) | KPI_COL1_PA7 /*!< Set PA7 function to KPI_COL1 */ +#define SET_KPI_COL1_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~KPI_COL1_PB14_Msk)) | KPI_COL1_PB14 /*!< Set PB14 function to KPI_COL1 */ +#define SET_KPI_COL2_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~KPI_COL2_PC6_Msk)) | KPI_COL2_PC6 /*!< Set PC6 function to KPI_COL2 */ +#define SET_KPI_COL2_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~KPI_COL2_PB13_Msk)) | KPI_COL2_PB13 /*!< Set PB13 function to KPI_COL2 */ +#define SET_KPI_COL3_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~KPI_COL3_PC7_Msk)) | KPI_COL3_PC7 /*!< Set PC7 function to KPI_COL3 */ +#define SET_KPI_COL3_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~KPI_COL3_PB12_Msk)) | KPI_COL3_PB12 /*!< Set PB12 function to KPI_COL3 */ +#define SET_KPI_COL4_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~KPI_COL4_PB7_Msk)) | KPI_COL4_PB7 /*!< Set PB7 function to KPI_COL4 */ +#define SET_KPI_COL4_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~KPI_COL4_PC8_Msk)) | KPI_COL4_PC8 /*!< Set PC8 function to KPI_COL4 */ +#define SET_KPI_COL5_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~KPI_COL5_PB6_Msk)) | KPI_COL5_PB6 /*!< Set PB6 function to KPI_COL5 */ +#define SET_KPI_COL5_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~KPI_COL5_PE13_Msk)) | KPI_COL5_PE13 /*!< Set PE13 function to KPI_COL5 */ +#define SET_KPI_COL6_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~KPI_COL6_PE12_Msk)) | KPI_COL6_PE12 /*!< Set PE12 function to KPI_COL6 */ +#define SET_KPI_COL6_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~KPI_COL6_PB5_Msk)) | KPI_COL6_PB5 /*!< Set PB5 function to KPI_COL6 */ +#define SET_KPI_COL7_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~KPI_COL7_PE11_Msk)) | KPI_COL7_PE11 /*!< Set PE11 function to KPI_COL7 */ +#define SET_KPI_COL7_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~KPI_COL7_PB4_Msk)) | KPI_COL7_PB4 /*!< Set PB4 function to KPI_COL7 */ +#define SET_KPI_ROW0_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~KPI_ROW0_PC5_Msk)) | KPI_ROW0_PC5 /*!< Set PC5 function to KPI_ROW0 */ +#define SET_KPI_ROW0_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~KPI_ROW0_PB3_Msk)) | KPI_ROW0_PB3 /*!< Set PB3 function to KPI_ROW0 */ +#define SET_KPI_ROW1_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~KPI_ROW1_PC4_Msk)) | KPI_ROW1_PC4 /*!< Set PC4 function to KPI_ROW1 */ +#define SET_KPI_ROW1_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~KPI_ROW1_PB2_Msk)) | KPI_ROW1_PB2 /*!< Set PB2 function to KPI_ROW1 */ +#define SET_KPI_ROW2_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~KPI_ROW2_PB1_Msk)) | KPI_ROW2_PB1 /*!< Set PB1 function to KPI_ROW2 */ +#define SET_KPI_ROW2_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~KPI_ROW2_PC3_Msk)) | KPI_ROW2_PC3 /*!< Set PC3 function to KPI_ROW2 */ +#define SET_KPI_ROW3_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~KPI_ROW3_PC2_Msk)) | KPI_ROW3_PC2 /*!< Set PC2 function to KPI_ROW3 */ +#define SET_KPI_ROW3_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~KPI_ROW3_PB0_Msk)) | KPI_ROW3_PB0 /*!< Set PB0 function to KPI_ROW3 */ +#define SET_KPI_ROW4_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~KPI_ROW4_PA11_Msk)) | KPI_ROW4_PA11 /*!< Set PA11 function to KPI_ROW4 */ +#define SET_KPI_ROW4_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~KPI_ROW4_PC1_Msk)) | KPI_ROW4_PC1 /*!< Set PC1 function to KPI_ROW4 */ +#define SET_KPI_ROW5_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~KPI_ROW5_PA10_Msk)) | KPI_ROW5_PA10 /*!< Set PA10 function to KPI_ROW5 */ +#define SET_KPI_ROW5_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~KPI_ROW5_PC0_Msk)) | KPI_ROW5_PC0 /*!< Set PC0 function to KPI_ROW5 */ +#define SET_PSIO0_CH0_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~PSIO0_CH0_PC5_Msk)) | PSIO0_CH0_PC5 /*!< Set PC5 function to PSIO0_CH0 */ +#define SET_PSIO0_CH0_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~PSIO0_CH0_PB15_Msk)) | PSIO0_CH0_PB15 /*!< Set PB15 function to PSIO0_CH0 */ +#define SET_PSIO0_CH0_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~PSIO0_CH0_PE7_Msk)) | PSIO0_CH0_PE7 /*!< Set PE7 function to PSIO0_CH0 */ +#define SET_PSIO0_CH0_PE14() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~PSIO0_CH0_PE14_Msk)) | PSIO0_CH0_PE14 /*!< Set PE14 function to PSIO0_CH0 */ +#define SET_PSIO0_CH1_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~PSIO0_CH1_PC4_Msk)) | PSIO0_CH1_PC4 /*!< Set PC4 function to PSIO0_CH1 */ +#define SET_PSIO0_CH1_PE15() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~PSIO0_CH1_PE15_Msk)) | PSIO0_CH1_PE15 /*!< Set PE15 function to PSIO0_CH1 */ +#define SET_PSIO0_CH1_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~PSIO0_CH1_PE6_Msk)) | PSIO0_CH1_PE6 /*!< Set PE6 function to PSIO0_CH1 */ +#define SET_PSIO0_CH1_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~PSIO0_CH1_PB14_Msk)) | PSIO0_CH1_PB14 /*!< Set PB14 function to PSIO0_CH1 */ +#define SET_PSIO0_CH2_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~PSIO0_CH2_PC3_Msk)) | PSIO0_CH2_PC3 /*!< Set PC3 function to PSIO0_CH2 */ +#define SET_PSIO0_CH2_PD9() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~PSIO0_CH2_PD9_Msk)) | PSIO0_CH2_PD9 /*!< Set PD9 function to PSIO0_CH2 */ +#define SET_PSIO0_CH2_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~PSIO0_CH2_PE5_Msk)) | PSIO0_CH2_PE5 /*!< Set PE5 function to PSIO0_CH2 */ +#define SET_PSIO0_CH2_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~PSIO0_CH2_PB13_Msk)) | PSIO0_CH2_PB13 /*!< Set PB13 function to PSIO0_CH2 */ +#define SET_PSIO0_CH3_PD8() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~PSIO0_CH3_PD8_Msk)) | PSIO0_CH3_PD8 /*!< Set PD8 function to PSIO0_CH3 */ +#define SET_PSIO0_CH3_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~PSIO0_CH3_PC2_Msk)) | PSIO0_CH3_PC2 /*!< Set PC2 function to PSIO0_CH3 */ +#define SET_PSIO0_CH3_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~PSIO0_CH3_PE4_Msk)) | PSIO0_CH3_PE4 /*!< Set PE4 function to PSIO0_CH3 */ +#define SET_PSIO0_CH3_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~PSIO0_CH3_PB12_Msk)) | PSIO0_CH3_PB12 /*!< Set PB12 function to PSIO0_CH3 */ +#define SET_PSIO0_CH4_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~PSIO0_CH4_PD7_Msk)) | PSIO0_CH4_PD7 /*!< Set PD7 function to PSIO0_CH4 */ +#define SET_PSIO0_CH4_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~PSIO0_CH4_PA12_Msk)) | PSIO0_CH4_PA12 /*!< Set PA12 function to PSIO0_CH4 */ +#define SET_PSIO0_CH4_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~PSIO0_CH4_PB5_Msk)) | PSIO0_CH4_PB5 /*!< Set PB5 function to PSIO0_CH4 */ +#define SET_PSIO0_CH4_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~PSIO0_CH4_PA3_Msk)) | PSIO0_CH4_PA3 /*!< Set PA3 function to PSIO0_CH4 */ +#define SET_PSIO0_CH5_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~PSIO0_CH5_PA13_Msk)) | PSIO0_CH5_PA13 /*!< Set PA13 function to PSIO0_CH5 */ +#define SET_PSIO0_CH5_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~PSIO0_CH5_PB4_Msk)) | PSIO0_CH5_PB4 /*!< Set PB4 function to PSIO0_CH5 */ +#define SET_PSIO0_CH5_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~PSIO0_CH5_PA2_Msk)) | PSIO0_CH5_PA2 /*!< Set PA2 function to PSIO0_CH5 */ +#define SET_PSIO0_CH5_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~PSIO0_CH5_PD6_Msk)) | PSIO0_CH5_PD6 /*!< Set PD6 function to PSIO0_CH5 */ +#define SET_PSIO0_CH6_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~PSIO0_CH6_PB3_Msk)) | PSIO0_CH6_PB3 /*!< Set PB3 function to PSIO0_CH6 */ +#define SET_PSIO0_CH6_PD5() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~PSIO0_CH6_PD5_Msk)) | PSIO0_CH6_PD5 /*!< Set PD5 function to PSIO0_CH6 */ +#define SET_PSIO0_CH6_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~PSIO0_CH6_PA1_Msk)) | PSIO0_CH6_PA1 /*!< Set PA1 function to PSIO0_CH6 */ +#define SET_PSIO0_CH6_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~PSIO0_CH6_PA14_Msk)) | PSIO0_CH6_PA14 /*!< Set PA14 function to PSIO0_CH6 */ +#define SET_PSIO0_CH7_PD4() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~PSIO0_CH7_PD4_Msk)) | PSIO0_CH7_PD4 /*!< Set PD4 function to PSIO0_CH7 */ +#define SET_PSIO0_CH7_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~PSIO0_CH7_PA15_Msk)) | PSIO0_CH7_PA15 /*!< Set PA15 function to PSIO0_CH7 */ +#define SET_PSIO0_CH7_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~PSIO0_CH7_PB2_Msk)) | PSIO0_CH7_PB2 /*!< Set PB2 function to PSIO0_CH7 */ +#define SET_PSIO0_CH7_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~PSIO0_CH7_PA0_Msk)) | PSIO0_CH7_PA0 /*!< Set PA0 function to PSIO0_CH7 */ +#define SET_EQEI0_A_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EQEI0_A_PE3_Msk)) | EQEI0_A_PE3 /*!< Set PE3 function to EQEI0_A */ +#define SET_EQEI0_A_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EQEI0_A_PA4_Msk)) | EQEI0_A_PA4 /*!< Set PA4 function to EQEI0_A */ +#define SET_EQEI0_A_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EQEI0_A_PD11_Msk)) | EQEI0_A_PD11 /*!< Set PD11 function to EQEI0_A */ +#define SET_EQEI0_B_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EQEI0_B_PA3_Msk)) | EQEI0_B_PA3 /*!< Set PA3 function to EQEI0_B */ +#define SET_EQEI0_B_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~EQEI0_B_PD10_Msk)) | EQEI0_B_PD10 /*!< Set PD10 function to EQEI0_B */ +#define SET_EQEI0_B_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~EQEI0_B_PE2_Msk)) | EQEI0_B_PE2 /*!< Set PE2 function to EQEI0_B */ +#define SET_EQEI0_INDEX_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EQEI0_INDEX_PE4_Msk)) | EQEI0_INDEX_PE4 /*!< Set PE4 function to EQEI0_INDEX */ +#define SET_EQEI0_INDEX_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~EQEI0_INDEX_PA5_Msk)) | EQEI0_INDEX_PA5 /*!< Set PA5 function to EQEI0_INDEX */ +#define SET_EQEI0_INDEX_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EQEI0_INDEX_PD12_Msk)) | EQEI0_INDEX_PD12 /*!< Set PD12 function to EQEI0_INDEX */ +#define SET_EQEI1_A_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EQEI1_A_PA9_Msk)) | EQEI1_A_PA9 /*!< Set PA9 function to EQEI1_A */ +#define SET_EQEI1_A_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~EQEI1_A_PA13_Msk)) | EQEI1_A_PA13 /*!< Set PA13 function to EQEI1_A */ +#define SET_EQEI1_A_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EQEI1_A_PE6_Msk)) | EQEI1_A_PE6 /*!< Set PE6 function to EQEI1_A */ +#define SET_EQEI1_B_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EQEI1_B_PE5_Msk)) | EQEI1_B_PE5 /*!< Set PE5 function to EQEI1_B */ +#define SET_EQEI1_B_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EQEI1_B_PA8_Msk)) | EQEI1_B_PA8 /*!< Set PA8 function to EQEI1_B */ +#define SET_EQEI1_B_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~EQEI1_B_PA14_Msk)) | EQEI1_B_PA14 /*!< Set PA14 function to EQEI1_B */ +#define SET_EQEI1_INDEX_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~EQEI1_INDEX_PA10_Msk)) | EQEI1_INDEX_PA10 /*!< Set PA10 function to EQEI1_INDEX */ +#define SET_EQEI1_INDEX_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~EQEI1_INDEX_PE7_Msk)) | EQEI1_INDEX_PE7 /*!< Set PE7 function to EQEI1_INDEX */ +#define SET_EQEI1_INDEX_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~EQEI1_INDEX_PA12_Msk)) | EQEI1_INDEX_PA12 /*!< Set PA12 function to EQEI1_INDEX */ +#define SET_EQEI2_A_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EQEI2_A_PE9_Msk)) | EQEI2_A_PE9 /*!< Set PE9 function to EQEI2_A */ +#define SET_EQEI2_A_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EQEI2_A_PF5_Msk)) | EQEI2_A_PF5 /*!< Set PF5 function to EQEI2_A */ +#define SET_EQEI2_A_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EQEI2_A_PD0_Msk)) | EQEI2_A_PD0 /*!< Set PD0 function to EQEI2_A */ +#define SET_EQEI2_B_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EQEI2_B_PF4_Msk)) | EQEI2_B_PF4 /*!< Set PF4 function to EQEI2_B */ +#define SET_EQEI2_B_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EQEI2_B_PE10_Msk)) | EQEI2_B_PE10 /*!< Set PE10 function to EQEI2_B */ +#define SET_EQEI2_B_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~EQEI2_B_PD13_Msk)) | EQEI2_B_PD13 /*!< Set PD13 function to EQEI2_B */ +#define SET_EQEI2_INDEX_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~EQEI2_INDEX_PE8_Msk)) | EQEI2_INDEX_PE8 /*!< Set PE8 function to EQEI2_INDEX */ +#define SET_EQEI2_INDEX_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EQEI2_INDEX_PD1_Msk)) | EQEI2_INDEX_PD1 /*!< Set PD1 function to EQEI2_INDEX */ +#define SET_EQEI2_INDEX_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~EQEI2_INDEX_PF6_Msk)) | EQEI2_INDEX_PF6 /*!< Set PF6 function to EQEI2_INDEX */ +#define SET_EQEI3_A_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EQEI3_A_PD3_Msk)) | EQEI3_A_PD3 /*!< Set PD3 function to EQEI3_A */ +#define SET_EQEI3_A_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EQEI3_A_PA1_Msk)) | EQEI3_A_PA1 /*!< Set PA1 function to EQEI3_A */ +#define SET_EQEI3_B_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EQEI3_B_PA0_Msk)) | EQEI3_B_PA0 /*!< Set PA0 function to EQEI3_B */ +#define SET_EQEI3_B_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~EQEI3_B_PD2_Msk)) | EQEI3_B_PD2 /*!< Set PD2 function to EQEI3_B */ +#define SET_EQEI3_INDEX_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~EQEI3_INDEX_PA2_Msk)) | EQEI3_INDEX_PA2 /*!< Set PA2 function to EQEI3_INDEX */ +#define SET_EQEI3_INDEX_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~EQEI3_INDEX_PA15_Msk)) | EQEI3_INDEX_PA15 /*!< Set PA15 function to EQEI3_INDEX */ +#define SET_QSPI0_CLK_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~QSPI0_CLK_PH8_Msk)) | QSPI0_CLK_PH8 /*!< Set PH8 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~QSPI0_CLK_PA2_Msk)) | QSPI0_CLK_PA2 /*!< Set PA2 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PI15() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~QSPI0_CLK_PI15_Msk)) | QSPI0_CLK_PI15 /*!< Set PI15 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI0_CLK_PC2_Msk)) | QSPI0_CLK_PC2 /*!< Set PC2 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~QSPI0_CLK_PF2_Msk)) | QSPI0_CLK_PF2 /*!< Set PF2 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~QSPI0_CLK_PC14_Msk)) | QSPI0_CLK_PC14 /*!< Set PC14 function to QSPI0_CLK */ +#define SET_QSPI0_MISO0_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI0_MISO0_PC1_Msk)) | QSPI0_MISO0_PC1 /*!< Set PC1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO0_PJ0() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~QSPI0_MISO0_PJ0_Msk)) | QSPI0_MISO0_PJ0 /*!< Set PJ0 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO0_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~QSPI0_MISO0_PE1_Msk)) | QSPI0_MISO0_PE1 /*!< Set PE1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO0_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~QSPI0_MISO0_PA1_Msk)) | QSPI0_MISO0_PA1 /*!< Set PA1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO1_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~QSPI0_MISO1_PB1_Msk)) | QSPI0_MISO1_PB1 /*!< Set PB1 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PI12() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~QSPI0_MISO1_PI12_Msk)) | QSPI0_MISO1_PI12 /*!< Set PI12 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~QSPI0_MISO1_PC5_Msk)) | QSPI0_MISO1_PC5 /*!< Set PC5 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~QSPI0_MISO1_PH10_Msk)) | QSPI0_MISO1_PH10 /*!< Set PH10 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~QSPI0_MISO1_PA5_Msk)) | QSPI0_MISO1_PA5 /*!< Set PA5 function to QSPI0_MISO1 */ +#define SET_QSPI0_MOSI0_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~QSPI0_MOSI0_PE0_Msk)) | QSPI0_MOSI0_PE0 /*!< Set PE0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI0_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI0_MOSI0_PC0_Msk)) | QSPI0_MOSI0_PC0 /*!< Set PC0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI0_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~QSPI0_MOSI0_PA0_Msk)) | QSPI0_MOSI0_PA0 /*!< Set PA0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI0_PJ1() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~QSPI0_MOSI0_PJ1_Msk)) | QSPI0_MOSI0_PJ1 /*!< Set PJ1 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI1_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~QSPI0_MOSI1_PA4_Msk)) | QSPI0_MOSI1_PA4 /*!< Set PA4 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~QSPI0_MOSI1_PC4_Msk)) | QSPI0_MOSI1_PC4 /*!< Set PC4 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PH11() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~QSPI0_MOSI1_PH11_Msk)) | QSPI0_MOSI1_PH11 /*!< Set PH11 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PI13() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~QSPI0_MOSI1_PI13_Msk)) | QSPI0_MOSI1_PI13 /*!< Set PI13 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~QSPI0_MOSI1_PB0_Msk)) | QSPI0_MOSI1_PB0 /*!< Set PB0 function to QSPI0_MOSI1 */ +#define SET_QSPI0_SS_PI14() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~QSPI0_SS_PI14_Msk)) | QSPI0_SS_PI14 /*!< Set PI14 function to QSPI0_SS */ +#define SET_QSPI0_SS_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~QSPI0_SS_PA3_Msk)) | QSPI0_SS_PA3 /*!< Set PA3 function to QSPI0_SS */ +#define SET_QSPI0_SS_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI0_SS_PC3_Msk)) | QSPI0_SS_PC3 /*!< Set PC3 function to QSPI0_SS */ +#define SET_QSPI0_SS_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~QSPI0_SS_PH9_Msk)) | QSPI0_SS_PH9 /*!< Set PH9 function to QSPI0_SS */ +#define SET_QSPI1_CLK_PH15() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~QSPI1_CLK_PH15_Msk)) | QSPI1_CLK_PH15 /*!< Set PH15 function to QSPI1_CLK */ +#define SET_QSPI1_CLK_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~QSPI1_CLK_PC4_Msk)) | QSPI1_CLK_PC4 /*!< Set PC4 function to QSPI1_CLK */ +#define SET_QSPI1_CLK_PJ3() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~QSPI1_CLK_PJ3_Msk)) | QSPI1_CLK_PJ3 /*!< Set PJ3 function to QSPI1_CLK */ +#define SET_QSPI1_CLK_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~QSPI1_CLK_PG12_Msk)) | QSPI1_CLK_PG12 /*!< Set PG12 function to QSPI1_CLK */ +#define SET_QSPI1_CLK_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI1_CLK_PC0_Msk)) | QSPI1_CLK_PC0 /*!< Set PC0 function to QSPI1_CLK */ +#define SET_QSPI1_MISO0_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~QSPI1_MISO0_PD7_Msk)) | QSPI1_MISO0_PD7 /*!< Set PD7 function to QSPI1_MISO0 */ +#define SET_QSPI1_MISO0_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~QSPI1_MISO0_PA12_Msk)) | QSPI1_MISO0_PA12 /*!< Set PA12 function to QSPI1_MISO0 */ +#define SET_QSPI1_MISO0_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI1_MISO0_PC3_Msk)) | QSPI1_MISO0_PC3 /*!< Set PC3 function to QSPI1_MISO0 */ +#define SET_QSPI1_MISO0_PJ4() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~QSPI1_MISO0_PJ4_Msk)) | QSPI1_MISO0_PJ4 /*!< Set PJ4 function to QSPI1_MISO0 */ +#define SET_QSPI1_MISO0_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~QSPI1_MISO0_PG13_Msk)) | QSPI1_MISO0_PG13 /*!< Set PG13 function to QSPI1_MISO0 */ +#define SET_QSPI1_MISO0_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~QSPI1_MISO0_PF0_Msk)) | QSPI1_MISO0_PF0 /*!< Set PF0 function to QSPI1_MISO0 */ +#define SET_QSPI1_MISO1_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~QSPI1_MISO1_PG9_Msk)) | QSPI1_MISO1_PG9 /*!< Set PG9 function to QSPI1_MISO1 */ +#define SET_QSPI1_MISO1_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~QSPI1_MISO1_PA7_Msk)) | QSPI1_MISO1_PA7 /*!< Set PA7 function to QSPI1_MISO1 */ +#define SET_QSPI1_MISO1_PH12() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~QSPI1_MISO1_PH12_Msk)) | QSPI1_MISO1_PH12 /*!< Set PH12 function to QSPI1_MISO1 */ +#define SET_QSPI1_MISO1_PG15() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~QSPI1_MISO1_PG15_Msk)) | QSPI1_MISO1_PG15 /*!< Set PG15 function to QSPI1_MISO1 */ +#define SET_QSPI1_MOSI0_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~QSPI1_MOSI0_PA13_Msk)) | QSPI1_MOSI0_PA13 /*!< Set PA13 function to QSPI1_MOSI0 */ +#define SET_QSPI1_MOSI0_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~QSPI1_MOSI0_PD13_Msk)) | QSPI1_MOSI0_PD13 /*!< Set PD13 function to QSPI1_MOSI0 */ +#define SET_QSPI1_MOSI0_PG14() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~QSPI1_MOSI0_PG14_Msk)) | QSPI1_MOSI0_PG14 /*!< Set PG14 function to QSPI1_MOSI0 */ +#define SET_QSPI1_MOSI0_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI1_MOSI0_PC2_Msk)) | QSPI1_MOSI0_PC2 /*!< Set PC2 function to QSPI1_MOSI0 */ +#define SET_QSPI1_MOSI0_PJ5() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~QSPI1_MOSI0_PJ5_Msk)) | QSPI1_MOSI0_PJ5 /*!< Set PJ5 function to QSPI1_MOSI0 */ +#define SET_QSPI1_MOSI0_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~QSPI1_MOSI0_PD6_Msk)) | QSPI1_MOSI0_PD6 /*!< Set PD6 function to QSPI1_MOSI0 */ +#define SET_QSPI1_MOSI0_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~QSPI1_MOSI0_PF1_Msk)) | QSPI1_MOSI0_PF1 /*!< Set PF1 function to QSPI1_MOSI0 */ +#define SET_QSPI1_MOSI1_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~QSPI1_MOSI1_PG10_Msk)) | QSPI1_MOSI1_PG10 /*!< Set PG10 function to QSPI1_MOSI1 */ +#define SET_QSPI1_MOSI1_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~QSPI1_MOSI1_PA6_Msk)) | QSPI1_MOSI1_PA6 /*!< Set PA6 function to QSPI1_MOSI1 */ +#define SET_QSPI1_MOSI1_PH13() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~QSPI1_MOSI1_PH13_Msk)) | QSPI1_MOSI1_PH13 /*!< Set PH13 function to QSPI1_MOSI1 */ +#define SET_QSPI1_MOSI1_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~QSPI1_MOSI1_PD13_Msk)) | QSPI1_MOSI1_PD13 /*!< Set PD13 function to QSPI1_MOSI1 */ +#define SET_QSPI1_SS_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~QSPI1_SS_PG11_Msk)) | QSPI1_SS_PG11 /*!< Set PG11 function to QSPI1_SS */ +#define SET_QSPI1_SS_PH14() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~QSPI1_SS_PH14_Msk)) | QSPI1_SS_PH14 /*!< Set PH14 function to QSPI1_SS */ +#define SET_QSPI1_SS_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~QSPI1_SS_PC5_Msk)) | QSPI1_SS_PC5 /*!< Set PC5 function to QSPI1_SS */ +#define SET_QSPI1_SS_PJ2() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~QSPI1_SS_PJ2_Msk)) | QSPI1_SS_PJ2 /*!< Set PJ2 function to QSPI1_SS */ +#define SET_QSPI1_SS_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~QSPI1_SS_PC1_Msk)) | QSPI1_SS_PC1 /*!< Set PC1 function to QSPI1_SS */ +#define SET_SC0_CLK_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SC0_CLK_PA0_Msk)) | SC0_CLK_PA0 /*!< Set PA0 function to SC0_CLK */ +#define SET_SC0_CLK_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SC0_CLK_PF6_Msk)) | SC0_CLK_PF6 /*!< Set PF6 function to SC0_CLK */ +#define SET_SC0_CLK_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SC0_CLK_PE2_Msk)) | SC0_CLK_PE2 /*!< Set PE2 function to SC0_CLK */ +#define SET_SC0_CLK_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SC0_CLK_PB5_Msk)) | SC0_CLK_PB5 /*!< Set PB5 function to SC0_CLK */ +#define SET_SC0_DAT_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SC0_DAT_PE3_Msk)) | SC0_DAT_PE3 /*!< Set PE3 function to SC0_DAT */ +#define SET_SC0_DAT_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SC0_DAT_PB4_Msk)) | SC0_DAT_PB4 /*!< Set PB4 function to SC0_DAT */ +#define SET_SC0_DAT_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SC0_DAT_PA1_Msk)) | SC0_DAT_PA1 /*!< Set PA1 function to SC0_DAT */ +#define SET_SC0_DAT_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SC0_DAT_PF7_Msk)) | SC0_DAT_PF7 /*!< Set PF7 function to SC0_DAT */ +#define SET_SC0_PWR_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SC0_PWR_PE5_Msk)) | SC0_PWR_PE5 /*!< Set PE5 function to SC0_PWR */ +#define SET_SC0_PWR_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SC0_PWR_PA3_Msk)) | SC0_PWR_PA3 /*!< Set PA3 function to SC0_PWR */ +#define SET_SC0_PWR_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SC0_PWR_PB2_Msk)) | SC0_PWR_PB2 /*!< Set PB2 function to SC0_PWR */ +#define SET_SC0_PWR_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~SC0_PWR_PF9_Msk)) | SC0_PWR_PF9 /*!< Set PF9 function to SC0_PWR */ +#define SET_SC0_RST_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SC0_RST_PE4_Msk)) | SC0_RST_PE4 /*!< Set PE4 function to SC0_RST */ +#define SET_SC0_RST_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SC0_RST_PA2_Msk)) | SC0_RST_PA2 /*!< Set PA2 function to SC0_RST */ +#define SET_SC0_RST_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~SC0_RST_PF8_Msk)) | SC0_RST_PF8 /*!< Set PF8 function to SC0_RST */ +#define SET_SC0_RST_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SC0_RST_PB3_Msk)) | SC0_RST_PB3 /*!< Set PB3 function to SC0_RST */ +#define SET_SC0_nCD_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SC0_nCD_PC12_Msk)) | SC0_nCD_PC12 /*!< Set PC12 function to SC0_nCD */ +#define SET_SC0_nCD_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SC0_nCD_PE6_Msk)) | SC0_nCD_PE6 /*!< Set PE6 function to SC0_nCD */ +#define SET_SC0_nCD_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SC0_nCD_PA4_Msk)) | SC0_nCD_PA4 /*!< Set PA4 function to SC0_nCD */ +#define SET_SC0_nCD_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~SC0_nCD_PF10_Msk)) | SC0_nCD_PF10 /*!< Set PF10 function to SC0_nCD */ +#define SET_SC1_CLK_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~SC1_CLK_PF1_Msk)) | SC1_CLK_PF1 /*!< Set PF1 function to SC1_CLK */ +#define SET_SC1_CLK_PD4() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SC1_CLK_PD4_Msk)) | SC1_CLK_PD4 /*!< Set PD4 function to SC1_CLK */ +#define SET_SC1_CLK_PI10() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~SC1_CLK_PI10_Msk)) | SC1_CLK_PI10 /*!< Set PI10 function to SC1_CLK */ +#define SET_SC1_CLK_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SC1_CLK_PB12_Msk)) | SC1_CLK_PB12 /*!< Set PB12 function to SC1_CLK */ +#define SET_SC1_CLK_PG8() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SC1_CLK_PG8_Msk)) | SC1_CLK_PG8 /*!< Set PG8 function to SC1_CLK */ +#define SET_SC1_CLK_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SC1_CLK_PC0_Msk)) | SC1_CLK_PC0 /*!< Set PC0 function to SC1_CLK */ +#define SET_SC1_DAT_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SC1_DAT_PC1_Msk)) | SC1_DAT_PC1 /*!< Set PC1 function to SC1_DAT */ +#define SET_SC1_DAT_PD5() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SC1_DAT_PD5_Msk)) | SC1_DAT_PD5 /*!< Set PD5 function to SC1_DAT */ +#define SET_SC1_DAT_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~SC1_DAT_PF0_Msk)) | SC1_DAT_PF0 /*!< Set PF0 function to SC1_DAT */ +#define SET_SC1_DAT_PG7() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~SC1_DAT_PG7_Msk)) | SC1_DAT_PG7 /*!< Set PG7 function to SC1_DAT */ +#define SET_SC1_DAT_PI9() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~SC1_DAT_PI9_Msk)) | SC1_DAT_PI9 /*!< Set PI9 function to SC1_DAT */ +#define SET_SC1_DAT_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SC1_DAT_PB13_Msk)) | SC1_DAT_PB13 /*!< Set PB13 function to SC1_DAT */ +#define SET_SC1_PWR_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SC1_PWR_PD7_Msk)) | SC1_PWR_PD7 /*!< Set PD7 function to SC1_PWR */ +#define SET_SC1_PWR_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SC1_PWR_PC3_Msk)) | SC1_PWR_PC3 /*!< Set PC3 function to SC1_PWR */ +#define SET_SC1_PWR_PI7() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~SC1_PWR_PI7_Msk)) | SC1_PWR_PI7 /*!< Set PI7 function to SC1_PWR */ +#define SET_SC1_PWR_PG5() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~SC1_PWR_PG5_Msk)) | SC1_PWR_PG5 /*!< Set PG5 function to SC1_PWR */ +#define SET_SC1_PWR_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SC1_PWR_PB15_Msk)) | SC1_PWR_PB15 /*!< Set PB15 function to SC1_PWR */ +#define SET_SC1_RST_PI8() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~SC1_RST_PI8_Msk)) | SC1_RST_PI8 /*!< Set PI8 function to SC1_RST */ +#define SET_SC1_RST_PG6() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~SC1_RST_PG6_Msk)) | SC1_RST_PG6 /*!< Set PG6 function to SC1_RST */ +#define SET_SC1_RST_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SC1_RST_PB14_Msk)) | SC1_RST_PB14 /*!< Set PB14 function to SC1_RST */ +#define SET_SC1_RST_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SC1_RST_PC2_Msk)) | SC1_RST_PC2 /*!< Set PC2 function to SC1_RST */ +#define SET_SC1_RST_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SC1_RST_PD6_Msk)) | SC1_RST_PD6 /*!< Set PD6 function to SC1_RST */ +#define SET_SC1_nCD_PD14() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SC1_nCD_PD14_Msk)) | SC1_nCD_PD14 /*!< Set PD14 function to SC1_nCD */ +#define SET_SC1_nCD_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SC1_nCD_PC4_Msk)) | SC1_nCD_PC4 /*!< Set PC4 function to SC1_nCD */ +#define SET_SC1_nCD_PI6() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~SC1_nCD_PI6_Msk)) | SC1_nCD_PI6 /*!< Set PI6 function to SC1_nCD */ +#define SET_SC1_nCD_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SC1_nCD_PD3_Msk)) | SC1_nCD_PD3 /*!< Set PD3 function to SC1_nCD */ +#define SET_SC1_nCD_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SC1_nCD_PC14_Msk)) | SC1_nCD_PC14 /*!< Set PC14 function to SC1_nCD */ +#define SET_SC2_CLK_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SC2_CLK_PA15_Msk)) | SC2_CLK_PA15 /*!< Set PA15 function to SC2_CLK */ +#define SET_SC2_CLK_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SC2_CLK_PD0_Msk)) | SC2_CLK_PD0 /*!< Set PD0 function to SC2_CLK */ +#define SET_SC2_CLK_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SC2_CLK_PA6_Msk)) | SC2_CLK_PA6 /*!< Set PA6 function to SC2_CLK */ +#define SET_SC2_CLK_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SC2_CLK_PE0_Msk)) | SC2_CLK_PE0 /*!< Set PE0 function to SC2_CLK */ +#define SET_SC2_CLK_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SC2_CLK_PA8_Msk)) | SC2_CLK_PA8 /*!< Set PA8 function to SC2_CLK */ +#define SET_SC2_DAT_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SC2_DAT_PD1_Msk)) | SC2_DAT_PD1 /*!< Set PD1 function to SC2_DAT */ +#define SET_SC2_DAT_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SC2_DAT_PA9_Msk)) | SC2_DAT_PA9 /*!< Set PA9 function to SC2_DAT */ +#define SET_SC2_DAT_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SC2_DAT_PE1_Msk)) | SC2_DAT_PE1 /*!< Set PE1 function to SC2_DAT */ +#define SET_SC2_DAT_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SC2_DAT_PA14_Msk)) | SC2_DAT_PA14 /*!< Set PA14 function to SC2_DAT */ +#define SET_SC2_DAT_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SC2_DAT_PA7_Msk)) | SC2_DAT_PA7 /*!< Set PA7 function to SC2_DAT */ +#define SET_SC2_PWR_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SC2_PWR_PC7_Msk)) | SC2_PWR_PC7 /*!< Set PC7 function to SC2_PWR */ +#define SET_SC2_PWR_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SC2_PWR_PA11_Msk)) | SC2_PWR_PA11 /*!< Set PA11 function to SC2_PWR */ +#define SET_SC2_PWR_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SC2_PWR_PA12_Msk)) | SC2_PWR_PA12 /*!< Set PA12 function to SC2_PWR */ +#define SET_SC2_PWR_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SC2_PWR_PD3_Msk)) | SC2_PWR_PD3 /*!< Set PD3 function to SC2_PWR */ +#define SET_SC2_PWR_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~SC2_PWR_PH8_Msk)) | SC2_PWR_PH8 /*!< Set PH8 function to SC2_PWR */ +#define SET_SC2_RST_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SC2_RST_PC6_Msk)) | SC2_RST_PC6 /*!< Set PC6 function to SC2_RST */ +#define SET_SC2_RST_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SC2_RST_PD2_Msk)) | SC2_RST_PD2 /*!< Set PD2 function to SC2_RST */ +#define SET_SC2_RST_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SC2_RST_PA13_Msk)) | SC2_RST_PA13 /*!< Set PA13 function to SC2_RST */ +#define SET_SC2_RST_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SC2_RST_PA10_Msk)) | SC2_RST_PA10 /*!< Set PA10 function to SC2_RST */ +#define SET_SC2_RST_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~SC2_RST_PH9_Msk)) | SC2_RST_PH9 /*!< Set PH9 function to SC2_RST */ +#define SET_SC2_nCD_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SC2_nCD_PD13_Msk)) | SC2_nCD_PD13 /*!< Set PD13 function to SC2_nCD */ +#define SET_SC2_nCD_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SC2_nCD_PA5_Msk)) | SC2_nCD_PA5 /*!< Set PA5 function to SC2_nCD */ +#define SET_SC2_nCD_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SC2_nCD_PC13_Msk)) | SC2_nCD_PC13 /*!< Set PC13 function to SC2_nCD */ +#define SET_SC2_nCD_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~SC2_nCD_PH10_Msk)) | SC2_nCD_PH10 /*!< Set PH10 function to SC2_nCD */ +#define SET_SD0_CLK_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SD0_CLK_PB1_Msk)) | SD0_CLK_PB1 /*!< Set PB1 function to SD0_CLK */ +#define SET_SD0_CLK_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SD0_CLK_PE6_Msk)) | SD0_CLK_PE6 /*!< Set PE6 function to SD0_CLK */ +#define SET_SD0_CMD_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SD0_CMD_PE7_Msk)) | SD0_CMD_PE7 /*!< Set PE7 function to SD0_CMD */ +#define SET_SD0_CMD_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SD0_CMD_PB0_Msk)) | SD0_CMD_PB0 /*!< Set PB0 function to SD0_CMD */ +#define SET_SD0_DAT0_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SD0_DAT0_PE2_Msk)) | SD0_DAT0_PE2 /*!< Set PE2 function to SD0_DAT0 */ +#define SET_SD0_DAT0_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SD0_DAT0_PB2_Msk)) | SD0_DAT0_PB2 /*!< Set PB2 function to SD0_DAT0 */ +#define SET_SD0_DAT1_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SD0_DAT1_PB3_Msk)) | SD0_DAT1_PB3 /*!< Set PB3 function to SD0_DAT1 */ +#define SET_SD0_DAT1_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SD0_DAT1_PE3_Msk)) | SD0_DAT1_PE3 /*!< Set PE3 function to SD0_DAT1 */ +#define SET_SD0_DAT2_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SD0_DAT2_PE4_Msk)) | SD0_DAT2_PE4 /*!< Set PE4 function to SD0_DAT2 */ +#define SET_SD0_DAT2_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SD0_DAT2_PB4_Msk)) | SD0_DAT2_PB4 /*!< Set PB4 function to SD0_DAT2 */ +#define SET_SD0_DAT3_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SD0_DAT3_PE5_Msk)) | SD0_DAT3_PE5 /*!< Set PE5 function to SD0_DAT3 */ +#define SET_SD0_DAT3_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SD0_DAT3_PB5_Msk)) | SD0_DAT3_PB5 /*!< Set PB5 function to SD0_DAT3 */ +#define SET_SD0_nCD_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SD0_nCD_PB12_Msk)) | SD0_nCD_PB12 /*!< Set PB12 function to SD0_nCD */ +#define SET_SD0_nCD_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SD0_nCD_PD13_Msk)) | SD0_nCD_PD13 /*!< Set PD13 function to SD0_nCD */ +#define SET_SD1_CLK_PJ13() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~SD1_CLK_PJ13_Msk)) | SD1_CLK_PJ13 /*!< Set PJ13 function to SD1_CLK */ +#define SET_SD1_CLK_PG14() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SD1_CLK_PG14_Msk)) | SD1_CLK_PG14 /*!< Set PG14 function to SD1_CLK */ +#define SET_SD1_CLK_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SD1_CLK_PD13_Msk)) | SD1_CLK_PD13 /*!< Set PD13 function to SD1_CLK */ +#define SET_SD1_CLK_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SD1_CLK_PA4_Msk)) | SD1_CLK_PA4 /*!< Set PA4 function to SD1_CLK */ +#define SET_SD1_CLK_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SD1_CLK_PB6_Msk)) | SD1_CLK_PB6 /*!< Set PB6 function to SD1_CLK */ +#define SET_SD1_CMD_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SD1_CMD_PA5_Msk)) | SD1_CMD_PA5 /*!< Set PA5 function to SD1_CMD */ +#define SET_SD1_CMD_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~SD1_CMD_PJ12_Msk)) | SD1_CMD_PJ12 /*!< Set PJ12 function to SD1_CMD */ +#define SET_SD1_CMD_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SD1_CMD_PB7_Msk)) | SD1_CMD_PB7 /*!< Set PB7 function to SD1_CMD */ +#define SET_SD1_CMD_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SD1_CMD_PG13_Msk)) | SD1_CMD_PG13 /*!< Set PG13 function to SD1_CMD */ +#define SET_SD1_DAT0_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SD1_DAT0_PA8_Msk)) | SD1_DAT0_PA8 /*!< Set PA8 function to SD1_DAT0 */ +#define SET_SD1_DAT0_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SD1_DAT0_PA0_Msk)) | SD1_DAT0_PA0 /*!< Set PA0 function to SD1_DAT0 */ +#define SET_SD1_DAT0_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SD1_DAT0_PG12_Msk)) | SD1_DAT0_PG12 /*!< Set PG12 function to SD1_DAT0 */ +#define SET_SD1_DAT0_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SD1_DAT0_PJ11_Msk)) | SD1_DAT0_PJ11 /*!< Set PJ11 function to SD1_DAT0 */ +#define SET_SD1_DAT1_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SD1_DAT1_PG11_Msk)) | SD1_DAT1_PG11 /*!< Set PG11 function to SD1_DAT1 */ +#define SET_SD1_DAT1_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SD1_DAT1_PJ10_Msk)) | SD1_DAT1_PJ10 /*!< Set PJ10 function to SD1_DAT1 */ +#define SET_SD1_DAT1_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SD1_DAT1_PA9_Msk)) | SD1_DAT1_PA9 /*!< Set PA9 function to SD1_DAT1 */ +#define SET_SD1_DAT1_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SD1_DAT1_PA1_Msk)) | SD1_DAT1_PA1 /*!< Set PA1 function to SD1_DAT1 */ +#define SET_SD1_DAT2_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SD1_DAT2_PA2_Msk)) | SD1_DAT2_PA2 /*!< Set PA2 function to SD1_DAT2 */ +#define SET_SD1_DAT2_PJ9() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SD1_DAT2_PJ9_Msk)) | SD1_DAT2_PJ9 /*!< Set PJ9 function to SD1_DAT2 */ +#define SET_SD1_DAT2_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SD1_DAT2_PG10_Msk)) | SD1_DAT2_PG10 /*!< Set PG10 function to SD1_DAT2 */ +#define SET_SD1_DAT2_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SD1_DAT2_PA10_Msk)) | SD1_DAT2_PA10 /*!< Set PA10 function to SD1_DAT2 */ +#define SET_SD1_DAT3_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SD1_DAT3_PA3_Msk)) | SD1_DAT3_PA3 /*!< Set PA3 function to SD1_DAT3 */ +#define SET_SD1_DAT3_PJ8() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SD1_DAT3_PJ8_Msk)) | SD1_DAT3_PJ8 /*!< Set PJ8 function to SD1_DAT3 */ +#define SET_SD1_DAT3_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SD1_DAT3_PA11_Msk)) | SD1_DAT3_PA11 /*!< Set PA11 function to SD1_DAT3 */ +#define SET_SD1_DAT3_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SD1_DAT3_PG9_Msk)) | SD1_DAT3_PG9 /*!< Set PG9 function to SD1_DAT3 */ +#define SET_SD1_nCD_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SD1_nCD_PA6_Msk)) | SD1_nCD_PA6 /*!< Set PA6 function to SD1_nCD */ +#define SET_SD1_nCD_PG15() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SD1_nCD_PG15_Msk)) | SD1_nCD_PG15 /*!< Set PG15 function to SD1_nCD */ +#define SET_SD1_nCD_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SD1_nCD_PA12_Msk)) | SD1_nCD_PA12 /*!< Set PA12 function to SD1_nCD */ +#define SET_SD1_nCD_PE14() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~SD1_nCD_PE14_Msk)) | SD1_nCD_PE14 /*!< Set PE14 function to SD1_nCD */ +#define SET_SPI0_CLK_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SPI0_CLK_PD2_Msk)) | SPI0_CLK_PD2 /*!< Set PD2 function to SPI0_CLK */ +#define SET_SPI0_CLK_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~SPI0_CLK_PF8_Msk)) | SPI0_CLK_PF8 /*!< Set PF8 function to SPI0_CLK */ +#define SET_SPI0_CLK_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPI0_CLK_PA2_Msk)) | SPI0_CLK_PA2 /*!< Set PA2 function to SPI0_CLK */ +#define SET_SPI0_CLK_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI0_CLK_PB14_Msk)) | SPI0_CLK_PB14 /*!< Set PB14 function to SPI0_CLK */ +#define SET_SPI0_CLK_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI0_CLK_PA13_Msk)) | SPI0_CLK_PA13 /*!< Set PA13 function to SPI0_CLK */ +#define SET_SPI0_I2SMCLK_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~SPI0_I2SMCLK_PF10_Msk)) | SPI0_I2SMCLK_PF10 /*!< Set PF10 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SPI0_I2SMCLK_PD13_Msk)) | SPI0_I2SMCLK_PD13 /*!< Set PD13 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI0_I2SMCLK_PB0_Msk)) | SPI0_I2SMCLK_PB0 /*!< Set PB0 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PD14() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SPI0_I2SMCLK_PD14_Msk)) | SPI0_I2SMCLK_PD14 /*!< Set PD14 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI0_I2SMCLK_PA4_Msk)) | SPI0_I2SMCLK_PA4 /*!< Set PA4 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SPI0_I2SMCLK_PC14_Msk)) | SPI0_I2SMCLK_PC14 /*!< Set PC14 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~SPI0_I2SMCLK_PB11_Msk)) | SPI0_I2SMCLK_PB11 /*!< Set PB11 function to SPI0_I2SMCLK */ +#define SET_SPI0_MISO_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SPI0_MISO_PD1_Msk)) | SPI0_MISO_PD1 /*!< Set PD1 function to SPI0_MISO */ +#define SET_SPI0_MISO_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI0_MISO_PB13_Msk)) | SPI0_MISO_PB13 /*!< Set PB13 function to SPI0_MISO */ +#define SET_SPI0_MISO_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SPI0_MISO_PF7_Msk)) | SPI0_MISO_PF7 /*!< Set PF7 function to SPI0_MISO */ +#define SET_SPI0_MISO_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPI0_MISO_PA1_Msk)) | SPI0_MISO_PA1 /*!< Set PA1 function to SPI0_MISO */ +#define SET_SPI0_MISO_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI0_MISO_PA14_Msk)) | SPI0_MISO_PA14 /*!< Set PA14 function to SPI0_MISO */ +#define SET_SPI0_MOSI_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SPI0_MOSI_PD0_Msk)) | SPI0_MOSI_PD0 /*!< Set PD0 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI0_MOSI_PB12_Msk)) | SPI0_MOSI_PB12 /*!< Set PB12 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SPI0_MOSI_PF6_Msk)) | SPI0_MOSI_PF6 /*!< Set PF6 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPI0_MOSI_PA0_Msk)) | SPI0_MOSI_PA0 /*!< Set PA0 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI0_MOSI_PA15_Msk)) | SPI0_MOSI_PA15 /*!< Set PA15 function to SPI0_MOSI */ +#define SET_SPI0_SS_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~SPI0_SS_PD3_Msk)) | SPI0_SS_PD3 /*!< Set PD3 function to SPI0_SS */ +#define SET_SPI0_SS_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~SPI0_SS_PF9_Msk)) | SPI0_SS_PF9 /*!< Set PF9 function to SPI0_SS */ +#define SET_SPI0_SS_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI0_SS_PB15_Msk)) | SPI0_SS_PB15 /*!< Set PB15 function to SPI0_SS */ +#define SET_SPI0_SS_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPI0_SS_PA3_Msk)) | SPI0_SS_PA3 /*!< Set PA3 function to SPI0_SS */ +#define SET_SPI0_SS_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI0_SS_PA12_Msk)) | SPI0_SS_PA12 /*!< Set PA12 function to SPI0_SS */ +#define SET_SPI1_CLK_PI9() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~SPI1_CLK_PI9_Msk)) | SPI1_CLK_PI9 /*!< Set PI9 function to SPI1_CLK */ +#define SET_SPI1_CLK_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~SPI1_CLK_PH8_Msk)) | SPI1_CLK_PH8 /*!< Set PH8 function to SPI1_CLK */ +#define SET_SPI1_CLK_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI1_CLK_PB3_Msk)) | SPI1_CLK_PB3 /*!< Set PB3 function to SPI1_CLK */ +#define SET_SPI1_CLK_PD5() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SPI1_CLK_PD5_Msk)) | SPI1_CLK_PD5 /*!< Set PD5 function to SPI1_CLK */ +#define SET_SPI1_CLK_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI1_CLK_PA7_Msk)) | SPI1_CLK_PA7 /*!< Set PA7 function to SPI1_CLK */ +#define SET_SPI1_CLK_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI1_CLK_PC1_Msk)) | SPI1_CLK_PC1 /*!< Set PC1 function to SPI1_CLK */ +#define SET_SPI1_CLK_PH6() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~SPI1_CLK_PH6_Msk)) | SPI1_CLK_PH6 /*!< Set PH6 function to SPI1_CLK */ +#define SET_SPI1_CLK_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SPI1_CLK_PB7_Msk)) | SPI1_CLK_PB7 /*!< Set PB7 function to SPI1_CLK */ +#define SET_SPI1_I2SMCLK_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SPI1_I2SMCLK_PC4_Msk)) | SPI1_I2SMCLK_PC4 /*!< Set PC4 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PI6() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~SPI1_I2SMCLK_PI6_Msk)) | SPI1_I2SMCLK_PI6 /*!< Set PI6 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~SPI1_I2SMCLK_PH10_Msk)) | SPI1_I2SMCLK_PH10 /*!< Set PH10 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI1_I2SMCLK_PA5_Msk)) | SPI1_I2SMCLK_PA5 /*!< Set PA5 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PH3() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~SPI1_I2SMCLK_PH3_Msk)) | SPI1_I2SMCLK_PH3 /*!< Set PH3 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SPI1_I2SMCLK_PD13_Msk)) | SPI1_I2SMCLK_PD13 /*!< Set PD13 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI1_I2SMCLK_PB1_Msk)) | SPI1_I2SMCLK_PB1 /*!< Set PB1 function to SPI1_I2SMCLK */ +#define SET_SPI1_MISO_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SPI1_MISO_PE1_Msk)) | SPI1_MISO_PE1 /*!< Set PE1 function to SPI1_MISO */ +#define SET_SPI1_MISO_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI1_MISO_PC3_Msk)) | SPI1_MISO_PC3 /*!< Set PC3 function to SPI1_MISO */ +#define SET_SPI1_MISO_PH4() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~SPI1_MISO_PH4_Msk)) | SPI1_MISO_PH4 /*!< Set PH4 function to SPI1_MISO */ +#define SET_SPI1_MISO_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SPI1_MISO_PC7_Msk)) | SPI1_MISO_PC7 /*!< Set PC7 function to SPI1_MISO */ +#define SET_SPI1_MISO_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SPI1_MISO_PB5_Msk)) | SPI1_MISO_PB5 /*!< Set PB5 function to SPI1_MISO */ +#define SET_SPI1_MISO_PI7() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~SPI1_MISO_PI7_Msk)) | SPI1_MISO_PI7 /*!< Set PI7 function to SPI1_MISO */ +#define SET_SPI1_MISO_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SPI1_MISO_PD7_Msk)) | SPI1_MISO_PD7 /*!< Set PD7 function to SPI1_MISO */ +#define SET_SPI1_MOSI_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SPI1_MOSI_PD6_Msk)) | SPI1_MOSI_PD6 /*!< Set PD6 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PH5() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~SPI1_MOSI_PH5_Msk)) | SPI1_MOSI_PH5 /*!< Set PH5 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PI8() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~SPI1_MOSI_PI8_Msk)) | SPI1_MOSI_PI8 /*!< Set PI8 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SPI1_MOSI_PE0_Msk)) | SPI1_MOSI_PE0 /*!< Set PE0 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI1_MOSI_PC2_Msk)) | SPI1_MOSI_PC2 /*!< Set PC2 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SPI1_MOSI_PC6_Msk)) | SPI1_MOSI_PC6 /*!< Set PC6 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SPI1_MOSI_PB4_Msk)) | SPI1_MOSI_PB4 /*!< Set PB4 function to SPI1_MOSI */ +#define SET_SPI1_SS_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI1_SS_PA6_Msk)) | SPI1_SS_PA6 /*!< Set PA6 function to SPI1_SS */ +#define SET_SPI1_SS_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~SPI1_SS_PH9_Msk)) | SPI1_SS_PH9 /*!< Set PH9 function to SPI1_SS */ +#define SET_SPI1_SS_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI1_SS_PC0_Msk)) | SPI1_SS_PC0 /*!< Set PC0 function to SPI1_SS */ +#define SET_SPI1_SS_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI1_SS_PB2_Msk)) | SPI1_SS_PB2 /*!< Set PB2 function to SPI1_SS */ +#define SET_SPI1_SS_PI10() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~SPI1_SS_PI10_Msk)) | SPI1_SS_PI10 /*!< Set PI10 function to SPI1_SS */ +#define SET_SPI1_SS_PD4() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~SPI1_SS_PD4_Msk)) | SPI1_SS_PD4 /*!< Set PD4 function to SPI1_SS */ +#define SET_SPI1_SS_PH7() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~SPI1_SS_PH7_Msk)) | SPI1_SS_PH7 /*!< Set PH7 function to SPI1_SS */ +#define SET_SPI2_CLK_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~SPI2_CLK_PE8_Msk)) | SPI2_CLK_PE8 /*!< Set PE8 function to SPI2_CLK */ +#define SET_SPI2_CLK_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SPI2_CLK_PA10_Msk)) | SPI2_CLK_PA10 /*!< Set PA10 function to SPI2_CLK */ +#define SET_SPI2_CLK_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI2_CLK_PA13_Msk)) | SPI2_CLK_PA13 /*!< Set PA13 function to SPI2_CLK */ +#define SET_SPI2_CLK_PG3() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~SPI2_CLK_PG3_Msk)) | SPI2_CLK_PG3 /*!< Set PG3 function to SPI2_CLK */ +#define SET_SPI2_I2SMCLK_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~SPI2_I2SMCLK_PG1_Msk)) | SPI2_I2SMCLK_PG1 /*!< Set PG1 function to SPI2_I2SMCLK */ +#define SET_SPI2_I2SMCLK_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SPI2_I2SMCLK_PC13_Msk)) | SPI2_I2SMCLK_PC13 /*!< Set PC13 function to SPI2_I2SMCLK */ +#define SET_SPI2_I2SMCLK_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI2_I2SMCLK_PB0_Msk)) | SPI2_I2SMCLK_PB0 /*!< Set PB0 function to SPI2_I2SMCLK */ +#define SET_SPI2_I2SMCLK_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~SPI2_I2SMCLK_PE12_Msk)) | SPI2_I2SMCLK_PE12 /*!< Set PE12 function to SPI2_I2SMCLK */ +#define SET_SPI2_MISO_PG4() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~SPI2_MISO_PG4_Msk)) | SPI2_MISO_PG4 /*!< Set PG4 function to SPI2_MISO */ +#define SET_SPI2_MISO_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~SPI2_MISO_PE9_Msk)) | SPI2_MISO_PE9 /*!< Set PE9 function to SPI2_MISO */ +#define SET_SPI2_MISO_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SPI2_MISO_PA9_Msk)) | SPI2_MISO_PA9 /*!< Set PA9 function to SPI2_MISO */ +#define SET_SPI2_MISO_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI2_MISO_PA14_Msk)) | SPI2_MISO_PA14 /*!< Set PA14 function to SPI2_MISO */ +#define SET_SPI2_MOSI_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SPI2_MOSI_PA8_Msk)) | SPI2_MOSI_PA8 /*!< Set PA8 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI2_MOSI_PA15_Msk)) | SPI2_MOSI_PA15 /*!< Set PA15 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~SPI2_MOSI_PF11_Msk)) | SPI2_MOSI_PF11 /*!< Set PF11 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~SPI2_MOSI_PE10_Msk)) | SPI2_MOSI_PE10 /*!< Set PE10 function to SPI2_MOSI */ +#define SET_SPI2_SS_PG2() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~SPI2_SS_PG2_Msk)) | SPI2_SS_PG2 /*!< Set PG2 function to SPI2_SS */ +#define SET_SPI2_SS_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SPI2_SS_PA11_Msk)) | SPI2_SS_PA11 /*!< Set PA11 function to SPI2_SS */ +#define SET_SPI2_SS_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI2_SS_PA12_Msk)) | SPI2_SS_PA12 /*!< Set PA12 function to SPI2_SS */ +#define SET_SPI2_SS_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~SPI2_SS_PE11_Msk)) | SPI2_SS_PE11 /*!< Set PE11 function to SPI2_SS */ +#define SET_SPI3_CLK_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~SPI3_CLK_PC10_Msk)) | SPI3_CLK_PC10 /*!< Set PC10 function to SPI3_CLK */ +#define SET_SPI3_CLK_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~SPI3_CLK_PB11_Msk)) | SPI3_CLK_PB11 /*!< Set PB11 function to SPI3_CLK */ +#define SET_SPI3_CLK_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SPI3_CLK_PE4_Msk)) | SPI3_CLK_PE4 /*!< Set PE4 function to SPI3_CLK */ +#define SET_SPI3_CLK_PG6() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~SPI3_CLK_PG6_Msk)) | SPI3_CLK_PG6 /*!< Set PG6 function to SPI3_CLK */ +#define SET_SPI3_CLK_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI3_CLK_PB13_Msk)) | SPI3_CLK_PB13 /*!< Set PB13 function to SPI3_CLK */ +#define SET_SPI3_I2SMCLK_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SPI3_I2SMCLK_PF6_Msk)) | SPI3_I2SMCLK_PF6 /*!< Set PF6 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI3_I2SMCLK_PB1_Msk)) | SPI3_I2SMCLK_PB1 /*!< Set PB1 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PD14() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SPI3_I2SMCLK_PD14_Msk)) | SPI3_I2SMCLK_PD14 /*!< Set PD14 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SPI3_I2SMCLK_PE6_Msk)) | SPI3_I2SMCLK_PE6 /*!< Set PE6 function to SPI3_I2SMCLK */ +#define SET_SPI3_MISO_PG7() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~SPI3_MISO_PG7_Msk)) | SPI3_MISO_PG7 /*!< Set PG7 function to SPI3_MISO */ +#define SET_SPI3_MISO_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~SPI3_MISO_PB9_Msk)) | SPI3_MISO_PB9 /*!< Set PB9 function to SPI3_MISO */ +#define SET_SPI3_MISO_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SPI3_MISO_PC12_Msk)) | SPI3_MISO_PC12 /*!< Set PC12 function to SPI3_MISO */ +#define SET_SPI3_MISO_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SPI3_MISO_PE3_Msk)) | SPI3_MISO_PE3 /*!< Set PE3 function to SPI3_MISO */ +#define SET_SPI3_MISO_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SPI3_MISO_PB7_Msk)) | SPI3_MISO_PB7 /*!< Set PB7 function to SPI3_MISO */ +#define SET_SPI3_MOSI_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~SPI3_MOSI_PB8_Msk)) | SPI3_MOSI_PB8 /*!< Set PB8 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PG8() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SPI3_MOSI_PG8_Msk)) | SPI3_MOSI_PG8 /*!< Set PG8 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~SPI3_MOSI_PC11_Msk)) | SPI3_MOSI_PC11 /*!< Set PC11 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SPI3_MOSI_PE2_Msk)) | SPI3_MOSI_PE2 /*!< Set PE2 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~SPI3_MOSI_PB6_Msk)) | SPI3_MOSI_PB6 /*!< Set PB6 function to SPI3_MOSI */ +#define SET_SPI3_SS_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SPI3_SS_PE5_Msk)) | SPI3_SS_PE5 /*!< Set PE5 function to SPI3_SS */ +#define SET_SPI3_SS_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~SPI3_SS_PB10_Msk)) | SPI3_SS_PB10 /*!< Set PB10 function to SPI3_SS */ +#define SET_SPI3_SS_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~SPI3_SS_PC9_Msk)) | SPI3_SS_PC9 /*!< Set PC9 function to SPI3_SS */ +#define SET_SPI3_SS_PG5() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~SPI3_SS_PG5_Msk)) | SPI3_SS_PG5 /*!< Set PG5 function to SPI3_SS */ +#define SET_SPI3_SS_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI3_SS_PB12_Msk)) | SPI3_SS_PB12 /*!< Set PB12 function to SPI3_SS */ +#define SET_SPI4_CLK_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI4_CLK_PB2_Msk)) | SPI4_CLK_PB2 /*!< Set PB2 function to SPI4_CLK */ +#define SET_SPI4_MISO_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI4_MISO_PB1_Msk)) | SPI4_MISO_PB1 /*!< Set PB1 function to SPI4_MISO */ +#define SET_SPI4_MOSI_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI4_MOSI_PB0_Msk)) | SPI4_MOSI_PB0 /*!< Set PB0 function to SPI4_MOSI */ +#define SET_SPI4_SS_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~SPI4_SS_PB3_Msk)) | SPI4_SS_PB3 /*!< Set PB3 function to SPI4_SS */ +#define SET_SPI5_CLK_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SPI5_CLK_PF6_Msk)) | SPI5_CLK_PF6 /*!< Set PF6 function to SPI5_CLK */ +#define SET_SPI5_CLK_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI5_CLK_PA6_Msk)) | SPI5_CLK_PA6 /*!< Set PA6 function to SPI5_CLK */ +#define SET_SPI5_MISO_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SPI5_MISO_PF4_Msk)) | SPI5_MISO_PF4 /*!< Set PF4 function to SPI5_MISO */ +#define SET_SPI5_MOSI_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SPI5_MOSI_PF5_Msk)) | SPI5_MOSI_PF5 /*!< Set PF5 function to SPI5_MOSI */ +#define SET_SPI5_SS_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI5_SS_PA7_Msk)) | SPI5_SS_PA7 /*!< Set PA7 function to SPI5_SS */ +#define SET_SPI5_SS_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~SPI5_SS_PF7_Msk)) | SPI5_SS_PF7 /*!< Set PF7 function to SPI5_SS */ +#define SET_SPI6_CLK_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI6_CLK_PA6_Msk)) | SPI6_CLK_PA6 /*!< Set PA6 function to SPI6_CLK */ +#define SET_SPI6_MISO_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SPI6_MISO_PC7_Msk)) | SPI6_MISO_PC7 /*!< Set PC7 function to SPI6_MISO */ +#define SET_SPI6_MOSI_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SPI6_MOSI_PC6_Msk)) | SPI6_MOSI_PC6 /*!< Set PC6 function to SPI6_MOSI */ +#define SET_SPI6_SS_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPI6_SS_PA7_Msk)) | SPI6_SS_PA7 /*!< Set PA7 function to SPI6_SS */ +#define SET_SPI7_CLK_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI7_CLK_PC2_Msk)) | SPI7_CLK_PC2 /*!< Set PC2 function to SPI7_CLK */ +#define SET_SPI7_MISO_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI7_MISO_PC1_Msk)) | SPI7_MISO_PC1 /*!< Set PC1 function to SPI7_MISO */ +#define SET_SPI7_MOSI_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI7_MOSI_PC0_Msk)) | SPI7_MOSI_PC0 /*!< Set PC0 function to SPI7_MOSI */ +#define SET_SPI7_SS_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPI7_SS_PC3_Msk)) | SPI7_SS_PC3 /*!< Set PC3 function to SPI7_SS */ +#define SET_SPI8_CLK_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SPI8_CLK_PG10_Msk)) | SPI8_CLK_PG10 /*!< Set PG10 function to SPI8_CLK */ +#define SET_SPI8_MISO_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SPI8_MISO_PG12_Msk)) | SPI8_MISO_PG12 /*!< Set PG12 function to SPI8_MISO */ +#define SET_SPI8_MOSI_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SPI8_MOSI_PG11_Msk)) | SPI8_MOSI_PG11 /*!< Set PG11 function to SPI8_MOSI */ +#define SET_SPI8_SS_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SPI8_SS_PG9_Msk)) | SPI8_SS_PG9 /*!< Set PG9 function to SPI8_SS */ +#define SET_SPI9_CLK_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI9_CLK_PB15_Msk)) | SPI9_CLK_PB15 /*!< Set PB15 function to SPI9_CLK */ +#define SET_SPI9_CLK_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~SPI9_CLK_PD12_Msk)) | SPI9_CLK_PD12 /*!< Set PD12 function to SPI9_CLK */ +#define SET_SPI9_MISO_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI9_MISO_PB13_Msk)) | SPI9_MISO_PB13 /*!< Set PB13 function to SPI9_MISO */ +#define SET_SPI9_MISO_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~SPI9_MISO_PD11_Msk)) | SPI9_MISO_PD11 /*!< Set PD11 function to SPI9_MISO */ +#define SET_SPI9_MOSI_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~SPI9_MOSI_PD10_Msk)) | SPI9_MOSI_PD10 /*!< Set PD10 function to SPI9_MOSI */ +#define SET_SPI9_MOSI_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SPI9_MOSI_PC14_Msk)) | SPI9_MOSI_PC14 /*!< Set PC14 function to SPI9_MOSI */ +#define SET_SPI9_SS_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~SPI9_SS_PC13_Msk)) | SPI9_SS_PC13 /*!< Set PC13 function to SPI9_SS */ +#define SET_SPI9_SS_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~SPI9_SS_PB14_Msk)) | SPI9_SS_PB14 /*!< Set PB14 function to SPI9_SS */ +#define SET_SPI10_CLK_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI10_CLK_PA13_Msk)) | SPI10_CLK_PA13 /*!< Set PA13 function to SPI10_CLK */ +#define SET_SPI10_MISO_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI10_MISO_PA14_Msk)) | SPI10_MISO_PA14 /*!< Set PA14 function to SPI10_MISO */ +#define SET_SPI10_MOSI_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI10_MOSI_PA15_Msk)) | SPI10_MOSI_PA15 /*!< Set PA15 function to SPI10_MOSI */ +#define SET_SPI10_SS_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPI10_SS_PA12_Msk)) | SPI10_SS_PA12 /*!< Set PA12 function to SPI10_SS */ +#define SET_SPIM_CLK_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SPIM_CLK_PE4_Msk)) | SPIM_CLK_PE4 /*!< Set PE4 function to SPIM_CLK */ +#define SET_SPIM_CLK_PJ12() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~SPIM_CLK_PJ12_Msk)) | SPIM_CLK_PJ12 /*!< Set PJ12 function to SPIM_CLK */ +#define SET_SPIM_CLK_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SPIM_CLK_PG12_Msk)) | SPIM_CLK_PG12 /*!< Set PG12 function to SPIM_CLK */ +#define SET_SPIM_CLK_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPIM_CLK_PA2_Msk)) | SPIM_CLK_PA2 /*!< Set PA2 function to SPIM_CLK */ +#define SET_SPIM_CLK_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPIM_CLK_PC2_Msk)) | SPIM_CLK_PC2 /*!< Set PC2 function to SPIM_CLK */ +#define SET_SPIM_CLK_PJ0() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~SPIM_CLK_PJ0_Msk)) | SPIM_CLK_PJ0 /*!< Set PJ0 function to SPIM_CLK */ +#define SET_SPIM_D2_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SPIM_D2_PJ10_Msk)) | SPIM_D2_PJ10 /*!< Set PJ10 function to SPIM_D2 */ +#define SET_SPIM_D2_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SPIM_D2_PE7_Msk)) | SPIM_D2_PE7 /*!< Set PE7 function to SPIM_D2 */ +#define SET_SPIM_D2_PI14() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~SPIM_D2_PI14_Msk)) | SPIM_D2_PI14 /*!< Set PI14 function to SPIM_D2 */ +#define SET_SPIM_D2_PG9() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SPIM_D2_PG9_Msk)) | SPIM_D2_PG9 /*!< Set PG9 function to SPIM_D2 */ +#define SET_SPIM_D2_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SPIM_D2_PC5_Msk)) | SPIM_D2_PC5 /*!< Set PC5 function to SPIM_D2 */ +#define SET_SPIM_D2_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPIM_D2_PA5_Msk)) | SPIM_D2_PA5 /*!< Set PA5 function to SPIM_D2 */ +#define SET_SPIM_D3_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SPIM_D3_PJ11_Msk)) | SPIM_D3_PJ11 /*!< Set PJ11 function to SPIM_D3 */ +#define SET_SPIM_D3_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SPIM_D3_PE6_Msk)) | SPIM_D3_PE6 /*!< Set PE6 function to SPIM_D3 */ +#define SET_SPIM_D3_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~SPIM_D3_PC4_Msk)) | SPIM_D3_PC4 /*!< Set PC4 function to SPIM_D3 */ +#define SET_SPIM_D3_PG10() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SPIM_D3_PG10_Msk)) | SPIM_D3_PG10 /*!< Set PG10 function to SPIM_D3 */ +#define SET_SPIM_D3_PI15() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~SPIM_D3_PI15_Msk)) | SPIM_D3_PI15 /*!< Set PI15 function to SPIM_D3 */ +#define SET_SPIM_D3_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~SPIM_D3_PA4_Msk)) | SPIM_D3_PA4 /*!< Set PA4 function to SPIM_D3 */ +#define SET_SPIM_MISO_PJ9() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SPIM_MISO_PJ9_Msk)) | SPIM_MISO_PJ9 /*!< Set PJ9 function to SPIM_MISO */ +#define SET_SPIM_MISO_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SPIM_MISO_PG13_Msk)) | SPIM_MISO_PG13 /*!< Set PG13 function to SPIM_MISO */ +#define SET_SPIM_MISO_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SPIM_MISO_PE3_Msk)) | SPIM_MISO_PE3 /*!< Set PE3 function to SPIM_MISO */ +#define SET_SPIM_MISO_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPIM_MISO_PC1_Msk)) | SPIM_MISO_PC1 /*!< Set PC1 function to SPIM_MISO */ +#define SET_SPIM_MISO_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPIM_MISO_PA1_Msk)) | SPIM_MISO_PA1 /*!< Set PA1 function to SPIM_MISO */ +#define SET_SPIM_MISO_PI13() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~SPIM_MISO_PI13_Msk)) | SPIM_MISO_PI13 /*!< Set PI13 function to SPIM_MISO */ +#define SET_SPIM_MOSI_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPIM_MOSI_PA0_Msk)) | SPIM_MOSI_PA0 /*!< Set PA0 function to SPIM_MOSI */ +#define SET_SPIM_MOSI_PG14() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~SPIM_MOSI_PG14_Msk)) | SPIM_MOSI_PG14 /*!< Set PG14 function to SPIM_MOSI */ +#define SET_SPIM_MOSI_PJ13() SYS->GPJ_MFP3 = (SYS->GPJ_MFP3 & (~SPIM_MOSI_PJ13_Msk)) | SPIM_MOSI_PJ13 /*!< Set PJ13 function to SPIM_MOSI */ +#define SET_SPIM_MOSI_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPIM_MOSI_PC0_Msk)) | SPIM_MOSI_PC0 /*!< Set PC0 function to SPIM_MOSI */ +#define SET_SPIM_MOSI_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~SPIM_MOSI_PA15_Msk)) | SPIM_MOSI_PA15 /*!< Set PA15 function to SPIM_MOSI */ +#define SET_SPIM_MOSI_PJ1() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~SPIM_MOSI_PJ1_Msk)) | SPIM_MOSI_PJ1 /*!< Set PJ1 function to SPIM_MOSI */ +#define SET_SPIM_MOSI_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~SPIM_MOSI_PE2_Msk)) | SPIM_MOSI_PE2 /*!< Set PE2 function to SPIM_MOSI */ +#define SET_SPIM_SS_PJ8() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~SPIM_SS_PJ8_Msk)) | SPIM_SS_PJ8 /*!< Set PJ8 function to SPIM_SS */ +#define SET_SPIM_SS_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~SPIM_SS_PG11_Msk)) | SPIM_SS_PG11 /*!< Set PG11 function to SPIM_SS */ +#define SET_SPIM_SS_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~SPIM_SS_PC3_Msk)) | SPIM_SS_PC3 /*!< Set PC3 function to SPIM_SS */ +#define SET_SPIM_SS_PI12() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~SPIM_SS_PI12_Msk)) | SPIM_SS_PI12 /*!< Set PI12 function to SPIM_SS */ +#define SET_SPIM_SS_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SPIM_SS_PA3_Msk)) | SPIM_SS_PA3 /*!< Set PA3 function to SPIM_SS */ +#define SET_SPIM_SS_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~SPIM_SS_PE5_Msk)) | SPIM_SS_PE5 /*!< Set PE5 function to SPIM_SS */ +#define SET_SWDH_CLK_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SWDH_CLK_PA10_Msk)) | SWDH_CLK_PA10 /*!< Set PA10 function to SWDH_CLK */ +#define SET_SWDH_DAT_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~SWDH_DAT_PA9_Msk)) | SWDH_DAT_PA9 /*!< Set PA9 function to SWDH_DAT */ +#define SET_TAMPER0_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~TAMPER0_PF6_Msk)) | TAMPER0_PF6 /*!< Set PF6 function to TAMPER0 */ +#define SET_TAMPER1_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~TAMPER1_PF7_Msk)) | TAMPER1_PF7 /*!< Set PF7 function to TAMPER1 */ +#define SET_TAMPER2_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~TAMPER2_PF8_Msk)) | TAMPER2_PF8 /*!< Set PF8 function to TAMPER2 */ +#define SET_TAMPER3_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~TAMPER3_PF9_Msk)) | TAMPER3_PF9 /*!< Set PF9 function to TAMPER3 */ +#define SET_TAMPER4_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~TAMPER4_PF10_Msk)) | TAMPER4_PF10 /*!< Set PF10 function to TAMPER4 */ +#define SET_TAMPER5_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~TAMPER5_PF11_Msk)) | TAMPER5_PF11 /*!< Set PF11 function to TAMPER5 */ +#define SET_TM0_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~TM0_PC7_Msk)) | TM0_PC7 /*!< Set PC7 function to TM0 */ +#define SET_TM0_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~TM0_PB5_Msk)) | TM0_PB5 /*!< Set PB5 function to TM0 */ +#define SET_TM0_PG2() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~TM0_PG2_Msk)) | TM0_PG2 /*!< Set PG2 function to TM0 */ +#define SET_TM0_EXT_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~TM0_EXT_PA11_Msk)) | TM0_EXT_PA11 /*!< Set PA11 function to TM0_EXT */ +#define SET_TM0_EXT_PH0() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~TM0_EXT_PH0_Msk)) | TM0_EXT_PH0 /*!< Set PH0 function to TM0_EXT */ +#define SET_TM0_EXT_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~TM0_EXT_PB15_Msk)) | TM0_EXT_PB15 /*!< Set PB15 function to TM0_EXT */ +#define SET_TM1_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~TM1_PC6_Msk)) | TM1_PC6 /*!< Set PC6 function to TM1 */ +#define SET_TM1_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~TM1_PB4_Msk)) | TM1_PB4 /*!< Set PB4 function to TM1 */ +#define SET_TM1_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~TM1_PC14_Msk)) | TM1_PC14 /*!< Set PC14 function to TM1 */ +#define SET_TM1_PG3() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~TM1_PG3_Msk)) | TM1_PG3 /*!< Set PG3 function to TM1 */ +#define SET_TM1_EXT_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~TM1_EXT_PA10_Msk)) | TM1_EXT_PA10 /*!< Set PA10 function to TM1_EXT */ +#define SET_TM1_EXT_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~TM1_EXT_PB14_Msk)) | TM1_EXT_PB14 /*!< Set PB14 function to TM1_EXT */ +#define SET_TM1_EXT_PH1() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~TM1_EXT_PH1_Msk)) | TM1_EXT_PH1 /*!< Set PH1 function to TM1_EXT */ +#define SET_TM2_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~TM2_PB3_Msk)) | TM2_PB3 /*!< Set PB3 function to TM2 */ +#define SET_TM2_PG4() SYS->GPG_MFP1 = (SYS->GPG_MFP1 & (~TM2_PG4_Msk)) | TM2_PG4 /*!< Set PG4 function to TM2 */ +#define SET_TM2_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~TM2_PD0_Msk)) | TM2_PD0 /*!< Set PD0 function to TM2 */ +#define SET_TM2_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~TM2_PA7_Msk)) | TM2_PA7 /*!< Set PA7 function to TM2 */ +#define SET_TM2_EXT_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~TM2_EXT_PB13_Msk)) | TM2_EXT_PB13 /*!< Set PB13 function to TM2_EXT */ +#define SET_TM2_EXT_PH2() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~TM2_EXT_PH2_Msk)) | TM2_EXT_PH2 /*!< Set PH2 function to TM2_EXT */ +#define SET_TM2_EXT_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~TM2_EXT_PA9_Msk)) | TM2_EXT_PA9 /*!< Set PA9 function to TM2_EXT */ +#define SET_TM3_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~TM3_PF11_Msk)) | TM3_PF11 /*!< Set PF11 function to TM3 */ +#define SET_TM3_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~TM3_PA6_Msk)) | TM3_PA6 /*!< Set PA6 function to TM3 */ +#define SET_TM3_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~TM3_PB2_Msk)) | TM3_PB2 /*!< Set PB2 function to TM3 */ +#define SET_TM3_EXT_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~TM3_EXT_PA8_Msk)) | TM3_EXT_PA8 /*!< Set PA8 function to TM3_EXT */ +#define SET_TM3_EXT_PH3() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~TM3_EXT_PH3_Msk)) | TM3_EXT_PH3 /*!< Set PH3 function to TM3_EXT */ +#define SET_TM3_EXT_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~TM3_EXT_PB12_Msk)) | TM3_EXT_PB12 /*!< Set PB12 function to TM3_EXT */ +#define SET_TRACE_CLK_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~TRACE_CLK_PE12_Msk)) | TRACE_CLK_PE12 /*!< Set PE12 function to TRACE_CLK */ +#define SET_TRACE_DATA0_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~TRACE_DATA0_PE11_Msk)) | TRACE_DATA0_PE11 /*!< Set PE11 function to TRACE_DATA0 */ +#define SET_TRACE_DATA1_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~TRACE_DATA1_PE10_Msk)) | TRACE_DATA1_PE10 /*!< Set PE10 function to TRACE_DATA1 */ +#define SET_TRACE_DATA2_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~TRACE_DATA2_PE9_Msk)) | TRACE_DATA2_PE9 /*!< Set PE9 function to TRACE_DATA2 */ +#define SET_TRACE_DATA3_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~TRACE_DATA3_PE8_Msk)) | TRACE_DATA3_PE8 /*!< Set PE8 function to TRACE_DATA3 */ +#define SET_UART0_RXD_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART0_RXD_PA0_Msk)) | UART0_RXD_PA0 /*!< Set PA0 function to UART0_RXD */ +#define SET_UART0_RXD_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART0_RXD_PC11_Msk)) | UART0_RXD_PC11 /*!< Set PC11 function to UART0_RXD */ +#define SET_UART0_RXD_PH11() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART0_RXD_PH11_Msk)) | UART0_RXD_PH11 /*!< Set PH11 function to UART0_RXD */ +#define SET_UART0_RXD_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART0_RXD_PA4_Msk)) | UART0_RXD_PA4 /*!< Set PA4 function to UART0_RXD */ +#define SET_UART0_RXD_PA6() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART0_RXD_PA6_Msk)) | UART0_RXD_PA6 /*!< Set PA6 function to UART0_RXD */ +#define SET_UART0_RXD_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~UART0_RXD_PD2_Msk)) | UART0_RXD_PD2 /*!< Set PD2 function to UART0_RXD */ +#define SET_UART0_RXD_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART0_RXD_PB8_Msk)) | UART0_RXD_PB8 /*!< Set PB8 function to UART0_RXD */ +#define SET_UART0_RXD_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART0_RXD_PF1_Msk)) | UART0_RXD_PF1 /*!< Set PF1 function to UART0_RXD */ +#define SET_UART0_RXD_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~UART0_RXD_PA15_Msk)) | UART0_RXD_PA15 /*!< Set PA15 function to UART0_RXD */ +#define SET_UART0_RXD_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART0_RXD_PF2_Msk)) | UART0_RXD_PF2 /*!< Set PF2 function to UART0_RXD */ +#define SET_UART0_RXD_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART0_RXD_PB12_Msk)) | UART0_RXD_PB12 /*!< Set PB12 function to UART0_RXD */ +#define SET_UART0_TXD_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~UART0_TXD_PD3_Msk)) | UART0_TXD_PD3 /*!< Set PD3 function to UART0_TXD */ +#define SET_UART0_TXD_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART0_TXD_PA5_Msk)) | UART0_TXD_PA5 /*!< Set PA5 function to UART0_TXD */ +#define SET_UART0_TXD_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART0_TXD_PF0_Msk)) | UART0_TXD_PF0 /*!< Set PF0 function to UART0_TXD */ +#define SET_UART0_TXD_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART0_TXD_PB9_Msk)) | UART0_TXD_PB9 /*!< Set PB9 function to UART0_TXD */ +#define SET_UART0_TXD_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART0_TXD_PF3_Msk)) | UART0_TXD_PF3 /*!< Set PF3 function to UART0_TXD */ +#define SET_UART0_TXD_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART0_TXD_PA1_Msk)) | UART0_TXD_PA1 /*!< Set PA1 function to UART0_TXD */ +#define SET_UART0_TXD_PA7() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART0_TXD_PA7_Msk)) | UART0_TXD_PA7 /*!< Set PA7 function to UART0_TXD */ +#define SET_UART0_TXD_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~UART0_TXD_PA14_Msk)) | UART0_TXD_PA14 /*!< Set PA14 function to UART0_TXD */ +#define SET_UART0_TXD_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~UART0_TXD_PC12_Msk)) | UART0_TXD_PC12 /*!< Set PC12 function to UART0_TXD */ +#define SET_UART0_TXD_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART0_TXD_PB13_Msk)) | UART0_TXD_PB13 /*!< Set PB13 function to UART0_TXD */ +#define SET_UART0_TXD_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART0_TXD_PH10_Msk)) | UART0_TXD_PH10 /*!< Set PH10 function to UART0_TXD */ +#define SET_UART0_nCTS_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART0_nCTS_PC7_Msk)) | UART0_nCTS_PC7 /*!< Set PC7 function to UART0_nCTS */ +#define SET_UART0_nCTS_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART0_nCTS_PB15_Msk)) | UART0_nCTS_PB15 /*!< Set PB15 function to UART0_nCTS */ +#define SET_UART0_nCTS_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART0_nCTS_PA5_Msk)) | UART0_nCTS_PA5 /*!< Set PA5 function to UART0_nCTS */ +#define SET_UART0_nCTS_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART0_nCTS_PB11_Msk)) | UART0_nCTS_PB11 /*!< Set PB11 function to UART0_nCTS */ +#define SET_UART0_nRTS_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART0_nRTS_PA4_Msk)) | UART0_nRTS_PA4 /*!< Set PA4 function to UART0_nRTS */ +#define SET_UART0_nRTS_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART0_nRTS_PB14_Msk)) | UART0_nRTS_PB14 /*!< Set PB14 function to UART0_nRTS */ +#define SET_UART0_nRTS_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART0_nRTS_PB10_Msk)) | UART0_nRTS_PB10 /*!< Set PB10 function to UART0_nRTS */ +#define SET_UART0_nRTS_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART0_nRTS_PC6_Msk)) | UART0_nRTS_PC6 /*!< Set PC6 function to UART0_nRTS */ +#define SET_UART1_RXD_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART1_RXD_PH9_Msk)) | UART1_RXD_PH9 /*!< Set PH9 function to UART1_RXD */ +#define SET_UART1_RXD_PD6() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~UART1_RXD_PD6_Msk)) | UART1_RXD_PD6 /*!< Set PD6 function to UART1_RXD */ +#define SET_UART1_RXD_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART1_RXD_PF1_Msk)) | UART1_RXD_PF1 /*!< Set PF1 function to UART1_RXD */ +#define SET_UART1_RXD_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART1_RXD_PA2_Msk)) | UART1_RXD_PA2 /*!< Set PA2 function to UART1_RXD */ +#define SET_UART1_RXD_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART1_RXD_PC8_Msk)) | UART1_RXD_PC8 /*!< Set PC8 function to UART1_RXD */ +#define SET_UART1_RXD_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~UART1_RXD_PB2_Msk)) | UART1_RXD_PB2 /*!< Set PB2 function to UART1_RXD */ +#define SET_UART1_RXD_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART1_RXD_PD10_Msk)) | UART1_RXD_PD10 /*!< Set PD10 function to UART1_RXD */ +#define SET_UART1_RXD_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~UART1_RXD_PG1_Msk)) | UART1_RXD_PG1 /*!< Set PG1 function to UART1_RXD */ +#define SET_UART1_RXD_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~UART1_RXD_PB6_Msk)) | UART1_RXD_PB6 /*!< Set PB6 function to UART1_RXD */ +#define SET_UART1_RXD_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~UART1_RXD_PA8_Msk)) | UART1_RXD_PA8 /*!< Set PA8 function to UART1_RXD */ +#define SET_UART1_TXD_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART1_TXD_PA3_Msk)) | UART1_TXD_PA3 /*!< Set PA3 function to UART1_TXD */ +#define SET_UART1_TXD_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART1_TXD_PD11_Msk)) | UART1_TXD_PD11 /*!< Set PD11 function to UART1_TXD */ +#define SET_UART1_TXD_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART1_TXD_PH8_Msk)) | UART1_TXD_PH8 /*!< Set PH8 function to UART1_TXD */ +#define SET_UART1_TXD_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~UART1_TXD_PB3_Msk)) | UART1_TXD_PB3 /*!< Set PB3 function to UART1_TXD */ +#define SET_UART1_TXD_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~UART1_TXD_PB7_Msk)) | UART1_TXD_PB7 /*!< Set PB7 function to UART1_TXD */ +#define SET_UART1_TXD_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~UART1_TXD_PA9_Msk)) | UART1_TXD_PA9 /*!< Set PA9 function to UART1_TXD */ +#define SET_UART1_TXD_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART1_TXD_PF0_Msk)) | UART1_TXD_PF0 /*!< Set PF0 function to UART1_TXD */ +#define SET_UART1_TXD_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~UART1_TXD_PE13_Msk)) | UART1_TXD_PE13 /*!< Set PE13 function to UART1_TXD */ +#define SET_UART1_TXD_PD7() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~UART1_TXD_PD7_Msk)) | UART1_TXD_PD7 /*!< Set PD7 function to UART1_TXD */ +#define SET_UART1_TXD_PG0() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~UART1_TXD_PG0_Msk)) | UART1_TXD_PG0 /*!< Set PG0 function to UART1_TXD */ +#define SET_UART1_nCTS_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~UART1_nCTS_PE11_Msk)) | UART1_nCTS_PE11 /*!< Set PE11 function to UART1_nCTS */ +#define SET_UART1_nCTS_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART1_nCTS_PB9_Msk)) | UART1_nCTS_PB9 /*!< Set PB9 function to UART1_nCTS */ +#define SET_UART1_nCTS_PA1() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART1_nCTS_PA1_Msk)) | UART1_nCTS_PA1 /*!< Set PA1 function to UART1_nCTS */ +#define SET_UART1_nRTS_PE12() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~UART1_nRTS_PE12_Msk)) | UART1_nRTS_PE12 /*!< Set PE12 function to UART1_nRTS */ +#define SET_UART1_nRTS_PA0() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART1_nRTS_PA0_Msk)) | UART1_nRTS_PA0 /*!< Set PA0 function to UART1_nRTS */ +#define SET_UART1_nRTS_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART1_nRTS_PB8_Msk)) | UART1_nRTS_PB8 /*!< Set PB8 function to UART1_nRTS */ +#define SET_UART2_RXD_PC0() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~UART2_RXD_PC0_Msk)) | UART2_RXD_PC0 /*!< Set PC0 function to UART2_RXD */ +#define SET_UART2_RXD_PE9() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~UART2_RXD_PE9_Msk)) | UART2_RXD_PE9 /*!< Set PE9 function to UART2_RXD */ +#define SET_UART2_RXD_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~UART2_RXD_PB0_Msk)) | UART2_RXD_PB0 /*!< Set PB0 function to UART2_RXD */ +#define SET_UART2_RXD_PF1() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART2_RXD_PF1_Msk)) | UART2_RXD_PF1 /*!< Set PF1 function to UART2_RXD */ +#define SET_UART2_RXD_PI7() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~UART2_RXD_PI7_Msk)) | UART2_RXD_PI7 /*!< Set PI7 function to UART2_RXD */ +#define SET_UART2_RXD_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~UART2_RXD_PD12_Msk)) | UART2_RXD_PD12 /*!< Set PD12 function to UART2_RXD */ +#define SET_UART2_RXD_PE15() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~UART2_RXD_PE15_Msk)) | UART2_RXD_PE15 /*!< Set PE15 function to UART2_RXD */ +#define SET_UART2_RXD_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART2_RXD_PC4_Msk)) | UART2_RXD_PC4 /*!< Set PC4 function to UART2_RXD */ +#define SET_UART2_RXD_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~UART2_RXD_PF5_Msk)) | UART2_RXD_PF5 /*!< Set PF5 function to UART2_RXD */ +#define SET_UART2_RXD_PG0() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~UART2_RXD_PG0_Msk)) | UART2_RXD_PG0 /*!< Set PG0 function to UART2_RXD */ +#define SET_UART2_RXD_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~UART2_RXD_PB4_Msk)) | UART2_RXD_PB4 /*!< Set PB4 function to UART2_RXD */ +#define SET_UART2_RXD_PI11() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~UART2_RXD_PI11_Msk)) | UART2_RXD_PI11 /*!< Set PI11 function to UART2_RXD */ +#define SET_UART2_TXD_PE8() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~UART2_TXD_PE8_Msk)) | UART2_TXD_PE8 /*!< Set PE8 function to UART2_TXD */ +#define SET_UART2_TXD_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART2_TXD_PC5_Msk)) | UART2_TXD_PC5 /*!< Set PC5 function to UART2_TXD */ +#define SET_UART2_TXD_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~UART2_TXD_PB5_Msk)) | UART2_TXD_PB5 /*!< Set PB5 function to UART2_TXD */ +#define SET_UART2_TXD_PF0() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART2_TXD_PF0_Msk)) | UART2_TXD_PF0 /*!< Set PF0 function to UART2_TXD */ +#define SET_UART2_TXD_PG1() SYS->GPG_MFP0 = (SYS->GPG_MFP0 & (~UART2_TXD_PG1_Msk)) | UART2_TXD_PG1 /*!< Set PG1 function to UART2_TXD */ +#define SET_UART2_TXD_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~UART2_TXD_PC13_Msk)) | UART2_TXD_PC13 /*!< Set PC13 function to UART2_TXD */ +#define SET_UART2_TXD_PE14() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~UART2_TXD_PE14_Msk)) | UART2_TXD_PE14 /*!< Set PE14 function to UART2_TXD */ +#define SET_UART2_TXD_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~UART2_TXD_PF4_Msk)) | UART2_TXD_PF4 /*!< Set PF4 function to UART2_TXD */ +#define SET_UART2_TXD_PI10() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~UART2_TXD_PI10_Msk)) | UART2_TXD_PI10 /*!< Set PI10 function to UART2_TXD */ +#define SET_UART2_TXD_PI6() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~UART2_TXD_PI6_Msk)) | UART2_TXD_PI6 /*!< Set PI6 function to UART2_TXD */ +#define SET_UART2_TXD_PB1() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~UART2_TXD_PB1_Msk)) | UART2_TXD_PB1 /*!< Set PB1 function to UART2_TXD */ +#define SET_UART2_TXD_PC1() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~UART2_TXD_PC1_Msk)) | UART2_TXD_PC1 /*!< Set PC1 function to UART2_TXD */ +#define SET_UART2_nCTS_PD9() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART2_nCTS_PD9_Msk)) | UART2_nCTS_PD9 /*!< Set PD9 function to UART2_nCTS */ +#define SET_UART2_nCTS_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~UART2_nCTS_PC2_Msk)) | UART2_nCTS_PC2 /*!< Set PC2 function to UART2_nCTS */ +#define SET_UART2_nCTS_PI9() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~UART2_nCTS_PI9_Msk)) | UART2_nCTS_PI9 /*!< Set PI9 function to UART2_nCTS */ +#define SET_UART2_nCTS_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~UART2_nCTS_PF5_Msk)) | UART2_nCTS_PF5 /*!< Set PF5 function to UART2_nCTS */ +#define SET_UART2_nRTS_PI8() SYS->GPI_MFP2 = (SYS->GPI_MFP2 & (~UART2_nRTS_PI8_Msk)) | UART2_nRTS_PI8 /*!< Set PI8 function to UART2_nRTS */ +#define SET_UART2_nRTS_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~UART2_nRTS_PF4_Msk)) | UART2_nRTS_PF4 /*!< Set PF4 function to UART2_nRTS */ +#define SET_UART2_nRTS_PD8() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART2_nRTS_PD8_Msk)) | UART2_nRTS_PD8 /*!< Set PD8 function to UART2_nRTS */ +#define SET_UART2_nRTS_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~UART2_nRTS_PC3_Msk)) | UART2_nRTS_PC3 /*!< Set PC3 function to UART2_nRTS */ +#define SET_UART3_RXD_PI15() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~UART3_RXD_PI15_Msk)) | UART3_RXD_PI15 /*!< Set PI15 function to UART3_RXD */ +#define SET_UART3_RXD_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART3_RXD_PE0_Msk)) | UART3_RXD_PE0 /*!< Set PE0 function to UART3_RXD */ +#define SET_UART3_RXD_PE11() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~UART3_RXD_PE11_Msk)) | UART3_RXD_PE11 /*!< Set PE11 function to UART3_RXD */ +#define SET_UART3_RXD_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART3_RXD_PB14_Msk)) | UART3_RXD_PB14 /*!< Set PB14 function to UART3_RXD */ +#define SET_UART3_RXD_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART3_RXD_PC9_Msk)) | UART3_RXD_PC9 /*!< Set PC9 function to UART3_RXD */ +#define SET_UART3_RXD_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~UART3_RXD_PD0_Msk)) | UART3_RXD_PD0 /*!< Set PD0 function to UART3_RXD */ +#define SET_UART3_RXD_PC2() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~UART3_RXD_PC2_Msk)) | UART3_RXD_PC2 /*!< Set PC2 function to UART3_RXD */ +#define SET_UART3_TXD_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART3_TXD_PB15_Msk)) | UART3_TXD_PB15 /*!< Set PB15 function to UART3_TXD */ +#define SET_UART3_TXD_PI14() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~UART3_TXD_PI14_Msk)) | UART3_TXD_PI14 /*!< Set PI14 function to UART3_TXD */ +#define SET_UART3_TXD_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~UART3_TXD_PD1_Msk)) | UART3_TXD_PD1 /*!< Set PD1 function to UART3_TXD */ +#define SET_UART3_TXD_PE10() SYS->GPE_MFP2 = (SYS->GPE_MFP2 & (~UART3_TXD_PE10_Msk)) | UART3_TXD_PE10 /*!< Set PE10 function to UART3_TXD */ +#define SET_UART3_TXD_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART3_TXD_PE1_Msk)) | UART3_TXD_PE1 /*!< Set PE1 function to UART3_TXD */ +#define SET_UART3_TXD_PC3() SYS->GPC_MFP0 = (SYS->GPC_MFP0 & (~UART3_TXD_PC3_Msk)) | UART3_TXD_PC3 /*!< Set PC3 function to UART3_TXD */ +#define SET_UART3_TXD_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART3_TXD_PC10_Msk)) | UART3_TXD_PC10 /*!< Set PC10 function to UART3_TXD */ +#define SET_UART3_nCTS_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART3_nCTS_PB12_Msk)) | UART3_nCTS_PB12 /*!< Set PB12 function to UART3_nCTS */ +#define SET_UART3_nCTS_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART3_nCTS_PH9_Msk)) | UART3_nCTS_PH9 /*!< Set PH9 function to UART3_nCTS */ +#define SET_UART3_nCTS_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~UART3_nCTS_PD2_Msk)) | UART3_nCTS_PD2 /*!< Set PD2 function to UART3_nCTS */ +#define SET_UART3_nRTS_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~UART3_nRTS_PB13_Msk)) | UART3_nRTS_PB13 /*!< Set PB13 function to UART3_nRTS */ +#define SET_UART3_nRTS_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART3_nRTS_PH8_Msk)) | UART3_nRTS_PH8 /*!< Set PH8 function to UART3_nRTS */ +#define SET_UART3_nRTS_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~UART3_nRTS_PD3_Msk)) | UART3_nRTS_PD3 /*!< Set PD3 function to UART3_nRTS */ +#define SET_UART4_RXD_PB10() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART4_RXD_PB10_Msk)) | UART4_RXD_PB10 /*!< Set PB10 function to UART4_RXD */ +#define SET_UART4_RXD_PI13() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~UART4_RXD_PI13_Msk)) | UART4_RXD_PI13 /*!< Set PI13 function to UART4_RXD */ +#define SET_UART4_RXD_PH3() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~UART4_RXD_PH3_Msk)) | UART4_RXD_PH3 /*!< Set PH3 function to UART4_RXD */ +#define SET_UART4_RXD_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~UART4_RXD_PA13_Msk)) | UART4_RXD_PA13 /*!< Set PA13 function to UART4_RXD */ +#define SET_UART4_RXD_PH11() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART4_RXD_PH11_Msk)) | UART4_RXD_PH11 /*!< Set PH11 function to UART4_RXD */ +#define SET_UART4_RXD_PA2() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART4_RXD_PA2_Msk)) | UART4_RXD_PA2 /*!< Set PA2 function to UART4_RXD */ +#define SET_UART4_RXD_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART4_RXD_PC6_Msk)) | UART4_RXD_PC6 /*!< Set PC6 function to UART4_RXD */ +#define SET_UART4_RXD_PF6() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~UART4_RXD_PF6_Msk)) | UART4_RXD_PF6 /*!< Set PF6 function to UART4_RXD */ +#define SET_UART4_RXD_PC4() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART4_RXD_PC4_Msk)) | UART4_RXD_PC4 /*!< Set PC4 function to UART4_RXD */ +#define SET_UART4_TXD_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~UART4_TXD_PA12_Msk)) | UART4_TXD_PA12 /*!< Set PA12 function to UART4_TXD */ +#define SET_UART4_TXD_PB11() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART4_TXD_PB11_Msk)) | UART4_TXD_PB11 /*!< Set PB11 function to UART4_TXD */ +#define SET_UART4_TXD_PF7() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~UART4_TXD_PF7_Msk)) | UART4_TXD_PF7 /*!< Set PF7 function to UART4_TXD */ +#define SET_UART4_TXD_PH2() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~UART4_TXD_PH2_Msk)) | UART4_TXD_PH2 /*!< Set PH2 function to UART4_TXD */ +#define SET_UART4_TXD_PI12() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~UART4_TXD_PI12_Msk)) | UART4_TXD_PI12 /*!< Set PI12 function to UART4_TXD */ +#define SET_UART4_TXD_PC5() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART4_TXD_PC5_Msk)) | UART4_TXD_PC5 /*!< Set PC5 function to UART4_TXD */ +#define SET_UART4_TXD_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART4_TXD_PC7_Msk)) | UART4_TXD_PC7 /*!< Set PC7 function to UART4_TXD */ +#define SET_UART4_TXD_PA3() SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~UART4_TXD_PA3_Msk)) | UART4_TXD_PA3 /*!< Set PA3 function to UART4_TXD */ +#define SET_UART4_TXD_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART4_TXD_PH10_Msk)) | UART4_TXD_PH10 /*!< Set PH10 function to UART4_TXD */ +#define SET_UART4_nCTS_PC8() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART4_nCTS_PC8_Msk)) | UART4_nCTS_PC8 /*!< Set PC8 function to UART4_nCTS */ +#define SET_UART4_nCTS_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART4_nCTS_PE1_Msk)) | UART4_nCTS_PE1 /*!< Set PE1 function to UART4_nCTS */ +#define SET_UART4_nRTS_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART4_nRTS_PE0_Msk)) | UART4_nRTS_PE0 /*!< Set PE0 function to UART4_nRTS */ +#define SET_UART4_nRTS_PE13() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~UART4_nRTS_PE13_Msk)) | UART4_nRTS_PE13 /*!< Set PE13 function to UART4_nRTS */ +#define SET_UART5_RXD_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART5_RXD_PF10_Msk)) | UART5_RXD_PF10 /*!< Set PF10 function to UART5_RXD */ +#define SET_UART5_RXD_PB4() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~UART5_RXD_PB4_Msk)) | UART5_RXD_PB4 /*!< Set PB4 function to UART5_RXD */ +#define SET_UART5_RXD_PH1() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~UART5_RXD_PH1_Msk)) | UART5_RXD_PH1 /*!< Set PH1 function to UART5_RXD */ +#define SET_UART5_RXD_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART5_RXD_PE6_Msk)) | UART5_RXD_PE6 /*!< Set PE6 function to UART5_RXD */ +#define SET_UART5_RXD_PA4() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART5_RXD_PA4_Msk)) | UART5_RXD_PA4 /*!< Set PA4 function to UART5_RXD */ +#define SET_UART5_TXD_PB5() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~UART5_TXD_PB5_Msk)) | UART5_TXD_PB5 /*!< Set PB5 function to UART5_TXD */ +#define SET_UART5_TXD_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART5_TXD_PF11_Msk)) | UART5_TXD_PF11 /*!< Set PF11 function to UART5_TXD */ +#define SET_UART5_TXD_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART5_TXD_PE7_Msk)) | UART5_TXD_PE7 /*!< Set PE7 function to UART5_TXD */ +#define SET_UART5_TXD_PA5() SYS->GPA_MFP1 = (SYS->GPA_MFP1 & (~UART5_TXD_PA5_Msk)) | UART5_TXD_PA5 /*!< Set PA5 function to UART5_TXD */ +#define SET_UART5_TXD_PH0() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~UART5_TXD_PH0_Msk)) | UART5_TXD_PH0 /*!< Set PH0 function to UART5_TXD */ +#define SET_UART5_nCTS_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART5_nCTS_PF8_Msk)) | UART5_nCTS_PF8 /*!< Set PF8 function to UART5_nCTS */ +#define SET_UART5_nCTS_PH3() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~UART5_nCTS_PH3_Msk)) | UART5_nCTS_PH3 /*!< Set PH3 function to UART5_nCTS */ +#define SET_UART5_nCTS_PB2() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~UART5_nCTS_PB2_Msk)) | UART5_nCTS_PB2 /*!< Set PB2 function to UART5_nCTS */ +#define SET_UART5_nRTS_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART5_nRTS_PF9_Msk)) | UART5_nRTS_PF9 /*!< Set PF9 function to UART5_nRTS */ +#define SET_UART5_nRTS_PH2() SYS->GPH_MFP0 = (SYS->GPH_MFP0 & (~UART5_nRTS_PH2_Msk)) | UART5_nRTS_PH2 /*!< Set PH2 function to UART5_nRTS */ +#define SET_UART5_nRTS_PB3() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~UART5_nRTS_PB3_Msk)) | UART5_nRTS_PB3 /*!< Set PB3 function to UART5_nRTS */ +#define SET_UART6_RXD_PE15() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~UART6_RXD_PE15_Msk)) | UART6_RXD_PE15 /*!< Set PE15 function to UART6_RXD */ +#define SET_UART6_RXD_PC6() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART6_RXD_PC6_Msk)) | UART6_RXD_PC6 /*!< Set PC6 function to UART6_RXD */ +#define SET_UART6_RXD_PH5() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART6_RXD_PH5_Msk)) | UART6_RXD_PH5 /*!< Set PH5 function to UART6_RXD */ +#define SET_UART6_RXD_PG14() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~UART6_RXD_PG14_Msk)) | UART6_RXD_PG14 /*!< Set PG14 function to UART6_RXD */ +#define SET_UART6_RXD_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~UART6_RXD_PA10_Msk)) | UART6_RXD_PA10 /*!< Set PA10 function to UART6_RXD */ +#define SET_UART6_RXD_PD13() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~UART6_RXD_PD13_Msk)) | UART6_RXD_PD13 /*!< Set PD13 function to UART6_RXD */ +#define SET_UART6_RXD_PC11() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART6_RXD_PC11_Msk)) | UART6_RXD_PC11 /*!< Set PC11 function to UART6_RXD */ +#define SET_UART6_RXD_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART6_RXD_PE4_Msk)) | UART6_RXD_PE4 /*!< Set PE4 function to UART6_RXD */ +#define SET_UART6_RXD_PJ11() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~UART6_RXD_PJ11_Msk)) | UART6_RXD_PJ11 /*!< Set PJ11 function to UART6_RXD */ +#define SET_UART6_TXD_PG13() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~UART6_TXD_PG13_Msk)) | UART6_TXD_PG13 /*!< Set PG13 function to UART6_TXD */ +#define SET_UART6_TXD_PE14() SYS->GPE_MFP3 = (SYS->GPE_MFP3 & (~UART6_TXD_PE14_Msk)) | UART6_TXD_PE14 /*!< Set PE14 function to UART6_TXD */ +#define SET_UART6_TXD_PC12() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~UART6_TXD_PC12_Msk)) | UART6_TXD_PC12 /*!< Set PC12 function to UART6_TXD */ +#define SET_UART6_TXD_PC7() SYS->GPC_MFP1 = (SYS->GPC_MFP1 & (~UART6_TXD_PC7_Msk)) | UART6_TXD_PC7 /*!< Set PC7 function to UART6_TXD */ +#define SET_UART6_TXD_PH4() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART6_TXD_PH4_Msk)) | UART6_TXD_PH4 /*!< Set PH4 function to UART6_TXD */ +#define SET_UART6_TXD_PJ10() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~UART6_TXD_PJ10_Msk)) | UART6_TXD_PJ10 /*!< Set PJ10 function to UART6_TXD */ +#define SET_UART6_TXD_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~UART6_TXD_PA11_Msk)) | UART6_TXD_PA11 /*!< Set PA11 function to UART6_TXD */ +#define SET_UART6_TXD_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART6_TXD_PE5_Msk)) | UART6_TXD_PE5 /*!< Set PE5 function to UART6_TXD */ +#define SET_UART6_nCTS_PC9() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART6_nCTS_PC9_Msk)) | UART6_nCTS_PC9 /*!< Set PC9 function to UART6_nCTS */ +#define SET_UART6_nCTS_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART6_nCTS_PE2_Msk)) | UART6_nCTS_PE2 /*!< Set PE2 function to UART6_nCTS */ +#define SET_UART6_nRTS_PC10() SYS->GPC_MFP2 = (SYS->GPC_MFP2 & (~UART6_nRTS_PC10_Msk)) | UART6_nRTS_PC10 /*!< Set PC10 function to UART6_nRTS */ +#define SET_UART6_nRTS_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART6_nRTS_PE3_Msk)) | UART6_nRTS_PE3 /*!< Set PE3 function to UART6_nRTS */ +#define SET_UART7_RXD_PD8() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART7_RXD_PD8_Msk)) | UART7_RXD_PD8 /*!< Set PD8 function to UART7_RXD */ +#define SET_UART7_RXD_PG12() SYS->GPG_MFP3 = (SYS->GPG_MFP3 & (~UART7_RXD_PG12_Msk)) | UART7_RXD_PG12 /*!< Set PG12 function to UART7_RXD */ +#define SET_UART7_RXD_PJ9() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~UART7_RXD_PJ9_Msk)) | UART7_RXD_PJ9 /*!< Set PJ9 function to UART7_RXD */ +#define SET_UART7_RXD_PH7() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART7_RXD_PH7_Msk)) | UART7_RXD_PH7 /*!< Set PH7 function to UART7_RXD */ +#define SET_UART7_RXD_PB8() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART7_RXD_PB8_Msk)) | UART7_RXD_PB8 /*!< Set PB8 function to UART7_RXD */ +#define SET_UART7_RXD_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART7_RXD_PE2_Msk)) | UART7_RXD_PE2 /*!< Set PE2 function to UART7_RXD */ +#define SET_UART7_RXD_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~UART7_RXD_PA8_Msk)) | UART7_RXD_PA8 /*!< Set PA8 function to UART7_RXD */ +#define SET_UART7_TXD_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART7_TXD_PE3_Msk)) | UART7_TXD_PE3 /*!< Set PE3 function to UART7_TXD */ +#define SET_UART7_TXD_PG11() SYS->GPG_MFP2 = (SYS->GPG_MFP2 & (~UART7_TXD_PG11_Msk)) | UART7_TXD_PG11 /*!< Set PG11 function to UART7_TXD */ +#define SET_UART7_TXD_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~UART7_TXD_PA9_Msk)) | UART7_TXD_PA9 /*!< Set PA9 function to UART7_TXD */ +#define SET_UART7_TXD_PJ8() SYS->GPJ_MFP2 = (SYS->GPJ_MFP2 & (~UART7_TXD_PJ8_Msk)) | UART7_TXD_PJ8 /*!< Set PJ8 function to UART7_TXD */ +#define SET_UART7_TXD_PB9() SYS->GPB_MFP2 = (SYS->GPB_MFP2 & (~UART7_TXD_PB9_Msk)) | UART7_TXD_PB9 /*!< Set PB9 function to UART7_TXD */ +#define SET_UART7_TXD_PD9() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART7_TXD_PD9_Msk)) | UART7_TXD_PD9 /*!< Set PD9 function to UART7_TXD */ +#define SET_UART7_TXD_PH6() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART7_TXD_PH6_Msk)) | UART7_TXD_PH6 /*!< Set PH6 function to UART7_TXD */ +#define SET_UART7_nCTS_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART7_nCTS_PE4_Msk)) | UART7_nCTS_PE4 /*!< Set PE4 function to UART7_nCTS */ +#define SET_UART7_nCTS_PH5() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART7_nCTS_PH5_Msk)) | UART7_nCTS_PH5 /*!< Set PH5 function to UART7_nCTS */ +#define SET_UART7_nRTS_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART7_nRTS_PE5_Msk)) | UART7_nRTS_PE5 /*!< Set PE5 function to UART7_nRTS */ +#define SET_UART7_nRTS_PH4() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART7_nRTS_PH4_Msk)) | UART7_nRTS_PH4 /*!< Set PH4 function to UART7_nRTS */ +#define SET_UART8_RXD_PJ1() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~UART8_RXD_PJ1_Msk)) | UART8_RXD_PJ1 /*!< Set PJ1 function to UART8_RXD */ +#define SET_UART8_RXD_PJ5() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~UART8_RXD_PJ5_Msk)) | UART8_RXD_PJ5 /*!< Set PJ5 function to UART8_RXD */ +#define SET_UART8_RXD_PE0() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART8_RXD_PE0_Msk)) | UART8_RXD_PE0 /*!< Set PE0 function to UART8_RXD */ +#define SET_UART8_RXD_PD10() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART8_RXD_PD10_Msk)) | UART8_RXD_PD10 /*!< Set PD10 function to UART8_RXD */ +#define SET_UART8_TXD_PE1() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART8_TXD_PE1_Msk)) | UART8_TXD_PE1 /*!< Set PE1 function to UART8_TXD */ +#define SET_UART8_TXD_PD11() SYS->GPD_MFP2 = (SYS->GPD_MFP2 & (~UART8_TXD_PD11_Msk)) | UART8_TXD_PD11 /*!< Set PD11 function to UART8_TXD */ +#define SET_UART8_TXD_PJ0() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~UART8_TXD_PJ0_Msk)) | UART8_TXD_PJ0 /*!< Set PJ0 function to UART8_TXD */ +#define SET_UART8_TXD_PJ4() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~UART8_TXD_PJ4_Msk)) | UART8_TXD_PJ4 /*!< Set PJ4 function to UART8_TXD */ +#define SET_UART8_nCTS_PJ2() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~UART8_nCTS_PJ2_Msk)) | UART8_nCTS_PJ2 /*!< Set PJ2 function to UART8_nCTS */ +#define SET_UART8_nCTS_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~UART8_nCTS_PC13_Msk)) | UART8_nCTS_PC13 /*!< Set PC13 function to UART8_nCTS */ +#define SET_UART8_nCTS_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART8_nCTS_PE3_Msk)) | UART8_nCTS_PE3 /*!< Set PE3 function to UART8_nCTS */ +#define SET_UART8_nCTS_PI14() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~UART8_nCTS_PI14_Msk)) | UART8_nCTS_PI14 /*!< Set PI14 function to UART8_nCTS */ +#define SET_UART8_nRTS_PI15() SYS->GPI_MFP3 = (SYS->GPI_MFP3 & (~UART8_nRTS_PI15_Msk)) | UART8_nRTS_PI15 /*!< Set PI15 function to UART8_nRTS */ +#define SET_UART8_nRTS_PJ3() SYS->GPJ_MFP0 = (SYS->GPJ_MFP0 & (~UART8_nRTS_PJ3_Msk)) | UART8_nRTS_PJ3 /*!< Set PJ3 function to UART8_nRTS */ +#define SET_UART8_nRTS_PD12() SYS->GPD_MFP3 = (SYS->GPD_MFP3 & (~UART8_nRTS_PD12_Msk)) | UART8_nRTS_PD12 /*!< Set PD12 function to UART8_nRTS */ +#define SET_UART8_nRTS_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~UART8_nRTS_PE2_Msk)) | UART8_nRTS_PE2 /*!< Set PE2 function to UART8_nRTS */ +#define SET_UART9_RXD_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART9_RXD_PF2_Msk)) | UART9_RXD_PF2 /*!< Set PF2 function to UART9_RXD */ +#define SET_UART9_RXD_PH11() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART9_RXD_PH11_Msk)) | UART9_RXD_PH11 /*!< Set PH11 function to UART9_RXD */ +#define SET_UART9_RXD_PF8() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART9_RXD_PF8_Msk)) | UART9_RXD_PF8 /*!< Set PF8 function to UART9_RXD */ +#define SET_UART9_RXD_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART9_RXD_PE4_Msk)) | UART9_RXD_PE4 /*!< Set PE4 function to UART9_RXD */ +#define SET_UART9_RXD_PH13() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~UART9_RXD_PH13_Msk)) | UART9_RXD_PH13 /*!< Set PH13 function to UART9_RXD */ +#define SET_UART9_TXD_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART9_TXD_PE5_Msk)) | UART9_TXD_PE5 /*!< Set PE5 function to UART9_TXD */ +#define SET_UART9_TXD_PF9() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART9_TXD_PF9_Msk)) | UART9_TXD_PF9 /*!< Set PF9 function to UART9_TXD */ +#define SET_UART9_TXD_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~UART9_TXD_PF3_Msk)) | UART9_TXD_PF3 /*!< Set PF3 function to UART9_TXD */ +#define SET_UART9_TXD_PH12() SYS->GPH_MFP3 = (SYS->GPH_MFP3 & (~UART9_TXD_PH12_Msk)) | UART9_TXD_PH12 /*!< Set PH12 function to UART9_TXD */ +#define SET_UART9_TXD_PH10() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART9_TXD_PH10_Msk)) | UART9_TXD_PH10 /*!< Set PH10 function to UART9_TXD */ +#define SET_UART9_nCTS_PJ6() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~UART9_nCTS_PJ6_Msk)) | UART9_nCTS_PJ6 /*!< Set PJ6 function to UART9_nCTS */ +#define SET_UART9_nCTS_PF11() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART9_nCTS_PF11_Msk)) | UART9_nCTS_PF11 /*!< Set PF11 function to UART9_nCTS */ +#define SET_UART9_nCTS_PH6() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART9_nCTS_PH6_Msk)) | UART9_nCTS_PH6 /*!< Set PH6 function to UART9_nCTS */ +#define SET_UART9_nCTS_PH8() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART9_nCTS_PH8_Msk)) | UART9_nCTS_PH8 /*!< Set PH8 function to UART9_nCTS */ +#define SET_UART9_nCTS_PE7() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART9_nCTS_PE7_Msk)) | UART9_nCTS_PE7 /*!< Set PE7 function to UART9_nCTS */ +#define SET_UART9_nRTS_PH7() SYS->GPH_MFP1 = (SYS->GPH_MFP1 & (~UART9_nRTS_PH7_Msk)) | UART9_nRTS_PH7 /*!< Set PH7 function to UART9_nRTS */ +#define SET_UART9_nRTS_PF10() SYS->GPF_MFP2 = (SYS->GPF_MFP2 & (~UART9_nRTS_PF10_Msk)) | UART9_nRTS_PF10 /*!< Set PF10 function to UART9_nRTS */ +#define SET_UART9_nRTS_PH9() SYS->GPH_MFP2 = (SYS->GPH_MFP2 & (~UART9_nRTS_PH9_Msk)) | UART9_nRTS_PH9 /*!< Set PH9 function to UART9_nRTS */ +#define SET_UART9_nRTS_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~UART9_nRTS_PE6_Msk)) | UART9_nRTS_PE6 /*!< Set PE6 function to UART9_nRTS */ +#define SET_UART9_nRTS_PJ7() SYS->GPJ_MFP1 = (SYS->GPJ_MFP1 & (~UART9_nRTS_PJ7_Msk)) | UART9_nRTS_PJ7 /*!< Set PJ7 function to UART9_nRTS */ +#define SET_USB_D_P_PA14() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~USB_D_P_PA14_Msk)) | USB_D_P_PA14 /*!< Set PA14 function to USB_D+ */ +#define SET_USB_D_N_PA13() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~USB_D_N_PA13_Msk)) | USB_D_N_PA13 /*!< Set PA13 function to USB_D- */ +#define SET_USB_OTG_ID_PA15() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~USB_OTG_ID_PA15_Msk)) | USB_OTG_ID_PA15 /*!< Set PA15 function to USB_OTG_ID */ +#define SET_USB_VBUS_PA12() SYS->GPA_MFP3 = (SYS->GPA_MFP3 & (~USB_VBUS_PA12_Msk)) | USB_VBUS_PA12 /*!< Set PA12 function to USB_VBUS */ +#define SET_USB_VBUS_EN_PB6() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~USB_VBUS_EN_PB6_Msk)) | USB_VBUS_EN_PB6 /*!< Set PB6 function to USB_VBUS_EN */ +#define SET_USB_VBUS_EN_PI7() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~USB_VBUS_EN_PI7_Msk)) | USB_VBUS_EN_PI7 /*!< Set PI7 function to USB_VBUS_EN */ +#define SET_USB_VBUS_EN_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~USB_VBUS_EN_PB15_Msk)) | USB_VBUS_EN_PB15 /*!< Set PB15 function to USB_VBUS_EN */ +#define SET_USB_VBUS_ST_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~USB_VBUS_ST_PB14_Msk)) | USB_VBUS_ST_PB14 /*!< Set PB14 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~USB_VBUS_ST_PC14_Msk)) | USB_VBUS_ST_PC14 /*!< Set PC14 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PD4() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~USB_VBUS_ST_PD4_Msk)) | USB_VBUS_ST_PD4 /*!< Set PD4 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PB7() SYS->GPB_MFP1 = (SYS->GPB_MFP1 & (~USB_VBUS_ST_PB7_Msk)) | USB_VBUS_ST_PB7 /*!< Set PB7 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PI6() SYS->GPI_MFP1 = (SYS->GPI_MFP1 & (~USB_VBUS_ST_PI6_Msk)) | USB_VBUS_ST_PI6 /*!< Set PI6 function to USB_VBUS_ST */ +#define SET_USCI0_CLK_PD0() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~USCI0_CLK_PD0_Msk)) | USCI0_CLK_PD0 /*!< Set PD0 function to USCI0_CLK */ +#define SET_USCI0_CLK_PE2() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~USCI0_CLK_PE2_Msk)) | USCI0_CLK_PE2 /*!< Set PE2 function to USCI0_CLK */ +#define SET_USCI0_CLK_PA11() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~USCI0_CLK_PA11_Msk)) | USCI0_CLK_PA11 /*!< Set PA11 function to USCI0_CLK */ +#define SET_USCI0_CLK_PB12() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~USCI0_CLK_PB12_Msk)) | USCI0_CLK_PB12 /*!< Set PB12 function to USCI0_CLK */ +#define SET_USCI0_CTL0_PC14() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~USCI0_CTL0_PC14_Msk)) | USCI0_CTL0_PC14 /*!< Set PC14 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PE6() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~USCI0_CTL0_PE6_Msk)) | USCI0_CTL0_PE6 /*!< Set PE6 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PB0() SYS->GPB_MFP0 = (SYS->GPB_MFP0 & (~USCI0_CTL0_PB0_Msk)) | USCI0_CTL0_PB0 /*!< Set PB0 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PD4() SYS->GPD_MFP1 = (SYS->GPD_MFP1 & (~USCI0_CTL0_PD4_Msk)) | USCI0_CTL0_PD4 /*!< Set PD4 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PC13() SYS->GPC_MFP3 = (SYS->GPC_MFP3 & (~USCI0_CTL0_PC13_Msk)) | USCI0_CTL0_PC13 /*!< Set PC13 function to USCI0_CTL0 */ +#define SET_USCI0_CTL1_PA8() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~USCI0_CTL1_PA8_Msk)) | USCI0_CTL1_PA8 /*!< Set PA8 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PD3() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~USCI0_CTL1_PD3_Msk)) | USCI0_CTL1_PD3 /*!< Set PD3 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PE5() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~USCI0_CTL1_PE5_Msk)) | USCI0_CTL1_PE5 /*!< Set PE5 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PB15() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~USCI0_CTL1_PB15_Msk)) | USCI0_CTL1_PB15 /*!< Set PB15 function to USCI0_CTL1 */ +#define SET_USCI0_DAT0_PA10() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~USCI0_DAT0_PA10_Msk)) | USCI0_DAT0_PA10 /*!< Set PA10 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PB13() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~USCI0_DAT0_PB13_Msk)) | USCI0_DAT0_PB13 /*!< Set PB13 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PE3() SYS->GPE_MFP0 = (SYS->GPE_MFP0 & (~USCI0_DAT0_PE3_Msk)) | USCI0_DAT0_PE3 /*!< Set PE3 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PD1() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~USCI0_DAT0_PD1_Msk)) | USCI0_DAT0_PD1 /*!< Set PD1 function to USCI0_DAT0 */ +#define SET_USCI0_DAT1_PD2() SYS->GPD_MFP0 = (SYS->GPD_MFP0 & (~USCI0_DAT1_PD2_Msk)) | USCI0_DAT1_PD2 /*!< Set PD2 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PE4() SYS->GPE_MFP1 = (SYS->GPE_MFP1 & (~USCI0_DAT1_PE4_Msk)) | USCI0_DAT1_PE4 /*!< Set PE4 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PA9() SYS->GPA_MFP2 = (SYS->GPA_MFP2 & (~USCI0_DAT1_PA9_Msk)) | USCI0_DAT1_PA9 /*!< Set PA9 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PB14() SYS->GPB_MFP3 = (SYS->GPB_MFP3 & (~USCI0_DAT1_PB14_Msk)) | USCI0_DAT1_PB14 /*!< Set PB14 function to USCI0_DAT1 */ +#define SET_X32_IN_PF5() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~X32_IN_PF5_Msk)) | X32_IN_PF5 /*!< Set PF5 function to X32_IN */ +#define SET_X32_OUT_PF4() SYS->GPF_MFP1 = (SYS->GPF_MFP1 & (~X32_OUT_PF4_Msk)) | X32_OUT_PF4 /*!< Set PF4 function to X32_OUT */ +#define SET_XT1_IN_PF3() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~XT1_IN_PF3_Msk)) | XT1_IN_PF3 /*!< Set PF3 function to XT1_IN */ +#define SET_XT1_OUT_PF2() SYS->GPF_MFP0 = (SYS->GPF_MFP0 & (~XT1_OUT_PF2_Msk)) | XT1_OUT_PF2 /*!< Set PF2 function to XT1_OUT */ + + +/** + * @brief Clear Brown-out detector interrupt flag + * @param None + * @return None + * @details This macro clear Brown-out detector interrupt flag. + * \hideinitializer + */ +#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk) + +/** + * @brief Set Brown-out detector function to normal mode + * @param None + * @return None + * @details This macro set Brown-out detector to normal mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + * \hideinitializer + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + * \hideinitializer + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Set Brown-out detector function low power mode + * @param None + * @return None + * @details This macro set Brown-out detector to low power mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + * \hideinitializer + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + * \hideinitializer + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + * \hideinitializer + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + * \hideinitializer + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + * \hideinitializer + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system (MCU) reset + * @param None + * @retval 0 Previous reset source is not from system (MCU) reset + * @retval >=1 Previous reset source is from system (MCU) reset + * @details This macro get previous reset source is from system (MCU) reset. + * \hideinitializer + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_MCURF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + * \hideinitializer + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_POR() (SYS->PORDISAN = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_POR() (SYS->PORDISAN = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_MCURF_Msk + * - \ref SYS_RSTSTS_HRESETRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * @return None + * @details This macro clear reset source flag. + * \hideinitializer + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + + if(--u32TimeOutCount == 0) break; + } + while(SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); +void SYS_SetVRef(uint32_t u32VRefCTL); + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_timer.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_timer.h new file mode 100644 index 0000000..801246a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_timer.h @@ -0,0 +1,537 @@ +/**************************************************************************//** + * @file timer.h + * @version V3.00 + * @brief Timer Controller(Timer) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_CAPTURE_SOURCE_FROM_PIN (0UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from TMx_EXT pin \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_FROM_INTERNAL (1UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from internal ACMPx signal or clock source \hideinitializer */ + +#define TIMER_CAPTURE_SOURCE_DIV_1 (0UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 1 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_2 (1UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 2 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_4 (2UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 4 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_8 (3UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 8 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_16 (4UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 16 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_32 (5UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 32 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_64 (6UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 64 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_128 (7UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 128 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_256 (8UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 256 \hideinitializer */ + +#define TIMER_INTER_CAPTURE_SOURCE_ACMP0 (0UL << TIMER_EXTCTL_ICAPSEL_Pos) /*!< Capture source from internal ACMP0 output signal \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_ACMP1 (1UL << TIMER_EXTCTL_ICAPSEL_Pos) /*!< Capture source from internal ACMP1 output signal \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_HXT (2UL << TIMER_EXTCTL_ICAPSEL_Pos) /*!< Capture source from HXT \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_LXT (3UL << TIMER_EXTCTL_ICAPSEL_Pos) /*!< Capture source from LXT \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_HIRC (4UL << TIMER_EXTCTL_ICAPSEL_Pos) /*!< Capture source from HIRC \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_LIRC (5UL << TIMER_EXTCTL_ICAPSEL_Pos) /*!< Capture source from LIRC \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_PWM (TIMER_TRGCTL_TRGPWM_Msk) /*!< Each timer event as BPWM and EPWM counter clock source \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_1 (0UL) /*!< Capture noise filter clock is PCLK divide by 1 \hideinitializer */ +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_2 (1UL) /*!< Capture noise filter clock is PCLK divide by 2 \hideinitializer */ +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_4 (2UL) /*!< Capture noise filter clock is PCLK divide by 4 \hideinitializer */ +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_8 (3UL) /*!< Capture noise filter clock is PCLK divide by 8 \hideinitializer */ +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_16 (4UL) /*!< Capture noise filter clock is PCLK divide by 16 \hideinitializer */ +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_32 (5UL) /*!< Capture noise filter clock is PCLK divide by 32 \hideinitializer */ +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_64 (6UL) /*!< Capture noise filter clock is PCLK divide by 64 \hideinitializer */ +#define TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_128 (7UL) /*!< Capture noise filter clock is PCLK divide by 128 \hideinitializer */ + +#define TIMER_TIMEOUT_ERR (-1L) /*!< TIMER operation abort due to timeout error \hideinitializer */ + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/** + * @brief Select Timer operating mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32OpMode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * + * @return None + * \hideinitializer + */ +#define TIMER_SET_OPMODE(timer, u32OpMode) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk) | (u32OpMode)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +int32_t TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); +void TIMER_EnableCaptureInputNoiseFilter(TIMER_T *timer, uint32_t u32FilterCount, uint32_t u32ClkSrcSel); +void TIMER_DisableCaptureInputNoiseFilter(TIMER_T *timer); +int32_t TIMER_ResetCounter(TIMER_T *timer); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_timer_pwm.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_timer_pwm.h new file mode 100644 index 0000000..9fb0eaf --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_timer_pwm.h @@ -0,0 +1,783 @@ +/**************************************************************************//** + * @file timer_pwm.h + * @version V3.00 + * @brief Timer PWM Controller(Timer PWM) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_PWM_H__ +#define __TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger EADC Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_EADC_AT_ZERO_POINT (0UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger EADC while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EADC_AT_PERIOD_POINT (1UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger EADC while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger EADC while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger EADC while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger EADC while counter down count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output function. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If the corresponding bit in ch parameter is 0, then output function will be disabled in this channel. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch)) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Set specified channel output is inversed or not. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * @note If ch parameter is 0, then output inverse function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid values are the combination of: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If ch parameter is 0, then output mask function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<CTL = (TRNG->CTL&~TRNG_CTL_CLKP_Msk)|((clkpsc & 0xf)<> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + * \hideinitializer + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified UART port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified UART port transmission is over nor not. + * \hideinitializer + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified UART port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified UART port transmission is over. + * \hideinitializer + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + * \hideinitializer + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + +/** + * @brief Rx Idle Status register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx is busy. + * @retval 1 Rx is Idle(Default) + * + * @details This macro get Rx Idle Status register value. + * \hideinitializer + */ +#define UART_RX_IDLE(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXIDLE_Msk )>> UART_FIFOSTS_RXIDLE_Pos) + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Single-wire Bit Error Detection Interrupt + * - \ref UART_INTEN_SWBEIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus Interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up Interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error Interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Single-wire Bit Error Detection Interrupt + * - \ref UART_INTEN_SWBEIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus Interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up Interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error Interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details This macro disable specified UART interrupt. + * \hideinitializer + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : PDMA Mode Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : PDMA Mode MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : PDMA Mode Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt Indicator + * - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag + * - \ref UART_INTSTS_HWBUFEIF_Msk : PDMA Mode Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : PDMA Mode Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : PDMA Mode MODEM Status Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : PDMA Mode Receive Line Status Flag + * - \ref UART_INTSTS_SWBEIF_Msk : Single-wire Bit Error Detect Interrupt Flag + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Interrupt Flag + * - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : MODEM Status Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Transmit Holding Register Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Receive Data Available Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart); +__STATIC_INLINE void UART_SET_RTS(UART_T* uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + * \hideinitializer + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + * \hideinitializer + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + +/** + * @brief Enable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * @details This macro enable specified UART PDMA function. + * \hideinitializer + */ +#define UART_PDMA_ENABLE(uart, u32FuncSel) ((uart)->INTEN |= (u32FuncSel)) +/** + * @brief Disable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * @details This macro disable specified UART PDMA function. + * \hideinitializer + */ +#define UART_PDMA_DISABLE(uart, u32FuncSel) ((uart)->INTEN &= ~(u32FuncSel)) + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UART_SelectSingleWireMode(UART_T *uart); + + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__UART_H__*/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usbd.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usbd.h new file mode 100644 index 0000000..0a736fd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usbd.h @@ -0,0 +1,830 @@ +/**************************************************************************//** + * @file usbd.h + * @version V3.00 + * @brief M460 series USBD driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ****************************************************************************/ +#ifndef __USBD_H__ +#define __USBD_H__ + +//#define SUPPORT_LPM // define to support LPM + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCT USBD Exported Struct + @{ +*/ + +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ + +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/*@}*/ /* end of group USBD_EXPORTED_STRUCT */ + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ + +#define USBD_BUF_BASE (USBD_BASE+0x800ul) /*!< USBD buffer base address \hideinitializer */ +#define USBD_MAX_EP 25ul /*!< Total EP number \hideinitializer */ + +#define EP0 0ul /*!< Endpoint 0 \hideinitializer */ +#define EP1 1ul /*!< Endpoint 1 \hideinitializer */ +#define EP2 2ul /*!< Endpoint 2 \hideinitializer */ +#define EP3 3ul /*!< Endpoint 3 \hideinitializer */ +#define EP4 4ul /*!< Endpoint 4 \hideinitializer */ +#define EP5 5ul /*!< Endpoint 5 \hideinitializer */ +#define EP6 6ul /*!< Endpoint 6 \hideinitializer */ +#define EP7 7ul /*!< Endpoint 7 \hideinitializer */ +#define EP8 8ul /*!< Endpoint 8 \hideinitializer */ +#define EP9 9ul /*!< Endpoint 9 \hideinitializer */ +#define EP10 10ul /*!< Endpoint 10 \hideinitializer */ +#define EP11 11ul /*!< Endpoint 11 \hideinitializer */ +#define EP12 12ul /*!< Endpoint 12 \hideinitializer */ +#define EP13 13ul /*!< Endpoint 13 \hideinitializer */ +#define EP14 14ul /*!< Endpoint 14 \hideinitializer */ +#define EP15 15ul /*!< Endpoint 15 \hideinitializer */ +#define EP16 16ul /*!< Endpoint 16 \hideinitializer */ +#define EP17 17ul /*!< Endpoint 17 \hideinitializer */ +#define EP18 18ul /*!< Endpoint 18 \hideinitializer */ +#define EP19 19ul /*!< Endpoint 19 \hideinitializer */ +#define EP20 20ul /*!< Endpoint 20 \hideinitializer */ +#define EP21 21ul /*!< Endpoint 21 \hideinitializer */ +#define EP22 22ul /*!< Endpoint 22 \hideinitializer */ +#define EP23 23ul /*!< Endpoint 23 \hideinitializer */ +#define EP24 24ul /*!< Endpoint 24 \hideinitializer */ + +/** @cond HIDDEN_SYMBOLS */ +/* USB Request Type */ +#define REQ_STANDARD 0x00ul +#define REQ_CLASS 0x20ul +#define REQ_VENDOR 0x40ul + +/* USB Standard Request */ +#define GET_STATUS 0x00ul +#define CLEAR_FEATURE 0x01ul +#define SET_FEATURE 0x03ul +#define SET_ADDRESS 0x05ul +#define GET_DESCRIPTOR 0x06ul +#define SET_DESCRIPTOR 0x07ul +#define GET_CONFIGURATION 0x08ul +#define SET_CONFIGURATION 0x09ul +#define GET_INTERFACE 0x0Aul +#define SET_INTERFACE 0x0Bul +#define SYNC_FRAME 0x0Cul + +/* USB Descriptor Type */ +#define DESC_DEVICE 0x01ul +#define DESC_CONFIG 0x02ul +#define DESC_STRING 0x03ul +#define DESC_INTERFACE 0x04ul +#define DESC_ENDPOINT 0x05ul +#define DESC_QUALIFIER 0x06ul +#define DESC_OTHERSPEED 0x07ul +#define DESC_IFPOWER 0x08ul +#define DESC_OTG 0x09ul +#define DESC_BOS 0x0Ful +#define DESC_CAPABILITY 0x10ul + +/* USB Device Capability Type */ +#define CAP_WIRELESS 0x01ul +#define CAP_USB20_EXT 0x02ul + +/* USB HID Descriptor Type */ +#define DESC_HID 0x21ul +#define DESC_HID_RPT 0x22ul + +/* USB Descriptor Length */ +#define LEN_DEVICE 18ul +#define LEN_QUALIFIER 10ul +#define LEN_CONFIG 9ul +#define LEN_INTERFACE 9ul +#define LEN_ENDPOINT 7ul +#define LEN_OTG 5ul +#define LEN_BOS 5ul +#define LEN_HID 9ul +#define LEN_CCID 0x36ul +#define LEN_BOSCAP 7ul + +/* USB Endpoint Type */ +#define EP_ISO 0x01 +#define EP_BULK 0x02 +#define EP_INT 0x03 + +#define EP_INPUT 0x80 +#define EP_OUTPUT 0x00 + +/* USB Feature Selector */ +#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01ul +#define FEATURE_ENDPOINT_HALT 0x00ul +/** @endcond HIDDEN_SYMBOLS */ + +/******************************************************************************/ +/* USB Specific Macros */ +/******************************************************************************/ + +#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable \hideinitializer */ +#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 \hideinitializer */ + +#define USBD_LPMACK USBD_ATTR_LPMACK_Msk /*!< LPM Enable \hideinitializer */ +#define USBD_BYTEM USBD_ATTR_BYTEM_Msk /*!< Access Size Mode Selection \hideinitializer */ +#define USBD_PWRDN USBD_ATTR_PWRDN_Msk /*!< PHY Turn-On \hideinitializer */ +#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable \hideinitializer */ +#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable \hideinitializer */ +#define USBD_RWAKEUP USBD_ATTR_RWAKEUP_Msk /*!< Remote Wake-Up \hideinitializer */ +#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable \hideinitializer */ + +#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt \hideinitializer */ +#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt \hideinitializer */ +#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt \hideinitializer */ +#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt \hideinitializer */ +#define USBD_INT_SOF USBD_INTEN_SOFIEN_Msk /*!< USB Start of Frame Interrupt \hideinitializer */ + +#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status \hideinitializer */ +#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status \hideinitializer */ +#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status \hideinitializer */ +#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event \hideinitializer */ +#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event \hideinitializer */ +#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event \hideinitializer */ +#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event \hideinitializer */ +#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event \hideinitializer */ +#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event \hideinitializer */ +#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event \hideinitializer */ +#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event \hideinitializer */ +#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event \hideinitializer */ +#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event \hideinitializer */ +#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event \hideinitializer */ +#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event \hideinitializer */ +#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event \hideinitializer */ + +#define USBD_EPINTSTS_EP0 USBD_EPINTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event \hideinitializer */ +#define USBD_EPINTSTS_EP1 USBD_EPINTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event \hideinitializer */ +#define USBD_EPINTSTS_EP2 USBD_EPINTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event \hideinitializer */ +#define USBD_EPINTSTS_EP3 USBD_EPINTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event \hideinitializer */ +#define USBD_EPINTSTS_EP4 USBD_EPINTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event \hideinitializer */ +#define USBD_EPINTSTS_EP5 USBD_EPINTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event \hideinitializer */ +#define USBD_EPINTSTS_EP6 USBD_EPINTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event \hideinitializer */ +#define USBD_EPINTSTS_EP7 USBD_EPINTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event \hideinitializer */ +#define USBD_EPINTSTS_EP8 USBD_EPINTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event \hideinitializer */ +#define USBD_EPINTSTS_EP9 USBD_EPINTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event \hideinitializer */ +#define USBD_EPINTSTS_EP10 USBD_EPINTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event \hideinitializer */ +#define USBD_EPINTSTS_EP11 USBD_EPINTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event \hideinitializer */ +#define USBD_EPINTSTS_EP12 USBD_EPINTSTS_EPEVT12_Msk /*!< USB Endpoint 12 Event \hideinitializer */ +#define USBD_EPINTSTS_EP13 USBD_EPINTSTS_EPEVT13_Msk /*!< USB Endpoint 13 Event \hideinitializer */ +#define USBD_EPINTSTS_EP14 USBD_EPINTSTS_EPEVT14_Msk /*!< USB Endpoint 14 Event \hideinitializer */ +#define USBD_EPINTSTS_EP15 USBD_EPINTSTS_EPEVT15_Msk /*!< USB Endpoint 15 Event \hideinitializer */ +#define USBD_EPINTSTS_EP16 USBD_EPINTSTS_EPEVT16_Msk /*!< USB Endpoint 16 Event \hideinitializer */ +#define USBD_EPINTSTS_EP17 USBD_EPINTSTS_EPEVT17_Msk /*!< USB Endpoint 17 Event \hideinitializer */ +#define USBD_EPINTSTS_EP18 USBD_EPINTSTS_EPEVT18_Msk /*!< USB Endpoint 18 Event \hideinitializer */ +#define USBD_EPINTSTS_EP19 USBD_EPINTSTS_EPEVT19_Msk /*!< USB Endpoint 19 Event \hideinitializer */ +#define USBD_EPINTSTS_EP20 USBD_EPINTSTS_EPEVT20_Msk /*!< USB Endpoint 20 Event \hideinitializer */ +#define USBD_EPINTSTS_EP21 USBD_EPINTSTS_EPEVT21_Msk /*!< USB Endpoint 21 Event \hideinitializer */ +#define USBD_EPINTSTS_EP22 USBD_EPINTSTS_EPEVT22_Msk /*!< USB Endpoint 22 Event \hideinitializer */ +#define USBD_EPINTSTS_EP23 USBD_EPINTSTS_EPEVT23_Msk /*!< USB Endpoint 23 Event \hideinitializer */ +#define USBD_EPINTSTS_EP24 USBD_EPINTSTS_EPEVT24_Msk /*!< USB Endpoint 24 Event \hideinitializer */ + +#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset \hideinitializer */ +#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend \hideinitializer */ +#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume \hideinitializer */ +#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout \hideinitializer */ +#define USBD_STATE_L1SUSPEND USBD_ATTR_L1SUSPEND_Msk /*!< USB Bus L1SUSPEND \hideinitializer */ +#define USBD_STATE_L1RESUME USBD_ATTR_L1RESUME_Msk /*!< USB Bus L1RESUME \hideinitializer */ + +#define USBD_CFG_DB_EN USBD_CFG_DBEN_Msk /*!< Double Buffer Enable \hideinitializer */ +#define USBD_CFG_DBTGACTIVE USBD_CFG_DBTGACTIVE_Msk /*!< Double Buffer Toggle Active \hideinitializer */ + +#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall \hideinitializer */ +#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall \hideinitializer */ + +#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos) /*!< Endpoint Disable \hideinitializer */ +#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos) /*!< Out Endpoint \hideinitializer */ +#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos) /*!< In Endpoint \hideinitializer */ +#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous \hideinitializer */ + +/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/** + * @brief Compare two input numbers and return maximum one. + * + * @param[in] a First number to be compared. + * @param[in] b Second number to be compared. + * + * @return Maximum value between a and b. + * + * @details If a > b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + * \hideinitializer + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * \hideinitializer + */ +#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0)) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * \hideinitializer + */ +#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * \hideinitializer + */ +#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN)) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * \hideinitializer + */ +#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * \hideinitializer + */ +#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0)) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * \hideinitializer + */ +#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0)) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * \hideinitializer + */ +#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * \hideinitializer + */ +#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_SOF, USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * \hideinitializer + */ +#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr)) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * \hideinitializer + */ +#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS)) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INT_SOF, USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * \hideinitializer + */ +#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag)) + +/** + * @brief Get endpoint interrupt status + * + * @param None + * + * @return The value of USB_EPINTSTS register + * + * @details Return all endpoint interrupt flags of USB_EPINTSTS register. + * \hideinitializer + */ +#define USBD_GET_EP_INT_FLAG() ((uint32_t)(USBD->EPINTSTS)) + +/** + * @brief Clear USB endpoint interrupt flag + * + * @param[in] flag The combination of the specified endpoint interrupt flags. + * Each bit corresponds to a endpoint interrupt source. + * This parameter decides which endpoint interrupt flags will be cleared. + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * \hideinitializer + */ +#define USBD_CLR_EP_INT_FLAG(flag) (USBD->EPINTSTS = (flag)) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * \hideinitializer + */ +#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS)) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[13:12] and USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * Bit 12 indicates USB bus LPM L1 suspend status. + * Bit 13 indicates USB bus LPM L1 resume status. + * + * @details Return USB_ATTR[13:12] and USB_ATTR[3:0] for USB bus events. + * \hideinitializer + */ +#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0x300f)) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * \hideinitializer + */ +#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * \hideinitializer + */ +#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * \hideinitializer + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M460 Series supports 8 endpoint ID. This parameter could be 0 ~ 24. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * \hideinitializer + */ +#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * \hideinitializer + */ +#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * \hideinitializer + */ +#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0ul].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + * \hideinitializer + */ +#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk) + +/** + * @brief Set USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Set DBEN bit of USB_CFGx register to enable the double buffer mode of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_DB_MODE(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBEN_Msk) + +/** + * @brief Set USB single buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Clear DBEN bit of USB_CFGx register to enable the single buffer mode of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_SB_MODE(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBEN_Msk)) + +/** + * @brief Get the buffer mode of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @retval 0 USB is single buffer mode. + * @retval 1 USB is double buffer mode. + * + * @details This macro will return the buffer mode of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_IS_DB_MODE(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_DBEN_Msk) + +/** + * @brief Set to active in USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Set DBTGACTIVE bit of USB_CFGx register for toggle active in the double buffer mode of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_DB_ACTIVE(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBTGACTIVE_Msk) + +/** + * @brief Set to inactive in USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M460 Series supports 25 hardware endpoint ID. This parameter could be 0 ~ 24. + * + * @return None + * + * @details Clear DBTGACTIVE bit of USB_CFGx register for toggle inactive in the double buffer mode of the specified endpoint ID. + * \hideinitializer + */ +#define USBD_SET_DB_INACTIVE(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBTGACTIVE_Msk)) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) +{ + uint32_t volatile i=0ul; + + while(size--) + { + dest[i] = src[i]; + i++; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + * + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + +extern uint8_t g_usbd_SetupPacket[8]; +extern volatile uint8_t g_usbd_RemoteWakeupEn; + + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_GetDescriptor(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__USBD_H__*/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_i2c.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_i2c.h new file mode 100644 index 0000000..da5d251 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_i2c.h @@ -0,0 +1,334 @@ +/**************************************************************************//** + * @file USCI_I2C.h + * @version V3.0 + * @brief M460 series USCI I2C(UI2C) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USCI_I2C_H__ +#define __USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */ +#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */ +#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */ +#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */ + +#define UI2C_TIMEOUT SystemCoreClock /*!< 1 second time-out \hideinitializer */ +#define UI2C_TIMEOUT_ERR (-1L) /*!< UI2C operation abort due to timeout error \hideinitializer */ + +/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + +extern int32_t g_UI2C_i32ErrCode; + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK. + * \hideinitializer + */ +#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + * \hideinitializer + */ +#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + * \hideinitializer + */ +#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + * \hideinitializer + */ +#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + * \hideinitializer + */ +#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + * \hideinitializer + */ +#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + * \hideinitializer + */ +#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + * \hideinitializer + */ +#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function. + * \hideinitializer + */ +#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *ui2c); +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c); +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c); +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *ui2c); +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *ui2c); +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *ui2c); +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen); +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen); + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_spi.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_spi.h new file mode 100644 index 0000000..7bb9981 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_spi.h @@ -0,0 +1,426 @@ +/**************************************************************************//** + * @file usci_spi.h + * @version V3.00 + * @brief M460 series USCI_SPI driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_SPI_H__ +#define __USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */ +#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define USPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define USPI_SS_ACTIVE_HIGH (0x0ul) /*!< SS active high \hideinitializer */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001ul) /*!< Slave Slave Inactive interrupt mask \hideinitializer */ +#define USPI_SSACT_INT_MASK (0x002ul) /*!< Slave Slave Active interrupt mask \hideinitializer */ +#define USPI_SLVTO_INT_MASK (0x004ul) /*!< Slave Mode Time-out interrupt mask \hideinitializer */ +#define USPI_SLVBE_INT_MASK (0x008ul) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */ +#define USPI_TXUDR_INT_MASK (0x010ul) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */ +#define USPI_RXOV_INT_MASK (0x020ul) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */ +#define USPI_TXST_INT_MASK (0x040ul) /*!< Transmit Start interrupt mask \hideinitializer */ +#define USPI_TXEND_INT_MASK (0x080ul) /*!< Transmit End interrupt mask \hideinitializer */ +#define USPI_RXST_INT_MASK (0x100ul) /*!< Receive Start interrupt mask \hideinitializer */ +#define USPI_RXEND_INT_MASK (0x200ul) /*!< Receive End interrupt mask \hideinitializer */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */ +#define USPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */ +#define USPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */ +#define USPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */ +#define USPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */ +#define USPI_SSLINE_STS_MASK (0x20ul) /*!< USCI_SPI_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(uspi) ( (uspi)->RXDAT ) + +/** + * @brief Write datum to TX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(uspi) \ + do{ \ + (uspi)->LINECTL &= ~USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(uspi) \ + do{ \ + (uspi)->LINECTL |= USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(uspi, u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0 ) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk ) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS ) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag) ) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS ) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag) ) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN |= (u32IntSel) ) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN &= ~ (u32IntSel) ) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL |= (u32IntSel) ) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL &= ~ (u32IntSel) ) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN |= (u32IntSel) ) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN &= ~ (u32IntSel) ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_TX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk) ) + +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *uspi); +void USPI_ClearRxBuf(USPI_T *uspi); +void USPI_ClearTxBuf(USPI_T *uspi); +void USPI_DisableAutoSS(USPI_T *uspi); +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *uspi); +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *uspi); +void USPI_DisableWakeup(USPI_T *uspi); + + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_SPI_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_uart.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_uart.h new file mode 100644 index 0000000..dfafec5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_usci_uart.h @@ -0,0 +1,519 @@ +/**************************************************************************//** + * @file usci_uart.h + * @version V3.00 + * @brief M460 series USCI UART (UUART) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_UART_H__ +#define __USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */ +#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */ +#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */ +#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */ +#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */ +#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */ + +#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */ +#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */ +#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */ +#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */ +#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */ +#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */ +#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */ +#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */ + + +/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UUART_READ(uuart) ((uuart)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + * \hideinitializer + */ +#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + * \hideinitializer + */ +#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + * \hideinitializer + */ +#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + * \hideinitializer + */ +#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + * \hideinitializer + */ +#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + * \hideinitializer + */ +#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + * \hideinitializer + */ +#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk) + +/** + * @brief Trigger RX PDMA function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Set RXPDMAEN bit of UUART_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define UUART_TRIGGER_RX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_RXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Set TXPDMAEN bit of UUART_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define UUART_TRIGGER_TX_PDMA(uuart) ((uuart)->PDMACTL |= UUART_PDMACTL_TXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Clear RXPDMAEN bit of UUART_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define UUART_DISABLE_RX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Clear TXPDMAEN bit of UUART_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define UUART_DISABLE_TX_PDMA(uuart) ( (uuart)->PDMACTL &= ~UUART_PDMACTL_TXPDMAEN_Msk ) + + +/** + * @brief Enable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * @details This macro enable specified USCI_UART PDMA function. + * \hideinitializer + */ +#define UUART_PDMA_ENABLE(uuart, u32FuncSel) ((uuart)->PDMACTL |= (u32FuncSel)) + +/** + * @brief Disable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * \hideinitializer + */ +#define UUART_PDMA_DISABLE(uuart, u32FuncSel) ((uuart)->PDMACTL &= ~(u32FuncSel)) + + + + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask); +void UUART_Close(UUART_T* uuart); +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask); +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate); +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T* uuart); +void UUART_EnableFlowCtrl(UUART_T* uuart); +void UUART_DisableFlowCtrl(UUART_T* uuart); + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_UART_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_wdt.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_wdt.h new file mode 100644 index 0000000..73d1b14 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_wdt.h @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file wdt.h + * @version V3.00 + * @brief Watchdog Timer(WDT) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_H__ +#define __WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW20 (8UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^20 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +#define WDT_TIMEOUT SystemCoreClock /*!< 1 second time-out \hideinitializer */ +#define WDT_TIMEOUT_ERR (-1L) /*!< WDT operation abort due to timeout error \hideinitializer */ + +/**@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + +extern int32_t g_WDT_i32ErrCode; + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 20-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 20-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + * + * @note This function sets g_WDT_i32ErrCode to WDT_TIMEOUT_ERR if waiting WDT time-out. + */ +__STATIC_INLINE void WDT_Close(void) +{ + uint32_t u32TimeOutCount = WDT_TIMEOUT; + + WDT->CTL = 0UL; + while(WDT->CTL & WDT_CTL_SYNC_Msk) /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */ + { + if(--u32TimeOutCount == 0) + { + g_WDT_i32ErrCode = WDT_TIMEOUT_ERR; /* Time-out error */ + break; + } + } +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WDT_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_wwdt.h b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_wwdt.h new file mode 100644 index 0000000..62dc74c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/inc/m460_wwdt.h @@ -0,0 +1,150 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V3.00 + * @brief Window Watchdog Timer(WWDT) driver header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/**@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/**@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_acmp.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_acmp.c new file mode 100644 index 0000000..d5091ff --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_acmp.c @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file acmp.c + * @version V1.00 + * @brief M480 series Analog Comparator(ACMP) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel) +{ + acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum) +{ + acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); +} + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_bmc.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_bmc.c new file mode 100644 index 0000000..0310b32 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_bmc.c @@ -0,0 +1,352 @@ +/**************************************************************************//** + * @file bmc.c + * @version V3.00 + * @brief M460 series BMC driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BMC_Driver BMC Driver + @{ +*/ + + +/** @addtogroup BMC_EXPORTED_FUNCTIONS BMC Exported Functions + @{ +*/ + +/** + * @brief Set the BMC bit clock + * @param[in] u32BitClock The expected frequency of BMC bit clock in Hz + * @return Actual frequency of BMC bit clock + * @details The actual clock rate may be different from the target BMC bit clock rate. + * For example, if the system clock rate is 200 MHz and the target BMC bit clock rate is 3 MHz, the actual BMC bit clock + * rate will be 2 MHz. + * \hideinitializer + */ +uint32_t BMC_SetBitClock(uint32_t u32BitClock) +{ + uint32_t u32HCLKFreq, u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + u32Div = ((u32HCLKFreq * 10UL) / u32BitClock + 5UL) / 10UL; /* Round to the nearest integer */ + + BMC->CTL = (BMC->CTL & (~BMC_CTL_BTDIV_Msk)) | (u32Div << BMC_CTL_BTDIV_Pos); + + /* Return BMC bit clock rate */ + u32RetValue = u32HCLKFreq / u32Div; + + return u32RetValue; +} + +/** + * @brief Get the actual frequency of BMC bit clock + * @return Actual BMC bit frequency in Hz + * @details This API will calculate the actual BMC bit clock rate according to the HBTDIV setting. + * \hideinitializer + */ +uint32_t BMC_GetBitClock(void) +{ + uint32_t u32HCLKFreq, u32Div; + + /* Get BTDIV setting */ + u32Div = (BMC->CTL & BMC_CTL_BTDIV_Msk) >> BMC_CTL_BTDIV_Pos; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + /* Return BMC bit clock rate */ + return (u32HCLKFreq / u32Div); +} + +/** + * @brief Set the dummy delay time period of each group + * @param[in] u32ChGroup BMC channel group selection, valid values are: + * - \ref BMC_GROUP_0 + * - \ref BMC_GROUP_1 + * - \ref BMC_GROUP_2 + * - \ref BMC_GROUP_3 + * - \ref BMC_GROUP_4 + * - \ref BMC_GROUP_5 + * - \ref BMC_GROUP_6 + * - \ref BMC_GROUP_7 + * @param[in] u32DumDelay The expected BMC dummy delay period in microsecond + * @return Actual dummy delay time period in microsecond + * @details This API is used to set each group dummy delay time period. + * \hideinitializer + */ +uint32_t BMC_SetDummyDelayPeriod(uint32_t u32ChGroup, uint32_t u32DumDelay) +{ + uint32_t i, u32BitNum; + + u32BitNum = ((BMC_GetBitClock() * u32DumDelay) / 1000000UL) / 8UL; + + for(i = 0UL; i < (uint32_t)BMC_CHANNEL_NUM; i += 4UL) + { + if((u32ChGroup == i) && (u32ChGroup <= BMC_GROUP_3)) + { + outp8((uint32_t)&(BMC->DNUM0) + (i >> 2UL), u32BitNum); + break; + } + else if((u32ChGroup == i) && (u32ChGroup > BMC_GROUP_3)) + { + outp8((uint32_t)&(BMC->DNUM1) + ((i >> 2UL) - 4UL), u32BitNum); + break; + } + } + + /* Return BMC dummy delay time period */ + return (8UL * 1000000UL / BMC_GetBitClock() * u32BitNum); +} + +/** + * @brief Enable interrupt function + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref BMC_FTXD_INT_MASK + * - \ref BMC_TXUND_INT_MASK + * @return None + * @details This API is used to enable BMC related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +void BMC_EnableInt(uint32_t u32Mask) +{ + /* Enable frame transmit done interrupt flag */ + if((u32Mask & BMC_FTXD_INT_MASK) == BMC_FTXD_INT_MASK) + { + BMC->INTEN |= BMC_INTEN_FTXDIEN_Msk; + } + + /* Enable transmit data under run interrupt flag */ + if((u32Mask & BMC_TXUND_INT_MASK) == BMC_TXUND_INT_MASK) + { + BMC->INTEN |= BMC_INTEN_TXUNDIEN_Msk; + } +} + +/** + * @brief Disable interrupt function + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref BMC_FTXD_INT_MASK + * - \ref BMC_TXUND_INT_MASK + * @return None + * @details This API is used to disable BMC related interrupts specified by u32Mask parameter. + * \hideinitializer + */ +void BMC_DisableInt(uint32_t u32Mask) +{ + /* Disable frame transmit done interrupt flag */ + if((u32Mask & BMC_FTXD_INT_MASK) == BMC_FTXD_INT_MASK) + { + BMC->INTEN &= ~BMC_INTEN_FTXDIEN_Msk; + } + + /* Disable transmit data under run interrupt flag */ + if((u32Mask & BMC_TXUND_INT_MASK) == BMC_TXUND_INT_MASK) + { + BMC->INTEN &= ~BMC_INTEN_TXUNDIEN_Msk; + } +} + +/** + * @brief Get interrupt flag + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref BMC_FTXD_INT_MASK + * - \ref BMC_TXUND_INT_MASK + * @return Interrupt flags of selected sources + * @details This API is used to get BMC related interrupt flags specified by u32Mask parameter. + * \hideinitializer + */ +uint32_t BMC_GetIntFlag(uint32_t u32Mask) +{ + uint32_t u32IntStatus; + uint32_t u32IntFlag = 0UL; + + u32IntStatus = BMC->INTSTS; + + /* Check frame transmit done interrupt flag */ + if((u32Mask & BMC_FTXD_INT_MASK) && (u32IntStatus & BMC_INTSTS_FTXDIF_Msk)) + { + u32IntFlag |= BMC_FTXD_INT_MASK; + } + + /* Check transmit data under run interrupt flag */ + if((u32Mask & BMC_TXUND_INT_MASK) && (u32IntStatus & BMC_INTSTS_TXUNDIF_Msk)) + { + u32IntFlag |= BMC_TXUND_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag + * @param[in] u32Mask The related interrupt source. + * This parameter decides which interrupt flag will be cleared. Possible option is: + * - \ref BMC_FTXD_INT_MASK + * @return None + * @details This API is used to clear BMC related interrupt flag specified by u32Mask parameter. + * \hideinitializer + */ +void BMC_ClearIntFlag(uint32_t u32Mask) +{ + if(u32Mask & BMC_FTXD_INT_MASK) + { + BMC->INTSTS = BMC_INTSTS_FTXDIF_Msk; /* Clear frame transmit done interrupt flag */ + } +} + +/** + * @brief Get BMC status + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a related source. + * This parameter decides which flags will be read. It is combination of: + * - \ref BMC_G0TXUND_MASK + * - \ref BMC_G1TXUND_MASK + * - \ref BMC_G2TXUND_MASK + * - \ref BMC_G3TXUND_MASK + * - \ref BMC_G4TXUND_MASK + * - \ref BMC_G5TXUND_MASK + * - \ref BMC_G6TXUND_MASK + * - \ref BMC_G7TXUND_MASK + * @return Flags of selected sources + * @details This API is used to get BMC related status specified by u32Mask parameter. + * \hideinitializer + */ +uint32_t BMC_GetStatus(uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Flag = 0UL; + + u32TmpStatus = BMC->INTSTS; + + /* Check group 0 transmit data under run status */ + if((u32Mask & BMC_G0TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G0TXUND_Msk)) + { + u32Flag |= BMC_G0TXUND_MASK; + } + + /* Check group 1 transmit data under run status */ + if((u32Mask & BMC_G1TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G1TXUND_Msk)) + { + u32Flag |= BMC_G1TXUND_MASK; + } + + /* Check group 2 transmit data under run status */ + if((u32Mask & BMC_G2TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G2TXUND_Msk)) + { + u32Flag |= BMC_G2TXUND_MASK; + } + + /* Check group 3 transmit data under run status */ + if((u32Mask & BMC_G3TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G3TXUND_Msk)) + { + u32Flag |= BMC_G3TXUND_MASK; + } + + /* Check group 4 transmit data under run status */ + if((u32Mask & BMC_G4TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G4TXUND_Msk)) + { + u32Flag |= BMC_G4TXUND_MASK; + } + + /* Check group 5 transmit data under run status */ + if((u32Mask & BMC_G5TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G5TXUND_Msk)) + { + u32Flag |= BMC_G5TXUND_MASK; + } + + /* Check group 6 transmit data under run status */ + if((u32Mask & BMC_G6TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G6TXUND_Msk)) + { + u32Flag |= BMC_G6TXUND_MASK; + } + + /* Check group 7 transmit data under run status */ + if((u32Mask & BMC_G7TXUND_MASK) && (u32TmpStatus & BMC_INTSTS_G7TXUND_Msk)) + { + u32Flag |= BMC_G7TXUND_MASK; + } + + return u32Flag; +} + +/** + * @brief Clear BMC status + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a related source. + * This parameter decides which flags will be cleared. It is combination of: + * - \ref BMC_G0TXUND_MASK + * - \ref BMC_G1TXUND_MASK + * - \ref BMC_G2TXUND_MASK + * - \ref BMC_G3TXUND_MASK + * - \ref BMC_G4TXUND_MASK + * - \ref BMC_G5TXUND_MASK + * - \ref BMC_G6TXUND_MASK + * - \ref BMC_G7TXUND_MASK + * @return None + * @details This API is used to clear BMC related status specified by u32Mask parameter. + * \hideinitializer + */ +void BMC_ClearStatus(uint32_t u32Mask) +{ + if(u32Mask & BMC_G0TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G0TXUND_Msk; /* Check group 0 transmit data under run status */ + } + + if(u32Mask & BMC_G1TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G1TXUND_Msk; /* Check group 1 transmit data under run status */ + } + + if(u32Mask & BMC_G2TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G2TXUND_Msk; /* Check group 2 transmit data under run status */ + } + + if(u32Mask & BMC_G3TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G3TXUND_Msk; /* Check group 3 transmit data under run status */ + } + + if(u32Mask & BMC_G4TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G4TXUND_Msk; /* Check group 4 transmit data under run status */ + } + + if(u32Mask & BMC_G5TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G5TXUND_Msk; /* Check group 5 transmit data under run status */ + } + + if(u32Mask & BMC_G6TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G6TXUND_Msk; /* Check group 6 transmit data under run status */ + } + + if(u32Mask & BMC_G7TXUND_MASK) + { + BMC->INTSTS = BMC_INTSTS_G7TXUND_Msk; /* Check group 7 transmit data under run status */ + } +} + + +/*@}*/ /* end of group BMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_bpwm.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_bpwm.c new file mode 100644 index 0000000..403dbc8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_bpwm.c @@ -0,0 +1,758 @@ +/**************************************************************************//** + * @file bpwm.c + * @version V1.00 + * @brief BPWM driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions + @{ +*/ + +/** + * @brief Configure BPWM capture and get the nearest unit time. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure BPWM capture and get the nearest unit time. + */ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec = 0U; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + (void)u32ChannelNum; + (void)u32CaptureEdge; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32PWMClockSrc /= 1000UL; + for(u32Prescale = 1U; u32Prescale <= 0x1000UL; u32Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if (u32Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if (!(1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + } + + /* convert to real register value */ + /* all channels share a prescaler */ + u32Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(bpwm == BPWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + i = (u32PWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i <= (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + /* all channels share a prescaler */ + u32Prescale -= 1U; + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + /* set BPWM to up counter type(edge aligned) */ + (bpwm)->CTL1 = BPWM_UP_COUNTER; + + u32CNR -= 1U; + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL); + + + (bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \ + (BPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << BPWM_WGCTL0_ZPCTL0_Pos)); + (bpwm)->WGCTL1 = ((bpwm)->WGCTL1 & ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \ + (BPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << BPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to start BPWM module. + * @note All channels share one counter. + */ +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Stop BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM module. + * @note All channels share one period. + */ +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->PERIOD = 0UL; +} + +/** + * @brief Stop BPWM generation immediately by clear channel enable bit + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM generation immediately by clear channel enable bit. + * @note All channels share one counter. + */ +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC + */ +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3)); + (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3)); + (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable selected channel to trigger ADC + */ +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3)); + } + else + { + (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag + */ +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (void)u32Condition; + (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel + */ +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s) + */ +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN |= u32ChannelMask; + (bpwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s) + */ +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN &= ~u32ChannelMask; + (bpwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables BPWM output generation of selected channel(s) + */ +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables BPWM output generation of selected channel(s) + */ +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + uint32_t u32CapIf = 0UL; + + u32CapIf = ((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1); + u32CapIf |= (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL); + return u32CapIf; +} + +/** + * @brief Enable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel + */ +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= (uint32_t)(~((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum)); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel + */ +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel + */ +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (void)u32ChannelNum; + (void)u32IntPeriodType; + (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk; +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk; +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Set BPWM clock source + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32ClkSrcSel BPWM external clock source. + * - \ref BPWM_CLKSRC_BPWM_CLK + * - \ref BPWM_CLKSRC_TIMER0 + * - \ref BPWM_CLKSRC_TIMER1 + * - \ref BPWM_CLKSRC_TIMER2 + * - \ref BPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set BPWM clock source. + * @note All channels share channel 0's setting. + */ +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (void)u32ChannelNum; + (bpwm)->CLKSRC = (u32ClkSrcSel); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk; +} + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_canfd.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_canfd.c new file mode 100644 index 0000000..5e78726 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_canfd.c @@ -0,0 +1,1840 @@ +/**************************************************************************** + * @file canfd.c + * @version V1.00 + * @brief CAN FD driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" +#include "string.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Minimum number of time quanta in a bit. */ +#define MIN_TIME_QUANTA 9ul +/* Maximum number of time quanta in a bit. */ +#define MAX_TIME_QUANTA 20ul +/* Number of receive FIFOs (1 - 2) */ +#define CANFD_NUM_RX_FIFOS 2ul + +/*CANFD max nominal bit rate*/ +#define MAX_NOMINAL_BAUDRATE (1000000UL) + +/* Tx Event FIFO Element ESI(Error State Indicator) */ +#define TX_FIFO_E0_EVENT_ESI_Pos (31) +#define TX_FIFO_E0_EVENT_ESI_Msk (0x1ul << TX_FIFO_E0_EVENT_ESI_Pos) + +/* Tx Event FIFO Element XTD(Extended Identifier) */ +#define TX_FIFO_E0_EVENT_XTD_Pos (30) +#define TX_FIFO_E0_EVENT_XTD_Msk (0x1ul << TX_FIFO_E0_EVENT_XTD_Pos) + +/* Tx Event FIFO Element RTR(Remote Transmission Request) */ +#define TX_FIFO_E0_EVENT_RTR_Pos (29) +#define TX_FIFO_E0_EVENT_RTR_Msk (0x1ul << TX_FIFO_E0_EVENT_RTR_Pos) + +/* Tx Event FIFO Element ID(Identifier) */ +#define TX_FIFO_E0_EVENT_ID_Pos (0) +#define TX_FIFO_E0_EVENT_ID_Msk (0x1FFFFFFFul << TX_FIFO_E0_EVENT_ID_Pos) + +/* Tx Event FIFO Element MM(Message Marker) */ +#define TX_FIFO_E1_EVENT_MM_Pos (24) +#define TX_FIFO_E1_EVENT_MM_Msk (0xFFul << TX_FIFO_E1_EVENT_MM_Pos) + +/* Tx Event FIFO Element ET(Event Type) */ +#define TX_FIFO_E1_EVENT_ET_Pos (22) +#define TX_FIFO_E1_EVENT_ET_Msk (0x3ul << TX_FIFO_E1_EVENT_ET_Pos) + +/* Tx Event FIFO Element FDF(FD Format) */ +#define TX_FIFO_E1_EVENT_FDF_Pos (21) +#define TX_FIFO_E1_EVENT_FDF_Msk (0x1ul << TX_FIFO_E1_EVENT_FDF_Pos) + +/* Tx Event FIFO Element BRS(Bit Rate Switch) */ +#define TX_FIFO_E1_EVENT_BRS_Pos (20) +#define TX_FIFO_E1_EVENT_BRS_Msk (0x1ul << TX_FIFO_E1_EVENT_BRS_Pos) + +/* Tx Event FIFO Element DLC(Data Length Code) */ +#define TX_FIFO_E1_EVENT_DLC_Pos (16) +#define TX_FIFO_E1_EVENT_DLC_Msk (0xFul << TX_FIFO_E1_EVENT_DLC_Pos) + +/* Tx Event FIFO Element TXTS(Tx Timestamp) */ +#define TX_FIFO_E1A_EVENT_TXTS_Pos (0) +#define TX_FIFO_E1A_EVENT_TXTS_Msk (0xFFFFul << TX_FIFO_E1A_EVENT_TXTS_Pos) + +/* Tx Event FIFO Element MM(Message Marker) */ +#define TX_FIFO_E1B_EVENT_MM_Pos (8) +#define TX_FIFO_E1B_EVENT_MM_Msk (0xFFul << TX_FIFO_E1B_EVENT_MM_Pos) + +/* Tx Event FIFO Element TSC(Timestamp Captured) */ +#define TX_FIFO_E1B_EVENT_TSC_Pos (4) +#define TX_FIFO_E1B_EVENT_TSC_Msk (0x1ul << TX_FIFO_E1B_EVENT_TSC_Pos) + +/* Tx Event FIFO Element TSC(Timestamp Captured) */ +#define TX_FIFO_E1B_EVENT_TXTS_Pos (0) +#define TX_FIFO_E1B_EVENT_TXTS_Msk (0xFul << TX_FIFO_E1B_EVENT_TSC_Pos) + +/* Rx Buffer and FIFO Element ESI2(Error State Indicator) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Pos (31) +#define RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Msk (0x1ul << RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Pos) + +/* Rx Buffer and FIFO Element XTD(Extended Identifier) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Pos (30) +#define RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Msk (0x1ul << RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Pos) + +/* Rx Buffer and FIFO Element RTR(Remote Transmission Request) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Pos (29) +#define RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Msk (0x1ul << RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Pos) + +/* Rx Buffer and FIFO Element ID(Identifier) */ +#define RX_BUFFER_AND_FIFO_R0_ELEM_ID_Pos (0) +#define RX_BUFFER_AND_FIFO_R0_ELEM_ID_Msk (0x1FFFFFFFul << RX_BUFFER_AND_FIFO_R0_ELEM_ID_Pos) + +/* Rx Buffer and FIFO Element ANMF(Accepted Non-matching Frame) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_ANMF_Pos (31) +#define RX_BUFFER_AND_FIFO_R1_ELEM_ANMF_Msk (0x1ul << RX_BUFFER_AND_FIFO_R1_ELEM_ANMF_Pos) + +/* Rx Buffer and FIFO Element FIDX(Filter Index) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_FIDX_Pos (24) +#define RX_BUFFER_AND_FIFO_R1_ELEM_FIDX_Msk (0x7Ful << RX_BUFFER_AND_FIFO_R1_ELEM_FIDX_Pos) + +/* Rx Buffer and FIFO Element FDF(FD Format) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Pos (21) +#define RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Msk (0x1ul << RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Pos) + +/* Rx Buffer and FIFO Element BRS(Bit Rate Swit) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Pos (20) +#define RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Msk (0x1ul << RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Pos) + +/* Rx Buffer and FIFO Element DLC(Bit Rate Swit) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Pos (16) +#define RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Msk (0xFul << RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Pos) + +/* Rx Buffer and FIFO Element RXTS(Rx Timestamp) */ +#define RX_BUFFER_AND_FIFO_R1_ELEM_RXTS_Pos (0) +#define RX_BUFFER_AND_FIFO_R1_ELEM_RXTS_Msk (0xFFFFul << RX_BUFFER_AND_FIFO_R1_ELEM_RXTS_Pos) + +/* Tx Buffer Element ESI(Error State Indicator) */ +#define TX_BUFFER_T0_ELEM_ESI_Pos (31) +#define TX_BUFFER_T0_ELEM_ESI_Msk (0x1ul << TX_BUFFER_T0_ELEM_ESI_Pos) + +/* Tx Buffer Element XTD(Extended Identifier) */ +#define TX_BUFFER_T0_ELEM_XTD_Pos (30) +#define TX_BUFFER_T0_ELEM_XTD_Msk (0x1ul << TX_BUFFER_T0_ELEM_XTD_Pos) + +/* Tx Buffer RTR(Remote Transmission Request) */ +#define TX_BUFFER_T0_ELEM_RTR_Pos (29) +#define TX_BUFFER_T0_ELEM_RTR_Msk (0x1ul << TX_BUFFER_T0_ELEM_RTR_Pos) + +/* Tx Buffer Element ID(Identifier) */ +#define TX_BUFFER_T0_ELEM_ID_Pos (0) +#define TX_BUFFER_T0_ELEM_ID_Msk (0x1FFFFFFFul << TX_BUFFER_T0_ELEM_ID_Pos) + +/* Tx Buffer Element MM(Message Marker) */ +#define TX_BUFFER_T1_ELEM_MM1_Pos (24) +#define TX_BUFFER_T1_ELEM_MM1_Msk (0xFFul << TX_BUFFER_T1_ELEM_MM1_Pos) + +/* Tx Buffer Element EFC(Event FIFO Control) */ +#define TX_BUFFER_T1_ELEM_EFC_Pos (23) +#define TX_BUFFER_T1_ELEM_EFC_Msk (0xFFul << TX_BUFFER_T1_ELEM_EFC_Pos) + +/* Tx Buffer Element TSCE(Time Stamp Capture Enable for TSU) */ +#define TX_BUFFER_T1_ELEM_TSCE_Pos (22) +#define TX_BUFFER_T1_ELEM_TSCE_Msk (0x1ul << TX_BUFFER_T1_ELEM_TSCE_Pos) + +/* Tx Buffer Element FDF(FD Format) */ +#define TX_BUFFER_T1_ELEM_FDF_Pos (21) +#define TX_BUFFER_T1_ELEM_FDF_Msk (0x1ul << TX_BUFFER_T1_ELEM_FDF_Pos) + +/* Tx Buffer Element BRS(Bit Rate Swit) */ +#define TX_BUFFER_T1_ELEM_BSR_Pos (20) +#define TX_BUFFER_T1_ELEM_BSR_Msk (0x1ul << TX_BUFFER_T1_ELEM_BSR_Pos) + +/* Tx Buffer Element DLC(Bit Rate Swit) */ +#define TX_BUFFER_T1_ELEM_DLC_Pos (16) +#define TX_BUFFER_T1_ELEM_DLC_Msk (0xFul << TX_BUFFER_T1_ELEM_DLC_Pos) + +/* Tx Buffer Element MM(Message Marker) */ +#define TX_BUFFER_T1_ELEM_MM0_Pos (8) +#define TX_BUFFER_T1_ELEM_MM0_Msk (0xFFul << TX_BUFFER_T1_ELEM_MM0_Pos) + +#define CANFD_RXFS_RFL CANFD_RXF0S_RF0L_Msk + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CANFD_Driver CAN_FD Driver + @{ +*/ + +int32_t g_CANFD_i32ErrCode = 0; /*!< CANFD global error code */ + +/** @addtogroup CANFD_EXPORTED_FUNCTIONS CAN_FD Exported Functions + @{ +*/ + +static uint32_t _GetCanfdSramBaseAddr(CANFD_T * psCanfd) +{ + if (psCanfd == CANFD0) + return (CANFD0_SRAM_BASE_ADDR); + else if (psCanfd == CANFD1) + return (CANFD1_SRAM_BASE_ADDR); + else if (psCanfd == CANFD2) + return (CANFD2_SRAM_BASE_ADDR); + else if (psCanfd == CANFD3) + return (CANFD3_SRAM_BASE_ADDR); + + return 0; +} + +/** + * @brief Calculates the CAN FD RAM buffer address. + * + * @param[in] psConfigAddr CAN FD element star address structure. + * @param[in] psConfigSize CAN FD element size structure. + * + * @return None. + * + * @details Calculates the CAN FD RAM buffer address. + */ +static void CANFD_CalculateRamAddress(CANFD_RAM_PART_T *psConfigAddr, CANFD_ELEM_SIZE_T *psConfigSize) +{ + uint32_t u32RamAddrOffset = 0; + + /* Get the Standard Message ID Filter element address */ + if (psConfigSize->u32SIDFC > 0) + { + psConfigAddr->u32SIDFC_FLSSA = 0; + u32RamAddrOffset += psConfigSize->u32SIDFC * sizeof(CANFD_STD_FILTER_T); + } + + /* Get the Standard Message ID Filter element address */ + if (psConfigSize->u32XIDFC > 0) + { + psConfigAddr->u32XIDFC_FLESA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32XIDFC * sizeof(CANFD_EXT_FILTER_T); + } + + /* Get the Tx Buffer element address */ + if (psConfigSize->u32TxBuf > 0) + { + psConfigAddr->u32TXBC_TBSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32TxBuf * sizeof(CANFD_BUF_T); + } + + /* Get the Rx Buffer element address */ + if (psConfigSize->u32RxBuf > 0) + { + psConfigAddr->u32RXBC_RBSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32RxBuf * sizeof(CANFD_BUF_T); + } + + /* Get the Rx FIFO0 element address */ + if (psConfigSize->u32RxFifo0 > 0) + { + psConfigAddr->u32RXF0C_F0SA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32RxFifo0 * sizeof(CANFD_BUF_T); + } + + /* Get the Rx FIFO1 element address */ + if (psConfigSize->u32RxFifo1 > 0) + { + psConfigAddr->u32RXF1C_F1SA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32RxFifo1 * sizeof(CANFD_BUF_T); + } + + /* Get the Rx FIFO1 element address */ + if (psConfigSize->u32TxEventFifo > 0) + { + psConfigAddr->u32TXEFC_EFSA = u32RamAddrOffset; + u32RamAddrOffset += psConfigSize->u32TxEventFifo * sizeof(CANFD_EXT_FILTER_T); + } +} + + +/** + * @brief Get the default configuration structure. + * + * @param[in] psConfig Pointer to CAN FD configuration structure. + * @param[in] u8OpMode Setting the CAN FD Operating mode. + * + * @return None. + * + * @details This function initializes the CAN FD configure structure to default value. + * The default value are: + * sNormBitRate.u32BitRate = 500000bps; + * u32DataBaudRate = 0(CAN mode) or 1000000(CAN FD mode) ; + * u32MRamSize = 0x20010000; + * bEnableLoopBack = FALSE; + * bBitRateSwitch = FALSE(CAN Mode) or TRUE(CAN FD Mode); + * bFDEn = FALSE(CAN Mode) or TRUE(CAN FD Mode); + * CAN FD Standard ID elements = 12 + * CAN FD Extended ID elements = 10 + * CAN FD TX Buffer elements = 3 + * CAN FD RX Buffer elements = 3 + * CAN FD RX FIFO0 elements = 3 + * CAN FD RX FIFO1 elements = 3 + * CAN FD TX Event FOFI elements = 3 +*/ +void CANFD_GetDefaultConfig(CANFD_FD_T *psConfig, uint8_t u8OpMode) +{ + memset(psConfig, 0, sizeof(CANFD_FD_T)); + + psConfig->sBtConfig.sNormBitRate.u32BitRate = 500000; + + if (u8OpMode == CANFD_OP_CAN_MODE) + { + psConfig->sBtConfig.sDataBitRate.u32BitRate = 0; + psConfig->sBtConfig.bFDEn = FALSE; + psConfig->sBtConfig.bBitRateSwitch = FALSE; + } + else + { + psConfig->sBtConfig.sDataBitRate.u32BitRate = 10000000; + psConfig->sBtConfig.bFDEn = TRUE; + psConfig->sBtConfig.bBitRateSwitch = TRUE; + } + + /*Disable the Internal Loopback mode */ + psConfig->sBtConfig.bEnableLoopBack = FALSE; + /*Get the CAN FD memory address*/ + psConfig->u32MRamSize = CANFD_SRAM_SIZE; + + /* CAN FD Standard message ID elements as 12 elements */ + psConfig->sElemSize.u32SIDFC = 12; + /* CAN FD Extended message ID elements as 10 elements */ + psConfig->sElemSize.u32XIDFC = 10; + /* CAN FD TX Buffer elements as 3 elements */ + psConfig->sElemSize.u32TxBuf = 3; + /* CAN FD RX Buffer elements as 3 elements */ + psConfig->sElemSize.u32RxBuf = 3; + /* CAN FD RX FIFO0 elements as 3 elements */ + psConfig->sElemSize.u32RxFifo0 = 3; + /* CAN FD RX FIFO1 elements as 3 elements */ + psConfig->sElemSize.u32RxFifo1 = 3; + /* CAN FD TX Event FOFI elements as 3 elements */ + psConfig->sElemSize.u32TxEventFifo = 3; + /*Calculates the CAN FD RAM buffer address*/ + CANFD_CalculateRamAddress(&psConfig->sMRamStartAddr, &psConfig->sElemSize); +} + + +/** + * @brief Encode the Data Length Code. + * + * @param[in] u8NumberOfBytes Number of bytes in a message. + * + * @return Data Length Code. + * + * @details Converts number of bytes in a message into a Data Length Code. + */ +static uint8_t CANFD_EncodeDLC(uint8_t u8NumberOfBytes) +{ + if (u8NumberOfBytes <= 8) return u8NumberOfBytes; + else if (u8NumberOfBytes <= 12) return 9; + else if (u8NumberOfBytes <= 16) return 10; + else if (u8NumberOfBytes <= 20) return 11; + else if (u8NumberOfBytes <= 24) return 12; + else if (u8NumberOfBytes <= 32) return 13; + else if (u8NumberOfBytes <= 48) return 14; + else return 15; +} + + +/** + * @brief Decode the Data Length Code. + * + * @param[in] u8Dlc Data Length Code. + * + * @return Number of bytes in a message. + * + * @details Converts a Data Length Code into a number of message bytes. + */ +static uint8_t CANFD_DecodeDLC(uint8_t u8Dlc) +{ + if (u8Dlc <= 8) return u8Dlc; + else if (u8Dlc == 9) return 12; + else if (u8Dlc == 10) return 16; + else if (u8Dlc == 11) return 20; + else if (u8Dlc == 12) return 24; + else if (u8Dlc == 13) return 32; + else if (u8Dlc == 14) return 48; + else return 64; +} + + +/** + * @brief Sets the CAN FD protocol timing characteristic. + * + * @param[in] psCanfd The pointer of the specified CANFD module. + * @param[in] psConfig Pointer to the timing configuration structure. + * + * @return None. + * + * @details This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the CANFD_Open() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + */ +static void CANFD_SetTimingConfig(CANFD_T *psCanfd, const CANFD_TIMEING_CONFIG_T *psConfig) +{ + uint32_t *pu32DBTP; + + /* configuration change enable */ + psCanfd->CCCR |= CANFD_CCCR_CCE_Msk; + + if (psCanfd == (CANFD_T *)CANFD0) + { + /* Get CANF D0 clock divider number */ + CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_CANFD0DIV_Msk) | CLK_CLKDIV5_CANFD0(psConfig->u8PreDivider) ; + } + + /* nominal bit rate */ + psCanfd->NBTP = (((psConfig->u8NominalRJumpwidth & 0x7F) - 1) << 25) + + (((psConfig->u16NominalPrescaler & 0x1FF) - 1) << 16) + + ((((psConfig->u8NominalPhaseSeg1 + psConfig->u8NominalPropSeg) & 0xFF) - 1) << 8) + + (((psConfig->u8NominalPhaseSeg2 & 0x7F) - 1) << 0); + + + /* canfd->DBTP */ + if (psCanfd->CCCR & CANFD_CCCR_FDOE_Msk) + { + pu32DBTP = (((uint32_t *)psCanfd) + 0x03); + *pu32DBTP = (((psConfig->u8DataPrescaler & 0x1F) - 1) << 16) + + ((((psConfig->u8DataPhaseSeg1 + psConfig->u8DataPropSeg) & 0x1F) - 1) << 8) + + (((psConfig->u8DataPhaseSeg2 & 0xF) - 1) << 4) + + (((psConfig->u8DataRJumpwidth & 0xF) - 1) << 0); + } +} + + +/** + * @brief Get the segment values. + * + * @param[in] u32NominalBaudRate The nominal speed in bps. + * @param[in] u32DataBaudRate The data speed in bps. + * @param[in] u32Ntq Number of nominal time quanta per bit. + * @param[in] u32Dtq Number of data time quanta per bit. + * @param[in] psConfig Passed is a configuration structure, on return the configuration is stored in the structure + * + * @return None. + * + * @details Calculates the segment values for a single bit time for nominal and data baudrates. + */ +static void CANFD_GetSegments(uint32_t u32NominalBaudRate, uint32_t u32DataBaudRate, uint32_t u32Ntq, uint32_t u32Dtq, CANFD_TIMEING_CONFIG_T *psConfig) +{ + float ideal_sp; + int int32P1; + + /* get ideal sample point */ + if (u32NominalBaudRate >= 1000000) ideal_sp = 0.750; + else if (u32NominalBaudRate >= 800000) ideal_sp = 0.800; + else ideal_sp = 0.875; + + /* distribute time quanta */ + int32P1 = (int)(u32Ntq * ideal_sp); + /* can controller doesn't separate prop seg and phase seg 1 */ + psConfig->u8NominalPropSeg = 0; + /* subtract one TQ for sync seg */ + psConfig->u8NominalPhaseSeg1 = int32P1 - 1; + psConfig->u8NominalPhaseSeg2 = u32Ntq - int32P1; + /* sjw is 20% of total TQ, rounded to nearest int */ + psConfig->u8NominalRJumpwidth = (u32Ntq + (5 - 1)) / 5; + + + /* if using baud rate switching then distribute time quanta for data rate */ + if (u32Dtq > 0) + { + /* get ideal sample point */ + if (u32DataBaudRate >= 1000000) ideal_sp = 0.750; + else if (u32DataBaudRate >= 800000) ideal_sp = 0.800; + else ideal_sp = 0.875; + + /* distribute time quanta */ + int32P1 = (int)(u32Dtq * ideal_sp); + /* can controller doesn't separate prop seg and phase seg 1 */ + psConfig->u8DataPropSeg = 0; + /* subtract one TQ for sync seg */ + psConfig->u8DataPhaseSeg1 = int32P1 - 1; + psConfig->u8DataPhaseSeg2 = u32Dtq - int32P1; + /* sjw is 20% of total TQ, rounded to nearest int */ + psConfig->u8DataRJumpwidth = (u32Dtq + (5 - 1)) / 5; + } + else + { + psConfig->u8DataPropSeg = 0; + psConfig->u8DataPhaseSeg1 = 0; + psConfig->u8DataPhaseSeg2 = 0; + psConfig->u8DataRJumpwidth = 0; + } +} + + +/** + * @brief Calculates the CAN controller timing values for specific baudrates. + * + * @param[in] u32NominalBaudRate The nominal speed in bps. + * @param[in] u32DataBaudRate The data speed in bps. Zero to disable baudrate switching. + * @param[in] u32SourceClock_Hz CAN FD Protocol Engine clock source frequency in Hz. + * @param[in] psConfig Passed is a configuration structure, on return the configuration is stored in the structure + * + * @return true if timing configuration found, false if failed to find configuration. + * + * @details Calculates the CAN controller timing values for specific baudrates. + */ +static uint32_t CANFD_CalculateTimingValues(uint32_t u32NominalBaudRate, uint32_t u32DataBaudRate, uint32_t u32SourceClock_Hz, CANFD_TIMEING_CONFIG_T *psConfig) +{ + int i32Nclk; + int i32Nclk2; + int i32Ntq; + int i32Dclk; + int i32Dclk2; + int i32Dtq; + + /* observe baud rate maximums */ + if (u32NominalBaudRate > MAX_NOMINAL_BAUDRATE) u32NominalBaudRate = MAX_NOMINAL_BAUDRATE; + + for (i32Ntq = MAX_TIME_QUANTA; i32Ntq >= MIN_TIME_QUANTA; i32Ntq--) + { + i32Nclk = u32NominalBaudRate * i32Ntq; + + for (psConfig->u16NominalPrescaler = 0x001; psConfig->u16NominalPrescaler <= 0x400; (psConfig->u16NominalPrescaler)++) + { + i32Nclk2 = i32Nclk * psConfig->u16NominalPrescaler; + + if (((u32SourceClock_Hz / i32Nclk2) <= 5) && ((float)(u32SourceClock_Hz) / i32Nclk2) == (u32SourceClock_Hz / i32Nclk2)) + { + psConfig->u8PreDivider = u32SourceClock_Hz / i32Nclk2; + + + /* if not using baudrate switch then we are done */ + if (!u32DataBaudRate) + { + i32Dtq = 0; + psConfig->u8DataPrescaler = 0; + CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); + return TRUE; + } + + /* if baudrates are the same and the solution for nominal will work for + data, then use the nominal settings for both */ + if ((u32DataBaudRate == u32NominalBaudRate) && psConfig->u16NominalPrescaler <= 0x20) + { + i32Dtq = i32Ntq; + psConfig->u8DataPrescaler = (uint8_t)psConfig->u16NominalPrescaler; + CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); + return TRUE; + } + + /* calculate data settings */ + for (i32Dtq = MAX_TIME_QUANTA; i32Dtq >= MIN_TIME_QUANTA; i32Dtq--) + { + i32Dclk = u32DataBaudRate * i32Dtq; + + for (psConfig->u8DataPrescaler = 0x01; psConfig->u8DataPrescaler <= 0x20; (psConfig->u8DataPrescaler)++) + { + i32Dclk2 = i32Dclk * psConfig->u8DataPrescaler; + + if ((float)(u32SourceClock_Hz) / i32Dclk2 == psConfig->u8PreDivider) + { + CANFD_GetSegments(u32NominalBaudRate, u32DataBaudRate, i32Ntq, i32Dtq, psConfig); + return TRUE; + } + } + } + + if (u32DataBaudRate == 0) + { + CANFD_GetSegments(u32NominalBaudRate, 0, i32Ntq, 0, psConfig); + return TRUE; + } + } + } + } + + /* failed to find solution */ + return 0; +} + + +/** + * @brief Config message ram and Set bit-time. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psCanfdStr message ram setting and bit-time setting + * + * @return None. + * + * @details Converts a Data Length Code into a number of message bytes. + */ +void CANFD_Open(CANFD_T *psCanfd, CANFD_FD_T *psCanfdStr) +{ + if (psCanfd == (CANFD_T *)CANFD0) + { + //CLK_EnableModuleClock(CANFD0_MODULE); + CLK->AHBCLK1 |= BIT0; + //SYS_ResetModule(CANFD0_RST); + NVIC_EnableIRQ(CANFD00_IRQn); + NVIC_EnableIRQ(CANFD01_IRQn); + } + else if (psCanfd == (CANFD_T *)CANFD1) + { + //CLK_EnableModuleClock(CANFD1_MODULE); + CLK->AHBCLK1 |= BIT1; + //SYS_ResetModule(CANFD1_RST); + NVIC_EnableIRQ(CANFD10_IRQn); + NVIC_EnableIRQ(CANFD11_IRQn); + } + else if (psCanfd == (CANFD_T *)CANFD2) + { + //CLK_EnableModuleClock(CANFD2_MODULE); + CLK->AHBCLK1 |= BIT2; + //SYS_ResetModule(CANFD2_RST); + NVIC_EnableIRQ(CANFD20_IRQn); + NVIC_EnableIRQ(CANFD21_IRQn); + } + else if (psCanfd == (CANFD_T *)CANFD3) + { + //CLK_EnableModuleClock(CANFD3_MODULE); + CLK->AHBCLK1 |= BIT3; + //SYS_ResetModule(CANFD3_RST); + NVIC_EnableIRQ(CANFD30_IRQn); + NVIC_EnableIRQ(CANFD31_IRQn); + } + + + /* configuration change enable */ + psCanfd->CCCR |= CANFD_CCCR_CCE_Msk; + + if (psCanfdStr->sBtConfig.bBitRateSwitch) + { + /* enable FD and baud-rate switching */ + psCanfd->CCCR |= CANFD_CCCR_BRSE_Msk; + } + + if (psCanfdStr->sBtConfig.bFDEn) + { + /*FD Operation enabled*/ + psCanfd->CCCR |= CANFD_CCCR_FDOE_Msk; + } + + /*Clear the Rx Fifo0 element setting */ + psCanfd->RXF0C = 0; + /*Clear the Rx Fifo1 element setting */ + psCanfd->RXF1C = 0; + + /* calculate and apply timing */ + if (CANFD_CalculateTimingValues(psCanfdStr->sBtConfig.sNormBitRate.u32BitRate, psCanfdStr->sBtConfig.sDataBitRate.u32BitRate, + SystemCoreClock, &psCanfdStr->sBtConfig.sConfigBitTing)) + { + CANFD_SetTimingConfig(psCanfd, &psCanfdStr->sBtConfig.sConfigBitTing); + } + + /* Configures the Standard ID Filter element */ + if (psCanfdStr->sElemSize.u32SIDFC != 0) + CANFD_ConfigSIDFC(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize); + + /*Configures the Extended ID Filter element */ + if (psCanfdStr->sElemSize.u32XIDFC != 0) + CANFD_ConfigXIDFC(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize); + + /*Configures the Tx Buffer element */ + if (psCanfdStr->sElemSize.u32RxBuf != 0) + CANFD_InitTxDBuf(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, eCANFD_BYTE64); + + /*Configures the Rx Buffer element */ + if (psCanfdStr->sElemSize.u32RxBuf != 0) + CANFD_InitRxDBuf(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, eCANFD_BYTE64); + + /*Configures the Rx Fifo0 element */ + if (psCanfdStr->sElemSize.u32RxFifo0 != 0) + CANFD_InitRxFifo(psCanfd, 0, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, 0, eCANFD_BYTE64); + + /*Configures the Rx Fifo1 element */ + if (psCanfdStr->sElemSize.u32RxFifo1 != 0) + CANFD_InitRxFifo(psCanfd, 1, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, 0, eCANFD_BYTE64); + + /*Configures the Tx Event FIFO element */ + if (psCanfdStr->sElemSize.u32TxEventFifo != 0) + CANFD_InitTxEvntFifo(psCanfd, &psCanfdStr->sMRamStartAddr, &psCanfdStr->sElemSize, 0); + + /*Reject all Non-matching Frames Extended ID and Frames Standard ID,Reject all remote frames with 11-bit standard IDs and 29-bit extended IDs */ + CANFD_SetGFC(psCanfd, eCANFD_REJ_NON_MATCH_FRM, eCANFD_REJ_NON_MATCH_FRM, 1, 1); + + if (psCanfdStr->sBtConfig.bEnableLoopBack) + { + psCanfd->CCCR |= CANFD_CCCR_TEST_Msk; + psCanfd->TEST |= CANFD_TEST_LBCK_Msk; + } +} + + +/** + * @brief Close the CAN FD Bus. + * + * @param[in] psCanfd The pointer to CANFD module base address. + * + * @return None. + * + * @details Disable the CAN FD clock and Interrupt. + */ +void CANFD_Close(CANFD_T *psCanfd) +{ + if (psCanfd == (CANFD_T *)CANFD0) + { + //CLK_DisableModuleClock(CANFD0_MODULE); + CLK->AHBCLK1 |= BIT20; + NVIC_DisableIRQ(CANFD00_IRQn); + NVIC_DisableIRQ(CANFD01_IRQn); + } + else if (psCanfd == (CANFD_T *)CANFD1) + { + //CLK_DisableModuleClock(CANFD1_MODULE); + CLK->AHBCLK1 |= BIT21; + NVIC_DisableIRQ(CANFD10_IRQn); + NVIC_DisableIRQ(CANFD11_IRQn); + } + else if (psCanfd == (CANFD_T *)CANFD2) + { + //CLK_DisableModuleClock(CANFD2_MODULE); + CLK->AHBCLK1 |= BIT22; + NVIC_DisableIRQ(CANFD20_IRQn); + NVIC_DisableIRQ(CANFD21_IRQn); + } + else if (psCanfd == (CANFD_T *)CANFD3) + { + //CLK_DisableModuleClock(CANFD3_MODULE); + CLK->AHBCLK1 |= BIT23; + NVIC_DisableIRQ(CANFD30_IRQn); + NVIC_DisableIRQ(CANFD31_IRQn); + } +} + + +/** + * @brief Get the element's address when read transmit buffer. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32Idx The number of the transmit buffer element + * + * @return Address of the element in transmit buffer. + * + * @details The function is used to get the element's address when read transmit buffer. + */ +static uint32_t CANFD_GetTxBufferElementAddress(CANFD_T *psCanfd, uint32_t u32Idx) +{ + uint32_t u32Size = 0; + u32Size = (psCanfd->TXESC & CANFD_TXESC_TBDS_Msk) >> CANFD_TXESC_TBDS_Pos; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + return (psCanfd->TXBC & CANFD_TXBC_TBSA_Msk) + u32Idx * u32Size * 4U; +} + + +/** + * @brief Enables CAN FD interrupts according to provided mask . + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32IntLine0 The Interrupt Line 0 type select. + * @param[in] u32IntLine1 The Interrupt Line 1 type select. + * - \ref CANFD_IE_ARAE_Msk : Access to Reserved Address Interrupt + * - \ref CANFD_IE_PEDE_Msk : Protocol Error in Data Phase Interrupt + * - \ref CANFD_IE_PEAE_Msk : Protocol Error in Arbitration Phase Interrupt + * - \ref CANFD_IE_WDIE_Msk : Watchdog Interrupt + * - \ref CANFD_IE_BOE_Msk : Bus_Off Status Interrupt + * - \ref CANFD_IE_EWE_Msk : Warning Status Interrupt + * - \ref CANFD_IE_EPE_Msk : Error Passive Interrupt + * - \ref CANFD_IE_ELOE_Msk : Error Logging Overflow Interrupt + * - \ref CANFD_IE_BEUE_Msk : Bit Error Uncorrected Interrupt + * - \ref CANFD_IE_BECE_Msk : Bit Error Corrected Interrupt + * - \ref CANFD_IE_DRXE_Msk : Message stored to Dedicated Rx Buffer Interrupt + * - \ref CANFD_IE_TOOE_Msk : Timeout Occurred Interrupt + * - \ref CANFD_IE_MRAFE_Msk : Message RAM Access Failure Interrupt + * - \ref CANFD_IE_TSWE_Msk : Timestamp Wraparound Interrupt + * - \ref CANFD_IE_TEFLE_Msk : Tx Event FIFO Event Lost Interrupt + * - \ref CANFD_IE_TEFFE_Msk : Tx Event FIFO Full Interrupt + * - \ref CANFD_IE_TEFWE_Msk : Tx Event FIFO Watermark Reached Interrupt + * - \ref CANFD_IE_TEFNE_Msk : Tx Event FIFO New Entry Interrupt + * - \ref CANFD_IE_TFEE_Msk : Tx FIFO Empty Interrupt + * - \ref CANFD_IE_TCFE_Msk : Transmission Cancellation Finished Interrupt + * - \ref CANFD_IE_TCE_Msk : Transmission Completed Interrupt + * - \ref CANFD_IE_HPME_Msk : High Priority Message Interrupt + * - \ref CANFD_IE_RF1LE_Msk : Rx FIFO 1 Message Lost Interrupt + * - \ref CANFD_IE_RF1FE_Msk : Rx FIFO 1 Full Interrupt + * - \ref CANFD_IE_RF1WE_Msk : Rx FIFO 1 Watermark Reached Interrupt + * - \ref CANFD_IE_RF1NE_Msk : Rx FIFO 1 New Message Interrupt + * - \ref CANFD_IE_RF0LE_Msk : Rx FIFO 0 Message Lost Interrupt + * - \ref CANFD_IE_RF0FE_Msk : Rx FIFO 0 Full Interrupt + * - \ref CANFD_IE_RF0WE_Msk : Rx FIFO 0 Watermark Reached Interrupt + * - \ref CANFD_IE_RF0NE_Msk : Rx FIFO 0 New Message Interrupt + * + * @param[in] u32TXBTIE Enable Tx Buffer Transmission 0-31 Interrupt. + * @param[in] u32TXBCIE Enable Tx Buffer Cancellation Finished 0-31 Interrupt. + * @return None. + * + * @details This macro enable specified CAN FD interrupt. + */ +void CANFD_EnableInt(CANFD_T *psCanfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE) +{ + + if (u32IntLine0 != 0) + { + /*Setting the CANFD0_IRQ0 Interrupt*/ + psCanfd->IE |= u32IntLine0; + /* Enable CAN FD specified interrupt */ + psCanfd->ILE |= ((uint32_t)1U << 0); + } + + if (u32IntLine1 != 0) + { + /*Setting the CANFD0_IRQ1 Interrupt*/ + psCanfd->ILS |= u32IntLine1; + /* Enable CAN FD specified interrupt */ + psCanfd->ILE |= ((uint32_t)1U << 1); + } + + /*Setting the Tx Buffer Transmission Interrupt Enable*/ + psCanfd->TXBTIE |= u32TXBTIE; + + /*Tx Buffer Cancellation Finished Interrupt Enable*/ + psCanfd->TXBCIE |= u32TXBCIE; +} + + +/** + * @brief Disables CAN FD interrupts according to provided mask . + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32IntLine0 The Interrupt Line 0 type select. + * @param[in] u32IntLine1 The Interrupt Line 1 type select. + * - \ref CANFD_IE_ARAE_Msk : Access to Reserved Address Interrupt + * - \ref CANFD_IE_PEDE_Msk : Protocol Error in Data Phase Interrupt + * - \ref CANFD_IE_PEAE_Msk : Protocol Error in Arbitration Phase Interrupt + * - \ref CANFD_IE_WDIE_Msk : Watchdog Interrupt + * - \ref CANFD_IE_BOE_Msk : Bus_Off Status Interrupt + * - \ref CANFD_IE_EWE_Msk : Warning Status Interrupt + * - \ref CANFD_IE_EPE_Msk : Error Passive Interrupt + * - \ref CANFD_IE_ELOE_Msk : Error Logging Overflow Interrupt + * - \ref CANFD_IE_BEUE_Msk : Bit Error Uncorrected Interrupt + * - \ref CANFD_IE_BECE_Msk : Bit Error Corrected Interrupt + * - \ref CANFD_IE_DRXE_Msk : Message stored to Dedicated Rx Buffer Interrupt + * - \ref CANFD_IE_TOOE_Msk : Timeout Occurred Interrupt + * - \ref CANFD_IE_MRAFE_Msk : Message RAM Access Failure Interrupt + * - \ref CANFD_IE_TSWE_Msk : Timestamp Wraparound Interrupt + * - \ref CANFD_IE_TEFLE_Msk : Tx Event FIFO Event Lost Interrupt + * - \ref CANFD_IE_TEFFE_Msk : Tx Event FIFO Full Interrupt + * - \ref CANFD_IE_TEFWE_Msk : Tx Event FIFO Watermark Reached Interrupt + * - \ref CANFD_IE_TEFNE_Msk : Tx Event FIFO New Entry Interrupt + * - \ref CANFD_IE_TFEE_Msk : Tx FIFO Empty Interrupt + * - \ref CANFD_IE_TCFE_Msk : Transmission Cancellation Finished Interrupt + * - \ref CANFD_IE_TCE_Msk : Transmission Completed Interrupt + * - \ref CANFD_IE_HPME_Msk : High Priority Message Interrupt + * - \ref CANFD_IE_RF1LE_Msk : Rx FIFO 1 Message Lost Interrupt + * - \ref CANFD_IE_RF1FE_Msk : Rx FIFO 1 Full Interrupt + * - \ref CANFD_IE_RF1WE_Msk : Rx FIFO 1 Watermark Reached Interrupt + * - \ref CANFD_IE_RF1NE_Msk : Rx FIFO 1 New Message Interrupt + * - \ref CANFD_IE_RF0LE_Msk : Rx FIFO 0 Message Lost Interrupt + * - \ref CANFD_IE_RF0FE_Msk : Rx FIFO 0 Full Interrupt + * - \ref CANFD_IE_RF0WE_Msk : Rx FIFO 0 Watermark Reached Interrupt + * - \ref CANFD_IE_RF0NE_Msk : Rx FIFO 0 New Message Interrupt + * + * @param[in] u32TXBTIE Disable Tx Buffer Transmission 0-31 Interrupt. + * @param[in] u32TXBCIE Disable Tx Buffer Cancellation Finished 0-31 Interrupt. + * @return None. + * + * @details This macro disable specified CAN FD interrupt. + */ +void CANFD_DisableInt(CANFD_T *psCanfd, uint32_t u32IntLine0, uint32_t u32IntLine1, uint32_t u32TXBTIE, uint32_t u32TXBCIE) +{ + if (u32IntLine0 != 0) + { + /*Clear the CANFD0_IRQ0 Interrupt*/ + psCanfd->IE &= ~u32IntLine0; + /* Disable CAN FD specified interrupt */ + psCanfd->ILE &= ~((uint32_t)1U << 0); + } + + if (u32IntLine1 != 0) + { + /*Clear the CANFD0_IRQ1 Interrupt*/ + psCanfd->ILS &= ~u32IntLine1; + /* Disable CAN FD specified interrupt */ + psCanfd->ILE &= ~((uint32_t)1U << 1); + } + + /*Setting the Tx Buffer Transmission Interrupt Disable*/ + psCanfd->TXBTIE &= ~u32TXBTIE; + + /*Tx Buffer Cancellation Finished Interrupt Disable*/ + psCanfd->TXBCIE &= ~u32TXBCIE; +} + + +/** + * @brief Copy Tx Message to TX buffer and Request transmission. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxBufIdx The Message Buffer index. + * @param[in] psTxMsg Message to be copied. + * + * @return number of tx requests set: 0= Tx Message Buffer is currently in use. + * 1= Write Tx Message Buffer Successfully. + * + * @details Copy Tx Message to FIFO/Queue TX buffer and Request transmission. + */ +uint32_t CANFD_TransmitTxMsg(CANFD_T *psCanfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg) +{ + uint32_t u32Success = 0; + uint32_t u32TimeOutCount = CANFD_TIMEOUT; + + /* write the message to the message buffer */ + u32Success = CANFD_TransmitDMsg(psCanfd, u32TxBufIdx, psTxMsg); + + if (u32Success == 1) + { + /* wait for completion */ + while (!(psCanfd->TXBRP & (1UL << u32TxBufIdx))) + { + if(u32TimeOutCount-- == 0) + { + u32Success = 0; + break; + } + + } + } + + return u32Success; +} + + +/** + * @brief Writes a Tx Message to Transmit Message Buffer. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32TxBufIdx The Message Buffer index. + * @param[in] psTxMsg Pointer to CAN FD message frame to be sent. + * + * @return 1 Write Tx Message Buffer Successfully. + * 0 Tx Message Buffer is currently in use. + * + * @details This function writes a CANFD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CANFD Message transmit. After + * that the function returns immediately. + */ +uint32_t CANFD_TransmitDMsg(CANFD_T *psCanfd, uint32_t u32TxBufIdx, CANFD_FD_MSG_T *psTxMsg) +{ + CANFD_BUF_T *psTxBuffer; + uint32_t u32Idx = 0, u32Success = 1; + uint32_t u32SramBaseAddr; + + if (u32TxBufIdx >= CANFD_MAX_TX_BUF_ELEMS) return 0; + + /* transmission is pending in this message buffer */ + if (psCanfd->TXBRP & (1UL << u32TxBufIdx)) return 0; + + //psTxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->TXBC & 0xFFFF) + (u32TxBufIdx * sizeof(CANFD_BUF_T))); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + psTxBuffer = (CANFD_BUF_T *)(u32SramBaseAddr + (psCanfd->TXBC & 0xFFFF) + (u32TxBufIdx * sizeof(CANFD_BUF_T))); + + if (psTxMsg->eIdType == eCANFD_XID) + { + psTxBuffer->u32Id = TX_BUFFER_T0_ELEM_XTD_Msk | (psTxMsg->u32Id & 0x1FFFFFFF); + } + else + { + psTxBuffer->u32Id = (psTxMsg->u32Id & 0x7FF) << 18; + } + + if (psTxMsg->eFrmType == eCANFD_REMOTE_FRM) psTxBuffer->u32Id |= TX_BUFFER_T0_ELEM_RTR_Msk; + + psTxBuffer->u32Config = (CANFD_EncodeDLC(psTxMsg->u32DLC) << 16); + + if (psTxMsg->bFDFormat) psTxBuffer->u32Config |= TX_BUFFER_T1_ELEM_FDF_Msk; + + if (psTxMsg->bBitRateSwitch) psTxBuffer->u32Config |= TX_BUFFER_T1_ELEM_BSR_Msk; + + + for (u32Idx = 0; u32Idx < (psTxMsg->u32DLC + (4 - 1)) / 4; u32Idx++) + { + psTxBuffer->au32Data[u32Idx] = psTxMsg->au32Data[u32Idx]; + } + + psCanfd->TXBAR = (1 << u32TxBufIdx); + + return u32Success; +} + + +/** + * @brief Global Filter Configuration (GFC). + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] eNMStdFrm Accept/Reject Non-Matching Standard(11-bits) Frames. + * @param[in] eEMExtFrm Accept/Reject Non-Matching Extended(29-bits) Frames. + * @param[in] u32RejRmtStdFrm Reject/Filter Remote Standard Frames. + * @param[in] u32RejRmtExtFrm Reject/Filter Remote Extended Frames. + * + * @return None. + * + * @details Global Filter Configuration. + */ +void CANFD_SetGFC(CANFD_T *psCanfd, E_CANFD_ACC_NON_MATCH_FRM eNMStdFrm, E_CANFD_ACC_NON_MATCH_FRM eEMExtFrm, uint32_t u32RejRmtStdFrm, uint32_t u32RejRmtExtFrm) +{ + psCanfd->GFC &= (CANFD_GFC_RRFS_Msk | CANFD_GFC_RRFE_Msk); + psCanfd->GFC = (eNMStdFrm << CANFD_GFC_ANFS_Pos) | (eEMExtFrm << CANFD_GFC_ANFE_Pos) + | (u32RejRmtStdFrm << CANFD_GFC_RRFS_Pos) | (u32RejRmtExtFrm << CANFD_GFC_RRFE_Pos); +} + + +/** + * @brief Rx FIFO Configuration for RX_FIFO_0 and RX_FIFO_1. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32RxFifoNum 0: RX FIFO_0, 1: RX_FIFO_1. + * @param[in] psRamConfig Rx FIFO Size in number of configuration ram address. + * @param[in] psElemSize Rx FIFO Size in number of Rx FIFO elements (element number (max. = 64)). + * @param[in] u32FifoWM Watermark in number of Rx FIFO elements + * @param[in] eFifoSize Maximum data field size that should be stored in this Rx FIFO + * (configure BYTE64 if you are unsure, as this is the largest data field allowed in CAN FD) + * + * @return None. + * + * @details Rx FIFO Configuration for RX_FIFO_0 and RX_FIFO_1. + */ +void CANFD_InitRxFifo(CANFD_T *psCanfd, uint32_t u32RxFifoNum, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWM, E_CANFD_DATA_FIELD_SIZE eFifoSize) +{ + uint32_t u32Address; + uint32_t u32Size; + uint32_t u32SramBaseAddr; + + /* ignore if index is too high */ + if (u32RxFifoNum > CANFD_NUM_RX_FIFOS)return; + + /* ignore if index is too high */ + if (psElemSize-> u32RxFifo0 > CANFD_MAX_RX_FIFO0_ELEMS) return; + + /* ignore if index is too high */ + if (psElemSize-> u32RxFifo1 > CANFD_MAX_RX_FIFO1_ELEMS) return; + + switch (u32RxFifoNum) + { + case 0: + if (psElemSize-> u32RxFifo0) + { + /* set size of Rx FIFO 0, set offset, blocking mode */ + psCanfd->RXF0C = (psRamConfig->u32RXF0C_F0SA) | (psElemSize->u32RxFifo0 << CANFD_RXF0C_F0S_Pos) + | (u32FifoWM << CANFD_RXF0C_F0WM_Pos); + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F0DS_Msk)) | (eFifoSize << CANFD_RXESC_F0DS_Pos); + /*Get the RX FIFO 0 Start Address in the RAM*/ + //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32RXF0C_F0SA & CANFD_RXF0C_F0SA_Msk); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + u32Address = u32SramBaseAddr + (psRamConfig->u32RXF0C_F0SA & CANFD_RXF0C_F0SA_Msk); + u32Size = eFifoSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the RX FIFO 0 Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo0)); + } + else + { + psCanfd->RXF0C = 0; + } + + break; + + case 1: + if (psElemSize-> u32RxFifo1) + { + + /* set size of Rx FIFO 1, set offset, blocking mode */ + psCanfd->RXF1C = (psRamConfig->u32RXF1C_F1SA) | (psElemSize->u32RxFifo1 << CANFD_RXF1C_F1S_Pos) + | (u32FifoWM << CANFD_RXF1C_F1WM_Pos); + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_F1DS_Msk)) | (eFifoSize << CANFD_RXESC_F1DS_Pos); + /*Get the RX FIFO 1 Start Address in the RAM*/ + //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32RXF1C_F1SA & CANFD_RXF1C_F1SA_Msk); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + u32Address = u32SramBaseAddr + (psRamConfig->u32RXF1C_F1SA & CANFD_RXF1C_F1SA_Msk); + + u32Size = eFifoSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the RX FIFO 0 Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxFifo1)); + } + else + { + psCanfd->RXF1C = 0; + } + + break; + } +} + + +/** + * @brief Function configures the data structures used by a dedicated Rx Buffer. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Tx buffer configuration ram address. + * @param[in] psElemSize Tx buffer configuration element size. + * @param[in] eTxBufSize Maximum data field size that should be stored in a dedicated Tx Buffer + * (configure BYTE64 if you are unsure, as this is the largest data field allowed in CAN FD)largest data field allowed in CAN FD) + * + * @return None. + * + * @details Function configures the data structures used by a dedicated Rx Buffer. + */ +void CANFD_InitTxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eTxBufSize) +{ + uint32_t u32Address; + uint32_t u32Size; + uint32_t u32SramBaseAddr; + /*Setting the Tx Buffer Start Address*/ + psCanfd->TXBC = ((psElemSize->u32TxBuf & 0x3F) << CANFD_TXBC_NDTB_Pos) | (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + /*Get the TX Buffer Start Address in the RAM*/ + //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + u32Address = u32SramBaseAddr + (psRamConfig->u32TXBC_TBSA & CANFD_TXBC_TBSA_Msk); + /*Setting the Tx Buffer Data Field Size*/ + psCanfd->TXESC = (psCanfd->TXESC & (~CANFD_TXESC_TBDS_Msk)) | (eTxBufSize << CANFD_TXESC_TBDS_Pos); + /*Get the Buffer Data Field Size*/ + u32Size = eTxBufSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the TX Buffer Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32TxBuf)); +} + + +/** + * @brief Function configures the data structures used by a dedicated Rx Buffer. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Rx buffer configuration ram address. + * @param[in] psElemSize Rx buffer configuration element size. + * @param[in] eRxBufSize Maximum data field size that should be stored in a dedicated Rx Buffer + * (configure BYTE64 if you are unsure, as this is the largest data field allowed in CAN FD)largest data field allowed in CAN FD) + * + * @return None. + * + * @details Function configures the data structures used by a dedicated Rx Buffer. + */ +void CANFD_InitRxDBuf(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, E_CANFD_DATA_FIELD_SIZE eRxBufSize) +{ + uint32_t u32Address; + uint32_t u32Size; + uint32_t u32SramBaseAddr; + /*Setting the Rx Buffer Start Address*/ + psCanfd->RXBC = (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + /*Get the RX Buffer Start Address in the RAM*/ + //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + u32Address = u32SramBaseAddr + (psRamConfig->u32RXBC_RBSA & CANFD_RXBC_RBSA_Msk); + /*Setting the Rx Buffer Data Field Size*/ + psCanfd->RXESC = (psCanfd->RXESC & (~CANFD_RXESC_RBDS_Msk)) | (eRxBufSize << CANFD_RXESC_RBDS_Pos); + /*Get the Buffer Data Field Size*/ + u32Size = eRxBufSize; + + if (u32Size < 5U) + { + u32Size += 4U; + } + else + { + u32Size = u32Size * 4U - 10U; + } + + /*Clear the RX Buffer Memory*/ + memset((uint32_t *)(u32Address), 0x00, (u32Size * 4 * psElemSize->u32RxBuf)); +} + + +/** + * @brief Configures the register SIDFC for the 11-bit Standard Message ID Filter elements. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Standard ID filter configuration ram address + * @param[in] psElemSize Standard ID filter configuration element size + * + * @return None. + * + * @details Function configures the data structures used by a dedicated Rx Buffer. + */ +void CANFD_ConfigSIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) +{ + uint32_t u32Address; + uint32_t u32SramBaseAddr; + /*Setting the Filter List Standard Start Address and List Size */ + psCanfd->SIDFC = ((psElemSize->u32SIDFC & 0xFF) << CANFD_SIDFC_LSS_Pos) | (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + /*Get the Filter List Standard Start Address in the RAM*/ + //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + u32Address = u32SramBaseAddr + (psRamConfig->u32SIDFC_FLSSA & CANFD_SIDFC_FLSSA_Msk); + /*Clear the Filter List Memory*/ + memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32SIDFC * 4)); +} + + +/** + * @brief Configures the register XIDFC for the 29-bit Extended Message ID Filter elements. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Extended ID filter configuration ram address + * @param[in] psElemSize Extended ID filter configuration element size + * + * @return None. + * + * @details Configures the register XIDFC for the 29-bit Extended Message ID Filter elements. + */ +void CANFD_ConfigXIDFC(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize) +{ + uint32_t u32Address; + uint32_t u32SramBaseAddr; + /*Setting the Filter List Extended Start Address and List Size */ + psCanfd->XIDFC = ((psElemSize->u32XIDFC & 0xFF) << CANFD_XIDFC_LSE_Pos) | (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + /*Get the Filter List Standard Start Address in the RAM*/ + //u32Address = CANFD_SRAM_BASE_ADDR + (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + u32Address = u32SramBaseAddr + (psRamConfig->u32XIDFC_FLESA & CANFD_XIDFC_FLESA_Msk); + /*Clear the Filter List Memory*/ + memset((uint32_t *)(u32Address), 0x00, (psElemSize->u32XIDFC * 8)); +} + + +/** + * @brief Writes a 11-bit Standard ID filter element in the Message RAM. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32FltrIdx Index at which the filter element should be written in the '11-bit Filter' section of Message RAM + * @param[in] u32Filter Rx Individual filter value. + * + * @return None. + * + * @details Writes a 11-bit Standard ID filter element in the Message RAM. + */ +void CANFD_SetSIDFltr(CANFD_T *psCanfd, uint32_t u32FltrIdx, uint32_t u32Filter) +{ + CANFD_STD_FILTER_T *psFilter; + uint32_t u32SramBaseAddr; + + /* ignore if index is too high */ + if (u32FltrIdx >= CANFD_MAX_11_BIT_FTR_ELEMS) return; + + /*Get the Filter List Configuration Address in the RAM*/ + //psFilter = (CANFD_STD_FILTER_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->SIDFC & CANFD_SIDFC_FLSSA_Msk) + (u32FltrIdx * sizeof(CANFD_STD_FILTER_T))); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + psFilter = (CANFD_STD_FILTER_T *)(u32SramBaseAddr + (psCanfd->SIDFC & CANFD_SIDFC_FLSSA_Msk) + (u32FltrIdx * sizeof(CANFD_STD_FILTER_T))); + /*Wirted the Standard ID filter element to RAM */ + psFilter->VALUE = u32Filter; +} + + +/** + * @brief Writes a 29-bit extended id filter element in the Message RAM. + * Size of an Extended Id filter element is 2 words. So 2 words are written into the Message RAM for each filter element + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32FltrIdx Index at which the filter element should be written in the '29-bit Filter' section of Message RAM. + * @param[in] u32FilterLow Rx Individual filter low value. + * @param[in] u32FilterHigh Rx Individual filter high value. + * + * @return None. + * + * @details Writes a 29-bit extended id filter element in the Message RAM. + */ +void CANFD_SetXIDFltr(CANFD_T *psCanfd, uint32_t u32FltrIdx, uint32_t u32FilterLow, uint32_t u32FilterHigh) +{ + CANFD_EXT_FILTER_T *psFilter; + uint32_t u32SramBaseAddr; + + /* ignore if index is too high */ + if (u32FltrIdx >= CANFD_MAX_29_BIT_FTR_ELEMS) return; + + /*Get the Filter List Configuration Address on RAM*/ + //psFilter = (CANFD_EXT_FILTER_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->XIDFC & CANFD_XIDFC_FLESA_Msk) + (u32FltrIdx * sizeof(CANFD_EXT_FILTER_T))); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + psFilter = (CANFD_EXT_FILTER_T *)(u32SramBaseAddr + (psCanfd->XIDFC & CANFD_XIDFC_FLESA_Msk) + (u32FltrIdx * sizeof(CANFD_EXT_FILTER_T))); + /*Wirted the Extended ID filter element to RAM */ + psFilter->LOWVALUE = u32FilterLow; + psFilter->HIGHVALUE = u32FilterHigh; +} + + +/** + * @brief Reads a CAN FD Message from Receive Message Buffer. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u8MbIdx The CANFD Message Buffer index. + * @param[in] psMsgBuf Pointer to CAN FD message frame structure for reception. + * + * @return 1:Rx Message Buffer is full and has been read successfully. + * 0:Rx Message Buffer is empty. + * + * @details This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with just received data + * and activates the Message Buffer again.The function returns immediately. +*/ +uint32_t CANFD_ReadRxBufMsg(CANFD_T *psCanfd, uint8_t u8MbIdx, CANFD_FD_MSG_T *psMsgBuf) +{ + CANFD_BUF_T *psRxBuffer; + uint32_t u32Success = 0; + uint32_t newData = 0; + uint32_t u32SramBaseAddr; + + if (u8MbIdx < CANFD_MAX_RX_BUF_ELEMS) + { + if (u8MbIdx < 32) + newData = (psCanfd->NDAT1 >> u8MbIdx) & 1; + else + newData = (psCanfd->NDAT2 >> (u8MbIdx - 32)) & 1; + + /* new message is waiting to be read */ + if (newData) + { + /* get memory location of rx buffer */ + //psRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR + (psCanfd->RXBC & 0xFFFF) + (u8MbIdx * sizeof(CANFD_BUF_T))); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + psRxBuffer = (CANFD_BUF_T *)(u32SramBaseAddr + (psCanfd->RXBC & 0xFFFF) + (u8MbIdx * sizeof(CANFD_BUF_T))); + + /* read the message */ + CANFD_CopyDBufToMsgBuf(psRxBuffer, psMsgBuf); + + /* clear 'new data' flag */ + if (u8MbIdx < 32) + psCanfd->NDAT1 |= (1UL << u8MbIdx); + else + psCanfd->NDAT2 |= (1UL << (u8MbIdx - 32)); + + u32Success = 1; + } + } + + return u32Success; +} + + +/** + * @brief Reads a CAN FD Message from Rx FIFO. + * + * @param[in] psCanfd The pointer of the specified CANFD module. + * @param[in] u8FifoIdx Number of the FIFO, 0 or 1. + * @param[in] psMsgBuf Pointer to CANFD message frame structure for reception. + * + * @return 1 Read Message from Rx FIFO successfully. + * 2 Rx FIFO is already overflowed and has been read successfully + * 0 Rx FIFO is not enabled. + * + * @details This function reads a CAN message from the CANFD build-in Rx FIFO. + */ +uint32_t CANFD_ReadRxFifoMsg(CANFD_T *psCanfd, uint8_t u8FifoIdx, CANFD_FD_MSG_T *psMsgBuf) +{ + CANFD_BUF_T *pRxBuffer; + uint8_t GetIndex; + uint32_t u32Success = 0; + __I uint32_t *pRXFS; + __IO uint32_t *pRXFC, *pRXFA; + uint8_t msgLostBit; + uint32_t u32SramBaseAddr; + + /* check for valid FIFO number */ + if (u8FifoIdx < CANFD_NUM_RX_FIFOS) + { + if (u8FifoIdx == 0) + { + pRXFS = &(psCanfd->RXF0S); + pRXFC = &(psCanfd->RXF0C); + pRXFA = &(psCanfd->RXF0A); + msgLostBit = 3; + } + else + { + pRXFS = &(psCanfd->RXF1S); + pRXFC = &(psCanfd->RXF1C); + pRXFA = &(psCanfd->RXF1A); + msgLostBit = 7; + } + + /* if FIFO is not empty */ + if ((*pRXFS & 0x7F) > 0) + { + GetIndex = (uint8_t)((*pRXFS >> 8) & 0x3F); + //pRxBuffer = (CANFD_BUF_T *)(CANFD_SRAM_BASE_ADDR + (*pRXFC & 0xFFFF) + (GetIndex * sizeof(CANFD_BUF_T))); + u32SramBaseAddr = _GetCanfdSramBaseAddr(psCanfd); + pRxBuffer = (CANFD_BUF_T *)(u32SramBaseAddr + (*pRXFC & 0xFFFF) + (GetIndex * sizeof(CANFD_BUF_T))); + + CANFD_CopyRxFifoToMsgBuf(pRxBuffer, psMsgBuf); + /* we got the message */ + *pRXFA = GetIndex; + + /* check for overflow */ + if (*pRXFS & CANFD_RXFS_RFL) + { + /* clear overflow flag */ + psCanfd->IR = (1UL << msgLostBit); + u32Success = 2; + } + else + { + u32Success = 1; + } + } + } + + return u32Success; +} + + +/** + * @brief Copies a message from a dedicated Rx buffer into a message buffer. + * + * @param[in] psRxBuf Buffer to read from. + * @param[in] psMsgBuf Location to store read message. + * + * @return None. + * + * @details Copies a message from a dedicated Rx buffer into a message buffer. + */ +void CANFD_CopyDBufToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf) +{ + uint32_t u32Idx; + + if (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_ESI_Msk) + psMsgBuf->bErrStaInd = TRUE; + else + psMsgBuf->bErrStaInd = FALSE; + + /* if 29-bit ID */ + if (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_XTD_Msk) + { + psMsgBuf->u32Id = (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_ID_Msk); + psMsgBuf->eIdType = eCANFD_XID; + } + /* if 11-bit ID */ + else + { + psMsgBuf->u32Id = (psRxBuf->u32Id >> 18) & 0x7FF; + psMsgBuf->eIdType = eCANFD_SID; + } + + if (psRxBuf->u32Id & RX_BUFFER_AND_FIFO_R0_ELEM_RTR_Msk) + psMsgBuf->eFrmType = eCANFD_REMOTE_FRM; + else + psMsgBuf->eFrmType = eCANFD_DATA_FRM; + + + if (psRxBuf->u32Config & RX_BUFFER_AND_FIFO_R1_ELEM_FDF_Msk) + psMsgBuf->bFDFormat = TRUE; + else + psMsgBuf->bFDFormat = FALSE; + + if (psRxBuf->u32Config & RX_BUFFER_AND_FIFO_R1_ELEM_BSR_Msk) + psMsgBuf->bBitRateSwitch = TRUE; + else + psMsgBuf->bBitRateSwitch = FALSE; + + psMsgBuf->u32DLC = CANFD_DecodeDLC((psRxBuf->u32Config & RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Msk) >> RX_BUFFER_AND_FIFO_R1_ELEM_DLC_Pos); + + for (u32Idx = 0 ; u32Idx < psMsgBuf->u32DLC ; u32Idx++) + { + psMsgBuf->au8Data[u32Idx] = psRxBuf->au8Data[u32Idx]; + } +} + + +/** + * @brief Get Rx FIFO water level. + * + * @param[in] psCanfd The pointer to CANFD module base address. + * @param[in] u32RxFifoNum 0: RX FIFO_0, 1: RX_FIFO_1 + * + * @return Rx FIFO water level. + * + * @details Get Rx FIFO water level. + */ +uint32_t CANFD_GetRxFifoWaterLvl(CANFD_T *psCanfd, uint32_t u32RxFifoNum) +{ + uint32_t u32WaterLevel = 0; + + if (u32RxFifoNum == 0) + u32WaterLevel = ((psCanfd->RXF0C & CANFD_RXF0C_F0WM_Msk) >> CANFD_RXF0C_F0WM_Pos); + else + u32WaterLevel = ((psCanfd->RXF1C & CANFD_RXF1C_F1WM_Msk) >> CANFD_RXF1C_F1WM_Pos); + + return u32WaterLevel; +} + + +/** + * @brief Copies messages from FIFO into a message buffert. + * + * @param[in] psRxBuf Buffer to read from. + * @param[in] psMsgBuf Location to store read message. + * + * @return None. + * + * @details Copies messages from FIFO into a message buffert. + */ +void CANFD_CopyRxFifoToMsgBuf(CANFD_BUF_T *psRxBuf, CANFD_FD_MSG_T *psMsgBuf) +{ + /*Copies a message from a dedicated Rx FIFO into a message buffer*/ + CANFD_CopyDBufToMsgBuf(psRxBuf, psMsgBuf); +} + + +/** + * @brief Cancel a Tx buffer transmission request. + * + * @param[in] psCanfd The pointer to CANFD module base address. + * @param[in] u32TxBufIdx Tx buffer index number + * + * @return None. + * + * @details Cancel a Tx buffer transmission request. + */ +void CANFD_TxBufCancelReq(CANFD_T *psCanfd, uint32_t u32TxBufIdx) +{ + psCanfd->TXBCR |= (0x1ul << u32TxBufIdx); +} + + +/** + * @brief Checks if a Tx buffer cancellation request has been finished or not. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxBufIdx Tx buffer index number + * + * @return 0: cancellation finished. + * 1: cancellation fail + * + * @details Checks if a Tx buffer cancellation request has been finished or not. + */ +uint32_t CANFD_IsTxBufCancelFin(CANFD_T *psCanfd, uint32_t u32TxBufIdx) +{ + /* wait for completion */ + return ((psCanfd->TXBCR & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); +} + + +/** + * @brief Checks if a Tx buffer transmission has occurred or not. + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxBufIdx Tx buffer index number + * + * @return 0: No transmission occurred. + * 1: Transmission occurred + * + * @details Checks if a Tx buffer transmission has occurred or not. + */ +uint32_t CANFD_IsTxBufTransmitOccur(CANFD_T *psCanfd, uint32_t u32TxBufIdx) +{ + return ((psCanfd->TXBTO & (0x1ul << u32TxBufIdx)) >> u32TxBufIdx); +} + + +/** + * @brief Init Tx event fifo + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] psRamConfig Tx Event Fifo configuration ram address. + * @param[in] psElemSize Tx Event Fifo configuration element size + * @param[in] u32FifoWaterLvl FIFO water level + * + * @return None. + * + * @details Init Tx event fifo. + */ +void CANFD_InitTxEvntFifo(CANFD_T *psCanfd, CANFD_RAM_PART_T *psRamConfig, CANFD_ELEM_SIZE_T *psElemSize, uint32_t u32FifoWaterLvl) +{ + /* Set TX Event FIFO element size,watermark,start address. */ + psCanfd->TXEFC = (u32FifoWaterLvl << CANFD_TXEFC_EFWN_Pos) | (psElemSize->u32TxEventFifo << CANFD_TXEFC_EFS_Pos) + | (psRamConfig->u32TXEFC_EFSA & CANFD_TXEFC_EFSA_Msk); +} + + +/** + * @brief Get Tx event fifo water level + * + * @param[in] psCanfd The pointer to CANFD module base address. + * + * @return Tx event fifo water level. + * + * @details Get Tx event fifo water level. + */ +uint32_t CANFD_GetTxEvntFifoWaterLvl(CANFD_T *psCanfd) +{ + return ((psCanfd->TXEFC & CANFD_TXEFC_EFWN_Msk) >> CANFD_TXEFC_EFWN_Pos); +} + + +/** + * @brief Copy Event Elements from TX Event FIFO to user buffer + * + * @param[in] psCanfd The pointer to CAN FD module base address. + * @param[in] u32TxEvntNum Tx Event FIFO number + * @param[in] psTxEvntElem Tx Event Message struct + * + * @return None. + * + * @details Copy all Event Elements from TX Event FIFO to the Software Event List . + */ +void CANFD_CopyTxEvntFifoToUsrBuf(CANFD_T *psCanfd, uint32_t u32TxEvntNum, CANFD_TX_EVNT_ELEM_T *psTxEvntElem) +{ + uint32_t *pu32TxEvnt; + /*Get the Tx Event FIFO Address*/ + pu32TxEvnt = (uint32_t *)CANFD_GetTxBufferElementAddress(psCanfd, u32TxEvntNum); + + /*Get the Error State Indicator*/ + if ((pu32TxEvnt[0] & TX_FIFO_E0_EVENT_ESI_Msk) > 0) + psTxEvntElem->bErrStaInd = TRUE; //Transmitting node is error passive + else + psTxEvntElem->bErrStaInd = FALSE;//Transmitting node is error active + + /*Get the Tx FIFO Identifier type and Identifier*/ + + if ((pu32TxEvnt[0] & TX_FIFO_E0_EVENT_XTD_Msk) > 0) + { + psTxEvntElem-> eIdType = eCANFD_XID; + psTxEvntElem->u32Id = (pu32TxEvnt[0] & TX_FIFO_E0_EVENT_ID_Msk);// Extended ID + } + else + { + psTxEvntElem-> eIdType = eCANFD_SID; + psTxEvntElem->u32Id = (pu32TxEvnt[0] & TX_FIFO_E0_EVENT_ID_Msk) >> 18;// Standard ID + } + + /*Get the Frame type*/ + if ((pu32TxEvnt[0] & TX_FIFO_E0_EVENT_RTR_Msk) > 0) + psTxEvntElem->bRemote = TRUE; //Remote frame + else + psTxEvntElem->bRemote = FALSE; //Data frame + + /*Get the FD Format type*/ + if ((pu32TxEvnt[0] & TX_FIFO_E1_EVENT_FDF_Msk) > 0) + psTxEvntElem->bFDFormat = TRUE; //CAN FD frame format + else + psTxEvntElem->bFDFormat = FALSE; //Classical CAN frame format + + /*Get the Bit Rate Switch type*/ + if ((pu32TxEvnt[0] & TX_FIFO_E1_EVENT_BRS_Msk) > 0) + psTxEvntElem->bBitRateSwitch = TRUE; //Frame transmitted with bit rate switching + else + psTxEvntElem->bBitRateSwitch = FALSE; //Frame transmitted without bit rate switching + + /*Get the Tx FIFO Data Length */ + psTxEvntElem->u32DLC = CANFD_DecodeDLC((uint8_t)((pu32TxEvnt[1] & TX_FIFO_E1_EVENT_DLC_Msk) >> TX_FIFO_E1_EVENT_DLC_Pos)); + + /*Get the Tx FIFO Timestamp */ + psTxEvntElem->u32TxTs = (((pu32TxEvnt[1] & TX_FIFO_E1A_EVENT_TXTS_Msk) >> TX_FIFO_E1A_EVENT_TXTS_Pos)); + /*Get the Tx FIFO Message marker */ + psTxEvntElem->u32MsgMarker = (((pu32TxEvnt[1] & TX_FIFO_E1_EVENT_MM_Msk) >> TX_FIFO_E1_EVENT_MM_Pos)); +} + + +/** + * @brief Get CAN FD interrupts status. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref CANFD_IR_ARA_Msk : Access to Reserved Address interrupt Indicator + * - \ref CANFD_IR_PED_Msk : Protocol Error in Data Phase interrupt Indicator + * - \ref CANFD_IR_PEA_Msk : Protocol Error in Arbitration Phase interrupt Indicator + * - \ref CANFD_IR_WDI_Msk : Watchdog interrupt Indicator + * - \ref CANFD_IR_BO_Msk : Bus_Off Status interrupt Indicator + * - \ref CANFD_IR_EW_Msk : Warning Status interrupt Indicator + * - \ref CANFD_IR_EP_Msk : Error Passive interrupt Indicator + * - \ref CANFD_IR_ELO_Msk : Error Logging Overflow interrupt Indicator + * - \ref CANFD_IR_DRX_Msk : Message stored to Dedicated Rx Buffer interrupt Indicator + * - \ref CANFD_IR_TOO_Msk : Timeout Occurred interrupt Indicator + * - \ref CANFD_IR_MRAF_Msk : Message RAM Access Failure interrupt Indicator + * - \ref CANFD_IR_TSW_Msk : Timestamp Wraparound interrupt Indicator + * - \ref CANFD_IR_TEFL_Msk : Tx Event FIFO Event Lost interrupt Indicator + * - \ref CANFD_IR_TEFF_Msk : Tx Event FIFO Full Indicator + * - \ref CANFD_IR_TEFW_Msk : Tx Event FIFO Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_TEFN_Msk : Tx Event FIFO New Entry Interrupt Indicator + * - \ref CANFD_IR_TFE_Msk : Tx FIFO Empty Interrupt Indicator + * - \ref CANFD_IR_TCF_Msk : Transmission Cancellation Finished Interrupt Indicator + * - \ref CANFD_IR_TC_Msk : Transmission Completed interrupt Indicator + * - \ref CANFD_IR_HPM_Msk : High Priority Message Interrupt Indicator + * - \ref CANFD_IR_RF1L_Msk : Rx FIFO 1 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF1F_Msk : Rx FIFO 1 Full Interrupt Indicator + * - \ref CANFD_IR_RF1W_Msk : Rx FIFO 1 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF1N_Msk : Rx FIFO 1 New Message Interrupt Indicator + * - \ref CANFD_IR_RF0L_Msk : Rx FIFO 0 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF0F_Msk : Rx FIFO 0 Full Interrupt Indicator + * - \ref CANFD_IR_RF0W_Msk : Rx FIFO 0 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF0N_Msk : Rx FIFO 0 New Message Interrupt Indicator + * + * @return None. + * + * @details This function gets all CAN FD interrupt status flags. + */ +uint32_t CANFD_GetStatusFlag(CANFD_T *psCanfd, uint32_t u32IntTypeFlag) +{ + return (psCanfd->IR & u32IntTypeFlag); +} + + +/** + * @brief Clears the CAN FD module interrupt flags + * + * @param[in] psCanfd The pointer of the specified CANFD module. + * @param[in] u32InterruptFlag The specified interrupt of CAN FD module + * - \ref CANFD_IR_ARA_Msk : Access to Reserved Address interrupt Indicator + * - \ref CANFD_IR_PED_Msk : Protocol Error in Data Phase interrupt Indicator + * - \ref CANFD_IR_PEA_Msk : Protocol Error in Arbitration Phase interrupt Indicator + * - \ref CANFD_IR_WDI_Msk : Watchdog interrupt Indicator + * - \ref CANFD_IR_BO_Msk : Bus_Off Status interrupt Indicator + * - \ref CANFD_IR_EW_Msk : Warning Status interrupt Indicator + * - \ref CANFD_IR_EP_Msk : Error Passive interrupt Indicator + * - \ref CANFD_IR_ELO_Msk : Error Logging Overflow interrupt Indicator + * - \ref CANFD_IR_DRX_Msk : Message stored to Dedicated Rx Buffer interrupt Indicator + * - \ref CANFD_IR_TOO_Msk : Timeout Occurred interrupt Indicator + * - \ref CANFD_IR_MRAF_Msk : Message RAM Access Failure interrupt Indicator + * - \ref CANFD_IR_TSW_Msk : Timestamp Wraparound interrupt Indicator + * - \ref CANFD_IR_TEFL_Msk : Tx Event FIFO Event Lost interrupt Indicator + * - \ref CANFD_IR_TEFF_Msk : Tx Event FIFO Full Indicator + * - \ref CANFD_IR_TEFW_Msk : Tx Event FIFO Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_TEFN_Msk : Tx Event FIFO New Entry Interrupt Indicator + * - \ref CANFD_IR_TFE_Msk : Tx FIFO Empty Interrupt Indicator + * - \ref CANFD_IR_TCF_Msk : Transmission Cancellation Finished Interrupt Indicator + * - \ref CANFD_IR_TC_Msk : Transmission Completed interrupt Indicator + * - \ref CANFD_IR_HPM_Msk : High Priority Message Interrupt Indicator + * - \ref CANFD_IR_RF1L_Msk : Rx FIFO 1 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF1F_Msk : Rx FIFO 1 Full Interrupt Indicator + * - \ref CANFD_IR_RF1W_Msk : Rx FIFO 1 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF1N_Msk : Rx FIFO 1 New Message Interrupt Indicator + * - \ref CANFD_IR_RF0L_Msk : Rx FIFO 0 Message Lost Interrupt Indicator + * - \ref CANFD_IR_RF0F_Msk : Rx FIFO 0 Full Interrupt Indicator + * - \ref CANFD_IR_RF0W_Msk : Rx FIFO 0 Watermark Reached Interrupt Indicator + * - \ref CANFD_IR_RF0N_Msk : Rx FIFO 0 New Message Interrupt Indicator + * + * @return None. + * + * @details This function clears CAN FD interrupt status flags. + */ +void CANFD_ClearStatusFlag(CANFD_T *psCanfd, uint32_t u32InterruptFlag) +{ + /* Write 1 to clear status flag. */ + psCanfd->IR |= u32InterruptFlag; +} + + +/** + * @brief Gets the CAN FD Bus Error Counter value. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] pu8TxErrBuf TxErrBuf Buffer to store Tx Error Counter value. + * @param[in] pu8RxErrBuf RxErrBuf Buffer to store Rx Error Counter value. + * + * @return None. + * + * @details This function gets the CAN FD Bus Error Counter value for both Tx and Rx direction. + * These values may be needed in the upper layer error handling. + */ +void CANFD_GetBusErrCount(CANFD_T *psCanfd, uint8_t *pu8TxErrBuf, uint8_t *pu8RxErrBuf) +{ + if (pu8TxErrBuf) + { + *pu8TxErrBuf = (uint8_t)((psCanfd->ECR >> CANFD_ECR_TEC_Pos) & CANFD_ECR_TEC_Msk); + } + + if (pu8RxErrBuf) + { + *pu8RxErrBuf = (uint8_t)((psCanfd->ECR >> CANFD_ECR_REC_Pos) & CANFD_ECR_REC_Msk); + } +} + + +/** + * @brief CAN FD Run to the Normal Operation. + * + * @param[in] psCanfd The pointer of the specified CAN FD module. + * @param[in] u8Enable TxErrBuf Buffer to store Tx Error Counter value. + * + * @return None. + * + * @details This function gets the CAN FD Bus Error Counter value for both Tx and Rx direction. + * These values may be needed in the upper layer error handling. + * + * @note This function sets g_CANFD_i32ErrCode to CANFD_TIMEOUT_ERR if waiting CANFD time-out. + */ +void CANFD_RunToNormal(CANFD_T *psCanfd, uint8_t u8Enable) +{ + uint32_t u32TimeOutCount = CANFD_TIMEOUT; + + g_CANFD_i32ErrCode = 0; + + if (u8Enable) + { + /* start operation */ + psCanfd->CCCR &= ~(CANFD_CCCR_CCE_Msk | CANFD_CCCR_INIT_Msk); + + while (psCanfd->CCCR & CANFD_CCCR_INIT_Msk) + { + if(u32TimeOutCount-- == 0) + { + g_CANFD_i32ErrCode = CANFD_TIMEOUT_ERR; + break; + } + } + } + else + { + /* init mode */ + psCanfd->CCCR |= CANFD_CCCR_INIT_Msk; + + while (!(psCanfd->CCCR & CANFD_CCCR_INIT_Msk)) + { + if(u32TimeOutCount-- == 0) + { + g_CANFD_i32ErrCode = CANFD_TIMEOUT_ERR; + break; + } + } + } +} + + + +/*@}*/ /* end of group CANFD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CANFD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ccap.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ccap.c new file mode 100644 index 0000000..50c5d9d6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ccap.c @@ -0,0 +1,307 @@ +/**************************************************************************//** + * @file ccap.c + * @version V3.00 + * @brief M460 Series CCAP Driver Source File + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CCAP_Driver CCAP Driver + @{ +*/ + +int32_t g_CCAP_i32ErrCode = 0; /*!< CCAP global error code */ + +/** @addtogroup CCAP_EXPORTED_FUNCTIONS CCAP Exported Functions + @{ +*/ + +/** + * @brief Open and set CCAP function + * + * @param[in] u32InFormat The bits corresponding VSP, HSP, PCLK, INFMT, SNRTYPE, OUTFMT and PDORD configurations. + * - VSP Sensor Vsync Polarity. It should be either \ref CCAP_PAR_VSP_LOW or \ref CCAP_PAR_VSP_HIGH + * - HSP Sensor Hsync Polarity. It should be either \ref CCAP_PAR_HSP_LOW or \ref CCAP_PAR_HSP_HIGH + * - PCLK Sensor Pixel Clock Polarity. It should be either \ref CCAP_PAR_PCLKP_LOW or \ref CCAP_PAR_PCLKP_HIGH + * - INFMT Sensor Input Data Format. It should be either \ref CCAP_PAR_INFMT_YUV422 or \ref CCAP_PAR_INFMT_RGB565 + * - SNRTYPE Sensor Input Type. It should be either \ref CCAP_PAR_SENTYPE_CCIR601 or \ref CCAP_PAR_SENTYPE_CCIR656 + * - OUTFMT Image Data Format Output to System Memory. It should be one of the following settings + * - \ref CCAP_PAR_OUTFMT_YUV422 + * - \ref CCAP_PAR_OUTFMT_ONLY_Y + * - \ref CCAP_PAR_OUTFMT_RGB555 + * - \ref CCAP_PAR_OUTFMT_RGB565 + * - PDORD Sensor Input Data Order. It should be one of the following settings + * - \ref CCAP_PAR_INDATORD_YUYV + * - \ref CCAP_PAR_INDATORD_YVYU + * - \ref CCAP_PAR_INDATORD_UYVY + * - \ref CCAP_PAR_INDATORD_VYUY + * - \ref CCAP_PAR_INDATORD_RGGB + * - \ref CCAP_PAR_INDATORD_BGGR + * - \ref CCAP_PAR_INDATORD_GBRG + * - \ref CCAP_PAR_INDATORD_GRBG + * @param[in] u32OutFormat Image Data Output Format. It should be + * - \ref CCAP_CTL_PKTEN + * + * @return None + * + * @details Initialize the Camera Capture Interface. + */ +void CCAP_Open(uint32_t u32InFormat, uint32_t u32OutFormat) +{ + CCAP->PAR = (CCAP->PAR & ~(0x000007BFUL)) | u32InFormat; + CCAP->CTL = (CCAP->CTL & ~(0x00000040UL)) | u32OutFormat; +} + +/** + * @brief Set Cropping Window Starting Address and Size + * + * @param[in] u32VStart: Cropping Window Vertical Starting Address. It should be 0 ~ 0x7FF. + * @param[in] u32HStart: Cropping Window Horizontal Starting Address. It should be 0 ~ 0x7FF. + * @param[in] u32Height: Cropping Window Height. It should be 0 ~ 0x7FF. + * @param[in] u32Width: Cropping Window Width. It should be 0 ~ 0x7FF. + * + * @return None + * + * @details This function is used to set cropping window starting address and size. + */ +void CCAP_SetCroppingWindow(uint32_t u32VStart, uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width) +{ + CCAP->CWSP = (CCAP->CWSP & ~(CCAP_CWSP_CWSADDRV_Msk | CCAP_CWSP_CWSADDRH_Msk)) + | (((u32VStart << 16) | u32HStart)); + + CCAP->CWS = (CCAP->CWS & ~(CCAP_CWS_CWH_Msk | CCAP_CWS_CWW_Msk)) + | ((u32Height << 16)| u32Width); +} + +/** + * @brief Set System Memory Packet Base Address + * + * @param[in] u32Address: Set CCAP_PKTBA0 register. It should be 0x0 ~ 0xFFFFFFFF. + * + * @return None + * + * @details This function is used to set System Memory Packet Base Address 0 Register. + */ +void CCAP_SetPacketBuf(uint32_t u32Address) +{ + CCAP->PKTBA0 = u32Address; + CCAP->CTL |= CCAP_CTL_UPDATE_Msk; +} + +/** + * @brief Close Camera Capture Interface + * + * @param None + * + * @return None + * + * @details This function is used to disable Camera Capture Interface. + */ +void CCAP_Close(void) +{ + CCAP->CTL &= ~CCAP_CTL_CCAPEN; +} + +/** + * @brief Enable CCAP Interrupt + * + * @param[in] u32IntMask Interrupt settings. It could be + * - \ref CCAP_INT_VIEN_Msk + * - \ref CCAP_INT_MEIEN_Msk + * - \ref CCAP_INT_ADDRMIEN_Msk + * + * @return None + * + * @details This function is used to enable Video Frame End Interrupt, + * Bus Master Transfer Error Interrupt and Memory Address Match Interrupt. + */ +void CCAP_EnableInt(uint32_t u32IntMask) +{ + CCAP->INT = (CCAP->INT & ~(CCAP_INT_VIEN_Msk | CCAP_INT_MEIEN_Msk | CCAP_INT_ADDRMIEN_Msk ) ) + | u32IntMask; +} + +/** + * @brief Disable CCAP Interrupt + * + * @param[in] u32IntMask Interrupt settings. It could be + * - \ref CCAP_INT_VINTF_Msk + * - \ref CCAP_INT_MEINTF_Msk + * - \ref CCAP_INT_ADDRMINTF_Msk + * + * @return None + * + * @details This function is used to disable Video Frame End Interrupt, + * Bus Master Transfer Error Interrupt and Memory Address Match Interrupt. + */ +void CCAP_DisableInt(uint32_t u32IntMask) +{ + CCAP->INT = (CCAP->INT & ~(u32IntMask)); +} + +/** + * @brief Enable Monochrome CMOS Sensor + * + * @param[in] u32Interface Data I/O interface setting. It could be + * - \ref CCAP_CTL_MY8_MY4 + * - \ref CCAP_CTL_MY8_MY8 + * @return None + * + * @details This function is used to select monochrome CMOS sensor and set data width. + */ +void CCAP_EnableMono(uint32_t u32Interface) +{ + CCAP->CTL = (CCAP->CTL & ~CCAP_CTL_MY8_MY4) | CCAP_CTL_MONO_Msk |u32Interface; +} + +/** + * @brief Disable Monochrome CMOS Sensor + * + * @param None + * + * @return None + * + * @details This function is used to disable monochrome CMOS sensor selection. + */ +void CCAP_DisableMono(void) +{ + CCAP->CTL &= ~CCAP_CTL_MONO_Msk; +} + +/** + * @brief Enable Luminance 8-bit Y to 1-bit Y Conversion + * + * @param[in] u32th Luminance Y8 to Y1 Threshold Value. It should be 0 ~ 255. + * + * @return None + * + * @details This function is used to enable luminance Y8 to Y1 function and set its threshold value. + */ +void CCAP_EnableLumaYOne(uint32_t u32th) +{ + CCAP->CTL |= CCAP_CTL_Luma_Y_One_Msk; + CCAP->LUMA_Y1_THD = u32th & 0xff; +} + +/** + * @brief Disable Luminance 8-bit Y to 1-bit Y Conversion + * + * @param None + * + * @return None + * + * @details This function is used to disable luminance Y8 to Y1 function. + * + */ +void CCAP_DisableLumaYOne(void) +{ + CCAP->CTL &= ~CCAP_CTL_Luma_Y_One_Msk; +} + +/** + * @brief Start Camera Capture Interface + * + * @param None + * + * @return None + * + * @details This function is used to start Camera Capture Interface function. + */ +void CCAP_Start(void) +{ + CCAP->CTL |= CCAP_CTL_CCAPEN; +} + +/** + * @brief Stop Camera Capture Interface + * + * @param[in] u32FrameComplete: + * - \ref TRUE: Capture module disables the CCAP module automatically after a frame had been captured. + * - \ref FALSE: Stop Capture module now. + * + * @return None + * + * @details If u32FrameComplete is set to TRUE then get a new frame and disable CCAP module. + * + * @note This function sets g_CCAP_i32ErrCode to CCAP_TIMEOUT_ERR if the CCAP_IS_STOPPED() longer than expected. + */ +void CCAP_Stop(uint32_t u32FrameComplete) +{ + uint32_t u32TimeOutCount = SystemCoreClock<<1; /* 2 second */ + + if(u32FrameComplete==FALSE) + CCAP->CTL &= ~CCAP_CTL_CCAPEN; + else + { + CCAP->CTL |= CCAP_CTL_SHUTTER_Msk; + while(!CCAP_IS_STOPPED()) + { + if(--u32TimeOutCount == 0){ + g_CCAP_i32ErrCode = CCAP_TIMEOUT_ERR; + break; + } + } + } +} + +/** + * @brief Set Packet Scaling Factor + * + * @param[in] u32VNumerator: Packet Scaling Vertical Factor N. It should be 0x0 ~ 0xFFFF. + * @param[in] u32VDenominator: Packet Scaling Vertical Factor M. It should be 0x0 ~ 0xFFFF. + * @param[in] u32HNumerator: Packet Scaling Horizontal Factor N. It should be 0x0 ~ 0xFFFF. + * @param[in] u32HDenominator: Packet Scaling Horizontal Factor M. It should be 0x0 ~ 0xFFFF. + * + * @return None + * + * @details This function is used to set Packet Scaling Vertical and Horizontal Factor register. + */ +void CCAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator) +{ + uint32_t u32NumeratorL, u32NumeratorH; + uint32_t u32DenominatorL, u32DenominatorH; + + u32NumeratorL = u32VNumerator&0xFF; + u32NumeratorH = u32VNumerator>>8; + u32DenominatorL = u32VDenominator&0xFF; + u32DenominatorH = u32VDenominator>>8; + CCAP->PKTSL = (CCAP->PKTSL & ~(CCAP_PKTSL_PKTSVNL_Msk | CCAP_PKTSL_PKTSVML_Msk)) + | ((u32NumeratorL << 24)| (u32DenominatorL << 16)); + CCAP->PKTSM = (CCAP->PKTSM & ~(CCAP_PKTSM_PKTSVNH_Msk | CCAP_PKTSM_PKTSVMH_Msk)) + | ((u32NumeratorH << 24) | (u32DenominatorH << 16)); + + u32NumeratorL = u32HNumerator&0xFF; + u32NumeratorH = u32HNumerator>>8; + u32DenominatorL = u32HDenominator&0xFF; + u32DenominatorH = u32HDenominator>>8; + CCAP->PKTSL = (CCAP->PKTSL & ~(CCAP_PKTSL_PKTSHNL_Msk | CCAP_PKTSL_PKTSHML_Msk)) + | ((u32NumeratorL << 8)| u32DenominatorL); + CCAP->PKTSM = (CCAP->PKTSM & ~(CCAP_PKTSM_PKTSHNH_Msk | CCAP_PKTSM_PKTSHMH_Msk)) + | ((u32NumeratorH << 8) | u32DenominatorH); +} + +/** + * @brief Set Packet Frame Output Pixel Stride Width + * + * @param[in] u32Stride: Set CCAP_STRIDE register. It should be 0x0 ~ 0x3FFF. + * + * @return None + * + * @details This function is used to set Packet Frame Output Pixel Stride Width. + */ +void CCAP_SetPacketStride(uint32_t u32Stride ) +{ + CCAP->STRIDE = (CCAP->STRIDE & ~CCAP_STRIDE_PKTSTRIDE_Msk) | u32Stride; +} + +/*@}*/ /* end of group CCAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CCAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_clk.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_clk.c new file mode 100644 index 0000000..a88a241 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_clk.c @@ -0,0 +1,1798 @@ +/**************************************************************************//** + * @file clk.c + * @version V3.00 + * @brief M460 series CLK driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +int32_t g_CLK_i32ErrCode = 0; /*!< CLK global error code */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable clock divider output function + * @param None + * @return None + * @details This function disable clock divider output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); +} + +/** + * @brief This function enable clock divider output module clock, + * enable clock divider output function and set frequency selection. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL1_CLKOSEL_HXT + * - \ref CLK_CLKSEL1_CLKOSEL_LXT + * - \ref CLK_CLKSEL1_CLKOSEL_HCLK + * - \ref CLK_CLKSEL1_CLKOSEL_HIRC + * - \ref CLK_CLKSEL1_CLKOSEL_LIRC + * - \ref CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2 + * - \ref CLK_CLKSEL1_CLKOSEL_PLL_DIV2 + * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15. + * @param[in] u32ClkDivBy1En is clock divided by one enabled. + * @return None + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n + * The formula is: \n + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. \n + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; + + /* Select CKO clock source */ + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc); +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + volatile uint32_t u32SysTickTICKINT = 0, u32HIRCTCTL = 0, u32IRCTCTL = 0; + + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled */ + CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk); + + /* Store Systick interrupt and HIRC auto trim setting */ + u32SysTickTICKINT = SysTick->CTRL & SysTick_CTRL_TICKINT_Msk; + u32HIRCTCTL = SYS->HIRCTCTL; + u32IRCTCTL = SYS->IRCTCTL; + + /* Disable Systick interrupt and HIRC auto trim */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + SYS->HIRCTCTL &= (~SYS_HIRCTCTL_FREQSEL_Msk); + SYS->IRCTCTL &= (~SYS_IRCTCTL_FREQSEL_Msk); + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); + + /* Restore Systick interrupt and HIRC auto trim setting */ + if(u32SysTickTICKINT) SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + SYS->HIRCTCTL = u32HIRCTCTL; + SYS->IRCTCTL = u32IRCTCTL; +} + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHXTFreq(void) +{ + uint32_t u32Freq; + + if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) + { + u32Freq = __HXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetLXTFreq(void) +{ + uint32_t u32Freq; + + if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) + { + u32Freq = __LXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + +/** + * @brief Get PCLK0 frequency + * @param None + * @return PCLK0 frequency + * @details This function get PCLK0 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK0Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + + if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV2) + { + u32Freq = SystemCoreClock>>1; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV4) + { + u32Freq = SystemCoreClock>>2; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV8) + { + u32Freq = SystemCoreClock>>3; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_APB0DIV_DIV16) + { + u32Freq = SystemCoreClock>>4; + } + else + { + u32Freq = SystemCoreClock; + } + + return u32Freq; +} + + +/** + * @brief Get PCLK1 frequency + * @param None + * @return PCLK1 frequency + * @details This function get PCLK1 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK1Freq(void) +{ + uint32_t u32Freq; + SystemCoreClockUpdate(); + + if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV1) + { + u32Freq = SystemCoreClock; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV2) + { + u32Freq = SystemCoreClock>>1; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV4) + { + u32Freq = SystemCoreClock>>2; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV8) + { + u32Freq = SystemCoreClock>>3; + } + else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_APB1DIV_DIV16) + { + u32Freq = SystemCoreClock>>4; + } + else + { + u32Freq = SystemCoreClock; + } + + return u32Freq; +} + + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCPUFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 50MHz ~ 200MHz. + * @return HCLK frequency + * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n + * Power level and flash access cycle are also set according to HCLK frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Check HCLK frequency range is 50MHz ~ 200MHz */ + if(u32Hclk > FREQ_200MHZ) + { + u32Hclk = FREQ_200MHZ; + } + else if(u32Hclk < FREQ_50MHZ) + { + u32Hclk = FREQ_50MHZ; + } + + /* Switch HCLK clock source to HIRC clock for safe */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); + + /* Configure PLL setting if HXT clock is stable */ + if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk) + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); + } + /* Configure PLL setting if HXT clock is not stable */ + else + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + } + + /* Select HCLK clock source to PLL, + select HCLK clock source divider as 1, + and update system core clock + */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } + + /* Return actually HCLK frequency is PLL frequency divide 1 */ + return u32Hclk; +} + +/** + * @brief Set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. \n + * Power level and flash access cycle are also set according to HCLK operation frequency. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + uint32_t u32TimeOutCount = 0; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Switch to HIRC for safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + + /* Switch to power level 0 for safe */ + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL0; + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk) + { + if(u32TimeOutCount-- == 0) break; + } + + /* Set Flash Access Cycle to 8 for safe */ + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (8); + + /* Apply new Divider */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Set power level according to new HCLK */ + if(SystemCoreClock <= FREQ_180MHZ) + { + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL1; + } + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk) + { + if(u32TimeOutCount-- == 0) break; + } + + /* Switch flash access cycle to suitable value base on HCLK */ + if (SystemCoreClock >= FREQ_175MHZ) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (8); + } + else if (SystemCoreClock >= FREQ_150MHZ) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (7); + } + else if (SystemCoreClock >= FREQ_125MHZ) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (6); + } + else if (SystemCoreClock >= FREQ_100MHZ) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (5); + } + else if (SystemCoreClock >= FREQ_75MHZ) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (4); + } + else if (SystemCoreClock >= FREQ_50MHZ) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (3); + } + else if (SystemCoreClock >= FREQ_25MHZ) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (2); + } + else /* SystemCoreClock < FREQ_25MHZ */ + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (1); + } + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :----------------------------------- | :-------------------------- | + * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48M |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL_DIV2 |\ref CLK_CLKDIV0_USB(x) | + * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48M |\ref CLK_CLKDIV0_USB(x) | + * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL_DIV2 |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48M |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL_DIV2 |\ref CLK_CLKDIV0_USB(x) | + * |\ref EADC0_MODULE |\ref CLK_CLKSEL0_EADC0SEL_PLLFN_DIV2 |\ref CLK_CLKDIV0_EADC0(x) | + * |\ref EADC0_MODULE |\ref CLK_CLKSEL0_EADC0SEL_PLL_DIV2 |\ref CLK_CLKDIV0_EADC0(x) | + * |\ref EADC0_MODULE |\ref CLK_CLKSEL0_EADC0SEL_HCLK |\ref CLK_CLKDIV0_EADC0(x) | + * |\ref EADC1_MODULE |\ref CLK_CLKSEL0_EADC1SEL_PLLFN_DIV2 |\ref CLK_CLKDIV2_EADC1(x) | + * |\ref EADC1_MODULE |\ref CLK_CLKSEL0_EADC1SEL_PLL_DIV2 |\ref CLK_CLKDIV2_EADC1(x) | + * |\ref EADC1_MODULE |\ref CLK_CLKSEL0_EADC1SEL_HCLK |\ref CLK_CLKDIV2_EADC1(x) | + * |\ref EADC2_MODULE |\ref CLK_CLKSEL0_EADC2SEL_PLLFN_DIV2 |\ref CLK_CLKDIV5_EADC2(x) | + * |\ref EADC2_MODULE |\ref CLK_CLKSEL0_EADC2SEL_PLL_DIV2 |\ref CLK_CLKDIV5_EADC2(x) | + * |\ref EADC2_MODULE |\ref CLK_CLKSEL0_EADC2SEL_HCLK |\ref CLK_CLKDIV5_EADC2(x) | + * |\ref CCAP_MODULE | x | x | + * |\ref CCAP_MODULE | x | x | + * |\ref CCAP_MODULE | x | x | + * |\ref CCAP_MODULE | x | x | + * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HXT |\ref CLK_CLKDIV3_VSENSE(x) | + * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_PLL_DIV2 |\ref CLK_CLKDIV3_VSENSE(x) | + * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HCLK |\ref CLK_CLKDIV3_VSENSE(x) | + * |\ref SEN_MODULE |\ref CLK_CLKSEL0_CCAPSEL_HIRC |\ref CLK_CLKDIV3_VSENSE(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL_DIV2 |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL_DIV2 |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) | + * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_HXT |\ref CLK_CLKDIV5_CANFD0(x) | + * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD0(x) | + * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_HCLK |\ref CLK_CLKDIV5_CANFD0(x) | + * |\ref CANFD0_MODULE |\ref CLK_CLKSEL0_CANFD0SEL_HIRC |\ref CLK_CLKDIV5_CANFD0(x) | + * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_HXT |\ref CLK_CLKDIV5_CANFD1(x) | + * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD1(x) | + * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_HCLK |\ref CLK_CLKDIV5_CANFD1(x) | + * |\ref CANFD1_MODULE |\ref CLK_CLKSEL0_CANFD1SEL_HIRC |\ref CLK_CLKDIV5_CANFD1(x) | + * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_HXT |\ref CLK_CLKDIV5_CANFD2(x) | + * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD2(x) | + * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_HCLK |\ref CLK_CLKDIV5_CANFD2(x) | + * |\ref CANFD2_MODULE |\ref CLK_CLKSEL0_CANFD2SEL_HIRC |\ref CLK_CLKDIV5_CANFD2(x) | + * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_HXT |\ref CLK_CLKDIV5_CANFD3(x) | + * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_PLL_DIV2 |\ref CLK_CLKDIV5_CANFD3(x) | + * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_HCLK |\ref CLK_CLKDIV5_CANFD3(x) | + * |\ref CANFD3_MODULE |\ref CLK_CLKSEL0_CANFD3SEL_HIRC |\ref CLK_CLKDIV5_CANFD3(x) | + * |\ref EMAC0_MODULE | x |\ref CLK_CLKDIV3_EMAC0(x) | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2 | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_PLL_DIV2 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL_DIV2 |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL_DIV2 |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_HCLK | x | + * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_HCLK | x | + * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL_DIV2 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL_DIV2 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC48M | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLLFN_DIV2 | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_HCLK | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_HCLK | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HXT | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PLL_DIV2 | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_PCLK1 | x | + * |\ref QSPI1_MODULE |\ref CLK_CLKSEL3_QSPI1SEL_HIRC | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL_DIV2 | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC48M | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLLFN_DIV2 | x | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_HXT |\ref CLK_CLKDIV2_I2S1(x) | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_PLL_DIV2 |\ref CLK_CLKDIV2_I2S1(x) | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_PCLK1 |\ref CLK_CLKDIV2_I2S1(x) | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_HIRC |\ref CLK_CLKDIV2_I2S1(x) | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_HIRC48M |\ref CLK_CLKDIV2_I2S1(x) | + * |\ref I2S1_MODULE |\ref CLK_CLKSEL2_I2S1SEL_PLLFN_DIV2 |\ref CLK_CLKDIV2_I2S1(x) | + * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_HXT |\ref CLK_CLKDIV5_UART8(x) | + * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_PLL_DIV2 |\ref CLK_CLKDIV5_UART8(x) | + * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_LXT |\ref CLK_CLKDIV5_UART8(x) | + * |\ref UART8_MODULE |\ref CLK_CLKSEL2_UART8SEL_HIRC |\ref CLK_CLKDIV5_UART8(x) | + * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_HXT |\ref CLK_CLKDIV5_UART9(x) | + * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_PLL_DIV2 |\ref CLK_CLKDIV5_UART9(x) | + * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_LXT |\ref CLK_CLKDIV5_UART9(x) | + * |\ref UART9_MODULE |\ref CLK_CLKSEL2_UART9SEL_HIRC |\ref CLK_CLKDIV5_UART9(x) | + * |\ref TRNG_MODULE |\ref CLK_CLKSEL2_TRNGSEL_LXT | x | + * |\ref TRNG_MODULE |\ref CLK_CLKSEL2_TRNGSEL_LIRC | x | + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_HXT |\ref CLK_CLKDIV1_PSIO(x) | + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_LXT |\ref CLK_CLKDIV1_PSIO(x) | + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_PCLK1 |\ref CLK_CLKDIV1_PSIO(x) | + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_PLL_DIV2 |\ref CLK_CLKDIV1_PSIO(x) | + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_LIRC |\ref CLK_CLKDIV1_PSIO(x) | + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_HIRC |\ref CLK_CLKDIV1_PSIO(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL_DIV2 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL_DIV2 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL_DIV2 |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | + * |\ref KPI_MODULE |\ref CLK_CLKSEL3_KPISEL_HXT |\ref CLK_CLKDIV2_KPI(x) | + * |\ref KPI_MODULE |\ref CLK_CLKSEL3_KPISEL_LIRC |\ref CLK_CLKDIV1_KPI(x) | + * |\ref KPI_MODULE |\ref CLK_CLKSEL3_KPISEL_HIRC |\ref CLK_CLKDIV1_KPI(x) | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_HXT | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_PLL_DIV2 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_PCLK1 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_HIRC | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_HIRC48M | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL3_SPI2SEL_PLLFN_DIV2 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_HXT | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_PLL_DIV2 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_PCLK0 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_HIRC | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_HIRC48M | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL3_SPI3SEL_PLLFN_DIV2 | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL_DIV2 |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC48M |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLLFN_DIV2 |\ref CLK_CLKDIV2_I2S0(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HXT |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_LXT |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART6_MODULE |\ref CLK_CLKSEL3_UART6SEL_HIRC |\ref CLK_CLKDIV4_UART6(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HXT |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_LXT |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART7_MODULE |\ref CLK_CLKSEL3_UART7SEL_HIRC |\ref CLK_CLKDIV4_UART7(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL_DIV2 |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) | + * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LXT | x | + * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LIRC | x | + * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_HXT | x | + * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_PLL_DIV2 | x | + * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_PCLK1 | x | + * |\ref SPI4_MODULE |\ref CLK_CLKSEL4_SPI4SEL_HIRC | x | + * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_HXT | x | + * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_PLL_DIV2 | x | + * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_PCLK0 | x | + * |\ref SPI5_MODULE |\ref CLK_CLKSEL4_SPI5SEL_HIRC | x | + * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_HXT | x | + * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_PLL_DIV2 | x | + * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_PCLK1 | x | + * |\ref SPI6_MODULE |\ref CLK_CLKSEL4_SPI6SEL_HIRC | x | + * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_HXT | x | + * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_PLL_DIV2 | x | + * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_PCLK0 | x | + * |\ref SPI7_MODULE |\ref CLK_CLKSEL4_SPI7SEL_HIRC | x | + * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_HXT | x | + * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_PLL_DIV2 | x | + * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_PCLK1 | x | + * |\ref SPI8_MODULE |\ref CLK_CLKSEL4_SPI8SEL_HIRC | x | + * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_HXT | x | + * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_PLL_DIV2 | x | + * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_PCLK0 | x | + * |\ref SPI9_MODULE |\ref CLK_CLKSEL4_SPI9SEL_HIRC | x | + * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_HXT | x | + * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_PLL_DIV2 | x | + * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_PCLK1 | x | + * |\ref SPI10_MODULE |\ref CLK_CLKSEL4_SPI10SEL_HIRC | x | + * + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32Sel = 0UL, u32Div = 0UL; + uint32_t au32SelTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x4CUL}; /* CLK_CLKSEL0~4 */ + uint32_t au32DivTbl[6] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x10UL, 0x1C}; /* CLK_CLKDIV0~5 */ + uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; + + if(u32ModuleIdx == RTC_MODULE) /* RTC clock source configuration */ + { + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */ + } + + /* Select RTC clock source */ + RTC->LXTCTL = (RTC->LXTCTL & (~RTC_LXTCTL_RTCCKSEL_Msk)) | (u32ClkSrc); + + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */ + } + } + else /* Others clock source configuration */ + { + /* Configure clock source divider */ + switch(u32ModuleIdx) + { + /* For 8 bits divider */ + case EADC0_MODULE: CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_EADC0DIV_Msk)) | (u32ClkDiv); break; + case SDH0_MODULE: CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_SDH0DIV_Msk)) | (u32ClkDiv); break; + case SC0_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_SC0DIV_Msk)) | (u32ClkDiv); break; + case SC1_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_SC1DIV_Msk)) | (u32ClkDiv); break; + case SC2_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_SC2DIV_Msk)) | (u32ClkDiv); break; + case PSIO_MODULE: CLK->CLKDIV1 = (CLK->CLKDIV1 & (~CLK_CLKDIV1_PSIODIV_Msk)) | (u32ClkDiv); break; + case KPI_MODULE: CLK->CLKDIV2 = (CLK->CLKDIV2 & (~CLK_CLKDIV2_KPIDIV_Msk)) | (u32ClkDiv); break; + case EADC1_MODULE: CLK->CLKDIV2 = (CLK->CLKDIV2 & (~CLK_CLKDIV2_EADC1DIV_Msk)) | (u32ClkDiv); break; + case SEN_MODULE: CLK->CLKDIV3 = (CLK->CLKDIV3 & (~CLK_CLKDIV3_VSENSEDIV_Msk)) | (u32ClkDiv); break; + case EMAC0_MODULE: CLK->CLKDIV3 = (CLK->CLKDIV3 & (~CLK_CLKDIV3_EMAC0DIV_Msk)) | (u32ClkDiv); break; + case SDH1_MODULE: CLK->CLKDIV3 = (CLK->CLKDIV3 & (~CLK_CLKDIV3_SDH1DIV_Msk)) | (u32ClkDiv); break; + case EADC2_MODULE: CLK->CLKDIV5 = (CLK->CLKDIV5 & (~CLK_CLKDIV5_EADC2DIV_Msk)) | (u32ClkDiv); break; + + /* Others */ + default: + { + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Apply new divider */ + M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + } + break; + } + + /* Configure clock source */ + if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Set new clock selection setting */ + M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } + } + +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_HIRC48MEN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_HIRC48MEN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief Enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref ST_MODULE + * - \ref EMAC0_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref CRC_MODULE + * - \ref CCAP_MODULE + * - \ref SEN_MODULE + * - \ref HSUSBD_MODULE + * - \ref HSOTG_MODULE + * - \ref HBI_MODULE + * - \ref CRPT_MODULE + * - \ref KS_MODULE + * - \ref SPIM_MODULE + * - \ref FMCIDLE_MODULE + * - \ref USBH_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref TRACE_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref GPI_MODULE + * - \ref GPJ_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref ACMP01_MODULE + * - \ref ACMP23_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref I2C3_MODULE + * - \ref I2C4_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref SPI4_MODULE + * - \ref SPI5_MODULE + * - \ref SPI6_MODULE + * - \ref SPI7_MODULE + * - \ref SPI8_MODULE + * - \ref SPI9_MODULE + * - \ref SPI10_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref EADC0_MODULE + * - \ref EADC1_MODULE + * - \ref EADC2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref USCI0_MODULE + * - \ref PSIO_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref EQEI0_MODULE + * - \ref EQEI1_MODULE + * - \ref EQEI2_MODULE + * - \ref EQEI3_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref ECAP2_MODULE + * - \ref ECAP3_MODULE + * - \ref TRNG_MODULE + * - \ref KPI_MODULE + * @return None + * @details This function is used to enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + /* Index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1 */ + uint32_t au32ClkEnTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0x34UL, 0x54UL}; + + u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32TmpAddr = (uint32_t)&CLK->AHBCLK0 + au32ClkEnTbl[MODULE_APBCLK(u32ModuleIdx)]; + + *(volatile uint32_t *)u32TmpAddr |= u32TmpVal; +} + +/** + * @brief Disable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref ST_MODULE + * - \ref EMAC0_MODULE + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref CRC_MODULE + * - \ref CCAP_MODULE + * - \ref SEN_MODULE + * - \ref HSUSBD_MODULE + * - \ref HSOTG_MODULE + * - \ref HBI_MODULE + * - \ref CRPT_MODULE + * - \ref KS_MODULE + * - \ref SPIM_MODULE + * - \ref FMCIDLE_MODULE + * - \ref USBH_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref TRACE_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref GPI_MODULE + * - \ref GPJ_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref ACMP01_MODULE + * - \ref ACMP23_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref I2C3_MODULE + * - \ref I2C4_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref SPI4_MODULE + * - \ref SPI5_MODULE + * - \ref SPI6_MODULE + * - \ref SPI7_MODULE + * - \ref SPI8_MODULE + * - \ref SPI9_MODULE + * - \ref SPI10_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref EADC0_MODULE + * - \ref EADC1_MODULE + * - \ref EADC2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref USCI0_MODULE + * - \ref PSIO_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref EQEI0_MODULE + * - \ref EQEI1_MODULE + * - \ref EQEI2_MODULE + * - \ref EQEI3_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * - \ref ECAP2_MODULE + * - \ref ECAP3_MODULE + * - \ref TRNG_MODULE + * - \ref KPI_MODULE + * @return None + * @details This function is used to disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + /* Index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1 */ + uint32_t au32ClkEnTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0x34UL, 0x54UL}; + + u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32TmpAddr = (uint32_t)&CLK->AHBCLK0 + au32ClkEnTbl[MODULE_APBCLK(u32ModuleIdx)]; + + *(uint32_t *)u32TmpAddr &= u32TmpVal; +} + + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCTL_PLLSRC_HXT + * - \ref CLK_PLLCTL_PLLSRC_HIRC + * @param[in] u32PllFreq is PLL frequency. The range of u32PllFreq is 50 MHz ~ 500 MHz. + * @return PLL frequency + * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR; + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; + + /* PLL source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLL source clock from HXT */ + u32PllSrcClk = __HXT; + } + + /* PLL source clock is from HIRC */ + else + { + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from HIRC */ + u32PllSrcClk = __HIRC; + } + + /* Check PLL frequency range */ + /* Constraint 1: 50MHz < FOUT < 500MHz */ + if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) + { + /* Select "NO" according to request frequency */ + if((u32PllFreq < FREQ_100MHZ) && (u32PllFreq >= FREQ_50MHZ)) + { + u32NO = 3UL; + u32PllFreq = u32PllFreq << 2; + } + else if((u32PllFreq < FREQ_200MHZ) && (u32PllFreq >= FREQ_100MHZ)) + { + u32NO = 1UL; + u32PllFreq = u32PllFreq << 1; + } + else + { + u32NO = 0UL; + } + + /* u32NR start from 3 to avoid calculation overflow */ + u32NR = 3UL; + + /* Find best solution */ + u32Min = (uint32_t) - 1; /* initial u32Min to max value of uint32_t (0xFFFFFFFF) */ + u32MinNR = 0UL; + u32MinNF = 0UL; + + for(; u32NR <= 32UL; u32NR++) /* max NR = 32 since NR = INDIV+1 and INDIV = 0~31 */ + { + u32Tmp = u32PllSrcClk / u32NR; /* FREF = FIN/NR */ + if((u32Tmp >= FREQ_4MHZ) && (u32Tmp <= FREQ_8MHZ)) /* Constraint 2: 4MHz < FREF < 8MHz. */ + { + for(u32NF = 2UL; u32NF <= 513UL; u32NF++) /* NF = 2~513 since NF = FBDIV+2 and FBDIV = 0~511 */ + { + u32Tmp2 = (u32Tmp * u32NF) << 1; /* FVCO = FREF*2*NF */ + if((u32Tmp2 >= FREQ_200MHZ) && (u32Tmp2 <= FREQ_500MHZ)) /* Constraint 3: 200MHz < FVCO < 500MHz */ + { + u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2; + if(u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + + /* Break when get good results */ + if(u32Min == 0UL) + { + break; + } + } + } + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCTL = u32PllClkSrc | + (u32NO << CLK_PLLCTL_OUTDIV_Pos) | + ((u32MinNR - 1UL) << CLK_PLLCTL_INDIV_Pos) | + ((u32MinNF - 2UL) << CLK_PLLCTL_FBDIV_Pos); + + /* Actual PLL output clock frequency. FOUT = (FIN/NR)*2*NF*(1/NO) */ + u32PllClk = u32PllSrcClk / ((u32NO + 1UL) * u32MinNR) * (u32MinNF << 1); + } + else + { + /* Apply default PLL setting and return */ + CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_192MHz_HXT; + + /* Actual PLL output clock frequency */ + u32PllClk = FREQ_192MHZ; + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Return actual PLL output clock frequency */ + return u32PllClk; +} + + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function set PLL in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_PLLSTB_Msk + * - \ref CLK_STATUS_PLLFNSTB_Msk + * - \ref CLK_STATUS_HIRC48MSTB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (>500ms) + * @note This function sets g_CLK_i32ErrCode to CLK_TIMEOUT_ERR if clock source status is not stable. + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + uint32_t u32TimeOutCnt = SystemCoreClock>>1; + uint32_t u32Ret = 1U; + + g_CLK_i32ErrCode = 0; + while((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if(--u32TimeOutCnt == 0) + { + g_CLK_i32ErrCode = CLK_TIMEOUT_ERR; + u32Ret = 0U; + break; + } + } + + return u32Ret; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) + { + /* Disable System Tick clock source from external reference clock */ + CLK->AHBCLK0 &= ~CLK_AHBCLK0_STCKEN_Msk; + + /* Select System Tick clock source from core */ + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + /* Enable System Tick clock source from external reference clock */ + CLK->AHBCLK0 |= CLK_AHBCLK0_STCKEN_Msk; + + /* Select System Tick external reference clock source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + + /* Select System Tick clock source from external reference clock */ + SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk; + } + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} + + +/** + * @brief Power-down mode selected + * @param[in] u32PDMode is power down mode index. Including : + * - \ref CLK_PMUCTL_PDMSEL_PD + * - \ref CLK_PMUCTL_PDMSEL_LLPD + * - \ref CLK_PMUCTL_PDMSEL_FWPD + * - \ref CLK_PMUCTL_PDMSEL_SPD + * - \ref CLK_PMUCTL_PDMSEL_DPD + * @return None + * @details This function is used to set power-down mode. + * The register write-protection function should be disabled before using this function. + */ + +void CLK_SetPowerDownMode(uint32_t u32PDMode) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode; +} + + +/** + * @brief Set Wake-up pin trigger type at Deep Power down mode + * + * @param[in] u32TriggerType Wake-up pin trigger type + * - \ref CLK_DPDWKPIN_RISING + * - \ref CLK_DPDWKPIN_FALLING + * - \ref CLK_DPDWKPIN_BOTHEDGE + * - \ref CLK_DPDWKPIN1_RISING + * - \ref CLK_DPDWKPIN1_FALLING + * - \ref CLK_DPDWKPIN1_BOTHEDGE + * - \ref CLK_DPDWKPIN2_RISING + * - \ref CLK_DPDWKPIN2_FALLING + * - \ref CLK_DPDWKPIN2_BOTHEDGE + * - \ref CLK_DPDWKPIN3_RISING + * - \ref CLK_DPDWKPIN3_FALLING + * - \ref CLK_DPDWKPIN3_BOTHEDGE + * - \ref CLK_DPDWKPIN4_RISING + * - \ref CLK_DPDWKPIN4_FALLING + * - \ref CLK_DPDWKPIN4_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin trigger type. + * The register write-protection function should be disabled before using this function. + */ + +void CLK_EnableDPDWKPin(uint32_t u32TriggerType) +{ + uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4; + + /* Get DPD wake-up pin configuration */ + u32Pin1 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN1_Msk); + u32Pin2 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN2_Msk); + u32Pin3 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN3_Msk); + u32Pin4 = ((u32TriggerType) & CLK_PMUCTL_WKPINEN4_Msk); + + /* Set DPD wake-up pin configuration */ + if(u32Pin1) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType; + } + else if(u32Pin2) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType; + } + else if(u32Pin3) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType; + } + else if(u32Pin4) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType; + } + else + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN0_Msk)) | u32TriggerType; + } + +} + +/** + * @brief Get power manager wake up source + * + * @param[in] None + * @return None + * + * @details This function get power manager wake up source. + */ + +uint32_t CLK_GetPMUWKSrc(void) +{ + return (CLK->PMUSTS); +} + +/** + * @brief Set specified GPIO as wake up source at Stand-by Power down mode + * + * @param[in] u32Port GPIO port. It could be 0~3. + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32TriggerType Wake-up pin trigger type + * - \ref CLK_SPDWKPIN_RISING + * - \ref CLK_SPDWKPIN_FALLING + * @param[in] u32DebounceEn Standby Power-down mode wake-up pin de-bounce function + * - \ref CLK_SPDWKPIN_DEBOUNCEEN + * - \ref CLK_SPDWKPIN_DEBOUNCEDIS + * @return None + * + * @details This function is used to set specified GPIO as wake up source at Stand-by Power down mode. + */ +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn) +{ + uint32_t u32tmpAddr = 0UL; + uint32_t u32tmpVal = 0UL; + + /* GPx Stand-by Power-down Wake-up Pin Select */ + u32tmpAddr = (uint32_t)&CLK->PASWKCTL; + u32tmpAddr += (0x4UL * u32Port); + + u32tmpVal = inpw((uint32_t *)u32tmpAddr); + u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) | + (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE; + outpw((uint32_t *)u32tmpAddr, u32tmpVal); +} + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq = 0UL, u32PllReg; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & CLK_PLLCTL_PD_Msk) + { + u32PllFreq = 0UL; /* PLL is in power down mode or fix low */ + } + else /* PLL is in normal mode */ + { + /* PLL source clock */ + if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + /* Calculate PLL frequency */ + if(u32PllReg & CLK_PLLCTL_BP_Msk) + { + u32PllFreq = u32FIN; /* PLL is in bypass mode */ + } + else + { + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2); + } + } + + return u32PllFreq; +} + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref SEN_MODULE + * - \ref USBH_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref QSPI0_MODULE + * - \ref QSPI1_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref SPI4_MODULE + * - \ref SPI5_MODULE + * - \ref SPI6_MODULE + * - \ref SPI7_MODULE + * - \ref SPI8_MODULE + * - \ref SPI9_MODULE + * - \ref SPI10_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref EADC0_MODULE + * - \ref EADC1_MODULE + * - \ref EADC2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref PSIO_MODULE + * - \ref TRNG_MODULE + * - \ref KPI_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + uint32_t au32SelTbl[5] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x4CUL}; /* CLK_CLKSEL0~4 */ + uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; + + /* Get clock source selection setting */ + if(u32ModuleIdx == RTC_MODULE) + { + if(u32RTCCKEN == 0UL) + { + /* Enable RTC clock to get LXT clock source */ + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; + } + + u32TmpVal = ((RTC->LXTCTL & RTC_LXTCTL_RTCCKSEL_Msk) >> RTC_LXTCTL_RTCCKSEL_Pos); + + if(u32RTCCKEN == 0UL) + { + /* Disable RTC clock if it is disabled before */ + CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); + } + + } + else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + + /* Get clock source selection setting */ + u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + + return u32TmpVal; + +} + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref SDH1_MODULE + * - \ref SEN_MODULE + * - \ref USBH_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref CANFD0_MODULE + * - \ref CANFD1_MODULE + * - \ref CANFD2_MODULE + * - \ref CANFD3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref UART6_MODULE + * - \ref UART7_MODULE + * - \ref UART8_MODULE + * - \ref UART9_MODULE + * - \ref EADC0_MODULE + * - \ref EADC1_MODULE + * - \ref EADC2_MODULE + * - \ref I2S0_MODULE + * - \ref I2S1_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref PSIO_MODULE + * - \ref KPI_MODULE + * - \ref EMAC0_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + uint32_t u32DivVal = 0UL, u32DivAddr = 0UL; + uint32_t au32DivTbl[6] = {0x0UL, 0x4UL, 0x8UL, 0xCUL, 0x10UL, 0x1C}; /* CLK_CLKDIV0~5 */ + + switch(u32ModuleIdx) + { + /* For 8 bits divider */ + case EADC0_MODULE: u32DivVal = (CLK->CLKDIV0 & CLK_CLKDIV0_EADC0DIV_Msk) >> CLK_CLKDIV0_EADC0DIV_Pos; break; + case SDH0_MODULE: u32DivVal = (CLK->CLKDIV0 & CLK_CLKDIV0_SDH0DIV_Msk) >> CLK_CLKDIV0_SDH0DIV_Pos; break; + case SC0_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_SC0DIV_Msk) >> CLK_CLKDIV1_SC0DIV_Pos; break; + case SC1_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_SC1DIV_Msk) >> CLK_CLKDIV1_SC1DIV_Pos; break; + case SC2_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_SC2DIV_Msk) >> CLK_CLKDIV1_SC2DIV_Pos; break; + case PSIO_MODULE: u32DivVal = (CLK->CLKDIV1 & CLK_CLKDIV1_PSIODIV_Msk) >> CLK_CLKDIV1_PSIODIV_Pos; break; + case KPI_MODULE: u32DivVal = (CLK->CLKDIV2 & CLK_CLKDIV2_KPIDIV_Msk) >> CLK_CLKDIV2_KPIDIV_Pos; break; + case EADC1_MODULE: u32DivVal = (CLK->CLKDIV2 & CLK_CLKDIV2_EADC1DIV_Msk) >> CLK_CLKDIV2_EADC1DIV_Pos; break; + case SEN_MODULE: u32DivVal = (CLK->CLKDIV3 & CLK_CLKDIV3_VSENSEDIV_Msk) >> CLK_CLKDIV3_VSENSEDIV_Pos; break; + case EMAC0_MODULE: u32DivVal = (CLK->CLKDIV3 & CLK_CLKDIV3_EMAC0DIV_Msk) >> CLK_CLKDIV3_EMAC0DIV_Pos; break; + case SDH1_MODULE: u32DivVal = (CLK->CLKDIV3 & CLK_CLKDIV3_SDH1DIV_Msk) >> CLK_CLKDIV3_SDH1DIV_Pos; break; + case EADC2_MODULE: u32DivVal = (CLK->CLKDIV5 & CLK_CLKDIV5_EADC2DIV_Msk) >> CLK_CLKDIV5_EADC2DIV_Pos; break; + + /* Others */ + default: + { + /* Get clock divider control register address */ + u32DivAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Get clock divider number setting */ + u32DivVal = ((inpw((uint32_t *)u32DivAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + break; + } + + return u32DivVal; +} + +/** + * @brief Disable PLLFN + * @param None + * @return None + * @details This function set PLLFN in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLLFN(void) +{ + CLK->PLLFNCTL1 |= CLK_PLLFNCTL1_PD_Msk; +} + +/** + * @brief Set PLLFN frequency + * @param[in] u32PllClkSrc is PLLFN clock source. Including : + * - \ref CLK_PLLFNCTL1_PLLSRC_HXT + * - \ref CLK_PLLFNCTL1_PLLSRC_HIRC + * @param[in] u32PllFreq is PLLFN frequency. The range of u32PllFreq is 50 MHz ~ 500 MHz. + * @return PLL frequency + * @details This function is used to configure PLLFNCTL0 and PLLFNCTL1 register to set specified PLLFN frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLLFN(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32FIN, u32FVCO, u32FREF, u32PllClk; + uint32_t u32NR, u32NF, u32NO, u32X; + float fNX_X = 0.0, fX = 0.0; + + /* Disable PLLFN first to avoid unstable when setting PLLFN */ + CLK->PLLFNCTL1 |= CLK_PLLFNCTL1_PD_Msk; + + /* PLLFN source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLFNCTL1_PLLSRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLLFN source clock from HXT */ + u32FIN = __HXT; + } + + /* PLL source clock is from HIRC */ + else + { + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from HIRC */ + u32FIN = __HIRC; + } + + /* Check PLL frequency range */ + /* Constraint 1: 50MHz < FOUT < 500MHz */ + if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) + { + /* Select "NO" according to request frequency */ + if((u32PllFreq < FREQ_100MHZ) && (u32PllFreq >= FREQ_50MHZ)) + { + u32NO = 3UL; + u32FVCO = u32PllFreq << 2; + } + else if((u32PllFreq < FREQ_200MHZ) && (u32PllFreq >= FREQ_100MHZ)) + { + u32NO = 1UL; + u32FVCO = u32PllFreq << 1; + } + else + { + u32NO = 0UL; + u32FVCO = u32PllFreq; + } + + /* u32NR start from 3 to avoid calculation overflow */ + u32NR = 3UL; + + for(; u32NR <= 32UL; u32NR++) /* max NR = 32 since NR = INDIV+1 and INDIV = 0~31 */ + { + u32FREF = u32FIN / u32NR; /* FREF = FIN/NR */ + + if((u32FREF >= FREQ_1MHZ) && (u32FREF <= FREQ_8MHZ)) /* Constraint 2: 1MHz <= FREF <= 8MHz. */ + { + fNX_X = (float)((u32FVCO * u32NR)>>1)/u32FIN; + u32NF = (uint32_t)fNX_X; + + if((u32NF >= 12) && (u32NF <= 255)) /* Constraint 4: 12<= NF <= 255. */ + { + fX = fNX_X - u32NF; + u32X = (uint32_t)(fX*4096); + break; + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLFNCTL0 = (u32X << CLK_PLLFNCTL0_FRDIV_Pos) | + (u32NO << CLK_PLLFNCTL0_OUTDIV_Pos) | + ((u32NR - 1UL) << CLK_PLLFNCTL0_INDIV_Pos) | + ((u32NF - 2UL) << CLK_PLLFNCTL0_FBDIV_Pos); + CLK->PLLFNCTL1 = u32PllClkSrc; + + /* Actual PLL output clock frequency. FOUT = (FIN/NR)*2*(NF.X)*(1/NO) */ + u32PllClk = (uint32_t)((float)u32FIN / (((u32NO + 1UL) * u32NR)<<11) * ((u32NF<<12)+u32X)); + } + + if((u32PllFreq > FREQ_500MHZ) || (u32PllFreq < FREQ_50MHZ) || (u32NR==33) ) + { + /* Apply default PLL setting and return */ + CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_192MHz_HXT; + + /* Actual PLL output clock frequency */ + u32PllClk = FREQ_192MHZ; + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLFNSTB_Msk); + + /* Return actual PLL output clock frequency */ + return u32PllClk; +} + + +/** + * @brief Get PLLFN clock frequency + * @param None + * @return PLL frequency + * @details This function get PLLFN frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPLLFNClockFreq(void) +{ + uint32_t u32PllFreq = 0UL, u32PllReg0, u32PllReg1; + uint32_t u32FIN, u32NF, u32NR, u32NO, u32X; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + + /* Get PLLFN configuration */ + u32PllReg0 = CLK->PLLFNCTL0; + u32PllReg1 = CLK->PLLFNCTL1; + + if(u32PllReg1 & CLK_PLLFNCTL1_PD_Msk) + { + u32PllFreq = 0UL; /* PLLFN is in power down mode or fix low */ + } + else /* PLLFN is in normal mode */ + { + /* PLLFN source clock */ + if(u32PllReg1 & CLK_PLLFNCTL1_PLLSRC_Msk) + { + u32FIN = __HIRC; /* PLLFN source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLLFN source clock from HXT */ + } + + /* Calculate PLLFN frequency */ + if(u32PllReg1 & CLK_PLLFNCTL1_BP_Msk) + { + u32PllFreq = u32FIN; /* PLLFN is in bypass mode */ + } + else + { + /* PLLFN is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg0 & CLK_PLLFNCTL0_OUTDIV_Msk) >> CLK_PLLFNCTL0_OUTDIV_Pos)]; + u32NF = ((u32PllReg0 & CLK_PLLFNCTL0_FBDIV_Msk) >> CLK_PLLFNCTL0_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg0 & CLK_PLLFNCTL0_INDIV_Msk) >> CLK_PLLFNCTL0_INDIV_Pos) + 1UL; + u32X = ((u32PllReg0 & CLK_PLLFNCTL0_FRDIV_Msk) >> CLK_PLLFNCTL0_FRDIV_Pos); + + u32PllFreq = (uint32_t)((float)u32FIN / ((u32NO * u32NR)<<11) * ( ((u32NF<<12)+u32X))); + } + } + + return u32PllFreq; +} + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_crc.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_crc.c new file mode 100644 index 0000000..b57aa4a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_crc.c @@ -0,0 +1,117 @@ +/**************************************************************************//** + * @file crc.c + * @version V3.00 + * @brief Cyclic Redundancy Check(CRC) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC operation polynomial mode. Valid values are: + * - \ref CRC_CCITT + * - \ref CRC_8 + * - \ref CRC_16 + * - \ref CRC_32 + * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with: + * - \ref CRC_CHECKSUM_COM + * - \ref CRC_CHECKSUM_RVS + * - \ref CRC_WDATA_COM + * - \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. Valid values are: + * - \ref CRC_CPU_WDATA_8 + * - \ref CRC_CPU_WDATA_16 + * - \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n + * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + CRC->SEED = u32Seed; + + switch(u32Mode) + { + case CRC_CCITT: + u32Mode = CRC_16; + CRC->POLYNOMIAL = 0x1021; + break; + case CRC_8: + CRC->POLYNOMIAL = 0x7; + break; + case CRC_16: + CRC->POLYNOMIAL = 0x8005; + break; + case CRC_32: + CRC->POLYNOMIAL = 0x04C11DB7; + break; + default: + CRC->POLYNOMIAL = 0x0ul; + break; + } + + CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; + + /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */ + CRC->CTL |= CRC_CTL_CHKSINIT_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum Result + * + * @details This function gets the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + uint32_t u32Checksum = 0UL; + + switch(CRC->CTL & CRC_CTL_CRCMODE_Msk) + { + case CRC_CCITT: + case CRC_16: + u32Checksum = (CRC->CHECKSUM & 0xFFFFUL); + break; + + case CRC_32: + u32Checksum = CRC->CHECKSUM; + break; + + case CRC_8: + u32Checksum = (CRC->CHECKSUM & 0xFFUL); + break; + + default: + break; + } + + return u32Checksum; +} + +/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_crypto.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_crypto.c new file mode 100644 index 0000000..028f188 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_crypto.c @@ -0,0 +1,3011 @@ +/**************************************************************************//** + * @file crypto.c + * @version V3.00 + * @brief Cryptographic Accelerator driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include +#include +#include "NuMicro.h" + +#define ENABLE_DEBUG 0 + +#define ECC_SCA_PROTECT 1 // Enable Side-Channel Protecton + +#if ENABLE_DEBUG +#define CRPT_DBGMSG printf +#else +#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +#if defined(__ICCARM__) +# pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */ +#endif + +#define TIMEOUT_ECC SystemCoreClock /* 1 second time-out */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/* // @cond HIDDEN_SYMBOLS */ + + +static char hex_char_tbl[] = "0123456789abcdef"; + +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count); +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx); +static void Hex2Reg(char input[], uint32_t volatile reg[]); +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +static char ch2hex(char ch); +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift); +static int get_nibble_value(char c); +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]); +void ECC_Complete(CRPT_T *crpt); + + +/* // @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Open PRNG function + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32KeySize it is PRNG key size, including: + * - \ref PRNG_KEY_SIZE_64 + * - \ref PRNG_KEY_SIZE_128 + * - \ref PRNG_KEY_SIZE_192 + * - \ref PRNG_KEY_SIZE_256 + * @param[in] u32SeedReload is PRNG seed reload or not, including: + * - \ref PRNG_SEED_CONT + * - \ref PRNG_SEED_RELOAD + * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD. + * @return None + */ +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed) +{ + if(u32SeedReload) + { + crpt->PRNG_SEED = u32Seed; + } + + crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos); +} + +/** + * @brief Start to generate one PRNG key. + * @param[in] crpt The pointer of CRYPTO module + * @retval 0 Generate PRNG key success. + * @retval -1 Generate PRNG key time-out. + */ +int32_t PRNG_Start(CRPT_T *crpt) +{ + int32_t i32TimeOutCnt = SystemCoreClock; /* 1 second time-out */ + + crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk; + + /* Waiting for PRNG Busy */ + while(crpt->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + return -1; + } + } + + return 0; +} + +/** + * @brief Read the PRNG key. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] u32RandKey The key buffer to store newly generated PRNG key. + * @return None + */ +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]) +{ + uint32_t i, wcnt; + + wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U; + + for(i = 0U; i < wcnt; i++) + { + u32RandKey[i] = crpt->PRNG_KEY[i]; + } + + crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk; +} + + +/** + * @brief Open AES encrypt/decrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32EncDec 1: AES encode; 0: AES decode + * @param[in] u32OpMode AES operation mode, including: + * - \ref AES_MODE_ECB + * - \ref AES_MODE_CBC + * - \ref AES_MODE_CFB + * - \ref AES_MODE_OFB + * - \ref AES_MODE_CTR + * - \ref AES_MODE_CBC_CS1 + * - \ref AES_MODE_CBC_CS2 + * - \ref AES_MODE_CBC_CS3 + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @param[in] u32SwapType is AES input/output data swap control, including: + * - \ref AES_NO_SWAP + * - \ref AES_OUT_SWAP + * - \ref AES_IN_SWAP + * - \ref AES_IN_OUT_SWAP + * @return None + */ +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, + uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType) +{ + (void)u32Channel; + + crpt->AES_CTL = (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) | + (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) | + (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) | + (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos); + +} + +/** + * @brief Start AES encrypt/decrypt + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32DMAMode AES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shot AES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start. + * @return None + */ +void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode) +{ + (void)u32Channel; + + crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos); +} + +/** + * @brief Set AES keys + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32Keys An word array contains AES keys. + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @return None + */ +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) +{ + uint32_t i, wcnt, key_reg_addr; + + (void) u32Channel; + + key_reg_addr = (uint32_t)&crpt->AES_KEY[0]; + wcnt = 4UL + u32KeySize * 2UL; + + for(i = 0U; i < wcnt; i++) + { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } +} + + + +/** + * @brief Set AES keys index of Key Store + * @param[in] crpt The pointer of CRYPTO module + * @param[in] mem Memory type of Key Store key. it could be: + * - \ref KS_SRAM + * - \ref KS_FLASH + * - \ref KS_OTP + * @param[in] i32KeyIdx Index of the key in Key Store. + * @details AES could use the key in Key Store. This function is used to set the key index of Key Store. + */ +void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx) +{ + /* Use key in key store */ + crpt->AES_KSCTL = CRPT_AES_KSCTL_RSRC_Msk /* use KS */ | + (uint32_t)((int)mem << CRPT_AES_KSCTL_RSSRC_Pos) /* KS Memory type */ | + (uint32_t)i32KeyIdx /* key num */ ; + +} + + +/** + * @brief Set AES initial vectors + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32IV A four entry word array contains AES initial vectors. + * @return None + */ +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]) +{ + uint32_t i, key_reg_addr; + + (void) u32Channel; + + key_reg_addr = (uint32_t)&crpt->AES_IV[0]; + + for(i = 0U; i < 4U; i++) + { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES DMA transfer configuration. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32SrcAddr AES DMA source address + * @param[in] u32DstAddr AES DMA destination address + * @param[in] u32TransCnt AES DMA transfer byte count + * @return None + */ +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + (void) u32Channel; + + crpt->AES_SADDR = u32SrcAddr; + crpt->AES_DADDR = u32DstAddr; + crpt->AES_CNT = u32TransCnt; + +} + +/** + * @brief Open SHA encrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32OpMode SHA operation mode, including: + * - \ref SHA_MODE_SHA1 + * - \ref SHA_MODE_SHA224 + * - \ref SHA_MODE_SHA256 + * @param[in] u32SwapType is SHA input/output data swap control, including: + * - \ref SHA_NO_SWAP + * - \ref SHA_OUT_SWAP + * - \ref SHA_IN_SWAP + * - \ref SHA_IN_OUT_SWAP + * @param[in] hmac_key_len HMAC key byte count + * @return None + */ +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len) +{ + crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) | + (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos); + + if(hmac_key_len != 0UL) + { + crpt->HMAC_KEYCNT = hmac_key_len; + } +} + +/** + * @brief Start SHA encrypt + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt. + * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start. + * @return None + */ +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode) +{ + crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos); + crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos); +} + +/** + * @brief Set SHA DMA transfer + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32SrcAddr SHA DMA source address + * @param[in] u32TransCnt SHA DMA transfer byte count + * @return None + */ +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt) +{ + crpt->HMAC_SADDR = u32SrcAddr; + crpt->HMAC_DMACNT = u32TransCnt; +} + +/** + * @brief Read the SHA digest. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] u32Digest The SHA encrypt output digest. + * @return None + */ +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]) +{ + uint32_t i, wcnt, reg_addr; + + i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; + + if(i == SHA_MODE_SHA1) + { + wcnt = 5UL; + } + else if(i == SHA_MODE_SHA224) + { + wcnt = 7UL; + } + else if(i == SHA_MODE_SHA256) + { + wcnt = 8UL; + } + else if(i == SHA_MODE_SHA384) + { + wcnt = 12UL; + } + else + { + /* SHA_MODE_SHA512 */ + wcnt = 16UL; + } + + reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]); + for(i = 0UL; i < wcnt; i++) + { + u32Digest[i] = inpw(reg_addr); + reg_addr += 4UL; + } +} + + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* ECC */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) + +#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos) + +#define OP_ECDSAS (0x1UL << CRPT_ECC_CTL_ECDSAS_Pos) +#define OP_ECDSAR (0x1UL << CRPT_ECC_CTL_ECDSAR_Pos) + +enum +{ + CURVE_GF_P, + CURVE_GF_2M, +}; + +/*-----------------------------------------------------*/ +/* Define elliptic curve (EC): */ +/*-----------------------------------------------------*/ +static const ECC_CURVE _Curve[] = +{ + { + /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */ + CURVE_P_192, + 48, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */ + "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1", + "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012", + "07192b95ffc8da78631011ed6b24cdd573f977a11e794811", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */ + CURVE_P_224, + 56, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */ + "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4", + "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21", + "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */ + 224, /* key_len */ + 9, + 8, + 3, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_P_256, + 64, /* Echar */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */ + "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b", + "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296", + "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5", + 78, /* Epl */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */ + 78, /* Eol */ + "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */ + CURVE_P_384, + 96, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef", + "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7", + "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f", + 116, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */ + 116, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */ + 384, /* key_len */ + 12, + 3, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/ + CURVE_P_521, + 131, /* Echar */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00", + "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66", + "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650", + 157, /* Epl */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */ + 157, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */ + 521, /* key_len */ + 32, + 32, + 32, + CURVE_GF_P + }, + { + /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */ + CURVE_B_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "20a601907b8c953ca1481eb10512f78744a3205fd", + "3f0eba16286a2d57ea0991168d4994637e8343e36", + "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */ + CURVE_B_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000001", + "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad", + "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b", + "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */ + CURVE_B_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000001", + "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5", + "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053", + "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */ + CURVE_B_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f", + "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7", + "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */ + CURVE_B_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a", + "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19", + "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */ + CURVE_K_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "00000000000000000000000000000000000000001", + "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8", + "289070fb05d38ff58321f2e800536d538ccdaa3d9", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */ + CURVE_K_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000001", + "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126", + "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */ + CURVE_K_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000001", + "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836", + "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */ + CURVE_K_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746", + "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */ + CURVE_K_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972", + "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* Koblitz: Curve secp192k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_192, + 48, /* Echar */ + "00000000000000000000000000000000000000000", + "00000000000000000000000000000000000000003", + "DB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D", + "9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37", /* p */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D", /* n */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp224k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_224, + 56, /* Echar */ + "00000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000005", + "A1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C", + "7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D", /* p */ + 70, /* Eol */ + "0000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7", /* n */ + 224, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp256k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_256, + 64, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000007", + "79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798", + "483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8", + 78, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F", /* p */ + 78, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141", /* n */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP256r1 */ + CURVE_BP_256, + 64, /* Echar */ + "7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9", /* A */ + "26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6", /* B */ + "8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262", /* x */ + "547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997", /* y */ + 78, /* Epl */ + "A9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377", /* p */ + 78, /* Eol */ + "A9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7", /* q */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP384r1 */ + CURVE_BP_384, + 96, /* Echar */ + "7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826", /* A */ + "04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11", /* B */ + "1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E", /* x */ + "8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315", /* y */ + 116, /* Epl */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53", /* p */ + 116, /* Eol */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565", /* q */ + 384, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP512r1 */ + CURVE_BP_512, + 128, /* Echar */ + "7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA", /* A */ + "3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723", /* B */ + "81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822", /* x */ + "7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892", /* y */ + 156, /* Epl */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3", /* p */ + 156, /* Eol */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069", /* q */ + 512, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + CURVE_25519, + 64, // Echar + "0000000000000000000000000000000000000000000000000000000000076D06", // "0000000000000000000000000000000000000000000000000000000000000003", + "0000000000000000000000000000000000000000000000000000000000000001", + "0000000000000000000000000000000000000000000000000000000000000009", + "20ae19a1b8a086b4e01edd2c7748d14c923d4d7e6d7c61b229e9c5a27eced3d9", + 78, // Epl + "7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffed", // "115792089210356248762697446949407573530086143415290314195533631308867097853951", + 78, // Eol + "1000000000000000000000000000000014def9dea2f79cd65812631a5cf5d3ed", // "115792089210356248762697446949407573529996955224135760342422259061068512044369", + 255, // key_len + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_SM2_256, + 64, /* Echar */ + "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFC", /* a */ + "28E9FA9E9D9F5E344D5A9E4BCF6509A7F39789F515AB8F92DDBCBD414D940E93", /* b */ + "32C4AE2C1F1981195F9904466A39C9948FE30BBFF2660BE1715A4589334C74C7", /* x */ + "BC3736A2F4F6779C59BDCEE36B692153D0A9877CC62A474002DF32E52139F0A0", /* y */ + 78, /* Epl */ + "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFF", /* p */ + 78, /* Eol */ + "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFF7203DF6B21C6052B53BBF40939D54123", /* n */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + +}; + + +static ECC_CURVE *pCurve; +static ECC_CURVE Curve_Copy; + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve); +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve); +static int32_t run_ecc_codec(CRPT_T *crpt, uint32_t mode); + +static char temp_hex_str[160]; + +static volatile uint32_t g_ECC_done, g_ECCERR_done; + +void ECC_DriverISR(CRPT_T *crpt) +{ + if(crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if(crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + /* printf("ECCERRIF is set!!\n"); */ + } +} + + +#if ENABLE_DEBUG +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + int32_t i; + + printf("%s => ", str); + for(i = 0; i < count; i++) + { + printf("0x%08x ", regs[i]); + } + printf("\n"); +} +#else +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + (void)str; + (void)regs; + (void)count; +} +#endif +static char ch2hex(char ch) +{ + if(ch <= '9') + { + return ch - '0'; + } + else if((ch <= 'z') && (ch >= 'a')) + { + return ch - 'a' + 10U; + } + else + { + return ch - 'A' + 10U; + } +} + +static void Hex2Reg(char input[], uint32_t volatile reg[]) +{ + char hex; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + + while(si >= 0) + { + val32 = 0UL; + for(i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = ch2hex(input[si]); + val32 |= (uint32_t)hex << (i * 4UL); + si--; + } + reg[ri++] = val32; + } +} + +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift) +{ + uint32_t hex, carry; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + carry = 0U; + while(si >= 0) + { + val32 = 0UL; + for(i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = (uint32_t)ch2hex(input[si]); + hex <<= shift; + + val32 |= (uint32_t)((hex & 0xFU) | carry) << (i * 4UL); + carry = (hex >> 4) & 0xFU; + si--; + } + reg[ri++] = val32; + } + if(carry != 0U) + { + reg[ri] = carry; + } +} + +/** + * @brief Extract specified nibble from an unsigned word in character format. + * For example: + * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'. + * @param[in] val32 The input unsigned word + * @param[in] idx The Nth nibble to be extracted. + * @return The nibble in character format. + */ +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx) +{ + return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ]; +} + + +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]) +{ + int32_t idx, ri; + uint32_t i; + + output[count] = 0U; + idx = count - 1; + + for(ri = 0; idx >= 0; ri++) + { + for(i = 0UL; (i < 8UL) && (idx >= 0); i++) + { + output[idx] = get_Nth_nibble_char(reg[ri], i); + idx--; + } + } +} + +/** + * @brief Translate registers value into hex string + * @param[in] count The string length of ouptut hex string. + * @param[in] reg Register array. + * @param[in] output String buffer for output hex string. + */ +void CRPT_Reg2Hex(int32_t count, volatile uint32_t reg[], char output[]) +{ + Reg2Hex(count, reg, output); +} + +/** + * @brief Translate hex string to registers value + * @param[in] input hex string. + * @param[in] reg Register array. + */ +void CRPT_Hex2Reg(char input[], uint32_t volatile reg[]) +{ + Hex2Reg(input, reg); +} + + +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve) +{ + int32_t i, ret = 0; + + pCurve = get_curve(ecc_curve); + if(pCurve == NULL) + { + CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve); + ret = -1; + } + + if(ret == 0) + { + for(i = 0; i < 18; i++) + { + crpt->ECC_A[i] = 0UL; + crpt->ECC_B[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_N[i] = 0UL; + } + + Hex2Reg(pCurve->Ea, crpt->ECC_A); + Hex2Reg(pCurve->Eb, crpt->ECC_B); + Hex2Reg(pCurve->Px, crpt->ECC_X1); + Hex2Reg(pCurve->Py, crpt->ECC_Y1); + + CRPT_DBGMSG("Key length = %d\n", pCurve->key_len); + dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10); + dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10); + dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10); + dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10); + + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_N[0] = 0x1UL; + crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32)); + crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32)); + crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32)); + crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32)); + } + else + { + Hex2Reg(pCurve->Pp, crpt->ECC_N); + } + } + dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10); + return ret; +} + + +static int get_nibble_value(char c) +{ + char ch; + + if((c >= '0') && (c <= '9')) + { + ch = '0'; + return ((int)c - (int)ch); + } + + if((c >= 'a') && (c <= 'f')) + { + ch = 'a'; + return ((int)c - (int)ch + 10); + } + + if((c >= 'A') && (c <= 'F')) + { + ch = 'A'; + return ((int)c - (int)ch + 10); + } + return 0; +} + + +/** + * @brief Check if the private key is located in valid range of curve. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k The input private key. + * @return 1 Is valid. + * @return 0 Is not valid. + * @return -1 Invalid curve. + */ +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]) +{ + uint32_t i; + + (void)crpt; + pCurve = get_curve(ecc_curve); + if(pCurve == NULL) + { + return -1; + } + + if(strlen(private_k) < strlen(pCurve->Eorder)) + { + return 1; + } + + if(strlen(private_k) > strlen(pCurve->Eorder)) + { + return 0; + } + + for(i = 0U; i < strlen(private_k); i++) + { + if(get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) + { + return 1; + } + + if(get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i])) + { + return 0; + } + } + return 0; +} + + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] private_k The input private key. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] public_k1 The output publick key 1. + * @param[out] public_k2 The output publick key 2. + * @return 0 Success. + * @return -1 Hardware error or time-out. + * @return -2 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]) +{ + int32_t ret = 0, i, i32TimeOutCnt; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -2; + } + + if(ret == 0) + { + CRPT->ECC_KSCTL = 0; + + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + + Hex2Reg(private_k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + i32TimeOutCnt = TIMEOUT_ECC; + while(g_ECC_done == 0UL) + { + if( (i32TimeOutCnt-- <= 0) || g_ECCERR_done ) + { + ret = -1; + break; + } + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + + + + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] mem Memory type of Key Store. It could be KS_SRAM, KS_FLASH or KS_OTP. + * @param[in] i32KeyIdx Index of the key in Key Store. + * @param[out] public_k1 The output publick key 1. + * @param[out] public_k2 The output publick key 2. + * @param[in] u32ExtraOp Extra options for ECC_KSCTL register. + * @return 0 Success. + * @return 0 Success. + * @return -1 Hardware error or time-out. + * @return -2 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp) +{ + int32_t ret = 0, i32TimeOutCnt; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -2; + } + + if(ret == 0) + { + + // key from key store + crpt->ECC_KSCTL = (uint32_t)(mem << 6)/* KS Memory Type */ | + (CRPT_ECC_KSCTL_RSRCK_Msk)/* Key from KS */ | + u32ExtraOp | + (uint32_t)i32KeyIdx; + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + i32TimeOutCnt = TIMEOUT_ECC; + while(g_ECC_done == 0UL) + { + if( (i32TimeOutCnt-- <= 0) || g_ECCERR_done ) + { + ret = -1; + break; + } + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[out] x1 The x-coordinate of input point. + * @param[out] y1 The y-coordinate of input point. + * @param[in] k The private key + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] x2 The x-coordinate of output point. + * @param[out] y2 The y-coordinate of output point. + * @return 0 Success. + * @return -1 Hardware error or time-out. + * @return -2 "ecc_curve" value is invalid. + */ +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]) +{ + int32_t i, ret = 0, i32TimeOutCnt; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -2; + } + + if(ret == 0) + { + for(i = 0; i < 9; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_K[i] = 0UL; + } + + Hex2Reg(x1, crpt->ECC_X1); + Hex2Reg(y1, crpt->ECC_Y1); + Hex2Reg(k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + + if(ecc_curve == CURVE_25519) + { + printf("!! Is curve-25519 !!\n"); + crpt->ECC_CTL |= CRPT_ECC_CTL_SCAP_Msk; + crpt->ECC_CTL |= CRPT_ECC_CTL_CSEL_Msk; + + /* If SCAP enabled, the curve order must be written to ECC_X2 */ + if(crpt->ECC_CTL & CRPT_ECC_CTL_SCAP_Msk) + { + Hex2Reg(pCurve->Eorder, crpt->ECC_X2); + } + } + + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + i32TimeOutCnt = TIMEOUT_ECC; + while(g_ECC_done == 0UL) + { + if( (i32TimeOutCnt-- <= 0) || g_ECCERR_done ) + { + ret = -1; + break; + } + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, x2); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, y2); + + } + + return ret; +} + + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 Hardware error or time-out. + * @return -2 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]) +{ + int32_t i, ret = 0, i32TimeOutCnt; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -2; + } + + if(ret == 0) + { + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + if((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) || + (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163)) + { + Hex2RegEx(private_k, crpt->ECC_K, 1); + } + else if((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) || + (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571)) + { + Hex2RegEx(private_k, crpt->ECC_K, 2); + } + else + { + Hex2Reg(private_k, crpt->ECC_K); + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + i32TimeOutCnt = TIMEOUT_ECC; + while(g_ECC_done == 0UL) + { + if( (i32TimeOutCnt-- <= 0) || g_ECCERR_done ) + { + ret = -1; + break; + } + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z); + } + + return ret; +} + + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 Hardware error or time-out. + * @return -2 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[]) +{ + int32_t i, i32TimeOutCnt; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + return -2; + } + + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + crpt->ECC_KSCTL = CRPT_ECC_KSCTL_ECDH_Msk | CRPT_ECC_KSCTL_RSRCK_Msk | + (uint32_t)(mem << CRPT_ECC_KSCTL_RSSRCK_Pos)/* KS Memory Type */ | + (uint32_t)i32KeyIdx; + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + i32TimeOutCnt = TIMEOUT_ECC; + while(g_ECC_done == 0UL) + { + if( (i32TimeOutCnt-- <= 0) || g_ECCERR_done ) + { + return -1; + } + } + + return (crpt->ECC_KSSTS & 0x1f); + +} + + +static int32_t run_ecc_codec(CRPT_T *crpt, uint32_t mode) +{ + uint32_t eccop; + int32_t i32TimeOutCnt; + + eccop = mode & CRPT_ECC_CTL_ECCOP_Msk; + if(eccop == ECCOP_MODULE) + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + else + { + if(pCurve->GF == (int)CURVE_GF_2M) + { + /* point */ + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + +#ifdef ECC_SCA_PROTECT + if(eccop == ECCOP_POINT_MUL) + { + /* Enable side-channel protection in some operation */ + crpt->ECC_CTL |= CRPT_ECC_CTL_SCAP_Msk; + /* If SCAP enabled, the curve order must be written to ECC_X2 */ + Hex2Reg(pCurve->Eorder, crpt->ECC_X2); + } +#endif + + } + + g_ECC_done = g_ECCERR_done = 0UL; + + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk; + + i32TimeOutCnt = TIMEOUT_ECC; + while(g_ECC_done == 0UL) + { + if( (i32TimeOutCnt-- <= 0) || g_ECCERR_done ) + { + return -1; + } + } + + i32TimeOutCnt = TIMEOUT_ECC; + while(crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + return -1; + } + } + + return 0; +} + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *d, char *k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + CRPT->ECC_KSCTL = 0; + + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Write the random integer k to K register */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_K); + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* 3-(9) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + /* + * 4. Compute s = k^-1 * (e + d * r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 4-(3) Write the random integer k to X1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(7) output = %s\n", temp_hex_str); +#endif + + /* 4-(8) Read X1 registers to get k^-1 */ + + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str); +#endif + + /* 4-(9) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(10) Write r, d to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + } + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(d, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(14) output = %s\n", temp_hex_str); +#endif + + /* 4-(15) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(16) Write e to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(message, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(20) output = %s\n", temp_hex_str); +#endif + + /* 4-(21) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(22) Write k^-1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(27) Read X1 registers to get s */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result2, S); + + } /* ret == 0 */ + + return ret; +} + + + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_d, int32_t i32KeyIdx_d, KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + CRPT->ECC_KSCTL = 0; + CRPT->ECC_KSXY = 0; + + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Use k in Key Store */ + crpt->ECC_KSCTL = (uint32_t)(mem_k << CRPT_ECC_KSCTL_RSSRCK_Pos)/* KS Memory Type */ | + CRPT_ECC_KSCTL_RSRCK_Msk/* Key from KS */ | + (uint32_t)i32KeyIdx_k; + + run_ecc_codec(crpt, ECCOP_POINT_MUL | OP_ECDSAR); + + /* 3-(9) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + + /* + * 4. Compute s = k ^-1 * (e + d * r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2)(3)(4)(5) Use d, k in Key Store */ + crpt->ECC_CTL = 0; + crpt->ECC_KSXY = CRPT_ECC_KSXY_RSRCXY_Msk | + (uint32_t)(mem_k << CRPT_ECC_KSXY_RSSRCX_Pos) | ((uint32_t)i32KeyIdx_k << CRPT_ECC_KSXY_NUMX_Pos) | // Key Store index of k + (uint32_t)(mem_d << CRPT_ECC_KSXY_RSSRCY_Pos) | ((uint32_t)i32KeyIdx_d << CRPT_ECC_KSXY_NUMY_Pos); // Key Store index of d + + // 4-5 + for(i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_result1[i]; + crpt->ECC_Y2[i] = 0; + } + Hex2Reg(message, crpt->ECC_Y2); + + run_ecc_codec(crpt, ECCOP_MODULE | OP_ECDSAS); + + /* 4-11 Read X1 registers to get s */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + Reg2Hex(pCurve->Echar, temp_result2, S); + + /* Clear KS Control */ + CRPT->ECC_KSCTL = 0; + CRPT->ECC_KSXY = 0; + + } /* ret == 0 */ + + return ret; +} + + +/** + * @brief ECDSA dogotal signature verification. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *public_k1, char *public_k2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + + /* 3-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for(i = 0; i < 18; i++) + { + CRPT->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e * w (mod n) and u2 = r * w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X * (x1', y1') = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X *(x1', y1') + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1 * (mod n) + * + * 6. The signature is valid if x1 * = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* (10) Write u2 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X * (x1', y1') */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1 * (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1 * = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if(strcasecmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + + + +/** + * @brief ECDSA signature verification with Key Store + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1, KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + crpt->ECC_KSCTL = 0; + crpt->ECC_KSXY = 0; + + /* 3-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for(i = 0; i < 18; i++) + { + CRPT->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e * w (mod n) and u2 = r * w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X * (x1', y1') = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X * (x1', y1') + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1 * (mod n) + * + * 6. The signature is valid if x1 * = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + +#if 0 + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); +#else + + /* 5-(2) Get the public key from key store */ + crpt->ECC_KSCTL = 0ul; + crpt->ECC_KSXY = CRPT_ECC_KSXY_RSRCXY_Msk | + (uint32_t)(mem_pk1 << CRPT_ECC_KSXY_RSSRCX_Pos) | ((uint32_t)i32KeyIdx_pk1 << CRPT_ECC_KSXY_NUMX_Pos) | // Key Store index of pk1 + (uint32_t)(mem_pk2 << CRPT_ECC_KSXY_RSSRCY_Pos) | ((uint32_t)i32KeyIdx_pk2 << CRPT_ECC_KSXY_NUMY_Pos); // Key Store index of pk2 + +#endif + + /* (10) Write u2 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X * (x1', y1') */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1 * (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1 * = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if(strcasecmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) +{ + uint32_t i; + ECC_CURVE *ret = NULL; + + for(i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++) + { + if(ecc_curve == _Curve[i].curve_id) + { + memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE)); + ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */ + } + if(ret != NULL) + { + break; + } + } + return ret; +} + + +/** + * @brief ECC interrupt service routine. User application must invoke this function in + * his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done. + * @param[in] crpt Reference to Crypto module. + * @return none + */ +void ECC_Complete(CRPT_T *crpt) +{ + if(crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if(crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + printf("ECCEIF flag is set!!\n"); + } +} + + +int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve) +{ + int32_t err; + + /* Update pCurve pointer */ + err = ecc_init_curve(crpt, ecc_curve); + if(err == 0) + { + /* get curve */ + memcpy(curve, pCurve, sizeof(ECC_CURVE)); + } + + return err; +} + + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* RSA */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +/** @cond HIDDEN_SYMBOLS */ + +static void *s_pRSABuf; +static uint32_t s_u32RsaOpMode; + +typedef enum +{ + BUF_NORMAL, + BUF_CRT, + BUF_CRTBYPASS, + BUF_SCAP, + BUF_CRT_SCAP, + BUF_CRTBYPASS_SCAP, + BUF_KS +} E_RSA_BUF_SEL; + +static int32_t CheckRsaBufferSize(uint32_t u32OpMode, uint32_t u32BufSize, uint32_t u32UseKS); + +/** @endcond HIDDEN_SYMBOLS */ + +/* Check the allocated buffer size for RSA operation. */ +static int32_t CheckRsaBufferSize(uint32_t u32OpMode, uint32_t u32BufSize, uint32_t u32UseKS) +{ + /* RSA buffer size for MODE_NORMAL, MODE_CRT, MODE_CRTBYPASS, MODE_SCAP, MODE_CRT_SCAP, MODE_CRTBYPASS_SCAP */ + uint32_t s_au32RsaBufSizeTbl[] = {sizeof(RSA_BUF_NORMAL_T), sizeof(RSA_BUF_CRT_T), sizeof(RSA_BUF_CRT_T), \ + sizeof(RSA_BUF_SCAP_T), sizeof(RSA_BUF_CRT_SCAP_T), sizeof(RSA_BUF_CRT_SCAP_T), \ + sizeof(RSA_BUF_KS_T) + }; + + if(u32UseKS) + { + if(u32BufSize != s_au32RsaBufSizeTbl[BUF_KS]) + return (-1); + } + else + { + switch(u32OpMode) + { + case RSA_MODE_NORMAL: + if(u32BufSize != s_au32RsaBufSizeTbl[BUF_NORMAL]) + return (-1); + break; + case RSA_MODE_CRT: + if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRT]) + return (-1); + break; + case RSA_MODE_CRTBYPASS: + if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRTBYPASS]) + return (-1); + break; + case RSA_MODE_SCAP: + if(u32BufSize != s_au32RsaBufSizeTbl[BUF_SCAP]) + return (-1); + break; + case RSA_MODE_CRT_SCAP: + if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRT_SCAP]) + return (-1); + break; + case RSA_MODE_CRTBYPASS_SCAP: + if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRTBYPASS_SCAP]) + return (-1); + break; + default: + return (-1); + } + } + + return 0; +} + +/** + * @brief Open RSA encrypt/decrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32OpMode RSA operation mode, including: + * - \ref RSA_MODE_NORMAL + * - \ref RSA_MODE_CRT + * - \ref RSA_MODE_CRTBYPASS + * - \ref RSA_MODE_SCAP + * - \ref RSA_MODE_CRT_SCAP + * - \ref RSA_MODE_CRTBYPASS_SCAP + * @param[in] u32KeySize is RSA key size, including: + * - \ref RSA_KEY_SIZE_1024 + * - \ref RSA_KEY_SIZE_2048 + * - \ref RSA_KEY_SIZE_3072 + * - \ref RSA_KEY_SIZE_4096 + * @param[in] psRSA_Buf The pointer of RSA buffer struct. User should declare correct RSA buffer for specific operation mode first. + * - \ref RSA_BUF_NORMAL_T The struct for normal mode + * - \ref RSA_BUF_CRT_T The struct for CRT ( + CRT bypass) mode + * - \ref RSA_BUF_SCAP_T The struct for SCAP mode + * - \ref RSA_BUF_CRT_SCAP_T The struct for CRT ( + CRT bypass) +SCAP mode + * - \ref RSA_BUF_KS_T The struct for using key store + * @param[in] u32BufSize is RSA buffer size. + * @param[in] u32UseKS is use key store function. + * - \ref 0 No use key store function + * - \ref 1 Use key store function + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, \ + void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS) +{ + if(psRSA_Buf == 0) + { + return (-1); + } + if(CheckRsaBufferSize(u32OpMode, u32BufSize, u32UseKS) != 0) + { + return (-1); + } + + s_u32RsaOpMode = u32OpMode; + s_pRSABuf = psRSA_Buf; + crpt->RSA_CTL = (u32OpMode) | (u32KeySize << CRPT_RSA_CTL_KEYLENG_Pos); + + return 0; +} + +/** + * @brief Set the RSA key + * @param[in] crpt The pointer of CRYPTO module + * @param[in] Key The private or public key. + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_SetKey(CRPT_T *crpt, char *Key) +{ + if(s_pRSABuf == 0) + { + return (-1); + } + Hex2Reg(Key, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaE); + crpt->RSA_SADDR[2] = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaE; /* the public key or private key */ + + return 0; +} + +/** + * @brief Set RSA DMA transfer configuration. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] Src RSA DMA source data + * @param[in] n The modulus for both the public and private keys + * @param[in] P The factor of modulus operation(P) for CRT/SCAP mode + * @param[in] Q The factor of modulus operation(Q) for CRT/SCAP mode + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q) +{ + if(s_pRSABuf == 0) + { + return (-1); + } + Hex2Reg(Src, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaM); + Hex2Reg(n, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaN); + + /* Assign the data to DMA */ + crpt->RSA_SADDR[0] = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaM; /* plaintext / encrypt data */ + crpt->RSA_SADDR[1] = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaN; /* the base of modulus operation */ + crpt->RSA_DADDR = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaOutput; /* encrypt data / decrypt data */ + + if((s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) && (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk)) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + Hex2Reg(P, ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaP); + Hex2Reg(Q, ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaQ); + + crpt->RSA_SADDR[3] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaP; /* prime P */ + crpt->RSA_SADDR[4] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaQ; /* prime Q */ + + crpt->RSA_MADDR[0] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpCp; /* for storing the intermediate temporary value(Cp) */ + crpt->RSA_MADDR[1] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpCq; /* for storing the intermediate temporary value(Cq) */ + crpt->RSA_MADDR[2] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpDp; /* for storing the intermediate temporary value(Dp) */ + crpt->RSA_MADDR[3] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpDq; /* for storing the intermediate temporary value(Dq) */ + crpt->RSA_MADDR[4] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpRp; /* for storing the intermediate temporary value(Rp) */ + crpt->RSA_MADDR[5] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpRq; /* for storing the intermediate temporary value(Rq) */ + + /* For SCAP mode to store the intermediate temporary value(blind key) */ + crpt->RSA_MADDR[6] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpBlindKey; + } + else if(s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + Hex2Reg(P, ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaP); + Hex2Reg(Q, ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaQ); + + crpt->RSA_SADDR[3] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaP; /* prime P */ + crpt->RSA_SADDR[4] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaQ; /* prime Q */ + + crpt->RSA_MADDR[0] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpCp; /* for storing the intermediate temporary value(Cp) */ + crpt->RSA_MADDR[1] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpCq; /* for storing the intermediate temporary value(Cq) */ + crpt->RSA_MADDR[2] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpDp; /* for storing the intermediate temporary value(Dp) */ + crpt->RSA_MADDR[3] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpDq; /* for storing the intermediate temporary value(Dq) */ + crpt->RSA_MADDR[4] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpRp; /* for storing the intermediate temporary value(Rp) */ + crpt->RSA_MADDR[5] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpRq; /* for storing the intermediate temporary value(Rq) */ + } + else if(s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + Hex2Reg(P, ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaP); + Hex2Reg(Q, ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaQ); + + crpt->RSA_SADDR[3] = (uint32_t) & ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaP; /* prime P */ + crpt->RSA_SADDR[4] = (uint32_t) & ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaQ; /* prime Q */ + + /* For SCAP mode to store the intermediate temporary value(blind key) */ + crpt->RSA_MADDR[6] = (uint32_t) & ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaTmpBlindKey; + } + + return 0; +} + +/** + * @brief Start RSA encrypt/decrypt + * @param[in] crpt The pointer of CRYPTO module + * @return None + */ +void RSA_Start(CRPT_T *crpt) +{ + crpt->RSA_CTL |= CRPT_RSA_CTL_START_Msk; +} + +/** + * @brief Read the RSA output. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] Output The RSA operation output data. + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_Read(CRPT_T *crpt, char *Output) +{ + uint32_t au32CntTbl[4] = {256, 512, 768, 1024}; /* count is key length divided by 4 */ + uint32_t u32CntIdx = 0; + + if(s_pRSABuf == 0) + { + return (-1); + } + + u32CntIdx = (crpt->RSA_CTL & CRPT_RSA_CTL_KEYLENG_Msk) >> CRPT_RSA_CTL_KEYLENG_Pos; + Reg2Hex((int32_t)au32CntTbl[u32CntIdx], ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaOutput, Output); + + return 0; +} + +/** + * @brief Set the RSA key is read from key store + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32KeyNum The number of private or public key in key store. + * @param[in] u32KSMemType The key is read from selected memory type of key store. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] u32BlindKeyNum The number of blind key in SRAM of key store for SCAP mode. This key is un-readable. + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum) +{ + if(s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk) + { + crpt->RSA_KSCTL = (u32BlindKeyNum << 8) | (u32KSMemType << CRPT_RSA_KSCTL_RSSRC_Pos) | CRPT_RSA_KSCTL_RSRC_Msk | u32KeyNum; + } + else + { + crpt->RSA_KSCTL = (u32KSMemType << CRPT_RSA_KSCTL_RSSRC_Pos) | CRPT_RSA_KSCTL_RSRC_Msk | u32KeyNum; + } + return 0; +} + +/** + * @brief Set RSA DMA transfer configuration while using key store. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32OpMode RSA operation mode, including: + * - \ref RSA_MODE_NORMAL + * - \ref RSA_MODE_CRT + * - \ref RSA_MODE_CRTBYPASS + * - \ref RSA_MODE_SCAP + * - \ref RSA_MODE_CRT_SCAP + * - \ref RSA_MODE_CRTBYPASS_SCAP + * @param[in] Src RSA DMA source data + * @param[in] n The modulus for both the public and private keys + * @param[in] u32PNum The number of the factor of modulus operation(P) in SRAM of key store for CRT/SCAP mode + * @param[in] u32QNum The number of the factor of modulus operation(Q) in SRAM of key store for CRT/SCAP mode + * @param[in] u32CpNum The number of Cp in SRAM of key store for CRT mode + * @param[in] u32CqNum The number of Cq in SRAM of key store for CRT mode + * @param[in] u32DpNum The number of Dp in SRAM of key store for CRT mode + * @param[in] u32DqNum The number of Dq in SRAM of key store for CRT mode + * @param[in] u32RpNum The number of Rp in SRAM of key store for CRT mode + * @param[in] u32RqNum The number of Rq in SRAM of key store for CRT mode + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + * @note P, Q, Dp, Dq are equal to half key length. Cp, Cq, Rp, Rq, Blind key are equal to key length. + */ +int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum, + uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum, + uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum) +{ + if(s_pRSABuf == 0) + { + return (-1); + } + Hex2Reg(Src, ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaM); + Hex2Reg(n, ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaN); + + /* Assign the data to DMA */ + crpt->RSA_SADDR[0] = (uint32_t) & ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaM; /* plaintext / encrypt data */ + crpt->RSA_SADDR[1] = (uint32_t) & ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaN; /* the base of modulus operation */ + crpt->RSA_DADDR = (uint32_t) & ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaOutput; /* encrypt data / decrypt data */ + + if((s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) || (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk)) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + crpt->RSA_KSSTS[0] = (crpt->RSA_KSSTS[0] & (~(CRPT_RSA_KSSTS0_NUM0_Msk | CRPT_RSA_KSSTS0_NUM1_Msk))) | \ + (u32PNum << CRPT_RSA_KSSTS0_NUM0_Pos) | (u32QNum << CRPT_RSA_KSSTS0_NUM1_Pos); + + } + if(s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) + { + /* For RSA CRT mode, Cp, Cq, Dp, Dq, Rp, Rq */ + crpt->RSA_KSSTS[0] = (crpt->RSA_KSSTS[0] & (~(CRPT_RSA_KSSTS0_NUM2_Msk | CRPT_RSA_KSSTS0_NUM3_Msk))) | \ + (u32CpNum << CRPT_RSA_KSSTS0_NUM2_Pos) | (u32CqNum << CRPT_RSA_KSSTS0_NUM3_Pos); + crpt->RSA_KSSTS[1] = (u32DpNum << CRPT_RSA_KSSTS1_NUM4_Pos) | (u32DqNum << CRPT_RSA_KSSTS1_NUM5_Pos) | \ + (u32RpNum << CRPT_RSA_KSSTS1_NUM6_Pos) | (u32RqNum << CRPT_RSA_KSSTS1_NUM7_Pos); + } + + return 0; +} + + +/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRYPTO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_dac.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_dac.c new file mode 100644 index 0000000..b39e5b6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_dac.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file dac.c + * @version V1.00 + * @brief DAC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make DAC module be ready to convert. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @param[in] u32TrgSrc Decides the trigger source. Valid values are: + * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger + * - \ref DAC_SOFTWARE_TRIGGER :Software trigger + * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger + * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger + * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger + * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger + * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger + * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger + * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger + * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger + * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger + * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger + * @return None + * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. + * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. + * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, + * external STDAC pin, timer event, or EPWM event. + */ +void DAC_Open(DAC_T *dac, + uint32_t u32Ch, + uint32_t u32TrgSrc) +{ + (void)u32Ch; + dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); + dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used. + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + (void)u32Ch; + dac->CTL &= (~DAC_CTL_DACEN_Msk); +} + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. + * @return Real DAC conversion settling time (micro second). + * @details For example, DAC controller clock speed is 160MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0xA0. + * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed. + */ +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + + dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL); + + return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq()); +} + + + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_eadc.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_eadc.c new file mode 100644 index 0000000..cf4586c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_eadc.c @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file eadc.c + * @version V2.00 + * @brief EADC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +int32_t g_EADC_i32ErrCode = 0; /*!< EADC global error code */ + + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. + * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode. + * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note This API will reset and calibrate EADC if EADC never be calibrated after chip power on. + * @note This function sets g_EADC_i32ErrCode to EADC_TIMEOUT_ERR if CALIF(CALSR[16]) is not set to 1. + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + uint32_t u32Delay = SystemCoreClock >> 4; + uint32_t u32ClkSel0Backup, u32EadcDivBackup, u32PclkDivBackup, u32RegLockBackup = 0; + + g_EADC_i32ErrCode = 0; + + eadc->CTL &= (~EADC_CTL_DIFFEN_Msk); + + eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); + + /* Do calibration for EADC to decrease the effect of electrical random noise. */ + if ((eadc->CALSR & EADC_CALSR_CALIF_Msk) == 0) + { + /* Must reset ADC before ADC calibration */ + eadc->CTL |= EADC_CTL_ADCRST_Msk; + while((eadc->CTL & EADC_CTL_ADCRST_Msk) == EADC_CTL_ADCRST_Msk) + { + if (--u32Delay == 0) + { + g_EADC_i32ErrCode = EADC_TIMEOUT_ERR; + break; + } + } + + /* Registers backup */ + u32ClkSel0Backup = CLK->CLKSEL0; + u32PclkDivBackup = CLK->PCLKDIV; + + u32RegLockBackup = SYS_IsRegLocked(); + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Set PCLK and EADC clock to the same frequency. */ + if (eadc == EADC0) + { + u32EadcDivBackup = CLK->CLKDIV0; + CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_EADC0DIV_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC0SEL_Msk) | CLK_CLKSEL0_EADC0SEL_HCLK; + } + else if (eadc == EADC1) + { + u32EadcDivBackup = CLK->CLKDIV2; + CLK->CLKDIV2 = (CLK->CLKDIV2 & ~CLK_CLKDIV2_EADC1DIV_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC1SEL_Msk) | CLK_CLKSEL0_EADC1SEL_HCLK; + } + else if (eadc == EADC2) + { + u32EadcDivBackup = CLK->CLKDIV5; + CLK->CLKDIV5 = (CLK->CLKDIV5 & ~CLK_CLKDIV5_EADC2DIV_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC2SEL_Msk) | CLK_CLKSEL0_EADC2SEL_HCLK; + } + CLK->PCLKDIV = (CLK->PCLKDIV & ~CLK_PCLKDIV_APB1DIV_Msk); + + eadc->CALSR |= EADC_CALSR_CALIF_Msk; /* Clear Calibration Finish Interrupt Flag */ + eadc->CALCTL = (eadc->CALCTL & ~(0x000F0000))|0x00020000; + eadc->CALCTL |= EADC_CALCTL_CAL_Msk; /* Enable Calibration function */ + + u32Delay = SystemCoreClock >> 4; + while((eadc->CALSR & EADC_CALSR_CALIF_Msk) != EADC_CALSR_CALIF_Msk) + { + if (--u32Delay == 0) + { + g_EADC_i32ErrCode = EADC_TIMEOUT_ERR; + + break; + } + } + + /* Restore registers */ + CLK->PCLKDIV = (CLK->PCLKDIV & ~CLK_PCLKDIV_APB1DIV_Msk) | (u32PclkDivBackup & CLK_PCLKDIV_APB1DIV_Msk); + if (eadc == EADC0) + { + CLK->CLKDIV0 = (u32EadcDivBackup & CLK_CLKDIV0_EADC0DIV_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC0SEL_Msk) | (u32ClkSel0Backup & CLK_CLKSEL0_EADC0SEL_Msk); + } + else if (eadc == EADC1) + { + CLK->CLKDIV2 = (u32EadcDivBackup & CLK_CLKDIV2_EADC1DIV_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC1SEL_Msk) | (u32ClkSel0Backup & CLK_CLKSEL0_EADC1SEL_Msk); + } + else if (eadc == EADC2) + { + CLK->CLKDIV5 = (u32EadcDivBackup & CLK_CLKDIV5_EADC2DIV_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_EADC2SEL_Msk) | (u32ClkSel0Backup & CLK_CLKSEL0_EADC2SEL_Msk); + } + if (u32RegLockBackup) + { + /* Lock protected registers */ + SYS_LockReg(); + } + } +} + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= ~EADC_CTL_ADCEN_Msk; +} + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : EADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : EADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_EPWM0TG0_TRIGGER : EPWM0TG0 trigger + * - \ref EADC_EPWM0TG1_TRIGGER : EPWM0TG1 trigger + * - \ref EADC_EPWM0TG2_TRIGGER : EPWM0TG2 trigger + * - \ref EADC_EPWM0TG3_TRIGGER : EPWM0TG3 trigger + * - \ref EADC_EPWM0TG4_TRIGGER : EPWM0TG4 trigger + * - \ref EADC_EPWM0TG5_TRIGGER : EPWM0TG5 trigger + * - \ref EADC_EPWM1TG0_TRIGGER : EPWM1TG0 trigger + * - \ref EADC_EPWM1TG1_TRIGGER : EPWM1TG1 trigger + * - \ref EADC_EPWM1TG2_TRIGGER : EPWM1TG2 trigger + * - \ref EADC_EPWM1TG3_TRIGGER : EPWM1TG3 trigger + * - \ref EADC_EPWM1TG4_TRIGGER : EPWM1TG4 trigger + * - \ref EADC_EPWM1TG5_TRIGGER : EPWM1TG5 trigger + * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger + * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. + * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk); + eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk); + eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + +/** + * @brief Set ADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, + * user can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk; + + eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + +} + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ebi.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ebi.c new file mode 100644 index 0000000..0d6e086 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ebi.c @@ -0,0 +1,193 @@ +/**************************************************************************//** + * @file ebi.c + * @version V3.00 + * @brief External Bus Interface(EBI) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + ((uint32_t)u32Bank * 0x10UL); + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + ((uint32_t)u32Bank * 0x10UL); + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + if(u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch(u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0UL; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318UL; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0UL; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318UL; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738UL; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738UL; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738UL; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL); + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index ); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL); + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (u32Bank * 0x10UL); + volatile uint32_t *pu32EBICTL = (uint32_t *)( u32Index0 ); + volatile uint32_t *pu32EBITCTL = (uint32_t *)( u32Index1 ); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/**@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EBI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ecap.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ecap.c new file mode 100644 index 0000000..7b81012 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_ecap.c @@ -0,0 +1,134 @@ +/**************************************************************************//** + * @file ecap.c + * @version V3.00 + * @brief Enhanced Input Capture Timer (ECAP) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions + @{ +*/ + +/** + * @brief Enable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @param[in] u32FuncMask Input capture function select + * - \ref ECAP_DISABLE_COMPARE + * - \ref ECAP_COMPARE_FUNCTION + * @return None + * @details This macro enable input capture function and select compare and reload function. + */ +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask) +{ + /* Clear Input capture mode*/ + ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk); + + /* Enable Input Capture and set mode */ + ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask); +} + + + +/** + * @brief Disable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @return None + * @details This macro disable input capture function. + */ +void ECAP_Close(ECAP_T* ecap) +{ + /* Disable Input Capture*/ + ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk; +} + +/** + * @brief This macro is used to enable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel Mask + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will enable the input channel_n interrupt. + */ +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Enable input channel interrupt */ + ecap->CTL0 |= (u32Mask); + + /* Enable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_EnableIRQ((IRQn_Type)ECAP0_IRQn); + } + else if(ecap == (ECAP_T*)ECAP1) + { + NVIC_EnableIRQ((IRQn_Type)ECAP1_IRQn); + } + else if(ecap == (ECAP_T*)ECAP2) + { + NVIC_EnableIRQ((IRQn_Type)ECAP2_IRQn); + } + else + { + NVIC_EnableIRQ((IRQn_Type)ECAP3_IRQn); + } +} + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel number + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will disable the input channel_n interrupt. + */ +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Disable input channel interrupt */ + ecap->CTL0 &= ~(u32Mask); + + /* Disable NVIC ECAP IRQ */ + if(ecap == (ECAP_T*)ECAP0) + { + NVIC_DisableIRQ((IRQn_Type)ECAP0_IRQn); + } + if(ecap == (ECAP_T*)ECAP1) + { + NVIC_DisableIRQ((IRQn_Type)ECAP1_IRQn); + } + if(ecap == (ECAP_T*)ECAP2) + { + NVIC_DisableIRQ((IRQn_Type)ECAP2_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)ECAP3_IRQn); + } +} + +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2021 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_epwm.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_epwm.c new file mode 100644 index 0000000..abc9979 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_epwm.c @@ -0,0 +1,1713 @@ +/**************************************************************************//** + * @file epwm.c + * @version V3.00 + * $Revision: 3 $ + * @brief EPWM driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + + +/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions + @{ +*/ + +/** + * @brief Configure EPWM capture and get the nearest unit time. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure EPWM capture and get the nearest unit time. + */ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint32_t u16Prescale = 1U, u16CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32EPWMClockSrc /= 1000U; + for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) + { + uint32_t u32Exit = 0U; + u32NearestUnitTimeNsec = (1000000U * u16Prescale) / u32EPWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + if(!((1000000U * (u16Prescale + 1U) > (u32NearestUnitTimeNsec * u32EPWMClockSrc)))) + { + u32Exit = 1U; + } + else + { + u32Exit = 0U; + } + } + else + { + u32Exit = 1U; + } + if (u32Exit == 1U) + { + break; + } + else {} + } + + /* convert to real register value */ + u16Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u16Prescale); + + /* set EPWM to down count type(edge aligned) */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))) | (1UL << (u32ChannelNum << 1U)); + /* set EPWM to auto-reload mode */ + (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum); + EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + return EPWM_ConfigOutputChannel2(epwm, u32ChannelNum, u32Frequency, u32DutyCycle*100, 1); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency / u32Frequency2 + * @param[in] u32HighDutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%... + * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2 + * @return Nearest frequency clock in nano second + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32HighDutyCycle, uint32_t u32Frequency2) +{ + uint32_t u32Src; + uint32_t u32EPWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + if(epwm == EPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk; + } + else /* (epwm == EPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk; + } + + if(u32Src == 0U) + { + /* clock source is from PLL clock */ + u32EPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + /* clock source is from PCLK */ + SystemCoreClockUpdate(); + if(epwm == EPWM0) + { + u32EPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (epwm == EPWM1) */ + { + u32EPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++) /* prescale could be 0~0xFFF */ + { + // Note: Support frequency < 1 + i = (uint64_t) u32EPWMClockSrc * u32Frequency2 / u32Frequency / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i < (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ + i = u32EPWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + u32Prescale -= 1U; + EPWM_SET_PRESCALER(epwm, (u32ChannelNum), u32Prescale); + /* set EPWM to up counter type(edge aligned) and auto-reload mode */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1U))|((1UL << EPWM_CTL1_CNTMODE0_Pos) << u32ChannelNum))); + + u32CNR -= 1U; + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + EPWM_SET_CMR(epwm, u32ChannelNum, u32HighDutyCycle * (u32CNR + 1U) / 10000U); + + (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_HIGH << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL0_ZPCTL0_Pos)); + (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1U))) | \ + ((uint32_t)EPWM_OUTPUT_LOW << ((u32ChannelNum << 1U) + (uint32_t)EPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start EPWM module. + */ +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN |= u32ChannelMask; +} + +/** + * @brief Stop EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM module. + */ +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->PERIOD[i] = 0U; + } + } +} + +/** + * @brief Stop EPWM generation immediately by clear channel enable bit + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM generation immediately by clear channel enable bit. + */ +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN &= ~u32ChannelMask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref EPWM_TRG_ADC_EVEN_ZERO + * - \ref EPWM_TRG_ADC_EVEN_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_ODD_ZERO + * - \ref EPWM_TRG_ADC_ODD_PERIOD + * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP + * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3U)); + (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4U) << 3U)); + (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4U) + { + (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3U)); + } + else + { + (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4U) << 3U)); + } +} + +/** + * @brief Enable and configure trigger ADC prescale + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32Prescale ADC prescale. Valid values are between 0 to 0xF. + * @param[in] u32PrescaleCnt ADC prescale counter. Valid values are between 0 to 0xF. + * @retval 0 Success. + * @retval -1 Failed. + * @details This function is used to enable and configure trigger ADC prescale. + * @note User can configure only when ADC trigger prescale is disabled. + * @note ADC prescale counter must less than ADC prescale. + */ +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt) +{ + /* User can write only when PSCENn(n = 0 ~ 5) is 0 */ + if ((epwm)->EADCPSCCTL & (1UL << u32ChannelNum)) + return (-1); + + if(u32ChannelNum < 4UL) + { + (epwm)->EADCPSC0 = ((epwm)->EADCPSC0 & ~((EPWM_EADCPSC0_EADCPSC0_Msk) << (u32ChannelNum << 3))) | \ + (u32Prescale << (u32ChannelNum << 3)); + (epwm)->EADCPSCNT0 = ((epwm)->EADCPSCNT0 & ~((EPWM_EADCPSCNT0_PSCNT0_Msk) << (u32ChannelNum << 3))) | \ + (u32PrescaleCnt << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCPSC1 = ((epwm)->EADCPSC1 & ~((EPWM_EADCPSC1_EADCPSC4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32Prescale << ((u32ChannelNum - 4UL) << 3)); + (epwm)->EADCPSCNT1 = ((epwm)->EADCPSCNT1 & ~((EPWM_EADCPSCNT1_PSCNT4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32PrescaleCnt << ((u32ChannelNum - 4UL) << 3)); + } + + (epwm)->EADCPSCCTL |= EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum; + + return 0; +} + +/** + * @brief Disable Trigger ADC prescale function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable trigger ADC prescale. + */ +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum))?1UL:0UL); +} + +/** + * @brief Enable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions: + * - \ref EPWM_TRIGGER_DAC_ZERO + * - \ref EPWM_TRIGGER_DAC_PERIOD + * - \ref EPWM_TRIGGER_DAC_COMPARE_UP + * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN + * @return None + * @details This function is used to enable selected channel to trigger DAC. + */ +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger DAC. + */ +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \ + EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @param[in] u32Condition The condition to trigger DAC. This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger DAC flag. + */ +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk; +} + +/** + * @brief Get selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @retval 0 The specified channel trigger DAC to start of conversion flag is not set + * @retval 1 The specified channel trigger DAC to start of conversion flag is set + * @details This function is used to get selected channel trigger DAC flag. + */ +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk)?1UL:0UL); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref EPWM_FB_EDGE_ADCRM + * - \ref EPWM_FB_EDGE_ACMP0 + * - \ref EPWM_FB_EDGE_ACMP1 + * - \ref EPWM_FB_EDGE_BKP0 + * - \ref EPWM_FB_EDGE_BKP1 + * - \ref EPWM_FB_EDGE_SYS_CSS + * - \ref EPWM_FB_EDGE_SYS_BOD + * - \ref EPWM_FB_EDGE_SYS_RAM + * - \ref EPWM_FB_EDGE_SYS_COR + * - \ref EPWM_FB_LEVEL_ADCRM + * - \ref EPWM_FB_LEVEL_ACMP0 + * - \ref EPWM_FB_LEVEL_ACMP1 + * - \ref EPWM_FB_LEVEL_BKP0 + * - \ref EPWM_FB_LEVEL_BKP1 + * - \ref EPWM_FB_LEVEL_SYS_CSS + * - \ref EPWM_FB_LEVEL_SYS_BOD + * - \ref EPWM_FB_LEVEL_SYS_RAM + * - \ref EPWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) + { + (epwm)->BRKCTL[i >> 1U] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk)); + (epwm)->FAILBRK |= (u32BrakeSource & 0xFU); + } + else + { + (epwm)->BRKCTL[i >> 1U] |= u32BrakeSource; + } + } + + if(u32LevelMask & (1UL << i)) + { + if((i & 0x1U) == 0U) + { + /* set brake action as high level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as high level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if((i & 0x1U) == 0U) + { + /* set brake action as low level for even channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as low level for odd channel */ + (epwm)->BRKCTL[i >> 1U] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1U] |= ((2U) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN |= u32ChannelMask; + (epwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN &= ~u32ChannelMask; + (epwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable EPWM output generation of selected channel(s). + */ +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable EPWM output generation of selected channel(s). + */ +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH + * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum & 0x1U; + (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1U) << 3U))) | \ + (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Disables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + */ +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + /* every two channels share the same setting */ + (epwm)->DTCTL |= (EPWM_DTCTL_RDTEN0_Msk << ((u32ChannelNum) >> 1U)) | (EPWM_DTCTL_FDTEN0_Msk << ((u32ChannelNum) >> 1U)); + (epwm)->RDTCNT[(u32ChannelNum) >> 1U] = u32Duration; + (epwm)->FDTCNT[(u32ChannelNum) >> 1U] = u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + /* every two channels shares the same setting */ + (epwm)->DTCTL &= ~((EPWM_DTCTL_RDTEN0_Msk << ((u32ChannelNum) >> 1U)) | (EPWM_DTCTL_FDTEN0_Msk << ((u32ChannelNum) >> 1U))); +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1) | \ + (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((uint32_t)(EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_PIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTSTS0_PIF0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 |= ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Zero interrupt flag of specified channel + * @retval 0 Zero interrupt did not occur + * @retval 1 Zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((1UL << EPWM_INTEN0_ZIEN0_Pos) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref EPWM_IFA_ZERO_POINT + * - \ref EPWM_IFA_PERIOD_POINT + * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator of selected channel. + */ +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \ + (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt) ); +} + +/** + * @brief Disable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to Disable interrupt flag accumulator of selected channel. + */ +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk)); +} + +/** + * @brief Enable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTSTS = (1UL << (u32ChannelNum)); +} + +/** + * @brief Get interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to Get interrupt flag accumulator interrupt of selected channel. + */ +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Enable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] |= EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Disable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] &= ~EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Clear free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear free trigger duty interrupt flag of selected channel. + */ +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U)); +} + +/** + * @brief Get free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Free trigger duty interrupt did not occur + * @retval 1 Free trigger duty interrupt occurred + * @details This function is used to get free trigger duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1U))) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Configure synchronization phase of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32SyncSrc EPWM synchronize source selection. + * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR + * - \ref EPWM_SYNC_OUT_DISABLE + * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing. + * - \ref EPWM_PHS_DIR_DECREMENT + * - \ref EPWM_PHS_DIR_INCREMENT + * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535. + * @return None + * @details This function is used to configure synchronization phase of selected channel. + * @note Every two channels share the same setting. + */ +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase) +{ + /* every two channels shares the same setting */ + u32ChannelNum >>= 1U; + (epwm)->SYNC = (((epwm)->SYNC & ~(((3UL << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U)) | ((1UL << EPWM_SYNC_PHSDIR0_Pos) << u32ChannelNum))) | \ + (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | ((u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1U))); + (epwm)->PHS[(u32ChannelNum)] = u32StartPhase; +} + + +/** + * @brief Enable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC |= ((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Disable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0U; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC &= ~((1UL << EPWM_SYNC_PHSEN0_Pos) << (i >> 1U)); + } + } +} + +/** + * @brief Enable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector. + * The valid value is 0~7. + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM SYNC_IN noise filter function. + */ +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \ + ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk); +} + +/** + * @brief Disable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC_IN noise filter function. + */ +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm) +{ + (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk; +} + +/** + * @brief Enable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to enable EPWM SYNC input pin inverse function. + */ +void EPWM_EnableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk; +} + +/** + * @brief Disable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC input pin inverse function. + */ +void EPWM_DisableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk); +} + +/** + * @brief Set EPWM clock source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel EPWM external clock source. + * - \ref EPWM_CLKSRC_EPWM_CLK + * - \ref EPWM_CLKSRC_TIMER0 + * - \ref EPWM_CLKSRC_TIMER1 + * - \ref EPWM_CLKSRC_TIMER2 + * - \ref EPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set EPWM clock source. + * @note Every two channels share the same setting. + * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1. + */ +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1U) << 3U))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1U) << 3U)); +} + +/** + * @brief Enable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM brake noise filter function. + */ +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3U))) | \ + (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake noise filter function. + */ +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Enable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable EPWM brake pin inverse function. + */ +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3U)); +} + +/** + * @brief Disable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake pin inverse function. + */ +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos)); +} + +/** + * @brief Set EPWM brake pin source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set EPWM brake pin source. + */ +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3U))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3U))); +} + +/** + * @brief Set EPWM leading edge blanking function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32TrigSrcSel Leading edge blanking source selection. + * - \ref EPWM_LEBCTL_SRCEN0 + * - \ref EPWM_LEBCTL_SRCEN2 + * - \ref EPWM_LEBCTL_SRCEN4 + * - \ref EPWM_LEBCTL_SRCEN0_2 + * - \ref EPWM_LEBCTL_SRCEN0_4 + * - \ref EPWM_LEBCTL_SRCEN2_4 + * - \ref EPWM_LEBCTL_SRCEN0_2_4 + * @param[in] u32TrigType Leading edge blanking trigger type. + * - \ref EPWM_LEBCTL_TRGTYPE_RISING + * - \ref EPWM_LEBCTL_TRGTYPE_FALLING + * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING + * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512. + This counter value decides leading edge blanking window size, and this counter clock base is ECLK. + * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE). + * - \ref FALSE + * - \ref TRUE + * @return None + * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition. + * @note EPWM leading edge blanking function is only used for brake source from ACMP. + */ +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable) +{ + (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable); + /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */ + (epwm)->LEBCNT = (u32BlankingCnt) - 1U; +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum); +} + +/** + * @brief Enable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32AfterPrescaler Fault Detect Clock Source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @param[in] u32ClkSel Fault Detect Clock Select. + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_1 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_2 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_4 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_8 + * @return None + * @details This function is used to enable fault detect of selected channel. + */ +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel) +{ + (epwm)->FDEN = ((epwm)->FDEN & ~(EPWM_FDEN_FDCKS0_Msk << (u32ChannelNum))) | \ + ((EPWM_FDEN_FDEN0_Msk | ((u32AfterPrescaler) << EPWM_FDEN_FDCKS0_Pos)) << (u32ChannelNum)); + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & ~EPWM_FDCTL0_FDCKSEL_Msk) | (u32ClkSel); +} + +/** + * @brief Disable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect of selected channel. + */ +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect output of selected channel. + */ +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect output of selected channel. + */ +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN |= (EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32DeglitchSmpCycle Deglitch Sampling Cycle. Valid values are between 0~7. + * @return None + * @details This function is used to enable fault detect deglitch function of selected channel. + */ +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_DGSMPCYC_Msk)) | \ + (EPWM_FDCTL0_FDDGEN_Msk | ((u32DeglitchSmpCycle) << EPWM_FDCTL0_DGSMPCYC_Pos)); +} + +/** + * @brief Disable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect deglitch function of selected channel. + */ +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDDGEN_Msk; +} + +/** + * @brief Enable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32MaskCnt Transition mask counter. Valid values are between 0~0x7F. + * @return None + * @details This function is used to enable fault detect mask function of selected channel. + */ +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_TRMSKCNT_Msk)) | (EPWM_FDCTL0_FDMSKEN_Msk | (u32MaskCnt)); +} + +/** + * @brief Disable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect mask function of selected channel. + */ +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDMSKEN_Msk; +} + +/** + * @brief Enable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect interrupt of selected channel. + */ +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN |= (EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect interrupt of selected channel. + */ +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN &= ~(EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Clear fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to clear fault detect interrupt of selected channel. + */ +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDSTS = (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum)); +} + +/** + * @brief Get fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @retval 0 Fault detect interrupt did not occur. + * @retval 1 Fault detect interrupt occurred. + * @details This function is used to Get fault detect interrupt of selected channel. + */ +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FDSTS & (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum))) ? 1UL : 0UL); +} + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_eqei.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_eqei.c new file mode 100644 index 0000000..e8417a1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_eqei.c @@ -0,0 +1,163 @@ +/**************************************************************************//** + * @file qei.c + * @version V3.00 + * @brief Enhanced Quadrature Encoder Interface (EQEI) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EQEI_Driver EQEI Driver + @{ +*/ + +/** @addtogroup EQEI_EXPORTED_FUNCTIONS EQEI Exported Functions + @{ +*/ + +/** + * @brief Close EQEI function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This function reset EQEI configuration and stop EQEI counting. + */ +void EQEI_Close(EQEI_T* eqei) +{ + /* Reset EQEI configuration */ + eqei->CTL = (uint32_t)0; +} + +/** + * @brief Disable EQEI interrupt + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref EQEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref EQEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref EQEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref EQEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function disable EQEI specified interrupt. + */ +void EQEI_DisableInt(EQEI_T* eqei, uint32_t u32IntSel) +{ + /* Disable EQEI specified interrupt */ + EQEI_DISABLE_INT(eqei, u32IntSel); + + /* Disable NVIC EQEI IRQ */ + if(eqei ==(EQEI_T*)EQEI0) + { + NVIC_DisableIRQ((IRQn_Type)EQEI0_IRQn); + } + else if(eqei ==(EQEI_T*)EQEI1) + { + NVIC_DisableIRQ((IRQn_Type)EQEI1_IRQn); + } + else if(eqei ==(EQEI_T*)EQEI2) + { + NVIC_DisableIRQ((IRQn_Type)EQEI2_IRQn); + } + else + { + NVIC_DisableIRQ((IRQn_Type)EQEI3_IRQn); + } +} + +/** + * @brief Enable EQEI interrupt + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref EQEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref EQEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref EQEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref EQEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function enable EQEI specified interrupt. + */ +void EQEI_EnableInt(EQEI_T* eqei, uint32_t u32IntSel) +{ + /* Enable EQEI specified interrupt */ + EQEI_ENABLE_INT(eqei, u32IntSel); + + /* Enable NVIC EQEI IRQ */ + if(eqei == (EQEI_T*)EQEI0) + { + NVIC_EnableIRQ(EQEI0_IRQn); + } + else if(eqei == (EQEI_T*)EQEI1) + { + NVIC_EnableIRQ(EQEI1_IRQn); + } + else if(eqei == (EQEI_T*)EQEI2) + { + NVIC_EnableIRQ(EQEI2_IRQn); + } + else + { + NVIC_EnableIRQ(EQEI3_IRQn); + } +} + +/** + * @brief Open EQEI in specified mode and enable input + * @param[in] eqei The pointer of the specified EQEI module. + * @param[in] u32Mode EQEI counting mode. + * - \ref EQEI_CTL_X4_FREE_COUNTING_MODE + * - \ref EQEI_CTL_X2_FREE_COUNTING_MODE + * - \ref EQEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref EQEI_CTL_X2_COMPARE_COUNTING_MODE + * - \ref EQEI_CTL_PHASE_COUNTING_MODE_TYPE1 + * - \ref EQEI_CTL_PHASE_COUNTING_MODE_TYPE2 + * - \ref EQEI_CTL_DIRECTIONAL_COUNTING_MODE + * @param[in] u32Value The counter maximum value in compare-counting mode. + * @return None + * @details This function set EQEI in specified mode and enable input. + */ +void EQEI_Open(EQEI_T* eqei, uint32_t u32Mode, uint32_t u32Value) +{ + /* Set EQEI function configuration */ + /* Set EQEI counting mode */ + /* Enable IDX, QEA and QEB input to EQEI controller */ + eqei->CTL = (eqei->CTL & (~EQEI_CTL_MODE_Msk)) | ((u32Mode) | EQEI_CTL_CHAEN_Msk | EQEI_CTL_CHBEN_Msk | EQEI_CTL_IDXEN_Msk); + + /* Set EQEI maximum count value in in compare-counting mode */ + eqei->CNTMAX = u32Value; +} + +/** + * @brief Start EQEI function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This function enable EQEI function and start EQEI counting. + */ +void EQEI_Start(EQEI_T* eqei) +{ + /* Enable EQEI controller function */ + eqei->CTL |= EQEI_CTL_QEIEN_Msk; +} + +/** + * @brief Stop EQEI function + * @param[in] eqei The pointer of the specified EQEI module. + * @return None + * @details This function disable EQEI function and stop EQEI counting. + */ +void EQEI_Stop(EQEI_T* eqei) +{ + /* Disable EQEI controller function */ + eqei->CTL &= (~EQEI_CTL_QEIEN_Msk); +} + + +/*@}*/ /* end of group EQEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EQEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2021 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_fmc.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_fmc.c new file mode 100644 index 0000000..680ca6f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_fmc.c @@ -0,0 +1,1197 @@ +/**************************************************************************//** + * @file fmc.c + * @version V1.00 + * @brief M460 series FMC driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include + +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +int32_t g_FMC_i32ErrCode; /*!< FMC global error code */ + +/** + * @brief Disable FMC ISP function. + * @return None + */ +void FMC_Close(void) +{ + FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk; +} + +/** + * @brief Config XOM Region + * @param[in] u32XomNum The XOM number(0~3) + * @param[in] u32XomBase The XOM region base address. + * @param[in] u8XomPage The XOM page number of region size. + * + * @retval 0 Success + * @retval 1 XOM is has already actived. + * @retval -1 Program failed. + * @retval -2 Invalid XOM number. + * + * @details Program XOM base address and XOM size(page) + * @note Global error code g_FMC_i32ErrCode + * -1 Program failed or program time-out + * -2 Invalid XOM number. + */ +int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if(u32XomNum >= 4UL) + { + g_FMC_i32ErrCode = -2; + ret = -2; + } + + if(ret == 0) + { + ret = FMC_GetXOMState(u32XomNum); + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u); + FMC->ISPDAT = u32XomBase; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u); + FMC->ISPDAT = u8XomPage; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 4096 bytes. + * @param[in] u32PageAddr Address of the flash page to be erased. + * It must be a 4096 bytes aligned address. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * + * @note Global error code g_FMC_i32ErrCode + * -1 Erase failed or erase time-out + */ +int32_t FMC_Erase(uint32_t u32PageAddr) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32PageAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_ERASE; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + + return ret; +} + + +/** + * @brief Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block. + * @param[in] u32BankAddr Base address of the flash bank to be erased. + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * + * @note Global error code g_FMC_i32ErrCode + * -1 Erase failed or erase time-out + */ +int32_t FMC_EraseBank(uint32_t u32BankAddr) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE; + FMC->ISPADDR = u32BankAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_ERASE; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + return ret; +} + +/** + * @brief Execute Erase XOM Region + * + * @param[in] u32XomNum The XOMRn(n=0~3) + * + * @return XOM erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * @retval -2 Invalid XOM number. + * + * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Program failed or program time-out + * -2 Invalid XOM number. + */ +int32_t FMC_EraseXOM(uint32_t u32XomNum) +{ + uint32_t u32Addr; + int32_t i32Active, err = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if(u32XomNum >= 4UL) + { + g_FMC_i32ErrCode = -2; + err = -2; + } + + if(err == 0) + { + i32Active = FMC_GetXOMState(u32XomNum); + + if(i32Active) + { + switch(u32XomNum) + { + case 0u: + u32Addr = (FMC->XOMR0STS & 0xFFFFFF00u) >> 8u; + break; + case 1u: + u32Addr = (FMC->XOMR1STS & 0xFFFFFF00u) >> 8u; + break; + case 2u: + u32Addr = (FMC->XOMR2STS & 0xFFFFFF00u) >> 8u; + break; + case 3u: + u32Addr = (FMC->XOMR3STS & 0xFFFFFF00u) >> 8u; + break; + default: + break; + } + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = 0x55aa03u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while(FMC->ISPTRG) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + err = -1; + break; + } + } + + /* Check ISPFF flag to know whether erase OK or fail. */ + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + err = -1; + } + } + else + { + err = -1; + } + } + return err; +} + +/** + * @brief Check the XOM is actived or not. + * + * @param[in] u32XomNum The xom number(0~3). + * + * @retval 1 XOM is actived. + * @retval 0 XOM is not actived. + * @retval -2 Invalid XOM number. + * + * @details To get specify XOMRn(n=0~3) active status + */ +int32_t FMC_GetXOMState(uint32_t u32XomNum) +{ + uint32_t u32act; + int32_t ret = 0; + + if(u32XomNum >= 4UL) + { + ret = -2; + } + + if(ret >= 0) + { + u32act = (((FMC->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum; + ret = (int32_t)u32act; + } + return ret; +} + +/** + * @brief Get the current boot source. + * @return The current boot source. + * @retval 0 Is boot from APROM. + * @retval 1 Is boot from LDROM. + * @retval 2 Is boot from Boot Loader. + */ +int32_t FMC_GetBootSource (void) +{ + if (FMC->ISPCTL & FMC_ISPCTL_BL_Msk) + { + return 2; + } + if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk) + { + return 1; + } + return 0; +} + + +/** + * @brief Enable FMC ISP function + * @return None + */ +void FMC_Open(void) +{ + FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Execute FMC_ISPCMD_READ command to read a word from flash. + * @param[in] u32Addr Address of the flash location to be read. + * It must be a word aligned address. + * @return The word data read from specified flash address. + * Return 0xFFFFFFFF if read failed. + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = u32Addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_READ; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + } + + return FMC->ISPDAT; +} + + +/** + * @brief Execute FMC_ISPCMD_READ_64 command to read a double-word from flash. + * @param[in] u32addr Address of the flash location to be read. + * It must be a double-word aligned address. + * @param[out] u32data0 Place holder of word 0 read from flash address u32addr. + * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + * + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_READ; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + else + { + *u32data0 = FMC->MPDAT0; + *u32data1 = FMC->MPDAT1; + } + return ret; +} + + +/** + * @brief Get the base address of Data Flash if enabled. + * @retval The base address of Data Flash + */ +uint32_t FMC_ReadDataFlashBaseAddr(void) +{ + return FMC->DFBA; +} + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * @param[in] i32BootSrc + * 1: Boot from LDROM + * 0: Boot from APROM + * @return None + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if(i32BootSrc) + { + FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */ + } + else + { + FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */ + } +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash. + * @param[in] u32Addr Address of the flash location to be programmed. + * It must be a word aligned address. + * @param[in] u32Data The word data to be programmed. + * @return 0 Success + * @return -1 Failed + * + * @note Global error code g_FMC_i32ErrCode + * -1 Read time-out + */ +int32_t FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = u32Data; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return -1; + } + } + + return 0; +} + +/** + * @brief Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash. + * @param[in] u32addr Address of the flash location to be programmed. + * It must be a double-word aligned address. + * @param[in] u32data0 The word data to be programmed to flash address u32addr. + * @param[in] u32data1 The word data to be programmed to flash address u32addr+4. + * @return 0 Success + * @return -1 Failed + * + * @note Global error code g_FMC_i32ErrCode + * -1 Program failed or time-out + */ +int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64; + FMC->ISPADDR = u32addr; + FMC->MPDAT0 = u32data0; + FMC->MPDAT1 = u32data1; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + return ret; +} + + +/** + * @brief Program Multi-Word data into specified address of flash. + * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into. + * This address must be 8-bytes aligned to flash address. + * @param[in] pu32Buf Buffer that carry the data chunk. + * @param[in] u32Len Length of the data chunk in bytes. + * @retval >=0 Number of data bytes were programmed. + * @retval -1 Program failed. + * @retval -2 Invalid address. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Program failed or time-out + * -2 Invalid address + */ +int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) +{ + int i, idx, retval = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if ((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) + { + g_FMC_i32ErrCode = -2; + return -2; + } + + u32Len = u32Len - (u32Len % 8); /* u32Len must be multiple of 8. */ + + idx = 0; + + while (u32Len >= 8) + { + FMC->ISPADDR = u32Addr; + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + for (i = 16; i < FMC_MULTI_WORD_PROG_LEN; ) + { + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->MPSTS & (FMC_MPSTS_D0_Msk | FMC_MPSTS_D1_Msk)) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return -1; + } + } + + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D0D1 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT0 = pu32Buf[idx++]; + FMC->MPDAT1 = pu32Buf[idx++]; + + if (i == FMC_MULTI_WORD_PROG_LEN/4) + break; // done + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->MPSTS & (FMC_MPSTS_D2_Msk | FMC_MPSTS_D3_Msk)) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return -1; + } + } + + retval += 8; + u32Len -= 8; + if (u32Len < 8) + { + return retval; + } + + if (!(FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk)) + { + /* printf(" [WARNING] busy cleared after D2D3 cleared!\n"); */ + i += 8; + break; + } + + FMC->MPDAT2 = pu32Buf[idx++]; + FMC->MPDAT3 = pu32Buf[idx++]; + } + + if (i != FMC_MULTI_WORD_PROG_LEN) + { + /* printf(" [WARNING] Multi-word program interrupted at 0x%x !!\n", i); */ + return retval; + } + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return -1; + } + } + + u32Addr += FMC_MULTI_WORD_PROG_LEN; + } + return retval; +} + + +/** + * @brief Program a 64-bits data to the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Program failed. + * @retval -2 Invalid OTP number. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Program failed or time-out + * -2 Invalid address + */ +int32_t FMC_WriteOTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if (otp_num > 255UL) + { + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL; + FMC->ISPDAT = low_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL; + FMC->ISPDAT = high_word; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Read the 64-bits data from the specified OTP. + * @param[in] otp_num The OTP number. + * @param[in] low_word Low word of the 64-bits data. + * @param[in] high_word Low word of the 64-bits data. + * @retval 0 Success + * @retval -1 Read failed. + * @retval -2 Invalid OTP number. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Read failed or time-out + * -2 Invalid OTP number + */ +int32_t FMC_ReadOTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if (otp_num > 255UL) + { + g_FMC_i32ErrCode = -2; + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_READ; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + else + { + *low_word = FMC->MPDAT0; + *high_word = FMC->MPDAT1; + } + } + return ret; +} + +/** + * @brief Lock the specified OTP. + * @param[in] otp_num The OTP number. + * @retval 0 Success + * @retval -1 Failed to write OTP lock bits. + * @retval -2 Invalid OTP number. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Failed to write OTP lock bits or write time-out + * -2 Invalid OTP number + */ +int32_t FMC_LockOTP(uint32_t otp_num) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if (otp_num > 255UL) + { + g_FMC_i32ErrCode = -2; + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPDAT = 0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + return ret; +} + +/** + * @brief Check the OTP is locked or not. + * @param[in] otp_num The OTP number. + * @retval 1 OTP is locked. + * @retval 0 OTP is not locked. + * @retval -1 Failed to read OTP lock bits. + * @retval -2 Invalid OTP number. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Failed to read OTP lock bits or read time-out + * -2 Invalid OTP number + */ +int32_t FMC_IsOTPLocked(uint32_t otp_num) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if (otp_num > 255UL) + { + g_FMC_i32ErrCode = -2; + ret = -2; + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_READ; + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + break; + } + } + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + else + { + if (FMC->ISPDAT != 0xFFFFFFFFUL) + { + g_FMC_i32ErrCode = -1; + ret = 1; /* Lock work was progrmmed. OTP was locked. */ + } + } + } + return ret; +} + +/** + * @brief Execute FMC_ISPCMD_READ command to read User Configuration. + * @param[out] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count Available word count in u32Config. + * @return Success or not. + * @retval 0 Success. + * @retval -1 Invalid parameter. + */ +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count) +{ + int32_t ret = 0; + + u32Config[0] = FMC_Read(FMC_CONFIG_BASE); + + if (u32Count < 2UL) + { + ret = -1; + } + else + { + u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4UL); + } + return ret; +} + + +/** + * @brief Execute ISP commands to erase then write User Configuration. + * @param[in] u32Config A two-word array. + * u32Config[0] holds CONFIG0, while u32Config[1] holds CONFIG1. + * @param[in] u32Count The number of User Configuration words to be written. + * @return Success or not. + * @retval 0 Success + * @retval -1 Failed + */ +int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count) +{ + int i; + + FMC_ENABLE_CFG_UPDATE(); + FMC_Erase(FMC_CONFIG_BASE); + + if ((FMC_Read(FMC_CONFIG_BASE) != 0xFFFFFFFF) || (FMC_Read(FMC_CONFIG_BASE+4) != 0xFFFFFFFF) || + (FMC_Read(FMC_CONFIG_BASE+8) != 0xFFFF5A5A)) + { + FMC_DISABLE_CFG_UPDATE(); + return -1; + } + + for (i = 0; i < u32Count; i++) + { + FMC_Write(FMC_CONFIG_BASE+i*4UL, u32Config[i]); + + if (FMC_Read(FMC_CONFIG_BASE+i*4UL) != u32Config[i]) + { + FMC_DISABLE_CFG_UPDATE(); + return -1; + } + } + + FMC_DISABLE_CFG_UPDATE(); + return 0; +} + + +/** + * @brief Run CRC32 checksum calculation and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @return Success or not. + * @retval 0 Success. + * @retval 0xFFFFFFFF Invalid parameter. + * + * @note Global error code g_FMC_i32ErrCode + * -1 Run/Read check sum time-out failed + * -2 u32addr or u32count must be aligned with 512 + */ +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + if ((u32addr % 512UL) || (u32count % 512UL)) + { + g_FMC_i32ErrCode = -2; + ret = 0xFFFFFFFF; + } + else + { + FMC->ISPCMD = FMC_ISPCMD_RUN_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_CHKSUM; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + } + + i32TimeOutCnt = FMC_TIMEOUT_CHKSUM; + FMC->ISPCMD = FMC_ISPCMD_READ_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_CHKSUM; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + return 0xFFFFFFFF; + } + } + + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Run flash all one verification and get result. + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF. + * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF. + * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred. + * + * @note Global error code g_FMC_i32ErrCode + * -1 RUN_ALL_ONE or CHECK_ALL_ONE commands time-out + */ +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret = READ_ALLONE_CMD_FAIL; + int32_t i32TimeOutCnt0, i32TimeOutCnt1; + + g_FMC_i32ErrCode = 0; + + FMC->ISPSTS = 0x80UL; /* clear check all one bit */ + + FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt0 = FMC_TIMEOUT_CHKALLONE; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) + { + if( i32TimeOutCnt0-- <= 0) + { + g_FMC_i32ErrCode = -1; + return READ_ALLONE_CMD_FAIL; + } + } + + i32TimeOutCnt1 = FMC_TIMEOUT_CHKALLONE; + do + { + FMC->ISPCMD = FMC_ISPCMD_READ_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt0 = FMC_TIMEOUT_CHKALLONE; + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) + { + if( i32TimeOutCnt0-- <= 0) + { + g_FMC_i32ErrCode = -1; + return READ_ALLONE_CMD_FAIL; + } + } + } + while ( (FMC->ISPDAT == 0UL) || (i32TimeOutCnt1-- > 0) ); + + if(i32TimeOutCnt1 <= 0) + { + g_FMC_i32ErrCode = -1; + return READ_ALLONE_CMD_FAIL; + } + + if ((FMC->ISPDAT == READ_ALLONE_YES) || (FMC->ISPDAT == READ_ALLONE_NOT)) + ret = FMC->ISPDAT; + else + { + g_FMC_i32ErrCode = -1; + ret = READ_ALLONE_CMD_FAIL; + } + + return ret; +} + +/** + * @brief Remap Bank0/Bank1 + * + * @param[in] u32Bank Bank Num which will remap to. + * + * @retval 0 Success + * @retval -1 Program failed. + * + * @details Remap Bank0/Bank1 + */ +int32_t FMC_RemapBank(uint32_t u32Bank) +{ + int32_t ret = 0; + int32_t i32TimeOutCnt; + + g_FMC_i32ErrCode = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_REMAP; + FMC->ISPADDR = u32Bank; + FMC->ISPDAT = 0x5AA55AA5UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + i32TimeOutCnt = FMC_TIMEOUT_WRITE; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) + { + if( i32TimeOutCnt-- <= 0) + { + g_FMC_i32ErrCode = -1; + ret = -1; + } + } + + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + g_FMC_i32ErrCode = -1; + ret = -1; + } + return ret; +} + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_gpio.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_gpio.c new file mode 100644 index 0000000..dc720dd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_gpio.c @@ -0,0 +1,180 @@ +/**************************************************************************//** + * @file gpio.c + * @version V3.00 + * @brief M460 series GPIO driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * @param[in] u32Mode Operation mode. It could be + * - \ref GPIO_MODE_INPUT + * - \ref GPIO_MODE_OUTPUT + * - \ref GPIO_MODE_OPEN_DRAIN + * - \ref GPIO_MODE_QUASI + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if((u32PinMask & (1ul << u32Idx)) == (1ul << u32Idx)) + { + port->MODE = (port->MODE & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be 0 ~ 14 for PC and PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 6 ~ 15 for PI GPIO port. \n + * It could be 0 ~ 13 for PJ GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be + * - \ref GPIO_INT_RISING + * - \ref GPIO_INT_FALLING + * - \ref GPIO_INT_BOTH_EDGE + * - \ref GPIO_INT_HIGH + * - \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + /* Configure interrupt mode of specified pin */ + port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); + + /* Enable interrupt function of specified pin */ + port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); +} + + +/** + * @brief Disable GPIO interrupt + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be 0 ~ 14 for PC and PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 6 ~ 15 for PI GPIO port. \n + * It could be 0 ~ 13 for PJ GPIO port. + * + * @return None + * + * @details This function is used to disable specified GPIO pin interrupt. + */ +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin) +{ + /* Configure interrupt mode of specified pin */ + port->INTTYPE &= ~(1UL << u32Pin); + + /* Disable interrupt function of specified pin */ + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * @param[in] u32Mode Slew rate mode. It could be + * - \ref GPIO_SLEWCTL_NORMAL + * - \ref GPIO_SLEWCTL_HIGH + * - \ref GPIO_SLEWCTL_FAST + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if(u32PinMask & (1ul << u32Idx)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + * @param[in] port GPIO port. It could be \ref PA, \ref PB, \ref PC, \ref PD, \ref PE, \ref PF, \ref PG, \ref PH, \ref PI or \ref PJ. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PE, PG and PH GPIO port. \n + * It could be BIT0 ~ BIT14 for PC and PD GPIO port. \n + * It could be BIT0 ~ BIT11 for PF GPIO port. \n + * It could be BIT6 ~ BIT15 for PI GPIO port. \n + * It could be BIT0 ~ BIT13 for PJ GPIO port. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * - \ref GPIO_PUSEL_DISABLE + * - \ref GPIO_PUSEL_PULL_UP + * - \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if(u32PinMask & (1ul << u32Idx)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/**@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_hbi.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_hbi.c new file mode 100644 index 0000000..35b5eae --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_hbi.c @@ -0,0 +1,301 @@ +/**************************************************************************//** + * @file hbi.c + * @version V3.00 + * @brief HyperBus Interface (HBI) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HBI_Driver HBI Driver + @{ +*/ + +int32_t g_HBI_i32ErrCode = 0; /*!< HBI global error code */ + +/** @addtogroup HBI_EXPORTED_FUNCTIONS HBI Exported Functions + @{ +*/ + + +/** + * @brief Reset HBI function + * @return None + * @note This function sets g_HBI_i32ErrCode to HBI_TIMEOUT_ERR if waiting Hyper RAM time-out. + */ +void HBI_ResetHyperRAM(void) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->CMD = HBI_CMD_RESET_HRAM; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief Exit from Hybrid sleep and deep Power down function + * @return None + * @note This function sets g_HBI_i32ErrCode to HBI_TIMEOUT_ERR if waiting Hyper RAM time-out. + */ +void HBI_ExitHSAndDPD(void) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->CMD = HBI_CMD_EXIT_HS_PD; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief Read HyperRAM register space + * @param[in] u32Addr Address of HyperRAM register space + * - \ref HYPERRAM_ID_REG0 : 0x0000_0000 = Identification Register 0 + * - \ref HYPERRAM_ID_REG1 : 0x0000_0002 = Identification Register 1 + * - \ref HYPERRAM_CONFIG_REG0 : 0x0000_1000 = Configuration Register 0 + * - \ref HYPERRAM_CONFIG_REG1 : 0x0000_1002 = Configuration Register 1 + * @return The data of HyperRAM register. + * @return -1 An illeagal register space + * @return -2 Wait Hyper RAM time-out + */ +int32_t HBI_ReadHyperRAMReg(uint32_t u32Addr) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + if( (u32Addr == HYPERRAM_ID_REG0) || (u32Addr == HYPERRAM_ID_REG1) || (u32Addr == HYPERRAM_CONFIG_REG0) || (u32Addr == HYPERRAM_CONFIG_REG1) ) + { + HBI->ADR = u32Addr; + HBI->CMD = HBI_CMD_READ_HRAM_REGISTER; + + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + return HBI_TIMEOUT_ERR; + } + } + return HBI->RDATA; + } + else + { + return -1; + } +} + +/** + * @brief Write HyperRAM register space + * @param[in] u32Addr Address of HyperRAM register space + * - \ref HYPERRAM_ID_REG0 : 0x0000_0000 = Identification Register 0 + * - \ref HYPERRAM_ID_REG1 : 0x0000_0002 = Identification Register 1 + * - \ref HYPERRAM_CONFIG_REG0 : 0x0000_1000 = Configuration Register 0 + * - \ref HYPERRAM_CONFIG_REG1 : 0x0000_1002 = Configuration Register 1 + * @param[in] + * @return 0 success. + * @return -1 An illeagal register space + * @return -2 Wait Hyper RAM time-out + */ +int32_t HBI_WriteHyperRAMReg(uint32_t u32Addr, uint32_t u32Value) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + if( (u32Addr == HYPERRAM_ID_REG0) || (u32Addr == HYPERRAM_ID_REG1) || (u32Addr == HYPERRAM_CONFIG_REG0) || (u32Addr == HYPERRAM_CONFIG_REG1) ) + { + HBI->ADR = u32Addr; + HBI->WDATA = u32Value; + HBI->CMD = HBI_CMD_WRITE_HRAM_REGISTER; + + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + return HBI_TIMEOUT_ERR; + } + } + return 0; + } + else + { + return -1; + } +} + +/** + * @brief Read 1 word from HyperRAM space + * @param[in] u32Addr Address of HyperRAM space + * @return The 16 bit data of HyperRAM space. + * @note This function sets g_HBI_i32ErrCode to HBI_TIMEOUT_ERR if waiting Hyper RAM time-out. + */ +uint32_t HBI_Read1Word(uint32_t u32Addr) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->ADR = u32Addr; + HBI->CMD = HBI_CMD_READ_HRAM_1_WORD; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } + return HBI->RDATA; +} + +/** + * @brief Read 2 word from HyperRAM space + * @param[in] u32Addr Address of HyperRAM space + * @return The 32bit data of HyperRAM space. + */ +uint32_t HBI_Read2Word(uint32_t u32Addr) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->ADR = u32Addr; + HBI->CMD = HBI_CMD_READ_HRAM_2_WORD; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } + return HBI->RDATA; +} + +/** + * @brief Write 1 byte to HyperRAM space + * @param[in] u32Addr Address of HyperRAM space + * @param[in] u8Data 8 bits data to be written to HyperRAM space + * @return None. + * @note This function sets g_HBI_i32ErrCode to HBI_TIMEOUT_ERR if waiting Hyper RAM time-out. + */ +void HBI_Write1Byte(uint32_t u32Addr, uint8_t u8Data) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->ADR = u32Addr; + HBI->WDATA = u8Data; + HBI->CMD = HBI_CMD_WRITE_HRAM_1_BYTE; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief Write 2 bytes to HyperRAM space + * @param[in] u32Addr Address of HyperRAM space + * @param[in] u16Data 16 bits data to be written to HyperRAM space + * @return None. + * @note This function sets g_HBI_i32ErrCode to HBI_TIMEOUT_ERR if waiting Hyper RAM time-out. + */ +void HBI_Write2Byte(uint32_t u32Addr, uint16_t u16Data) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->ADR = u32Addr; + HBI->WDATA = u16Data; + HBI->CMD = HBI_CMD_WRITE_HRAM_2_BYTE; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief Write 3 bytes to HyperRAM space + * @param[in] u32Addr Address of HyperRAM space + * @param[in] u32Data 24 bits data to be written to HyperRAM space + * @return None. + * @note This function sets g_HBI_i32ErrCode to HBI_TIMEOUT_ERR if waiting Hyper RAM time-out. + */ +void HBI_Write3Byte(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->ADR = u32Addr; + HBI->WDATA = u32Data; + HBI->CMD = HBI_CMD_WRITE_HRAM_3_BYTE; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief Write 4 byte to HyperRAM space + * @param[in] u32Addr Address of HyperRAM space + * @param[in] u32Data 32 bits data to be written to HyperRAM space + * @return None. + * @note This function sets g_HBI_i32ErrCode to HBI_TIMEOUT_ERR if waiting Hyper RAM time-out. + */ +void HBI_Write4Byte(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32TimeOutCnt = HBI_TIMEOUT; + + HBI->ADR = u32Addr; + HBI->WDATA = u32Data; + HBI->CMD = HBI_CMD_WRITE_HRAM_4_BYTE; + + g_HBI_i32ErrCode = 0; + while(HBI->CMD != HBI_CMD_HRAM_IDLE) + { + if( i32TimeOutCnt-- <= 0) + { + g_HBI_i32ErrCode = HBI_TIMEOUT_ERR; + break; + } + } +} + + +/*@}*/ /* end of group HBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_hsusbd.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_hsusbd.c new file mode 100644 index 0000000..a884293 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_hsusbd.c @@ -0,0 +1,741 @@ +/**************************************************************************//** + * @file hsusbd.c + * @version V3.00 + * @brief M460 series HSUSBD driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HSUSBD_Driver HSUSBD Driver + @{ +*/ + +/** @addtogroup HSUSBD_EXPORTED_FUNCTIONS HSUSBD Exported Functions + @{ +*/ +/*--------------------------------------------------------------------------*/ +/** @cond HIDDEN_SYMBOLS */ +/* Global variables for Control Pipe */ +S_HSUSBD_CMD_T gUsbCmd; +S_HSUSBD_INFO_T *g_hsusbd_sInfo; + +HSUSBD_VENDOR_REQ g_hsusbd_pfnVendorRequest = NULL; +HSUSBD_CLASS_REQ g_hsusbd_pfnClassRequest = NULL; +HSUSBD_SET_INTERFACE_REQ g_hsusbd_pfnSetInterface = NULL; +uint32_t g_u32HsEpStallLock = 0ul; /* Bit map flag to lock specified EP when SET_FEATURE */ + +static uint8_t *g_hsusbd_CtrlInPointer = 0; +static uint32_t g_hsusbd_CtrlMaxPktSize = 64ul; +static uint8_t g_hsusbd_UsbConfig = 0ul; +static uint8_t g_hsusbd_UsbAltInterface = 0ul; +static uint8_t g_hsusbd_EnableTestMode = 0ul; +static uint8_t g_hsusbd_TestSelector = 0ul; + +static uint8_t g_hsusbd_buf[12]; + +uint8_t volatile g_hsusbd_Configured = 0ul; +uint8_t g_hsusbd_CtrlZero = 0ul; +uint8_t g_hsusbd_UsbAddr = 0ul; +uint8_t g_hsusbd_ShortPacket = 0ul; +uint32_t volatile g_hsusbd_DmaDone = 0ul; +uint32_t g_hsusbd_CtrlInSize = 0ul; + +int32_t g_HSUSBD_i32ErrCode = 0; /*!< HSUSBD global error code */ +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief HSUSBD Initial + * + * @param[in] param Descriptor + * @param[in] pfnClassReq Class Request Callback Function + * @param[in] pfnSetInterface SetInterface Request Callback Function + * + * @return None + * + * @details This function is used to initial HSUSBD. + * + * @note This function sets g_HSUSBD_i32ErrCode to HSUSBD_TIMEOUT_ERR if waiting HSUSBD time-out. + */ +void HSUSBD_Open(S_HSUSBD_INFO_T *param, HSUSBD_CLASS_REQ pfnClassReq, HSUSBD_SET_INTERFACE_REQ pfnSetInterface) +{ + int32_t i32TimeOutCnt = HSUSBD_TIMEOUT; + + g_HSUSBD_i32ErrCode = 0; + + g_hsusbd_sInfo = param; + g_hsusbd_pfnClassRequest = pfnClassReq; + g_hsusbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_hsusbd_CtrlMaxPktSize = g_hsusbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ + HSUSBD_ENABLE_PHY(); + + /* wait PHY clock ready */ + while(!(HSUSBD->PHYCTL & HSUSBD_PHYCTL_PHYCLKSTB_Msk)) + { + if( i32TimeOutCnt-- < 0) + { + g_HSUSBD_i32ErrCode = HSUSBD_TIMEOUT_ERR; + break; + } + } + HSUSBD->OPER &= ~HSUSBD_OPER_HISPDEN_Msk; /* full-speed */ +} + +/** + * @brief HSUSBD Start + * + * @param[in] None + * + * @return None + * + * @details This function is used to start transfer + */ +void HSUSBD_Start(void) +{ + HSUSBD->OPER = HSUSBD_OPER_HISPDEN_Msk; /* high-speed */ + HSUSBD_CLR_SE0(); +} + +/** + * @brief Process Setup Packet + * + * @param[in] None + * + * @return None + * + * @details This function is used to process Setup packet. + */ +void HSUSBD_ProcessSetupPacket(void) +{ + /* Setup packet process */ + gUsbCmd.bmRequestType = (uint8_t)(HSUSBD->SETUP1_0 & 0xfful); + gUsbCmd.bRequest = (uint8_t)((HSUSBD->SETUP1_0 >> 8) & 0xfful); + gUsbCmd.wValue = (uint16_t)HSUSBD->SETUP3_2; + gUsbCmd.wIndex = (uint16_t)HSUSBD->SETUP5_4; + gUsbCmd.wLength = (uint16_t)HSUSBD->SETUP7_6; + + /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */ + switch(gUsbCmd.bmRequestType & 0x60ul) + { + case REQ_STANDARD: + { + HSUSBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if(g_hsusbd_pfnClassRequest != NULL) + { + g_hsusbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if(g_hsusbd_pfnVendorRequest != NULL) + { + g_hsusbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } +} + +/** + * @brief Get Descriptor request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process GetDescriptor request. + */ +int HSUSBD_GetDescriptor(void) +{ + uint32_t u32Len; + int val = 0; + + u32Len = gUsbCmd.wLength; + g_hsusbd_CtrlZero = (uint8_t)0ul; + + switch((gUsbCmd.wValue & 0xff00ul) >> 8) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = Minimum(u32Len, LEN_DEVICE); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8DevDesc, u32Len); + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + if((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8ConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FullConfigDesc[2] + (u32TotalLen << 8); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FullConfigDesc, u32Len); + } + + break; + } + /* Get BOS Descriptor */ + case DESC_BOS: + { + if(g_hsusbd_sInfo->gu8BosDesc == 0) + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + } + else + { + u32Len = Minimum(u32Len, LEN_BOS + LEN_BOSCAP); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8BosDesc, u32Len); + } + break; + } + /* Get Qualifier Descriptor */ + case DESC_QUALIFIER: + { + u32Len = Minimum(u32Len, LEN_QUALIFIER); + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8QualDesc, u32Len); + break; + } + /* Get Other Speed Descriptor - Full speed */ + case DESC_OTHERSPEED: + { + uint32_t u32TotalLen; + if((HSUSBD->OPER & 0x04ul) == 0x04ul) + { + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8HSOtherConfigDesc[2] + (u32TotalLen << 8); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HSOtherConfigDesc, u32Len); + } + else + { + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[3]; + u32TotalLen = g_hsusbd_sInfo->gu8FSOtherConfigDesc[2] + (u32TotalLen << 8); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8FSOtherConfigDesc, u32Len); + } + + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_hsusbd_sInfo->gu32ConfigHidDescIdx[gUsbCmd.wIndex & 0xfful]; + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if(u32Len > g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]) + { + u32Len = g_hsusbd_sInfo->gu32HidReportSize[gUsbCmd.wIndex & 0xfful]; + if((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8HidReportDesc[gUsbCmd.wIndex & 0xfful], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + if((gUsbCmd.wValue & 0xfful) < 8ul) + { + if(u32Len > g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]) + { + u32Len = g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful][0]; + if((u32Len % g_hsusbd_CtrlMaxPktSize) == 0ul) + { + g_hsusbd_CtrlZero = (uint8_t)1ul; + } + } + HSUSBD_PrepareCtrlIn((uint8_t *)g_hsusbd_sInfo->gu8StringDesc[gUsbCmd.wValue & 0xfful], u32Len); + } + else + { + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + } + break; + } + default: + /* Not support. Reply STALL. */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + val = 1; + break; + } + return val; +} + + +/** + * @brief Process USB standard request + * + * @param[in] None + * + * @return None + * + * @details This function is used to process USB Standard Request. + */ +void HSUSBD_StandardRequest(void) +{ + /* clear global variables for new request */ + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + + if((gUsbCmd.bmRequestType & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch(gUsbCmd.bRequest) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbConfig, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_DESCRIPTOR: + { + if(!HSUSBD_GetDescriptor()) + { + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + } + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + HSUSBD_PrepareCtrlIn((uint8_t *)&g_hsusbd_UsbAltInterface, 1ul); + + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + case GET_STATUS: + { + /* Device */ + if(gUsbCmd.bmRequestType == 0x80ul) + { + if((g_hsusbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + g_hsusbd_buf[0] = (uint8_t)1ul; /* Self-Powered */ + } + else + { + g_hsusbd_buf[0] = (uint8_t)0ul; /* bus-Powered */ + } + } + /* Interface */ + else if(gUsbCmd.bmRequestType == 0x81ul) + { + g_hsusbd_buf[0] = (uint8_t)0ul; + } + /* Endpoint */ + else if(gUsbCmd.bmRequestType == 0x82ul) + { + uint8_t ep = (uint8_t)(gUsbCmd.wIndex & 0xFul); + g_hsusbd_buf[0] = (uint8_t)HSUSBD_GetStall((uint32_t)ep) ? (uint8_t)1 : (uint8_t)0; + } + g_hsusbd_buf[1] = (uint8_t)0ul; + HSUSBD_PrepareCtrlIn(g_hsusbd_buf, 2ul); + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_INTKIF_Msk); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_INTKIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } + else + { + /* Host to device */ + switch(gUsbCmd.bRequest) + { + case CLEAR_FEATURE: + { + if((gUsbCmd.wValue & 0xfful) == FEATURE_ENDPOINT_HALT) + { + + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32HsEpStallLock is added to support it */ + epNum = (uint32_t)(gUsbCmd.wIndex & 0xFul); + for(i = 0ul; i < HSUSBD_MAX_EP; i++) + { + if((((HSUSBD->EP[i].EPCFG & 0xf0ul) >> 4) == epNum) && ((g_u32HsEpStallLock & (1ul << i)) == 0ul)) + { + HSUSBD->EP[i].EPRSPCTL = (HSUSBD->EP[i].EPRSPCTL & 0xeful) | HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_ADDRESS: + { + g_hsusbd_UsbAddr = (uint8_t)gUsbCmd.wValue; + /* Status Stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_CONFIGURATION: + { + g_hsusbd_UsbConfig = (uint8_t)gUsbCmd.wValue; + g_hsusbd_Configured = (uint8_t)1ul; + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_FEATURE: + { + if((gUsbCmd.wValue & 0x3ul) == 2ul) /* TEST_MODE */ + { + g_hsusbd_EnableTestMode = (uint8_t)1ul; + g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8); + } + if((gUsbCmd.wValue & 0x3ul) == 3ul) /* HNP ebable */ + { + HSOTG->CTL |= (HSOTG_CTL_HNPREQEN_Msk | HSOTG_CTL_BUSREQ_Msk); + } + + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + case SET_INTERFACE: + { + g_hsusbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue; + if(g_hsusbd_pfnSetInterface != NULL) + { + g_hsusbd_pfnSetInterface((uint32_t)g_hsusbd_UsbAltInterface); + } + /* Status stage */ + HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk); + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR); + HSUSBD_ENABLE_CEP_INT(HSUSBD_CEPINTEN_STSDONEIEN_Msk); + break; + } + default: + { + /* Setup error, stall the device */ + HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_STALLEN_Msk); + break; + } + } + } +} + +/** + * @brief Update Device State + * + * @param[in] None + * + * @return None + * + * @details This function is used to update Device state when Setup packet complete + */ +/** @cond HIDDEN_SYMBOLS */ +#define TEST_J 0x01ul +#define TEST_K 0x02ul +#define TEST_SE0_NAK 0x03ul +#define TEST_PACKET 0x04ul +#define TEST_FORCE_ENABLE 0x05ul +/** @endcond HIDDEN_SYMBOLS */ + +void HSUSBD_UpdateDeviceState(void) +{ + switch(gUsbCmd.bRequest) + { + case SET_ADDRESS: + { + HSUSBD_SET_ADDR(g_hsusbd_UsbAddr); + break; + } + case SET_CONFIGURATION: + { + if(g_hsusbd_UsbConfig == 0ul) + { + uint32_t volatile i; + /* Reset PID DATA0 */ + for(i = 0ul; i < HSUSBD_MAX_EP; i++) + { + if((HSUSBD->EP[i].EPCFG & 0x1ul) == 0x1ul) + { + HSUSBD->EP[i].EPRSPCTL = HSUSBD_EP_RSPCTL_TOGGLE; + } + } + } + break; + } + case SET_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_SetStall(idx); + } + else if(g_hsusbd_EnableTestMode) + { + g_hsusbd_EnableTestMode = (uint8_t)0ul; + if(g_hsusbd_TestSelector == TEST_J) + { + HSUSBD->TEST = TEST_J; + } + else if(g_hsusbd_TestSelector == TEST_K) + { + HSUSBD->TEST = TEST_K; + } + else if(g_hsusbd_TestSelector == TEST_SE0_NAK) + { + HSUSBD->TEST = TEST_SE0_NAK; + } + else if(g_hsusbd_TestSelector == TEST_PACKET) + { + HSUSBD->TEST = TEST_PACKET; + } + else if(g_hsusbd_TestSelector == TEST_FORCE_ENABLE) + { + HSUSBD->TEST = TEST_FORCE_ENABLE; + } + } + break; + } + case CLEAR_FEATURE: + { + if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT) + { + uint32_t idx; + idx = (uint32_t)(gUsbCmd.wIndex & 0xFul); + HSUSBD_ClearStall(idx); + } + break; + } + default: + break; + } +} + + +/** + * @brief Prepare Control IN transaction + * + * @param[in] pu8Buf Control IN data pointer + * @param[in] u32Size IN transfer size + * + * @return None + * + * @details This function is used to prepare Control IN transfer + */ +void HSUSBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + g_hsusbd_CtrlInPointer = pu8Buf; + g_hsusbd_CtrlInSize = u32Size; +} + + + +/** + * @brief Start Control IN transfer + * + * @param[in] None + * + * @return None + * + * @details This function is used to start Control IN + */ +void HSUSBD_CtrlIn(void) +{ + uint32_t volatile i, cnt; + uint8_t u8Value; + if(g_hsusbd_CtrlInSize >= g_hsusbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + cnt = g_hsusbd_CtrlMaxPktSize >> 2; + for(i = 0ul; i < cnt; i++) + { + HSUSBD->CEPDAT = *(uint32_t *)g_hsusbd_CtrlInPointer; + g_hsusbd_CtrlInPointer = (uint8_t *)(g_hsusbd_CtrlInPointer + 4ul); + } + HSUSBD_START_CEP_IN(g_hsusbd_CtrlMaxPktSize); + g_hsusbd_CtrlInSize -= g_hsusbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + cnt = g_hsusbd_CtrlInSize; + for(i = 0ul; i < cnt; i++) + { + u8Value = *(uint8_t *)(g_hsusbd_CtrlInPointer + i); + outpb(&HSUSBD->CEPDAT, u8Value); + } + + HSUSBD_START_CEP_IN(g_hsusbd_CtrlInSize); + g_hsusbd_CtrlInPointer = 0; + g_hsusbd_CtrlInSize = 0ul; + } +} + +/** + * @brief Start Control OUT transaction + * + * @param[in] pu8Buf Control OUT data pointer + * @param[in] u32Size OUT transfer size + * + * @return None + * + * @details This function is used to start Control OUT transfer + * + * @note This function sets g_HSUSBD_i32ErrCode to HSUSBD_TIMEOUT_ERR if waiting HSUSBD time-out. + */ +void HSUSBD_CtrlOut(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t volatile i; + int32_t i32TimeOutCnt = HSUSBD_TIMEOUT; + + g_HSUSBD_i32ErrCode = 0; + + while(1) + { + if((HSUSBD->CEPINTSTS & HSUSBD_CEPINTSTS_RXPKIF_Msk) == HSUSBD_CEPINTSTS_RXPKIF_Msk) + { + for(i = 0ul; i < u32Size; i++) + { + pu8Buf[i] = inpb(&HSUSBD->CEPDAT); + } + HSUSBD->CEPINTSTS = HSUSBD_CEPINTSTS_RXPKIF_Msk; + break; + } + + if( i32TimeOutCnt-- < 0) + { + g_HSUSBD_i32ErrCode = HSUSBD_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief Clear all software flags + * + * @param[in] None + * + * @return None + * + * @details This function is used to clear all software control flag + */ +void HSUSBD_SwReset(void) +{ + /* Reset all variables for protocol */ + g_hsusbd_UsbAddr = (uint8_t)0ul; + g_hsusbd_DmaDone = 0ul; + g_hsusbd_ShortPacket = (uint8_t)0ul; + g_hsusbd_Configured = (uint8_t)0ul; + + /* Reset USB device address */ + HSUSBD_SET_ADDR(0ul); +} + +/** + * @brief HSUSBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set HSUSBD vendor request callback function + */ +void HSUSBD_SetVendorRequest(HSUSBD_VENDOR_REQ pfnVendorReq) +{ + g_hsusbd_pfnVendorRequest = pfnVendorReq; +} + + +/*@}*/ /* end of group HSUSBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HSUSBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_i2c.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_i2c.c new file mode 100644 index 0000000..5fc92d5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_i2c.c @@ -0,0 +1,1661 @@ +/**************************************************************************//** + * @file i2c.c + * @version V3.00 + * @brief M460 series I2C driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +int32_t g_I2C_i32ErrCode = 0; /*!< I2C global error code */ + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C4) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C Controller */ + if((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; + } + else if((uint32_t)i2c == I2C1_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk; + } + else if((uint32_t)i2c == I2C2_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk; + } + else if((uint32_t)i2c == I2C3_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C3RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C3RST_Msk; + } + else if((uint32_t)i2c == I2C4_BASE) + { + SYS->IPRST1 |= SYS_IPRST2_I2C4RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST2_I2C4RST_Msk; + } + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + + if(u8Start) + { + u32Reg |= I2C_CTL_STA; + } + + if(u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + + if(u8Si) + { + u32Reg |= I2C_CTL_SI; + } + + if(u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + if(i2c == I2C4) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + return (u32Pclk / ((u32Divider + 1U) << 2U)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if(i2c == I2C4) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + uint32_t u32Value; + + if((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk) + { + u32Value = 1U; + } + else + { + u32Value = 0U; + } + + return u32Value; +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 2: + i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 3: + i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + case 0: + default: + i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1U) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 2: + i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 3: + i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1U; + break; + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1U; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +uint32_t I2C_SMBusGetStatus(I2C_T *i2c) +{ + return (i2c->BUSSTS); +} + +/** + * @brief Clear SMBus Interrupt Flag + * + * @param[in] i2c Specify I2C port + * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag + * + * @return None + * + * @details To clear flags of I2C_BUSSTS status register if interrupt set. + * + */ +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag) +{ + i2c->BUSSTS = u8SMBusIntFlag; +} + +/** + * @brief Set SMBus Bytes Counts of Transmission or Reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize) +{ + i2c->PKTSIZE = u32PktSize; +} + +/** + * @brief Init SMBus Host/Device Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0)) + * + * @return None + * + * @details Using SMBus communication must specify the port is a Host or a Device. + * + */ +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice) +{ + /* Clear BMHEN, BMDEN of BUSCTL Register */ + i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk); + + /* Set SMBus Host/Device Mode, and enable Bus Management*/ + if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) + { + i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } + else + { + i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } +} + +/** + * @brief Disable SMBus function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode. + * + */ +void I2C_SMBusClose(I2C_T *i2c) +{ + + i2c->BUSCTL = 0x00U; +} + +/** + * @brief Enable SMBus PEC Transmit Function + * + * @param[in] i2c Specify I2C port + * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE) + * + * @return None + * + * @details When enable CRC check function, the Host or Device needs to transmit CRC byte. + * + */ +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn) +{ + i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk; + + if(u8PECTxEn) + { + i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk); + } + else + { + i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk; + } +} + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return A byte is packet error check value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c) +{ + return (uint8_t)i2c->PKTCRC; +} + +/** + * @brief Calculate Time-out of SMBus idle period + * + * @param[in] i2c Specify I2C port + * @param[in] us Time-out length(us) + * @param[in] u32Hclk I2C peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Idle state. + * + */ + +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk) +{ + uint32_t u32Div, u32Hclk_kHz; + + i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; + u32Hclk_kHz = u32Hclk / 1000U; + u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U; + if(u32Div > 255U) + { + i2c->BUSTOUT = 0xFFU; + } + else + { + i2c->BUSTOUT = u32Div; + } + +} + +/** + * @brief Calculate Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in active state. + * Time-out length is calculate the SCL line "one clock" pull low timing. + * + */ + +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->BUSTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Calculate Cumulative Clock low Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Active state. + * Time-out length is calculate the SCL line "clocks" low cumulative timing. + * + */ + +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->CLKTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + + +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u, u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u, u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < 1u) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u, u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, data[u32txLen++]); + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u, u32TimeOutCount = 0U; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < 1u) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u, u32TimeOutCount = 0U; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < u32wLen) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + uint32_t u32TimeOutCount = 0U; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u, u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + uint32_t u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u, u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * @note This function sets g_I2C_i32ErrCode to I2C_TIMEOUT_ERR if waiting I2C time-out. + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u, u32TimeOutCount = 0u; + + g_I2C_i32ErrCode = 0; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = I2C_TIMEOUT; + I2C_WAIT_READY(i2c) + { + if(--u32TimeOutCount == 0) + { + g_I2C_i32ErrCode = I2C_TIMEOUT_ERR; + u8Err = 1u; + break; + } + } + + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_i2s.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_i2s.c new file mode 100644 index 0000000..017684b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_i2s.c @@ -0,0 +1,301 @@ +/**************************************************************************//** + * @file i2s.c + * @version V3.00 + * @brief M460 series I2S driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s); + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s is the base address of I2S module. + * @return I2S source clock frequency (Hz). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + uint32_t u32Freq, u32ClkSrcSel; + + if(i2s == I2S0) + { + /* get I2S selection clock source */ + u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk; + + switch(u32ClkSrcSel) + { + case CLK_CLKSEL3_I2S0SEL_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL3_I2S0SEL_PLL_DIV2: + u32Freq = (CLK_GetPLLClockFreq() >> 1); + break; + + case CLK_CLKSEL3_I2S0SEL_PCLK0: + u32Freq = CLK_GetPCLK0Freq(); + break; + + case CLK_CLKSEL3_I2S0SEL_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL3_I2S0SEL_HIRC48M: + u32Freq = __HIRC48M; + break; + + case CLK_CLKSEL3_I2S0SEL_PLLFN_DIV2: + u32Freq = (CLK_GetPLLFNClockFreq() >> 1); + break; + + default: + u32Freq = __HXT; + break; + } + } + else if(i2s == I2S1) + { + /* get I2S selection clock source */ + u32ClkSrcSel = CLK->CLKSEL2 & CLK_CLKSEL2_I2S1SEL_Msk; + + switch(u32ClkSrcSel) + { + case CLK_CLKSEL2_I2S1SEL_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL2_I2S1SEL_PLL_DIV2: + u32Freq = (CLK_GetPLLClockFreq() >> 1); + break; + + case CLK_CLKSEL2_I2S1SEL_PCLK1: + u32Freq = CLK_GetPCLK1Freq(); + break; + + case CLK_CLKSEL2_I2S1SEL_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL2_I2S1SEL_HIRC48M: + u32Freq = __HIRC48M; + break; + + case CLK_CLKSEL2_I2S1SEL_PLLFN_DIV2: + u32Freq = (CLK_GetPLLFNClockFreq() >> 1); + break; + + default: + u32Freq = __HXT; + break; + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32MonoData: Set audio data to mono or not. Valid values are: + * - \ref I2S_ENABLE_MONO + * - \ref I2S_DISABLE_MONO + * @param[in] u32DataFormat: Data format. This is also used to select I2S or PCM(TDM) function. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_I2S_MSB + * - \ref I2S_FORMAT_I2S_LSB + * - \ref I2S_FORMAT_PCM + * - \ref I2S_FORMAT_PCM_MSB + * - \ref I2S_FORMAT_PCM_LSB + * @return Real sample rate. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat) +{ + uint16_t u16Divider; + uint32_t u32BitRate, u32SrcClk; + + if(i2s == I2S0) + { + SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk; + } + else if(i2s == I2S1) + { + SYS->IPRST2 |= SYS_IPRST2_I2S1RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_I2S1RST_Msk; + } + + i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat; + i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + u32BitRate = u32SampleRate * (((u32WordWidth >> 4U) & 0x3U) + 1U) * 16U; + u16Divider = (uint16_t)((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; /* Round to the nearest integer */ + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8U); + + /* Calculate real sample rate */ + u32BitRate = u32SrcClk / (2U * ((uint32_t)u16Divider + 1U)); + u32SampleRate = u32BitRate / ((((u32WordWidth >> 4U) & 0x3U) + 1U) * 16U); + + i2s->CTL0 |= I2S_CTL0_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function and I2S clock. + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk; +} + +/** + * @brief This function enables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN |= u32Mask; +} + +/** + * @brief This function disables the interrupt according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return none + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN &= ~u32Mask; +} + +/** + * @brief Enable MCLK . + * @param[in] i2s is the base address of I2S module. + * @param[in] u32BusClock is the target MCLK clock + * @return Actual MCLK clock + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg, u32Clock; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u8Divider = 0U; + } + else + { + u8Divider = (uint8_t)(u32SrcClk / u32BusClock) >> 1U; + } + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider; + + i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk; + + if(u32Reg == 0U) + { + u32Clock = u32SrcClk; + } + else + { + u32Clock = (u32SrcClk >> 1U) / u32Reg; + } + + return u32Clock; +} + +/** + * @brief Disable MCLK . + * @param[in] i2s is the base address of I2S module. + * @return none + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 15. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 15. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTL1 = (i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) | + (u32TxThreshold << I2S_CTL1_TXTH_Pos) | + (u32RxThreshold << I2S_CTL1_RXTH_Pos); +} + +/** + * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChannelWidth Channel width. Valid values are: + * - \ref I2S_TDM_WIDTH_8BIT + * - \ref I2S_TDM_WIDTH_16BIT + * - \ref I2S_TDM_WIDTH_24BIT + * - \ref I2S_TDM_WIDTH_32BIT + * @param[in] u32ChannelNum Channel number. Valid values are: + * - \ref I2S_TDM_2CH + * - \ref I2S_TDM_4CH + * - \ref I2S_TDM_6CH + * - \ref I2S_TDM_8CH + * @param[in] u32SyncWidth Width for sync pulse. Valid values are: + * - \ref I2S_TDM_SYNC_ONE_BCLK + * - \ref I2S_TDM_SYNC_ONE_CHANNEL + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth) +{ + i2s->CTL0 = (i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) | + (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) | + (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) | + (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos); +} + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_keystore.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_keystore.c new file mode 100644 index 0000000..b38d55b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_keystore.c @@ -0,0 +1,722 @@ +/**************************************************************************//** + * @file keystore.c + * @version V3.00 + * @brief Key store driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KS_Driver Key Store Driver + @{ +*/ + +int32_t g_KS_i32ErrCode = 0; /*!< KS global error code */ + +/** @addtogroup KS_EXPORTED_FUNCTIONS Key Store Exported Functions + @{ +*/ + +/** + * @brief Initial key store + * @return None + * @details This function is used to initial the key store. + * It is necessary to be called before using other APIs of Key Store. + * @note This function sets g_KS_i32ErrCode to KS_TIMEOUT_ERR if waiting Key Store time-out. + */ +void KS_Open(void) +{ + uint32_t u32TimeOutCount; + + CLK->AHBCLK0 |= CLK_AHBCLK0_KSCKEN_Msk; + + g_KS_i32ErrCode = 0; + + if((KS->STS & KS_STS_INITDONE_Msk) == 0) + { + /* Waiting for busy */ + u32TimeOutCount = KS_TIMEOUT; + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + { + g_KS_i32ErrCode = KS_TIMEOUT_ERR; + break; + } + } + + /* Start Key Store Initial */ + KS->CTL = KS_CTL_INIT_Msk | KS_CTL_START_Msk; + + /* Waiting for initilization */ + u32TimeOutCount = KS_TIMEOUT; + while((KS->STS & KS_STS_INITDONE_Msk) == 0) + { + if(--u32TimeOutCount == 0) + { + g_KS_i32ErrCode = KS_TIMEOUT_ERR; + break; + } + } + } + + /* Waiting busy to make sure KS is ready. */ + u32TimeOutCount = KS_TIMEOUT; + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + { + g_KS_i32ErrCode = KS_TIMEOUT_ERR; + break; + } + } +} + + +/** + * @brief Read key from key store + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] i32KeyIdx The key index to read + * @param[out] au32Key The buffer to store the key + * @param[in] u32WordCnt The word (32-bit) count of the key buffer size + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to read the key. + */ + +int32_t KS_Read(KS_MEM_Type eType, int32_t i32KeyIdx, uint32_t au32Key[], uint32_t u32WordCnt) +{ + int32_t i32Cnt; + uint32_t u32Cont; + int32_t offset, i, cnt; + uint32_t u32TimeOutCount; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Specify the key address */ + KS->METADATA = ((uint32_t)eType << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + offset = 0; + u32Cont = 0; + i32Cnt = (int32_t)u32WordCnt; + do + { + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Trigger to read the key */ + KS->CTL = u32Cont | KS_OP_READ | KS_CTL_START_Msk; + /* Waiting for key store processing */ + u32TimeOutCount = KS_TIMEOUT; + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + /* Read the key to key buffer */ + cnt = i32Cnt; + if(cnt > 8) + cnt = 8; + for(i = 0; i < cnt; i++) + { + au32Key[offset + i] = KS->KEY[i]; + //printf("R[%d]:0x%08x\n", i, au32Key[offset+i]); + } + + u32Cont = KS_CTL_CONT_Msk; + i32Cnt -= 8; + offset += 8; + } + while(i32Cnt > 0); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + + return 0; +} + +/** + * @brief Get the word count of the specified Metadata key length + * @param[in] u32Meta The metadata define of the key length. It could be + \ref KS_META_128 + \ref KS_META_163 + \ref KS_META_192 + \ref KS_META_224 + \ref KS_META_233 + \ref KS_META_255 + \ref KS_META_256 + \ref KS_META_283 + \ref KS_META_384 + \ref KS_META_409 + \ref KS_META_512 + \ref KS_META_521 + \ref KS_META_571 + \ref KS_META_1024 + \ref KS_META_2048 + \ref KS_META_4096 + * @return The word (32-bit) count of the key + * @details This function is used to get word counts of the specified metadata key length. + * It could be used to know how may words needs to allocate for the key. + */ + +uint32_t KS_GetKeyWordCnt(uint32_t u32Meta) +{ + const uint16_t au8CntTbl[21] = { 4, 6, 6, 7, 8, 8, 8, 9, 12, 13, 16, 17, 18, 0, 0, 0, 32, 48, 64, 96, 128 }; + return au8CntTbl[((u32Meta & KS_METADATA_SIZE_Msk) >> KS_METADATA_SIZE_Pos)]; +} + +/** + * @brief Write key to key store +* @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + * @param[in] u32Meta The metadata of the key. It could be the combine of + \ref KS_META_AES + \ref KS_META_HMAC + \ref KS_META_RSA_EXP + \ref KS_META_RSA_MID + \ref KS_META_ECC + \ref KS_META_CPU + \ref KS_META_128 + \ref KS_META_163 + \ref KS_META_192 + \ref KS_META_224 + \ref KS_META_233 + \ref KS_META_255 + \ref KS_META_256 + \ref KS_META_283 + \ref KS_META_384 + \ref KS_META_409 + \ref KS_META_512 + \ref KS_META_521 + \ref KS_META_571 + \ref KS_META_1024 + \ref KS_META_2048 + \ref KS_META_4096 + \ref KS_META_BOOT + \ref KS_META_READABLE + \ref KS_META_PRIV + \ref KS_META_NONPRIV + \ref KS_META_SECURE + \ref KS_META_NONSECUR + + * @param[out] au32Key The buffer to store the key + * @param[in] u32WordCnt The word (32-bit) count of the key buffer size + * @return Index of the key. Failed when index < 0. + * @details This function is used to write a key to key store. + */ + +int32_t KS_Write(KS_MEM_Type eType, uint32_t u32Meta, uint32_t au32Key[]) +{ + int32_t i32Cnt; + uint32_t u32Cont; + int32_t i, cnt; + volatile int32_t offset; + uint32_t u32TimeOutCount; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Specify the key address */ + KS->METADATA = (eType << KS_METADATA_DST_Pos) | u32Meta; + + /* Get size index */ + i32Cnt = (int32_t)KS_GetKeyWordCnt(u32Meta); + + /* Invalid key length */ + if(i32Cnt == 0) + return -1; + + /* OTP only support maximum 256 bits */ + if((eType == KS_OTP) && (i32Cnt > 8)) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + offset = 0; + u32Cont = 0; + do + { + /* Prepare the key to write */ + cnt = i32Cnt; + if(cnt > 8) + cnt = 8; + for(i = 0; i < cnt; i++) + { + KS->KEY[i] = au32Key[offset + i]; + } +// for(;i < 8;i++) +// { +// KS->KEY[i] = 0; +// } + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Write the key */ + KS->CTL = u32Cont | KS_OP_WRITE | KS_CTL_START_Msk; + + u32Cont = KS_CTL_CONT_Msk; + i32Cnt -= 8; + offset += 8; + + /* Waiting for key store processing */ + u32TimeOutCount = KS_TIMEOUT; + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + } + while(i32Cnt > 0); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + { + //printf("KS_Write. EIF!\n"); + return -1; + } + + return KS_TOKEYIDX(KS->METADATA); +} + +/** + * @brief Erase a key from key store SRAM + * @param[in] i32KeyIdx The key index to read + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to erase a key from SRAM of key store. + */ +int32_t KS_EraseKey(int32_t i32KeyIdx) +{ + uint32_t u32TimeOutCount = KS_TIMEOUT; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = (KS_SRAM << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_ERASE | KS_CTL_START_Msk; + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + + +/** + * @brief Erase a key from key store OTP + * @param[in] i32KeyIdx The key index to erase + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to erase a key from key store OTP. + */ +int32_t KS_EraseOTPKey(int32_t i32KeyIdx) +{ + uint32_t u32TimeOutCount = KS_TIMEOUT; /* 1 second time-out */ + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = ((uint32_t)KS_OTP << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_ERASE | KS_CTL_START_Msk; + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + + + +/** + * @brief Lock the OTP key + * @param[in] i32KeyIdx The key index to lock + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to lock a key of KS OTP. + */ +int32_t KS_LockOTPKey(int32_t i32KeyIdx) +{ + uint32_t u32TimeOutCount = KS_TIMEOUT; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = ((uint32_t)KS_OTP << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_LOCK | KS_CTL_START_Msk; + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + +/** + * @brief Erase all keys from key store + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] i32KeyIdx The key index to read + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to erase all keys in SRAM or Flash of key store. + */ +int32_t KS_EraseAll(KS_MEM_Type eType) +{ + uint32_t u32TimeOutCount = KS_TIMEOUT; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = (eType << KS_METADATA_DST_Pos); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_ERASE_ALL | KS_CTL_START_Msk; + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + + + +/** + * @brief Revoke a key in key store + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] i32KeyIdx The key index to read + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to revoke a key in key store. + */ +int32_t KS_RevokeKey(KS_MEM_Type eType, int32_t i32KeyIdx) +{ + uint32_t u32TimeOutCount = KS_TIMEOUT; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = (eType << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_REVOKE | KS_CTL_START_Msk; + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + + +/** + * @brief Get remain size of specified Key Store memory + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + * @retval remain size of specified Key Store memory + * @details This function is used to get remain size of Key Store. + */ +uint32_t KS_GetRemainSize(KS_MEM_Type mem) +{ + uint32_t u32Reg; + uint32_t u32SramRemain, u32FlashRemain; + + u32Reg = KS->REMAIN; + //printf("KS Remain 0x%08x\n", u32Reg); + //printf("SRAM remain %lu bytes, Flash remain %lu bytes\n",(u32Reg&KS_REMAIN_RRMNG_Msk) >> KS_REMAIN_RRMNG_Pos, (u32Reg&KS_REMAIN_FRMNG_Msk) >> KS_REMAIN_FRMNG_Pos); + u32SramRemain = (u32Reg & KS_REMAIN_RRMNG_Msk) >> KS_REMAIN_RRMNG_Pos; + u32FlashRemain = (u32Reg & KS_REMAIN_FRMNG_Msk) >> KS_REMAIN_FRMNG_Pos; + + if(mem == KS_SRAM) + return u32SramRemain; + else + return u32FlashRemain; +} + + + +/** + * @brief Get remain key count of specified Key Store memory + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + * @retval Remain key count in the specified key store memory + * @details This function is used to get remain key count in specified key store memory. + */ +uint32_t KS_GetRemainKeyCount(KS_MEM_Type mem) +{ + uint32_t u32Reg; + uint32_t u32SramRemain, u32FlashRemain; + + u32Reg = KS->REMKCNT; + u32SramRemain = (u32Reg & KS_REMKCNT_RRMKCNT_Msk) >> KS_REMKCNT_RRMKCNT_Pos; + u32FlashRemain = (u32Reg & KS_REMKCNT_FRMKCNT_Msk) >> KS_REMKCNT_FRMKCNT_Pos; + + if(mem == KS_SRAM) + return u32SramRemain; + else + return u32FlashRemain; +} + + + +/** + * @brief Write OTP key to key store + * @param[in] i32KeyIdx The OTP key index to store the key. It could be 0~7. + OTP key index 0 is default for ROTPK. + * @param[in] u32Meta The metadata of the key. It could be the combine of + \ref KS_META_AES + \ref KS_META_HMAC + \ref KS_META_RSA_EXP + \ref KS_META_RSA_MID + \ref KS_META_ECC + \ref KS_META_CPU + \ref KS_META_128 + \ref KS_META_163 + \ref KS_META_192 + \ref KS_META_224 + \ref KS_META_233 + \ref KS_META_255 + \ref KS_META_256 + \ref KS_META_BOOT + \ref KS_META_READABLE + \ref KS_META_PRIV + \ref KS_META_NONPRIV + \ref KS_META_SECURE + \ref KS_META_NONSECUR + + * @param[out] au32Key The buffer to store the key + * @param[in] u32WordCnt The word (32-bit) count of the key buffer size + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to write a key to OTP key store. + */ +int32_t KS_WriteOTP(int32_t i32KeyIdx, uint32_t u32Meta, uint32_t au32Key[]) +{ + const uint16_t au8CntTbl[7] = {4, 6, 6, 7, 8, 8, 8}; + int32_t i32Cnt; + uint32_t u32Cont; + int32_t offset, i, cnt, sidx; + uint32_t u32TimeOutCount; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Specify the key address */ + KS->METADATA = ((uint32_t)KS_OTP << KS_METADATA_DST_Pos) | u32Meta | KS_TOMETAKEY(i32KeyIdx); + + /* Get size index */ + sidx = (u32Meta >> KS_METADATA_SIZE_Pos) & 0xful; + + /* OTP only support maximum 256 bits */ + if(sidx >= 7) + return -1; + + i32Cnt = au8CntTbl[sidx]; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + offset = 0; + u32Cont = 0; + do + { + /* Prepare the key to write */ + cnt = i32Cnt; + if(cnt > 8) + cnt = 8; + for(i = 0; i < cnt; i++) + { + KS->KEY[i] = au32Key[offset + i]; + } + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Write the key */ + KS->CTL = u32Cont | KS_OP_WRITE | KS_CTL_START_Msk; + + u32Cont = KS_CTL_CONT_Msk; + i32Cnt -= 8; + offset += 8; + + /* Waiting for key store processing */ + u32TimeOutCount = KS_TIMEOUT; + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + } + while(i32Cnt > 0); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + { + //printf("KS_WriteOTP. EIF!\n"); + return -1; + } + + return i32KeyIdx; +} + + +/** + * @brief Trigger to inverse the date in KS_SRAM. + * @retval 1 The data in KS SRAM is inverted. + * @retval 0 The data in KS SRAM is non-inverted. + * @retval -1 Fail to invert the date in KS SRAM. + * @details This function is used to trigger anti-remanence procedure by inverse the data in SRAM. + * This won't change the reading key. + */ + +int32_t KS_ToggleSRAM(void) +{ + uint32_t u32TimeOutCount = KS_TIMEOUT; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + + /* Specify the key address */ + KS->METADATA = ((uint32_t)KS_SRAM << KS_METADATA_DST_Pos); + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + /* Trigger to do anti-remanence procedure */ + KS->CTL = KS_OP_REMAN | KS_CTL_START_Msk; + + /* Waiting for key store processing */ + while(KS->STS & KS_STS_BUSY_Msk) + { + if(--u32TimeOutCount == 0) + return -1; + } + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return ((KS->STS & KS_STS_RAMINV_Msk) > 0); +} + + +/**@}*/ /* end of group KS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group KS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_kpi.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_kpi.c new file mode 100644 index 0000000..0b40bf2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_kpi.c @@ -0,0 +1,271 @@ +/**************************************************************************//** + * @file kpi.c + * @version V3.00 + * @brief KPI driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KPI_Driver KPI Driver + @{ +*/ + +/** @addtogroup KPI_EXPORTED_FUNCTIONS KPI Exported Functions + @{ +*/ + +static KPI_KEY_T *s_pKeyQueue = 0; +static volatile uint32_t s_u32MaxKeyCnt = 0; +static volatile uint32_t s_u32FirstKey = 0; +static volatile uint32_t s_u32LastKey = 0; + +__WEAK void KPI_KeyHandler(KPI_KEY_T key) + +{ + uint32_t u32Next; + + /* Move last to next available space */ + u32Next = s_u32LastKey + 1; + if(u32Next >= s_u32MaxKeyCnt) + u32Next = 0; // buffer wrap + if(u32Next == s_u32FirstKey) + return; // Queue full + + /* Push key to the queue */ + s_pKeyQueue[s_u32LastKey] = key; + s_u32LastKey = u32Next; + +} + + +void KPI_IRQHandler() +{ + int32_t i,j, idx, r; + uint32_t u32KeyPress[2], u32KeyRelease[2], status; + uint32_t row, col, mask; + KPI_KEY_T key; + + /* cache key events ASAP */ + status = KPI->STATUS; + u32KeyPress[0] = KPI->KPF[0]; + u32KeyPress[1] = KPI->KPF[1]; + u32KeyRelease[0] = KPI->KRF[0]; + u32KeyRelease[1] = KPI->KRF[1]; + + if(status & KPI_STATUS_KIF_Msk) + { + /* Get current row/column setting */ + row = ((KPI->CTL & KPI_CTL_KROW_Msk) >> KPI_CTL_KROW_Pos) + 1; + col = ((KPI->CTL & KPI_CTL_KCOL_Msk) >> KPI_CTL_KCOL_Pos) + 1; + + /* Deal with the key evernts */ + for(i=0;iKRF[idx] = mask; + + /* Record the key */ + key.x = i; + key.y = j; + key.st= KPI_RELEASE; + + /* call handler */ + KPI_KeyHandler(key); + } + } + } + } + + /* Deal with the key evernts */ + for(i=0;iKPF[idx] = mask; + + /* Record the key */ + key.x = i; + key.y = j; + key.st= KPI_PRESS; + + /* call handler */ + KPI_KeyHandler(key); + } + } + } + } + } + + if(status & KPI_STATUS_TKRIF_Msk) + { + /* Clear flag */ + KPI->STATUS = KPI_STATUS_TKRIF_Msk; + + printf("Three key press!!\n"); + + } + +} + + + +/** + * @brief Open Keypad interface + * + * @param[in] kpi The pointer of the specified KPI module. + * @param[in] u32Rows The number of key rows for key scan. it could be 2 ~ 6. + * @param[in] u32Columns The number of key columns for key scan. it could be 1 ~ 8. + * @param[in] keyQueue The FIFO queue of the key press/release status. + * + * @retval 0 Sucessful + * @retval -1 Failure + * + * @details The function is used to set row and column of keypad and start to key scan. + */ +int32_t KPI_Open(uint32_t u32Rows, uint32_t u32Columns, KPI_KEY_T *pkeyQueue, uint32_t u32MaxKeyCnt) +{ + /* Key ROW limitation */ + if((u32Rows < 2) || (u32Rows > 6)) + return -1; + + /* Key COLUMN limitation */ + if(u32Columns > 8) + return -1; + + /* Enable KPI Clock */ + CLK->APBCLK2 |= CLK_APBCLK2_KPICKEN_Msk; + + /* Seleck KPI Clock Source */ + CLK->CLKSEL3 |= CLK_CLKSEL3_KPISEL_HIRC; + + + /* Reset KPI */ + SYS->IPRST3 |= SYS_IPRST3_KPIRST_Msk; + SYS->IPRST3 ^= SYS_IPRST3_KPIRST_Msk; + + /* Set KPI */ + KPI->CTL = ((u32Rows-1) << KPI_CTL_KROW_Pos) | ((u32Columns-1) << KPI_CTL_KCOL_Pos) | + KPI_CTL_KIEN_Msk | KPI_CTL_KPIEN_Msk | KPI_CTL_KRIEN_Msk | + (3 << KPI_CTL_DBCLKSEL_Pos) | + KPI_CTL_KPEN_Msk; + + NVIC_EnableIRQ(KPI_IRQn); + + /* Set up the queue of key */ + s_pKeyQueue = pkeyQueue; + s_u32MaxKeyCnt = u32MaxKeyCnt; + s_u32FirstKey = 0; + s_u32LastKey = 0; + + return 0; +} + +/** + * @brief Close Keypad interface + * + * @details The function is used to stop and close key pad. + */ + +void KPI_Close() +{ + /* Disable Keypad */ + KPI->CTL = 0; +} + + +/** + * @brief Detect any key press + * + * + * @retval 1 Key pressed + * @retval 0 No key pressed + * + * @details The function is used to check if any key pressed. + */ +int32_t KPI_kbhit() +{ + if(s_u32FirstKey != s_u32LastKey) + return 1; + return 0; +} + + +/** + * @brief Get pressed/released key + * + * @return return the pressed key information. If no key pressed, return key index is 0xff, 0xff. + * + * @details The function is get the key pressed or key released. + */ +KPI_KEY_T KPI_GetKey() +{ + KPI_KEY_T key = {0xff,0xff,0xffff}; + + /* Check if queue is empty */ + if(s_u32FirstKey != s_u32LastKey) + { + /* Pop the key from queue */ + key = s_pKeyQueue[s_u32FirstKey++]; + + /* Wrap around check */ + if(s_u32FirstKey >= s_u32MaxKeyCnt) + s_u32FirstKey = 0; + } + + return key; +} + + +/** + * @brief Set key sample time + * + * @param[in] ms The key sample time in milliseconds. + * + * @details The function is used to set key sample time. The maximum time is 1398 milliseconds. + */ +void KPI_SetSampleTime(uint32_t ms) +{ + if(ms >= 1398) + ms = 1398; + + KPI->DLYCTL = 0x1F | ((__HIRC / 1000)*ms << 8); +} + + +/*@}*/ /* end of group KPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group KPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_pdma.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_pdma.c new file mode 100644 index 0000000..119f660 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_pdma.c @@ -0,0 +1,556 @@ +/**************************************************************************//** + * @file pdma.c + * @version V1.00 + * @brief PDMA driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +static uint8_t au8ChSelect[PDMA_CH_MAX]; + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask) +{ + uint32_t i; + + for(i = 0UL; i < (int)PDMA_CH_MAX; i++) + { + if((1 << i) & u32Mask) + { + (pdma)->DSCT[i].CTL = 0UL; + au8ChSelect[i] = (uint8_t)PDMA_MEM; + } + } + + (pdma)->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T * pdma) +{ + (pdma)->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + (pdma)->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen; + (pdma)->STRIDE[u32Ch].STCR = u32TransCount; +} + +/** + * @brief Set PDMA Repeat + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestInterval Destination address interval count + * @param[in] u32SrcInterval Source address interval count + * @param[in] u32RepeatCount Repeat count + * + * @return None + * + * @details This function set the selected repeat. + */ +void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount) +{ + (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + (pdma)->REPEAT[u32Ch].AICTL =((u32DestInterval)<<16) | (u32SrcInterval); + (pdma)->REPEAT[u32Ch].RCNT = u32RepeatCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + (pdma)->DSCT[u32Ch].SA = u32SrcAddr; + (pdma)->DSCT[u32Ch].DA = u32DstAddr; + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_USB_TX + * - \ref PDMA_USB_RX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_UART3_TX + * - \ref PDMA_UART3_RX + * - \ref PDMA_UART4_TX + * - \ref PDMA_UART4_RX + * - \ref PDMA_UART5_TX + * - \ref PDMA_UART5_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_QSPI1_TX + * - \ref PDMA_QSPI1_RX + * - \ref PDMA_EPWM0_P1_RX + * - \ref PDMA_EPWM0_P2_RX + * - \ref PDMA_EPWM0_P3_RX + * - \ref PDMA_EPWM1_P1_RX + * - \ref PDMA_EPWM1_P2_RX + * - \ref PDMA_EPWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_I2C2_TX + * - \ref PDMA_I2C2_RX + * - \ref PDMA_I2S0_TX + * - \ref PDMA_I2S0_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_EADC0_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_DAC1_TX + * - \ref PDMA_EPWM0_CH0_TX + * - \ref PDMA_EPWM0_CH1_TX + * - \ref PDMA_EPWM0_CH2_TX + * - \ref PDMA_EPWM0_CH3_TX + * - \ref PDMA_EPWM0_CH4_TX + * - \ref PDMA_EPWM0_CH5_TX + * - \ref PDMA_EPWM1_CH0_TX + * - \ref PDMA_EPWM1_CH1_TX + * - \ref PDMA_EPWM1_CH2_TX + * - \ref PDMA_EPWM1_CH3_TX + * - \ref PDMA_EPWM1_CH4_TX + * - \ref PDMA_EPWM1_CH5_TX + * - \ref PDMA_UART6_TX + * - \ref PDMA_UART6_RX + * - \ref PDMA_UART7_TX + * - \ref PDMA_UART7_RX + * - \ref PDMA_EADC1_RX + * - \ref PDMA_ACMP0 + * - \ref PDMA_ACMP1 + * - \ref PDMA_PSIO_TX + * - \ref PDMA_PSIO_RX + * - \ref PDMA_I2C3_TX + * - \ref PDMA_I2C3_RX + * - \ref PDMA_I2C4_TX + * - \ref PDMA_I2C4_RX + * - \ref PDMA_I2S1_TX + * - \ref PDMA_I2S1_RX + * - \ref PDMA_EINT0 + * - \ref PDMA_EINT1 + * - \ref PDMA_EINT2 + * - \ref PDMA_EINT3 + * - \ref PDMA_EINT4 + * - \ref PDMA_EINT5 + * - \ref PDMA_EINT6 + * - \ref PDMA_EINT7 + * - \ref PDMA_UART8_TX + * - \ref PDMA_UART8_RX + * - \ref PDMA_UART9_TX + * - \ref PDMA_UART9_RX + * - \ref PDMA_EADC2_RX + * - \ref PDMA_ACMP2 + * - \ref PDMA_ACMP3 + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + au8ChSelect[u32Ch] = (uint8_t)u32Peripheral; + switch(u32Ch) + { + case 0UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; + break; + case 1UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); + break; + case 2UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); + break; + case 3UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); + break; + case 4UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; + break; + case 5UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); + break; + case 6UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); + break; + case 7UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); + break; + case 8UL: + (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral; + break; + case 9UL: + (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos); + break; + case 10UL: + (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos); + break; + case 11UL: + (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos); + break; + case 12UL: + (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral; + break; + case 13UL: + (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos); + break; + case 14UL: + (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos); + break; + case 15UL: + (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos); + break; + default: + break; + } + + if(u32ScatterEn) + { + (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + (pdma)->DSCT[u32Ch].NEXT = u32DescAddr - ((pdma)->SCATBA); + } + else + { + (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + */ +void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + (pdma)->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + */ +void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask) +{ + (pdma)->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel, + * @param[in] u32OnOff Enable/disable time out function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + */ +void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + switch(u32Ch) + { + case 0UL: + (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; + break; + case 1UL: + (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); + break; + case 2UL: + (pdma)->TOC2_3 = ((pdma)->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt; + break; + case 3UL: + (pdma)->TOC2_3 = ((pdma)->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos); + break; + case 4UL: + (pdma)->TOC4_5 = ((pdma)->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt; + break; + case 5UL: + (pdma)->TOC4_5 = ((pdma)->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos); + break; + case 6UL: + (pdma)->TOC6_7 = ((pdma)->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt; + break; + case 7UL: + (pdma)->TOC6_7 = ((pdma)->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos); + break; + case 8UL: + (pdma)->TOC8_9 = ((pdma)->TOC8_9 & ~PDMA_TOC8_9_TOC8_Msk) | u32TimeOutCnt; + break; + case 9UL: + (pdma)->TOC8_9 = ((pdma)->TOC8_9 & ~PDMA_TOC8_9_TOC9_Msk) | (u32TimeOutCnt << PDMA_TOC8_9_TOC9_Pos); + break; + case 10UL: + (pdma)->TOC10_11 = ((pdma)->TOC10_11 & ~PDMA_TOC10_11_TOC10_Msk) | u32TimeOutCnt; + break; + case 11UL: + (pdma)->TOC10_11 = ((pdma)->TOC10_11 & ~PDMA_TOC10_11_TOC11_Msk) | (u32TimeOutCnt << PDMA_TOC10_11_TOC11_Pos); + break; + case 12UL: + (pdma)->TOC12_13 = ((pdma)->TOC12_13 & ~PDMA_TOC12_13_TOC12_Msk) | u32TimeOutCnt; + break; + case 13UL: + (pdma)->TOC12_13 = ((pdma)->TOC12_13 & ~PDMA_TOC12_13_TOC13_Msk) | (u32TimeOutCnt << PDMA_TOC12_13_TOC13_Pos); + break; + case 14UL: + (pdma)->TOC14_15 = ((pdma)->TOC14_15 & ~PDMA_TOC14_15_TOC14_Msk) | u32TimeOutCnt; + break; + case 15UL: + (pdma)->TOC14_15 = ((pdma)->TOC14_15 & ~PDMA_TOC14_15_TOC15_Msk) | (u32TimeOutCnt << PDMA_TOC14_15_TOC15_Pos); + break; + default: + break; + } + + if (u32OnOff) + { + (pdma)->TOUTEN |= (1UL << u32Ch); + } + else + { + (pdma)->TOUTEN &= ~(1UL << u32Ch); + } +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch) +{ + if(au8ChSelect[u32Ch] == PDMA_MEM) + { + (pdma)->SWREQ = (1UL << u32Ch); + } +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + (pdma)->INTEN |= (1UL << u32Ch); + break; + case PDMA_INT_TEMPTY: + (pdma)->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + (pdma)->TOUTIEN |= (1UL << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function disable the selected channel interrupt. + * @note The transfer done interrupt is disabled when table empty interrupt is disabled(PDMA_INT_TEMPTY). + */ +void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + (pdma)->INTEN &= ~(1UL << u32Ch); + break; + case PDMA_INT_TEMPTY: + (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + (pdma)->TOUTIEN &= ~(1UL << u32Ch); + break; + + default: + break; + } +} + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_qspi.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_qspi.c new file mode 100644 index 0000000..bab560c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_qspi.c @@ -0,0 +1,901 @@ +/**************************************************************************//** + * @file qspi.c + * @version V3.00 + * @brief M460 series QSPI driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue = 0U; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + if(qspi == QSPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + else if(qspi == QSPI1) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI1SEL_Msk)) | CLK_CLKSEL2_QSPI1SEL_PCLK1; + } + + /* Check clock source of QSPI */ + if(qspi == QSPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(qspi == QSPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + + /* Select PCLK as the clock source of QSPI */ + if(qspi == QSPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(qspi == QSPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI1SEL_Msk)) | CLK_CLKSEL2_QSPI1SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will reset QSPI controller. + */ +void QSPI_Close(QSPI_T *qspi) +{ + /* Reset QSPI */ + if(qspi == QSPI0) + { + SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk; + } + else if(qspi == QSPI1) + { + SYS->IPRST2 |= SYS_IPRST2_QSPI1RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_QSPI1RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + if(qspi == QSPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + else if(qspi == QSPI1) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI1SEL_Msk)) | CLK_CLKSEL2_QSPI1SEL_PCLK1; + } + + /* Check clock source of QSPI */ + if(qspi == QSPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(qspi == QSPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QSPIxSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of QSPI */ + if(qspi == QSPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(qspi == QSPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI1SEL_Msk) == CLK_CLKSEL2_QSPI1SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return QSPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVTOIF_Msk; + /* Check slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVTO_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if(u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & QSPI_SLVTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */ + } + + if(u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_SPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SPIENSTS_Msk; + /* Check SPIEN flag */ + if((u32Mask & QSPI_SPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_SPIEN_STS_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk; + /* Check QSPIx_SS line status */ + if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + +/** + * @brief Get QSPI status2. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_SLVBENUM_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Number = 0U; + + u32TmpStatus = qspi->STATUS2; + + /* Check effective bit number of uncompleted RX data status */ + if(u32Mask & QSPI_SLVBENUM_MASK) + { + u32Number = (u32TmpStatus & QSPI_STATUS2_SLVBENUM_Msk) >> QSPI_STATUS2_SLVBENUM_Pos; + } + + return u32Number; +} + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_rng.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_rng.c new file mode 100644 index 0000000..e606f22 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_rng.c @@ -0,0 +1,318 @@ +/**************************************************************************//** + * @file rng.c + * @version V3.01 + * @brief Show how to get true random number. + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RNG_Driver RNG Driver + @{ +*/ + + +/** @addtogroup RNG_EXPORTED_FUNCTIONS RNG Exported Functions + @{ +*/ + +typedef enum _RNG_KEY_SIZE +{ + KEY_128 = 0, + KEY_192 = 2, + KEY_224 = 3, + KEY_233 = 4, + KEY_255 = 5, + KEY_256 = 6, + KEY_283 = 7, + KEY_384 = 8, + KEY_409 = 9, + KEY_512 = 10, + KEY_521 = 11, + KEY_571 = 12 + +} eRNG_SZ; + + +/** + * @brief Basic Configuration of TRNG and PRNG + * + * @details The function is used to set the basic configuration for TRNG and PRNG. + */ +static void RNG_BasicConfig() +{ + int32_t i; + int32_t timeout = 0x1000000; + + /* Enable TRNG & PRNG */ + CLK->AHBCLK0 |= CLK_AHBCLK0_CRPTCKEN_Msk; + CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk; + + /* Use LIRC as TRNG engine clock */ + CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk; + while((CLK->STATUS & CLK_STATUS_LIRCSTB_Msk) == 0) + { + if(i++ > timeout) break; /* Wait LIRC time-out */ + } + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_TRNGSEL_Msk)) | CLK_CLKSEL2_TRNGSEL_LIRC; + +} + + + + +/** + * @brief Open random number generator + * + * @return 0 Successful + * -1 Failed + * + * @details The function is used to disable rng interrupt. + */ +int32_t RNG_Open() +{ + int32_t i; + int32_t timeout = 0x1000000; + + RNG_BasicConfig(); + + /* TRNG Activate */ + TRNG->ACT |= TRNG_ACT_ACT_Msk; + /* Waiting for ready */ + i = 0; + while((TRNG->CTL & TRNG_CTL_READY_Msk) == 0) + { + if(i++ > timeout) + { + /* TRNG ready timeout */ + return -1; + } + } + + /* CLKPSC is default to 0. The performance maybe low but suitable for any cases */ + TRNG->CTL = 0; + + /* Waiting for PRNG busy */ + i = 0; + while((CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) == CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + /* PRNG busy timeout */ + return -1; + } + } + + /* Reload seed from TRNG only at first time */ + CRPT->PRNG_CTL = (PRNG_KEY_SIZE_256 << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk | PRNG_CTL_SEEDSRC_TRNG; + + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + /* busy timeout */ + return -1; + } + } + + return 0; +} + + +/** + * @brief Get random words + * + * @param[in] pu32Buf Buffer pointer to store the random number + * + * @param[in] nWords Buffer size in word count. nWords must <= 8 + * + * @return Word count of random number in buffer + * + * @details The function is used to generate random numbers + */ +int32_t RNG_Random(uint32_t *pu32Buf, int32_t nWords) +{ + int32_t i; + int32_t timeout = 0x10000; + + /* Waiting for Busy */ + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(timeout-- < 0) + return 0; + } + + if(nWords > 8) + nWords = 8; + + /* Trig to generate seed 256 bits random number */ + CRPT->PRNG_CTL = (6 << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk; + + timeout = 0x10000; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(timeout-- < 0) + return 0; + } + + for(i = 0; i < nWords; i++) + { + pu32Buf[i] = CRPT->PRNG_KEY[i]; + } + + return nWords; +} + + + +/** + * @brief Initial function for ECDSA key generator for Key Store + * + * @param[in] u32KeySize It could be PRNG_KEY_SIZE_128 ~ PRNG_KEY_SIZE_571 + * + * @param[in] au32ECC_N The N value of specified ECC curve. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is initial funciton of RNG_ECDSA function. + * This funciton should be called before calling RNG_ECDSA(). + */ +int32_t RNG_ECDSA_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]) +{ + int32_t i; + + /* Initial TRNG and PRNG for random number */ + if(RNG_Open()) + return -1; + + /* It is necessary to set ECC_N for ECDSA */ + for(i = 0; i < 18; i++) + CRPT->ECC_N[i] = au32ECC_N[i]; + + CRPT->PRNG_KSCTL = (KS_OWNER_ECC << CRPT_PRNG_KSCTL_OWNER_Pos) | + CRPT_PRNG_KSCTL_ECDSA_Msk | + (CRPT_PRNG_KSCTL_WDST_Msk) | + (KS_SRAM << CRPT_PRNG_KSCTL_WSDST_Pos); + + return 0; +} + + +/** + * @brief To generate a key to KS SRAM for ECDSA. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is used to generate a key to KS SRAM for ECDSA. + * This key is necessary for ECDSA+Key Store function of ECC. + */ +int32_t RNG_ECDSA(uint32_t u32KeySize) +{ + + int32_t timeout; + int32_t i; + + /* Reload seed only at first time */ + CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk | PRNG_CTL_SEEDSRC_TRNG; + + timeout = 0x10000; + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + return -1; + } + } + + if(CRPT->PRNG_KSSTS & CRPT_PRNG_KSSTS_KCTLERR_Msk) + { + return -1; + } + + return (CRPT->PRNG_KSSTS & CRPT_PRNG_KSCTL_NUM_Msk); +} + + + +/** + * @brief Initial funciton for RNG_ECDH. + * + * @param[in] u32KeySize It could be PRNG_KEY_SIZE_128 ~ PRNG_KEY_SIZE_571 + * + * @param[in] au32ECC_N The N value of specified ECC curve. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is initial function of RNG_ECDH. + * + */ +int32_t RNG_ECDH_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]) +{ + int32_t i; + + /* Initial Random Number Generator */ + if(RNG_Open()) + return -1; + + /* It is necessary to set ECC_N for ECDSA */ + for(i = 0; i < 18; i++) + CRPT->ECC_N[i] = au32ECC_N[i]; + + CRPT->PRNG_KSCTL = (KS_OWNER_ECC << CRPT_PRNG_KSCTL_OWNER_Pos) | + (CRPT_PRNG_KSCTL_ECDH_Msk) | + (CRPT_PRNG_KSCTL_WDST_Msk) | + (KS_SRAM << CRPT_PRNG_KSCTL_WSDST_Pos); + + return 0; +} + + +/** + * @brief To generate a key to KS SRAM for ECDH. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is used to generate a key to KS SRAM for ECDH. + * This key is necessary for ECDH+Key Store function of ECC. + */ +int32_t RNG_ECDH(uint32_t u32KeySize) +{ + int32_t timeout; + int32_t i; + + /* Reload seed only at first time */ + CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk | PRNG_CTL_SEEDSRC_TRNG; + + timeout = 0x10000; + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + return -1; + } + + if(CRPT->PRNG_KSSTS & CRPT_PRNG_KSSTS_KCTLERR_Msk) + return -1; + + return (CRPT->PRNG_KSSTS & CRPT_PRNG_KSCTL_NUM_Msk); +} + +/**@}*/ /* end of group RNG_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RNG_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_rtc.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_rtc.c new file mode 100644 index 0000000..fb485ed --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_rtc.c @@ -0,0 +1,1178 @@ +/**************************************************************************//** + * @file rtc.c + * @version V3.00 + * @brief Real Time Clock(RTC) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/** @endcond HIDDEN_SYMBOLS */ + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +int32_t g_RTC_i32ErrCode = 0; /*!< RTC global error code */ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @retval 0: SUCCESS + * @retval -1: Initialize RTC module fail + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * 4. Enable frequency dynamic compensation function. \n + * @note Null pointer for using default starting date/time. + */ +int32_t RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + RTC->INIT = RTC_INIT_KEY; + + if(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + RTC->INIT = RTC_INIT_KEY; + while(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + if(--u32TimeOutCount == 0) return -1; + } + } + + if(sPt != 0) + { + /* Enable frequency dynamic compensation function */ + RTC->CLKFMT |= RTC_CLKFMT_DCOMPEN_Msk; + + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + } + + return 0; +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock. + */ +void RTC_Close(void) +{ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; +} + +/** + * @brief Set 32K Frequency Compensation Data + * + * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512. + * + * @return None + * + * @details This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application. + * + * @note This function sets g_RTC_i32ErrCode to RTC_TIMEOUT_ERR if waiting RTC time-out. + */ +void RTC_32KCalibration(int32_t i32FrequencyX10000) +{ + int32_t i32RegInt, i32RegFra; + uint32_t u32TimeOutCount = SystemCoreClock<<1; /* 2 second time-out */ + + g_RTC_i32ErrCode = 0; + + /* Compute integer and fraction for RTC FCR register */ + i32RegInt = (i32FrequencyX10000 / 10000) - RTC_FCR_REFERENCE; + i32RegFra = ((((i32FrequencyX10000 % 10000)) * 64) + 5000) / 10000; + + if(i32RegFra >= 0x40) + { + i32RegFra = 0x0; + i32RegInt++; + } + + /* Judge Integer part is reasonable */ + if((i32RegInt >= 0) && (i32RegInt <= 31)) + { + u32TimeOutCount = SystemCoreClock<<1; /* 2 second time-out */ + while((RTC->FREQADJ & RTC_FREQADJ_FCRBUSY_Msk) == RTC_FREQADJ_FCRBUSY_Msk) + if(--u32TimeOutCount == 0) + { + g_RTC_i32ErrCode = RTC_TIMEOUT_ERR; + break; + } + RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra); + u32TimeOutCount = SystemCoreClock<<1; /* 2 second time-out */ + while((RTC->FREQADJ & RTC_FREQADJ_FCRBUSY_Msk) == RTC_FREQADJ_FCRBUSY_Msk) + if(--u32TimeOutCount == 0) + { + g_RTC_i32ErrCode = RTC_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10UL); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10UL); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10UL); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21UL) + { + sPt->u32AmPm = (uint32_t)RTC_PM; + sPt->u32Hour -= 20UL; + } + else + { + sPt->u32AmPm = (uint32_t)RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10UL); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10UL); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10UL); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21UL) + { + sPt->u32AmPm = (uint32_t)RTC_PM; + sPt->u32Hour -= 20UL; + } + else + { + sPt->u32AmPm = (uint32_t)RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if(sPt != 0) + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == (uint32_t)RTC_PM) + { + sPt->u32Hour += 20UL; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set Day of the Week */ + RTC->WEEKDAY = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCAL |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCAL |= ((sPt->u32Month / 10UL) << 12); + u32RegCAL |= ((sPt->u32Month % 10UL) << 8); + u32RegCAL |= ((sPt->u32Day / 10UL) << 4); + u32RegCAL |= (sPt->u32Day % 10UL); + + u32RegTIME = ((sPt->u32Hour / 10UL) << 20); + u32RegTIME |= ((sPt->u32Hour % 10UL) << 16); + u32RegTIME |= ((sPt->u32Minute / 10UL) << 12); + u32RegTIME |= ((sPt->u32Minute % 10UL) << 8); + u32RegTIME |= ((sPt->u32Second / 10UL) << 4); + u32RegTIME |= (sPt->u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC->CAL = (uint32_t)u32RegCAL; + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if(sPt != 0) + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == (uint32_t)RTC_PM) + { + sPt->u32Hour += 20UL; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCALM |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCALM |= ((sPt->u32Month / 10UL) << 12); + u32RegCALM |= ((sPt->u32Month % 10UL) << 8); + u32RegCALM |= ((sPt->u32Day / 10UL) << 4); + u32RegCALM |= (sPt->u32Day % 10UL); + + u32RegTALM = ((sPt->u32Hour / 10UL) << 20); + u32RegTALM |= ((sPt->u32Hour % 10UL) << 16); + u32RegTALM |= ((sPt->u32Minute / 10UL) << 12); + u32RegTALM |= ((sPt->u32Minute % 10UL) << 8); + u32RegTALM |= ((sPt->u32Second / 10UL) << 4); + u32RegTALM |= (sPt->u32Second % 10UL); + + RTC->CALM = (uint32_t)u32RegCALM; + RTC->TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCAL |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCAL |= ((u32Month / 10UL) << 12); + u32RegCAL |= ((u32Month % 10UL) << 8); + u32RegCAL |= ((u32Day / 10UL) << 4); + u32RegCAL |= (u32Day % 10UL); + + + /* Set Day of the Week */ + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM)) + { + u32Hour += 20UL; + } + + u32RegTIME = ((u32Hour / 10UL) << 20); + u32RegTIME |= ((u32Hour % 10UL) << 16); + u32RegTIME |= ((u32Minute / 10UL) << 12); + u32RegTIME |= ((u32Minute % 10UL) << 8); + u32RegTIME |= ((u32Second / 10UL) << 4); + u32RegTIME |= (u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(u32TimeMode == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCALM |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCALM |= ((u32Month / 10UL) << 12); + u32RegCALM |= ((u32Month % 10UL) << 8); + u32RegCALM |= ((u32Day / 10UL) << 4); + u32RegCALM |= (u32Day % 10UL); + + + /* Set RTC Alarm Date */ + RTC->CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM)) + { + u32Hour += 20UL; + } + + u32RegTALM = ((u32Hour / 10UL) << 20); + u32RegTALM |= ((u32Hour % 10UL) << 16); + u32RegTALM |= ((u32Minute / 10UL) << 12); + u32RegTALM |= ((u32Minute % 10UL) << 8); + u32RegTALM |= ((u32Second / 10UL) << 4); + u32RegTALM |= (u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(u32TimeMode == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set RTC Alarm Time */ + RTC->TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + RTC->INTEN &= ~u32IntFlagMask; + RTC->INTSTS = u32IntFlagMask; +} + +/** + * @brief Enable Spare Registers Access + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare registers 0~19 can be accessed. + */ +void RTC_EnableSpareAccess(void) +{ + RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~19 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER0_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER5_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT + * - \ref RTC_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + * User need disable dynamic tamper function before use this API. + */ +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) | + (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos)); + + for(i = 0UL; i < (uint32_t)RTC_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4UL)); + u32Reg |= (u32TmpReg << (i * 4UL)); + } + } + + RTC->TAMPCTL = u32Reg; + +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER0_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER5_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void RTC_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk); + + for(i = 0UL; i < (uint32_t)RTC_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << (i * 4UL)); + } + } + + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Detect + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select + * 0: Pair 2 source select tamper 4 + * 1: Pair 2 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the dynamic tamper. + */ +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2Debounce, u32Tamper4Debounce; + + u32Reg = RTC->TAMPCTL; + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + + u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk; + u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk; + + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk); + u32Reg |= ((u32Pair1Source & 0x1UL) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1UL) << RTC_TAMPCTL_DYN2ISS_Pos); + + if(u32DebounceEn) + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | + RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + else + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + + for(i = 0UL; i < (uint32_t)RTC_MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8UL)); + u32Reg |= (u32TmpReg << (i * 8UL)); + } + } + + if((u32Pair1Source) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk; + u32Reg |= u32Tamper2Debounce; + } + + if((u32Pair2Source) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk; + u32Reg |= u32Tamper4Debounce; + } + + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Disable + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the dynamic tamper. + */ +void RTC_DynamicTamperDisable(uint32_t u32PairSel) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2En = 0UL, u32Tamper4En = 0UL; + + u32Reg = RTC->TAMPCTL; + + if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT)) + { + u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk; + } + + if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT)) + { + u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk; + } + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + + for(i = 0UL; i < (uint32_t)RTC_MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << ((i * 8UL))); + } + } + + u32Reg |= (u32Tamper2En | u32Tamper4En); + + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Configure Dynamic Tamper + * + * @param[in] u32ChangeRate The dynamic tamper output change rate + * - \ref RTC_2POW10_CLK + * - \ref RTC_2POW11_CLK + * - \ref RTC_2POW12_CLK + * - \ref RTC_2POW13_CLK + * - \ref RTC_2POW14_CLK + * - \ref RTC_2POW15_CLK + * - \ref RTC_2POW16_CLK + * - \ref RTC_2POW17_CLK + * + * @param[in] u32SeedReload Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern Reference pattern + * - \ref RTC_REF_RANDOM_PATTERN + * - \ref RTC_REF_SEED_VALUE + * + * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config dynamic tamper setting. + */ +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed) +{ + uint32_t u32Reg; + + u32Reg = RTC->TAMPCTL; + + u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk); + + u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1UL) << RTC_TAMPCTL_SEEDRLD_Pos) | + (u32RefPattern << RTC_TAMPCTL_DYNSRC_Pos); + + RTC->TAMPSEED = u32Seed; /* need set seed value before re-loade seed */ + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Set RTC Clock Source + * + * @param[in] u32ClkSrc u32ClkSrc is the RTC clock source. It could be + * - \ref RTC_CLOCK_SOURCE_LXT + * - \ref RTC_CLOCK_SOURCE_LIRC + * + * @retval RTC_CLOCK_SOURCE_LXT + * @retval RTC_CLOCK_SOURCE_LIRC + * + * @details This API is used to get the setting of RTC clock source. + * User must to enable the selected clock source by themselves executing perform this API. + */ +uint32_t RTC_SetClockSource(uint32_t u32ClkSrc) +{ + uint32_t u32TrimDefault = inpw(SYS_BASE + 0x14Cul); + + if(u32ClkSrc == RTC_CLOCK_SOURCE_LXT) + { + /* RTC clock source is external LXT */ + RTC->LXTCTL &= ~RTC_LXTCTL_RTCCKSEL_Msk; + + return RTC_CLOCK_SOURCE_LXT; + } + else if(u32ClkSrc == RTC_CLOCK_SOURCE_LIRC) + { + /* RTC clock source is LIRC */ + RTC->LXTCTL |= RTC_LXTCTL_RTCCKSEL_Msk; + + return RTC_CLOCK_SOURCE_LIRC; + } + else + { + /* Set the default RTC clock source is LIRC */ + RTC->LXTCTL |= RTC_LXTCTL_RTCCKSEL_Msk; + + return RTC_CLOCK_SOURCE_LIRC; + } +} + +/** + * @brief Set RTC GPIO Operation Mode + * + * @param[in] u32Pin The single pin of GPIO-F port. + * It could be 4~11, which means PF.4~PF.11. + * @param[in] u32Mode Operation mode. It could be + * - \ref RTC_IO_MODE_INPUT + * - \ref RTC_IO_MODE_OUTPUT + * - \ref RTC_IO_MODE_OPEN_DRAIN + * - \ref RTC_IO_MODE_QUASI + * @param[in] u32DigitalCtl The digital input path control of specified pin. It could be + * - \ref RTC_IO_DIGITAL_ENABLE + * - \ref RTC_IO_DIGITAL_DISABLE + * @param[in] u32PullCtl The pull-up or pull-down control of specified pin. It could be + * - \ref RTC_IO_PULL_UP_DOWN_DISABLE + * - \ref RTC_IO_PULL_UP_ENABLE + * - \ref RTC_IO_PULL_DOWN_ENABLE + * @param[in] u32OutputLevel The I/O output level. 0: output low; 1: output high. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode controlled by RTC module. + */ +void RTC_SetGPIOMode(uint32_t u32PFPin, uint32_t u32Mode, uint32_t u32DigitalCtl, uint32_t u32PullCtl, uint32_t u32OutputLevel) +{ + uint32_t u32Offset; + + if((u32PFPin == 4) || (u32PFPin == 5) || (u32PFPin == 6) || (u32PFPin == 7)) + { + u32Offset = u32PFPin - 4; + + RTC_SET_IOCTL_BY_RTC(); + + RTC->GPIOCTL0 = (RTC->GPIOCTL0 & ~(0x3FUL << (u32Offset * 8))) | + (u32Mode << (u32Offset * 8)) | + (u32OutputLevel << ((u32Offset * 8) + 2)) | + (u32DigitalCtl << ((u32Offset * 8) + 3)) | + (u32PullCtl << ((u32Offset * 8) + 4)); + } + + if((u32PFPin == 8) || (u32PFPin == 9) || (u32PFPin == 10) || (u32PFPin == 11)) + { + u32Offset = u32PFPin - 8; + + RTC_SET_IOCTL_BY_RTC(); + + RTC->GPIOCTL1 = (RTC->GPIOCTL1 & ~(0x3FUL << (u32Offset * 8))) | + (u32Mode << (u32Offset * 8)) | + (u32OutputLevel << ((u32Offset * 8) + 2)) | + (u32DigitalCtl << ((u32Offset * 8) + 3)) | + (u32PullCtl << ((u32Offset * 8) + 4)); + } +} + +/** + * @brief Set RTC GPIO Output Level + * + * @param[in] u32Pin The single pin of GPIO-F port. + * It could be 4~11, which means PF.4~PF.11. + * @param[in] u32OutputLevel The I/O output level. 0: output low; 1: output high. + * + * @return None + * + * @details This function is used to set GPIO output level by RTC module. + */ +void RTC_SetGPIOLevel(uint32_t u32PFPin, uint32_t u32OutputLevel) +{ + uint32_t u32Offset; + + if((u32PFPin == 4) || (u32PFPin == 5) || (u32PFPin == 6) || (u32PFPin == 7)) + { + u32Offset = u32PFPin - 4; + + RTC->GPIOCTL0 = (RTC->GPIOCTL0 & ~(0x4UL << (u32Offset * 8))) | + (u32OutputLevel << ((u32Offset * 8) + 2)); + } + + if((u32PFPin == 8) || (u32PFPin == 9) || (u32PFPin == 10) || (u32PFPin == 11)) + { + u32Offset = u32PFPin - 8; + + RTC->GPIOCTL1 = (RTC->GPIOCTL1 & ~(0x4UL << (u32Offset * 8))) | + (u32OutputLevel << ((u32Offset * 8) + 2)); + } +} + +/**@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RTC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sc.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sc.c new file mode 100644 index 0000000..0dd7f62 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sc.c @@ -0,0 +1,478 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * @brief Smartcard(SC) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t g_u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief Indicates specified smartcard slot status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + * + * @details This function is used to check if specified smartcard slot is presented. + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + uint32_t u32Ret; + + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if((sc == SC0) && (g_u32CardStateIgnore[0] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if((sc == SC1) && (g_u32CardStateIgnore[1] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if((sc == SC2) && (g_u32CardStateIgnore[2] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if(cond1 != cond2) + { + u32Ret = (uint32_t)FALSE; + } + else + { + u32Ret = (uint32_t)TRUE; + } + + return u32Ret; +} + +/* + * @brief Reset the Tx and Rx FIFO of smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function reset both transmit and receive FIFO of specified smartcard module. + */ +void SC_ClearFIFO(SC_T *sc) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief Disable specified smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function disable specified smartcard module, and force all transition to IDLE state. + */ +void SC_Close(SC_T *sc) +{ + uint32_t u32TimeOutCount = 0UL; + + sc->INTEN = 0UL; + + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + sc->PINCTL = 0UL; + sc->ALTCTL = 0UL; + + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + sc->CTL = 0UL; +} + +/** + * @brief Initialized smartcard module + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CardDet Card detect polarity, select the SC_CD pin state which indicates card absent. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present. + * @param[in] u32PWR Power off polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * + * @return None + * + * @details This function initialized smartcard module. + */ +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + if(u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk; + g_u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + g_u32CardStateIgnore[u32Intf] = 1UL; + } + sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; +} + +/** + * @brief Reset specified smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function reset specified smartcard module to its default state for activate smartcard. + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf, u32TimeOutCount; + + if(sc == SC0) + { + u32Intf = 0UL; + } + else if(sc == SC1) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + /* Enable auto convention, and all three smartcard internal timers */ + sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + sc->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + sc->ETUCTL = 371UL; + + /* Enable necessary interrupt for smartcard operation */ + if(g_u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk | + SC_INTEN_CDIEN_Msk); + } +} + +/** + * @brief Set Block Guard Time (BGT) + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32. + * + * @return None + * + * @details This function is used to configure block guard time (BGT) of specified smartcard module. + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief Set Character Guard Time (CGT) + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267. + * + * @return None + * + * @details This function is used to configure character guard time (CGT) of specified smartcard module. + * @note Before using this API, user should set the correct stop bit length first. + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + /* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */ + u32CGT -= ((sc->CTL & SC_CTL_NSB_Msk) == SC_CTL_NSB_Msk) ? 11UL : 12UL; + sc->EGT = u32CGT; +} + +/** + * @brief Stop all smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @note This function stop the timers within specified smartcard module, \b not timer module. + */ +void SC_StopAllTimer(SC_T *sc) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0) break; + } + sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief Configure and start smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1 ~ 0x1000000 ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs. + * + * @return None + * + * @note This function start the timer within specified smartcard module, \b not timer module. + * @note Depend on the timer operating mode, timer may not start counting immediately and starts when condition match. + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t u32Reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + uint32_t u32TimeOutCount = 0UL; + + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + if(u32TimerNum == 0UL) + { + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) == SC_TMRCTL0_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + sc->TMRCTL0 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) == SC_TMRCTL1_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + sc->TMRCTL1 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while((sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) == SC_TMRCTL2_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + sc->TMRCTL2 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief Stop a smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2. + * + * @return None + * + * @note This function stop the timer within specified smartcard module, \b not timer module. + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + if(--u32TimeOutCount == 0UL) break; + } + + if(u32TimerNum == 0UL) /* timer 0 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) /* timer 1 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief Get smartcard clock frequency + * + * @param[in] sc The pointer of smartcard module. + * + * @return Smartcard frequency in kHZ + * + * @details This function is used to get specified smartcard module clock frequency in kHz. + */ +uint32_t SC_GetInterfaceClock(SC_T *sc) +{ + uint32_t u32ClkSrc = 0, u32Num = 0, u32ClkFreq = __HIRC, u32Div = 0; + + /* Get smartcard module clock source and divider */ + if(sc == SC0) + { + u32Num = 0UL; + u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE); + u32Div = CLK_GetModuleClockDivider(SC0_MODULE); + } + else if(sc == SC1) + { + u32Num = 1UL; + u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE); + u32Div = CLK_GetModuleClockDivider(SC1_MODULE); + } + else if(sc == SC2) + { + u32Num = 2UL; + u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE); + u32Div = CLK_GetModuleClockDivider(SC2_MODULE); + } + else + { + u32ClkFreq = 0UL; + } + + if(u32ClkFreq != 0UL) + { + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32ClkFreq = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32ClkFreq = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32ClkFreq = CLK_GetPCLK1Freq(); + } + else + { + u32ClkFreq = CLK_GetPCLK0Freq(); + } + } + else + { + u32ClkFreq = __HIRC; + } + + u32ClkFreq /= (u32Div + 1UL) * 1000UL; + } + + return u32ClkFreq; +} + +/**@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_scuart.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_scuart.c new file mode 100644 index 0000000..bb5cedf --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_scuart.c @@ -0,0 +1,286 @@ +/**************************************************************************//** + * @file scuart.c + * @version V3.00 + * @brief Smartcard UART mode (SCUART) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +int32_t g_SCUART_i32ErrCode = 0; /*!< SCUART global error code */ + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief Disable smartcard interface + * + * @param sc The pointer of smartcard module. + * + * @return None + * + * @details The function is used to disable smartcard interface UART mode. + */ +void SCUART_Close(SC_T* sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; +} + +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief Returns module clock of specified SC interface + * + * @param[in] sc The pointer of smartcard module. + * + * @return Module clock of specified SC interface. + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc = 0, u32Num = 0, u32ClkFreq = __HIRC, u32Div = 0; + + /* Get smartcard module clock source and divider */ + if(sc == SC0) + { + u32Num = 0UL; + u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE); + u32Div = CLK_GetModuleClockDivider(SC0_MODULE); + } + else if(sc == SC1) + { + u32Num = 1UL; + u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE); + u32Div = CLK_GetModuleClockDivider(SC1_MODULE); + } + else if(sc == SC2) + { + u32Num = 2UL; + u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE); + u32Div = CLK_GetModuleClockDivider(SC2_MODULE); + } + else + { + u32ClkFreq = 0UL; + } + + if(u32ClkFreq != 0UL) + { + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32ClkFreq = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32ClkFreq = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32ClkFreq = CLK_GetPCLK1Freq(); + } + else + { + u32ClkFreq = CLK_GetPCLK0Freq(); + } + } + else + { + u32ClkFreq = __HIRC; + } + + u32ClkFreq /= (u32Div + 1UL); + } + + return u32ClkFreq; +} +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Enable smartcard module UART mode and set baudrate + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard UART module. + * + * @return Actual baudrate of smartcard UART mode + * + * @details This function use to enable smartcard module UART mode and set baudrate. + * + * @note This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings. + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate) +{ + uint32_t u32ClkFreq = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32ClkFreq + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL; + + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; /* Enable smartcard interface and stop bit = 1 */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; /* Enable UART mode, disable parity and 8 bit per character */ + sc->ETUCTL = u32Div; + + return (u32ClkFreq / (u32Div + 1UL)); +} + +/** + * @brief Read Rx data from Rx FIFO + * + * @param[in] sc The pointer of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data. + * @param[in] u32ReadBytes Target number of characters to receive + * + * @return Actual character number reads to buffer + * + * @details The function is used to read data from Rx FIFO. + * + * @note This function does not block and return immediately if there's no data available. + */ +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if(SCUART_GET_RX_EMPTY(sc) == SC_STATUS_RXEMPTY_Msk) + { + /* No data available */ + break; + } + /* Get data from FIFO */ + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); + } + + return u32Count; +} + +/** + * @brief Configure smartcard UART mode line setting + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard UART mode. If this value is 0, SC UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be: + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be: + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be: + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * + * @return Actual baudrate of smartcard UART mode + * + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + uint32_t u32ClkFreq = SCUART_GetClock(sc), u32Div; + + if(u32Baudrate == 0UL) + { + /* Keep original baudrate setting */ + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = ((u32ClkFreq + (u32Baudrate >> 1) - 1UL) / u32Baudrate) - 1UL; + sc->ETUCTL = u32Div; + } + + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; /* Set stop bit */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; /* Set character width and parity */ + + return (u32ClkFreq / (u32Div + 1UL)); +} + +/** + * @brief Set receive timeout count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TOC Rx time-out counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable time-out counter. + * + * @return None + * + * @details The time-out counter resets and starts counting whenever the Rx buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC) +{ + sc->RXTOUT = u32TOC; +} + +/** + * @brief Write data into transmit FIFO to send data out + * + * @param[in] sc The pointer of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * + * @return Actual number of data put into SCUART Tx FIFO + * + * @details This function is used to write data into Tx FIFO to send data out. + * + * @note This function sets g_SCUART_i32ErrCode to SCUART_TIMEOUT_ERR if the Tx FIFO + * blocks longer than expected. + */ +uint32_t SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + /* Baudrate * (start bit + 8-bit data + 1-bit parity + 2-bit stop) */ + uint32_t u32Delay = (SystemCoreClock / SCUART_GetClock(sc)) * sc->ETUCTL * 12, i; + + g_SCUART_i32ErrCode = 0; + for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + i = 0; + /* Wait 'til FIFO not full */ + while(SCUART_GET_TX_FULL(sc)) + { + /* Block longer than expected. Maybe some interrupt disable SCUART clock? */ + if(i++ > u32Delay) + { + g_SCUART_i32ErrCode = SCUART_TIMEOUT_ERR; + return u32Count; + } + } + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; + } + return u32Count; +} + + +/**@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SCUART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sdh.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sdh.c new file mode 100644 index 0000000..3259b84 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sdh.c @@ -0,0 +1,1446 @@ +/**************************************************************************//** + * @file SDH.c + * @version V1.00 + * @brief SDH driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + +int32_t g_SDH_i32ErrCode = 0; /*!< SDH global error code */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ +#define SDH_BLOCK_SIZE 512ul + +/** @cond HIDDEN_SYMBOLS */ + +/* global variables */ +/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */ +/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */ +/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */ + +static uint32_t _SDH0_ReferenceClock, _SDH1_ReferenceClock; + +#ifdef __ICCARM__ +#pragma data_alignment = 4 +static uint8_t _SDH0_ucSDHCBuffer[512]; +static uint8_t _SDH1_ucSDHCBuffer[512]; +#else +static uint8_t _SDH0_ucSDHCBuffer[512] __attribute__((aligned(4))); +static uint8_t _SDH1_ucSDHCBuffer[512] __attribute__((aligned(4))); +#endif + +SDH_INFO_T SD0, SD1; + +void SDH_CheckRB(SDH_T *sdh) +{ + uint32_t u32TimeOutCount1, u32TimeOutCount2; + + g_SDH_i32ErrCode = 0; + u32TimeOutCount2 = TIMEOUT_SDH; + while(1) + { + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + u32TimeOutCount1 = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + if(--u32TimeOutCount1 == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + if ((sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) == SDH_INTSTS_DAT0STS_Msk) + { + break; + } + if(--u32TimeOutCount2 == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } +} + + +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf, val = 0ul; + SDH_INFO_T *pSD; + uint32_t u32TimeOutCount = TIMEOUT_SDH; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)|(SDH_CTL_COEN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_COEN_Msk) == SDH_CTL_COEN_Msk) + { + if (pSD->IsCardInsert == 0ul) + { + val = SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + return val; +} + + +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t ntickCount) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + uint32_t u32TimeOutCount = TIMEOUT_SDH; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (ucCmd << 8ul) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); + sdh->CTL = buf; + + if (ntickCount > 0ul) + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if(ntickCount-- == 0ul) + { + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ + return 2ul; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + else + { + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + } + + if (pSD->R7Flag) + { + uint32_t tmp0 = 0ul, tmp1= 0ul; + tmp1 = sdh->RESP1 & 0xfful; + tmp0 = sdh->RESP0 & 0xful; + if ((tmp1 != 0x55ul) && (tmp0 != 0x01ul)) + { + pSD->R7Flag = 0ul; + return SDH_CMD8_ERROR; + } + } + + if (!pSD->R3Flag) + { + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } + } + else + { + /* ignore CRC error for R3 case */ + pSD->R3Flag = 0ul; + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return Successful; + } +} + + +uint32_t SDH_Swap32(uint32_t val) +{ + uint32_t buf; + + buf = val; + val <<= 24; + val |= (buf<<8) & 0xff0000ul; + val |= (buf>>8) & 0xff00ul; + val |= (buf>>24)& 0xfful; + return val; +} + +/* Get 16 bytes CID or CSD */ +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg, uint32_t puR2ptr[]) +{ + uint32_t i, buf; + uint32_t tmpBuf[5]; + SDH_INFO_T *pSD; + uint32_t u32TimeOutCount = TIMEOUT_SDH; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk); + sdh->CTL = buf; + + while ((sdh->CTL & SDH_CTL_R2EN_Msk) == SDH_CTL_R2EN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) == SDH_INTSTS_CRC7_Msk) + { + for (i=0ul; i<5ul; i++) + { + tmpBuf[i] = SDH_Swap32(sdh->FB[i]); + } + for (i=0ul; i<4ul; i++) + { + puR2ptr[i] = ((tmpBuf[i] & 0x00fffffful)<<8) | ((tmpBuf[i+1ul] & 0xff000000ul)>>24); + } + } + else + { + return SDH_CRC7_ERROR; + } + return Successful; +} + + +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t ucCmd, uint32_t uArg) +{ + volatile uint32_t buf; + SDH_INFO_T *pSD; + uint32_t u32TimeOutCount; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + sdh->CMDARG = uArg; + buf = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8ul)| + (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + + sdh->CTL = buf; + + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_RIEN_Msk) == SDH_CTL_RIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_DIEN_Msk) == SDH_CTL_DIEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) + { + /* check CRC7 */ + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) + { + /* check CRC16 */ + return SDH_CRC16_ERROR; + } + return 0ul; +} + +/* there are 8 bits for divider0, maximum is 256 */ +#define SDH_CLK_DIV0_MAX 256ul + +void SDH_Set_clock(SDH_T *sdh, uint32_t sd_clock_khz) +{ + uint32_t rate, div1; + static uint32_t u32SD_ClkSrc = 0ul, u32SD_PwrCtl = 0ul; + + SYS_UnlockReg(); + + /* initial state, clock source use HIRC */ + if (sd_clock_khz <= 400ul) + { + u32SD_PwrCtl = CLK->PWRCTL; + if ((u32SD_PwrCtl & CLK_PWRCTL_HIRCEN_Msk) != 0x4ul) + { + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + } + + if (sdh == SDH0) + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | CLK_CLKSEL0_SDH0SEL_HIRC; + _SDH0_ReferenceClock = (__HIRC / 1000ul); + } + else + { + u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH1SEL_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | CLK_CLKSEL0_SDH1SEL_HIRC; + _SDH1_ReferenceClock = (__HIRC / 1000ul); + } + } + /* transfer state, clock source use sys_init() */ + else + { + CLK->PWRCTL = u32SD_PwrCtl; + if (sdh == SDH0) + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH0SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HXT) + { + _SDH0_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC) + { + _SDH0_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_PLL_DIV2) + { + _SDH0_ReferenceClock = ((CLK_GetPLLClockFreq()>>1) / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK) + { + _SDH0_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_SDH1SEL_Msk) | u32SD_ClkSrc; + if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HXT) + { + _SDH1_ReferenceClock = (CLK_GetHXTFreq() / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HIRC) + { + _SDH1_ReferenceClock = (__HIRC / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_PLL_DIV2) + { + _SDH1_ReferenceClock = ((CLK_GetPLLClockFreq()>>1) / 1000ul); + } + else if(u32SD_ClkSrc == CLK_CLKSEL0_SDH1SEL_HCLK) + { + _SDH1_ReferenceClock = (CLK_GetHCLKFreq() / 1000ul); + } + } + + if(sd_clock_khz >= 50000ul) + { + sd_clock_khz = 50000ul; + } + } + if (sdh == SDH0) + { + rate = _SDH0_ReferenceClock / sd_clock_khz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if ((_SDH0_ReferenceClock % sd_clock_khz) != 0ul) + { + rate++; + } + } + else + { + rate = _SDH1_ReferenceClock / sd_clock_khz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if ((_SDH1_ReferenceClock % sd_clock_khz) != 0ul) + { + rate++; + } + } + + if(rate >= SDH_CLK_DIV0_MAX) + { + rate = SDH_CLK_DIV0_MAX; + } + + /*--- calculate the second divider CLKDIV0[SDHOST_N]*/ + div1 = (rate - 1ul) & 0xFFul; + + /*--- setup register */ + if (sdh == SDH0) + { + CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; + CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDH0DIV_Pos); + } + else + { + CLK->CLKDIV3 &= ~CLK_CLKDIV3_SDH1DIV_Msk; + CLK->CLKDIV3 |= (div1 << CLK_CLKDIV3_SDH1DIV_Pos); + } + return; +} + +uint32_t SDH_CardDetection(SDH_T *sdh) +{ + uint32_t i, val = TRUE; + SDH_INFO_T *pSD; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + + if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) == SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */ + { + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card remove */ + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + else + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + } + else if ((sdh->INTEN & SDH_INTEN_CDSRC_Msk) != SDH_INTEN_CDSRC_Msk) + { + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + for(i= 0ul; i < 5000ul; i++) + { + } + + if ((sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) == SDH_INTSTS_CDSTS_Msk) /* Card insert */ + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + else + { + pSD->IsCardInsert = (uint8_t)FALSE; + val = FALSE; + } + + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + + return val; +} + +uint32_t SDH_Init(SDH_T *sdh) +{ + uint32_t volatile i, status; + uint32_t resp; + uint32_t CIDBuffer[4]; + uint32_t volatile u32CmdTimeOut; + SDH_INFO_T *pSD; + uint32_t u32TimeOutCount; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + /* set the clock to 300KHz */ + SDH_Set_clock(sdh, 300ul); + + /* power ON 74 clock */ + sdh->CTL |= SDH_CTL_CLK74OEN_Msk; + + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_CLK74OEN_Msk) == SDH_CTL_CLK74OEN_Msk) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x1000ul; i>0ul; i--) + { + } + + /* initial SDHC */ + pSD->R7Flag = 1ul; + u32CmdTimeOut = 0xFFFFFul; + + i = SDH_SDCmdAndRsp(sdh, 8ul, 0x00000155ul, u32CmdTimeOut); + if (i == Successful) + { + /* SD 2.0 */ + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 2.7v-3.6v */ + resp = sdh->RESP0; + + u32TimeOutCount = TIMEOUT_SDH; + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x40ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_SD_HIGH; + } + else + { + pSD->CardType = SDH_TYPE_SD_LOW; + } + } + else + { + /* SD 1.1 */ + SDH_SDCommand(sdh, 0ul, 0ul); /* reset all cards */ + for (i=0x100ul; i>0ul; i--) + { + } + + i = SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + if (i == 2ul) /* MMC memory */ + { + + SDH_SDCommand(sdh, 0ul, 0ul); /* reset */ + for (i=0x100ul; i>0ul; i--) + { + } + + pSD->R3Flag = 1ul; + + if (SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut) != 2ul) /* eMMC memory */ + { + resp = sdh->RESP0; + u32TimeOutCount = TIMEOUT_SDH; + while ((resp & 0x00800000ul) != 0x00800000ul) + { + /* check if card is ready */ + pSD->R3Flag = 1ul; + + SDH_SDCmdAndRsp(sdh, 1ul, 0x40ff8000ul, u32CmdTimeOut); /* high voltage */ + resp = sdh->RESP0; + + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((resp & 0x00400000ul) == 0x00400000ul) + { + pSD->CardType = SDH_TYPE_EMMC; + } + else + { + pSD->CardType = SDH_TYPE_MMC; + } + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_ERR_DEVICE; + } + } + else if (i == 0ul) /* SD Memory */ + { + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + u32TimeOutCount = TIMEOUT_SDH; + while ((resp & 0x00800000ul) != 0x00800000ul) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55ul, 0x00ul, u32CmdTimeOut); + pSD->R3Flag = 1ul; + SDH_SDCmdAndRsp(sdh, 41ul, 0x00ff8000ul, u32CmdTimeOut); /* 3.0v-3.4v */ + resp = sdh->RESP0; + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + pSD->CardType = SDH_TYPE_SD_LOW; + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_INIT_ERROR; + } + } + + if (pSD->CardType != SDH_TYPE_UNKNOWN) + { + SDH_SDCmdAndRsp2(sdh, 2ul, 0x00ul, CIDBuffer); + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x10000ul, 0ul)) != Successful) /* set RCA */ + { + return status; + } + pSD->RCA = 0x10000ul; + } + else + { + if ((status = SDH_SDCmdAndRsp(sdh, 3ul, 0x00ul, 0ul)) != Successful) /* get RCA */ + { + return status; + } + else + { + pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000; + } + } + } + return Successful; +} + + +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD) +{ + uint32_t volatile status=0ul; + uint16_t current_comsumption, busy_status0; + uint32_t u32TimeOutCount = TIMEOUT_SDH; + + g_SDH_i32ErrCode = 0; + + sdh->DMASA = (uint32_t)pSD->dmabuf; + sdh->BLEN = 63ul; + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x00ffff01ul)) != Successful) + { + return Fail; + } + + current_comsumption = (uint16_t)(*pSD->dmabuf) << 8; + current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1)); + if (!current_comsumption) + { + return Fail; + } + + busy_status0 = (uint16_t)(*(pSD->dmabuf + 28)) << 8; + busy_status0 |= (uint16_t)(*(pSD->dmabuf + 29)); + + if (!busy_status0) /* function ready */ + { + sdh->DMASA = (uint32_t)pSD->dmabuf; + sdh->BLEN = 63ul; /* 512 bit */ + + if ((status = SDH_SDCmdAndRspDataIn(sdh, 6ul, 0x80ffff01ul)) != Successful) + { + return Fail; + } + + /* function change timing: 8 clocks */ + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + current_comsumption = (uint16_t)(*pSD->dmabuf) << 8; + current_comsumption |= (uint16_t)(*(pSD->dmabuf + 1)); + if (!current_comsumption) + { + return Fail; + } + + return Successful; + } + else + { + return Fail; + } +} + + +uint32_t SDH_SelectCardType(SDH_T *sdh) +{ + uint32_t volatile status=0ul; + uint32_t param; + SDH_INFO_T *pSD; + uint32_t u32TimeOutCount; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* if SD card set 4bit */ + if (pSD->CardType == SDH_TYPE_SD_HIGH) + { + sdh->DMASA = (uint32_t)pSD->dmabuf; + sdh->BLEN = 0x07ul; /* 64 bit */ + sdh->DMACTL |= SDH_DMACTL_DMARST_Msk; + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == 0x2) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + if ((*pSD->dmabuf & 0xful) == 0x2ul) + { + status = SDH_SwitchToHighSpeed(sdh, pSD); + if (status == Successful) + { + /* divider */ + SDH_Set_clock(sdh, SDHC_FREQ); + } + } + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) /* set bus width */ + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if (pSD->CardType == SDH_TYPE_SD_LOW) + { + sdh->DMASA = (uint32_t)pSD->dmabuf;; + sdh->BLEN = 0x07ul; + + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + if ((status = SDH_SDCmdAndRspDataIn(sdh, 51ul, 0x00ul)) != Successful) + { + return status; + } + + /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */ + if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, 0x02ul, 0ul)) != Successful) + { + return status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if ((pSD->CardType == SDH_TYPE_MMC) ||(pSD->CardType == SDH_TYPE_EMMC)) + { + + if(pSD->CardType == SDH_TYPE_MMC) + { + sdh->CTL &= ~SDH_CTL_DBW_Msk; + } + + /*--- sent CMD6 to MMC card to set bus width to 4 bits mode */ + /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */ + param = (3ul << 24) | (183ul << 16) | (1ul << 8); + if ((status = SDH_SDCmdAndRsp(sdh, 6ul, param, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */ + + } + + if ((status = SDH_SDCmdAndRsp(sdh, 16ul, SDH_BLOCK_SIZE, 0ul)) != Successful) + { + return status; + } + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk; + + return Successful; +} + +void SDH_Get_SD_info(SDH_T *sdh) +{ + unsigned int R_LEN, C_Size, MULT, size; + uint32_t Buffer[4]; + //unsigned char *ptr; + SDH_INFO_T *pSD; + uint32_t u32TimeOutCount = TIMEOUT_SDH; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + SDH_SDCmdAndRsp2(sdh, 9ul, pSD->RCA, Buffer); + + if ((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + /* for MMC/eMMC card */ + if ((Buffer[0] & 0xc0000000) == 0xc0000000) + { + /* CSD_STRUCTURE [127:126] is 3 */ + /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */ + SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul); + + //ptr = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer ); + sdh->DMASA = (uint32_t)pSD->dmabuf;; + sdh->BLEN = 511ul; /* read 512 bytes for EXT_CSD */ + + if (SDH_SDCmdAndRspDataIn(sdh, 8ul, 0x00ul) == Successful) + { + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + pSD->totalSectorN = (uint32_t)(*(pSD->dmabuf+215))<<24; + pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+214))<<16; + pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+213))<<8; + pSD->totalSectorN |= (uint32_t)(*(pSD->dmabuf+212)); + pSD->diskSize = pSD->totalSectorN / 2ul; + } + } + else + { + /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */ + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + else + { + if ((Buffer[0] & 0xc0000000) != 0x0ul) + { + C_Size = ((Buffer[1] & 0x0000003ful) << 16) | ((Buffer[2] & 0xffff0000ul) >> 16); + size = (C_Size+1ul) * 512ul; /* Kbytes */ + + pSD->diskSize = size; + pSD->totalSectorN = size << 1; + } + else + { + R_LEN = (Buffer[1] & 0x000f0000ul) >> 16; + C_Size = ((Buffer[1] & 0x000003fful) << 2) | ((Buffer[2] & 0xc0000000ul) >> 30); + MULT = (Buffer[2] & 0x00038000ul) >> 15; + size = (C_Size+1ul) * (1ul<<(MULT+2ul)) * (1ul<diskSize = size / 1024ul; + pSD->totalSectorN = size / 512ul; + } + } + pSD->sectorSize = (int)512; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief This function use to reset SD function and select card detection source and pin. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3) + * + * @return None + */ +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc) +{ + uint32_t u32TimeOutCount; + + g_SDH_i32ErrCode = 0; + + sdh->DMACTL = SDH_DMACTL_DMARST_Msk; + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->DMACTL & SDH_DMACTL_DMARST_Msk) == SDH_DMACTL_DMARST_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + + sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk; + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->GCTL & SDH_GCTL_GCTLRST_Msk) == SDH_GCTL_GCTLRST_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if (sdh == SDH0) + { + NVIC_EnableIRQ(SDH0_IRQn); + memset(&SD0, 0, sizeof(SDH_INFO_T)); + SD0.dmabuf = _SDH0_ucSDHCBuffer; + } + else if (sdh == SDH1) + { + NVIC_EnableIRQ(SDH1_IRQn); + memset(&SD1, 0, sizeof(SDH_INFO_T)); + SD1.dmabuf = _SDH1_ucSDHCBuffer; + } + else + { + } + + sdh->GCTL = SDH_GCTL_SDEN_Msk; + + if ((u32CardDetSrc & CardDetect_From_DAT3) == CardDetect_From_DAT3) + { + sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk; + } + else + { + sdh->INTEN |= SDH_INTEN_CDSRC_Msk; + } + sdh->INTEN |= SDH_INTEN_CDIEN_Msk; + + sdh->CTL |= SDH_CTL_CTLRST_Msk; + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_CTLRST_Msk) == SDH_CTL_CTLRST_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } +} + +/** + * @brief This function use to initial SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * + * @return None + * + * @details This function is used to initial SD card. + * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source. + * And then switch back to the user's setting. + */ +uint32_t SDH_Probe(SDH_T *sdh) +{ + uint32_t val; + + sdh->GINTEN = 0ul; + sdh->CTL &= ~SDH_CTL_SDNWR_Msk; + sdh->CTL |= 0x09ul << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */ + sdh->CTL &= ~SDH_CTL_BLKCNT_Msk; + sdh->CTL |= 0x01ul << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */ + sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */ + + if(!(SDH_CardDetection(sdh))) + { + return SDH_NO_SD_CARD; + } + + if ((val = SDH_Init(sdh)) != 0ul) + { + return val; + } + + /* divider */ + if ((SD0.CardType == SDH_TYPE_MMC) || (SD1.CardType == SDH_TYPE_MMC)) + { + SDH_Set_clock(sdh, MMC_FREQ); + } + else + { + SDH_Set_clock(sdh, SD_FREQ); + } + SDH_Get_SD_info(sdh); + + if ((val = SDH_SelectCardType(sdh)) != 0ul) + { + return val; + } + + return 0ul; +} + +/** + * @brief This function use to read data from SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[out] pu8BufAddr The buffer to receive the data from SD card. + * @param[in] u32StartSec The start read sector address. + * @param[in] u32SecCount The the read sector number of data + * + * @return None + */ +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE, buf; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + uint32_t blksize = SDH_BLOCK_SIZE; + uint32_t u32TimeOutCount; + + SDH_INFO_T *pSD; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + SDH_CheckRB(sdh); + + sdh->BLEN = blksize - 1ul; /* the actual byte count is equal to (SDBLEN+1) */ + + if ( (pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC) ) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * blksize; + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + + loop = u32SecCount / 255ul; + for (i=0ul; iDataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk; + reg = reg | 0xff0000ul; /* set BLK_CNT to 255 */ + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + u32TimeOutCount = TIMEOUT_SDH; + while(!pSD->DataReadyFlag) + { + if(pSD->DataReadyFlag) + { + break; + } + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + pSD->DataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk); + reg = reg & (~SDH_CTL_BLKCNT_Msk); + reg |= (loop << 16); /* setup SDCR_BLKCNT */ + + if (bIsSendCmd == FALSE) + { + sdh->CTL = reg|(18ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DIEN_Msk; + } + + u32TimeOutCount = TIMEOUT_SDH; + while(!pSD->DataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC7_Msk) != SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if ((sdh->INTSTS & SDH_INTSTS_CRC16_Msk) != SDH_INTSTS_CRC16_Msk) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + return Successful; +} + + +/** + * @brief This function use to write data to SD card. + * + * @param[in] sdh Select SDH0 or SDH1. + * @param[in] pu8BufAddr The buffer to send the data to SD card. + * @param[in] u32StartSec The start write sector address. + * @param[in] u32SecCount The the write sector number of data. + * + * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n + * \ref SDH_NO_SD_CARD : SD card be removed. \n + * \ref SDH_CRC_ERROR : CRC error happen. \n + * \ref SDH_CRC7_ERROR : CRC7 error happen. \n + * \ref Successful : Write data to SD card success. + */ +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile bIsSendCmd = FALSE; + uint32_t volatile reg; + uint32_t volatile i, loop, status; + uint32_t u32TimeOutCount; + + SDH_INFO_T *pSD; + + g_SDH_i32ErrCode = 0; + + if (sdh == SDH0) + { + pSD = &SD0; + } + else + { + pSD = &SD1; + } + + if (u32SecCount == 0ul) + { + return SDH_SELECT_ERROR; + } + + if ((status = SDH_SDCmdAndRsp(sdh, 7ul, pSD->RCA, 0ul)) != Successful) + { + return status; + } + + SDH_CheckRB(sdh); + + /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */ + sdh->BLEN = SDH_BLOCK_SIZE - 1ul; + + if ((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */ + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + loop = u32SecCount / 255ul; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */ + for (i=0ul; iDataReadyFlag = (uint8_t)FALSE; + reg = sdh->CTL & 0xff00c080; + reg = reg | 0xff0000ul; /* set BLK_CNT to 0xFF=255 */ + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + u32TimeOutCount = TIMEOUT_SDH; + while(!pSD->DataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + + loop = u32SecCount % 255ul; + if (loop != 0ul) + { + pSD->DataReadyFlag = (uint8_t)FALSE; + reg = (sdh->CTL & 0xff00c080) | (loop << 16); + if (!bIsSendCmd) + { + sdh->CTL = reg|(25ul << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + bIsSendCmd = TRUE; + } + else + { + sdh->CTL = reg | SDH_CTL_DOEN_Msk; + } + + u32TimeOutCount = TIMEOUT_SDH; + while(!pSD->DataReadyFlag) + { + if (pSD->IsCardInsert == FALSE) + { + return SDH_NO_SD_CARD; + } + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + if ((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0ul) + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + + if (SDH_SDCmdAndRsp(sdh, 12ul, 0ul, 0ul)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7ul, 0ul); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + u32TimeOutCount = TIMEOUT_SDH; + while ((sdh->CTL & SDH_CTL_CLK8OEN_Msk) == SDH_CTL_CLK8OEN_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SDH_i32ErrCode = SDH_TIMEOUT_ERR; + break; + } + } + + return Successful; +} + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_spi.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_spi.c new file mode 100644 index 0000000..daeb606 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_spi.c @@ -0,0 +1,2127 @@ +/**************************************************************************//** + * @file spi.c + * @version V3.00 + * @brief M460 series SPI driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0U, u32Div, u32HCLKFreq, u32RetValue = 0U; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if(u32DataWidth == 32U) + { + u32DataWidth = 0U; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if(spi == SPI2) + { + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI2SEL_Msk)) | CLK_CLKSEL3_SPI2SEL_PCLK1; + } + else if(spi == SPI3) + { + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI3SEL_Msk)) | CLK_CLKSEL3_SPI3SEL_PCLK0; + } + else if(spi == SPI4) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI4SEL_Msk)) | CLK_CLKSEL4_SPI4SEL_PCLK1; + } + else if(spi == SPI5) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI5SEL_Msk)) | CLK_CLKSEL4_SPI5SEL_PCLK0; + } + else if(spi == SPI6) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI6SEL_Msk)) | CLK_CLKSEL4_SPI6SEL_PCLK1; + } + else if(spi == SPI7) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI7SEL_Msk)) | CLK_CLKSEL4_SPI7SEL_PCLK0; + } + else if(spi == SPI8) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI8SEL_Msk)) | CLK_CLKSEL4_SPI8SEL_PCLK1; + } + else if(spi == SPI9) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI9SEL_Msk)) | CLK_CLKSEL4_SPI9SEL_PCLK0; + } + else + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI10SEL_Msk)) | CLK_CLKSEL4_SPI10SEL_PCLK1; + } + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI3) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI4) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI5) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI6) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI7) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI8) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI9) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI1) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(spi == SPI2) + { + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI2SEL_Msk)) | CLK_CLKSEL3_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI3) + { + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI3SEL_Msk)) | CLK_CLKSEL3_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(spi == SPI4) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI4SEL_Msk)) | CLK_CLKSEL4_SPI4SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI5) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI5SEL_Msk)) | CLK_CLKSEL4_SPI5SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(spi == SPI6) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI6SEL_Msk)) | CLK_CLKSEL4_SPI6SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI7) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI7SEL_Msk)) | CLK_CLKSEL4_SPI7SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(spi == SPI8) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI8SEL_Msk)) | CLK_CLKSEL4_SPI8SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(spi == SPI9) + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI9SEL_Msk)) | CLK_CLKSEL4_SPI9SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else + { + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI10SEL_Msk)) | CLK_CLKSEL4_SPI10SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will reset SPI controller. + */ +void SPI_Close(SPI_T *spi) +{ + if(spi == SPI0) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(spi == SPI1) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(spi == SPI2) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else if(spi == SPI3) + { + /* Reset SPI */ + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + else if(spi == SPI4) + { + /* Reset SPI */ + SYS->IPRST2 |= SYS_IPRST2_SPI4RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI4RST_Msk; + } + else if(spi == SPI5) + { + /* Reset SPI */ + SYS->IPRST3 |= SYS_IPRST3_SPI5RST_Msk; + SYS->IPRST3 &= ~SYS_IPRST3_SPI5RST_Msk; + } + else if(spi == SPI6) + { + /* Reset SPI */ + SYS->IPRST3 |= SYS_IPRST3_SPI6RST_Msk; + SYS->IPRST3 &= ~SYS_IPRST3_SPI6RST_Msk; + } + else if(spi == SPI7) + { + /* Reset SPI */ + SYS->IPRST3 |= SYS_IPRST3_SPI7RST_Msk; + SYS->IPRST3 &= ~SYS_IPRST3_SPI7RST_Msk; + } + else if(spi == SPI8) + { + /* Reset SPI */ + SYS->IPRST3 |= SYS_IPRST3_SPI8RST_Msk; + SYS->IPRST3 &= ~SYS_IPRST3_SPI8RST_Msk; + } + else if(spi == SPI9) + { + /* Reset SPI */ + SYS->IPRST3 |= SYS_IPRST3_SPI9RST_Msk; + SYS->IPRST3 &= ~SYS_IPRST3_SPI9RST_Msk; + } + else + { + /* Reset SPI */ + SYS->IPRST3 |= SYS_IPRST3_SPI10RST_Msk; + SYS->IPRST3 &= ~SYS_IPRST3_SPI10RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if(spi == SPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + else if(spi == SPI1) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + else if(spi == SPI2) + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI2SEL_Msk)) | CLK_CLKSEL3_SPI2SEL_PCLK1; + else if(spi == SPI3) + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI3SEL_Msk)) | CLK_CLKSEL3_SPI3SEL_PCLK0; + else if(spi == SPI4) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI4SEL_Msk)) | CLK_CLKSEL4_SPI4SEL_PCLK1; + else if(spi == SPI5) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI5SEL_Msk)) | CLK_CLKSEL4_SPI5SEL_PCLK0; + else if(spi == SPI6) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI6SEL_Msk)) | CLK_CLKSEL4_SPI6SEL_PCLK1; + else if(spi == SPI7) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI7SEL_Msk)) | CLK_CLKSEL4_SPI7SEL_PCLK0; + else if(spi == SPI8) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI8SEL_Msk)) | CLK_CLKSEL4_SPI8SEL_PCLK1; + else if(spi == SPI9) + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI9SEL_Msk)) | CLK_CLKSEL4_SPI9SEL_PCLK0; + else + CLK->CLKSEL4 = (CLK->CLKSEL4 & (~CLK_CLKSEL4_SPI10SEL_Msk)) | CLK_CLKSEL4_SPI10SEL_PCLK1; + } + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI3) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI4) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI5) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI6) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI7) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI8) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI9) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0U; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0U) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + u32Div = (((u32ClkSrc * 10U) / u32BusClock + 5U) / 10U) - 1U; /* Round to the nearest integer */ + if(u32Div > 0x1FFU) + { + u32Div = 0x1FFU; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1U)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1U)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. If data width is 4 ~ 16 bits, it could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. If data width is 4 ~ 16 bits, it could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPIxSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if(spi == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI2) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI3) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC) + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC48M) + { + u32ClkSrc = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32ClkSrc = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(spi == SPI4) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI4SEL_Msk) == CLK_CLKSEL4_SPI4SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI5) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI5SEL_Msk) == CLK_CLKSEL4_SPI5SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI6) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI6SEL_Msk) == CLK_CLKSEL4_SPI6SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI7) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI7SEL_Msk) == CLK_CLKSEL4_SPI7SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI8) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI8SEL_Msk) == CLK_CLKSEL4_SPI8SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if(spi == SPI9) + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI9SEL_Msk) == CLK_CLKSEL4_SPI9SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_PLL_DIV2) + { + u32ClkSrc = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL4 & CLK_CLKSEL4_SPI10SEL_Msk) == CLK_CLKSEL4_SPI10SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1U)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk; + /* Check unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk; + /* Check slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk; + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk; + /* Check slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk; + /* Check slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk; + /* Check slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk; + /* Check TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk; + /* Check RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk; + /* Check RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk; + /* Check RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if(u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0U, u32TmpValue; + + u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk; + /* Check busy status */ + if((u32Mask & SPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_BUSY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk; + /* Check RX empty flag */ + if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk; + /* Check RX full flag */ + if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk; + /* Check TX empty flag */ + if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk; + /* Check TX full flag */ + if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk; + /* Check TX/RX reset flag */ + if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk; + /* Check SPIEN flag */ + if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk; + /* Check SPIx_SS line status */ + if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + +/** + * @brief Get SPI status2. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_SLVBENUM_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Number = 0U; + + u32TmpStatus = spi->STATUS2; + + /* Check effective bit number of uncompleted RX data status */ + if(u32Mask & SPI_SLVBENUM_MASK) + { + u32Number = (u32TmpStatus & SPI_STATUS2_SLVBENUM_Msk) >> SPI_STATUS2_SLVBENUM_Pos; + } + + return u32Number; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPIxSEL. + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq; + + if(i2s == SPI0) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL_DIV2) + { + u32Freq = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC) + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HIRC48M) + { + u32Freq = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32Freq = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(i2s == SPI1) + { + if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL_DIV2) + { + u32Freq = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC) + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HIRC48M) + { + u32Freq = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32Freq = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else if(i2s == SPI2) + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PLL_DIV2) + { + u32Freq = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_PCLK1) + { + u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC) + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI2SEL_Msk) == CLK_CLKSEL3_SPI2SEL_HIRC48M) + { + u32Freq = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32Freq = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + else + { + if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PLL_DIV2) + { + u32Freq = (CLK_GetPLLClockFreq() >> 1); /* Clock source is PLL/2 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_PCLK0) + { + u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC) + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + else if((CLK->CLKSEL3 & CLK_CLKSEL3_SPI3SEL_Msk) == CLK_CLKSEL3_SPI3SEL_HIRC48M) + { + u32Freq = __HIRC48M; /* Clock source is RC48M */ + } + else + { + u32Freq = (CLK_GetPLLFNClockFreq() >> 1); /* Clock source is PLLFN/2 */ + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + + /* Reset SPI/I2S */ + if(i2s == SPI0) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if(i2s == SPI1) + { + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if(i2s == SPI2) + { + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + SPII2S_SetFIFO(i2s, 2, 1); + + if(u32MasterSlave == SPII2S_MODE_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U; + u32Divider = ((((u32SrcClk * 10UL / u32BitRate) >> 1U) + 5UL) / 10UL) - 1U; /* Round to the nearest integer */ + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + /* Enable I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= SPI_I2SCLK_I2SMODE_Msk; + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1U) * 2U); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1U) * 16U); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + + if(i2s == SPI0) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else if(i2s == SPI1) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + else if(i2s == SPI2) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI2SEL_Msk)) | CLK_CLKSEL3_SPI2SEL_PCLK1; + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + else + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL3 = (CLK->CLKSEL3 & (~CLK_CLKSEL3_SPI3SEL_Msk)) | CLK_CLKSEL3_SPI3SEL_PCLK0; + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * - \ref SPII2S_SLAVE_ERR_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } + /* Enable bit clock loss interrupt flag */ + if((u32Mask & SPII2S_SLAVE_ERR_INT_MASK) == SPII2S_SLAVE_ERR_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_SLVERRIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * - \ref SPII2S_SLAVE_ERR_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } + /* Disable bit clock loss interrupt flag */ + if((u32Mask & SPII2S_SLAVE_ERR_INT_MASK) == SPII2S_SLAVE_ERR_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_SLVERRIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u32Divider = 0U; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1U; + /* MCLKDIV is a 7-bit width configuration. The maximum value is 0x7F. */ + if(u32Divider > 0x7FU) + { + u32Divider = 0x7FU; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[6:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if(u32Divider == 0U) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1U) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_spim.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_spim.c new file mode 100644 index 0000000..1156484 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_spim.c @@ -0,0 +1,1381 @@ +/**************************************************************************//** + * @file spim.c + * @version V1.00 + * @brief M460 series SPIM driver + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPIM_Driver SPIM Driver + @{ +*/ + +int32_t g_SPIM_i32ErrCode = 0; /*!< SPIM global error code */ + +/** @addtogroup SPIM_EXPORTED_FUNCTIONS SPIM Exported Functions + @{ +*/ + + +/** @cond HIDDEN_SYMBOLS */ + + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG +#define SPIM_DBGMSG printf +#else +#define SPIM_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +static volatile uint8_t g_Supported_List[] = +{ + MFGID_WINBOND, + MFGID_MXIC, + MFGID_EON, + MFGID_ISSI, + MFGID_SPANSION +}; + +static void N_delay(int n); +static void SwitchNBitOutput(uint32_t u32NBit); +static void SwitchNBitInput(uint32_t u32NBit); +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx); +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx); +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit); +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit); +static int spim_is_write_done(uint32_t u32NBit); +static int spim_wait_write_done(uint32_t u32NBit); +static void spim_set_write_enable(int isEn, uint32_t u32NBit); +static void spim_enable_spansion_quad_mode(int isEn); +static void spim_eon_set_qpi_mode(int isEn); +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit); +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync); +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync); + + +static void N_delay(int n) +{ + while (n-- > 0) + { + __NOP(); + } +} + +static void SwitchNBitOutput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_OUTPUT_MODE(); /* 2-bit, Output. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 4-bit, Output. */ + break; + + default: + break; + } +} + +static void SwitchNBitInput(uint32_t u32NBit) +{ + switch (u32NBit) + { + case 1UL: + SPIM_ENABLE_SING_INPUT_MODE(); /* 1-bit, Input. */ + break; + + case 2UL: + SPIM_ENABLE_DUAL_INPUT_MODE(); /* 2-bit, Input. */ + break; + + case 4UL: + SPIM_ENABLE_QUAD_INPUT_MODE(); /* 4-bit, Input. */ + break; + + default: + break; + } +} + + +/** + * @brief Write data to SPI slave. + * @param pu8TxBuf Transmit buffer. + * @param u32NTx Number of bytes to transmit. + * @return None. + * @note This function sets g_SPIM_i32ErrCode to SPIM_TIMEOUT_ERR if waiting SPIM time-out. + */ +static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx) +{ + uint32_t buf_idx = 0UL; + uint32_t u32TimeOutCount = 0UL; + + g_SPIM_i32ErrCode = 0; + + while (u32NTx) + { + uint32_t dataNum = 0UL, dataNum2; + + if (u32NTx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NTx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NTx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NTx >= 4UL) + { + dataNum = 1UL; + } + + dataNum2 = dataNum; + while (dataNum2) + { + uint32_t tmp; + + memcpy(&tmp, &pu8TxBuf[buf_idx], 4U); + buf_idx += 4UL; + u32NTx -= 4UL; + + dataNum2 --; + /* *((__O uint32_t *) &SPIM->TX0 + dataNum2) = tmp; */ + SPIM->TX[dataNum2] = tmp; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + SPIM_WAIT_FREE() + { + if(--u32TimeOutCount == 0) + { + g_SPIM_i32ErrCode = SPIM_TIMEOUT_ERR; + break; + } + } + } + + if (u32NTx && (u32NTx < 4UL)) + { + uint32_t rnm, tmp; + + rnm = u32NTx; + memcpy(&tmp, &pu8TxBuf[buf_idx], u32NTx); + buf_idx += u32NTx; + u32NTx = 0UL; + SPIM->TX[0] = tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(rnm * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + SPIM_WAIT_FREE() + { + if(--u32TimeOutCount == 0) + { + g_SPIM_i32ErrCode = SPIM_TIMEOUT_ERR; + break; + } + } + } + } +} + +/** + * @brief Read data from SPI slave. + * @param pu8TxBuf Receive buffer. + * @param u32NRx Size of receive buffer in bytes. + * @return None. + * @note This function sets g_SPIM_i32ErrCode to SPIM_TIMEOUT_ERR if waiting SPIM time-out. + */ +static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx) +{ + uint32_t buf_idx = 0UL; + uint32_t u32TimeOutCount = 0UL; + + g_SPIM_i32ErrCode = 0; + + while (u32NRx) + { + uint32_t dataNum = 0UL; /* number of words */ + + if (u32NRx >= 16UL) + { + dataNum = 4UL; + } + else if (u32NRx >= 12UL) + { + dataNum = 3UL; + } + else if (u32NRx >= 8UL) + { + dataNum = 2UL; + } + else if (u32NRx >= 4UL) + { + dataNum = 1UL; + } + + if (dataNum) + { + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(32UL); + SPIM_SET_DATA_NUM(dataNum); + SPIM_SET_GO(); + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + SPIM_WAIT_FREE() + { + if(--u32TimeOutCount == 0) + { + g_SPIM_i32ErrCode = SPIM_TIMEOUT_ERR; + break; + } + } + } + + while (dataNum) + { + uint32_t tmp; + + tmp = SPIM->RX[dataNum-1UL]; + memcpy(&pu8RxBuf[buf_idx], &tmp, 4U); + buf_idx += 4UL; + dataNum --; + u32NRx -= 4UL; + } + + if (u32NRx && (u32NRx < 4UL)) + { + uint32_t tmp; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */ + SPIM_SET_DATA_WIDTH(u32NRx * 8UL); + SPIM_SET_DATA_NUM(1UL); + SPIM_SET_GO(); + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + SPIM_WAIT_FREE() + { + if(--u32TimeOutCount == 0) + { + g_SPIM_i32ErrCode = SPIM_TIMEOUT_ERR; + break; + } + } + + tmp = SPIM->RX[0]; + memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx); + buf_idx += u32NRx; + u32NRx = 0UL; + } + } +} + +/** + * @brief Issue Read Status Register #1 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Write Status Register #1 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U}; /* 1-byte Write Status Register #1 command + 1-byte data. */ + + cmdBuf[1] = dataBuf[0]; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Read Status Register #2 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR2}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Issue Winbond Write Status Register command. This command write both Status Register-1 + * and Status Register-2. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U}; + + cmdBuf[1] = dataBuf[0]; + cmdBuf[2] = dataBuf[1]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Status Register #3 command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Status Register #3 command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSR3}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +#if 0 /* not used */ +/** + * @brief Issue Write Security Register command. + * @param dataBuf Transmit buffer. + * @param u32NTx Size of transmit buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */ + cmdBuf[1] = dataBuf[0]; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} +#endif + +/** + * @brief Issue Read Security Register command. + * @param dataBuf Receive buffer. + * @param u32NRx Size of receive buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {OPCODE_RDSCUR}; /* 1-byte Read Status Register #1 command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(dataBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Check if Erase/Write is done. + * @return 0: Not done. 1: Done. + */ +static int spim_is_write_done(uint32_t u32NBit) +{ + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), u32NBit); + return ! (status[0] & SR_WIP); +} + +/** + * @brief Wait until Erase/Write done. + * @param u32NBit N-bit transmit/receive. + * @return 0 SPIM write done. + */ +static int spim_wait_write_done(uint32_t u32NBit) +{ + uint32_t count; + int ret = -1; + + for (count = 0UL; count < SystemCoreClock/1000UL; count++) + { + if (spim_is_write_done(u32NBit)) + { + ret = 0; + break; + } + } + if (ret != 0) + { + SPIM_DBGMSG("spim_wait_write_done time-out!!\n"); + } + return ret; +} + +/** + * @brief Issue Write Enable/disable command. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +static void spim_set_write_enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = {0U}; /* 1-byte Write Enable command. */ + cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Get SPIM serial clock. + * @return SPI serial clock. + * @details This function calculates the serial clock of SPI in Hz. + */ +uint32_t SPIM_GetSClkFreq(void) +{ + uint32_t clkDiv = SPIM_GET_CLOCK_DIVIDER(); + + return clkDiv ? SystemCoreClock / (clkDiv * 2U) : SystemCoreClock; +} + +/** + * @brief Initialize SPIM flash. + * @param clrWP Clear Write Protect or not. + * @return 0 Success. + * @return -1 Unrecognized manufacture ID or failed on reading manufacture ID. + */ +int SPIM_InitFlash(int clrWP) +{ + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; + uint32_t i; + int32_t ret = -1; + + SPIM_SET_SS_ACTLVL(0); + + /* + * Because not sure in SPI or QPI mode, do QPI reset and then SPI reset. + */ + /* QPI Reset Enable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* QPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI ResetEnable */ + cmdBuf[0] = OPCODE_RSTEN; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* SPI Reset */ + cmdBuf[0] = OPCODE_RST; + SPIM_SET_SS_EN(1); /* CS activated. */ + SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */ + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (clrWP) + { + uint8_t dataBuf[] = {0x00U}; + + spim_set_write_enable(1, 1UL); /* Clear Block Protect. */ + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), 1U); + spim_wait_write_done(1UL); + } + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), 1UL); + + /* printf("ID: 0x%x, 0x%x, px%x\n", idBuf[0], idBuf[1], idBuf[2]); */ + + for (i = 0UL; i < sizeof(g_Supported_List)/sizeof(g_Supported_List[0]); i++) + { + if (idBuf[0] == g_Supported_List[i]) + { + ret = 0; + } + } + if (ret != 0) + { + SPIM_DBGMSG("Flash initialize failed!! 0x%x\n", idBuf[0]); + } + return ret; +} + +/** + * @brief Issue JEDEC ID command. + * @param idBuf ID buffer. + * @param u32NRx Size of ID buffer. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit) +{ + uint8_t cmdBuf[] = { OPCODE_RDID }; /* 1-byte JEDEC ID command. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(u32NBit); + spim_read(idBuf, u32NRx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +static void spim_enable_spansion_quad_mode(int isEn) +{ + uint8_t cmdBuf[3]; + uint8_t dataBuf[1], status1; + + cmdBuf[0] = 0x5U; /* Read Status Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("SR1 = 0x%x\n", dataBuf[0]); */ + + status1 = dataBuf[0]; + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + + spim_set_write_enable(1, 1UL); + + cmdBuf[0] = 0x1U; /* Write register */ + cmdBuf[1] = status1; + + if (isEn) + { + cmdBuf[2] = dataBuf[0] | 0x2U; /* set QUAD */ + } + else + { + cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */ + } + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 3UL); + SPIM_SET_SS_EN(0); + + spim_set_write_enable(0, 1UL); + + + cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */ + + SPIM_SET_SS_EN(1); + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SwitchNBitInput(1UL); + spim_read(dataBuf, sizeof (dataBuf)); + SPIM_SET_SS_EN(0); + + /* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */ + N_delay(10000); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Set Quad Enable/disable. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return None. + */ +void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit) +{ + uint8_t idBuf[3]; + uint8_t dataBuf[2]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + SPIM_DBGMSG("SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]); + + switch (idBuf[0]) + { + case MFGID_WINBOND: /* Winbond SPI flash */ + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + if (isEn) + { + dataBuf[1] |= SR2_QE; + } + else + { + dataBuf[1] &= ~SR2_QE; + } + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + break; + + case MFGID_MXIC: /* MXIC SPI flash. */ + case MFGID_EON: + case MFGID_ISSI: /* ISSI SPI flash. */ + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + dataBuf[0] = isEn ? SR_QE : 0U; + SPIM_WriteStatusRegister(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + break; + + case MFGID_SPANSION: + spim_enable_spansion_quad_mode(isEn); + break; + + default: + break; + } +} + +/** + * @brief Enter/exit QPI mode. + * @param isEn Enable/disable. + * @return None. + */ +static void spim_eon_set_qpi_mode(int isEn) +{ + uint8_t cmdBuf[1]; /* 1-byte command. */ + + uint8_t status[1]; + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); + + if (isEn) /* Assume in SPI mode. */ + { + cmdBuf[0] = OPCODE_ENQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + else /* Assume in QPI mode. */ + { + cmdBuf[0] = OPCODE_EXQPI; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(4UL); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + } + + SPIM_ReadStatusRegister(status, sizeof (status), 1UL); + SPIM_DBGMSG("Status: 0x%x\n", status[0]); +} + + +static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit) +{ + uint8_t cmdBuf[2]; + uint8_t dataBuf[1]; + + cmdBuf[0] = OPCODE_BRRD; + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, 1UL); + SwitchNBitInput(1UL); + spim_read(dataBuf, 1UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]); + + cmdBuf[0] = OPCODE_BRWR; + + if (isEn) + { + cmdBuf[1] = dataBuf[0] | 0x80U; /* set EXTADD */ + } + else + { + cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */ + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(1UL); + spim_write(cmdBuf, 2UL); + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Query 4-byte address mode enabled or not. + * @param u32NBit N-bit transmit/receive. + * @return 0: 4-byte address mode disabled. 1: 4-byte address mode enabled. + */ +int SPIM_Is4ByteModeEnable(uint32_t u32NBit) +{ + int isEn = 0; + int isSupt = 0; + uint8_t idBuf[3]; + uint8_t dataBuf[1]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + default: + break; + } + + if (isSupt != 0) + { + if (idBuf[0] == MFGID_WINBOND) + { + /* Winbond SPI flash. */ + SPIM_ReadStatusRegister3(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SR3_ADR); + } + else if ((idBuf[0] == MFGID_MXIC) || (idBuf[0] ==MFGID_EON)) + { + /* MXIC/EON SPI flash. */ + SPIM_ReadSecurityRegister(dataBuf, sizeof (dataBuf), u32NBit); + isEn = !! (dataBuf[0] & SCUR_4BYTE); + } + } + + return isEn; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief Enter/Exit 4-byte address mode. + * @param isEn Enable/disable. + * @param u32NBit N-bit transmit/receive. + * @return 0 success + * -1 failed + */ +int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit) +{ + int isSupt = 0L, ret = -1; + uint8_t idBuf[3]; + uint8_t cmdBuf[1]; /* 1-byte Enter/Exit 4-Byte Mode command. */ + int32_t i32TimeOutCount = 0; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + /* Based on Flash size, check if 4-byte address mode is supported. */ + switch (idBuf[0]) + { + case MFGID_WINBOND: + case MFGID_MXIC: + case MFGID_EON: + isSupt = (idBuf[2] < 0x19U) ? 0L : 1L; + break; + + case MFGID_ISSI: + isSupt = (idBuf[2] < 0x49U) ? 0L : 1L; + break; + + case MFGID_SPANSION: + SPIM_SPANSION_4Bytes_Enable(isEn, u32NBit); + isSupt = 1L; + ret = 0L; + break; + + default: + break; + } + + if ((isSupt) && (idBuf[0] != MFGID_SPANSION)) + { + cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B; + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + /* + * FIXME: Per test, 4BYTE Indicator bit doesn't set after EN4B, which + * doesn't match spec(MX25L25635E), so skip the check below. + */ + ret = 0; + if (idBuf[0] != MFGID_MXIC) + { + /* + * About over 100 instrucsions executed, just want to give + * a time-out about 1 seconds to avoid infinite loop + */ + i32TimeOutCount = (SystemCoreClock)/100; + + if (isEn) + { + while ((i32TimeOutCount-- > 0) && !SPIM_Is4ByteModeEnable(u32NBit)) { } + } + else + { + while ((i32TimeOutCount-- > 0) && SPIM_Is4ByteModeEnable(u32NBit)) { } + } + if (i32TimeOutCount <= 0) + ret = -1; + } + } + return ret; +} + + +void SPIM_WinbondUnlock(uint32_t u32NBit) +{ + uint8_t idBuf[3]; + uint8_t dataBuf[4]; + + SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit); + + if ((idBuf[0] != MFGID_WINBOND) || (idBuf[1] != 0x40) || (idBuf[2] != 0x16)) + { + SPIM_DBGMSG("SPIM_WinbondUnlock - Not W25Q32, do nothing.\n"); + return; + } + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); + dataBuf[1] &= ~0x40; /* clear Status Register-1 SEC bit */ + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit); + spim_wait_write_done(u32NBit); + + SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit); + SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit); + SPIM_DBGMSG("Status Register (after unlock): 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]); +} + +/** + * @brief Erase whole chip. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_ChipErase(uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[] = { OPCODE_CHIP_ERASE }; /* 1-byte Chip Erase command. */ + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, sizeof (cmdBuf)); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + + +/** + * @brief Erase one block. + * @param u32Addr Block to erase which contains the u32Addr. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u8ErsCmd Erase command. + * @param u32NBit N-bit transmit/receive. + * @param isSync Block or not. + * @return None. + */ +void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx = 0UL; + + spim_set_write_enable(1, u32NBit); /* Write Enable. */ + + cmdBuf[buf_idx++] = u8ErsCmd; + + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL); + } + + SPIM_SET_SS_EN(1); /* CS activated. */ + SwitchNBitOutput(u32NBit); + spim_write(cmdBuf, buf_idx); + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBit); + } +} + + +/** @cond HIDDEN_SYMBOLS */ + +/** + * @brief Write data in the same page by I/O mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param isSync Block or not. + * @return None. + */ +static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int isSync) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + spim_set_write_enable(1, u32NBitCmd); /* Write Enable. */ + + SPIM_SET_SS_EN(1); /* CS activated. */ + + SwitchNBitOutput(u32NBitCmd); + cmdBuf[0] = wrCmd; + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + SwitchNBitOutput(u32NBitDat); + spim_write(pu8TxBuf, u32NTx); /* Write out data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ + + if (isSync) + { + spim_wait_write_done(u32NBitCmd); + } +} + +/** + * @brief Write data in the same page by Page Write mode. + * @param u32Addr Start u32Address to write. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @param isSync Block or not. + * @return None. + * @note This function sets g_SPIM_i32ErrCode to SPIM_TIMEOUT_ERR if waiting SPIM time-out. + */ +static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, + uint8_t pu8TxBuf[], uint32_t wrCmd, int isSync) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + g_SPIM_i32ErrCode = 0; + + if ((wrCmd == CMD_QUAD_PAGE_PROGRAM_WINBOND) || + (wrCmd == CMD_QUAD_PAGE_PROGRAM_MXIC)) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + } + else if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */ + spim_eon_set_qpi_mode(1); /* Enter QPI mode. */ + } + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode. */ + SPIM_SET_SPIM_MODE(wrCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8TxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NTx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE() + { + if(--u32TimeOutCount == 0) + { + g_SPIM_i32ErrCode = SPIM_TIMEOUT_ERR; + break; + } + } + } + + if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) + { + spim_eon_set_qpi_mode(0); /* Exit QPI mode. */ + } +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Write data to SPI Flash by sending commands manually (I/O mode). + * @param u32Addr: Start u32Address to write. + * @param is4ByteAddr: 4-byte u32Address or not. + * @param u32NTx: Number of bytes to write. + * @param pu8TxBuf: Transmit buffer. + * @param wrCmd: Write command. + * @param u32NBitCmd: N-bit transmit command. + * @param u32NBitAddr: N-bit transmit u32Address. + * @param u32NBitDat: N-bit transmit/receive data. + * @return None. + */ +void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) /* Do all the bytes fit onto one page ? */ + { + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, u32NTx, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], + wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1); + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by sending commands manually (I/O mode). + * @param u32Addr Start u32Address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param rdCmd Read command. + * @param u32NBitCmd N-bit transmit command. + * @param u32NBitAddr N-bit transmit u32Address. + * @param u32NBitDat N-bit transmit/receive data. + * @param u32NDummy Number of dummy bytes following address. + * @return None. + */ +void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, + uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy) +{ + uint8_t cmdBuf[16]; + uint32_t buf_idx; + + SPIM_SET_SS_EN(1); /* CS activated. */ + + cmdBuf[0] = rdCmd; + SwitchNBitOutput(u32NBitCmd); + spim_write(cmdBuf, 1UL); /* Write out command. */ + + buf_idx = 0UL; + if (is4ByteAddr) + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + else + { + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16); + cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8); + cmdBuf[buf_idx++] = (uint8_t) u32Addr; + } + SwitchNBitOutput(u32NBitAddr); + spim_write(cmdBuf, buf_idx); /* Write out u32Address. */ + + buf_idx = 0UL; + while (u32NDummy --) + { + cmdBuf[buf_idx++] = 0x00U; + } + + /* Same bit mode as above. */ + spim_write(cmdBuf, buf_idx); /* Write out dummy bytes. */ + + SwitchNBitInput(u32NBitDat); + spim_read(pu8RxBuf, u32NRx); /* Read back data. */ + + SPIM_SET_SS_EN(0); /* CS deactivated. */ +} + +/** + * @brief Write data to SPI Flash by Page Write mode. + * @param u32Addr Start address to write. + * @param is4ByteAddr 4-byte address or not. + * @param u32NTx Number of bytes to write. + * @param pu8TxBuf Transmit buffer. + * @param wrCmd Write command. + * @return None. + */ +void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd) +{ + uint32_t pageOffset, toWr; + uint32_t buf_idx = 0UL; + + pageOffset = u32Addr % 256UL; + + if ((pageOffset + u32NTx) <= 256UL) + { + /* Do all the bytes fit onto one page ? */ + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, u32NTx, pu8TxBuf, wrCmd, 1); + } + else + { + toWr = 256UL - pageOffset; /* Size of data remaining on the first page. */ + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + + while (u32NTx) + { + toWr = 256UL; + if (toWr > u32NTx) + { + toWr = u32NTx; + } + + SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1); + + u32Addr += toWr; /* Advance indicator. */ + u32NTx -= toWr; + buf_idx += toWr; + } + } +} + +/** + * @brief Read data from SPI Flash by Page Read mode. + * @param u32Addr Start address to read. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32NRx Number of bytes to read. + * @param pu8RxBuf Receive buffer. + * @param u32RdCmd Read command. + * @param isSync Block or not. + * @return None. + * @note This function sets g_SPIM_i32ErrCode to SPIM_TIMEOUT_ERR if waiting SPIM time-out. + */ +void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], + uint32_t u32RdCmd, int isSync) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + g_SPIM_i32ErrCode = 0; + + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */ + + SPIM->SRAMADDR = (uint32_t) pu8RxBuf; /* SRAM u32Address. */ + SPIM->DMACNT = u32NRx; /* Transfer length. */ + SPIM->FADDR = u32Addr; /* Flash u32Address.*/ + SPIM_SET_GO(); /* Go. */ + + if (isSync) + { + SPIM_WAIT_FREE() /* Wait for DMA done. */ + { + if(--u32TimeOutCount == 0) + { + g_SPIM_i32ErrCode = SPIM_TIMEOUT_ERR; + break; + } + } + } +} + +/** + * @brief Enter Direct Map mode. + * @param is4ByteAddr 4-byte u32Address or not. + * @param u32RdCmd Read command. + * @param u32IdleIntvl Idle interval. + * @return None. + */ +void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl) +{ + SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-byte u32Address. */ + SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */ + SPIM_SET_IDL_INTVL(u32IdleIntvl); /* Idle interval. */ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP); /* Switch to Direct Map mode. */ +} + +/** + * @brief Exit Direct Map mode. + * @return None. + */ +void SPIM_ExitDirectMapMode(void) +{ + SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch back to Normal mode. */ +} + + +/*@}*/ /* end of group SPIM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPIM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sys.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sys.c new file mode 100644 index 0000000..84d0ac5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_sys.c @@ -0,0 +1,331 @@ +/**************************************************************************//** + * @file sys.c + * @version V3.00 + * @brief M460 series SYS driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +int32_t g_SYS_i32ErrCode = 0; /*!< SYS global error code */ + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_HRESETRF_Msk + * - \ref SYS_RSTSTS_MCURF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_PORF_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSTS = u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BODVL setting or BODEN is 0. + * @retval 1 System voltage is lower than BODVL setting. + * @details This function get Brown-out detector output status. + */ +uint32_t SYS_GetBODStatus(void) +{ + return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos); +} + +/** + * @brief Get reset status register value + * @param None + * @return Reset source + * @details This function get the system reset status register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSTS); +} + +/** + * @brief Check if register is locked nor not + * @param None + * @retval 0 Write-protection function is disabled. + * 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return SYS->REGLCTL & 1UL ? 0UL : 1UL; +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetChip(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk; +} + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA0_RST + * - \ref PDMA1_RST + * - \ref EBI_RST + * - \ref EMAC0_RST + * - \ref SDH0_RST + * - \ref SDH1_RST + * - \ref CRC_RST + * - \ref CCAP_RST + * - \ref HSUSBD_RST + * - \ref HBI_RST + * - \ref CRPT_RST + * - \ref KS_RST + * - \ref SPIM_RST + * - \ref HSUSBH_RST + * - \ref CANFD0_RST + * - \ref CANFD1_RST + * - \ref CANFD2_RST + * - \ref CANFD3_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref ACMP01_RST + * - \ref ACMP23_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref I2C2_RST + * - \ref I2C3_RST + * - \ref I2C4_RST + * - \ref QSPI0_RST + * - \ref QSPI1_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref SPI3_RST + * - \ref SPI4_RST + * - \ref SPI5_RST + * - \ref SPI6_RST + * - \ref SPI7_RST + * - \ref SPI8_RST + * - \ref SPI9_RST + * - \ref SPI10_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref UART3_RST + * - \ref UART4_RST + * - \ref UART5_RST + * - \ref UART6_RST + * - \ref UART7_RST + * - \ref UART8_RST + * - \ref UART9_RST + * - \ref OTG_RST + * - \ref USBD_RST + * - \ref EADC0_RST + * - \ref EADC1_RST + * - \ref EADC2_RST + * - \ref I2S0_RST + * - \ref I2S1_RST + * - \ref HSOTG_RST + * - \ref TRNG_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref SC2_RST + * - \ref USCI0_RST + * - \ref PSIO_RST + * - \ref DAC_RST + * - \ref EPWM0_RST + * - \ref EPWM1_RST + * - \ref BPWM0_RST + * - \ref BPWM1_RST + * - \ref EQEI0_RST + * - \ref EQEI1_RST + * - \ref EQEI2_RST + * - \ref EQEI3_RST + * - \ref ECAP0_RST + * - \ref ECAP1_RST + * - \ref ECAP2_RST + * - \ref ECAP3_RST + * - \ref EADC1_RST + * - \ref KPI_RST + * @return None + * @details This function reset selected module. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; + + /* Generate reset signal to the corresponding module */ + u32tmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL)); + u32tmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL)); + *(uint32_t *)u32tmpAddr |= u32tmpVal; + + /* Release corresponding module from reset state */ + u32tmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); + *(uint32_t *)u32tmpAddr &= u32tmpVal; +} + +/** + * @brief Enable and configure Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD_RST_EN + * - \ref SYS_BODCTL_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_1_6V + * @return None + * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + /* Enable Brown-out Detector function */ + /* Enable Brown-out interrupt or reset function */ + /* Select Brown-out Detector threshold voltage */ + SYS->BODCTL = (SYS->BODCTL & ~(SYS_BODCTL_BODRSTEN_Msk | SYS_BODCTL_BODVL_Msk)) | + ((uint32_t)i32Mode) | (u32BODLevel) | (SYS_BODCTL_BODEN_Msk); +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + * The register write-protection function should be disabled before using this function. + */ +void SYS_DisableBOD(void) +{ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; +} + +/** + * @brief Set Power Level + * @param[in] u32PowerLevel is power level setting. Including : + * - \ref SYS_PLCTL_PLSEL_PL0 + * - \ref SYS_PLCTL_PLSEL_PL1 + * @return None + * @details This function select power level. + * The register write-protection function should be disabled before using this function. + * @note This function sets g_SYS_i32ErrCode to SYS_TIMEOUT_ERR if waiting SYS time-out. + */ +void SYS_SetPowerLevel(uint32_t u32PowerLevel) +{ + uint32_t u32TimeOutCount = 0; + + g_SYS_i32ErrCode = 0; + + /* Wait for power level change busy flag is cleared */ + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SYS_i32ErrCode = SYS_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + /* Set power voltage level */ + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel); + + /* Wait for power level change busy flag is cleared */ + u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk) + { + if(--u32TimeOutCount == 0) + { + g_SYS_i32ErrCode = SYS_TIMEOUT_ERR; /* Time-out error */ + break; + } + } +} + +/** + * @brief Set Reference Voltage + * @param[in] u32VRefCTL is reference voltage setting. Including : + * - \ref SYS_VREFCTL_VREF_PIN + * - \ref SYS_VREFCTL_VREF_1_6V + * - \ref SYS_VREFCTL_VREF_2_0V + * - \ref SYS_VREFCTL_VREF_2_5V + * - \ref SYS_VREFCTL_VREF_3_0V + * @return None + * @details This function select reference voltage. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetVRef(uint32_t u32VRefCTL) +{ + /* Set reference voltage */ + SYS->VREFCTL = (SYS->VREFCTL & (~SYS_VREFCTL_VREFCTL_Msk)) | (u32VRefCTL); +} + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_timer.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_timer.c new file mode 100644 index 0000000..8a58203 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_timer.c @@ -0,0 +1,437 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.00 + * @brief Timer Controller(Timer) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if(u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32Clk / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return(u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return Delay success or not + * @retval 0 Success, target delay time reached + * @retval TIMER_TIMEOUT_ERR Delay function execute failed due to timer stop working + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +int32_t TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, u32Delay; + uint32_t u32Cmpr, u32Cntr, u32NsecPerTick, i = 0UL; + + /* Clear current timer configuration */ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if(u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if(u32Usec < 100UL) + { + u32Usec = 100UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if(u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32Clk / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay larger than 1 ECLK here allowing timer start counting and raise active flag. */ + for(u32Delay = (SystemCoreClock / u32Clk) + 1UL; u32Delay > 0UL; u32Delay--) + { + __NOP(); + } + + /* Add a bail out counter here in case timer clock source is disabled accidentally. + Prescale counter reset every ECLK * (prescale value + 1). + The u32Delay here is to make sure timer counter value changed when prescale counter reset */ + u32Delay = (SystemCoreClock / TIMER_GetModuleClock(timer)) * (u32Prescale + 1); + u32Cntr = timer->CNT; + while(timer->CTL & TIMER_CTL_ACTSTS_Msk) + { + /* Bailed out if timer stop counting e.g. Some interrupt handler close timer clock source. */ + if(u32Cntr == timer->CNT) + { + if(i++ > u32Delay) + { + return TIMER_TIMEOUT_ERR; + } + } + else + { + i = 0; + u32Cntr = timer->CNT; + } + } + return 0; +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src, u32Clk; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC}; + + if(timer == TIMER0) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; + } + else if(timer == TIMER1) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; + } + else if(timer == TIMER2) + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; + } + else /* Timer 3 */ + { + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; + } + + if(u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1)) + { + u32Clk = CLK_GetPCLK0Freq(); + } + else + { + u32Clk = CLK_GetPCLK1Freq(); + } + } + else + { + u32Clk = au32Clk[u32Src]; + } + + return u32Clk; +} + +/** + * @brief This function is used to enable the Timer frequency counter function + * @param[in] timer The base address of Timer module. Can be \ref TIMER0 or \ref TIMER2 + * @param[in] u32DropCount This parameter has no effect in M480 series BSP + * @param[in] u32Timeout This parameter has no effect in M480 series BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * @return None + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t; /* store the timer base to configure compare value */ + + t = (timer == TIMER0) ? TIMER1 : TIMER3; + + t->CMP = 0xFFFFFFUL; + t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + + return; +} + +/** + * @brief This function is used to disable the Timer frequency counter function. + * @param[in] timer The base address of Timer module + * @return None + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + +/** + * @brief This function is used to select the interrupt source used to trigger other modules. + * @param[in] timer The base address of Timer module + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSRC_TIMEOUT_EVENT + * - \ref TIMER_TRGSRC_CAPTURE_EVENT + * @return None + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief This function is used to set modules trigger by timer interrupt + * @param[in] timer The base address of Timer module + * @param[in] u32Mask The mask of modules (EPWM/BPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of + * - \ref TIMER_TRG_TO_PWM, + * - \ref TIMER_TRG_TO_EADC, + * - \ref TIMER_TRG_TO_DAC, and + * - \ref TIMER_TRG_TO_PDMA + * @return None + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Reset success or not + * @retval 0 Timer reset success + * @retval TIMER_TIMEOUT_ERR Timer reset failed + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +int32_t TIMER_ResetCounter(TIMER_T *timer) +{ + uint32_t u32Delay; + + timer->CNT = 0UL; + /* Takes 2~3 ECLKs to reset timer counter */ + u32Delay = (SystemCoreClock / TIMER_GetModuleClock(timer)) * 3; + while(((timer->CNT&TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) && (--u32Delay)) + { + __NOP(); + } + return u32Delay > 0 ? 0 : TIMER_TIMEOUT_ERR; +} + +/** + * @brief Enable Capture Input Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] u32FilterCount Noise filter counter. Valid values are between 0~7. + * + * @param[in] u32ClkSrcSel Noise filter counter clock source, could be one of following source + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_1 + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_2 + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_4 + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_8 + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_16 + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_32 + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_64 + * - \ref TIMER_CAPTURE_NOISE_FILTER_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable capture input noise filter function. + */ +void TIMER_EnableCaptureInputNoiseFilter(TIMER_T *timer, uint32_t u32FilterCount, uint32_t u32ClkSrcSel) +{ + timer->CAPNF = (((timer)->CAPNF & ~(TIMER_CAPNF_CAPNFCNT_Msk | TIMER_CAPNF_CAPNFSEL_Msk)) + | (TIMER_CAPNF_CAPNFEN_Msk | (u32FilterCount << TIMER_CAPNF_CAPNFCNT_Pos) | (u32ClkSrcSel << TIMER_CAPNF_CAPNFSEL_Pos))); +} + +/** + * @brief Disable Capture Input Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable capture input noise filter function. + */ +void TIMER_DisableCaptureInputNoiseFilter(TIMER_T *timer) +{ + timer->CAPNF &= ~TIMER_CAPNF_CAPNFEN_Msk; +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_timer_pwm.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_timer_pwm.c new file mode 100644 index 0000000..9b810fb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_timer_pwm.c @@ -0,0 +1,595 @@ +/**************************************************************************//** + * @file timer_pwm.c + * @version V3.00 + * @brief Timer PWM Controller(Timer PWM) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Set PWM Counter Clock Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source + * - \ref TPWM_CNTR_CLKSRC_TMR_CLK + * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT + * + * @return None + * + * @details This function is used to set PWM counter clock source. + */ +void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc) +{ + (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc; +} + +/** + * @brief Configure PWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP; + + if((timer == TIMER0) || (timer == TIMER1)) + { + u32PWMClockFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PWMClockFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate u16PERIOD and u16PSC */ + for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if(u32Period <= 0x10000UL) + { + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to up count type */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos); + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | TPWM_AUTO_RELOAD_MODE; + + /* Convert to real register value */ + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + if(u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + + return (u32TargetFreq); +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Disable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable Dead-time of selected channel. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableDeadTime(TIMER_T *timer) +{ + timer->PWMDTCTL = 0x0UL; +} + +/** + * @brief Enable PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable PWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable PWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger EADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_EADC_AT_ZERO_POINT + * - \ref TPWM_TRIGGER_EADC_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_EADC_AT_ZERO_OR_PERIOD_POINT + * - \ref TPWM_TRIGGER_EADC_AT_COMPARE_UP_COUNT_POINT + * - \ref TPWM_TRIGGER_EADC_AT_COMPARE_DOWN_COUNT_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger EADC. + */ +void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMTRGCTL = TIMER_PWMTRGCTL_TRGEADC_Msk | u32Condition; +} + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +void TPWM_DisableTriggerADC(TIMER_T *timer) +{ + timer->PWMTRGCTL = 0x0UL; +} + +/** + * @brief Enable Fault Brake Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32BrakeSource Fault brake source, combination of following source + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM + * + * @return None + * + * @details This function is used to enable fault brake function. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource) +{ + timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL); + timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) | + (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos); +} + +/** + * @brief Enable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to enable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 |= u32IntSource; +} + +/** + * @brief Disable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to disable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 &= ~u32IntSource; +} + +/** + * @brief Indicate Fault Brake Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * + * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source. + */ +uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource))? 1UL : 0UL); +} + +/** + * @brief Clear Fault Brake Interrupt Flags + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to clear fault brake interrupt flags of selected source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTSTS1 = (0x3UL << u32IntSource); +} + +/** + * @brief Enable Load Mode of Selected Channel + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode + * - \ref TPWM_LOAD_MODE_PERIOD + * - \ref TPWM_LOAD_MODE_IMMEDIATE + * - \ref TPWM_LOAD_MODE_CENTER + * + * @return None + * + * @details This function is used to enable load mode of selected channel. + * @note The default loading mode is period loading mode. + */ +void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode) +{ + timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode; +} + +/** + * @brief Enable Brake Pin Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @param[in] u32DebounceCnt This value controls the real debounce sample time. + * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt). + * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable external brake pin detector noise filter function. + */ +void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel) +{ + timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) | + (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) | + (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) | + (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Disable Brake Pin Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable external brake pin detector noise filter function. + */ +void TPWM_DisableBrakePinDebounce(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk; +} + + +/** + * @brief Enable Brake Pin Inverse Function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to enable PWM brake pin inverse function. + */ +void TPWM_EnableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Disable Brake Pin Inverse Function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable PWM brake pin inverse function. + */ +void TPWM_DisableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Set Brake Pin Source + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinNum Brake pin selection. One of the following: + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @return None + * @details This function is used to set PWM brake pin source. + */ +void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum) +{ + timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos)); +} + +/** + * @brief Enable Interrupt Flag Accumulator + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref TPWM_IFA_ZERO_POINT + * - \ref TPWM_IFA_PERIOD_POINT + * - \ref TPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref TPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator. + */ +void TPWM_EnableAcc(TIMER_T *timer, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + timer->PWMIFA = (((timer)->PWMIFA & ~(TIMER_PWMIFA_IFACNT_Msk | TIMER_PWMIFA_IFASEL_Msk | TIMER_PWMIFA_STPMOD_Msk)) + | (TIMER_PWMIFA_IFAEN_Msk | (u32IntFlagCnt << TIMER_PWMIFA_IFACNT_Pos) | (u32IntAccSrc << TIMER_PWMIFA_IFASEL_Pos))); +} + +/** + * @brief Disable Interrupt Flag Accumulator + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable interrupt flag accumulator. + */ +void TPWM_DisableAcc(TIMER_T *timer) +{ + timer->PWMIFA &= ~TIMER_PWMIFA_IFAEN_Msk; +} + +/** + * @brief Enable Interrupt Flag Accumulator Interrupt Function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt. + */ +void TPWM_EnableAccInt(TIMER_T *timer) +{ + timer->PWMAINTEN |= TIMER_PWMAINTEN_IFAIEN_Msk; +} + +/** + * @brief Disable Interrupt Flag Accumulator Interrupt Function + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt. + */ +void TPWM_DisableAccInt(TIMER_T *timer) +{ + timer->PWMAINTEN &= ~TIMER_PWMAINTEN_IFAIEN_Msk; +} + +/** + * @brief Clear Interrupt Flag Accumulator Interrupt Flag + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt. + */ +void TPWM_ClearAccInt(TIMER_T *timer) +{ + timer->PWMAINTSTS = TIMER_PWMAINTSTS_IFAIF_Msk; +} + +/** + * @brief Get Interrupt Flag Accumulator Interrupt Flag + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to get interrupt flag accumulator interrupt. + */ +uint32_t TPWM_GetAccInt(TIMER_T *timer) +{ + return (((timer)->PWMAINTSTS & TIMER_PWMAINTSTS_IFAIF_Msk)? 1UL : 0UL); +} + +/** + * @brief Enable Accumulator Interrupt Trigger PDMA + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA transfer. + */ +void TPWM_EnableAccPDMA(TIMER_T *timer) +{ + timer->PWMAPDMACTL |= TIMER_PWMAPDMACTL_APDMAEN_Msk; +} + +/** + * @brief Disable Accumulator Interrupt Trigger PDMA + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA transfer. + */ +void TPWM_DisableAccPDMA(TIMER_T *timer) +{ + timer->PWMAPDMACTL &= ~TIMER_PWMAPDMACTL_APDMAEN_Msk; +} + +/** + * @brief Enable Interrupt Flag Accumulator Stop Mode + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to enable interrupt flag accumulator event to stop PWM counting. + */ +void TPWM_EnableAccStopMode(TIMER_T *timer) +{ + timer->PWMIFA |= TIMER_PWMIFA_STPMOD_Msk; +} + +/** + * @brief Disable Interrupt Flag Accumulator Stop Mode + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable interrupt flag accumulator event to stop PWM counting. + */ +void TPWM_DisableAccStopMode(TIMER_T *timer) +{ + timer->PWMIFA &= ~TIMER_PWMIFA_STPMOD_Msk; +} + +/** + * @brief Enable External Event Trigger Counter Action + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ExtEventSrc External event source selection. + * - \ref TPWM_EXT_TGR_PIN_INT0 + * - \ref TPWM_EXT_TGR_PIN_INT1 + * - \ref TPWM_EXT_TGR_PIN_INT2 + * - \ref TPWM_EXT_TGR_PIN_INT3 + * - \ref TPWM_EXT_TGR_PIN_INT4 + * - \ref TPWM_EXT_TGR_PIN_INT5 + * - \ref TPWM_EXT_TGR_PIN_INT6 + * - \ref TPWM_EXT_TGR_PIN_INT7 + * @param[in] u32CounterAction Counter action selection. + * - \ref TPWM_EXT_TGR_COUNTER_RESET + * - \ref TPWM_EXT_TGR_COUNTER_START + * - \ref TPWM_EXT_TGR_COUNTER_RESET_AND_START + * @return None + * @details This function is used to enable external event to trigger the counter specified action. + */ +void TPWM_EnableExtEventTrigger(TIMER_T *timer, uint32_t u32ExtEventSrc, uint32_t u32CounterAction) +{ + timer->PWMEXTETCTL = (((timer)->PWMEXTETCTL & ~(TIMER_PWMEXTETCTL_EXTTRGS_Msk | TIMER_PWMEXTETCTL_CNTACTS_Msk)) + | (TIMER_PWMEXTETCTL_EXTETEN_Msk | (u32ExtEventSrc << TIMER_PWMEXTETCTL_EXTTRGS_Pos) | (u32CounterAction << TIMER_PWMEXTETCTL_CNTACTS_Pos))); +} + +/** + * @brief Disable External Event Trigger Counter Action + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @return None + * @details This function is used to disable external event to trigger counter action. + */ +void TPWM_DisableExtEventTrigger(TIMER_T *timer) +{ + timer->PWMEXTETCTL &= ~TIMER_PWMEXTETCTL_EXTETEN_Msk; +} + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_trng.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_trng.c new file mode 100644 index 0000000..927b5c9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_trng.c @@ -0,0 +1,177 @@ +/**************************************************************************//** + * @file trng.c + * @version V3.00 + * @brief M460 series TRNG driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include + +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TRNG_Driver TRNG Driver + @{ +*/ + + +/** @addtogroup TRNG_EXPORTED_FUNCTIONS TRNG Exported Functions + @{ +*/ + + +/** + * @brief Initialize TRNG hardware. + * @return TRNG hardware enable success or failed. + * @retval 0 Success + * @retval -1 Time-out. TRNG hardware may not be enabled. + */ +int32_t TRNG_Open(void) +{ + uint32_t u32TimeOutCount = SystemCoreClock; /* 1 second time-out */ + + SYS->IPRST1 |= SYS_IPRST1_TRNGRST_Msk; + SYS->IPRST1 ^= SYS_IPRST1_TRNGRST_Msk; + + TRNG->CTL |= TRNG_CTL_TRNGEN_Msk; + + TRNG->ACT |= TRNG_ACT_ACT_Msk; + + /* Waiting for ready */ + while ((TRNG->CTL & TRNG_CTL_READY_Msk) == 0) + { + if(--u32TimeOutCount == 0) return -1; /* Time-out error */ + } + + return 0; +} + + +/** + * @brief Generate a 32-bits random number word. + * @param[out] u32RndNum The output 32-bits word random number. + * + * @return Success or time-out. + * @retval 0 Success + * @retval -1 Time-out. TRNG hardware may not be enabled. + */ +int32_t TRNG_GenWord(uint32_t *u32RndNum) +{ + uint32_t i, u32Reg, timeout; + + *u32RndNum = 0; + u32Reg = TRNG->CTL; + + for (i = 0; i < 4; i++) + { + TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; + + /* TRNG should generate one byte per 125*8 us */ + for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--) + { + if (TRNG->CTL & TRNG_CTL_DVIF_Msk) + break; + } + + if (timeout == 0) + return -1; + + *u32RndNum |= ((TRNG->DATA & 0xff) << i*8); + + } + return 0; +} + +/** + * @brief Generate a big number in binary format. + * @param[out] u8BigNum The output big number. + * @param[in] i32Len Request bit length of the output big number. It must be multiple of 8. + * + * @return Success or time-out. + * @retval 0 Success + * @retval -1 Time-out. TRNG hardware may not be enabled. + */ +int32_t TRNG_GenBignum(uint8_t u8BigNum[], int32_t i32Len) +{ + uint32_t i, u32Reg, timeout; + + u32Reg = TRNG->CTL; + + for (i = 0; i < i32Len/8; i++) + { + TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; + + /* TRNG should generate one byte per 125*8 us */ + for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--) + { + if (TRNG->CTL & TRNG_CTL_DVIF_Msk) + break; + } + + if (timeout == 0) + return -1; + + u8BigNum[i] = (TRNG->DATA & 0xff); + } + return 0; +} + +/** + * @brief Generate a big number in hex format. + * @param[out] cBigNumHex The output hex format big number. + * @param[in] i32Len Request bit length of the output big number. It must be multiple of 8. + * + * @return Success or time-out. + * @retval 0 Success + * @retval -1 Time-out. TRNG hardware may not be enabled. + */ +int32_t TRNG_GenBignumHex(char cBigNumHex[], int32_t i32Len) +{ + uint32_t i, idx, u32Reg, timeout; + uint32_t data; + + u32Reg = TRNG->CTL; + idx = 0; + for (i = 0; i < i32Len/8; i++) + { + TRNG->CTL = TRNG_CTL_TRNGEN_Msk | u32Reg; + + /* TRNG should generate one byte per 125*8 us */ + for (timeout = (CLK_GetHCLKFreq() / 100); timeout > 0; timeout--) + { + if (TRNG->CTL & TRNG_CTL_DVIF_Msk) + break; + } + + if (timeout == 0) + return -1; + + data = (TRNG->DATA & 0xff); + + if (data >= 0xA0) + cBigNumHex[idx++] = ((data >> 4) & 0xf) - 10 + 'A'; + else + cBigNumHex[idx++] = ((data >> 4) & 0xf) + '0'; + + data &= 0xf; + if (data >= 0xA) + cBigNumHex[idx++] = data - 10 + 'A'; + else + cBigNumHex[idx++] = data + '0'; + } + cBigNumHex[idx] = 0; + return 0; +} + + +/*@}*/ /* end of group TRNG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TRNG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_uart.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_uart.c new file mode 100644 index 0000000..9210b0f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_uart.c @@ -0,0 +1,670 @@ +/**************************************************************************//** + * @file uart.c + * @version V3.00 + * @brief M460 series UART driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt Indicator + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag) +{ + if(u32InterruptFlag & UART_INTSTS_SWBEINT_Msk) /* Clear Single-wire Bit Error Detect Interrupt */ + { + uart->FIFOSTS = UART_INTSTS_SWBEIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk | UART_FIFOSTS_ADDRDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk |UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */ + { + uart->INTSTS = UART_INTSTS_LINIF_Msk; + uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk | + UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk | + UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ; + } +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T* uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_SWBEIEN_Msk : Single-wire Bit Error Detect Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details The function is used to disable UART specified interrupt. + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T* uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief Enable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_SWBEIEN_Msk : Single-wire Bit Error Detect Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details The function is used to enable UART specified interrupt. + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul; + uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32BaudDiv = 0ul; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + break; + case UART1_BASE: + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + break; + case UART2_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + break; + case UART3_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + break; + case UART4_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + break; + case UART5_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + break; + case UART6_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos; + break; + case UART7_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos; + break; + case UART8_BASE: + u32UartClkSrcSel = (CLK->CLKSEL2 & CLK_CLKSEL2_UART8SEL_Msk) >> CLK_CLKSEL2_UART8SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART8DIV_Msk) >> CLK_CLKDIV5_UART8DIV_Pos; + break; + case UART9_BASE: + u32UartClkSrcSel = (CLK->CLKSEL2 & CLK_CLKSEL2_UART9SEL_Msk) >> CLK_CLKSEL2_UART9SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART9DIV_Msk) >> CLK_CLKDIV5_UART9DIV_Pos; + break; + default: + return; + } + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL/2 clock frequency if UART clock source selection is PLL/2 */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[1] = CLK_GetPLLClockFreq()>>1; + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32BaudDiv > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul; + uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32BaudDiv = 0ul; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + break; + case UART1_BASE: + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + break; + case UART2_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + break; + case UART3_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + break; + case UART4_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + break; + case UART5_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + break; + case UART6_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos; + break; + case UART7_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos; + break; + case UART8_BASE: + u32UartClkSrcSel = (CLK->CLKSEL2 & CLK_CLKSEL2_UART8SEL_Msk) >> CLK_CLKSEL2_UART8SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART8DIV_Msk) >> CLK_CLKDIV5_UART8DIV_Pos; + break; + case UART9_BASE: + u32UartClkSrcSel = (CLK->CLKSEL2 & CLK_CLKSEL2_UART9SEL_Msk) >> CLK_CLKSEL2_UART9SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART9DIV_Msk) >> CLK_CLKDIV5_UART9DIV_Pos; + break; + default: + return; + } + + /* Get PLL/2 clock frequency if UART clock source selection is PLL/2 */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[1] = CLK_GetPLLClockFreq()>>1; + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32BaudDiv > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv); + } + } + + /* Set UART line configuration */ + uart->LINE = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul; + uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32BaudDiv = 0ul; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + break; + case UART1_BASE: + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + break; + case UART2_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + break; + case UART3_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART3SEL_Msk) >> CLK_CLKSEL3_UART3SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART3DIV_Msk) >> CLK_CLKDIV4_UART3DIV_Pos; + break; + case UART4_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART4SEL_Msk) >> CLK_CLKSEL3_UART4SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART4DIV_Msk) >> CLK_CLKDIV4_UART4DIV_Pos; + break; + case UART5_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART5SEL_Msk) >> CLK_CLKSEL3_UART5SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART5DIV_Msk) >> CLK_CLKDIV4_UART5DIV_Pos; + break; + case UART6_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART6SEL_Msk) >> CLK_CLKSEL3_UART6SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART6DIV_Msk) >> CLK_CLKDIV4_UART6DIV_Pos; + break; + case UART7_BASE: + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART7SEL_Msk) >> CLK_CLKSEL3_UART7SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART7DIV_Msk) >> CLK_CLKDIV4_UART7DIV_Pos; + break; + case UART8_BASE: + u32UartClkSrcSel = (CLK->CLKSEL2 & CLK_CLKSEL2_UART8SEL_Msk) >> CLK_CLKSEL2_UART8SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART8DIV_Msk) >> CLK_CLKDIV5_UART8DIV_Pos; + break; + case UART9_BASE: + u32UartClkSrcSel = (CLK->CLKSEL2 & CLK_CLKSEL2_UART9SEL_Msk) >> CLK_CLKSEL2_UART9SEL_Pos; + u32UartClkDivNum = (CLK->CLKDIV5 & CLK_CLKDIV5_UART9DIV_Msk) >> CLK_CLKDIV5_UART9DIV_Pos; + break; + default: + return; + } + + /* Get PLL/2 clock frequency if UART clock source selection is PLL/2 */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[1] = CLK_GetPLLClockFreq()>>1; + } + + /* Set UART IrDA baud rate in mode 0 */ + if(u32Buadrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate); + + if(u32BaudDiv < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32BaudDiv); + } + } + + /* Configure IrDA relative settings */ + if(u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /* Rx signal is inverse */ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /* Tx signal is not inverse */ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - \ref UART_ALTCTL_LINTXEN_Msk + * - \ref UART_ALTCTL_LINRXEN_Msk + * @param[in] u32BreakLength The break field length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUNCSEL = UART_FUNCSEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk); + uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while(uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) /* Wait Tx not full or Time-out manner */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; +} + +/** + * @brief Select Single Wire mode function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to select Single Wire mode. + */ +void UART_SelectSingleWireMode(UART_T *uart) +{ + /* Select UART Single Wire function mode */ + uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE); +} + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usbd.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usbd.c new file mode 100644 index 0000000..72afae6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usbd.c @@ -0,0 +1,743 @@ +/**************************************************************************//** + * @file usbd.c + * @version V3.00 + * @brief M460 series USBD driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_usbd_SetupPacket[8] = {0ul}; /*!< Setup packet buffer */ +volatile uint8_t g_usbd_RemoteWakeupEn = 0ul; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static uint8_t *g_usbd_CtrlInPointer = 0; +static uint8_t *g_usbd_CtrlOutPointer = 0; +static volatile uint32_t g_usbd_CtrlInSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSize = 0ul; +static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0ul; +static volatile uint32_t g_usbd_UsbAddr = 0ul; +static volatile uint32_t g_usbd_UsbConfig = 0ul; +static volatile uint32_t g_usbd_CtrlMaxPktSize = 8ul; +static volatile uint32_t g_usbd_UsbAltInterface = 0ul; +static volatile uint8_t g_usbd_CtrlInZeroFlag = 0ul; +/** + * @endcond + */ + +const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + g_usbd_sInfo = param; + g_usbd_pfnClassRequest = pfnClassReq; + g_usbd_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ +#ifdef SUPPORT_LPM + USBD->ATTR = 0x7D0ul | USBD_LPMACK; +#else + USBD->ATTR = 0x7D0ul; +#endif + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_usbd_SetupPacket, 8ul); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul); + + /* Check the request type */ + switch(g_usbd_SetupPacket[0] & 0x60ul) + { + case REQ_STANDARD: + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: + { + if(g_usbd_pfnClassRequest != NULL) + { + g_usbd_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: + { + if(g_usbd_pfnVendorRequest != NULL) + { + g_usbd_pfnVendorRequest(); + } + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + u32Len = 0ul; + u32Len = g_usbd_SetupPacket[7]; + u32Len <<= 8ul; + u32Len += g_usbd_SetupPacket[6]; + + switch(g_usbd_SetupPacket[3]) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len); + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len); + break; + } + /* Get BOS Descriptor */ + case DESC_BOS: + { + if(g_usbd_sInfo->gu8BosDesc == 0) + { + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + } + else + { + u32Len = USBD_Minimum(u32Len, LEN_BOS + LEN_BOSCAP); + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8BosDesc, u32Len); + } + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + + u32Len = USBD_Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if(u32Len > g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]) + { + u32Len = g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]; + if((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + /* Get String Descriptor */ + if(g_usbd_SetupPacket[2] < 4ul) + { + if(u32Len > g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]) + { + u32Len = g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]; + if((u32Len % g_usbd_CtrlMaxPktSize) == 0ul) + { + g_usbd_CtrlInZeroFlag = (uint8_t)1ul; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len); + break; + } + else + { + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + default: + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + uint32_t addr; + + /* clear global variables for new request */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + + if((g_usbd_SetupPacket[0] & 0x80ul) == 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch(g_usbd_SetupPacket[1]) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + USBD_PrepareCtrlOut(0, 0ul); /* For status stage */ + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + /* Data stage */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)g_usbd_UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + case GET_STATUS: + { + /* Device */ + if(g_usbd_SetupPacket[0] == 0x80ul) + { + uint8_t u8Tmp = 0; + + u8Tmp = (uint8_t)0ul; + if((g_usbd_sInfo->gu8ConfigDesc[7] & 0x40ul) == 0x40ul) + { + u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered.*/ + } + if((g_usbd_sInfo->gu8ConfigDesc[7] & 0x20ul) == 0x20ul) + { + u8Tmp |= (uint8_t)(g_usbd_RemoteWakeupEn << 1ul); /* Remote wake up */ + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = u8Tmp; + } + /* Interface */ + else if(g_usbd_SetupPacket[0] == 0x81ul) + { + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)0ul; + } + /* Endpoint */ + else if(g_usbd_SetupPacket[0] == 0x82ul) + { + uint8_t ep = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(addr) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul); + } + + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1ul; + M8(addr) = (uint8_t)0ul; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } + else + { + /* Host to device */ + switch(g_usbd_SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_u32EpStallLock is added to support it */ + epNum = (uint8_t)(g_usbd_SetupPacket[4] & 0xFul); + for(i = 0ul; i < USBD_MAX_EP; i++) + { + if(((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_u32EpStallLock & (1ul << i)) == 0ul)) + { + USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + } + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)0; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_ADDRESS: + { + g_usbd_UsbAddr = g_usbd_SetupPacket[2]; + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_CONFIGURATION: + { + g_usbd_UsbConfig = g_usbd_SetupPacket[2]; + + if(g_usbd_pfnSetConfigCallback) + { + g_usbd_pfnSetConfigCallback(); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_FEATURE: + { + if((g_usbd_SetupPacket[0] & 0xFul) == 0ul) /* 0: device */ + { + if((g_usbd_SetupPacket[2] == 3ul) && (g_usbd_SetupPacket[3] == 0ul)) /* 3: HNP enable */ + { + OTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); + } + } + if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall((uint8_t)(g_usbd_SetupPacket[4] & 0xFul)); + } + else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_usbd_RemoteWakeupEn = (uint8_t)1ul; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + case SET_INTERFACE: + { + g_usbd_UsbAltInterface = g_usbd_SetupPacket[2]; + if(g_usbd_pfnSetInterface != NULL) + { + g_usbd_pfnSetInterface(g_usbd_UsbAltInterface); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t addr; + + if(u32Size > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + } + else + { + /* Data size <= MXPLD */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + USBD_SET_DATA1(EP0); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + uint32_t addr; + + if(g_usbd_CtrlInSize) + { + /* Process remained data */ + if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize) + { + /* Data size > MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize); + g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize; + g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)addr, (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize); + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + } + } + else + { + /* In ACK for Set address */ + if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) + { + addr = USBD_GET_ADDR(); + if((addr != g_usbd_UsbAddr) && (addr == 0ul)) + { + USBD_SET_ADDR(g_usbd_UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(g_usbd_CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + g_usbd_CtrlInZeroFlag = (uint8_t)0ul; + } + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + g_usbd_CtrlOutPointer = pu8Buf; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + uint32_t addr; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1); + USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)addr, u32Size); + g_usbd_CtrlOutPointer += u32Size; + g_usbd_CtrlOutSize += u32Size; + + if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit) + { + USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize); + } + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + uint32_t i, u32CFG; + + /* Reset all variables for protocol */ + g_usbd_CtrlInPointer = 0; + g_usbd_CtrlInSize = 0ul; + g_usbd_CtrlOutPointer = 0; + g_usbd_CtrlOutSize = 0ul; + g_usbd_CtrlOutSizeLimit = 0ul; + g_u32EpStallLock = 0ul; + memset(g_usbd_SetupPacket, 0, 8ul); + + for(i = 0ul; i < USBD_MAX_EP; i++) + { + if(!USBD_IS_DB_MODE(i)) + { + /* Reset PID DATA0 */ + USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + else + { + /* Reset double buffer setting */ + u32CFG = USBD->EP[i].CFG; + USBD->EP[i].CFG = u32CFG; + } + } + + /* Reset USB device address */ + USBD_SET_ADDR(0ul); +} + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_usbd_pfnVendorRequest = pfnVendorReq; +} + +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_usbd_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +/** + * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request. + * + * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked + * + * @return None + * + * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request. + * If ep stall locked, user needs to reset USB device or re-configure device to clear it. + */ +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_u32EpStallLock = u32EpBitmap; +} + + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_i2c.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_i2c.c new file mode 100644 index 0000000..1bb91e9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_i2c.c @@ -0,0 +1,1805 @@ +/****************************************************************************//** + * @file usci_i2c.c + * @version V3.00 + * @brief M460 series USCI I2C(UI2C) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +int32_t g_UI2C_i32ErrCode = 0; /*!< UI2C global error code */ + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This function makes USCI_I2C module be ready and set the wanted bus clock + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format). + */ +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if( ui2c == UI2C0 ) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Enable USCI_I2C protocol */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; + ui2c->CTL = 4U << UI2C_CTL_FUNMODE_Pos; + + /* Data format configuration */ + /* 8 bit data length */ + ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk; + ui2c->LINECTL |= 8U << UI2C_LINECTL_DWIDTH_Pos; + + /* MSB data format */ + ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk; + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk; + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function closes the USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Close USCI_I2C protocol function. + */ +void UI2C_Close(UI2C_T *ui2c) +{ + /* Disable USCI_I2C function */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; +} + +/** + * @brief This function clears the time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Clear time-out flag when time-out flag is set. + */ +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c) +{ + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; +} + +/** + * @brief This function sets the control bit of the USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Start Set START bit to USCI_I2C module. + * @param[in] u8Stop Set STOP bit to USCI_I2C module. + * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module. + * @param[in] u8Ack Set ACK bit to USCI_I2C module. + * + * @return None + * + * @details The function set USCI_I2C control bit of USCI_I2C bus protocol. + */ +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk); + + if (u8Start) + { + u32Reg |= UI2C_PROTCTL_STA_Msk; + } + if (u8Stop) + { + u32Reg |= UI2C_PROTCTL_STO_Msk; + } + if (u8Ptrg) + { + u32Reg |= UI2C_PROTCTL_PTRG_Msk; + } + if (u8Ack) + { + u32Reg |= UI2C_PROTCTL_AA_Msk; + } + + ui2c->PROTCTL = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to an interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details The function is used to disable USCI_I2C bus interrupt events. + */ +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Disable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk; + } + + /* Disable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk; + } + + /* Disable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk; + } + + /* Disable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Disable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Disable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Disable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function enables the interrupt of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * @return None + * + * @details The function is used to enable USCI_I2C bus interrupt events. + */ +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Enable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk; + } + + /* Enable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk; + } + + /* Enable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk; + } + + /* Enable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Enable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Enable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Enable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function returns the real bus clock of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details The function returns the actual USCI_I2C module bus clock. + */ +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c) +{ + uint32_t u32Divider; + uint32_t u32Pclk; + + u32Pclk = CLK_GetPCLK1Freq(); + u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos; + + return ( u32Pclk / ((u32Divider+1U)<<1U) ); +} + +/** + * @brief This function sets bus clock frequency of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock. + */ +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + u32Pclk = CLK_GetPCLK1Freq(); + u32ClkDiv = (uint32_t) ((((((u32Pclk/2U)*10U)/(u32BusClock))+5U)/10U)-1U); /* Compute proper divider for USCI_I2C clock */ + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + + return ( u32Pclk / ((u32ClkDiv+1U)<<1U) ); +} + +/** + * @brief This function gets the interrupt flag of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event. + */ +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U; + uint32_t u32TmpValue; + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk; + /* Check Time-out Interrupt Flag */ + if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_TO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk; + /* Check Start Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STAR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk; + /* Check Stop Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STOR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk; + /* Check Non-Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_NACK_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk; + /* Check Arbitration Lost Interrupt Flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ARBLO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk; + /* Check Error Interrupt Flag */ + if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ERR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk; + /* Check Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ACK_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief This function clears the interrupt flag of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag. + */ +void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Clear Time-out Interrupt Flag */ + if(u32Mask & UI2C_TO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; + } + + /* Clear Start Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STAR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk; + } + + /* Clear Stop Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STOR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk; + } + + /* Clear Non-Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_NACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk; + } + + /* Clear Arbitration Lost Interrupt Flag */ + if(u32Mask & UI2C_ARBLO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk; + } + + /* Clear Error Interrupt Flag */ + if(u32Mask & UI2C_ERR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk; + } + + /* Clear Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_ACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk; + } +} + +/** + * @brief This function returns the data stored in data register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return USCI_I2C data. + * + * @details To read a byte data from USCI_I2C module receive data register. + */ +uint32_t UI2C_GetData(UI2C_T *ui2c) +{ + return ( ui2c->RXDAT ); +} + +/** + * @brief This function writes a byte data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details To write a byte data to transmit data register to transmit data. + */ +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data) +{ + ui2c->TXDAT = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddr The slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref UI2C_GCMODE_ENABLE + * - \ref UI2C_GCMODE_DISABLE + * + * @return None + * + * @details To configure USCI_I2C module slave address and GC mode. + */ +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + if(u8SlaveNo) + { + ui2c->DEVADDR1 = u16SlaveAddr; + } + else + { + ui2c->DEVADDR0 = u16SlaveAddr; + } + + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) |u8GCMode; +} + +/** + * @brief Configure the mask bit of slave address. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddrMask The slave address mask. + * + * @return None + * + * @details To configure USCI_I2C module slave address mask bit. + * @note The corresponding address bit is "Don't Care". + */ +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + if(u8SlaveNo) + { + ui2c->ADDRMSK1 = u16SlaveAddrMask; + } + else + { + ui2c->ADDRMSK0 = u16SlaveAddrMask; + } +} + +/** + * @brief This function enables time-out function and configures timeout counter + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF + * + * @return None + * + * @details To enable USCI_I2C bus time-out function and set time-out counter. + */ +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt) +{ + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos); + ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function disables time-out function + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C bus time-out function. + */ +void UI2C_DisableTimeout(UI2C_T *ui2c) +{ + ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk; + ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8WakeupMode The wake-up mode selection. Valid values are: + * - \ref UI2C_DATA_TOGGLE_WK + * - \ref UI2C_ADDR_MATCH_WK + * + * @return None + * + * @details To enable USCI_I2C module wake-up function. + */ +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode) +{ + ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk); +} + +/** + * @brief This function disables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C module wake-up function. + */ +void UI2C_DisableWakeup(UI2C_T *ui2c) +{ + ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master write a byte data to Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ + +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + uint32_t u32TimeOutCount = 0U; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering && (u8Err == 0U)) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master write multi bytes data to Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ + +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U, u32TimeOutCount = 0U; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify a address that data write to in Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ + +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U, u32TimeOutCount = 0U; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + u32TimeOutCount = UI2C_TIMEOUT; + while(u8Xfering && (u8Err == 0U)) + { + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ + +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U, u32TimeOutCount = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + if (u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ + +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U, u32TimeOutCount = 0U; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering && (u8Err == 0U)) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if (u32txLen == 2U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ + +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U, u32TimeOutCount = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u8Addr = 0; + } + else + { + if (u32txLen < u32wLen) + { + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master to read a byte data from Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + uint32_t u32TimeOutCount = 0U; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering && (u8Err == 0U)) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + eEvent = MASTER_READ_DATA; + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Err = 1U; + } + else + { + rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; + + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master to read multi data bytes from Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U, u32TimeOutCount = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < (u32rLen - 1U)) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + uint32_t u32TimeOutCount = 0U; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering && (u8Err == 0U)) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U, u32TimeOutCount = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + /* SLA+R ACK */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address(2 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + uint32_t u32TimeOutCount = 0U; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering && (u8Err == 0u)) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave. + * + * @note This function sets g_UI2C_i32ErrCode to UI2C_TIMEOUT_ERR if waiting USCI_I2C time-out. + * + */ +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U, u32TimeOutCount = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + g_UI2C_i32ErrCode = 0; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + u32TimeOutCount = UI2C_TIMEOUT; + while (!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)) /* Wait UI2C new status occur */ + { + if(--u32TimeOutCount == 0) + { + g_UI2C_i32ErrCode = UI2C_TIMEOUT_ERR; /* Time-out error */ + break; + } + } + + switch (UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if (u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_spi.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_spi.c new file mode 100644 index 0000000..abc9412 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_spi.c @@ -0,0 +1,677 @@ +/**************************************************************************//** + * @file usci_spi.c + * @version V3.00 + * @brief M460 series USCI_SPI driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief This function make USCI_SPI module be ready to transfer. + * By default, the USCI_SPI transfer sequence is MSB first, the slave selection + * signal is active low and the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock + * divider setting will be 0. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref USPI_SLAVE + * - \ref USPI_MASTER + * @param[in] u32SPIMode Decide the transfer timing. Valid values are: + * - \ref USPI_MODE_0 + * - \ref USPI_MODE_1 + * - \ref USPI_MODE_2 + * - \ref USPI_MODE_3 + * @param[in] u32DataWidth The data width of a USCI_SPI transaction. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv = 0ul; + uint32_t u32Pclk; + uint32_t u32UspiClk = 0ul; + + if(uspi == (USPI_T *)USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + if(u32BusClock != 0ul) + { + u32ClkDiv = (uint32_t)((((((u32Pclk / 2ul) * 10ul) / (u32BusClock)) + 5ul) / 10ul) - 1ul); /* Compute proper divider for USCI_SPI clock */ + } + else {} + + /* Enable USCI_SPI protocol */ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; + uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos; + + /* Data format configuration */ + if(u32DataWidth == 16ul) + { + u32DataWidth = 0ul; + } + else {} + uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk; + uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos); + + /* MSB data format */ + uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk; + + /* Set slave selection signal active low */ + if(u32MasterSlave == USPI_MASTER) + { + uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk; + } + else + { + uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk; + } + + /* Set operating mode and transfer timing */ + uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk); + uspi->PROTCTL |= (u32MasterSlave | u32SPIMode); + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk; + + if(u32BusClock != 0ul) + { + u32UspiClk = (uint32_t)(u32Pclk / ((u32ClkDiv + 1ul) << 1)); + } + else {} + + return u32UspiClk; +} + +/** + * @brief Disable USCI_SPI function mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_Close(USPI_T *uspi) +{ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; +} + +/** + * @brief Clear Rx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearRxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk; +} + +/** + * @brief Clear Tx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearTxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableAutoSS(USPI_T *uspi) +{ + uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SSPinMask This parameter is not used. + * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are: + * - \ref USPI_SS_ACTIVE_HIGH + * - \ref USPI_SS_ACTIVE_LOW + * @return None + */ +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel; + uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk; +} + +/** + * @brief Set the USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if(uspi == USPI0) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2ul) * 10ul) / (u32BusClock)) + 5ul) / 10ul) - 1ul); /* Compute proper divider for USCI_SPI clock */ + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + + return (u32Pclk / ((u32ClkDiv + 1ul) << 1)); +} + +/** + * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Actual USCI_SPI bus clock frequency. + */ +uint32_t USPI_GetBusClock(USPI_T *uspi) +{ + uint32_t u32BusClk; + uint32_t u32ClkDiv; + + u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos; + + if(uspi == USPI0) + { + u32BusClk = (uint32_t)(CLK_GetPCLK0Freq() / ((u32ClkDiv + 1ul) << 1)); + } + + return u32BusClk; +} + +/** + * @brief Enable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + + /* Enable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + + /* Enable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + + /* Enable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + + /* Enable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk; + } + else {} + + /* Enable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk; + } + else {} + + /* Enable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk; + } + else {} + + /* Enable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Disable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + + /* Disable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + + /* Disable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + + /* Disable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + + /* Disable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk; + } + else {} + + /* Disable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk; + } + else {} + + /* Disable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk; + } + else {} + + /* Disable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Get interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return Interrupt flags of selected sources. + */ +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32TmpFlag; + uint32_t u32IntFlag = 0ul; + + /* Check slave selection signal inactive interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk; + if(((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSINAIF_Msk)) + { + u32IntFlag |= USPI_SSINACT_INT_MASK; + } + else {} + + /* Check slave selection signal active interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk; + if(((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) + { + u32IntFlag |= USPI_SSACT_INT_MASK; + } + else {} + + /* Check slave time-out interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk; + if(((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk)) + { + u32IntFlag |= USPI_SLVTO_INT_MASK; + } + else {} + + /* Check slave bit count error interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk; + if(((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk)) + { + u32IntFlag |= USPI_SLVBE_INT_MASK; + } + else {} + + /* Check TX under run interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk; + if(((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk)) + { + u32IntFlag |= USPI_TXUDR_INT_MASK; + } + else {} + + /* Check RX overrun interrupt flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk; + if(((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk)) + { + u32IntFlag |= USPI_RXOV_INT_MASK; + } + else {} + + /* Check TX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk; + if(((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk)) + { + u32IntFlag |= USPI_TXST_INT_MASK; + } + else {} + + /* Check TX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk; + if(((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk)) + { + u32IntFlag |= USPI_TXEND_INT_MASK; + } + else {} + + /* Check RX start interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk; + if(((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk)) + { + u32IntFlag |= USPI_RXST_INT_MASK; + } + else {} + + /* Check RX end interrupt flag */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk; + if(((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk)) + { + u32IntFlag |= USPI_RXEND_INT_MASK; + } + else {} + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + /* Clear slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk; + } + else {} + + /* Clear slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk; + } + else {} + + /* Clear slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk; + } + else {} + + /* Clear slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk; + } + else {} + + /* Clear TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk; + } + else {} + + /* Clear RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk; + } + else {} + + /* Clear TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk; + } + else {} + + /* Clear TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk; + } + else {} + + /* Clear RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk; + } + else {} + + /* Clear RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk; + } + else {} +} + +/** + * @brief Get USCI_SPI status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref USPI_BUSY_MASK + * - \ref USPI_RX_EMPTY_MASK + * - \ref USPI_RX_FULL_MASK + * - \ref USPI_TX_EMPTY_MASK + * - \ref USPI_TX_FULL_MASK + * - \ref USPI_SSLINE_STS_MASK + * @return Flags of selected sources. + */ +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0ul; + uint32_t u32TmpFlag; + + /* Check busy status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk; + if(((u32Mask & USPI_BUSY_MASK) == USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk)) + { + u32Flag |= USPI_BUSY_MASK; + } + else {} + + /* Check RX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk; + if(((u32Mask & USPI_RX_EMPTY_MASK) == USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk)) + { + u32Flag |= USPI_RX_EMPTY_MASK; + } + else {} + + /* Check RX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk; + if(((u32Mask & USPI_RX_FULL_MASK) == USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk)) + { + u32Flag |= USPI_RX_FULL_MASK; + } + else {} + + /* Check TX empty flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk; + if(((u32Mask & USPI_TX_EMPTY_MASK) == USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk)) + { + u32Flag |= USPI_TX_EMPTY_MASK; + } + else {} + + /* Check TX full flag */ + u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk; + if(((u32Mask & USPI_TX_FULL_MASK) == USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk)) + { + u32Flag |= USPI_TX_FULL_MASK; + } + else {} + + /* Check USCI_SPI_SS line status */ + u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk; + if(((u32Mask & USPI_SSLINE_STS_MASK) == USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk)) + { + u32Flag |= USPI_SSLINE_STS_MASK; + } + else {} + + return u32Flag; +} + +/** + * @brief Enable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_EnableWakeup(USPI_T *uspi) +{ + uspi->WKCTL |= USPI_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableWakeup(USPI_T *uspi) +{ + uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk; +} + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_uart.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_uart.c new file mode 100644 index 0000000..ec85505 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_usci_uart.c @@ -0,0 +1,713 @@ +/**************************************************************************//** + * @file usci_uart.c + * @version V3.00 + * @brief M460 series USCI UART (UUART) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + +/** + * @brief Clear USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + + if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk; + } + + if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ + { + uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk); + } + + if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ + { + uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk; + } + + if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk; + } + + if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk; + } + + if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk; + } + + if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk; + } + +} + +/** + * @brief Get USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0ul; + uint32_t u32Tmp1, u32Tmp2; + + /* Check Auto-baud Rate Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_ABR_INT_MASK; + } + + /* Check Receive Line Status Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RLS_INT_MASK; + } + + /* Check Receive Buffer Over-run Error Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK); + u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_BUF_RXOV_INT_MASK; + } + + /* Check Transmit Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXST_INT_MASK; + } + + /* Check Transmit End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXEND_INT_MASK; + } + + /* Check Receive Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXST_INT_MASK; + } + + /* Check Receive End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXEND_INT_MASK; + } + + return u32IntFlag; + +} + + +/** + * @brief Disable USCI_UART function mode + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART function mode. + */ +void UUART_Close(UUART_T* uuart) +{ + uuart->CTL = 0ul; +} + + +/** + * @brief Disable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask) +{ + + /* Disable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk; + } + + /* Disable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Enable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask) +{ + /* Enable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk; + } + + /* Enable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Open and set USCI_UART function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The baud rate of USCI_UART module. + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to enable USCI_UART function and set baud-rate. + */ +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + u32PCLKFreq = CLK_GetPCLK0Freq(); + + /* Calculate baud rate divider */ + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + if(u32Div >= 65536ul) + { + + /* Set the smallest baud rate that USCI_UART can generate */ + u32PDSCnt = 0x4ul; + u32MinDSCnt = 0x10ul; + u32MinClkDiv = 0x400ul; + + } + else + { + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + u32Tmp = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + } + + /* Enable USCI_UART protocol */ + uuart->CTL &= ~UUART_CTL_FUNMODE_Msk; + uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos; + + /* Set USCI_UART line configuration */ + uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk; + uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */ + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv-1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt-1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt-1ul) << UUART_BRGEN_PDSCNT_Pos); + + uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive buffer. + * @param[in] u32ReadBytes The read bytes number of data. + * + * @return Receive byte count + * + * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf. + */ +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */ + } + + return u32Count; + +} + + +/** + * @brief Set USCI_UART line configuration + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The register value of baud rate of USCI_UART module. + * If u32baudrate = 0, USCI_UART baud rate will not change. + * @param[in] u32data_width The data length of USCI_UART module. + * - \ref UUART_WORD_LEN_6 + * - \ref UUART_WORD_LEN_7 + * - \ref UUART_WORD_LEN_8 + * - \ref UUART_WORD_LEN_9 + * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module. + * - \ref UUART_PARITY_NONE + * - \ref UUART_PARITY_ODD + * - \ref UUART_PARITY_EVEN + * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module. + * - \ref UUART_STOP_BIT_1 + * - \ref UUART_STOP_BIT_2 + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to config USCI_UART line setting. + */ +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + u32PCLKFreq = CLK_GetPCLK0Freq(); + + + if(u32baudrate != 0ul) + { + + /* Calculate baud rate divider */ + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div+1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + if(u32Div >= 65536ul) + { + + /* Set the smallest baud rate that USCI_UART can generate */ + u32PDSCnt = 0x4ul; + u32MinDSCnt = 0x10ul; + u32MinClkDiv = 0x400ul; + + } + else + { + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv+1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + } + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos); + } + else + { + u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul; + u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul; + u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul; + } + + /* Set USCI_UART line configuration */ + uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width; + uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk | + UUART_PROTCTL_PARITYEN_Msk)) | u32parity; + uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk ) | u32stop_bits; + + return (u32PCLKFreq/u32PDSCnt/u32MinDSCnt/u32MinClkDiv); +} + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer. + * @param[out] u32WriteBytes The byte number of data. + * + * @return Transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by USCI_UART. + */ +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */ + } + + return u32Count; + +} + + +/** + * @brief Enable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32WakeupMode The wakeup mode of USCI_UART module. + * - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode + * - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode + * + * @return None + * + * @details The function is used to enable Wake-up function of USCI_UART. + */ +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode) +{ + uuart->PROTCTL |= u32WakeupMode; + uuart->WKCTL |= UUART_WKCTL_WKEN_Msk; +} + + +/** + * @brief Disable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable Wake-up function of USCI_UART. + */ +void UUART_DisableWakeup(UUART_T* uuart) +{ + uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk|UUART_PROTCTL_CTSWKEN_Msk); + uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk; +} + +/** + * @brief Enable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to enable USCI_UART auto flow control. + */ +void UUART_EnableFlowCtrl(UUART_T* uuart) +{ + /* Set RTS signal is low level active */ + uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk; + + /* Set CTS signal is low level active */ + uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk; + + /* Enable CTS and RTS auto flow control function */ + uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk; +} + +/** + * @brief Disable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART auto flow control. + */ +void UUART_DisableFlowCtrl(UUART_T* uuart) +{ + /* Disable CTS and RTS auto flow control function */ + uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk|UUART_PROTCTL_CTSAUTOEN_Msk); +} + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_wdt.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_wdt.c new file mode 100644 index 0000000..d70334e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_wdt.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file wdt.c + * @version V3.00 + * @brief Watchdog Timer(WDT) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +int32_t g_WDT_i32ErrCode = 0; /*!< WDT global error code */ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * - \ref WDT_TIMEOUT_2POW20 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + * @note This function sets g_WDT_i32ErrCode to WDT_TIMEOUT_ERR if waiting WDT time-out. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + uint32_t u32TimeOutCount = WDT_TIMEOUT; + + WDT->ALTCTL = u32ResetDelay; + + WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); + + while((WDT->CTL & WDT_CTL_SYNC_Msk) == WDT_CTL_SYNC_Msk) /* Wait enable WDTEN bit completed, it needs 2 * WDT_CLK. */ + { + if(--u32TimeOutCount == 0) + { + g_WDT_i32ErrCode = WDT_TIMEOUT_ERR; /* Time-out error */ + break; + } + } +} + +/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_wwdt.c b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_wwdt.c new file mode 100644 index 0000000..c45f482 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/StdDriver/src/m460_wwdt.c @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V3.00 + * @brief Window Watchdog Timer(WWDT) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note Application can call this function only once after boot up. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == (uint32_t)TRUE) ? WWDT_CTL_INTEN_Msk : 0UL) | + WWDT_CTL_WWDTEN_Msk; +} + +/**@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_ARM_STD/M467.sct b/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_ARM_STD/M467.sct new file mode 100644 index 0000000..0fc73a1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_ARM_STD/M467.sct @@ -0,0 +1,73 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 + +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "../M460_mem.h" + +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define VECTOR_SIZE (4*(16 + 128)) + +#if !defined(NU_HYPERRAM_START) +#define NU_HYPERRAM_START 0x80000000 +#endif + +#if !defined(NU_HYPERRAM_SIZE) +#define NU_HYPERRAM_SIZE 0x800000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *(RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE { + } + + /* VTOR[TBLOFF] alignment requires: + * + * 1. Minumum 32-word + * 2. Rounding up to the next power of two of table size + */ + ER_IRAMVEC AlignExpr(+0, 1024) EMPTY VECTOR_SIZE { ; Reserve for vectors + } + + RW_m_crash_data AlignExpr(+0, 0x100) EMPTY 0x100 { ; Reserve for crash data storage + } + + RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { + } + + NU_HYPERRAM NU_HYPERRAM_START NU_HYPERRAM_SIZE { + *(.text.nu.hyperram) + *(.data.nu.hyperram) + *(.bss.nu.hyperram) + } +} + +ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) +ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE)) diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_GCC_ARM/M467.ld b/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_GCC_ARM/M467.ld new file mode 100644 index 0000000..31aa74c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_GCC_ARM/M467.ld @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Nuvoton M467 GCC linker script file + */ + +#include "../M460_mem.h" + +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#if !defined(NU_HYPERRAM_START) +#define NU_HYPERRAM_START 0x80000000 +#endif + +#if !defined(NU_HYPERRAM_SIZE) +#define NU_HYPERRAM_SIZE 0x800000 +#endif + +M_CRASH_DATA_RAM_SIZE = 0x100; +StackSize = MBED_BOOT_STACK_SIZE; + +MEMORY +{ + VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x00000400 + RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE + HYPERRAM (rwx) : ORIGIN = NU_HYPERRAM_START, LENGTH = NU_HYPERRAM_SIZE +} + +/** + * Must match cmsis_nvic.h + */ +__vector_size = 4 * (16 + 128); + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(8); + } > VECTORS + + .copy.table : ALIGN(4) + { + __copy_table_start__ = .; + + /* .data located at internal SRAM */ + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data)) + + /* .text.nu.hyperram located at HyperRAM */ + LONG (LOADADDR(.text.nu.hyperram)) + LONG (ADDR(.text.nu.hyperram)) + LONG (SIZEOF(.text.nu.hyperram)) + + /* .data.nu.hyperram located at HyperRAM */ + LONG (LOADADDR(.data.nu.hyperram)) + LONG (ADDR(.data.nu.hyperram)) + LONG (SIZEOF(.data.nu.hyperram)) + + __copy_table_end__ = .; + } > FLASH + + .zero.table : ALIGN(4) + { + __zero_table_start__ = .; + + /* .bss located at internal SRAM */ + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)) + + /* .bss.nu.hyperram located at HyperRAM */ + LONG (ADDR(.bss.nu.hyperram)) + LONG (SIZEOF(.bss.nu.hyperram)) + + __zero_table_end__ = .; + } > FLASH + + /* First match used, so place in front of .text */ + .text.nu.hyperram : + { + *(.text.nu.hyperram) + } >HYPERRAM AT>FLASH + + Image$$NU_HYPERRAM$$RO$$Base = ADDR(.text.nu.hyperram); + Image$$NU_HYPERRAM$$RO$$Limit = ADDR(.text.nu.hyperram) + SIZEOF(.text.nu.hyperram); + Image$$NU_HYPERRAM$$RO$$Length = SIZEOF(.text.nu.hyperram); + + .text : + { + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* .stack section doesn't contains any symbols. It is only + * used for linker to reserve space for the main stack section + * WARNING: .stack should come immediately after the last secure memory + * section. This provides stack overflow detection. */ + .stack (NOLOAD): + { + __StackLimit = .; + *(.stack*); + . += StackSize - (. - __StackLimit); + } > RAM_INTERN + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ADDR(.stack) + SIZEOF(.stack); + __StackLimit = ADDR(.stack); + PROVIDE(__stack = __StackTop); + + /* Relocate vector table in SRAM */ + .isr_vector.reloc (NOLOAD) : + { + . = ALIGN(1 << LOG2CEIL(__vector_size)); + PROVIDE(__start_vector_table__ = .); + . += __vector_size; + PROVIDE(__end_vector_table__ = .); + } > RAM_INTERN + + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > RAM_INTERN + + /* First match used, so place in front of .data */ + .data.nu.hyperram : + { + *(.data.nu.hyperram) + } >HYPERRAM AT>FLASH + + Image$$NU_HYPERRAM$$RW$$Base = ADDR(.data.nu.hyperram); + Image$$NU_HYPERRAM$$RW$$Limit = ADDR(.data.nu.hyperram) + SIZEOF(.data.nu.hyperram); + Image$$NU_HYPERRAM$$RW$$Length = SIZEOF(.data.nu.hyperram); + + .data : + { + PROVIDE( __etext = LOADADDR(.data) ); + + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* All data end */ + . = ALIGN(32); + __data_end__ = .; + + } >RAM_INTERN AT>FLASH + + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM_INTERN + + /* First match used, so place in front of .bss */ + /* If a variable defined with __attribute__((section())) keyword the + * variable is treated like an initialized variable. To not waste memory + * NOLOAD attribute used here. The whole section is zero initialized by + * adding section information to .zero.table */ + .bss.nu.hyperram (NOLOAD): + { + *(.bss.nu.hyperram) + } > HYPERRAM + + Image$$NU_HYPERRAM$$ZI$$Base = ADDR(.bss.nu.hyperram); + Image$$NU_HYPERRAM$$ZI$$Limit = ADDR(.bss.nu.hyperram) + SIZEOF(.bss.nu.hyperram); + Image$$NU_HYPERRAM$$ZI$$Length = SIZEOF(.bss.nu.hyperram); + + .bss (NOLOAD): + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM_INTERN + + .heap (NOLOAD): + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + *(.heap*); + . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .); + __HeapLimit = .; + } > RAM_INTERN + PROVIDE(__heap_size = SIZEOF(.heap)); + PROVIDE(__mbed_sbrk_start = ADDR(.heap)); + PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap)); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_IAR/M467.icf b/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_IAR/M467.icf new file mode 100644 index 0000000..3d0dc73 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/TOOLCHAIN_IAR/M467.icf @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ + +include "../M460_mem.icf.h"; + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +if (!isdefinedsymbol(NU_HYPERRAM_START)) { + define symbol NU_HYPERRAM_START = 0x80000000; +} + +if (!isdefinedsymbol(NU_HYPERRAM_SIZE)) { + define symbol NU_HYPERRAM_SIZE = 0x800000; +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START; +define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 0x100 - 1; +define symbol __region_CRASH_DATA_RAM_start__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 0x100; +define symbol __region_CRASH_DATA_RAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1; +define symbol __ICFEDIT_region_HYPERRAM_start__ = NU_HYPERRAM_START; +define symbol __ICFEDIT_region_HYPERRAM_end__ = NU_HYPERRAM_START + NU_HYPERRAM_SIZE - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; +define symbol __ICFEDIT_size_intvec__ = (4 * (16 + 128)); +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; +define region HYPERRAM_region = mem:[from __ICFEDIT_region_HYPERRAM_start__ to __ICFEDIT_region_HYPERRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */ +define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { }; +/* Place .text.nu.hyperram/.data.nu.hyperram/.bss.nu.hyperram together + * + * NOTE: Don't use wildcard like .text.nu.hyperram*. This can collide with .text.nu.hyperram*_init or + * linker-generated initializer for .text.nu.hyperram*. + * NOTE: Per test, 'section .data.nu.hyperram*' will cause linker-generated initializer (const) + * also placed here, resulting in large gap, though it can get fixed with + * 'readwrite section .data.nu.hyperram*'. + * NOTE: With 'initialize by copy { section .text.nu.hyperram }', .text.nu.hyperram is still taken + * as readonly (for initializer), resulting in large gap. + * NOTE: With 'initialize manually { section .text.nu.hyperram }', .text.nu.hyperram becomes readwrite + * .text.nu.hyperram_init is generated by linker to be readonly. We need to do the initialization + * for .text.nu.hyperram manually. + */ +define block NU_HYPERRAM with alignment = 8 { section .text.nu.hyperram, + section .data.nu.hyperram, + section .bss.nu.hyperram }; + +/* Define Crash Data Symbols */ +define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__; +define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__; + +initialize by copy { readwrite }; +initialize manually { section .text.nu.hyperram }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place at start of IRAM_region { block CSTACK }; +place in IRAM_region { block IRAMVEC }; +place in IRAM_region { readwrite }; +place in IRAM_region { block HEAP }; +place in HYPERRAM_region { block NU_HYPERRAM }; diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/cmsis.h b/targets/TARGET_NUVOTON/TARGET_M460/device/cmsis.h new file mode 100644 index 0000000..159f607 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/cmsis.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "M460.h" +#include "cmsis_nvic.h" + +// Support linker-generated symbol as start of relocated vector table. +#if defined(__ARMCC_VERSION) +extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; +#elif defined(__ICCARM__) + +#elif defined(__GNUC__) +extern uint32_t __start_vector_table__; +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/cmsis_nvic.h b/targets/TARGET_NUVOTON/TARGET_M460/device/cmsis_nvic.h new file mode 100644 index 0000000..9a7c832 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/cmsis_nvic.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_USER_IRQ_OFFSET 16 +#define NVIC_USER_IRQ_NUMBER 128 +#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) + +#if defined(__ARMCC_VERSION) +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) +#elif defined(__ICCARM__) +# pragma section = "IRAMVEC" +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC")) +#elif defined(__GNUC__) +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__) +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/startup_M460.c b/targets/TARGET_NUVOTON/TARGET_M460/device/startup_M460.c new file mode 100644 index 0000000..7d95105 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/startup_M460.c @@ -0,0 +1,570 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(__GNUC__) + +/* Get around error: conflicting type qualifiers for '__copy_table_start__' + * + * cmsis_gcc.h also imports the following symbols but with different type qualifier: + * + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * + * Define `__PROGRAM_START` to exclude __cmsis_start() in cmsis_gcc.h. + */ +#define __PROGRAM_START + +#endif + +#include "M460.h" + +/* Suppress warning messages */ +#if defined(__ARMCC_VERSION) +#elif defined(__ICCARM__) +// Suppress warning message Pe1665 +#pragma diag_suppress=Pe1665 +#elif defined(__GNUC__) +#endif + +/* Macro definitions */ +#if defined(__ARMCC_VERSION) +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias(#f))) +#define USED __attribute__ ((used)) + +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); + +#elif defined(__ICCARM__) +#define USED __root +//#define STRINGIFY(x) #x +//#define _STRINGIFY(x) STRINGIFY(x) +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void); \ +_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS))) +#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) +#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS + +#elif defined(__GNUC__) +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias(#f))) +#define USED __attribute__ ((used)) + +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); + +#endif + + +/* Initialize segments */ +#if defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit; +extern void __main(void); +#elif defined(__ICCARM__) +void __iar_program_start(void); +#elif defined(__GNUC__) +extern uint32_t __StackTop; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; + +#if defined(TOOLCHAIN_GCC_ARM) +extern void _start(void); +#else +#error("For GCC toolchain, only support GNU ARM Embedded") +#endif +#endif + +/* Default empty handler */ +void Default_Handler(void); + +/* Reset handler */ +void Reset_Handler(void); +void Reset_Handler_1(void); +void Reset_Handler_2(void); +USED void Reset_Handler_Cascade(void *sp, void *pc); + +/* Cortex-M4 core handlers */ +WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler) +WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler) +WEAK_ALIAS_FUNC(MemManage_Handler, Default_Handler) +WEAK_ALIAS_FUNC(BusFault_Handler , Default_Handler) +WEAK_ALIAS_FUNC(UsageFault_Handler, Default_Handler) +WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler) +WEAK_ALIAS_FUNC(DebugMon_Handler, Default_Handler) +WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler) +WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler) + +/* Peripherals handlers */ +WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection +WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC +WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power down wake up +WEAK_ALIAS_FUNC(RAMPE_IRQHandler, Default_Handler) // 3: RAM parity error +WEAK_ALIAS_FUNC(CKFAIL_IRQHandler, Default_Handler) // 4: Clock detection fail +WEAK_ALIAS_FUNC(ISP_IRQHandler, Default_Handler) // 5: ISP +WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock +WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler) // 7: Tamper detection +WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler) // 8: Watchdog timer +WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler) // 9: Window watchdog timer +WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler) // 10: External Input 0 +WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler) // 11: External Input 1 +WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler) // 12: External Input 2 +WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler) // 13: External Input 3 +WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler) // 14: External Input 4 +WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler) // 15: External Input 5 +WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler) // 16: GPIO Port A +WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler) // 17: GPIO Port B +WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C +WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D +WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E +WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F +WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: QSPI0 +WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 23: SPI0 +WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24: EPWM0 brake +WEAK_ALIAS_FUNC(EPWM0P0_IRQHandler, Default_Handler) // 25: EPWM0 pair 0 +WEAK_ALIAS_FUNC(EPWM0P1_IRQHandler, Default_Handler) // 26: EPWM0 pair 1 +WEAK_ALIAS_FUNC(EPWM0P2_IRQHandler, Default_Handler) // 27: EPWM0 pair 2 +WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28: EPWM1 brake +WEAK_ALIAS_FUNC(EPWM1P0_IRQHandler, Default_Handler) // 29: EPWM1 pair 0 +WEAK_ALIAS_FUNC(EPWM1P1_IRQHandler, Default_Handler) // 30: EPWM1 pair 1 +WEAK_ALIAS_FUNC(EPWM1P2_IRQHandler, Default_Handler) // 31: EPWM1 pair 2 +WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0 +WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1 +WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2 +WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler) // 35: Timer 3 +WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0 +WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1 +WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0 +WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1 +WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA 0 +WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC +WEAK_ALIAS_FUNC(EADC00_IRQHandler, Default_Handler) // 42: EADC0 interrupt source 0 +WEAK_ALIAS_FUNC(EADC01_IRQHandler, Default_Handler) // 43: EADC0 interrupt source 1 +WEAK_ALIAS_FUNC(ACMP01_IRQHandler, Default_Handler) // 44: ACMP0 and ACMP1 +WEAK_ALIAS_FUNC(ACMP23_IRQHandler, Default_Handler) // 45: ACMP2 and ACMP3 +WEAK_ALIAS_FUNC(EADC02_IRQHandler, Default_Handler) // 46: EADC0 interrupt source 2 +WEAK_ALIAS_FUNC(EADC03_IRQHandler, Default_Handler) // 47: EADC0 interrupt source 3 +WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler) // 48: UART2 +WEAK_ALIAS_FUNC(UART3_IRQHandler, Default_Handler) // 49: UART3 +WEAK_ALIAS_FUNC(QSPI1_IRQHandler, Default_Handler) // 50: QSPI1 +WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler) // 51: SPI1 +WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler) // 52: SPI2 +WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler) // 53: USB device +WEAK_ALIAS_FUNC(OHCI_IRQHandler, Default_Handler) // 54: OHCI +WEAK_ALIAS_FUNC(USBOTG_IRQHandler, Default_Handler) // 55: USB OTG +WEAK_ALIAS_FUNC(BMC_IRQHandler, Default_Handler) // 56: BMC +WEAK_ALIAS_FUNC(SPI5_IRQHandler, Default_Handler) // 57: SPI5 +WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler) // 58: SC0 +WEAK_ALIAS_FUNC(SC1_IRQHandler, Default_Handler) // 59: SC1 +WEAK_ALIAS_FUNC(SC2_IRQHandler, Default_Handler) // 60: SC2 +WEAK_ALIAS_FUNC(GPJ_IRQHandler, Default_Handler) // 61: GPIO Port J +WEAK_ALIAS_FUNC(SPI3_IRQHandler, Default_Handler) // 62: SPI3 +WEAK_ALIAS_FUNC(SPI4_IRQHandler, Default_Handler) // 63: SPI4 +WEAK_ALIAS_FUNC(SDH0_IRQHandler, Default_Handler) // 64: SDH0 +WEAK_ALIAS_FUNC(USBD20_IRQHandler, Default_Handler) // 65: USBD20 +WEAK_ALIAS_FUNC(EMAC0_IRQHandler, Default_Handler) // 66: EMAC0 + // 67: +WEAK_ALIAS_FUNC(I2S0_IRQHandler, Default_Handler) // 68: I2S0 +WEAK_ALIAS_FUNC(I2S1_IRQHandler, Default_Handler) // 69: I2S1 +WEAK_ALIAS_FUNC(SPI6_IRQHandler, Default_Handler) // 70: SPI6 +WEAK_ALIAS_FUNC(CRPT_IRQHandler, Default_Handler) // 71: CRYPTO +WEAK_ALIAS_FUNC(GPG_IRQHandler, Default_Handler) // 72: GPIO Port G +WEAK_ALIAS_FUNC(EINT6_IRQHandler, Default_Handler) // 73: External Input 6 +WEAK_ALIAS_FUNC(UART4_IRQHandler, Default_Handler) // 74: UART4 +WEAK_ALIAS_FUNC(UART5_IRQHandler, Default_Handler) // 75: UART5 +WEAK_ALIAS_FUNC(USCI0_IRQHandler, Default_Handler) // 76: USCI0 +WEAK_ALIAS_FUNC(SPI7_IRQHandler, Default_Handler) // 77: SPI7 +WEAK_ALIAS_FUNC(BPWM0_IRQHandler, Default_Handler) // 78: BPWM0 +WEAK_ALIAS_FUNC(BPWM1_IRQHandler, Default_Handler) // 79: BPWM1 +WEAK_ALIAS_FUNC(SPIM_IRQHandler, Default_Handler) // 80: SPIM +WEAK_ALIAS_FUNC(CCAP_IRQHandler, Default_Handler) // 81: CCAP +WEAK_ALIAS_FUNC(I2C2_IRQHandler, Default_Handler) // 82: I2C2 +WEAK_ALIAS_FUNC(I2C3_IRQHandler, Default_Handler) // 83: I2C3 +WEAK_ALIAS_FUNC(EQEI0_IRQHandler, Default_Handler) // 84: EQEI0 +WEAK_ALIAS_FUNC(EQEI1_IRQHandler, Default_Handler) // 85: EQEI1 +WEAK_ALIAS_FUNC(ECAP0_IRQHandler, Default_Handler) // 86: ECAP0 +WEAK_ALIAS_FUNC(ECAP1_IRQHandler, Default_Handler) // 87: ECAP1 +WEAK_ALIAS_FUNC(GPH_IRQHandler, Default_Handler) // 88: GPIO Port H +WEAK_ALIAS_FUNC(EINT7_IRQHandler, Default_Handler) // 89: External Input 7 +WEAK_ALIAS_FUNC(SDH1_IRQHandler, Default_Handler) // 90: SDH1 +WEAK_ALIAS_FUNC(PSIO_IRQHandler, Default_Handler) // 91: PSIO +WEAK_ALIAS_FUNC(EHCI_IRQHandler, Default_Handler) // 92: EHCI +WEAK_ALIAS_FUNC(USBOTG20_IRQHandler,Default_Handler) // 93: HSOTG +WEAK_ALIAS_FUNC(ECAP2_IRQHandler, Default_Handler) // 94: ECAP2 +WEAK_ALIAS_FUNC(ECAP3_IRQHandler, Default_Handler) // 95: ECAP3 +WEAK_ALIAS_FUNC(KPI_IRQHandler, Default_Handler) // 96: KPI +WEAK_ALIAS_FUNC(HBI_IRQHandler, Default_Handler) // 97: HBI +WEAK_ALIAS_FUNC(PDMA1_IRQHandler, Default_Handler) // 98: Peripheral DMA 1 +WEAK_ALIAS_FUNC(UART8_IRQHandler, Default_Handler) // 99: UART8 +WEAK_ALIAS_FUNC(UART9_IRQHandler, Default_Handler) // 100: UART9 +WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101: TRNG +WEAK_ALIAS_FUNC(UART6_IRQHandler, Default_Handler) // 102: UART6 +WEAK_ALIAS_FUNC(UART7_IRQHandler, Default_Handler) // 103: UART7 +WEAK_ALIAS_FUNC(EADC10_IRQHandler, Default_Handler) // 104: EADC1 interrupt source 0 +WEAK_ALIAS_FUNC(EADC11_IRQHandler, Default_Handler) // 105: EADC1 interrupt source 1 +WEAK_ALIAS_FUNC(EADC12_IRQHandler, Default_Handler) // 106: EADC1 interrupt source 2 +WEAK_ALIAS_FUNC(EADC13_IRQHandler, Default_Handler) // 107: EADC1 interrupt source 3 +WEAK_ALIAS_FUNC(SPI8_IRQHandler, Default_Handler) // 108: SPI8 +WEAK_ALIAS_FUNC(KS_IRQHandler, Default_Handler) // 109: Key Store +WEAK_ALIAS_FUNC(GPI_IRQHandler, Default_Handler) // 110: GPIO Port I +WEAK_ALIAS_FUNC(SPI9_IRQHandler, Default_Handler) // 111: SPI9 +WEAK_ALIAS_FUNC(CANFD00_IRQHandler, Default_Handler) // 112: CANFD0 interrupt source 0 +WEAK_ALIAS_FUNC(CANFD01_IRQHandler, Default_Handler) // 113: CANFD0 interrupt source 1 +WEAK_ALIAS_FUNC(CANFD10_IRQHandler, Default_Handler) // 114: CANFD1 interrupt source 0 +WEAK_ALIAS_FUNC(CANFD11_IRQHandler, Default_Handler) // 115: CANFD1 interrupt source 1 +WEAK_ALIAS_FUNC(EQEI2_IRQHandler, Default_Handler) // 116: EQEI2 +WEAK_ALIAS_FUNC(EQEI3_IRQHandler, Default_Handler) // 117: EQEI3 +WEAK_ALIAS_FUNC(I2C4_IRQHandler, Default_Handler) // 118: I2C4 +WEAK_ALIAS_FUNC(SPI10_IRQHandler, Default_Handler) // 119: SPI10 +WEAK_ALIAS_FUNC(CANFD20_IRQHandler, Default_Handler) // 120: CANFD2 interrupt source 0 +WEAK_ALIAS_FUNC(CANFD21_IRQHandler, Default_Handler) // 121: CANFD2 interrupt source 1 +WEAK_ALIAS_FUNC(CANFD30_IRQHandler, Default_Handler) // 122: CANFD3 interrupt source 0 +WEAK_ALIAS_FUNC(CANFD31_IRQHandler, Default_Handler) // 123: CANFD3 interrupt source 1 +WEAK_ALIAS_FUNC(EADC20_IRQHandler, Default_Handler) // 124: EADC2 interrupt source 0 +WEAK_ALIAS_FUNC(EADC21_IRQHandler, Default_Handler) // 125: EADC2 interrupt source 1 +WEAK_ALIAS_FUNC(EADC22_IRQHandler, Default_Handler) // 126: EADC2 interrupt source 2 +WEAK_ALIAS_FUNC(EADC23_IRQHandler, Default_Handler) // 127: EADC2 interrupt source 3 + + +/* Vector table */ +#if defined(__ARMCC_VERSION) +__attribute__ ((section("RESET"), used)) +const uint32_t __vector_handlers[] = { +#elif defined(__ICCARM__) +extern uint32_t CSTACK$$Limit; +const uint32_t __vector_table[] @ ".intvec" = { +#elif defined(__GNUC__) +__attribute__ ((section(".vector_table"))) +const uint32_t __vector_handlers[] = { +#endif + + /* Configure Initial Stack Pointer, using linker-generated symbols */ +#if defined(__ARMCC_VERSION) + (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit, +#elif defined(__ICCARM__) + (uint32_t) &CSTACK$$Limit, +#elif defined(__GNUC__) + (uint32_t) &__StackTop, +#endif + + (uint32_t) Reset_Handler, // Reset Handler + (uint32_t) NMI_Handler, // NMI Handler + (uint32_t) HardFault_Handler, // Hard Fault Handler + (uint32_t) MemManage_Handler, // MPU Fault Handler + (uint32_t) BusFault_Handler, // Bus Fault Handler + (uint32_t) UsageFault_Handler, // Usage Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + (uint32_t) SVC_Handler, // SVCall Handler + (uint32_t) DebugMon_Handler, // Debug Monitor Handler + 0, // Reserved + (uint32_t) PendSV_Handler, // PendSV Handler + (uint32_t) SysTick_Handler, // SysTick Handler + + /* External Interrupts */ + (uint32_t) BOD_IRQHandler, // 0: Brown Out detection + (uint32_t) IRC_IRQHandler, // 1: Internal RC + (uint32_t) PWRWU_IRQHandler, // 2: Power down wake up + (uint32_t) RAMPE_IRQHandler, // 3: RAM parity error + (uint32_t) CKFAIL_IRQHandler, // 4: Clock detection fail + (uint32_t) ISP_IRQHandler, // 5: ISP + (uint32_t) RTC_IRQHandler, // 6: Real Time Clock + (uint32_t) TAMPER_IRQHandler, // 7: Tamper detection + (uint32_t) WDT_IRQHandler, // 8: Watchdog timer + (uint32_t) WWDT_IRQHandler, // 9: Window watchdog timer + (uint32_t) EINT0_IRQHandler, // 10: External Input 0 + (uint32_t) EINT1_IRQHandler, // 11: External Input 1 + (uint32_t) EINT2_IRQHandler, // 12: External Input 2 + (uint32_t) EINT3_IRQHandler, // 13: External Input 3 + (uint32_t) EINT4_IRQHandler, // 14: External Input 4 + (uint32_t) EINT5_IRQHandler, // 15: External Input 5 + (uint32_t) GPA_IRQHandler, // 16: GPIO Port A + (uint32_t) GPB_IRQHandler, // 17: GPIO Port B + (uint32_t) GPC_IRQHandler, // 18: GPIO Port C + (uint32_t) GPD_IRQHandler, // 19: GPIO Port D + (uint32_t) GPE_IRQHandler, // 20: GPIO Port E + (uint32_t) GPF_IRQHandler, // 21: GPIO Port F + (uint32_t) QSPI0_IRQHandler, // 22: QSPI0 + (uint32_t) SPI0_IRQHandler, // 23: SPI0 + (uint32_t) BRAKE0_IRQHandler, // 24: EPWM0 brake + (uint32_t) EPWM0P0_IRQHandler, // 25: EPWM0 pair 0 + (uint32_t) EPWM0P1_IRQHandler, // 26: EPWM0 pair 1 + (uint32_t) EPWM0P2_IRQHandler, // 27: EPWM0 pair 2 + (uint32_t) BRAKE1_IRQHandler, // 28: EPWM1 brake + (uint32_t) EPWM1P0_IRQHandler, // 29: EPWM1 pair 0 + (uint32_t) EPWM1P1_IRQHandler, // 30: EPWM1 pair 1 + (uint32_t) EPWM1P2_IRQHandler, // 31: EPWM1 pair 2 + (uint32_t) TMR0_IRQHandler, // 32: Timer 0 + (uint32_t) TMR1_IRQHandler, // 33: Timer 1 + (uint32_t) TMR2_IRQHandler, // 34: Timer 2 + (uint32_t) TMR3_IRQHandler, // 35: Timer 3 + (uint32_t) UART0_IRQHandler, // 36: UART0 + (uint32_t) UART1_IRQHandler, // 37: UART1 + (uint32_t) I2C0_IRQHandler, // 38: I2C0 + (uint32_t) I2C1_IRQHandler, // 39: I2C1 + (uint32_t) PDMA0_IRQHandler, // 40: Peripheral DMA 0 + (uint32_t) DAC_IRQHandler, // 41: DAC + (uint32_t) EADC00_IRQHandler, // 42: EADC0 interrupt source 0 + (uint32_t) EADC01_IRQHandler, // 43: EADC0 interrupt source 1 + (uint32_t) ACMP01_IRQHandler, // 44: ACMP0 and ACMP1 + (uint32_t) ACMP23_IRQHandler, // 45: ACMP2 and ACMP3 + (uint32_t) EADC02_IRQHandler, // 46: EADC0 interrupt source 2 + (uint32_t) EADC03_IRQHandler, // 47: EADC0 interrupt source 3 + (uint32_t) UART2_IRQHandler, // 48: UART2 + (uint32_t) UART3_IRQHandler, // 49: UART3 + (uint32_t) QSPI1_IRQHandler, // 50: QSPI1 + (uint32_t) SPI1_IRQHandler, // 51: SPI1 + (uint32_t) SPI2_IRQHandler, // 52: SPI2 + (uint32_t) USBD_IRQHandler, // 53: USB device + (uint32_t) OHCI_IRQHandler, // 54: OHCI + (uint32_t) USBOTG_IRQHandler, // 55: USB OTG + (uint32_t) BMC_IRQHandler, // 56: BMC + (uint32_t) SPI5_IRQHandler, // 57: SPI5 + (uint32_t) SC0_IRQHandler, // 58: SC0 + (uint32_t) SC1_IRQHandler, // 59: SC1 + (uint32_t) SC2_IRQHandler, // 60: SC2 + (uint32_t) GPJ_IRQHandler, // 61: GPIO Port J + (uint32_t) SPI3_IRQHandler, // 62: SPI3 + (uint32_t) SPI4_IRQHandler, // 63: SPI4 + (uint32_t) SDH0_IRQHandler, // 64: SDH0 + (uint32_t) USBD20_IRQHandler, // 65: USBD20 + (uint32_t) EMAC0_IRQHandler, // 66: EMAC0 + (uint32_t) Default_Handler, // 67: + (uint32_t) I2S0_IRQHandler, // 68: I2S0 + (uint32_t) I2S1_IRQHandler, // 69: I2S1 + (uint32_t) SPI6_IRQHandler, // 70: SPI6 + (uint32_t) CRPT_IRQHandler, // 71: CRYPTO + (uint32_t) GPG_IRQHandler, // 72: GPIO Port G + (uint32_t) EINT6_IRQHandler, // 73: External Input 6 + (uint32_t) UART4_IRQHandler, // 74: UART4 + (uint32_t) UART5_IRQHandler, // 75: UART5 + (uint32_t) USCI0_IRQHandler, // 76: USCI0 + (uint32_t) SPI7_IRQHandler, // 77: SPI7 + (uint32_t) BPWM0_IRQHandler, // 78: BPWM0 + (uint32_t) BPWM1_IRQHandler, // 79: BPWM1 + (uint32_t) SPIM_IRQHandler, // 80: SPIM + (uint32_t) CCAP_IRQHandler, // 81: CCAP + (uint32_t) I2C2_IRQHandler, // 82: I2C2 + (uint32_t) I2C3_IRQHandler, // 83: I2C3 + (uint32_t) EQEI0_IRQHandler, // 84: EQEI0 + (uint32_t) EQEI1_IRQHandler, // 85: EQEI1 + (uint32_t) ECAP0_IRQHandler, // 86: ECAP0 + (uint32_t) ECAP1_IRQHandler, // 87: ECAP1 + (uint32_t) GPH_IRQHandler, // 88: GPIO Port H + (uint32_t) EINT7_IRQHandler, // 89: External Input 7 + (uint32_t) SDH1_IRQHandler, // 90: SDH1 + (uint32_t) PSIO_IRQHandler, // 91: PSIO + (uint32_t) EHCI_IRQHandler, // 92: EHCI + (uint32_t) USBOTG20_IRQHandler, // 93: HSOTG + (uint32_t) ECAP2_IRQHandler, // 94: ECAP2 + (uint32_t) ECAP3_IRQHandler, // 95: ECAP3 + (uint32_t) KPI_IRQHandler, // 96: KPI + (uint32_t) HBI_IRQHandler, // 97: HBI + (uint32_t) PDMA1_IRQHandler, // 98: Peripheral DMA 1 + (uint32_t) UART8_IRQHandler, // 99: UART8 + (uint32_t) UART9_IRQHandler, // 100: UART9 + (uint32_t) TRNG_IRQHandler, // 101: TRNG + (uint32_t) UART6_IRQHandler, // 102: UART6 + (uint32_t) UART7_IRQHandler, // 103: UART7 + (uint32_t) EADC10_IRQHandler, // 104: EADC1 interrupt source 0 + (uint32_t) EADC11_IRQHandler, // 105: EADC1 interrupt source 1 + (uint32_t) EADC12_IRQHandler, // 106: EADC1 interrupt source 2 + (uint32_t) EADC13_IRQHandler, // 107: EADC1 interrupt source 3 + (uint32_t) SPI8_IRQHandler, // 108: SPI8 + (uint32_t) KS_IRQHandler, // 109: Key Store + (uint32_t) GPI_IRQHandler, // 110: GPIO Port I + (uint32_t) SPI9_IRQHandler, // 111: SPI9 + (uint32_t) CANFD00_IRQHandler, // 112: CANFD0 interrupt source 0 + (uint32_t) CANFD01_IRQHandler, // 113: CANFD0 interrupt source 1 + (uint32_t) CANFD10_IRQHandler, // 114: CANFD1 interrupt source 0 + (uint32_t) CANFD11_IRQHandler, // 115: CANFD1 interrupt source 1 + (uint32_t) EQEI2_IRQHandler, // 116: EQEI2 + (uint32_t) EQEI3_IRQHandler, // 117: EQEI3 + (uint32_t) I2C4_IRQHandler, // 118: I2C4 + (uint32_t) SPI10_IRQHandler, // 119: SPI10 + (uint32_t) CANFD20_IRQHandler, // 120: CANFD2 interrupt source 0 + (uint32_t) CANFD21_IRQHandler, // 121: CANFD2 interrupt source 1 + (uint32_t) CANFD30_IRQHandler, // 122: CANFD3 interrupt source 0 + (uint32_t) CANFD31_IRQHandler, // 123: CANFD3 interrupt source 1 + (uint32_t) EADC20_IRQHandler, // 124: EADC2 interrupt source 0 + (uint32_t) EADC21_IRQHandler, // 125: EADC2 interrupt source 1 + (uint32_t) EADC22_IRQHandler, // 126: EADC2 interrupt source 2 + (uint32_t) EADC23_IRQHandler, // 127: EADC2 interrupt source 3 +}; + +/* + * Reset_Handler: + * Divert one small memory block for Initial Stack + * Continue Initial Stack for Reset_Handler_1 + * Jump to Reset_Handler_1 + * + * Reset_Handler_1 + * Enable other SRAM modules. From now on, these memory modules could be used for Initial Stack, depending on linker. + * - SRAM bank1/2 + * - EBI SRAM (like NUC472) + * - SPIM CCM (like M487) + * Configure Initial Stack, using linker-generated symbols for Reset_Handler_2 + * Jump to Reset_Handler_2 + * + * Reset_Handler_2 + * C/C++ runtime initialization + */ + +#if defined (__GNUC__) || defined (__ICCARM__) + +__attribute__((naked)) void Reset_Handler(void) +{ + __asm("ldr sp, =0x20000200 \n"); + __asm("mov r0, sp \n"); + __asm("ldr r1, =Reset_Handler_1 \n"); + __asm("b Reset_Handler_Cascade \n"); +} + +void Reset_Handler_Cascade(void *sp, void *pc) +{ + __asm volatile ( + "mov sp, %0 \n" + "bx %1 \n" + : /* output operands */ + : "l"(sp), "l"(pc) /* input operands */ + : "cc" /* list of clobbered registers */ + ); +} + +#else + +#error "Unsupported toolchain" + +#endif + +void Reset_Handler_1(void) +{ + /* Disable register write-protection function */ + SYS_UnlockReg(); + + /** + * NOTE 1: Some register accesses require unlock. + * NOTE 2: SystemInit() must be called at the very start to initialize other SRAM modules. + */ + SystemInit(); + + /* Enable register write-protection function */ + SYS_LockReg(); + +#if defined(__ARMCC_VERSION) + Reset_Handler_Cascade((void *) &Image$$ARM_LIB_STACK$$ZI$$Limit, (void *) Reset_Handler_2); +#elif defined(__ICCARM__) + Reset_Handler_Cascade((void *) &CSTACK$$Limit, (void *) Reset_Handler_2); +#elif defined(__GNUC__) + Reset_Handler_Cascade((void *) &__StackTop, (void *) Reset_Handler_2); +#endif +} + +void Reset_Handler_2(void) +{ +#if defined(__ARMCC_VERSION) + __main(); + +#elif defined(__ICCARM__) + /* With 'initialize manually { section .text.nu.hyperram }' in .icf, do the + * initialization for .text.nu.hyperram manually. + * + * NOTE: C runtime not initialized yet, don't invoke memcpy() for safe. */ + { + /* BSP not defined yet, define it */ + #pragma section=".text.nu.hyperram" + #pragma section=".text.nu.hyperram_init" + uint32_t *src_ind = (uint32_t *) __section_begin(".text.nu.hyperram_init"); + uint32_t *src_end = (uint32_t *) __section_end(".text.nu.hyperram_init"); + uint32_t *dst_ind = (uint32_t *) __section_begin(".text.nu.hyperram"); + if (src_ind != dst_ind) { + for (; src_ind < src_end;) { + *dst_ind ++ = *src_ind ++; + } + } + } + + __iar_program_start(); + +#elif defined(__GNUC__) + /* Move (multiple) .data section(s) from ROM to RAM */ + { + /* Struct of copy table entry which must match linker script */ + typedef struct copy_table_entry_ { + uint32_t src; // Address to copy from + uint32_t dst; // Address to copy to + uint32_t size; // Copy size in bytes + } copy_table_entry; + + copy_table_entry *copy_table_ind = (copy_table_entry *) &__copy_table_start__; + copy_table_entry *copy_table_end = (copy_table_entry *) &__copy_table_end__; + + for (; copy_table_ind != copy_table_end; copy_table_ind ++) { + uint32_t *src_ind = (uint32_t *) copy_table_ind->src; + uint32_t *src_end = (uint32_t *) (copy_table_ind->src + copy_table_ind->size); + uint32_t *dst_ind = (uint32_t *) copy_table_ind->dst; + if (src_ind != dst_ind) { + for (; src_ind < src_end;) { + *dst_ind ++ = *src_ind ++; + } + } + } + } + + /* Initialize (multiple) .bss sections to zero */ + { + /* Struct of zero table entry which must match linker script */ + typedef struct zero_table_entry_ { + uint32_t start; // Address to start zero'ing + uint32_t size; // Zero size in bytes + } zero_table_entry; + + zero_table_entry *zero_table_ind = (zero_table_entry *) &__zero_table_start__; + zero_table_entry *zero_table_end = (zero_table_entry *) &__zero_table_end__; + + for (; zero_table_ind != zero_table_end; zero_table_ind ++) { + uint32_t *dst_ind = (uint32_t *) zero_table_ind->start; + uint32_t *dst_end = (uint32_t *) (zero_table_ind->start + zero_table_ind->size); + + for (; dst_ind < dst_end; ) { + *dst_ind ++ = 0; + } + } + } + + _start(); + +#endif + + /* Infinite loop */ + while (1); +} + + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/system_M460.c b/targets/TARGET_NUVOTON/TARGET_M460/device/system_M460.c new file mode 100644 index 0000000..4c5b5fa --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/system_M460.c @@ -0,0 +1,190 @@ +/**************************************************************************//** + * @file system_M460.c + * @version V3.000 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M460 + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ +uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */ +uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */ +uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC}; + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t u32Freq, u32ClkSrc; + uint32_t u32HclkDiv; + + /* Update PLL Clock */ + PllClock = CLK_GetPLLClockFreq(); + + u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; + + if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL) + { + /* Use PLL clock */ + u32Freq = PllClock; + } + else + { + /* Use the clock sources directly */ + u32Freq = gau32ClkSrcTbl[u32ClkSrc]; + } + + u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + + //if(SystemCoreClock == 0) + // __BKPT(0); + + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; +} + + +/** + * @brief Initialize the System + * + * @param none + * @return none + */ +void SystemInit (void) +{ + + /* Add your system initialize code here. + Do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Set HCLK switch to be reset by HRESET reset sources */ + outpw(0x40000014, inpw(0x40000014)|BIT7); + +#if MBED_CONF_TARGET_HXT_PRESENT + /* Set HXT crystal as INV type */ + CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk; +#endif + + /* Lock protected registers */ + SYS_LockReg(); + +#if defined(MBED_CONF_TARGET_HBI_ENABLE) && MBED_CONF_TARGET_HBI_ENABLE + /* Initialize HBI for HyperRAM */ + void nu_hbi_init(void); + nu_hbi_init(); +#else + int32_t nu_hyperram_used(void); + if (nu_hyperram_used()) { + /* TODO: Report error: HyperRAM used but HBI not enabled */ + } +#endif +} + +/* Detect whether or not HyperRAM is used + * + * NOTE: For Arm Compiler, Image$$region_name doesn't include ZI. To avoid + * confusion, use Image$$region_name$$RO/Image$$region_name$$RW/ + * Image$$region_name$$ZI instead. + * NOTE: Compiler e.g. Arm Compiler can optimize assuming (®ion_name$$Limit != ®ion_name$$Base) being true. + * Change to (®ion_name$$Limit - ®ion_name$$Base) instead. + * NOTE: Compiler e.g. GCC can optimize assuming ®ion_name$$Length being non-zero. + * Change to (®ion_name$$Limit - ®ion_name$$Base) instead. + */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t Image$$NU_HYPERRAM$$RO$$Base; +extern uint32_t Image$$NU_HYPERRAM$$RO$$Limit; +extern uint32_t Image$$NU_HYPERRAM$$RW$$Base; +extern uint32_t Image$$NU_HYPERRAM$$RW$$Limit; +extern uint32_t Image$$NU_HYPERRAM$$ZI$$Base; +extern uint32_t Image$$NU_HYPERRAM$$ZI$$Limit; +#define NU_HYPERRAM_USED \ + ((((uint32_t) &Image$$NU_HYPERRAM$$RO$$Limit) - ((uint32_t) &Image$$NU_HYPERRAM$$RO$$Base)) || \ + (((uint32_t) &Image$$NU_HYPERRAM$$RW$$Limit) - ((uint32_t) &Image$$NU_HYPERRAM$$RW$$Base)) || \ + (((uint32_t) &Image$$NU_HYPERRAM$$ZI$$Limit) - ((uint32_t) &Image$$NU_HYPERRAM$$ZI$$Base))) +#elif defined(__ICCARM__) +extern uint32_t NU_HYPERRAM$$Base; +extern uint32_t NU_HYPERRAM$$Limit; +#define NU_HYPERRAM_USED \ + (!!(((uint32_t) &NU_HYPERRAM$$Limit) - ((uint32_t) &NU_HYPERRAM$$Base))) +#endif + +int32_t nu_hyperram_used(void) +{ + return NU_HYPERRAM_USED; +} + +#if defined(MBED_CONF_TARGET_HBI_ENABLE) && MBED_CONF_TARGET_HBI_ENABLE + +/* Simple array size macro without type check */ +#define _NU_ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) + +void nu_hbi_init(void) +{ + /* Configurable HBI multi-function pin + * + * NOTE: C runtime not initialized yet, locate at ROM region. + */ + static const uint32_t hbi_mfp_reg_arr[] = { + MBED_CONF_TARGET_HBI_MFP_REG_LIST + }; + static const uint32_t hbi_mfp_reg_msk_arr[] = { + MBED_CONF_TARGET_HBI_MFP_REG_MSK_LIST + }; + static const uint32_t hbi_mfp_reg_val_arr[] = { + MBED_CONF_TARGET_HBI_MFP_REG_VAL_LIST + }; + + /* Make sure consistent HBI multi-function pin configurations */ + _Static_assert(_NU_ARRAY_SIZE(hbi_mfp_reg_arr) == _NU_ARRAY_SIZE(hbi_mfp_reg_msk_arr), + "Inconsistent HBI MFP register and mask list length"); + _Static_assert(_NU_ARRAY_SIZE(hbi_mfp_reg_arr) == _NU_ARRAY_SIZE(hbi_mfp_reg_val_arr), + "Inconsistent HBI MFP register and value list length"); + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Initialize HBI module */ + SYS_ResetModule(HBI_RST); + + /* Enable HBI module clock */ + CLK_EnableModuleClock(HBI_MODULE); + + /* Set HBI multi-function pins */ + const uint32_t *reg_pos = hbi_mfp_reg_arr; + const uint32_t *reg_end = hbi_mfp_reg_arr + _NU_ARRAY_SIZE(hbi_mfp_reg_arr); + const uint32_t *msk_pos = hbi_mfp_reg_msk_arr; + const uint32_t *val_pos = hbi_mfp_reg_val_arr; + for (; reg_pos != reg_end; reg_pos ++, msk_pos ++, val_pos ++) { + M32(*reg_pos) = (M32(*reg_pos) & ~*msk_pos) | *val_pos; + } + + /* Lock protected registers */ + SYS_LockReg(); +} + +#endif /* #if defined(MBED_CONF_TARGET_HBI_ENABLE) && MBED_CONF_TARGET_HBI_ENABLE */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/device/system_M460.h b/targets/TARGET_NUVOTON/TARGET_M460/device/system_M460.h new file mode 100644 index 0000000..97a3460 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/device/system_M460.h @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file system_M460.h + * @version V3.00 + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M460 + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#ifndef __SYSTEM_M460_H__ +#define __SYSTEM_M460_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#ifndef __HSI +#define __HSI (12000000UL) /*!< PLL default output is 50MHz */ +#endif + +#ifndef __HXT +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#endif + +#ifndef __LXT +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#endif + +#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */ +#define __HIRC48M (48000000UL) /*!< Internal 48M RC Oscillator Frequency */ +#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */ +#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */ + + +#define __SYSTEM_CLOCK (1UL*__HXT) + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the micro controller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_M460_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M460/dma.h b/targets/TARGET_NUVOTON/TARGET_M460/dma.h new file mode 100644 index 0000000..0994231 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/dma.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DMA_H +#define MBED_DMA_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DMA_CAP_NONE (0 << 0) + +#define DMA_EVENT_ABORT (1 << 0) +#define DMA_EVENT_TRANSFER_DONE (1 << 1) +#define DMA_EVENT_TIMEOUT (1 << 2) +#define DMA_EVENT_ALL (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT) +#define DMA_EVENT_MASK DMA_EVENT_ALL + +void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event); +PDMA_T *dma_modbase(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M460/dma_api.c new file mode 100644 index 0000000..b9808c5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/dma_api.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dma_api.h" +#include "string.h" +#include "cmsis.h" +#include "mbed_assert.h" +#include "PeripheralNames.h" +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include "dma.h" + +/* Specify maximum channels of PDMA */ +#define NU_PDMA_CH_MAX PDMA_CH_MAX +/* Specify first channel number of PDMA */ +#define NU_PDMA_CH_Pos 0 +#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos) +/* Bitmap of all PDMA_INTSTS_REQTOFx_Msk */ +#define NU_PDMA_INTSTS_REQTOF_ALL_Msk \ + (PDMA_INTSTS_REQTOF0_Msk | PDMA_INTSTS_REQTOF1_Msk | \ + PDMA_INTSTS_REQTOF2_Msk | PDMA_INTSTS_REQTOF3_Msk | \ + PDMA_INTSTS_REQTOF4_Msk | PDMA_INTSTS_REQTOF5_Msk | \ + PDMA_INTSTS_REQTOF6_Msk | PDMA_INTSTS_REQTOF7_Msk | \ + PDMA_INTSTS_REQTOF8_Msk | PDMA_INTSTS_REQTOF9_Msk | \ + PDMA_INTSTS_REQTOF10_Msk | PDMA_INTSTS_REQTOF11_Msk | \ + PDMA_INTSTS_REQTOF12_Msk | PDMA_INTSTS_REQTOF13_Msk | \ + PDMA_INTSTS_REQTOF14_Msk | PDMA_INTSTS_REQTOF15_Msk) + +struct nu_dma_chn_s { + void (*handler)(uint32_t, uint32_t); + uint32_t id; + uint32_t event; +}; + +static int dma_inited = 0; +static uint32_t dma_chn_mask = 0; +static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX]; + +static void pdma0_vec(void); +static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA0_MODULE, 0, 0, PDMA0_RST, PDMA0_IRQn, (void *) pdma0_vec}; + + +void dma_init(void) +{ + if (dma_inited) { + return; + } + + dma_inited = 1; + dma_chn_mask = ~NU_PDMA_CH_Msk; + memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); + + // Enable IP clock + CLK_EnableModuleClock(dma_modinit.clkidx); + + // Reset this module + SYS_ResetModule(dma_modinit.rsetidx); + + PDMA_Open(dma_modbase(), 0); + + NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); + NVIC_EnableIRQ(dma_modinit.irq_n); +} + +int dma_channel_allocate(uint32_t capabilities) +{ + if (! dma_inited) { + dma_init(); + } + + int i = nu_cto(dma_chn_mask); + if (i != 32) { + dma_chn_mask |= 1 << i; + memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s)); + return i; + } + + // No channel available + return DMA_ERROR_OUT_OF_CHANNELS; +} + +int dma_channel_free(int channelid) +{ + if (channelid != DMA_ERROR_OUT_OF_CHANNELS) { + dma_chn_mask &= ~(1 << channelid); + } + + return 0; +} + +void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event) +{ + MBED_ASSERT(dma_chn_mask & (1 << channelid)); + + dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event; + + // Set interrupt vector if someone has removed it. + NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); + NVIC_EnableIRQ(dma_modinit.irq_n); +} + +PDMA_T *dma_modbase(void) +{ + return (PDMA_T *) NU_MODBASE(dma_modinit.modname); +} + +static void pdma0_vec(void) +{ + uint32_t intsts = PDMA_GET_INT_STATUS(dma_modbase()); + + // Abort + if (intsts & PDMA_INTSTS_ABTIF_Msk) { + uint32_t abtsts = PDMA_GET_ABORT_STS(dma_modbase()); + // Clear all Abort flags + PDMA_CLR_ABORT_FLAG(dma_modbase(), abtsts); + + while (abtsts) { + int chn_id = nu_ctz(abtsts) - PDMA_ABTSTS_ABTIF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT); + } + } + abtsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_ABTSTS_ABTIF0_Pos)); + } + } + + // Transfer done + if (intsts & PDMA_INTSTS_TDIF_Msk) { + uint32_t tdsts = PDMA_GET_TD_STS(dma_modbase()); + // Clear all transfer done flags + PDMA_CLR_TD_FLAG(dma_modbase(), tdsts); + + while (tdsts) { + int chn_id = nu_ctz(tdsts) - PDMA_TDSTS_TDIF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE); + } + } + tdsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_TDSTS_TDIF0_Pos)); + } + } + + // Timeout + uint32_t reqto = intsts & NU_PDMA_INTSTS_REQTOF_ALL_Msk; + if (reqto) { + // Clear all Timeout flags + dma_modbase()->INTSTS = reqto; + + while (reqto) { + int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT); + } + } + reqto &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_INTSTS_REQTOF0_Pos)); + } + } +} diff --git a/targets/TARGET_NUVOTON/TARGET_M460/flash_api.c b/targets/TARGET_NUVOTON/TARGET_M460/flash_api.c new file mode 100644 index 0000000..7a63a74 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/flash_api.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "flash_data.h" +#include "mbed_critical.h" +#include "M460_mem.h" + +// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM +// NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian. +static uint32_t FLASH_ALGO[] = { + 0x4770ba40, 0x4770bac0, 0x0030ea4f, 0x00004770, 0xf8114601, 0xf8110b01, 0xeb003b01, 0xf8112003, + 0xeb003b01, 0xf8114003, 0xeb003b01, 0x47706003, 0x4603b510, 0x4c952059, 0x20166020, 0xf8c405a4, + 0x20880100, 0x0100f8c4, 0xf8d006c0, 0x28010100, 0x2001d001, 0x488ebd10, 0xf0406800, 0xf04f0004, + 0xf8c44480, 0x46200200, 0x0204f8d0, 0x0004f040, 0x0204f8c4, 0x68004887, 0x0029f040, 0x60204c85, + 0x68004620, 0x0029f000, 0xd0012829, 0xe7e12001, 0xe7df2000, 0xbf004601, 0x30c0487e, 0xf0006800, + 0x28000001, 0x487bd1f8, 0xf0206800, 0x4a790001, 0x20006010, 0xb5304770, 0x460c4603, 0x4875bf00, + 0x680030c0, 0x0001f000, 0xd1f82800, 0x68004871, 0x0040f040, 0x60284d6f, 0x60444628, 0x60c36082, + 0x61282001, 0xbf00bf00, 0xf3bfbf00, 0xbf008f6f, 0xbf00bf00, 0x4867bf00, 0x680030c0, 0x0001f000, + 0xd1f82800, 0x68014863, 0x0040f001, 0x4861b118, 0x20016001, 0x2000bd30, 0xb530e7fc, 0x25004604, + 0x040bf36f, 0x0070f404, 0x6f72f1b0, 0xf1a4d102, 0x4d596472, 0x4621462a, 0xf7ff2022, 0xbd30ffbc, + 0x4604b570, 0x2600460d, 0x4631e008, 0xf8541c76, 0xf7ff0021, 0xb108ffe2, 0xbd702001, 0xd3f442ae, + 0xe7fa2000, 0x41f0e92d, 0x460d4604, 0xf0044616, 0xb1100003, 0xe8bd2001, 0x1ce881f0, 0x0503f020, + 0x4844bf00, 0x680030c0, 0x0001f000, 0xd1f82800, 0x68004840, 0x0040f040, 0x6008493e, 0x60c82021, + 0x483ce024, 0x46306044, 0xff32f7ff, 0x60884939, 0x61082001, 0xbf00bf00, 0xf3bfbf00, 0xbf008f6f, + 0xbf00bf00, 0x4833bf00, 0x680030c0, 0x0001f000, 0xd1f82800, 0x6807482f, 0x0040f007, 0x482db118, + 0x20016007, 0x1d24e7c7, 0x1f2d1d36, 0xd1d82d00, 0xe7c02000, 0x41f0e92d, 0x460d4604, 0xf0044616, + 0xb1100003, 0xe8bd2001, 0x1ce881f0, 0x0503f020, 0x4820bf00, 0x680030c0, 0x0001f000, 0xd1f82800, + 0x6800481c, 0x0040f040, 0x6008491a, 0x60c82000, 0x4818e027, 0x20016044, 0x61084916, 0xbf00bf00, + 0xf3bfbf00, 0xbf008f6f, 0xbf00bf00, 0x4811bf00, 0x680030c0, 0x0001f000, 0xd1f82800, 0x6807480d, + 0x0040f007, 0x480bb110, 0xe00c6007, 0x68874809, 0xf7ff4630, 0x42b8fecd, 0xe004d000, 0x1d361d24, + 0x2d001f2d, 0xbf00d1d5, 0xe7bc4620, 0x40000100, 0x40000200, 0x4000c000, 0x0055aa03, 0x00000000, +}; + +static const flash_algo_t flash_algo_config = { + .init = 0x00000031, + .uninit = 0x00000095, + .erase_sector = 0x0000011b, + .program_page = 0x00000165, + .static_base = 0x0000029c, + .algo_blob = FLASH_ALGO +}; + +static const sector_info_t sectors_info[] = { + {MBED_ROM_START, 0x1000}, // (start, sector size) +}; + +static const flash_target_config_t flash_target_config = { + .page_size = 4, // 4 bytes + // Here page_size is program unit, which is different than FMC definition. + .flash_start = MBED_ROM_START, + .flash_size = MBED_ROM_SIZE, + .sectors = sectors_info, + .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) +}; + +void flash_set_target_config(flash_t *obj) +{ + obj->flash_algo = &flash_algo_config; + obj->target_config = &flash_target_config; +} diff --git a/targets/TARGET_NUVOTON/TARGET_M460/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M460/gpio_api.c new file mode 100644 index 0000000..bcb9d18 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/gpio_api.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_api.h" +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +uint32_t gpio_set(PinName pin) +{ + if (pin == (PinName) NC) { + return 0; + } + + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + +#if 1 + pin_function(pin, 0 << NU_MFP_POS(pin_index)); +#else + pinmap_pinout(pin, PinMap_GPIO); +#endif + + return (uint32_t)(1 << pin_index); // Return the pin mask +} + +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + + if (obj->pin == (PinName) NC) { + return; + } + + obj->mask = gpio_set(pin); + /* Default mode/direction */ + obj->mode = PullUp; + obj->direction = PIN_INPUT; +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + if (obj->pin == (PinName) NC) { + return; + } + + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + switch (mode) { + case PullNone: + if (mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } + MBED_FALLTHROUGH; + case PullDown: + if (mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } + MBED_FALLTHROUGH; + case PullUp: + if (mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } + /* H/W doesn't support separate configuration for input pull mode/direction. + * We translate to input-only/push-pull output I/O mode dependent on direction. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + case QuasiBidirectional: + /* With quasi-bidirectional I/O mode, before digital input function is performed, + * the corresponding bit in GPIOx_DOUT must be set to 1. */ + obj->mode = QuasiBidirectional; + if (obj->direction == PIN_INPUT) { + gpio_write(obj, 1); + } + break; + + case InputOnly: + case PushPullOutput: + /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode + * in the gpio_mode call here. */ + if (mode == InputOnly) { + obj->direction = PIN_INPUT; + obj->mode = InputOnly; + } else { + obj->direction = PIN_OUTPUT; + obj->mode = PushPullOutput; + } + break; + + default: + /* Allow for configuring other I/O modes directly */ + obj->mode = mode; + break; + } + + pin_mode(obj->pin, obj->mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + if (obj->pin == (PinName) NC) { + return; + } + + obj->direction = direction; + + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + switch (obj->mode) { + case PullNone: + if (obj->mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } + MBED_FALLTHROUGH; + case PullDown: + if (obj->mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } + MBED_FALLTHROUGH; + case PullUp: + if (obj->mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } + /* H/W doesn't support separate configuration for input pull mode/direction. + * We translate to input-only/push-pull output I/O mode dependent on direction. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + case QuasiBidirectional: + /* With quasi-bidirectional I/O mode, before digital input function is performed, + * the corresponding bit in GPIOx_DOUT must be set to 1. */ + if (obj->direction == PIN_INPUT) { + gpio_write(obj, 1); + } + break; + + case InputOnly: + case PushPullOutput: + /* We may meet contradictory I/O mode/direction configuration. Favor direction + * in the gpio_dir call here. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + default: + break; + } + + pin_mode(obj->pin, obj->mode); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M460/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M460/gpio_irq_api.c new file mode 100644 index 0000000..580cbd4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/gpio_irq_api.c @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_irq_api.h" + +#if DEVICE_INTERRUPTIN + +#include "gpio_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_bitutil.h" +#include "mbed_assert.h" + +#define NU_MAX_PIN_PER_PORT 16 + +struct nu_gpio_irq_var { + gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT]; + IRQn_Type irq_n; + void (*vec)(void); + uint32_t port_index; +}; + +static void gpio_irq_0_vec(void); +static void gpio_irq_1_vec(void); +static void gpio_irq_2_vec(void); +static void gpio_irq_3_vec(void); +static void gpio_irq_4_vec(void); +static void gpio_irq_5_vec(void); +static void gpio_irq_6_vec(void); +static void gpio_irq_7_vec(void); +static void gpio_irq_8_vec(void); +static void gpio_irq_9_vec(void); +static void gpio_irq(struct nu_gpio_irq_var *var); + +//EINT0_IRQn +static struct nu_gpio_irq_var gpio_irq_var_arr[] = { + {{NULL}, GPA_IRQn, gpio_irq_0_vec, 0}, + {{NULL}, GPB_IRQn, gpio_irq_1_vec, 1}, + {{NULL}, GPC_IRQn, gpio_irq_2_vec, 2}, + {{NULL}, GPD_IRQn, gpio_irq_3_vec, 3}, + {{NULL}, GPE_IRQn, gpio_irq_4_vec, 4}, + {{NULL}, GPF_IRQn, gpio_irq_5_vec, 5}, + {{NULL}, GPG_IRQn, gpio_irq_6_vec, 6}, + {{NULL}, GPH_IRQn, gpio_irq_7_vec, 7}, + {{NULL}, GPI_IRQn, gpio_irq_8_vec, 8}, + {{NULL}, GPJ_IRQn, gpio_irq_9_vec, 9}, +}; + +#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0])) + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0 +#endif + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC +#endif +static PinName gpio_irq_debounce_arr[] = { + MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST +}; + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC +#endif + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 +#endif + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) +{ + if (pin == NC) { + return -1; + } + + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + uint32_t port_index = NU_PINNAME_TO_PORT(pin); + if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) { + return -1; + } + + obj->pin = pin; + obj->irq_types = 0; + obj->irq_handler = (uint32_t) handler; + obj->irq_id = context; + + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. + // There is no need to call gpio_set() redundantly. + + { +#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE + // Suppress compiler warning + (void) gpio_irq_debounce_arr; + + // Configure de-bounce clock source and sampling cycle time + GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); +#else + // Enable de-bounce if the pin is in the de-bounce enable list + + // De-bounce defaults to disabled. + GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index); + + PinName *debounce_pos = gpio_irq_debounce_arr; + PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]); + for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) { + uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos); + uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos); + + if (pin_index == pin_index_debunce && + port_index == port_index_debounce) { + // Configure de-bounce clock source and sampling cycle time + GPIO_SET_DEBOUNCE_TIME(gpio_base, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); + break; + } + } +#endif + } + + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + var->obj_arr[pin_index] = obj; + + // NOTE: InterruptIn requires IRQ enabled by default. + gpio_irq_enable(obj); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_DisableIRQ(var->irq_n); + NU_PORT_BASE(port_index)->INTEN = 0; + + MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT); + var->obj_arr[pin_index] = NULL; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + /* We assume BSP has such coding so that we can easily add/remove either irq type. */ + static_assert(GPIO_INT_BOTH_EDGE == (GPIO_INT_RISING | GPIO_INT_FALLING), + "GPIO_INT_BOTH_EDGE must be bitwise OR of GPIO_INT_RISING and GPIO_INT_FALLING"); + uint32_t irq_type; + switch (event) { + case IRQ_RISE: + irq_type = GPIO_INT_RISING; + break; + + case IRQ_FALL: + irq_type = GPIO_INT_FALLING; + break; + + default: + irq_type = 0; + } + + /* We can handle invalid/null irq type. */ + if (enable) { + obj->irq_types |= irq_type; + } else { + obj->irq_types &= ~irq_type; + } + + /* Update irq types: + * + * Implementations of GPIO_EnableInt(...) are inconsistent: disable or not irq type not enabled. + * For consistency, disable GPIO_INT_BOTH_EDGE and then enable OR'ed irq types, GPIO_INT_RISING, + * GPIO_INT_FALLING, or both. + */ + GPIO_DisableInt(gpio_base, pin_index); + GPIO_EnableInt(gpio_base, pin_index, obj->irq_types); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_SetVector(var->irq_n, (uint32_t) var->vec); + NVIC_EnableIRQ(var->irq_n); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_DisableIRQ(var->irq_n); +} + +static void gpio_irq_0_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 0); +} +static void gpio_irq_1_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 1); +} +static void gpio_irq_2_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 2); +} +static void gpio_irq_3_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 3); +} +static void gpio_irq_4_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 4); +} +static void gpio_irq_5_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 5); +} +static void gpio_irq_6_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 6); +} +static void gpio_irq_7_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 7); +} +static void gpio_irq_8_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 8); +} +static void gpio_irq_9_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 9); +} + +static void gpio_irq(struct nu_gpio_irq_var *var) +{ + // NOTE: GPA_IRQn, GPB_IRQn, ... are not arranged sequentially, so we cannot calculate out port_index through offset from GPA_IRQn. + // Instead, we add port_index into gpio_irq_var_arr table. + uint32_t port_index = var->port_index; + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + uint32_t intsrc = gpio_base->INTSRC; + uint32_t inten = gpio_base->INTEN; + while (intsrc) { + int pin_index = nu_ctz(intsrc); + gpio_irq_t *obj = var->obj_arr[pin_index]; + if (inten & (GPIO_INT_RISING << pin_index)) { + if (GPIO_PIN_DATA(port_index, pin_index)) { + if (obj->irq_handler) { + ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE); + } + } + } + + if (inten & (GPIO_INT_FALLING << pin_index)) { + if (! GPIO_PIN_DATA(port_index, pin_index)) { + if (obj->irq_handler) { + ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL); + } + } + } + + intsrc &= ~(1 << pin_index); + } + // Clear all interrupt flags + gpio_base->INTSRC = gpio_base->INTSRC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/gpio_object.h b/targets/TARGET_NUVOTON/TARGET_M460/gpio_object.h new file mode 100644 index 0000000..14478ba --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/gpio_object.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + PinDirection direction; + PinMode mode; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + + GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0; +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + + return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M460/i2c_api.c new file mode 100644 index 0000000..9175204 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/i2c_api.c @@ -0,0 +1,1020 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" +#include "mbed_critical.h" +#include "us_ticker_api.h" + +struct nu_i2c_var { + i2c_t * obj; + void (*vec)(void); +}; + +static void i2c0_vec(void); +static void i2c1_vec(void); +static void i2c2_vec(void); +static void i2c3_vec(void); +static void i2c4_vec(void); +static void i2c_irq(i2c_t *obj); +static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl); +static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked); + +static struct nu_i2c_var i2c0_var = { + .obj = NULL, + .vec = i2c0_vec, +}; +static struct nu_i2c_var i2c1_var = { + .obj = NULL, + .vec = i2c1_vec, +}; +static struct nu_i2c_var i2c2_var = { + .obj = NULL, + .vec = i2c2_vec, +}; +static struct nu_i2c_var i2c3_var = { + .obj = NULL, + .vec = i2c3_vec, +}; +static struct nu_i2c_var i2c4_var = { + .obj = NULL, + .vec = i2c4_vec, +}; + +static uint32_t i2c_modinit_mask = 0; + +static const struct nu_modinit_s i2c_modinit_tab[] = { + {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var}, + {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var}, + {I2C_2, I2C2_MODULE, 0, 0, I2C2_RST, I2C2_IRQn, &i2c2_var}, + {I2C_3, I2C3_MODULE, 0, 0, I2C3_RST, I2C3_IRQn, &i2c3_var}, + {I2C_4, I2C4_MODULE, 0, 0, I2C4_RST, I2C4_IRQn, &i2c4_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata); +static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync); +#define NU_I2C_TIMEOUT_STAT_INT 500000 +#define NU_I2C_TIMEOUT_STOP 500000 +static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout); +static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout); +static int i2c_is_trsn_done(i2c_t *obj); +static int i2c_is_tran_started(i2c_t *obj); +static int i2c_addr2data(int address, int read); +#if DEVICE_I2CSLAVE +// Convert mbed address to BSP address. +static int i2c_addr2bspaddr(int address); +#endif // #if DEVICE_I2CSLAVE +static void i2c_enable_int(i2c_t *obj); +static void i2c_disable_int(i2c_t *obj); +static int i2c_set_int(i2c_t *obj, int inten); + + +#if DEVICE_I2C_ASYNCH +static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length); +static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable); +static void i2c_rollback_vector_interrupt(i2c_t *obj); +#endif + +#define TRANCTRL_STARTED (1) // Guard I2C ISR from data transfer prematurely +#define TRANCTRL_NAKLASTDATA (1 << 1) // Request NACK on last data +#define TRANCTRL_LASTDATANAKED (1 << 2) // Last data NACKed +#define TRANCTRL_RECVDATA (1 << 3) // Receive data available + +uint32_t us_ticker_read(void); + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c.i2c != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + obj->i2c.pin_sda = sda; + obj->i2c.pin_scl = scl; + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + +#if DEVICE_I2C_ASYNCH + obj->i2c.dma_usage = DMA_USAGE_NEVER; + obj->i2c.event = 0; + obj->i2c.stop = 0; + obj->i2c.address = 0; +#endif + + // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp. + I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000); + // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL0. We cannot control interrupt through + // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control. + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + i2c_base->CTL0 |= (I2C_CTL0_INTEN_Msk | I2C_CTL0_I2CEN_Msk); + + // Enable sync-mode vector interrupt. + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + var->obj = obj; + obj->i2c.tran_ctrl = 0; + obj->i2c.stop = 0; + i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1); + + // Mark this module to be inited. + int i = modinit - i2c_modinit_tab; + i2c_modinit_mask |= 1 << i; +} + +void i2c_free(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + /* Disable I2C interrupt */ + NVIC_DisableIRQ(modinit->irq_n); + + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + /* Disable I2C module */ + I2C_Close(i2c_base); + + /* Disable IP clock */ + CLK_DisableModuleClock(modinit->clkidx); + + // Mark this module to be deinited. + int i = modinit - i2c_modinit_tab; + i2c_modinit_mask &= ~(1 << i); + + /* Free up pins */ + gpio_set(obj->i2c.pin_sda); + gpio_set(obj->i2c.pin_scl); + obj->i2c.pin_sda = NC; + obj->i2c.pin_scl = NC; +} + +int i2c_start(i2c_t *obj) +{ + return i2c_do_trsn(obj, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk, 1); +} + +int i2c_stop(i2c_t *obj) +{ + return i2c_do_trsn(obj, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk, 1); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in bytes + length = i2c_do_tran(obj, data, length, 1, 1); + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Write out bytes + length = i2c_do_tran(obj, (char *) data, length, 0, 1); + + if (stop) { + i2c_stop(obj); + } + + return length; +} + +void i2c_reset(i2c_t *obj) +{ + i2c_stop(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + char data = 0; + i2c_do_tran(obj, &data, 1, 1, last); + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + char data_[1]; + data_[0] = data & 0xFF; + + if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 && + ! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) { + return 1; + } else { + return 0; + } +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if DEVICE_I2CSLAVE + +// See I2CSlave.h +#define NoData 0 // the slave has not been addressed +#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +#define WriteGeneral 2 // the master is writing to all slave +#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + i2c_disable_int(obj); + + obj->i2c.slaveaddr_state = NoData; + + // Switch to not addressed mode + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + + i2c_enable_int(obj); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int slaveaddr_state; + + i2c_disable_int(obj); + slaveaddr_state = obj->i2c.slaveaddr_state; + i2c_enable_int(obj); + + return slaveaddr_state; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + return i2c_do_tran(obj, data, length, 1, 1); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + return i2c_do_tran(obj, (char *) data, length, 0, 1); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + i2c_disable_int(obj); + + // NOTE: On NUC472/M451, non-zero slave address can still work as GC mode is enabled. + // On M480, non-zero slave address won't work as GC mode is enabled. + I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_DISABLE); + + i2c_enable_int(obj); +} + +static int i2c_addr2bspaddr(int address) +{ + return (address >> 1); +} + +#endif // #if DEVICE_I2CSLAVE + +static void i2c_enable_int(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + + core_util_critical_section_enter(); + + // Enable I2C interrupt + NVIC_EnableIRQ(modinit->irq_n); + obj->i2c.inten = 1; + + core_util_critical_section_exit(); +} + +static void i2c_disable_int(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + + core_util_critical_section_enter(); + + // Disable I2C interrupt + NVIC_DisableIRQ(modinit->irq_n); + obj->i2c.inten = 0; + + core_util_critical_section_exit(); +} + +static int i2c_set_int(i2c_t *obj, int inten) +{ + int inten_back; + + core_util_critical_section_enter(); + + inten_back = obj->i2c.inten; + + core_util_critical_section_exit(); + + if (inten) { + i2c_enable_int(obj); + } else { + i2c_disable_int(obj); + } + + return inten_back; +} + +static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata) +{ + if (! buf || ! length) { + return 0; + } + + int tran_len = 0; + + i2c_disable_int(obj); + obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED; + obj->i2c.tran_beg = buf; + obj->i2c.tran_pos = buf; + obj->i2c.tran_end = buf + length; + i2c_enable_int(obj); + + if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) { + // N/A + } else { + i2c_disable_int(obj); + tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg; + obj->i2c.tran_beg = NULL; + obj->i2c.tran_pos = NULL; + obj->i2c.tran_end = NULL; + i2c_enable_int(obj); + } + + return tran_len; +} + +static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + int err = 0; + + i2c_disable_int(obj); + + if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) { + err = I2C_ERROR_BUS_BUSY; + } else { + // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error. + uint32_t status = I2C_GET_STATUS(i2c_base); + + switch (status) { + case 0x08: // Start + case 0x10: // Master Repeat Start + if (i2c_ctl & I2C_CTL0_STA_Msk) { + goto cleanup; + } else { + break; + } + case 0xF8: // Bus Released + if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) { + goto cleanup; + } else { + break; + } + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) { + err = I2C_ERROR_BUS_BUSY; + } + } + +cleanup: + + i2c_enable_int(obj); + + return err; +} + +static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout) +{ + uint32_t t1, t2, elapsed = 0; + int status_assert = 0; + const uint32_t bits = us_ticker_get_info()->bits; + const uint32_t mask = (1 << bits) - 1; + + t1 = us_ticker_read(); + while (1) { + status_assert = is_status(obj); + if (status_assert) { + break; + } + + t2 = us_ticker_read(); + elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + mask - t1 + 1); + if (elapsed >= timeout) { + break; + } + } + + return (elapsed >= timeout); +} + +static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout) +{ + uint32_t t1, t2, elapsed = 0; + int tran_started; + char *tran_pos = NULL; + char *tran_pos2 = NULL; + const uint32_t bits = us_ticker_get_info()->bits; + const uint32_t mask = (1 << bits) - 1; + + i2c_disable_int(obj); + tran_pos = obj->i2c.tran_pos; + i2c_enable_int(obj); + t1 = us_ticker_read(); + while (1) { + i2c_disable_int(obj); + tran_started = i2c_is_tran_started(obj); + i2c_enable_int(obj); + if (! tran_started) { // Transfer completed or stopped + break; + } + + i2c_disable_int(obj); + tran_pos2 = obj->i2c.tran_pos; + i2c_enable_int(obj); + t2 = us_ticker_read(); + if (tran_pos2 != tran_pos) { // Transfer on-going + t1 = t2; + tran_pos = tran_pos2; + continue; + } + + elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + mask - t1 + 1); + if (elapsed >= timeout) { // Transfer idle + break; + } + } + + return (elapsed >= timeout); +} + +#if 0 +static int i2c_is_stat_int(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + return !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk); +} + +static int i2c_is_stop_det(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + return ! (i2c_base->CTL0 & I2C_CTL0_STO_Msk); +} +#endif + +static int i2c_is_trsn_done(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + int i2c_int; + uint32_t status; + int inten_back; + + inten_back = i2c_set_int(obj, 0); + i2c_int = !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk); + status = I2C_GET_STATUS(i2c_base); + i2c_set_int(obj, inten_back); + + return (i2c_int || status == 0xF8); +} + +static int i2c_is_tran_started(i2c_t *obj) +{ + int started; + int inten_back; + + inten_back = i2c_set_int(obj, 0); + started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED); + i2c_set_int(obj, inten_back); + + return started; +} + +static int i2c_addr2data(int address, int read) +{ + return read ? (address | 1) : (address & 0xFE); +} + +static void i2c0_vec(void) +{ + i2c_irq(i2c0_var.obj); +} +static void i2c1_vec(void) +{ + i2c_irq(i2c1_var.obj); +} +static void i2c2_vec(void) +{ + i2c_irq(i2c2_var.obj); +} +static void i2c3_vec(void) +{ + i2c_irq(i2c3_var.obj); +} +static void i2c4_vec(void) +{ + i2c_irq(i2c4_var.obj); +} + +static void i2c_irq(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + uint32_t status; + + if (I2C_GET_TIMEOUT_FLAG(i2c_base)) { + I2C_ClearTimeoutFlag(i2c_base); + return; + } + + status = I2C_GET_STATUS(i2c_base); + + switch (status) { + // Master Transmit + case 0x28: // Master Transmit Data ACK + case 0x18: // Master Transmit Address ACK + case 0x08: // Start + case 0x10: // Master Repeat Start + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else { + i2c_fsm_tranfini(obj, 0); + } + } else { + i2c_disable_int(obj); + } + break; + + case 0x30: // Master Transmit Data NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x20: // Master Transmit Address NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x38: // Master Arbitration Lost + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + break; + + case 0x48: // Master Receive Address NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x40: // Master Receive Address ACK + case 0x50: // Master Receive Data ACK + case 0x58: // Master Receive Data NACK + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x50 || status == 0x58) { + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } + } + + if (status == 0x58) { + i2c_fsm_tranfini(obj, 1); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + + //case 0x00: // Bus error + + // Slave Transmit + case 0xB8: // Slave Transmit Data ACK + case 0xA8: // Slave Transmit Address ACK + case 0xB0: // Slave Transmit Arbitration Lost + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + + I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++); + if (obj->i2c.tran_pos == obj->i2c.tran_end && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + obj->i2c.slaveaddr_state = ReadAddressed; + break; + //case 0xA0: // Slave Transmit Repeat Start or Stop + case 0xC0: // Slave Transmit Data NACK + case 0xC8: // Slave Transmit Last Data ACK + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + break; + + // Slave Receive + case 0x80: // Slave Receive Data ACK + case 0x88: // Slave Receive Data NACK + case 0x60: // Slave Receive Address ACK + case 0x68: // Slave Receive Arbitration Lost + obj->i2c.slaveaddr_state = WriteAddressed; + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x80 || status == 0x88) { + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } + } + + if (status == 0x88) { + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + //case 0xA0: // Slave Receive Repeat Start or Stop + + // GC mode + //case 0xA0: // GC mode Repeat Start or Stop + case 0x90: // GC mode Data ACK + case 0x98: // GC mode Data NACK + case 0x70: // GC mode Address ACK + case 0x78: // GC mode Arbitration Lost + obj->i2c.slaveaddr_state = WriteAddressed; + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x90 || status == 0x98) { + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } + } + + if (status == 0x98) { + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + + case 0xF8: // Bus Released + break; + + default: + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } +} + +static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + obj->i2c.stop = 0; + + obj->i2c.tran_ctrl = 0; + + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.slaveaddr_state = NoData; +} + +static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked) +{ + if (lastdatanaked) { + obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED; + } + + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); +} + +#if DEVICE_I2C_ASYNCH + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + // NOTE: M451 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1). + MBED_ASSERT((address & 0xFFFFFF00) == 0); + + // NOTE: First transmit and then receive. + + (void) hint; + obj->i2c.dma_usage = DMA_USAGE_NEVER; + obj->i2c.stop = stop; + obj->i2c.address = address; + obj->i2c.event = event; + i2c_buffer_set(obj, tx, tx_length, rx, rx_length); + + i2c_enable_vector_interrupt(obj, handler, 1); + i2c_start(obj); +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + int event = 0; + + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + uint32_t status = I2C_GET_STATUS(i2c_base); + switch (status) { + case 0x08: // Start + case 0x10: {// Master Repeat Start + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0))); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1))); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + } + + case 0x18: // Master Transmit Address ACK + case 0x28: // Master Transmit Data ACK + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + uint8_t *tx = (uint8_t *)obj->tx_buff.buffer; + I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + + case 0x20: // Master Transmit Address NACK + event = I2C_EVENT_ERROR_NO_SLAVE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + break; + + case 0x30: // Master Transmit Data NACK + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + event = I2C_EVENT_TRANSFER_EARLY_NACK; + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + + case 0x38: // Master Arbitration Lost + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); // Enter not addressed SLV mode + event = I2C_EVENT_ERROR; + break; + + case 0x50: // Master Receive Data ACK + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + uint8_t *rx = (uint8_t *) obj->rx_buff.buffer; + rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c))); + } + MBED_FALLTHROUGH; + case 0x40: // Master Receive Address ACK + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL0_AA_Msk : 0)); + break; + + case 0x48: // Master Receive Address NACK + event = I2C_EVENT_ERROR_NO_SLAVE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + break; + + case 0x58: // Master Receive Data NACK + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + uint8_t *rx = (uint8_t *) obj->rx_buff.buffer; + rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c))); + } + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + break; + + case 0x00: // Bus error + event = I2C_EVENT_ERROR; + i2c_reset(obj); + break; + + default: + event = I2C_EVENT_ERROR; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + + if (event) { + i2c_rollback_vector_interrupt(obj); + } + + return (event & obj->i2c.event); +} + +uint8_t i2c_active(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + // Vector will be changed for async transfer. Use it to judge if async transfer is on-going. + uint32_t vec = NVIC_GetVector(modinit->irq_n); + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + return (vec && vec != (uint32_t) var->vec); +} + +void i2c_abort_asynch(i2c_t *obj) +{ + i2c_rollback_vector_interrupt(obj); + i2c_stop(obj); +} + +static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; +} + +static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + if (enable) { + NVIC_SetVector(modinit->irq_n, handler); + i2c_enable_int(obj); + } else { + i2c_disable_int(obj); + } + +} + +static void i2c_rollback_vector_interrupt(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1); +} + +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M460/lp_ticker.c new file mode 100644 index 0000000..5af6f36 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/lp_ticker.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lp_ticker_api.h" + +#if DEVICE_LPTICKER + +#include "sleep_api.h" +#include "mbed_assert.h" +#include "nu_modutil.h" +#include "nu_timer.h" +#include "nu_miscutil.h" + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per lp_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT +#define NU_TMRCLK_PER_SEC (__LXT) +#else +#define NU_TMRCLK_PER_SEC (__LIRC) +#endif +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) + +static void tmr1_vec(void); + +/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +#if MBED_CONF_TARGET_LXT_PRESENT +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#else +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#endif + +#define TIMER_MODINIT timer1_modinit + +/* Timer interrupt enable/disable + * + * Because Timer interrupt enable/disable (TIMER_EnableInt/TIMER_DisableInt) needs wait for lp_ticker, + * we call NVIC_DisableIRQ/NVIC_EnableIRQ instead. + */ + +/* Track ticker status */ +static volatile uint16_t ticker_inited = 0; + +#define TMR_CMP_MIN 2 +#define TMR_CMP_MAX 0xFFFFFFu + +/* Synchronization issue with LXT/LIRC-clocked Timer + * + * PCLK : typical HCLK/2 + * ECLK (engine clock) : LXT/LIRC for Timer used to implement lp_ticker + * + * When system clock is higher than Timer clock (LXT/LIRC), we need to add delay for ECLK + * domain to take effect: + * 1. Write : typical 1PCLK + 2ECLK + * Read-check doesn't work because it just checks PCLK domain and doesn't check into + * ECLK domain. + * 2. Clear interrupt flag : typical 2PCLK + * It is very rare that we would meet dummy interrupt and get stuck in ISR until + * 'clear interrupt flag' takes effect. The issue is ignorable because the pending + * time is very short (at most 1 dummy interrupt). We won't take special handling for it. + */ + +void lp_ticker_init(void) +{ + if (ticker_inited) { + /* By HAL spec, ticker_init allows the ticker to keep counting and disables the + * ticker interrupt. */ + lp_ticker_disable_interrupt(); + return; + } + ticker_inited = 1; + + // Select IP clock source + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + // Enable IP clock + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + + // Reset module + SYS_ResetModule(TIMER_MODINIT.rsetidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + // Configure clock + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + // Continuous mode + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + timer_base->CMP = cmp_timer; + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + // Set vector + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + TIMER_EnableWakeup(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + TIMER_Start(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + /* Wait for timer to start counting and raise active flag */ + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); +} + +void lp_ticker_free(void) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + /* Disable IP clock */ + CLK_DisableModuleClock(TIMER_MODINIT.clkidx); + + ticker_inited = 0; +} + +timestamp_t lp_ticker_read() +{ + if (! ticker_inited) { + lp_ticker_init(); + } + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + /* Clear any previously pending interrupts */ + lp_ticker_clear_interrupt(); + NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n); + + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + + /* NOTE: Rely on LPTICKER_DELAY_TICKS to be non-blocking. */ + timer_base->CMP = cmp_timer; + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +void lp_ticker_disable_interrupt(void) +{ + /* We cannot call ticker_irq_handler now. */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); +} + +void lp_ticker_clear_interrupt(void) +{ + /* To avoid sync issue, we clear TIF/TWKF simultaneously rather than call separate + * driver API: + * + * TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + * TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + timer_base->INTSTS = TIMER_INTSTS_TIF_Msk | TIMER_INTSTS_TWKF_Msk; +} + +void lp_ticker_fire_interrupt(void) +{ + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +const ticker_info_t* lp_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +static void tmr1_vec(void) +{ + lp_ticker_clear_interrupt(); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M460/mbed_overrides.c new file mode 100644 index 0000000..b81ad3e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/mbed_overrides.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogin_api.h" + +void mbed_sdk_init(void) +{ + // NOTE: Support singleton semantics to be called from other init functions + static int inited = 0; + if (inited) { + return; + } + inited = 1; + + /*---------------------------------------------------------------------------------------------------------*/ + /* Init System Clock */ + /*---------------------------------------------------------------------------------------------------------*/ + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* Enable HIRC clock (Internal RC 22.1184MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT + /* Enable HXT clock (external XTAL 12MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#else + /* Disable HXT clock (external XTAL 12MHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#endif + /* Enable LIRC */ + CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT + /* Enable LXT */ + CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#else + /* Disable LXT */ + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#endif + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); +#endif + /* Wait for LIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT + /* Wait for LXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); +#endif + + /* Set PCLK0 and PCLK1 to HCLK/2 */ + CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2); + + /* Set core clock to 200MHz */ + CLK_SetCoreClock(200000000); + + /* Enable all GPIO clock */ + CLK->AHBCLK0 |= CLK_AHBCLK0_GPACKEN_Msk | CLK_AHBCLK0_GPBCKEN_Msk | CLK_AHBCLK0_GPCCKEN_Msk | CLK_AHBCLK0_GPDCKEN_Msk | + CLK_AHBCLK0_GPECKEN_Msk | CLK_AHBCLK0_GPFCKEN_Msk | CLK_AHBCLK0_GPGCKEN_Msk | CLK_AHBCLK0_GPHCKEN_Msk; + CLK->AHBCLK1 |= CLK_AHBCLK1_GPICKEN_Msk | CLK_AHBCLK1_GPJCKEN_Msk; + +#if DEVICE_ANALOGIN + /* Vref connect to internal */ + SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V; +#endif + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M460/objects.h b/targets/TARGET_NUVOTON/TARGET_M460/objects.h new file mode 100644 index 0000000..9c747f7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/objects.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "dma_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + PinName pin; + uint32_t irq_types; + uint32_t irq_handler; + uint32_t irq_id; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct dac_s { + DACName dac; + PinName pin; +}; + +struct serial_s { + UARTName uart; + PinName pin_tx; + PinName pin_rx; + PinName pin_rts; + PinName pin_cts; + + uint32_t baudrate; + uint32_t databits; + uint32_t parity; + uint32_t stopbits; + + void (*vec)(void); + uint32_t irq_handler; + uint32_t irq_id; + uint32_t irq_en; + uint32_t inten_msk; + + // Async transfer related fields + DMAUsage dma_usage_tx; + DMAUsage dma_usage_rx; + int dma_chn_id_tx; + int dma_chn_id_rx; + uint32_t event; + void (*irq_handler_tx_async)(void); + void (*irq_handler_rx_async)(void); +}; + +struct spi_s { + SPIName spi; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; + + // Async transfer related fields + DMAUsage dma_usage; + int dma_chn_id_tx; + int dma_chn_id_rx; + uint32_t event; + uint32_t txrx_rmn; // Track tx/rx frames remaining in interrupt way +}; + +struct i2c_s { + I2CName i2c; + PinName pin_sda; + PinName pin_scl; + int slaveaddr_state; + + uint32_t tran_ctrl; + char * tran_beg; + char * tran_pos; + char * tran_end; + int inten; + + // Async transfer related fields + DMAUsage dma_usage; + uint32_t event; + int stop; + uint32_t address; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period_us; + uint32_t pulsewidth_us; +}; + +struct can_s { + CANName can; + PinName pin_rd; + PinName pin_td; + int index; +}; + +struct trng_s { + uint8_t dummy; +}; + +#ifdef __cplusplus +} +#endif + +#include "gpio_object.h" + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M460/pinmap.c new file mode 100644 index 0000000..7474c0a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/pinmap.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "mbed_error.h" + +/** + * Configure pin multi-function + */ +void pin_function(PinName pin, int data) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + uint32_t port_index = NU_PINNAME_TO_PORT(pin); + __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFP0) + port_index * 4 + (pin_index / 4); + uint32_t MFP_Msk = NU_MFP_MSK(pin_index); + + // E.g.: SYS->GPA_MFP0 = (SYS->GPA_MFP0 & (~SYS_GPA_MFP0_PA0MFP_Msk) ) | SYS_GPA_MFP0_PA0MFP_SC0_CLK ; + *GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data; +} + +/** + * Configure pin pull-up/pull-down + */ +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + uint32_t port_index = NU_PINNAME_TO_PORT(pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + uint32_t mode_intern = GPIO_MODE_INPUT; + + switch (mode) { + case InputOnly: + mode_intern = GPIO_MODE_INPUT; + break; + + case PushPullOutput: + mode_intern = GPIO_MODE_OUTPUT; + break; + + case OpenDrain: + mode_intern = GPIO_MODE_OPEN_DRAIN; + break; + + case QuasiBidirectional: + mode_intern = GPIO_MODE_QUASI; + break; + + default: + /* H/W doesn't support separate configuration for input pull mode/direction. + * We expect upper layer would have translated input pull mode/direction + * to I/O mode */ + return; + } + + GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern); + + /* Invalid combinations of PinMode/PinDirection + * + * We assume developer would avoid the following combinations of PinMode/PinDirection + * which are invalid: + * 1. InputOnly/PIN_OUTPUT + * 2. PushPullOutput/PIN_INPUT + */ +} + +/* List of pins excluded from testing */ +const PinList *pinmap_restricted_pins() +{ + static const PinName pins[] = { + CONSOLE_TX, CONSOLE_RX, // Dedicated to USB VCOM +#if MBED_CONF_TARGET_EXCLUDE_UNO_SPI_FROM_FPGA_CI_TEST_SHIELD_TEST + ARDUINO_UNO_D8, // Dedicated to on-board SPI flash + ARDUINO_UNO_D9, + ARDUINO_UNO_D10, + ARDUINO_UNO_D11, + ARDUINO_UNO_D12, + ARDUINO_UNO_D13, +#endif + }; + static const PinList pin_list = { + sizeof(pins) / sizeof(pins[0]), + pins + }; + return &pin_list; +} + +/* List of UART peripherals excluded from testing */ +#if DEVICE_SERIAL +const PeripheralList *pinmap_uart_restricted_peripherals() +{ + static const int peripherals[] = { + USB_UART, // Dedicated to USB VCOM + }; + + static const PeripheralList peripheral_list = { + sizeof peripherals / sizeof peripherals[0], + peripherals + }; + return &peripheral_list; +} +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/port_api.c b/targets/TARGET_NUVOTON/TARGET_M460/port_api.c new file mode 100644 index 0000000..0e78a19 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/port_api.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "port_api.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + obj->port = port; + obj->mask = mask; + obj->direction = dir; + + uint32_t i; + obj->direction = dir; + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + gpio_set(port_pin(port, i)); + } + } + + port_dir(obj, dir); +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + obj->direction = dir; + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + if (dir == PIN_OUTPUT) { + GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT); + } else { // PIN_INPUT + GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT); + } + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t i; + uint32_t port_index = obj->port; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0; + } + } +} + +int port_read(port_t *obj) +{ + uint32_t i; + uint32_t port_index = obj->port; + int value = 0; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + value = value | (GPIO_PIN_DATA(port_index, i) << i); + } + } + + return value; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M460/pwmout_api.c new file mode 100644 index 0000000..86292a4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/pwmout_api.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" + +struct nu_pwm_var { + uint32_t en_msk; +}; + +static struct nu_pwm_var pwm0_var = { + .en_msk = 0 +}; + +static struct nu_pwm_var pwm1_var = { + .en_msk = 0 +}; + +static uint32_t pwm_modinit_mask = 0; + +static const struct nu_modinit_s pwm_modinit_tab[] = { + {PWM_0_0, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P0_IRQn, &pwm0_var}, + {PWM_0_1, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P0_IRQn, &pwm0_var}, + {PWM_0_2, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P1_IRQn, &pwm0_var}, + {PWM_0_3, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P1_IRQn, &pwm0_var}, + {PWM_0_4, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P2_IRQn, &pwm0_var}, + {PWM_0_5, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0P2_IRQn, &pwm0_var}, + + {PWM_1_0, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P0_IRQn, &pwm1_var}, + {PWM_1_1, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P0_IRQn, &pwm1_var}, + {PWM_1_2, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P1_IRQn, &pwm1_var}, + {PWM_1_3, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P1_IRQn, &pwm1_var}, + {PWM_1_4, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P2_IRQn, &pwm1_var}, + {PWM_1_5, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1P2_IRQn, &pwm1_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +static void pwmout_config(pwmout_t *obj, int start); + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT((int) obj->pwm != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->pwm); + + obj->pin = pin; + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); + + // NOTE: Channels 0/1/2/3/4/5 share a clock source. + if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) { + // Select clock source of paired channels + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + // Enable clock of paired channels + CLK_EnableModuleClock(modinit->clkidx); + } + + // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module. + if (!((struct nu_pwm_var *) modinit->var)->en_msk) { + // Reset this module if no channel enabled + SYS_ResetModule(modinit->rsetidx); + } + + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + + // Default: period = 10 ms, pulse width = 0 ms + obj->period_us = 1000 * 10; + obj->pulsewidth_us = 0; + pwmout_config(obj, 0); + + ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn; + + // Mark this module to be inited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask |= 1 << i; +} + +void pwmout_free(pwmout_t *obj) +{ + EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm); + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + EPWM_ForceStop(pwm_base, 1 << chn); + + const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->pwm); + ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn); + + + if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) { + CLK_DisableModuleClock(modinit->clkidx); + } + + // Mark this module to be deinited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->pin); + obj->pin = NC; +} + +void pwmout_write(pwmout_t *obj, float value) +{ + obj->pulsewidth_us = NU_CLAMP((uint32_t)(value * obj->period_us), 0, obj->period_us); + pwmout_config(obj, 1); +} + +float pwmout_read(pwmout_t *obj) +{ + return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f); +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t *obj, int us) +{ + uint32_t period_us_old = obj->period_us; + uint32_t pulsewidth_us_old = obj->pulsewidth_us; + obj->period_us = us; + obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us); + pwmout_config(obj, 1); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->period_us; +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us); + pwmout_config(obj, 1); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) +{ + return obj->pulsewidth_us; +} + +static void pwmout_config(pwmout_t *obj, int start) +{ + EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm); + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + + // To avoid abnormal pulse on (re-)configuration, follow the sequence: stop/configure(/re-start). + // NOTE: The issue is met in ARM mbed CI test tests-api-pwm on M487. + EPWM_ForceStop(pwm_base, 1 << chn); + + // NOTE: Support period < 1s + // NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by: + // 1. Inverse duty cycle (10000 - duty) + // 2. Inverse PWM output polarity + // This trick is here to pass ARM mbed CI test. First PWM pulse error still remains. + EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us); + pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn); + + if (start) { + // Enable output of the specified PWM channel + EPWM_EnableOutput(pwm_base, 1 << chn); + EPWM_Start(pwm_base, 1 << chn); + } +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/reset_reason.c b/targets/TARGET_NUVOTON/TARGET_M460/reset_reason.c new file mode 100644 index 0000000..48f61a1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/reset_reason.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "reset_reason_api.h" + +#if DEVICE_RESET_REASON + +#include "cmsis.h" + +/* All reset source flags + * + * NOTE: HRESETRF is combined reset flag. Filter it out to avoid interference with reset reason check. + */ +#define SYS_RSTSTS_ALLRF_Msk \ + (SYS_RSTSTS_PORF_Msk | \ + SYS_RSTSTS_PINRF_Msk | \ + SYS_RSTSTS_WDTRF_Msk | \ + SYS_RSTSTS_LVRF_Msk | \ + SYS_RSTSTS_BODRF_Msk | \ + SYS_RSTSTS_MCURF_Msk | \ + SYS_RSTSTS_CPURF_Msk | \ + SYS_RSTSTS_CPULKRF_Msk) + +reset_reason_t hal_reset_reason_get(void) +{ + uint32_t reset_reason_raw = hal_reset_reason_get_raw(); + reset_reason_t reset_reason_cast; + uint32_t reset_reason_count = 0; + + if (SYS_IS_POR_RST()) { + reset_reason_cast = RESET_REASON_POWER_ON; + reset_reason_count ++; + } + + if (SYS_IS_RSTPIN_RST()) { + reset_reason_cast = RESET_REASON_PIN_RESET; + reset_reason_count ++; + } + + if (SYS_IS_WDT_RST()) { + reset_reason_cast = RESET_REASON_WATCHDOG; + reset_reason_count ++; + } + + if (SYS_IS_LVR_RST()) { + reset_reason_cast = RESET_REASON_PLATFORM; + reset_reason_count ++; + } + + if (SYS_IS_BOD_RST()) { + reset_reason_cast = RESET_REASON_BROWN_OUT; + reset_reason_count ++; + } + + /* This MCU supports MKROM and we need to take care of bootloader/SYSRESETREQ flow. */ + if (SYS_IS_SYSTEM_RST()) { + if (reset_reason_raw & (SYS_RSTSTS_ALLRF_Msk & ~SYS_RSTSTS_MCURF_Msk)) { + /* We may boot from bootloader which would reset to go to LDROM/APROM at its end + * through writing 1 to SYSRESETREQ bit. If there are other reset reasons, we think + * it is just the case and ignore the reset reason with SYSRESETREQ. */ + } else { + reset_reason_cast = RESET_REASON_SOFTWARE; + reset_reason_count ++; + } + } + + if (SYS_IS_CPU_RST()) { + reset_reason_cast = RESET_REASON_PLATFORM; + reset_reason_count ++; + } + + if (reset_reason_raw & SYS_RSTSTS_CPULKRF_Msk) { + reset_reason_cast = RESET_REASON_LOCKUP; + reset_reason_count ++; + } + + if (reset_reason_count == 0) { + reset_reason_cast = RESET_REASON_UNKNOWN; + } else if (reset_reason_count >= 2) { + reset_reason_cast = RESET_REASON_MULTIPLE; + } + + return reset_reason_cast; +} + +uint32_t hal_reset_reason_get_raw(void) +{ + return (SYS->RSTSTS & SYS_RSTSTS_ALLRF_Msk); +} + +void hal_reset_reason_clear(void) +{ + SYS_CLEAR_RST_SOURCE(SYS->RSTSTS); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M460/rtc_api.c new file mode 100644 index 0000000..f174dc9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/rtc_api.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "mbed_mktime.h" + +/* Not support LIRC-clocked RTC + * + * Though H/W supports this path, it is still not supported because: + * 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates. + * 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing. + */ +#if !MBED_CONF_TARGET_LXT_PRESENT +#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json" +#endif + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per second + * + * NOTE: This dependents on real hardware. + */ +#if MBED_CONF_TARGET_LXT_PRESENT +#define NU_RTCCLK_PER_SEC __LXT +#else +#define NU_RTCCLK_PER_SEC __LIRC +#endif + +/* Strategy for implementation of RTC HAL + * + * H/W RTC just supports year range 2000~2099, which cannot fully cover POSIX time (starting since 2970) + * and date time of struct TM (starting since 1900). + * + * To conquer the difficulty, we don't use H/W RTC to keep real date time. Instead, we use it to keep + * elapsed time in seconds since one reference time point. The strategy would be: + * + * 1. Choose DATETIME_HWRTC_ORIGIN (00:00:00 UTC, Saturday, 1 January 2000) as reference time point of H/W RTC. + * 2. t_hwrtc_origin = DATETIME_HWRTC_ORIGIN in POSIX time + * 3. t_hwrtc_elapsed = t_hwrtc_origin + elapsed time since t_hwrtc_origin + * 4. t_write = POSIX time set by rtc_write(). + * 5. t_present = rtc_read() = t_write + (t_hwrtc_elapsed - t_hwrtc_origin) + * + * 1900 + * |---------------------------------------------------------------------------------| + * 1970 t_write t_present + * |---------|-------|-----------------|---------------------------------------------| + * + * 2000 + * |-----------------|---------------------------------------------------------------| + * t_hwrtc_origin t_hwrtc_elapsed + * + */ +/* Start year of struct TM*/ +#define NU_TM_YEAR0 1900 +/* Start year of POSIX time (set_time()/time()) */ +#define NU_POSIX_YEAR0 1970 +/* Start year of H/W RTC */ +#define NU_HWRTC_YEAR0 2000 + +/* RTC H/W origin time: 00:00:00 UTC, Saturday, 1 January 2000 */ +static const S_RTC_TIME_DATA_T DATETIME_HWRTC_ORIGIN = { + 2000, /* Year value, range between 2000 ~ 2099 */ + 1, /* Month value, range between 1 ~ 12 */ + 1, /* Day value, range between 1 ~ 31 */ + RTC_SATURDAY, /* Day of the week */ + 0, /* Hour value, range between 0 ~ 23 */ + 0, /* Minute value, range between 0 ~ 59 */ + 0, /* Second value, range between 0 ~ 59 */ + RTC_CLOCK_24, /* 12-Hour (RTC_CLOCK_12) / 24-Hour (RTC_CLOCK_24) */ + 0 /* RTC_AM / RTC_PM (used only for 12-Hour) */ +}; +/* t_hwrtc_origin initialized or not? */ +static bool t_hwrtc_origin_inited = 0; +/* POSIX time of DATETIME_HWRTC_ORIGIN (since 00:00:00 UTC, Thursday, 1 January 1970) */ +static time_t t_hwrtc_origin = 0; +/* POSIX time set by rtc_write() */ +static time_t t_write = 0; +/* Convert date time from H/W RTC to struct TM */ +static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc); + +#if MBED_CONF_TARGET_LXT_PRESENT +static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, RTC_LXTCTL_RTCCKSEL_LXT, 0, 0, RTC_IRQn, NULL}; +#else +static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, RTC_LXTCTL_RTCCKSEL_LIRC, 0, 0, RTC_IRQn, NULL}; +#endif + +void rtc_init(void) +{ + if (rtc_isenabled()) { + return; + } + + RTC_Open(NULL); + + /* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */ + rtc_write(0); +} + +void rtc_free(void) +{ + CLK_DisableModuleClock(rtc_modinit.clkidx); +} + +int rtc_isenabled(void) +{ + // To access (RTC) registers, clock must be enabled first. + // For TZ, with RTC being secure, we needn't call the secure gateway versions. + CLK_EnableModuleClock(rtc_modinit.clkidx); + CLK_SetModuleClock(rtc_modinit.clkidx, rtc_modinit.clksrc, rtc_modinit.clkdiv); + + // NOTE: Check RTC Init Active flag to support crossing reset cycle. + return !! (RTC->INIT & RTC_INIT_ACTIVE_Msk); +} + +time_t rtc_read(void) +{ + /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency. + * RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect. + * NUC472/M453: Known issue + * M487: Fixed + */ + if (! rtc_isenabled()) { + rtc_init(); + } + + /* Used for intermediary between date time of H/W RTC and POSIX time */ + struct tm datetime_tm; + + if (! t_hwrtc_origin_inited) { + t_hwrtc_origin_inited = 1; + + /* Convert date time from H/W RTC to struct TM */ + rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &DATETIME_HWRTC_ORIGIN); + /* Convert date time of struct TM to POSIX time */ + if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) { + return 0; + } + + /* Load t_write from RTC spare register to cross reset cycle */ + RTC_WaitAccessEnable(); + RTC_EnableSpareAccess(); + RTC_WaitAccessEnable(); + t_write = RTC_READ_SPARE_REGISTER(0); + } + + S_RTC_TIME_DATA_T hwrtc_datetime_2K_present; + RTC_WaitAccessEnable(); + RTC_GetDateAndTime(&hwrtc_datetime_2K_present); + /* Convert date time from H/W RTC to struct TM */ + rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present); + /* Convert date time of struct TM to POSIX time */ + time_t t_hwrtc_elapsed; + if (! _rtc_maketime(&datetime_tm, &t_hwrtc_elapsed, RTC_FULL_LEAP_YEAR_SUPPORT)) { + return 0; + } + + /* Present time in POSIX time */ + time_t t_present = t_write + (t_hwrtc_elapsed - t_hwrtc_origin); + return t_present; +} + +void rtc_write(time_t t) +{ + if (! rtc_isenabled()) { + rtc_init(); + } + + t_write = t; + + /* Store t_write to RTC spare register to cross reset cycle */ + RTC_WaitAccessEnable(); + RTC_EnableSpareAccess(); + RTC_WaitAccessEnable(); + RTC_WRITE_SPARE_REGISTER(0, t_write); + + RTC_WaitAccessEnable(); + RTC_SetDateAndTime((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN); + /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ + wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3); +} + +/* + struct tm + tm_sec seconds after the minute 0-61 + tm_min minutes after the hour 0-59 + tm_hour hours since midnight 0-23 + tm_mday day of the month 1-31 + tm_mon months since January 0-11 + tm_year years since 1900 + tm_wday days since Sunday 0-6 + tm_yday days since January 1 0-365 + tm_isdst Daylight Saving Time flag +*/ +static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc) +{ + datetime_tm->tm_year = datetime_hwrtc->u32Year - NU_TM_YEAR0; + datetime_tm->tm_mon = datetime_hwrtc->u32Month - 1; + datetime_tm->tm_mday = datetime_hwrtc->u32Day; + datetime_tm->tm_wday = datetime_hwrtc->u32DayOfWeek; + datetime_tm->tm_hour = datetime_hwrtc->u32Hour; + if (datetime_hwrtc->u32TimeScale == RTC_CLOCK_12 && datetime_hwrtc->u32AmPm == RTC_PM) { + datetime_tm->tm_hour += 12; + } + datetime_tm->tm_min = datetime_hwrtc->u32Minute; + datetime_tm->tm_sec = datetime_hwrtc->u32Second; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M460/serial_api.c new file mode 100644 index 0000000..e86d607 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/serial_api.c @@ -0,0 +1,1353 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "mbed_error.h" +#include "mbed_assert.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include +#include + +#if DEVICE_SERIAL_ASYNCH +#include "dma_api.h" +#include "dma.h" +#endif + +struct nu_uart_var { + uint32_t ref_cnt; // Reference count of the H/W module + serial_t * obj; + uint32_t fifo_size_tx; + uint32_t fifo_size_rx; + void (*vec)(void); +#if DEVICE_SERIAL_ASYNCH + void (*vec_async)(void); + uint8_t pdma_perp_tx; + uint8_t pdma_perp_rx; +#endif +}; + +static void uart0_vec(void); +static void uart1_vec(void); +static void uart2_vec(void); +static void uart3_vec(void); +static void uart4_vec(void); +static void uart5_vec(void); +static void uart6_vec(void); +static void uart7_vec(void); +static void uart8_vec(void); +static void uart9_vec(void); +static void uart_irq(serial_t *obj); + +#if DEVICE_SERIAL_ASYNCH +static void uart0_vec_async(void); +static void uart1_vec_async(void); +static void uart2_vec_async(void); +static void uart3_vec_async(void); +static void uart4_vec_async(void); +static void uart5_vec_async(void); +static void uart6_vec_async(void); +static void uart7_vec_async(void); +static void uart8_vec_async(void); +static void uart9_vec_async(void); +static void uart_irq_async(serial_t *obj); + +static void uart_dma_handler_tx(uint32_t id, uint32_t event); +static void uart_dma_handler_rx(uint32_t id, uint32_t event); + +static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable); +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq); +static int serial_write_async(serial_t *obj); +static int serial_read_async(serial_t *obj); + +static uint32_t serial_rx_event_check(serial_t *obj); +static uint32_t serial_tx_event_check(serial_t *obj); + +static int serial_is_tx_complete(serial_t *obj); +static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable); + +static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width); +static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width); +static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match); +static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable); +static int serial_is_rx_complete(serial_t *obj); + +static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch); +#endif + +static int serial_is_irq_en(serial_t *obj, SerialIrq irq); + +bool serial_can_deep_sleep(void); + +static struct nu_uart_var uart0_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart0_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart0_vec_async, + .pdma_perp_tx = PDMA_UART0_TX, + .pdma_perp_rx = PDMA_UART0_RX +#endif +}; +static struct nu_uart_var uart1_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart1_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart1_vec_async, + .pdma_perp_tx = PDMA_UART1_TX, + .pdma_perp_rx = PDMA_UART1_RX +#endif +}; +static struct nu_uart_var uart2_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart2_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart2_vec_async, + .pdma_perp_tx = PDMA_UART2_TX, + .pdma_perp_rx = PDMA_UART2_RX +#endif +}; +static struct nu_uart_var uart3_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart3_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart3_vec_async, + .pdma_perp_tx = PDMA_UART3_TX, + .pdma_perp_rx = PDMA_UART3_RX +#endif +}; +static struct nu_uart_var uart4_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart4_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart4_vec_async, + .pdma_perp_tx = PDMA_UART4_TX, + .pdma_perp_rx = PDMA_UART4_RX +#endif +}; +static struct nu_uart_var uart5_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart5_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart5_vec_async, + .pdma_perp_tx = PDMA_UART5_TX, + .pdma_perp_rx = PDMA_UART5_RX +#endif +}; +static struct nu_uart_var uart6_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart6_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart6_vec_async, + .pdma_perp_tx = PDMA_UART6_TX, + .pdma_perp_rx = PDMA_UART6_RX +#endif +}; +static struct nu_uart_var uart7_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart7_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart7_vec_async, + .pdma_perp_tx = PDMA_UART7_TX, + .pdma_perp_rx = PDMA_UART7_RX +#endif +}; +static struct nu_uart_var uart8_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart8_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart8_vec_async, + .pdma_perp_tx = PDMA_UART8_TX, + .pdma_perp_rx = PDMA_UART8_RX +#endif +}; +static struct nu_uart_var uart9_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart9_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart9_vec_async, + .pdma_perp_tx = PDMA_UART9_TX, + .pdma_perp_rx = PDMA_UART9_RX +#endif +}; + +int stdio_uart_inited = 0; +serial_t stdio_uart; +static uint32_t uart_modinit_mask = 0; + +static const struct nu_modinit_s uart_modinit_tab[] = { + {UART_0, UART0_MODULE, CLK_CLKSEL1_UART0SEL_HIRC, CLK_CLKDIV0_UART0(1), UART0_RST, UART0_IRQn, &uart0_var}, + {UART_1, UART1_MODULE, CLK_CLKSEL1_UART1SEL_HIRC, CLK_CLKDIV0_UART1(1), UART1_RST, UART1_IRQn, &uart1_var}, + {UART_2, UART2_MODULE, CLK_CLKSEL3_UART2SEL_HIRC, CLK_CLKDIV4_UART2(1), UART2_RST, UART2_IRQn, &uart2_var}, + {UART_3, UART3_MODULE, CLK_CLKSEL3_UART3SEL_HIRC, CLK_CLKDIV4_UART3(1), UART3_RST, UART3_IRQn, &uart3_var}, + {UART_4, UART4_MODULE, CLK_CLKSEL3_UART4SEL_HIRC, CLK_CLKDIV4_UART4(1), UART4_RST, UART4_IRQn, &uart4_var}, + {UART_5, UART5_MODULE, CLK_CLKSEL3_UART5SEL_HIRC, CLK_CLKDIV4_UART5(1), UART5_RST, UART5_IRQn, &uart5_var}, + {UART_6, UART6_MODULE, CLK_CLKSEL3_UART6SEL_HIRC, CLK_CLKDIV4_UART6(1), UART6_RST, UART6_IRQn, &uart6_var}, + {UART_7, UART7_MODULE, CLK_CLKSEL3_UART7SEL_HIRC, CLK_CLKDIV4_UART7(1), UART7_RST, UART7_IRQn, &uart7_var}, + {UART_8, UART8_MODULE, CLK_CLKSEL2_UART8SEL_HIRC, CLK_CLKDIV5_UART8(1), UART8_RST, UART8_IRQn, &uart8_var}, + {UART_9, UART9_MODULE, CLK_CLKSEL2_UART9SEL_HIRC, CLK_CLKDIV5_UART9(1), UART9_RST, UART9_IRQn, &uart9_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +extern void mbed_sdk_init(void); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init(). + mbed_sdk_init(); + + // Determine which UART_x the pins are used for + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + // Get the peripheral name (UART_x) from the pins and assign it to the object + obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->serial.uart != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + obj->serial.pin_tx = tx; + obj->serial.pin_rx = rx; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (! var->ref_cnt) { + // Select IP clock source + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); + } + var->ref_cnt ++; + + obj->serial.vec = var->vec; + obj->serial.irq_en = 0; + +#if DEVICE_SERIAL_ASYNCH + obj->serial.dma_usage_tx = DMA_USAGE_NEVER; + obj->serial.dma_usage_rx = DMA_USAGE_NEVER; + obj->serial.event = 0; + obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; +#endif + + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); + stdio_uart_inited = 1; + } + + if (var->ref_cnt) { + // Mark this module to be inited. + int i = modinit - uart_modinit_tab; + uart_modinit_mask |= 1 << i; + } +} + +void serial_free(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + var->ref_cnt --; + if (! var->ref_cnt) { +#if DEVICE_SERIAL_ASYNCH + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.dma_chn_id_tx); + obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + } + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.dma_chn_id_rx); + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +#endif + + do { + UART_Close((UART_T *) NU_MODBASE(obj->serial.uart)); + + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + NVIC_DisableIRQ(modinit->irq_n); + + // Disable IP clock + CLK_DisableModuleClock(modinit->clkidx); + } while (0); + } + + if (var->obj == obj) { + var->obj = NULL; + } + + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); + stdio_uart_inited = 0; + } + + if (! var->ref_cnt) { + // Mark this module to be deinited. + int i = modinit - uart_modinit_tab; + uart_modinit_mask &= ~(1 << i); + } + + // Free up pins + gpio_set(obj->serial.pin_tx); + gpio_set(obj->serial.pin_rx); + gpio_set(obj->serial.pin_rts); + gpio_set(obj->serial.pin_cts); + obj->serial.pin_tx = NC; + obj->serial.pin_rx = NC; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + obj->serial.baudrate = baudrate; + UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + // Sanity check arguments + MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0)); + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + + obj->serial.databits = data_bits; + obj->serial.parity = parity; + obj->serial.stopbits = stop_bits; + + uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 : + (data_bits == 6) ? UART_WORD_LEN_6 : + (data_bits == 7) ? UART_WORD_LEN_7 : + UART_WORD_LEN_8; + uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD : + (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN : + UART_PARITY_NONE; + uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1; + UART_SetLineConfig((UART_T *) NU_MODBASE(obj->serial.uart), + 0, // Don't change baudrate + databits_intern, + parity_intern, + stopbits_intern); +} + +#if DEVICE_SERIAL_FC + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + // Free up old rts/cts pins when they are different from new ones + if (obj->serial.pin_rts != rxflow) { + gpio_set(obj->serial.pin_rts); + obj->serial.pin_rts = rxflow; + } + if (obj->serial.pin_cts != txflow) { + gpio_set(obj->serial.pin_cts); + obj->serial.pin_cts = txflow; + } + + if (rxflow != NC) { + // Check if RTS pin matches. + uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS); + MBED_ASSERT(uart_rts == obj->serial.uart); + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + + // NOTE: Added in M480. Before configuring RTSACTLV, disable TX/RX. + uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk; + while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk); + // nRTS pin output is low level active + uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk; + // NOTE: Added in M480. After configuring RTSACTLV, re-enable TX/RX. + uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk; + // Configure RTS trigger level to 8 bytes + uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES; + + if (type == FlowControlRTS || type == FlowControlRTSCTS) { + // Enable RTS + uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk; + } else { + // Disable RTS + uart_base->INTEN &= ~UART_INTEN_ATORTSEN_Msk; + /* Drive nRTS pin output to low-active. Allow the peer to be able to send data + * even though its CTS is still enabled. */ + uart_base->MODEM &= ~UART_MODEM_RTS_Msk; + } + } + + /* If CTS is disabled, we don't need to configure CTS. But to be consistent with + * RTS code above, we still configure CTS. */ + if (txflow != NC) { + // Check if CTS pin matches. + uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS); + MBED_ASSERT(uart_cts == obj->serial.uart); + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + + // NOTE: Added in M480. Before configuring CTSACTLV, disable TX/RX. + uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk; + while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk); + // nCTS pin input is low level active + uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + // NOTE: Added in M480. After configuring CTSACTLV, re-enable TX/RX. + uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk; + + if (type == FlowControlCTS || type == FlowControlRTSCTS) { + // Enable CTS + uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk; + } else { + // Disable CTS + uart_base->INTEN &= ~UART_INTEN_ATOCTSEN_Msk; + } + } +} + +#endif //DEVICE_SERIAL_FC + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + obj->serial.irq_handler = (uint32_t) handler; + obj->serial.irq_id = id; + + // Restore sync-mode vector + obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + obj->serial.irq_en = enable; + serial_enable_interrupt(obj, irq, enable); +} + +int serial_getc(serial_t *obj) +{ + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. + while (! serial_readable(obj)); + int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. + if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + + return c; +} + +void serial_putc(serial_t *obj, int c) +{ + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. + while (! serial_writable(obj)); + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c); + + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } +} + +int serial_readable(serial_t *obj) +{ + return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))); +} + +int serial_writable(serial_t *obj) +{ + return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart))); +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk; +} + +void serial_break_clear(serial_t *obj) +{ + ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk; +} + +static void uart0_vec(void) +{ + uart_irq(uart0_var.obj); +} + +static void uart1_vec(void) +{ + uart_irq(uart1_var.obj); +} + +static void uart2_vec(void) +{ + uart_irq(uart2_var.obj); +} + +static void uart3_vec(void) +{ + uart_irq(uart3_var.obj); +} + +static void uart4_vec(void) +{ + uart_irq(uart4_var.obj); +} + +static void uart5_vec(void) +{ + uart_irq(uart5_var.obj); +} + +static void uart6_vec(void) +{ + uart_irq(uart6_var.obj); +} + +static void uart7_vec(void) +{ + uart_irq(uart7_var.obj); +} + +static void uart8_vec(void) +{ + uart_irq(uart8_var.obj); +} + +static void uart9_vec(void) +{ + uart_irq(uart9_var.obj); +} + +static void uart_irq(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. + UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + if (obj->serial.irq_handler && serial_is_irq_en(obj, RxIrq)) { + // Call irq_handler() only when RxIrq is enabled + ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq); + } + } + + if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. + UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); + if (obj->serial.irq_handler && serial_is_irq_en(obj, TxIrq)) { + // Call irq_handler() only when TxIrq is enabled + ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq); + } + } + + // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt. + uart_base->INTSTS = uart_base->INTSTS; + uart_base->FIFOSTS = uart_base->FIFOSTS; +} + + +#if DEVICE_SERIAL_ASYNCH +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32); + + obj->serial.dma_usage_tx = hint; + serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx); + + // UART IRQ is necessary for both interrupt way and DMA way + serial_tx_enable_event(obj, event, 1); + serial_tx_buffer_set(obj, tx, tx_length, tx_width); + + int n_word = 0; + if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { + // Interrupt way + n_word = serial_write_async(obj); + serial_tx_enable_interrupt(obj, handler, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->serial.dma_chn_id_tx, + ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->serial.dma_chn_id_tx, + (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + tx_length); + PDMA_SetTransferAddr(pdma_base, + obj->serial.dma_chn_id_tx, + (uint32_t) tx, // NOTE: + // NUC472: End of source address + // M451: Start of source address + // M480: Start of source address + PDMA_SAR_INC, // Source address incremental + (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address + PDMA_DAR_FIX); // Destination address fixed + PDMA_SetBurstType(pdma_base, + obj->serial.dma_chn_id_tx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->serial.dma_chn_id_tx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); + serial_tx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer + } + + return n_word; +} + +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32); + + obj->serial.dma_usage_rx = hint; + serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx); + // DMA doesn't support char match, so fall back to IRQ if it is requested. + if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER && + (event & SERIAL_EVENT_RX_CHARACTER_MATCH) && + char_match != SERIAL_RESERVED_CHAR_MATCH) { + obj->serial.dma_usage_rx = DMA_USAGE_NEVER; + dma_channel_free(obj->serial.dma_chn_id_rx); + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } + + // UART IRQ is necessary for both interrupt way and DMA way + serial_rx_enable_event(obj, event, 1); + serial_rx_buffer_set(obj, rx, rx_length, rx_width); + serial_rx_set_char_match(obj, char_match); + + if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { + // Interrupt way + serial_rx_enable_interrupt(obj, handler, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->serial.dma_chn_id_rx, + ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->serial.dma_chn_id_rx, + (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + rx_length); + PDMA_SetTransferAddr(pdma_base, + obj->serial.dma_chn_id_rx, + (uint32_t) NU_MODBASE(obj->serial.uart), // Source address + PDMA_SAR_FIX, // Source address fixed + (uint32_t) rx, // NOTE: + // NUC472: End of destination address + // M451: Start of destination address + // M480: Start of destination address + PDMA_DAR_INC); // Destination address incremental + PDMA_SetBurstType(pdma_base, + obj->serial.dma_chn_id_rx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->serial.dma_chn_id_rx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); + serial_rx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer + } +} + +void serial_tx_abort_asynch(serial_t *obj) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); + } + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk); + } + + // Necessary for both interrupt way and DMA way + serial_enable_interrupt(obj, TxIrq, 0); + serial_rollback_interrupt(obj, TxIrq); +} + +void serial_rx_abort_asynch(serial_t *obj) +{ + if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); + } + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk); + } + + // Necessary for both interrupt way and DMA way + serial_enable_interrupt(obj, RxIrq, 0); + serial_rollback_interrupt(obj, RxIrq); +} + +uint8_t serial_tx_active(serial_t *obj) +{ + // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); +} + +uint8_t serial_rx_active(serial_t *obj) +{ + // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + int event_rx = 0; + int event_tx = 0; + + // Necessary for both interrupt way and DMA way + if (serial_is_irq_en(obj, RxIrq)) { + event_rx = serial_rx_event_check(obj); + if (event_rx) { + serial_rx_abort_asynch(obj); + } + } + + if (serial_is_irq_en(obj, TxIrq)) { + event_tx = serial_tx_event_check(obj); + if (event_tx) { + serial_tx_abort_asynch(obj); + } + } + + return (obj->serial.event & (event_rx | event_tx)); +} + +static void uart0_vec_async(void) +{ + uart_irq_async(uart0_var.obj); +} + +static void uart1_vec_async(void) +{ + uart_irq_async(uart1_var.obj); +} + +static void uart2_vec_async(void) +{ + uart_irq_async(uart2_var.obj); +} + +static void uart3_vec_async(void) +{ + uart_irq_async(uart3_var.obj); +} + +static void uart4_vec_async(void) +{ + uart_irq_async(uart4_var.obj); +} + +static void uart5_vec_async(void) +{ + uart_irq_async(uart5_var.obj); +} + +static void uart6_vec_async(void) +{ + uart_irq_async(uart6_var.obj); +} + +static void uart7_vec_async(void) +{ + uart_irq_async(uart7_var.obj); +} + +static void uart8_vec_async(void) +{ + uart_irq_async(uart8_var.obj); +} + +static void uart9_vec_async(void) +{ + uart_irq_async(uart9_var.obj); +} + +static void uart_irq_async(serial_t *obj) +{ + if (serial_is_irq_en(obj, RxIrq)) { + (*obj->serial.irq_handler_rx_async)(); + } + if (serial_is_irq_en(obj, TxIrq)) { + (*obj->serial.irq_handler_tx_async)(); + } +} + +static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match) +{ + obj->char_match = char_match; + obj->char_found = 0; +} + +static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) +{ + obj->serial.event &= ~SERIAL_EVENT_TX_MASK; + obj->serial.event |= (event & SERIAL_EVENT_TX_MASK); + + if (event & SERIAL_EVENT_TX_COMPLETE) { + // N/A + } +} + +static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) +{ + obj->serial.event &= ~SERIAL_EVENT_RX_MASK; + obj->serial.event |= (event & SERIAL_EVENT_RX_MASK); + + if (event & SERIAL_EVENT_RX_COMPLETE) { + // N/A + } + if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + // N/A + } + if (event & SERIAL_EVENT_RX_FRAMING_ERROR) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); + } + if (event & SERIAL_EVENT_RX_PARITY_ERROR) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); + } + if (event & SERIAL_EVENT_RX_OVERFLOW) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk); + } + if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) { + // N/A + } +} + +static int serial_is_tx_complete(serial_t *obj) +{ + // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way + return (obj->tx_buff.pos == obj->tx_buff.length); +} + +static int serial_is_rx_complete(serial_t *obj) +{ + return (obj->rx_buff.pos == obj->rx_buff.length); +} + +static uint32_t serial_tx_event_check(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. + UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); + } + + uint32_t event = 0; + + if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { + serial_write_async(obj); + } + + if (serial_is_tx_complete(obj)) { + event |= SERIAL_EVENT_TX_COMPLETE; + } + + return event; +} + +static uint32_t serial_rx_event_check(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. + UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + + uint32_t event = 0; + + if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk; + } + if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk; + event |= SERIAL_EVENT_RX_FRAMING_ERROR; + } + if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk; + event |= SERIAL_EVENT_RX_PARITY_ERROR; + } + + if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk; + event |= SERIAL_EVENT_RX_OVERFLOW; + } + + if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { + serial_read_async(obj); + } + + if (serial_is_rx_complete(obj)) { + event |= SERIAL_EVENT_RX_COMPLETE; + } + if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) { + event |= SERIAL_EVENT_RX_CHARACTER_MATCH; + } + + return event; +} + +static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma) +{ + serial_t *obj = (serial_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect UART IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->tx_buff.pos = obj->tx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + uart_irq_async(obj); +} + +static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma) +{ + serial_t *obj = (serial_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect UART IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->rx_buff.pos = obj->rx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + uart_irq_async(obj); +} + +static int serial_write_async(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx; + uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos; + if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) { + tx_fifo_busy = tx_fifo_max; + } + uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy; + if (tx_fifo_free == 0) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } + return 0; + } + + uint32_t bytes_per_word = obj->tx_buff.width / 8; + + uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; + int n_words = 0; + while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) { + switch (bytes_per_word) { + case 4: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + case 2: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + case 1: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + } + + n_words ++; + tx_fifo_free -= bytes_per_word; + obj->tx_buff.pos ++; + } + + if (n_words) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } + } + + return n_words; +} + +static int serial_read_async(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos; + + uint32_t bytes_per_word = obj->rx_buff.width / 8; + + uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; + int n_words = 0; + while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) { + switch (bytes_per_word) { + case 4: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + case 2: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + case 1: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + } + + n_words ++; + rx_fifo_busy -= bytes_per_word; + obj->rx_buff.pos ++; + + if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) && + obj->char_match != SERIAL_RESERVED_CHAR_MATCH) { + uint8_t *rx_cmp = rx; + switch (bytes_per_word) { + case 4: + rx_cmp -= 2; + case 2: + rx_cmp --; + case 1: + rx_cmp --; + } + if (*rx_cmp == obj->char_match) { + obj->char_found = 1; + break; + } + } + } + + if (n_words) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + } + + return n_words; +} + +static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = width; +} + +static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width) +{ + obj->rx_buff.buffer = rx; + obj->rx_buff.length = length; + obj->rx_buff.pos = 0; + obj->rx_buff.width = width; +} + +static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + // Necessary for both interrupt way and DMA way + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // With our own async vector, tx/rx handlers can be different. + obj->serial.vec = var->vec_async; + obj->serial.irq_handler_tx_async = (void (*)(void)) handler; + serial_enable_interrupt(obj, TxIrq, enable); +} + +static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + // Necessary for both interrupt way and DMA way + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // With our own async vector, tx/rx handlers can be different. + obj->serial.vec = var->vec_async; + obj->serial.irq_handler_rx_async = (void (*) (void)) handler; + serial_enable_interrupt(obj, RxIrq, enable); +} + +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if (enable) { + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); + NVIC_EnableIRQ(modinit->irq_n); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // Multiple serial S/W objects for single UART H/W module possibly. + // Bind serial S/W object to UART H/W module as interrupt is enabled. + var->obj = obj; + + switch (irq) { + // NOTE: Setting inten_msk first to avoid race condition + case RxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + break; + case TxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + break; + } + } else { // disable + switch (irq) { + case RxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; + break; + } + } +} + +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + obj->serial.vec = var->vec; + serial_enable_interrupt(obj, irq, obj->serial.irq_en); +} + +static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) +{ + if (*dma_usage != DMA_USAGE_NEVER) { + if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch = dma_channel_allocate(DMA_CAP_NONE); + } + if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_usage = DMA_USAGE_NEVER; + } + } else { + dma_channel_free(*dma_ch); + *dma_ch = DMA_ERROR_OUT_OF_CHANNELS; + } +} + +#endif // #if DEVICE_SERIAL_ASYNCH + +static int serial_is_irq_en(serial_t *obj, SerialIrq irq) +{ + int inten_msk = 0; + + switch (irq) { + case RxIrq: + inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk; + break; + } + + return !! inten_msk; +} + +bool serial_can_deep_sleep(void) +{ + bool sleep_allowed = 1; + const struct nu_modinit_s *modinit = uart_modinit_tab; + while (modinit->var != NULL) { + struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var; + UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); + if (uart_var->ref_cnt > 0) { + if (!UART_IS_TX_EMPTY(uart_base)) { + sleep_allowed = 0; + break; + } + } + modinit++; + } + return sleep_allowed; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} + +#endif // #if DEVICE_SERIAL diff --git a/targets/TARGET_NUVOTON/TARGET_M460/sleep.c b/targets/TARGET_NUVOTON/TARGET_M460/sleep.c new file mode 100644 index 0000000..881a55e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/sleep.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "sleep_api.h" + +#if DEVICE_SLEEP + +#include "cmsis.h" +#include "device.h" +#include "objects.h" +#include "PeripheralPins.h" +#include + +#if DEVICE_SERIAL +bool serial_can_deep_sleep(void); +#endif + +/** + * Enter idle mode, in which just CPU is halted. + */ +void hal_sleep(void) +{ + SYS_UnlockReg(); + CLK_Idle(); + SYS_LockReg(); +} + +/** + * Enter power-down mode, in which HXT/HIRC are halted. + */ +void hal_deepsleep(void) +{ +#if DEVICE_SERIAL + if (!serial_can_deep_sleep()) { + return; + } +#endif + + SYS_UnlockReg(); + CLK_PowerDown(); + SYS_LockReg(); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M460/spi_api.c new file mode 100644 index 0000000..c9f7d48 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/spi_api.c @@ -0,0 +1,1003 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" + +#if DEVICE_SPI_ASYNCH +#include "dma_api.h" +#include "dma.h" +#endif + +#define NU_SPI_FRAME_MIN 8 +#define NU_SPI_FRAME_MAX 32 + +struct nu_spi_var { +#if DEVICE_SPI_ASYNCH + uint8_t pdma_perp_tx; + uint8_t pdma_perp_rx; +#endif +}; + +static struct nu_spi_var spi0_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI0_TX, + .pdma_perp_rx = PDMA_SPI0_RX +#endif +}; +static struct nu_spi_var spi1_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI1_TX, + .pdma_perp_rx = PDMA_SPI1_RX +#endif +}; +static struct nu_spi_var spi2_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI2_TX, + .pdma_perp_rx = PDMA_SPI2_RX +#endif +}; +static struct nu_spi_var spi3_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI3_TX, + .pdma_perp_rx = PDMA_SPI3_RX +#endif +}; +static struct nu_spi_var spi4_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI4_TX, + .pdma_perp_rx = PDMA_SPI4_RX +#endif +}; +static struct nu_spi_var spi5_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI5_TX, + .pdma_perp_rx = PDMA_SPI5_RX +#endif +}; +static struct nu_spi_var spi6_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI6_TX, + .pdma_perp_rx = PDMA_SPI6_RX +#endif +}; +static struct nu_spi_var spi7_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI7_TX, + .pdma_perp_rx = PDMA_SPI7_RX +#endif +}; +static struct nu_spi_var spi8_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI8_TX, + .pdma_perp_rx = PDMA_SPI8_RX +#endif +}; +static struct nu_spi_var spi9_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI9_TX, + .pdma_perp_rx = PDMA_SPI9_RX +#endif +}; +static struct nu_spi_var spi10_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI10_TX, + .pdma_perp_rx = PDMA_SPI10_RX +#endif +}; +/* Degrade QSPI0/1 to SPI_11/12 for standard SPI usage */ +static struct nu_spi_var spi11_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_QSPI0_TX, + .pdma_perp_rx = PDMA_QSPI0_RX +#endif +}; +static struct nu_spi_var spi12_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_QSPI1_TX, + .pdma_perp_rx = PDMA_QSPI1_RX +#endif +}; + +/* Change to QSPI version functions + * + * In most cases, we can control degraded QSPI H/W to standard through BSP SPI driver + * directly as if it is just SPI H/W. However, BSP SPI driver distinguishes among + * SPI H/W instances in below functions: + * + * SPI_Open + * SPI_Close + * SPI_SetBusClock + * SPI_GetBusClock + * + * In these cases, we must change to QSPI version instead for QSPI H/W. + */ +static int spi_is_qspi(spi_t *obj); + +/* Synchronous version of SPI_ENABLE()/SPI_DISABLE() macros + * + * The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI + * control logic is enabled/disabled, this bit indicates the real status of SPI controller. + * + * NOTE: All configurations shall be ready before calling SPI_ENABLE_SYNC(). + * NOTE: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, + * user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0 + * (by SPI_DISABLE_SYNC here). + */ +__STATIC_INLINE void SPI_ENABLE_SYNC(SPI_T *spi_base) +{ + if (! (spi_base->CTL & SPI_CTL_SPIEN_Msk)) { + SPI_ENABLE(spi_base); + } + while (! (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk)); +} +__STATIC_INLINE void SPI_DISABLE_SYNC(SPI_T *spi_base) +{ + if (spi_base->CTL & SPI_CTL_SPIEN_Msk) { + // NOTE: SPI H/W may get out of state without the busy check. + while (SPI_IS_BUSY(spi_base)); + + SPI_DISABLE(spi_base); + } + while (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk); +} + +#if DEVICE_SPI_ASYNCH +static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable); +static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable); +static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit); +static uint32_t spi_master_read_asynch(spi_t *obj); +static uint32_t spi_event_check(spi_t *obj); +static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable); +static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length); +static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx); +static uint8_t spi_get_data_width(spi_t *obj); +static int spi_is_tx_complete(spi_t *obj); +static int spi_is_rx_complete(spi_t *obj); +static int spi_writeable(spi_t * obj); +static int spi_readable(spi_t * obj); +static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma); +static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma); +static uint32_t spi_fifo_depth(spi_t *obj); +#endif + +static uint32_t spi_modinit_mask = 0; + +static const struct nu_modinit_s spi_modinit_tab[] = { + {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var}, + {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK0, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var}, + {SPI_2, SPI2_MODULE, CLK_CLKSEL3_SPI2SEL_PCLK1, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var}, + {SPI_3, SPI3_MODULE, CLK_CLKSEL3_SPI3SEL_PCLK0, MODULE_NoMsk, SPI3_RST, SPI3_IRQn, &spi3_var}, + {SPI_4, SPI4_MODULE, CLK_CLKSEL4_SPI4SEL_PCLK1, MODULE_NoMsk, SPI4_RST, SPI4_IRQn, &spi4_var}, + {SPI_5, SPI5_MODULE, CLK_CLKSEL4_SPI5SEL_PCLK0, MODULE_NoMsk, SPI5_RST, SPI5_IRQn, &spi5_var}, + {SPI_6, SPI6_MODULE, CLK_CLKSEL4_SPI6SEL_PCLK1, MODULE_NoMsk, SPI6_RST, SPI6_IRQn, &spi6_var}, + {SPI_7, SPI7_MODULE, CLK_CLKSEL4_SPI7SEL_PCLK0, MODULE_NoMsk, SPI7_RST, SPI7_IRQn, &spi7_var}, + {SPI_8, SPI8_MODULE, CLK_CLKSEL4_SPI8SEL_PCLK1, MODULE_NoMsk, SPI8_RST, SPI8_IRQn, &spi8_var}, + {SPI_9, SPI9_MODULE, CLK_CLKSEL4_SPI9SEL_PCLK0, MODULE_NoMsk, SPI9_RST, SPI9_IRQn, &spi9_var}, + {SPI_10, SPI10_MODULE, CLK_CLKSEL4_SPI10SEL_PCLK1, MODULE_NoMsk, SPI10_RST, SPI10_IRQn, &spi10_var}, + /* Degrade QSPI0/1 to SPI_11/12 for standard SPI usage */ + {SPI_11, QSPI0_MODULE, CLK_CLKSEL2_QSPI0SEL_PCLK0, MODULE_NoMsk, QSPI0_RST, QSPI0_IRQn, &spi11_var}, + {SPI_12, QSPI1_MODULE, CLK_CLKSEL2_QSPI1SEL_PCLK1, MODULE_NoMsk, QSPI1_RST, QSPI1_IRQn, &spi12_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Determine which SPI_x the pins are used for + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi.spi != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + obj->spi.pin_mosi = mosi; + obj->spi.pin_miso = miso; + obj->spi.pin_sclk = sclk; + obj->spi.pin_ssel = ssel; + + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); + + // Select IP clock source + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + +#if DEVICE_SPI_ASYNCH + obj->spi.dma_usage = DMA_USAGE_NEVER; + obj->spi.event = 0; + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + + /* NOTE: We use vector to judge if asynchronous transfer is on-going (spi_active). + * At initial time, asynchronous transfer is not on-going and so vector must + * be cleared to zero for correct judgement. */ + NVIC_SetVector(modinit->irq_n, 0); +#endif + + // Mark this module to be inited. + int i = modinit - spi_modinit_tab; + spi_modinit_mask |= 1 << i; +} + +void spi_free(spi_t *obj) +{ +#if DEVICE_SPI_ASYNCH + if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.dma_chn_id_tx); + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + } + if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.dma_chn_id_rx); + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +#endif + + if (spi_is_qspi(obj)) { + QSPI_Close((QSPI_T *) NU_MODBASE(obj->spi.spi)); + } else { + SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi)); + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK)); + NVIC_DisableIRQ(modinit->irq_n); + + // Disable IP clock + CLK_DisableModuleClock(modinit->clkidx); + + // Mark this module to be deinited. + int i = modinit - spi_modinit_tab; + spi_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->spi.pin_mosi); + gpio_set(obj->spi.pin_miso); + gpio_set(obj->spi.pin_sclk); + gpio_set(obj->spi.pin_ssel); + obj->spi.pin_mosi = NC; + obj->spi.pin_miso = NC; + obj->spi.pin_sclk = NC; + obj->spi.pin_ssel = NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX); + + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_DISABLE_SYNC(spi_base); + + if (spi_is_qspi(obj)) { + QSPI_Open((QSPI_T *) spi_base, + slave ? QSPI_SLAVE : QSPI_MASTER, + (mode == 0) ? QSPI_MODE_0 : (mode == 1) ? QSPI_MODE_1 : (mode == 2) ? QSPI_MODE_2 : QSPI_MODE_3, + bits, + QSPI_GetBusClock((QSPI_T *)spi_base)); + } else { + SPI_Open(spi_base, + slave ? SPI_SLAVE : SPI_MASTER, + (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3, + bits, + SPI_GetBusClock(spi_base)); + } + // NOTE: Hardcode to be MSB first. + SPI_SET_MSB_FIRST(spi_base); + + if (! slave) { + // Master + if (obj->spi.pin_ssel != NC) { + // Configure SS as low active. + SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW); + } else { + SPI_DisableAutoSS(spi_base); + } + } else { + // Slave + // Configure SS as low active. + spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk; + } + + /* NOTE: M451's/M480's/M2351's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). + * We cannot use SPI_CTL_SPIEN_Msk for judgement of spi_active(). + * Judge with vector instead. */ +} + +void spi_frequency(spi_t *obj, int hz) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_DISABLE_SYNC(spi_base); + + if (spi_is_qspi(obj)) { + QSPI_SetBusClock((QSPI_T *) NU_MODBASE(obj->spi.spi), hz); + } else { + SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz); + } +} + + +int spi_master_write(spi_t *obj, int value) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + PinName spi_miso = obj->spi.pin_miso; + + SPI_ENABLE_SYNC(spi_base); + + /* Wait for TX FIFO not full */ + while(! spi_writeable(obj)); + SPI_WRITE_TX(spi_base, value); + + /* Make inter-frame (SPI data frame) delay match configured suspend interval + * in no MISO case + * + * This API requires data write/read simultaneously. However, it can enlarge + * the inter-frame delay. The data flow for one call of this API would be: + * 1. Write data to TX FIFO when it is not full + * 2. Write delay consisting of TX FIFO to TX Shift Register... + * 3. Actual data transfer on SPI bus + * 4. Read delay consisting of RX FIFO from RX Shift Register... + * 5. Read data from RX FIFO when it is not empty + * Among above, S2&S4 contribute to the inter-frame delay. + * + * To favor no MISO case, we skip S4&S5. Thus, S2 can overlap with S3 and doesn't + * contribute to the inter-frame delay when data is written successively. The solution + * can cause RX FIFO overrun. Ignore it. + */ + int value2 = -1; + if (spi_miso != NC) { + /* Wait for RX FIFO not empty */ + while (! spi_readable(obj)); + value2 = SPI_READ_RX(spi_base); + } + + /* We don't call SPI_DISABLE_SYNC here for performance. */ + + return value2; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) { + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#if DEVICE_SPISLAVE +int spi_slave_receive(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + return spi_readable(obj); +}; + +int spi_slave_read(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + // Wait for rx buffer full + while (! spi_readable(obj)); + int value = SPI_READ_RX(spi_base); + return value; +} + +void spi_slave_write(spi_t *obj, int value) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + // Wait for tx buffer empty + while(! spi_writeable(obj)); + SPI_WRITE_TX(spi_base, value); +} +#endif + +#if DEVICE_SPI_ASYNCH +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + SPI_SET_DATA_WIDTH(spi_base, bit_width); + + obj->spi.dma_usage = hint; + spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx); + uint32_t data_width = spi_get_data_width(obj); + // Conditions to go DMA way: + // (1) No DMA support for non-8 multiple data width. + // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx. + if ((data_width % 8) || + (tx_length < rx_length)) { + obj->spi.dma_usage = DMA_USAGE_NEVER; + dma_channel_free(obj->spi.dma_chn_id_tx); + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + dma_channel_free(obj->spi.dma_chn_id_rx); + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } + + // SPI IRQ is necessary for both interrupt way and DMA way + spi_enable_event(obj, event, 1); + spi_buffer_set(obj, tx, tx_length, rx, rx_length); + + SPI_ENABLE_SYNC(spi_base); + + // Initialize total SPI transfer frames + obj->spi.txrx_rmn = NU_MAX(tx_length, rx_length); + + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + // Interrupt way + spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2); + spi_enable_vector_interrupt(obj, handler, 1); + spi_master_enable_interrupt(obj, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + PDMA_T *pdma_base = dma_modbase(); + + // Configure tx DMA + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->spi.dma_chn_id_tx, + ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->spi.dma_chn_id_tx, + (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + tx_length); + PDMA_SetTransferAddr(pdma_base, + obj->spi.dma_chn_id_tx, + (uint32_t) tx, // NOTE: + // NUC472: End of source address + // M451/M480: Start of source address + PDMA_SAR_INC, // Source address incremental + (uint32_t) &spi_base->TX, // Destination address + PDMA_DAR_FIX); // Destination address fixed + PDMA_SetBurstType(pdma_base, + obj->spi.dma_chn_id_tx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->spi.dma_chn_id_tx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); + + // Configure rx DMA + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->spi.dma_chn_id_rx, + ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->spi.dma_chn_id_rx, + (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + rx_length); + PDMA_SetTransferAddr(pdma_base, + obj->spi.dma_chn_id_rx, + (uint32_t) &spi_base->RX, // Source address + PDMA_SAR_FIX, // Source address fixed + (uint32_t) rx, // NOTE: + // NUC472: End of destination address + // M451/M480: Start of destination address + PDMA_DAR_INC); // Destination address incremental + PDMA_SetBurstType(pdma_base, + obj->spi.dma_chn_id_rx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->spi.dma_chn_id_rx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); + + /* Start tx/rx DMA transfer + * + * If we have both PDMA and SPI interrupts enabled and PDMA priority is lower than SPI priority, + * we would trap in SPI interrupt handler endlessly with the sequence: + * + * 1. PDMA TX transfer done interrupt occurs and is well handled. + * 2. SPI RX FIFO threshold interrupt occurs. Trap here because PDMA RX transfer done interrupt doesn't get handled. + * 3. PDMA RX transfer done interrupt occurs but it cannot be handled due to above. + * + * To fix it, we don't enable SPI TX/RX threshold interrupts but keep SPI vector handler set to be called + * in PDMA TX/RX transfer done interrupt handlers (spi_dma_handler_tx/spi_dma_handler_rx). + */ + NVIC_SetVector(modinit->irq_n, handler); + + /* Order to enable PDMA TX/RX functions + * + * H/W spec: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are + * enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable + * TX PDMA function firstly or enable both functions simultaneously. + * Per real test, it is safer to start RX PDMA first and then TX PDMA. Otherwise, receive FIFO is + * subject to overflow by TX DMA. + * + * With the above conflicts, we enable PDMA TX/RX functions simultaneously. + */ + spi_base->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk); + + /* Don't enable SPI TX/RX threshold interrupts as commented above */ + } +} + +/** + * Abort an SPI transfer + * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing + * transfers + * @param[in] obj The SPI peripheral to stop + */ +void spi_abort_asynch(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + PDMA_T *pdma_base = dma_modbase(); + + if (obj->spi.dma_usage != DMA_USAGE_NEVER) { + // Receive FIFO Overrun in case of tx length > rx length on DMA way + if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; + } + + if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); + } + SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); + + if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); + } + SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); + } + + // Necessary for both interrupt way and DMA way + spi_enable_vector_interrupt(obj, 0, 0); + spi_master_enable_interrupt(obj, 0); + + /* Necessary for accessing FIFOCTL below */ + SPI_DISABLE_SYNC(spi_base); + + SPI_ClearRxFIFO(spi_base); + SPI_ClearTxFIFO(spi_base); +} + +/** + * Handle the SPI interrupt + * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way, + * it is unlikely that the RX FIFO will overflow. + * @param[in] obj The SPI peripheral that generated the interrupt + * @return + */ +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + // Check for SPI events + uint32_t event = spi_event_check(obj); + if (event) { + spi_abort_asynch(obj); + } + + return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0); +} + +uint8_t spi_active(spi_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + /* Vector will be cleared when asynchronous transfer is finished or aborted. + Use it to judge if asynchronous transfer is on-going. */ + uint32_t vec = NVIC_GetVector(modinit->irq_n); + return vec ? 1 : 0; +} + +static int spi_is_qspi(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + return (spi_base == ((SPI_T *) QSPI0) || spi_base == ((SPI_T *) QSPI1)); +} + +static int spi_writeable(spi_t * obj) +{ + // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive + return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))); +} + +static int spi_readable(spi_t * obj) +{ + return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))); +} + +static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) +{ + obj->spi.event &= ~SPI_EVENT_ALL; + obj->spi.event |= (event & SPI_EVENT_ALL); + if (event & SPI_EVENT_RX_OVERFLOW) { + SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK); + } +} + +static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + if (enable) { + NVIC_SetVector(modinit->irq_n, handler); + NVIC_EnableIRQ(modinit->irq_n); + } else { + NVIC_DisableIRQ(modinit->irq_n); + NVIC_SetVector(modinit->irq_n, 0); + } +} + +static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + if (enable) { + uint32_t fifo_depth = spi_fifo_depth(obj); + SPI_SetFIFO(spi_base, fifo_depth / 2, fifo_depth / 2); + // Enable tx/rx FIFO threshold interrupt + SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); + } else { + SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); + } +} + +static uint32_t spi_event_check(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + uint32_t event = 0; + + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + uint32_t n_rec = spi_master_read_asynch(obj); + spi_master_write_asynch(obj, n_rec); + } + + if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) { + event |= SPI_EVENT_COMPLETE; + } + + // Receive FIFO Overrun + if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; + // In case of tx length > rx length on DMA way + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + event |= SPI_EVENT_RX_OVERFLOW; + } + } + + // Receive Time-Out + if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXTOIF_Msk; + // Not using this IF. Just clear it. + } + // Transmit FIFO Under-Run + if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) { + spi_base->STATUS = SPI_STATUS_TXUFIF_Msk; + event |= SPI_EVENT_ERROR; + } + + return event; +} + +/** + * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full + * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed. + * @param[in] obj The SPI object on which to operate + * @param[in] tx_limit The maximum number of words to send + * @return The number of SPI words that have been transfered + */ +static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) +{ + uint32_t n_words = 0; + uint8_t data_width = spi_get_data_width(obj); + uint8_t bytes_per_word = (data_width + 7) / 8; + uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + while (obj->spi.txrx_rmn && spi_writeable(obj)) { + if (spi_is_tx_complete(obj)) { + // Transmit dummy as transmit buffer is empty + SPI_WRITE_TX(spi_base, 0); + } else { + switch (bytes_per_word) { + case 4: + SPI_WRITE_TX(spi_base, nu_get32_le(tx)); + tx += 4; + break; + case 2: + SPI_WRITE_TX(spi_base, nu_get16_le(tx)); + tx += 2; + break; + case 1: + SPI_WRITE_TX(spi_base, *((uint8_t *) tx)); + tx += 1; + break; + } + + obj->tx_buff.pos ++; + } + n_words ++; + obj->spi.txrx_rmn --; + } + + //Return the number of words that have been sent + return n_words; +} + +/** + * Read SPI words out of the RX FIFO + * Continues reading words out of the RX FIFO until the following condition is met: + * o There are no more words in the FIFO + * OR BOTH OF: + * o At least as many words as the TX buffer have been received + * o At least as many words as the RX buffer have been received + * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size + * @param[in] obj The SPI object on which to operate + * @return Returns the number of words extracted from the RX FIFO + */ +static uint32_t spi_master_read_asynch(spi_t *obj) +{ + uint32_t n_words = 0; + uint8_t data_width = spi_get_data_width(obj); + uint8_t bytes_per_word = (data_width + 7) / 8; + uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + while (spi_readable(obj)) { + if (spi_is_rx_complete(obj)) { + // Disregard as receive buffer is full + SPI_READ_RX(spi_base); + } else { + switch (bytes_per_word) { + case 4: { + uint32_t val = SPI_READ_RX(spi_base); + nu_set32_le(rx, val); + rx += 4; + break; + } + case 2: { + uint16_t val = SPI_READ_RX(spi_base); + nu_set16_le(rx, val); + rx += 2; + break; + } + case 1: + *rx ++ = SPI_READ_RX(spi_base); + break; + } + + obj->rx_buff.pos ++; + } + n_words ++; + } + + // Return the number of words received + return n_words; +} + +static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = spi_get_data_width(obj); + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + obj->rx_buff.width = spi_get_data_width(obj); +} + +static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx) +{ + if (*dma_usage != DMA_USAGE_NEVER) { + if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE); + } + if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE); + } + + if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_usage = DMA_USAGE_NEVER; + } + } + + if (*dma_usage == DMA_USAGE_NEVER) { + dma_channel_free(*dma_ch_tx); + *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS; + dma_channel_free(*dma_ch_rx); + *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +} + +static uint8_t spi_get_data_width(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos); + if (data_width == 0) { + data_width = 32; + } + + return data_width; +} + +static int spi_is_tx_complete(spi_t *obj) +{ + return (obj->tx_buff.pos == obj->tx_buff.length); +} + +static int spi_is_rx_complete(spi_t *obj) +{ + return (obj->rx_buff.pos == obj->rx_buff.length); +} + +static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma) +{ + spi_t *obj = (spi_t *) id; + + // TODO: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect SPI IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->tx_buff.pos = obj->tx_buff.length; + } + // TODO: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); + vec(); +} + +static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma) +{ + spi_t *obj = (spi_t *) id; + + // TODO: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect SPI IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->rx_buff.pos = obj->rx_buff.length; + } + // TODO: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); + vec(); +} + +/* Return FIFO depth of the SPI peripheral + * + * M480 + * QSPI0/1 8 + * SPI0/1/2/3 8 if data width <=16; 4 otherwise + */ +static uint32_t spi_fifo_depth(spi_t *obj) +{ + if (spi_is_qspi(obj)) { + return 8; + } + + return (spi_get_data_width(obj) <= 16) ? 8 : 4; +} + +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/trng_api.cpp b/targets/TARGET_NUVOTON/TARGET_M460/trng_api.cpp new file mode 100644 index 0000000..2083c74 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/trng_api.cpp @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if DEVICE_TRNG + +#include "cmsis.h" +#include +//#include "crypto-misc.h" +#include "hal/trng_api.h" +#include "platform/mbed_toolchain.h" +#include "platform/mbed_critical.h" +#include "platform/mbed_error.h" +#include "nu_modutil.h" + +/* Module init definition: modname, clkidx, clksrc, clkdiv, rstidx, irqnum, misc */ +static const struct nu_modinit_s trng_modinit = {TRNG_0, TRNG_MODULE, 0, 0, TRNG_RST, TRNG_IRQn, NULL}; + +/* TRNG init counter. TRNG is kept active as it is non-zero. */ +static uint16_t trng_init_counter = 0U; + +void trng_init(MBED_UNUSED trng_t *obj) +{ + core_util_critical_section_enter(); + if (trng_init_counter == USHRT_MAX) { + core_util_critical_section_exit(); + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_OVERFLOW), \ + "TRNG initialization counter would overflow"); + } + ++ trng_init_counter; + if (trng_init_counter == 1) { + /* Enable IP clock */ + CLK_EnableModuleClock(trng_modinit.clkidx); + + /* Reset IP */ + SYS_ResetModule(trng_modinit.rsetidx); + +#if MBED_CONF_TARGET_LXT_PRESENT + /* Clock source from (external) LXT */ + CLK->CLKSEL2 &= ~CLK_CLKSEL2_TRNGSEL_Msk; + CLK->CLKSEL2 |= CLK_CLKSEL2_TRNGSEL_LXT; +#else + /* Clock source from (internal) LIRC */ + CLK->CLKSEL2 &= ~CLK_CLKSEL2_TRNGSEL_Msk; + CLK->CLKSEL2 |= CLK_CLKSEL2_TRNGSEL_LIRC; +#endif + + TRNG_T *trng_base = (TRNG_T *) NU_MODBASE(trng_modinit.modname); + + /* TRNG_ACT.ACT is enable bit of analog part. */ + trng_base->ACT |= TRNG_ACT_ACT_Msk; + while (!(trng_base->CTL & TRNG_CTL_READY_Msk)); + + /* TRNG_CTL.TRNGEN is enable bit of digital part. */ + trng_base->CTL |= TRNG_CTL_TRNGEN_Msk; + } + core_util_critical_section_exit(); +} + +void trng_free(MBED_UNUSED trng_t *obj) +{ + core_util_critical_section_enter(); + if (trng_init_counter == 0) { + core_util_critical_section_exit(); + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_UNDERFLOW), \ + "TRNG initialization counter would underflow"); + } + -- trng_init_counter; + if (trng_init_counter == 0) { + TRNG_T *trng_base = (TRNG_T *) NU_MODBASE(trng_modinit.modname); + + /* When TRNG is not required to generate random number, TRNG_CTL.TRNGEN + * and TRNG_ACT.ACT should be set to 0 to reduce power consumption. */ + trng_base->CTL &= ~TRNG_CTL_TRNGEN_Msk; + trng_base->ACT &= ~TRNG_ACT_ACT_Msk; + + /* Disable IP clock */ + CLK_DisableModuleClock(trng_modinit.clkidx); + } + core_util_critical_section_exit(); +} + +int trng_get_bytes(MBED_UNUSED trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + /* Check augument validity */ + if (!output && length) { + return -1; + } + + uint8_t *output_ind = output; + uint8_t *output_end = output + length; + + TRNG_T *trng_base = (TRNG_T *) NU_MODBASE(trng_modinit.modname); + + for (; output_ind != output_end; output_ind ++) { + while (!(trng_base->CTL & TRNG_CTL_DVIF_Msk)); + *output_ind = trng_base->DATA & 0xff; + } + + if (output_length) { + *output_length = length; + } + + return 0; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M460/us_ticker.c new file mode 100644 index 0000000..f228d22 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/us_ticker.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "us_ticker_api.h" + +#if DEVICE_USTICKER + +#include "sleep_api.h" +#include "mbed_assert.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per us_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#define NU_TMRCLK_PER_SEC (1000 * 1000) +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) + +static void tmr0_vec(void); + +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; + +#define TIMER_MODINIT timer0_modinit + +/* Track ticker status */ +static volatile uint16_t ticker_inited = 0; + +#define TMR_CMP_MIN 2 +#define TMR_CMP_MAX 0xFFFFFFu + +void us_ticker_init(void) +{ + if (ticker_inited) { + /* By HAL spec, ticker_init allows the ticker to keep counting and disables the + * ticker interrupt. */ + us_ticker_disable_interrupt(); + return; + } + ticker_inited = 1; + + // Select IP clock source + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + // Enable IP clock + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + + // Reset IP + SYS_ResetModule(TIMER_MODINIT.rsetidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + // Timer for normal counter + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + timer_base->CMP = cmp_timer; + + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + + TIMER_Start(timer_base); + /* Wait for timer to start counting and raise active flag */ + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); +} + +void us_ticker_free(void) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + /* Disable IP clock */ + CLK_DisableModuleClock(TIMER_MODINIT.clkidx); + + ticker_inited = 0; +} + +uint32_t us_ticker_read() +{ + if (! ticker_inited) { + us_ticker_init(); + } + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + /* Clear any previously pending interrupts */ + us_ticker_clear_interrupt(); + NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n); + + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +void us_ticker_disable_interrupt(void) +{ + /* We cannot call ticker_irq_handler now. */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); +} + +void us_ticker_clear_interrupt(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); +} + +void us_ticker_fire_interrupt(void) +{ + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +static void tmr0_vec(void) +{ + us_ticker_clear_interrupt(); + + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M460/watchdog_api.c b/targets/TARGET_NUVOTON/TARGET_M460/watchdog_api.c new file mode 100644 index 0000000..8903875 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M460/watchdog_api.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2022, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "watchdog_api.h" + +#if DEVICE_WATCHDOG + +#include "cmsis.h" + +/* Watchdog clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT +#define NU_WDTCLK_PER_SEC (__LXT) +#define NU_WDTCLK_PER_SEC_MAX (__LXT) +#define NU_WDTCLK_PER_SEC_MIN (__LXT) +#else +#define NU_WDTCLK_PER_SEC (__LIRC) +#define NU_WDTCLK_PER_SEC_MAX ((uint32_t) ((__LIRC) * 2.0f)) +#define NU_WDTCLK_PER_SEC_MIN ((uint32_t) ((__LIRC) * 0.5f)) +#endif + +/* Convert watchdog clock to nearest ms */ +#define NU_WDTCLK2MS(WDTCLK) (((WDTCLK) * 1000 + ((NU_WDTCLK_PER_SEC) / 2)) / (NU_WDTCLK_PER_SEC)) + +/* Convert ms to nearest watchdog clock */ +#define NU_MS2WDTCLK(MS) (((MS) * (NU_WDTCLK_PER_SEC) + 500) / 1000) + +/* List of hardware-supported watchdog timeout in clocks */ +#define NU_WDT_16CLK 16 +#define NU_WDT_64CLK 64 +#define NU_WDT_256CLK 256 +#define NU_WDT_1024CLK 1024 +#define NU_WDT_4096CLK 4096 +#define NU_WDT_16384CLK 16384 +#define NU_WDT_65536CLK 65536 +#define NU_WDT_262144CLK 262144 + +/* Watchdog reset delay + * + * 1. Cannot be too small. This is to avoid premature WDT reset in pieces of timeout cascading. + * 2. Cannot be too large. This is to pass Greentea reset_reason/watchdog_reset tests, which have e.g. 50~100 reset delay tolerance. + */ +#define NU_WDT_RESET_DELAY_RSTDSEL WDT_RESET_DELAY_130CLK + +/* Support watchdog timeout values beyond H/W + * + * Watchdog Timer H/W just supports timeout values of 2^4, 2^6, ..., 2^18 clocks. + * To extend the support range to 1 and UINT32_MAX, we cascade multiple small timeouts to + * reach one large timeout specified in hal_watchdog_init. + */ + +/* Track if WDT H/W has been initialized */ +static bool wdt_hw_inited = 0; +/* Hold initially-configured timeout in hal_watchdog_init */ +static uint32_t wdt_timeout_reload_ms = 0; +/* Track remaining timeout for cascading */ +static uint32_t wdt_timeout_rmn_clk = 0; + +static void watchdog_setup_cascade_timeout(void); +static void WDT_IRQHandler(void); + +watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) +{ + /* Check validity of arguments */ + if (! config || ! config->timeout_ms) { + return WATCHDOG_STATUS_INVALID_ARGUMENT; + } + + wdt_timeout_reload_ms = config->timeout_ms; + wdt_timeout_rmn_clk = NU_MS2WDTCLK(wdt_timeout_reload_ms); + + if (! wdt_hw_inited) { + wdt_hw_inited = 1; + + SYS_UnlockReg(); + + /* Enable IP module clock */ + CLK_EnableModuleClock(WDT_MODULE); + + /* Select IP clock source */ +#if MBED_CONF_TARGET_LXT_PRESENT + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, 0); +#else + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); +#endif + + SYS_LockReg(); + + /* Set up IP interrupt */ + NVIC_SetVector(WDT_IRQn, (uint32_t) WDT_IRQHandler); + NVIC_EnableIRQ(WDT_IRQn); + } + + watchdog_setup_cascade_timeout(); + + return WATCHDOG_STATUS_OK; +} + +void hal_watchdog_kick(void) +{ + /* If a watchdog is not running, this function does nothing */ + if (!(WDT->CTL & WDT_CTL_WDTEN_Msk)) { + return; + } + + wdt_timeout_rmn_clk = NU_MS2WDTCLK(wdt_timeout_reload_ms); + watchdog_setup_cascade_timeout(); +} + +watchdog_status_t hal_watchdog_stop(void) +{ + SYS_UnlockReg(); + + /* Clear all flags & Disable interrupt & Disable WDT */ + WDT->CTL = (WDT->CTL & ~(WDT_CTL_WDTEN_Msk | WDT_CTL_INTEN_Msk)) | (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + + SYS_LockReg(); + + return WATCHDOG_STATUS_OK; +} + +uint32_t hal_watchdog_get_reload_value(void) +{ + return wdt_timeout_reload_ms; +} + +watchdog_features_t hal_watchdog_get_platform_features(void) +{ + watchdog_features_t wdt_feat; + + /* We can support timeout values between 1 and UINT32_MAX by cascading. */ + wdt_feat.max_timeout = UINT32_MAX; + /* Support re-configuring watchdog timer */ + wdt_feat.update_config = 1; + /* Support stopping watchdog timer */ + wdt_feat.disable_watchdog = 1; + /* Typical frequency of not calibrated watchdog clock in Hz */ + wdt_feat.clock_typical_frequency = NU_WDTCLK_PER_SEC; + /* Maximum frequency of not calibrated watchdog clock in Hz */ + wdt_feat.clock_max_frequency = NU_WDTCLK_PER_SEC_MAX; + + return wdt_feat; +} + +static void watchdog_setup_cascade_timeout(void) +{ + uint32_t wdt_timeout_clk_toutsel; + + if (wdt_timeout_rmn_clk >= NU_WDT_262144CLK) { + wdt_timeout_rmn_clk -= NU_WDT_262144CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW18; + } else if (wdt_timeout_rmn_clk >= NU_WDT_65536CLK) { + wdt_timeout_rmn_clk -= NU_WDT_65536CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW16; + } else if (wdt_timeout_rmn_clk >= NU_WDT_16384CLK) { + wdt_timeout_rmn_clk -= NU_WDT_16384CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW14; + } else if (wdt_timeout_rmn_clk >= NU_WDT_4096CLK) { + wdt_timeout_rmn_clk -= NU_WDT_4096CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW12; + } else if (wdt_timeout_rmn_clk >= NU_WDT_1024CLK) { + wdt_timeout_rmn_clk -= NU_WDT_1024CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW10; + } else if (wdt_timeout_rmn_clk >= NU_WDT_256CLK) { + wdt_timeout_rmn_clk -= NU_WDT_256CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW8; + } else if (wdt_timeout_rmn_clk >= NU_WDT_64CLK) { + wdt_timeout_rmn_clk -= NU_WDT_64CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW6; + } else if (wdt_timeout_rmn_clk >= NU_WDT_16CLK) { + wdt_timeout_rmn_clk -= NU_WDT_16CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW4; + } else if (wdt_timeout_rmn_clk) { + wdt_timeout_rmn_clk = 0; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW4; + } else { + /* WDT has timed-out and will restart system soon. We just disable interrupt to escape + * getting stuck in WDT ISR. */ + SYS_UnlockReg(); + + /* Clear all flags & Disable interrupt */ + WDT->CTL = (WDT->CTL & ~WDT_CTL_INTEN_Msk) | (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + + SYS_LockReg(); + return; + } + + SYS_UnlockReg(); + + /* Configure reset delay on timeout */ + WDT->ALTCTL = NU_WDT_RESET_DELAY_RSTDSEL; + + /* Configure another piece of cascaded WDT timeout */ + WDT->CTL = wdt_timeout_clk_toutsel | // Timeout interval + WDT_CTL_WDTEN_Msk | // Enable watchdog timer + WDT_CTL_INTEN_Msk | // Enable interrupt + WDT_CTL_WKF_Msk | // Clear wake-up flag + WDT_CTL_WKEN_Msk | // Enable wake-up on timeout + WDT_CTL_IF_Msk | // Clear interrupt flag + WDT_CTL_RSTF_Msk | // Clear reset flag + WDT_CTL_RSTEN_Msk; // Enable reset always to address cascaded timeout failure in interrupt disabled scenario e.g. Hard Fault + WDT_RESET_COUNTER(); // Reset watchdog timer + + SYS_LockReg(); +} + +void WDT_IRQHandler(void) +{ + /* Check WDT interrupt flag */ + if (WDT_GET_TIMEOUT_INT_FLAG()) { + /* Continue another piece of cascaded WDT timeout */ + watchdog_setup_cascade_timeout(); + } else { + /* Clear all flags */ + WDT->CTL |= (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + } +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c index 66dae37..8fa211e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c @@ -432,13 +432,13 @@ case 0x08: // Start case 0x10: // Master Repeat Start if (i2c_ctl & I2C_CTL0_STA_Msk) { - return 0; + goto cleanup; } else { break; } case 0xF8: // Bus Released if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) { - return 0; + goto cleanup; } else { break; } @@ -449,6 +449,8 @@ } } +cleanup: + i2c_enable_int(obj); return err; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c index bf26483..72aa9cd 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c @@ -468,14 +468,14 @@ case 0x08: // Start case 0x10: // Master Repeat Start if (i2c_ctl & I2C_CON_START_Msk) { - return 0; + goto cleanup; } else { break; } case 0xF8: // Bus Released if ((i2c_ctl & (I2C_CON_START_Msk | I2C_CON_STOP_Msk)) == I2C_CON_STOP_Msk) { - return 0; + goto cleanup; } else { break; @@ -492,8 +492,10 @@ } } +cleanup: + i2c_enable_int(obj); - + return err; } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c index f9e2b96..e88835c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c @@ -465,14 +465,14 @@ case 0x08: // Start case 0x10: // Master Repeat Start if (i2c_ctl & I2C_CTL_STA_Msk) { - return 0; + goto cleanup; } else { break; } case 0xF8: // Bus Released if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) { - return 0; + goto cleanup; } else { break; @@ -489,8 +489,10 @@ } } +cleanup: + i2c_enable_int(obj); - + return err; } diff --git a/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.cpp b/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.cpp index 02d96d1..f057247 100644 --- a/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.cpp +++ b/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.cpp @@ -24,9 +24,9 @@ #if defined (TARGET_M451) #undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD #define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 0 /* USB 1.1 Only */ -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined(TARGET_M460) #define USBD_SET_ADDRESS 0x05ul -#elif defined (TARGET_M2351) || defined(TARGET_M261) +#elif defined (TARGET_M2351) || defined(TARGET_M261) || defined(TARGET_M2354) #undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD #define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 0 /* USB 1.1 Only */ #define USBD_SET_ADDRESS 0x05ul @@ -43,8 +43,12 @@ extern "C" void USBD_IRQHandler(void); +//#define NVT_USB_Debug(x) { mbed_error_printf x;} +#define NVT_USB_Debug(x) + void chip_config(void) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); #if defined(TARGET_M451) /* Enable USBD module clock */ CLK_EnableModuleClock(USBD_MODULE); @@ -67,7 +71,7 @@ /* Enable IP clock */ CLK_EnableModuleClock(USBD_MODULE); - + /* Configure pins for USB 1.1 port: VBUS/D+/D-/ID */ pin_function(PA_12, SYS_GPA_MFPH_PA12MFP_USB_VBUS); pin_function(PA_13, SYS_GPA_MFPH_PA13MFP_USB_D_N); @@ -100,7 +104,22 @@ /* USBD multi-function pins for VBUS, D+, D-, and ID pins */ SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA12MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA15MFP_Msk); SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA12MFP_USB_VBUS | SYS_GPA_MFPH_PA13MFP_USB_D_N | SYS_GPA_MFPH_PA14MFP_USB_D_P | SYS_GPA_MFPH_PA15MFP_USB_OTG_ID); +#elif defined (TARGET_M2354) + /* To select USBD in TF-M image secure domain */ + //SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk; + + /* Enable IP clock */ + CLK_EnableModuleClock_S(USBD_MODULE); + + /* Select IP clock source */ + CLK_SetModuleClock_S(USBD_MODULE, CLK_CLKSEL0_USBSEL_HIRC48, CLK_CLKDIV0_USB(1)); + + /* USBD multi-function pins for VBUS, D+, D-, and ID pins */ + nu_pin_function_s(0, 12, SYS_GPA_MFPH_PA12MFP_USB_VBUS); + nu_pin_function_s(0, 13, SYS_GPA_MFPH_PA13MFP_USB_D_N); + nu_pin_function_s(0, 14, SYS_GPA_MFPH_PA14MFP_USB_D_P); + nu_pin_function_s(0, 15, SYS_GPA_MFPH_PA15MFP_USB_OTG_ID); #elif defined (TARGET_NANO100) @@ -117,6 +136,51 @@ /* Enable USB PHY's LDO33. Run as USB device. */ SYS->USBPHY = SYS_USBPHY_USBROLE_OTG_V33_EN | SYS_USBPHY_USBROLE_STD_USBD; +#elif defined(TARGET_M460) +#if (MBED_CONF_TARGET_USB_DEVICE_HSUSBD == 0) + #if MBED_CONF_TARGET_HXT_PRESENT /* CLK src from HXT/PLL */ + /* Enable HXT clock */ + //CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); + /* Wait for HXT clock ready */ + //CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + /* Select USB clock source as PLL/2 and USB clock divider as 2 */ + CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USBSEL_PLL_DIV2, CLK_CLKDIV0_USB(2)); + #else /* For CRYSTAL_LESS */ + /* Enable HIRC48M clock */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRC48MEN_Msk); + /* Waiting for HIRC48M clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRC48MSTB_Msk); + /* Select USB clock source as HIRC48M and USB clock divider as 1 */ + CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USBSEL_HIRC48M, CLK_CLKDIV0_USB(1)); + #endif + + /* Configure USB to Device mode */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_USBROLE_STD_USBD; + + /* Enable USB PHY */ + SYS->USBPHY |= SYS_USBPHY_USBEN_Msk | SYS_USBPHY_SBO_Msk; + + /* Enable IP clock */ + CLK_EnableModuleClock(USBD_MODULE); + + /* Configure pins for USB 1.1 port: VBUS/D+/D-/ID */ + SET_USB_VBUS_PA12(); + SET_USB_D_N_PA13(); + SET_USB_D_P_PA14(); + SET_USB_OTG_ID_PA15(); +#else + /* Configure HSUSB to Device mode */ + SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_HSUSBROLE_Msk) | SYS_USBPHY_HSUSBROLE_STD_USBD; + /* Enable HSUSB PHY */ + SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBEN_Msk | SYS_USBPHY_HSUSBACT_Msk)) | SYS_USBPHY_HSUSBEN_Msk; + /* Delay >10 us and then switch HSUSB PHY from reset state to active state */ + wait_us(10); + SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk; + + /* Enable USBD module clock */ + CLK_EnableModuleClock(HSUSBD_MODULE); +#endif + #endif } @@ -129,7 +193,7 @@ #define HW_TO_DESC(endpoint) (endpoint|(((endpoint&1)?0x0:0x80))) /* Global variables for Control Pipe */ -#if defined(TARGET_M2351) || defined(TARGET_M261) +#if defined(TARGET_M2351) || defined(TARGET_M261) || defined(TARGET_M2354) extern uint8_t g_USBD_au8SetupPacket[]; /*!< Setup packet buffer */ uint8_t* g_usbd_SetupPacket=g_USBD_au8SetupPacket; #else @@ -161,6 +225,7 @@ USBPhy *get_usb_phy() { static USBPhyHw usbphy; + NVT_USB_Debug(("### %s\n", __FUNCTION__)); return &usbphy; } @@ -180,13 +245,17 @@ */ void USBPhyHw::init(USBPhyEvents *events) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); if (this->events == NULL) { sleep_manager_lock_deep_sleep(); } this->events = events; - +#if defined(TARGET_M2354) + wait_us(10); /* To init us_ticker to avoid invoking NSC for us_ticker, it could keep wait_us safe from ISR Context */ + SYS_UnlockReg_S(); +#else SYS_UnlockReg(); - +#endif s_ep_buf_ind = 0; chip_config(); @@ -209,6 +278,7 @@ void USBPhyHw::deinit() { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); NVIC_DisableIRQ(USBD_IRQn); USBD_SET_SE0(); USBD_DISABLE_PHY(); @@ -233,7 +303,8 @@ void USBPhyHw::connect() { - int volatile i = 0; + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); + memset(read_buffers, 0, sizeof(read_buffers)); memset(read_sizes, 0, sizeof(read_sizes)); @@ -255,6 +326,7 @@ void USBPhyHw::disconnect() { uint32_t volatile i = 0; + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); #if 1 #if defined (TARGET_NANO100) SYS->IPRST_CTL2 = SYS_IPRST_CTL2_USBD_RST_Msk; @@ -301,7 +373,7 @@ void EpInit(void) { uint32_t volatile i = 0; - + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); #if defined (TARGET_NANO100) USBD->BUFSEG = 0; #else @@ -437,6 +509,7 @@ */ uint32_t USBPhyHw::ep0_read_result() { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t i; uint8_t *buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1)); uint8_t *buffer = read_buffers[0]; @@ -457,8 +530,10 @@ /* Write a packet on endpoint 0. */ void USBPhyHw::ep0_write(uint8_t *buffer, uint32_t size) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); if (buffer && size) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); if(s_ep_data_bit[0] & 1) USBD_SET_DATA1(EP0); else @@ -471,6 +546,7 @@ } else { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); s_ep_data_bit[0] = 1; USBD_SET_DATA1(EP0); wait_us(500); @@ -483,6 +559,7 @@ void stallEndpoint(uint8_t endpoint) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t ep_logic_index = DESC_TO_LOG(endpoint); if (ep_logic_index >= NUMBER_OF_LOGICAL_ENDPOINTS) return; @@ -496,6 +573,7 @@ */ void USBPhyHw::ep0_stall() { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); stallEndpoint(0); stallEndpoint(1); } @@ -509,6 +587,7 @@ */ bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t ep_type = 0; uint32_t ep_logic_index = DESC_TO_LOG(endpoint); uint32_t ep_hw_index = NU_EPL2EPH(ep_logic_index); @@ -539,6 +618,7 @@ */ void USBPhyHw::endpoint_stall(usb_ep_t endpoint) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); USBD_SetStall(DESC_TO_LOG(endpoint)); } @@ -548,6 +628,7 @@ */ void USBPhyHw::endpoint_unstall(usb_ep_t endpoint) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t ep_logic_index = DESC_TO_LOG(endpoint); uint32_t ep_hw_index = NU_EPL2EPH(ep_logic_index); if (ep_logic_index >= NUMBER_OF_LOGICAL_ENDPOINTS) @@ -561,6 +642,7 @@ /* Start a read on the given endpoint. */ bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); /* Store the buffer address & length */ uint32_t ep_logic_index = DESC_TO_LOG(endpoint); uint32_t ep_hw_index = NU_EPL2EPH(ep_logic_index); @@ -576,6 +658,7 @@ */ uint32_t USBPhyHw::endpoint_read_result(usb_ep_t endpoint) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint8_t ep_logic_index = DESC_TO_LOG(endpoint); uint32_t bytes_read = 0; endpoint_read_result_core(endpoint, read_buffers[ep_logic_index], read_sizes[ep_logic_index], &bytes_read); @@ -586,6 +669,7 @@ bool USBPhyHw::endpoint_read_result_core(usb_ep_t endpoint, uint8_t *data, uint32_t size, uint32_t *bytes_read) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t i; uint8_t ep_logic_index = DESC_TO_LOG(endpoint); uint32_t ep_hw_index = NU_EPL2EPH(ep_logic_index); @@ -603,6 +687,7 @@ */ bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t ep_logic_index = DESC_TO_LOG(endpoint); uint32_t ep_hw_index = NU_EPL2EPH(ep_logic_index); @@ -631,6 +716,7 @@ /* Abort the current transfer if it has not yet been sent. */ void USBPhyHw::endpoint_abort(usb_ep_t endpoint) { + NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t ep_logic_index = DESC_TO_LOG(endpoint); uint32_t ep_hw_index = NU_EPL2EPH(ep_logic_index); USBD_STOP_TRANSACTION(ep_hw_index); @@ -644,6 +730,7 @@ */ void USBPhyHw::process() { +// NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); uint32_t u32IntSts = USBD_GET_INT_FLAG(); uint32_t u32State = USBD_GET_BUS_STATE(); @@ -741,7 +828,7 @@ /* Control IN */ events->ep0_in(); /* In ACK for Set address */ -#if defined(TARGET_M480) || defined(TARGET_M451) +#if defined(TARGET_M480) || defined(TARGET_M451) || defined(TARGET_M460) if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == USBD_SET_ADDRESS)) #else if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS)) @@ -776,7 +863,7 @@ ep_status = (USBD->EPSTS >> (ep_hw_index * 4 + 8)) & 0xF; else ep_status = (USBD->EPSTS2 >> ((ep_hw_index - 6) * 4)) & 0x7; -#elif defined(TARGET_M480) || defined(TARGET_M2351) || defined(TARGET_M261) +#elif defined(TARGET_M480) || defined(TARGET_M2351) || defined(TARGET_M261) || defined(TARGET_M460) || defined(TARGET_M2354) if(ep_hw_index < 8) ep_status = (USBD->EPSTS0 >> (ep_hw_index * 4)) & 0xF; else @@ -808,6 +895,7 @@ extern "C" void USBD_IRQHandler(void) { +// NVT_USB_Debug(("### %s[%d]\n", __FUNCTION__, __LINE__)); instance->events->start_process(); } #else @@ -823,7 +911,7 @@ #define EP_DIR_OUT 0x00 #define EP_DIR_IN 0x80 -#if defined (TARGET_M480) +#if defined (TARGET_M480) || defined (TARGET_M460) #define HSUSBD_GET_EP_MAX_PAYLOAD(ep) HSUSBD->EP[ep].EPMPS #define HSUSBD_GET_EP_DATA_COUNT(ep) (HSUSBD->EP[ep].EPDATCNT & 0xFFFFF) #define HSUSBD_SET_EP_SHORT_PACKET(ep) HSUSBD->EP[ep].EPRSPCTL = ((HSUSBD->EP[ep].EPRSPCTL & 0x10) | 0x40) @@ -843,7 +931,7 @@ static volatile uint32_t s_ep0_max_packet_size = 64; static volatile uint8_t s_usb_addr = 0; -#if defined (TARGET_M480) +#if defined (TARGET_M480) || defined (TARGET_M460) static volatile S_HSUSBD_CMD_T s_setup; #elif defined (TARGET_NUC472) static volatile S_USBD_CMD_T s_setup; @@ -879,7 +967,7 @@ g_usb_CtrlInSize = 0; } } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) void HSUSBD_CtrlInput(void) { unsigned volatile i; @@ -954,7 +1042,7 @@ NVIC_SetVector(USBD_IRQn, (uint32_t) &USBD_IRQHandler); NVIC_EnableIRQ(USBD_IRQn); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_ENABLE_PHY(); while (1) @@ -985,7 +1073,7 @@ USBD_SET_SE0(); USBD_DISABLE_PHY(); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) NVIC_DisableIRQ(USBD20_IRQn); @@ -1043,7 +1131,7 @@ /* Clear SE0 (connect) */ USBD_CLR_SE0(); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_ResetDMA(); HSUSBD_SET_ADDR(0); @@ -1081,7 +1169,7 @@ /* Set SE0 (disconnect) */ #if defined (TARGET_NUC472) USBD_SET_SE0(); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SET_SE0(); #endif } @@ -1107,7 +1195,7 @@ { #if defined (TARGET_NUC472) USBD->BUSINTEN |= USBD_BUSINTEN_SOFIEN_Msk; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD->BUSINTEN |= HSUSBD_BUSINTEN_SOFIEN_Msk; #endif } @@ -1117,7 +1205,7 @@ { #if defined (TARGET_NUC472) USBD->BUSINTEN &= ~USBD_BUSINTEN_SOFIEN_Msk; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD->BUSINTEN &= ~HSUSBD_BUSINTEN_SOFIEN_Msk; #endif } @@ -1133,7 +1221,7 @@ { #if defined (TARGET_NUC472) USBD->OPER |= USBD_OPER_RESUMEEN_Msk; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD->OPER |= HSUSBD_OPER_RESUMEEN_Msk; #endif } @@ -1190,7 +1278,7 @@ s_setup.wValue = (uint16_t) USBD->SETUP3_2; s_setup.wIndex = (uint16_t) USBD->SETUP5_4; s_setup.wLength = (uint16_t) USBD->SETUP7_6; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) *((uint16_t *) (buffer + 0)) = (uint16_t) HSUSBD->SETUP1_0; *((uint16_t *) (buffer + 2)) = (uint16_t) HSUSBD->SETUP3_2; *((uint16_t *) (buffer + 4)) = (uint16_t) HSUSBD->SETUP5_4; @@ -1224,7 +1312,7 @@ USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR); USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk|USBD_CEPINTEN_INTKIEN_Msk); } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if (s_setup.wLength && ! (s_setup.bmRequestType & 0x80)) { /* Control OUT */ @@ -1256,7 +1344,7 @@ for (i = 0; i < ceprxcnt; i ++) ep0_data[i] = USBD->CEPDAT_BYTE; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) uint32_t ceprxcnt = HSUSBD->CEPRXCNT; for (i = 0; i < ceprxcnt; i ++) @@ -1283,7 +1371,7 @@ USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR); USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk); } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if (buffer && size) { g_usbd_CtrlInPointer = buffer; @@ -1308,7 +1396,7 @@ return; #if defined (TARGET_NUC472) USBD_SetStall(ep_hw_index); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SetStall(ep_hw_index); #endif } @@ -1321,7 +1409,7 @@ { #if defined (TARGET_NUC472) USBD_SetStall(0); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SetStall(0); #endif } @@ -1367,7 +1455,7 @@ if (ep_dir != 0) USBD_ENABLE_EP_INT(ep_hw_index, USBD_EPINTEN_TXPKIEN_Msk); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SetEpBufAddr(ep_hw_index, s_ep_buf_ind, max_packet); s_ep_buf_ind += max_packet; HSUSBD_SET_MAX_PAYLOAD(ep_hw_index, max_packet); @@ -1402,7 +1490,7 @@ uint32_t ep_hw_index = NU_EPL2EPH(DESC_TO_LOG(endpoint)); #if defined (TARGET_NUC472) *((__IO uint32_t *) ((uint32_t)&USBD->EPACFG + (uint32_t)(ep_hw_index*0x28))) = (*((__IO uint32_t *)((uint32_t)&USBD->EPACFG+(uint32_t)(ep_hw_index*0x28))) & ~USB_EP_CFG_VALID); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD->EP[ep_hw_index].EPCFG = HSUSBD->EP[ep_hw_index].EPCFG & ~HSUSBD_EP_CFG_VALID; #endif } @@ -1420,7 +1508,7 @@ USBD_SetStall(0); else USBD_SetStall(ep_logic_index); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if(ep_logic_index == 0) HSUSBD_SetEpStall(CEP); else @@ -1439,7 +1527,7 @@ #if defined (TARGET_NUC472) if(ep_logic_index != 0) USBD_ClearStall(ep_logic_index); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if(ep_logic_index != 0) HSUSBD_ClearEpStall(ep_hw_index); #endif @@ -1455,7 +1543,7 @@ read_sizes[ep_logic_index] = size; #if defined (TARGET_NUC472) USBD_ENABLE_EP_INT(ep_hw_index, USBD_GET_EP_INT_EN(ep_hw_index) | USBD_EPINTEN_RXPKIEN_Msk); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD->EP[ep_hw_index].EPINTEN |= HSUSBD_EPINTEN_RXPKIEN_Msk; #endif return true; @@ -1485,7 +1573,7 @@ uint32_t mps = USBD_GET_EP_MAX_PAYLOAD(ep_hw_index); gEpReadCnt = USBD_GET_EP_DATA_COUNT(ep_hw_index); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) uint32_t mps = HSUSBD_GET_EP_MAX_PAYLOAD(ep_hw_index); gEpReadCnt = HSUSBD_GET_EP_DATA_COUNT(ep_hw_index); @@ -1512,7 +1600,7 @@ break; else if (!USBD_IS_ATTACHED()) break; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if (!(HSUSBD->DMACTL & HSUSBD_DMACTL_DMAEN_Msk)) break; else if (!HSUSBD_IS_ATTACHED()) @@ -1524,7 +1612,7 @@ USBD_SET_DMA_ADDR((uint32_t)tmp_buffer); USBD_SET_DMA_WRITE(ep_logic_index); USBD_ENABLE_DMA(); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SET_DMA_LEN(len); HSUSBD_SET_DMA_ADDR((uint32_t)tmp_buffer); HSUSBD_SET_DMA_WRITE(ep_logic_index); @@ -1538,7 +1626,7 @@ break; else if (!USBD_IS_ATTACHED()) break; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if (!(HSUSBD->DMACTL & HSUSBD_DMACTL_DMAEN_Msk)) break; else if (!HSUSBD_IS_ATTACHED()) @@ -1568,7 +1656,7 @@ else if (!USBD_IS_ATTACHED()) break; } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SET_DMA_LEN(len); HSUSBD_SET_DMA_ADDR(buffer); HSUSBD_SET_DMA_WRITE(ep_logic_index); @@ -1603,7 +1691,7 @@ { #if defined (TARGET_NUC472) uint32_t mps = USBD_GET_EP_MAX_PAYLOAD(ep_hw_index); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) uint32_t mps = HSUSBD_GET_EP_MAX_PAYLOAD(ep_hw_index); #endif @@ -1617,7 +1705,7 @@ USBD_SET_EP_SHORT_PACKET(ep_hw_index); return false; } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if(HSUSBD->EP[ep_hw_index].EPDATCNT & 0xFFFF) { HSUSBD_SET_EP_SHORT_PACKET(ep_hw_index); @@ -1635,7 +1723,7 @@ break; else if (!USBD_IS_ATTACHED()) break; -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if (!(HSUSBD->DMACTL & HSUSBD_DMACTL_DMAEN_Msk)) break; else if (!HSUSBD_IS_ATTACHED()) @@ -1664,7 +1752,7 @@ else if (!USBD_IS_ATTACHED()) break; } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SET_DMA_LEN(len); HSUSBD_SET_DMA_ADDR((uint32_t)tmp_buffer); HSUSBD_SET_DMA_READ(ep_logic_index); @@ -1697,7 +1785,7 @@ else if (!USBD_IS_ATTACHED()) break; } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD_SET_DMA_LEN(len); HSUSBD_SET_DMA_ADDR((uint32_t)buffer); HSUSBD_SET_DMA_READ(ep_logic_index); @@ -1716,7 +1804,7 @@ if(g_usb_ShortPacket) USBD_SET_EP_SHORT_PACKET(ep_hw_index); USBD_ENABLE_EP_INT(ep_hw_index, USBD_GET_EP_INT_EN(ep_hw_index) | USBD_EPINTEN_TXPKIEN_Msk); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) if(g_usb_ShortPacket) HSUSBD_SET_EP_SHORT_PACKET(ep_hw_index); HSUSBD->EP[ep_hw_index].EPINTEN |= HSUSBD_EPINTEN_TXPKIEN_Msk; @@ -1734,7 +1822,7 @@ USBD_CLR_EP_INT(ep_hw_index, USBD_GET_EP_INT(ep_hw_index)); USBD_ENABLE_EP_INT(ep_hw_index, 0); USBD_SET_EP_BUF_FLUSH(ep_hw_index); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) HSUSBD->EP[ep_hw_index].EPINTEN = 0; HSUSBD->EP[ep_hw_index].EPINTSTS = HSUSBD->EP[ep_hw_index].EPINTSTS; HSUSBD->EP[ep_hw_index].EPRSPCTL = HSUSBD_EPRSPCTL_FLUSH_Msk; @@ -2045,7 +2133,7 @@ gintsts_epx = gintsts_epx >> 1; ep_hw_index++; } -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) uint32_t gintsts = HSUSBD->GINTSTS & HSUSBD->GINTEN; uint32_t gintsts_epx = gintsts >> 2; /* EPA, EPB, EPC, ... EPL interrupts */ uint32_t ep_hw_index = 0; @@ -2366,7 +2454,7 @@ NVIC_ClearPendingIRQ(USBD_IRQn); NVIC_EnableIRQ(USBD_IRQn); -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined (TARGET_M460) NVIC_DisableIRQ(USBD20_IRQn); instance->events->start_process(); diff --git a/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.h b/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.h index 9412a06..21966b5 100644 --- a/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.h +++ b/targets/TARGET_NUVOTON/USBEndpoints_Nuvoton.h @@ -18,7 +18,7 @@ #if defined(TARGET_M451) #define NUMBER_OF_LOGICAL_ENDPOINTS (8) #define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS) -#elif defined (TARGET_M480) +#elif defined (TARGET_M480) || defined(TARGET_M460) #if (MBED_CONF_TARGET_USB_DEVICE_HSUSBD == 0) #define NUMBER_OF_LOGICAL_ENDPOINTS (12) #define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS) @@ -26,7 +26,7 @@ #define NUMBER_OF_LOGICAL_ENDPOINTS (12) #define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS) #endif -#elif defined (TARGET_M2351) || defined(TARGET_M261) +#elif defined (TARGET_M2351) || defined(TARGET_M261) || defined(TARGET_M2354) #define NUMBER_OF_LOGICAL_ENDPOINTS (12) #define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS) #elif defined (TARGET_NANO100) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt index f8f18a8..9b26267 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt @@ -1,6 +1,8 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(TARGET_NUCLEO_H723ZG EXCLUDE_FROM_ALL) + if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S) set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h723xg.ld) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt new file mode 100644 index 0000000..d27c221 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-nucleo-h723zg INTERFACE) + +target_sources(mbed-nucleo-h723zg + INTERFACE + PeripheralPins.c + system_clock.c +) + +target_include_directories(mbed-nucleo-h723zg + INTERFACE + . +) + +target_link_libraries(mbed-nucleo-h723zg INTERFACE mbed-stm32h723xg) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PeripheralPins.c new file mode 100644 index 0000000..29d17fa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PeripheralPins.c @@ -0,0 +1,643 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2022 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H723ZGTx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 // Connected to RMII_REF_CLK + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 // Connected to RMII_MDIO + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 // Connected to RMII_MDIO + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 // Connected to RMII_CRS_DV + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 // Connected to RMII_CRS_DV + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 // Connected to LED_GREEN + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 // Connected to LED_GREEN + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 // Connected to RMII_MDC + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to RMII_MDC + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 // Connected to RMII_MDC + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 // Connected to RMII_RXD0 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 // Connected to RMII_RXD0 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 // Connected to RMII_RXD1 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 // Connected to RMII_RXD1 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PC_9_ALT0, I2C_5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C5)}, + {PC_10, I2C_5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_0_ALT0, I2C_5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C5)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_8_ALT0, I2C_5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C5)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_11, I2C_5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C5)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_1_ALT0, I2C_5, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C5)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// (update us_ticker_data.h file if another timer is chosen) +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to RMII_REF_CLK +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to RMII_REF_CLK + {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to RMII_REF_CLK + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to RMII_MDIO +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to RMII_MDIO + {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to RMII_MDIO + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_CRS_DV + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to RMII_CRS_DV + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to RMII_CRS_DV + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to RMII_CRS_DV + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_FS_VBUS + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_FS_ID + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_FS_DM + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LED_GREEN + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LED_GREEN + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LED_GREEN + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to RMII_TXD1 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LED_RED + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LED_RED + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LED_RED + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PC_12, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_0, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 1, 0)}, // TIM23_CH1 + {PF_1, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 2, 0)}, // TIM23_CH2 + {PF_2, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 3, 0)}, // TIM23_CH3 + {PF_3, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 4, 0)}, // TIM23_CH4 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_6_ALT0, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 1, 0)}, // TIM23_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_7_ALT0, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 2, 0)}, // TIM23_CH2 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_8_ALT1, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 3, 0)}, // TIM23_CH3 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PF_9_ALT1, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 4, 0)}, // TIM23_CH4 + {PF_11, PWM_24, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM24, 1, 0)}, // TIM24_CH1 + {PF_12, PWM_24, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM24, 2, 0)}, // TIM24_CH2 + {PF_13, PWM_24, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM24, 3, 0)}, // TIM24_CH3 + {PF_14, PWM_24, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM24, 4, 0)}, // TIM24_CH4 + {PG_12, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 1, 0)}, // TIM23_CH1 + {PG_13, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 2, 0)}, // TIM23_CH2 // Connected to RMII_TXD0 + {PG_14, PWM_23, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF13_TIM23, 3, 0)}, // TIM23_CH3 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_MDIO + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_FS_VBUS + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_FS_VBUS + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_FS_DP + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to RMII_TXD1 + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to LED_RED + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX + {PD_15, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to LED_YELLOW + {PE_3, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_USART10)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_1, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_12, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART10)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to RMII_REF_CLK + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_FS_ID + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_FS_ID + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_FS_DM + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to SWO + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX + {PD_14, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_2, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART10)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_11, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART10)}, // Connected to RMII_TX_EN + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to RMII_REF_CLK + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_FS_DP + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_FS_DP + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED_RED + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LED_RED + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_13, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_14, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART10)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_FS_DM + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_FS_DM + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LED_GREEN + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to RMII_TXD1 + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_0, UART_9, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART9)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to RMII_TXD0 + {PG_13_ALT0, UART_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART10)}, // Connected to RMII_TXD0 + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to RMII_CRS_DV + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to RMII_CRS_DV + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RMII_MDC + {PC_3C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LED_RED + {PC_2C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_FS_VBUS + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_FS_DP + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to SWO + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RMII_TXD1 + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PC_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to RMII_TX_EN + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to RMII_TXD0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_FS_DM + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to USB_FS_DM + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_12, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_FDCAN3)}, + {PF_6, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_FDCAN3)}, + {PG_10, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_FDCAN3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to USB_FS_DP + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to RMII_TXD1 + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PD_13, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_FDCAN3)}, + {PF_7, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_FDCAN3)}, + {PG_9, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_FDCAN3)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 // Connected to RMII_MDIO + {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PB_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PC_3C, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PF_0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 // Connected to LED_GREEN + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {PF_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to RMII_CRS_DV + {PB_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to RMII_TXD1 + {PC_2C, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PF_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 // Connected to RMII_REF_CLK + {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {PF_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {PF_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PG_12, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS + {NC, NC, 0} +}; + +//*** OCTOSPI *** + +MBED_WEAK const PinMap PinMap_OSPI_DATA0[] = { + {PA_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 // Connected to RMII_MDIO + {PB_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PB_12, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PC_3C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PC_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PD_11, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PF_0, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO0 + {PF_8, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA1[] = { + {PB_0, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 // Connected to LED_GREEN + {PC_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {PD_12, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {PF_1, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO1 + {PF_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA2[] = { + {PA_3, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PA_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to RMII_CRS_DV + {PB_13, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to RMII_TXD1 + {PC_2C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PE_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PF_2, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO2 + {PF_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA3[] = { + {PA_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 // Connected to RMII_REF_CLK + {PA_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {PD_13, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {PF_3, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO3 + {PF_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA4[] = { + {PC_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO4 // Connected to RMII_MDC + {PD_4, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO4 + {PE_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO4 + {PG_0, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO4 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA5[] = { + {PC_2C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 + {PD_5, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 + {PE_8, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 + {PG_1, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO5 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA6[] = { + {PC_3C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 + {PD_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 + {PE_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 + {PG_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 + {PG_10, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO6 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DATA7[] = { + {PD_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO7 + {PE_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO7 + {PG_11, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO7 // Connected to RMII_TX_EN + {PG_14, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO7 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_DQS[] = { + {PA_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OCTOSPIM_P1)}, // OCTOSPIM_P1_DQS // Connected to RMII_REF_CLK + {PB_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_DQS + {PC_5, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_DQS // Connected to RMII_RXD1 + {PF_12, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_DQS + {PG_7, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_DQS // Connected to USB_FS_OVCR + {PG_15, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_DQS + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_SCLK[] = { + {PA_3, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {PB_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {PF_4, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P2)}, // OCTOSPIM_P2_CLK + {PF_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_OSPI_SSEL[] = { + {PB_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PB_10, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PC_11, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PE_11, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PG_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS + {PG_12, OSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_8, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_SOF + {PA_9, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS // Connected to USB_FS_VBUS + {PA_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ID // Connected to USB_FS_ID + {PA_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DM // Connected to USB_FS_DM + {PA_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, // USB_OTG_HS_DP // Connected to USB_FS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D1 // Connected to LED_GREEN + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D6 // Connected to RMII_TXD1 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_NXT +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h new file mode 100644 index 0000000..9e4001b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TARGET_NUCLEO_H723ZG/PinNames.h @@ -0,0 +1,423 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2022 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H723ZGTx.xml + */ + +/* MBED TARGET LIST: NUCLEO_H723ZGT */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DUAL_PAD 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_8_ALT0 = PA_8 | ALT0, // same pin used for alternate HW + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | DUAL_PAD, // dual pad + PC_3 = 0x23, + PC_3C = PC_3 | DUAL_PAD, // dual pad + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_0_ALT0 = PF_0 | ALT0, // same pin used for alternate HW + PF_1 = 0x51, + PF_1_ALT0 = PF_1 | ALT0, // same pin used for alternate HW + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_7_ALT0 = PF_7 | ALT0, // same pin used for alternate HW + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_8_ALT1 = PF_8 | ALT1, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_9_ALT1 = PF_9 | ALT1, // same pin used for alternate HW + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_13_ALT0 = PG_13 | ALT0, // same pin used for alternate HW + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Uno (Rev3) pins + ARDUINO_UNO_A0 = PA_3, + ARDUINO_UNO_A1 = PC_0, + ARDUINO_UNO_A2 = PC_3C, + ARDUINO_UNO_A3 = PB_1, + ARDUINO_UNO_A4 = PC_2C, + ARDUINO_UNO_A5 = PF_10, + + ARDUINO_UNO_D0 = PB_7, + ARDUINO_UNO_D1 = PB_6, + ARDUINO_UNO_D2 = PG_14, + ARDUINO_UNO_D3 = PE_13, + ARDUINO_UNO_D4 = PE_14, + ARDUINO_UNO_D5 = PE_11, + ARDUINO_UNO_D6 = PE_9, + ARDUINO_UNO_D7 = PG_12, + ARDUINO_UNO_D8 = PF_3, + ARDUINO_UNO_D9 = PD_15, + ARDUINO_UNO_D10 = PD_14, + ARDUINO_UNO_D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */ + ARDUINO_UNO_D12 = PA_6, + ARDUINO_UNO_D13 = PA_5, + ARDUINO_UNO_D14 = PB_9, + ARDUINO_UNO_D15 = PB_8, +#endif + + // ST ZIO connector extending Arduino Uno + A6 = PF_4, + A7 = PF_5, + A8 = PF_6, + D16 = PC_6, + D17 = PB_15, + D18 = PB_13, + D19 = PB_12, + D20 = PA_15, + D21 = PC_7, + D22 = PB_5, + D23 = PB_3, + D24 = PA_4, + D25 = PB_4, + D26 = PG_6, + D27 = PB_2, + D28 = PD_13, + D29 = PD_12, + D30 = PD_11, + D31 = PE_2, + D32 = PA_0, + D33 = PB_0, + D34 = PE_0, + D35 = PB_11, + D36 = PB_10, + D37 = PE_15, + D38 = PE_6, + D39 = PE_12, + D40 = PE_10, + D41 = PE_7, + D42 = PE_8, + D43 = PC_8, + D44 = PC_9, + D45 = PC_10, + D46 = PC_11, + D47 = PC_12, + D48 = PD_2, + D49 = PG_2, + D50 = PG_3, + D51 = PD_7, + D52 = PD_6, + D53 = PD_5, + D54 = PD_4, + D55 = PD_3, + D56 = PE_2, + D57 = PE_4, + D58 = PE_5, + D59 = PE_6, + D60 = PE_3, + D61 = PF_8, + D62 = PF_7, + D63 = PF_9, + D64 = PG_1, + D65 = PG_0, + D66 = PD_1, + D67 = PD_0, + D68 = PF_0, + D69 = PF_1, + D70 = PF_2, + D71 = PE_2, + D72 = PB_2, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PD_9, +#endif + + /**** USB FS pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + + /**** USB HS pins ****/ + USB_OTG_HS_DM = PA_11, + USB_OTG_HS_DP = PA_12, + USB_OTG_HS_ID = PA_10, + USB_OTG_HS_SOF = PA_8, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2C, + USB_OTG_HS_ULPI_NXT = PC_3C, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PA_9, + + /**** ETHERNET pins ****/ + ETH_COL = PA_3, + ETH_CRS = PA_0, + ETH_CRS_DV = PA_7, + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_PPS_OUT = PG_8, + ETH_PPS_OUT_ALT0 = PB_5, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RXD2 = PB_0, + ETH_RXD3 = PB_1, + ETH_RX_CLK = PA_1, + ETH_RX_DV = PA_7, + ETH_RX_ER = PB_10, + ETH_TXD0 = PB_12, + ETH_TXD0_ALT0 = PG_13, + ETH_TXD1 = PB_13, + ETH_TXD1_ALT0 = PG_12, + ETH_TXD1_ALT1 = PG_14, + ETH_TXD2 = PC_2C, + ETH_TXD3 = PE_2, + ETH_TXD3_ALT0 = PB_8, + ETH_TX_CLK = PC_3C, + ETH_TX_EN = PB_11, + ETH_TX_EN_ALT0 = PG_11, + ETH_TX_ER = PB_2, + ETH_TX_ER_ALT0 = PA_9, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + DEBUG_JTCK_SWCLK = PA_14, + DEBUG_JTDI = PA_15, + DEBUG_JTDO_SWO = PB_3, + DEBUG_JTMS_SWDIO = PA_13, + DEBUG_JTRST = PB_4, + DEBUG_TRACECLK = PE_2, + DEBUG_TRACED0 = PE_3, + DEBUG_TRACED0_ALT0 = PC_1, + DEBUG_TRACED0_ALT1 = PG_13, + DEBUG_TRACED1 = PE_4, + DEBUG_TRACED1_ALT0 = PC_8, + DEBUG_TRACED1_ALT1 = PG_14, + DEBUG_TRACED2 = PE_5, + DEBUG_TRACED2_ALT0 = PD_2, + DEBUG_TRACED3 = PE_6, + DEBUG_TRACED3_ALT0 = PC_12, + DEBUG_TRGIO = PC_7, + PWR_CSLEEP = PC_3C, + PWR_CSTOP = PC_2C, + PWR_NDSTOP2 = PA_5, + PWR_PVD_IN = PB_7, + SYS_PWR_WKUP1 = PA_0, + SYS_PWR_WKUP2 = PA_2, + SYS_PWR_WKUP4 = PC_13, + SYS_PWR_WKUP6 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 PB_0 // LED_GREEN +#define LED2 PB_14 // LED_RED +#define LED3 PE_1 // LED_YELLOW +#define BUTTON1 PC_13 // B1 (Blue_User_Button) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S index a9b669f..26c31d0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S @@ -61,39 +61,36 @@ Reset_Handler: ldr sp, =_estack /* set stack pointer */ -/* Call the clock system initialization function.*/ - bl SystemInit - /* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit + movs r1, #0 + b LoopCopyDataInit CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss /* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - FillZerobss: - str r3, [r2] - adds r2, r2, #4 + movs r3, #0 + str r3, [r2], #4 LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system initialization function.*/ + bl SystemInit bl _start bx lr bx lr diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld index 5f47993..bf7b215 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld @@ -26,19 +26,29 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif +M_CRASH_DATA_RAM_SIZE = 0x100; + #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 #endif -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +/* Round up MBED_VECTTABLE_RAM_SIZE to 8 bytes */ +#define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) +#define MBED_RAM0_START (MBED_RAM_START + MBED_VECTTABLE_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE) MEMORY { - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + SRAM_DTC (xrw) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE + SRAM (xrw) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE + SRAM_LOWER (xrw) : ORIGIN = 0x30000000, LENGTH = 32K + SRAM_UPPER (xrw) : ORIGIN = 0x38000000, LENGTH = 16K + SRAM_ITC (xrw) : ORIGIN = 0x00000000, LENGTH = 64K } /* Linker script to place sections and symbol values. Should be used together @@ -113,7 +123,48 @@ __etext = .; _sidata = .; - + + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > SRAM_UPPER + + /* .stack section doesn't contains any symbols. It is only + * used for linker to reserve space for the isr stack section + * WARNING: .stack should come immediately after the last secure memory + * section. This provides stack overflow detection. */ + .stack (NOLOAD): + { + __StackLimit = .; + *(.stack*); + . += STACK_SIZE - (. - __StackLimit); + } > SRAM_DTC + + /* Set stack top to end of SRAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ADDR(.stack) + SIZEOF(.stack); + _estack = __StackTop; + __StackLimit = ADDR(.stack); + PROVIDE(__stack = __StackTop); + + /* Place holder for additional heap */ + .heap_0 (COPY): + { + __mbed_sbrk_start_0 = .; + . += (ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - .); + __mbed_krbs_start_0 = .; + } > SRAM_DTC + + /* Check if heap exceeds SRAM_DTC */ + ASSERT(__mbed_krbs_start_0 <= (ORIGIN(SRAM_DTC)+LENGTH(SRAM_DTC)), "Heap is too big for SRAM_DTC") + .data : AT (__etext) { __data_start__ = .; @@ -147,7 +198,10 @@ __data_end__ = .; _edata = .; - } > RAM + } > SRAM + + /* Check if bss exceeds SRAM */ + ASSERT(__data_end__ <= (ORIGIN(SRAM)+LENGTH(SRAM)), ".data is too big for SRAM") /* Uninitialized data section * This region is not initialized by the C/C++ library and can be used to @@ -160,8 +214,8 @@ KEEP(*(.keep.uninitialized)) . = ALIGN(32); __uninitialized_end = .; - } > RAM - + } > SRAM + .bss : { . = ALIGN(8); @@ -172,32 +226,22 @@ . = ALIGN(8); __bss_end__ = .; _ebss = .; - } > RAM + } > SRAM + + /* Check if bss exceeds SRAM */ + ASSERT(__bss_end__ <= (ORIGIN(SRAM)+LENGTH(SRAM)), "BSS is too big for SRAM") .heap (COPY): { __end__ = .; - PROVIDE(end = .); + end = __end__; + __mbed_sbrk_start = .; *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + . += (ORIGIN(SRAM) + LENGTH(SRAM) - .); + __mbed_krbs_start = .; __HeapLimit = .; - } > RAM + } > SRAM - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + /* Check if data + heap exceeds SRAM limit */ + ASSERT(__HeapLimit <= (ORIGIN(SRAM)+LENGTH(SRAM)), "Heap is too big for SRAM") } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h index e981df8..6559955 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h @@ -25,20 +25,28 @@ #define MBED_ROM_SIZE 0x100000 // 1 MB #endif +// 0x20000000 - 0x2001FFFF 128K DTCM +// 0x24000000 - 0x2404FFFF 320K AXI SRAM +// 0x30000000 - 0x30003FFF 16K SRAM1 +// 0x30004000 - 0x30007FFF 16K SRAM2 +// 0x38000000 - 0x38003FFF 16K SRAM4 + #if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x24000000 +#define MBED_RAM_START 0x20000000 #endif #if !defined(MBED_RAM_SIZE) -// 0x38000000 - 0x38003FFF 16K SRAM4 -// 0x30004000 - 0x30007FFF 16K SRAM2 -// 0x30000000 - 0x30003FFF 16K SRAM1 -// 0x24000000 - 0x2404FFFF 320K AXI SRAM -// 0x20000000 - 0x2001FFFF 128K DTCM -#define MBED_RAM_SIZE 0x50000 // 320 KB +#define MBED_RAM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM1_START) +#define MBED_RAM_1START 0x24000000 +#endif + +#if !defined(MBED_RAM1_SIZE) +#define MBED1_RAM_SIZE 0x50000 // 320 KB #endif #define NVIC_NUM_VECTORS 180 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START - #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/system_clock.c index 2075555..60dca86 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/system_clock.c @@ -20,12 +20,12 @@ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) * | 3- USE_PLL_HSI (internal 64 MHz clock) *-------------------------------------------------------------------- - * SYSCLK(MHz) | 480 - * AHBCLK (MHz) | 240 - * APB1CLK (MHz) | 120 - * APB2CLK (MHz) | 120 - * APB3CLK (MHz) | 120 - * APB4CLK (MHz) | 120 + * SYSCLK(MHz) | 550 + * AHBCLK (MHz) | 275 + * APB1CLK (MHz) | 137.5 + * APB2CLK (MHz) | 137.5 + * APB3CLK (MHz) | 137.5 + * APB4CLK (MHz) | 137.5 * USB capable (48 MHz) | YES *-------------------------------------------------------------------- **/ @@ -85,17 +85,23 @@ /******************************************************************************/ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /* Supply configuration update enable */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); /* Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); - while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /* Enable HSE Oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + /* Configure LSE Drive Capability */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + /* Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; if (bypass) { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; } else { @@ -104,38 +110,36 @@ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; -#if HSE_VALUE==8000000 - RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz - RCC_OscInitStruct.PLL.PLLN = 275; // 550 MHz -#else -#error Unsupported externall clock value, check HSE_VALUE define -#endif - RCC_OscInitStruct.PLL.PLLP = 1; // PLLCLK = SYSCLK = 550 MHz - RCC_OscInitStruct.PLL.PLLQ = 5; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLM = 1; // 8 MHz + RCC_OscInitStruct.PLL.PLLN = 68; // 550 MHz (see PLLFRACN) + RCC_OscInitStruct.PLL.PLLP = 1; // 550 MHz + RCC_OscInitStruct.PLL.PLLQ = 5; // 110 MHz + RCC_OscInitStruct.PLL.PLLR = 2; // 275 MHz + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLFRACN = 6144; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return 0; // FAIL } - /* Select PLL as system clock source and configure bus clocks dividers */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | - RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | - RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { return 0; // FAIL } #if DEVICE_USBDEVICE + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { @@ -155,6 +159,67 @@ /******************************************************************************/ uint8_t SetSysClock_PLL_HSI(void) { - return 0; // FAIL + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /* Supply configuration update enable */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Configure LSE Drive Capability */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + + /* Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 4; // 16 MHz + RCC_OscInitStruct.PLL.PLLN = 34; // 550 MHz (see PLLFRACN) + RCC_OscInitStruct.PLL.PLLP = 1; // 550 MHz + RCC_OscInitStruct.PLL.PLLQ = 5; // 110 MHz + RCC_OscInitStruct.PLL.PLLR = 2; // 275 MHz + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 3072; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + +#if DEVICE_USBDEVICE + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + + return 1; // OK } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp index c45150d..a243961 100644 --- a/targets/TARGET_STM/USBPhy_STM32.cpp +++ b/targets/TARGET_STM/USBPhy_STM32.cpp @@ -264,8 +264,17 @@ hpcd.Init.vbus_sensing_enable = DISABLE; hpcd.Init.use_external_vbus = DISABLE; +#ifdef __HAL_RCC_OTGPHYC_CLK_ENABLE + __HAL_RCC_OTGPHYC_CLK_ENABLE(); +#endif __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); +#ifdef __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE + __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE(); +#endif +#ifdef __HAL_RCC_USB2_OTG_HS_ULPI_CLK_SLEEP_DISABLE + __HAL_RCC_USB2_OTG_HS_ULPI_CLK_SLEEP_DISABLE(); +#endif #ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); #endif diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index a2f34a9..f3c27aa 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -333,9 +333,9 @@ uint32_t nominalPrescaler = 1; // !When the sample point should be lower than 50%, this must be changed to - // !IS_FDCAN_DATA_TSEG2(ntq/nominalPrescaler), since + // !IS_FDCAN_NOMINAL_TSEG2(ntq/nominalPrescaler), since // NTSEG2 and SJW max values are lower. For now the sample point is fix @75% - while (!IS_FDCAN_DATA_TSEG1(ntq / nominalPrescaler)) { + while (!IS_FDCAN_NOMINAL_TSEG1(ntq / nominalPrescaler)) { nominalPrescaler ++; if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)) { error("Could not determine good nominalPrescaler. Bad clock value\n"); diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc.h new file mode 100644 index 0000000..2e61156 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc.h @@ -0,0 +1,463 @@ +/** + ******************************************************************************* + * @file txz_adc.h + * @brief This file provides all the functions prototypes for ADC driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_H +#define __ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_adc_ch.h" +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/** + * @defgroup ADC_ChannelMax Channel Num Max + * @brief Max Num of channel. + * @{ + */ + +#define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */ +/** + * @} + */ /* End of group ADC_ChannelMax */ +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + @defgroup ADC_Exported_define ADC Exported Define + @{ + */ +/** @enum adc_sampling_period0_t + @brief Outside AIN sampling period. + */ +typedef enum { + ADC_SAMPLING_PERIOD0_XN = 0x00, /*!< SCLK Period (1/SCLK)xN */ + ADC_SAMPLING_PERIOD0_X2N = 0x08, /*!< SCLK Period (1/SCLK)x2N */ + ADC_SAMPLING_PERIOD0_X3N = 0x10, /*!< SCLK Period (1/SCLK)x3N */ + ADC_SAMPLING_PERIOD0_X4N = 0x18, /*!< SCLK Period (1/SCLK)x4N */ +} adc_sampling_period0_t; +/** @enum adc_sampling_period1_t + @brief Outside AIN sampling period. + */ +typedef enum { + ADC_SAMPLING_PERIOD1_XN = 0x000, /*!< SCLK Period (1/SCLK)xN */ + ADC_SAMPLING_PERIOD1_X2N = 0x100, /*!< SCLK Period (1/SCLK)x2N */ + ADC_SAMPLING_PERIOD1_X3N = 0x200, /*!< SCLK Period (1/SCLK)x3N */ + ADC_SAMPLING_PERIOD1_X4N = 0x300, /*!< SCLK Period (1/SCLK)x4N */ +} adc_sampling_period1_t; + +/*! @enum adc_sclk_t + @brief Select AD prescaler output (SCLK). + */ +typedef enum { + ADC_SCLK_2 = (0x00000000U), /*!< ADCLK/2 */ + ADC_SCLK_4 = (0x00000001U), /*!< ADCLK/4 */ + ADC_SCLK_8 = (0x00000002U), /*!< ADCLK/8 */ + ADC_SCLK_16 = (0x00000003U), /*!< ADCLK/16 */ + ADC_SCLK_3 = (0x00000004U), /*!< ADCLK/3 */ + ADC_SCLK_5 = (0x00000005U), /*!< ADCLK/5 */ + ADC_SCLK_6 = (0x00000006U), /*!< ADCLK/6 */ + ADC_SCLK_10 = (0x00000007U), /*!< ADCLK/10 */ +} adc_sclk_t; + +/*! @enum adc_mod1_t + @brief Select SCLK Frequency Band (MOD1). + */ +typedef enum { + ADC_MOD1_SCLK_1 = (0x00001000U), /*!< SCLK =< 20MHz > */ + ADC_MOD1_SCLK_2 = (0x00003000U), /*!< 20MHz < SCLK =< 25MHz > */ + ADC_MOD1_SCLK_3 = (0x00004000U), /*!< 25MHz < SCLK =< 30MHz > */ + ADC_MOD1_SCLK_4 = (0x00006011U), /*!< 30MHz < SCLK =< 40MHz > */ +} adc_mod1_t; + +/*! @enum adc_mod2_t + @brief Select ADC Product Setting Value (MOD2). + */ +typedef enum { + ADC_MOD2_SET = (0x00000000U), /*!< SET Value */ + ADC_MOD2_CLEAR = (0x00000000U), /*!< Reset Value */ +} adc_mod2_t; + +/*! @enum adc_int_t + @brief Select Interrupt Enable/Disable. + */ +typedef enum { + ADC_INT_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_INT_ENABLE = (0x00000080U), /*!< Enable. */ +} adc_int_t; + +/*! @enum adc_conversion_t + @brief Select conversion method. + */ +typedef enum { + ADC_CONVERSION_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_CONVERSION_CNT = (0x00000100U), /*!< Continuation. */ + ADC_CONVERSION_SGL = (0x00000200U), /*!< Single. */ + ADC_CONVERSION_TRG = (0x00000300U), /*!< Universal Trigger. */ + ADC_CONVERSION_HPTG = (0x00000400U), /*!< High Priority Trigger. */ +} adc_conversion_t; + +/*! @enum adc_dma_int_t + @brief Select DMA interrupt method. + */ +typedef enum { + ADC_DMA_INT_SGL_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_SGL_ENABLE = (0x00000020U), /*!< DMA Single interrupt Enable. */ + ADC_DMA_INT_CNT_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_CNT_ENABLE = (0x00000040U), /*!< DMA Continuation interrupt Enable. */ + ADC_DMA_INT_TRG_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_TRG_ENABLE = (0x00000010U), /*!< DMA Universal Trigger interrupt Enable. */ + ADC_TRG_DISABLE = (0x00000000U), /*!< Universal Trigger Disable. */ + ADC_TRG_ENABLE = (0x00000001U), /*!< Universal Trigger Enable. */ + ADC_HPTG_DISABLE = (0x00000000U), /*!< High Priority Trigger Disable. */ + ADC_HPTG_ENABLE = (0x00000002U), /*!< High Priority Trigger Enable. */ +} adc_dma_int_t; + +/*! @enum adc_ain_range_t + @brief Range of AIN Macro Definition. + Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)". + */ +typedef enum { + ADC_AIN_RANGE_MIN = (0x00000000U), /*!< Minimum Value :AINx00 */ + ADC_AIN_RANGE_MAX = (0x00000017U), /*!< Maximum Value :AINx23 */ +} adc_ain_range_t; + +/*! @enum adc_status_t + @brief AD Running Status. + */ +typedef enum { + ADC_STATUS_MASK = (0x00000080U), /*!< for Mask. */ + ADC_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_STATUS_RUNNING = (0x00000080U), /*!< Running. */ +} adc_status_t; + +/*! @enum adc_cnt_status_t + @brief Continuity Conversion Running Status. + */ +typedef enum { + ADC_CNT_STATUS_MASK = (0x00000008U), /*!< for Mask. */ + ADC_CNT_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_CNT_STATUS_RUNNING = (0x00000008U), /*!< Running. */ +} adc_cnt_status_t; + +/*! @enum adc_sgl_status_t + @brief Single Conversion Running Status. + */ +typedef enum { + ADC_SGL_STATUS_MASK = (0x00000004U), /*!< for Mask. */ + ADC_SGL_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_SGL_STATUS_RUNNING = (0x00000004U), /*!< Running. */ +} adc_sgl_status_t; + +/*! @enum adc_trg_status_t + @brief Trigger Conversion Running Status. + */ +typedef enum { + ADC_TRG_STATUS_MASK = (0x00000002U), /*!< for Mask. */ + ADC_TRG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_TRG_STATUS_RUNNING = (0x00000002U), /*!< Running. */ +} adc_trg_status_t; + +/*! @enum adc_hpri_status_t + @brief Trigger Conversion Running Status. + */ +typedef enum { + ADC_HPTG_STATUS_MASK = (0x00000001U), /*!< for Mask. */ + ADC_HPTG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_HPTG_STATUS_RUNNING = (0x00000001U), /*!< Running. */ +} adc_hpri_status_t; + +/*! @enum adcmpxen_t + @brief Select Enable, Disable setting(ADxCMPEN). + */ +typedef enum { + ADCMP1EN_DISABLE = (0x00000000U), /*!< Disable. */ + ADCMP1EN_ENABLE = (0x00000002U), /*!< Enable. */ + ADCMP0EN_DISABLE = (0x00000000U), /*!< Disable. */ + ADCMP0EN_ENABLE = (0x00000001U), /*!< Enable. */ +} adcmpxen_t; + +/*! @enum adcmpcnt_t + @brief Select Compare count num. + */ +typedef enum { + ADCMPCNT_1 = (0x00000000U), /*!< 1 time */ + ADCMPCNT_2 = (0x00000100U), /*!< 2 times */ + ADCMPCNT_3 = (0x00000200U), /*!< 3 times */ + ADCMPCNT_4 = (0x00000300U), /*!< 4 times */ + ADCMPCNT_5 = (0x00000400U), /*!< 5 times */ + ADCMPCNT_6 = (0x00000500U), /*!< 6 times */ + ADCMPCNT_7 = (0x00000600U), /*!< 7 times */ + ADCMPCNT_8 = (0x00000700U), /*!< 8 times */ + ADCMPCNT_9 = (0x00000800U), /*!< 9 times */ + ADCMPCNT_10 = (0x00000900U), /*!< 10 times */ + ADCMPCNT_11 = (0x00000a00U), /*!< 11 times */ + ADCMPCNT_12 = (0x00000b00U), /*!< 12 times */ + ADCMPCNT_13 = (0x00000c00U), /*!< 13 times */ + ADCMPCNT_14 = (0x00000d00U), /*!< 14 times */ + ADCMPCNT_15 = (0x00000e00U), /*!< 15 times */ + ADCMPCNT_16 = (0x00000f00U), /*!< 16 times */ +} adcmpcnt_t; + +/*! @enum adcmpcond_t + @brief Compare condition + */ +typedef enum { + ADCMPCond_CNT = (0x00000000U), /*!< Continuous */ + ADCMPCond_ACC = (0x00000040U), /*!< Accumulation */ +} adcmpcond_t; + +/*! @enum adcmpbigsml_t + @brief Compare Big, Small condition + */ +typedef enum { + ADCMPBigSml_Big = (0x00000000U), /*!< Big */ + ADCMPBigSml_Sml = (0x00000020U), /*!< Small */ +} adcmpbigsml_t; + +/*! @enum adcmpstr_t + @brief Select Compare Store register + */ +typedef enum { + ADCMPStr_Reg0 = (0x00000000U), /*!< ADxREG0 */ + ADCMPStr_Reg1 = (0x00000001U), /*!< ADxREG1 */ + ADCMPStr_Reg2 = (0x00000002U), /*!< ADxREG2 */ + ADCMPStr_Reg3 = (0x00000003U), /*!< ADxREG3 */ + ADCMPStr_Reg4 = (0x00000004U), /*!< ADxREG4 */ + ADCMPStr_Reg5 = (0x00000005U), /*!< ADxREG5 */ + ADCMPStr_Reg6 = (0x00000006U), /*!< ADxREG6 */ + ADCMPStr_Reg7 = (0x00000007U), /*!< ADxREG7 */ + ADCMPStr_Reg8 = (0x00000008U), /*!< ADxREG8 */ + ADCMPStr_Reg9 = (0x00000009U), /*!< ADxREG9 */ + ADCMPStr_Reg10 = (0x0000000aU), /*!< ADxREG10 */ + ADCMPStr_Reg11 = (0x0000000bU), /*!< ADxREG11 */ + ADCMPStr_Reg12 = (0x0000000cU), /*!< ADxREG12 */ + ADCMPStr_Reg13 = (0x0000000dU), /*!< ADxREG13 */ + ADCMPStr_Reg14 = (0x0000000eU), /*!< ADxREG14 */ + ADCMPStr_Reg15 = (0x0000000fU), /*!< ADxREG15 */ + ADCMPStr_Reg16 = (0x00000010U), /*!< ADxREG16 */ + ADCMPStr_Reg17 = (0x00000011U), /*!< ADxREG17 */ + ADCMPStr_Reg18 = (0x00000012U), /*!< ADxREG18 */ + ADCMPStr_Reg19 = (0x00000013U), /*!< ADxREG19 */ + ADCMPStr_Reg20 = (0x00000014U), /*!< ADxREG20 */ + ADCMPStr_Reg21 = (0x00000015U), /*!< ADxREG21 */ + ADCMPStr_Reg22 = (0x00000016U), /*!< ADxREG22 */ + ADCMPStr_Reg23 = (0x00000017U), /*!< ADxREG23 */ +} adcmpstr_t; +/*! @enum adcexazain_t + @brief Select AIN no. + */ + +typedef enum { + ADCEXAZSEL_AIN0 = 0, /*!< AIN0 */ + ADCEXAZSEL_AIN1, /*!< AIN1 */ + ADCEXAZSEL_AIN2, /*!< AIN2 */ + ADCEXAZSEL_AIN3, /*!< AIN3 */ + ADCEXAZSEL_AIN4, /*!< AIN4 */ + ADCEXAZSEL_AIN5, /*!< AIN5 */ + ADCEXAZSEL_AIN6, /*!< AIN6 */ + ADCEXAZSEL_AIN7, /*!< AIN7 */ + ADCEXAZSEL_AIN8, /*!< AIN8 */ + ADCEXAZSEL_AIN9, /*!< AIN9 */ + ADCEXAZSEL_AIN10, /*!< AIN10 */ + ADCEXAZSEL_AIN11, /*!< AIN11 */ + ADCEXAZSEL_AIN12, /*!< AIN12 */ + ADCEXAZSEL_AIN13, /*!< AIN13 */ + ADCEXAZSEL_AIN14, /*!< AIN14 */ + ADCEXAZSEL_AIN15, /*!< AIN15 */ + ADCEXAZSEL_AIN16, /*!< AIN16 */ + ADCEXAZSEL_AIN17, /*!< AIN17 */ + ADCEXAZSEL_AIN18, /*!< AIN18 */ + ADCEXAZSEL_AIN19, /*!< AIN19 */ + ADCEXAZSEL_AIN20, /*!< AIN20 */ + ADCEXAZSEL_AIN21, /*!< AIN21 */ + ADCEXAZSEL_AIN22, /*!< AIN22 */ + ADCEXAZSEL_AIN23, /*!< AIN23 */ +} adcexazain_t; +/*! @enum adcexazsel_t + @brief Select sampling period, EXAS0 or EXAS1. + */ +typedef enum { + ADCEXAZSEL_EXAZ0 = (0x00000000), /*< EXAZ0 */ + ADCEXAZSEL_EXAZ1 = (0x00000001), /*< EXAZ1 */ +} adcexazsel_t; + +/*! + @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/*! + @defgroup ADC_Exported_typedef ADC Exported Typedef + @{ + */ + +/*----------------------------------*/ +/*! @struct adc_clock_t + @brief Clock information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + adc_sampling_period0_t exaz0; /*!< Outside AIN0 Sampling period. + : Use @ref adc_sampling_period0_t. */ + adc_sampling_period1_t exaz1; /*!< Outside AIN1 Sampling period. + : Use @ref adc_sampling_period1_t. */ + adc_sclk_t vadcld; /*!< Select AD prescaler output (SCLK). + : Use @ref adc_sclk_t. */ + uint32_t sampling_select; /*!< Sampling period select. : bit0-bit23 */ +} adc_clock_t; + +/*----------------------------------*/ +/*! @struct adc_cmpx_t + @brief Clock information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t CMPEN; /*!< Enable Register status */ + uint32_t CMPCNT; /*!< Compare count num. */ + uint32_t CMPCond; /*!< Compare condition */ + uint32_t CMPBigSml; /*!< Compare Big/Small condition */ + uint32_t StrReg; /*!< Compare Store register */ + uint32_t ADComp; /*!< ADxCMP0 register data */ + void (*handle)(uint32_t id, TXZ_Result result); /*!< Notify Compare Done. */ +} adc_cmpx_t; + +/*----------------------------------*/ +/*! @struct adc_initial_setting_t + @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + adc_clock_t clk; /*!< Clock setting. + : Use @ref adc_clock_t. */ + uint32_t mod1; /*!< AVDD3 voltage band setting. + : Use @ref adc_mod1_t. */ + uint32_t mod2; /*!< Product info setting. + : Use @ref adc_mod2_t. */ + adc_cmpx_t CMPxEN[4]; /*!< adc_cmpx_t. */ +} adc_initial_setting_t; + +/*----------------------------------*/ +/*! @struct adc_channel_setting_t + @brief Channel Setting. \n +*/ +/*----------------------------------*/ +typedef struct { + uint32_t interrupt; /*!< Interrupt Enable/Disable. + : Use @ref adc_dma_int_t. */ + uint32_t type; /*!< Conversion Type. + : Use @ref adc_conversion_t. */ + uint32_t ain; /*!< AIN. */ +} adc_channel_setting_t; + +/*----------------------------------*/ +/*! @struct adc_internal_info_t + @brief Driver internal information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */ +} adc_internal_info_t; + +/*----------------------------------*/ +/*! @struct adc_t + @brief ADC handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_AD_TypeDef *p_instance; /*!< Registers base address. */ + adc_initial_setting_t init; /*!< Initial setting. */ + adc_internal_info_t info; /*!< Driver internal information. */ + struct { + void (*single)(uint32_t id, TXZ_Result result); /*!< Notify Single Conversion Done. */ + void (*continuity)(uint32_t id, TXZ_Result result); /*!< Notify Continuity Conversion Done. */ + void (*trigger)(uint32_t id, TXZ_Result result); /*!< Notify Trigger Conversion Done. */ + void (*highpriority)(uint32_t id, TXZ_Result result); /*!< Notify HighPriority Conversion Done. */ + } handler; /*!< Handler structure. */ +} adc_t; + +/** + * @} + */ /* End of group ADC_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_functions ADC Exported Functions + * @{ + */ +TXZ_Result adc_init(adc_t *p_obj); +TXZ_Result adc_deinit(adc_t *p_obj); +TXZ_Result adc_mode1_setting(void); +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting); +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch); +TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); +TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value); +TXZ_Result adc_start(adc_t *p_obj); +TXZ_Result adc_stop(adc_t *p_obj); +TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status); +TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout); +void adc_compa_irq_handler(void); +void adc_compb_irq_handler(void); +void adc_single_irq_handler(void); +void adc_continuity_irq_handler(void); +void adc_trigger_irq_handler(void); +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_ch.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_ch.h new file mode 100644 index 0000000..bce9c39 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_ch.h @@ -0,0 +1,132 @@ +/** + ******************************************************************************* + * @file txz_adc_ch.h + * @brief This file provides all the functions prototypes for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_CH_H +#define __ADC_CH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_typedef ADC Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/*! @struct adc_ch_initial_setting_t + * @brief Initialize Setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t interrupt; /*!< Interrupt Enable/Disable. + : Use @ref adc_dma_int_t. */ + uint32_t type; /*!< Conversion Type. + : Use @ref adc_conversion_t. */ + uint32_t ain; /*!< AIN. */ +} adc_ch_initial_setting_t; + +/*----------------------------------*/ +/*! @struct adc_ch_t + * @brief ADC handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + __IO uint32_t *p_tset; /*!< ADxTSETn Address. */ + __I uint32_t *p_reg; /*!< ADxREGx Address. */ + adc_ch_initial_setting_t init; /*!< Initial setting. */ +} adc_ch_t; + +/** + * @} + */ /* End of group ADC_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_functions ADC Exported Functions + * @{ + */ +uint32_t get_conversion_data(uint32_t reg); +TXZ_Result adc_ch_init(adc_ch_t *p_obj); +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj); +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj); +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj); +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value); +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_CH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_include.h new file mode 100644 index 0000000..2d99bbd --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_adc_include.h @@ -0,0 +1,348 @@ +/** + ******************************************************************************* + * @file txz_adc_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_INCLUDE_H +#define __ADC_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_hal.h" + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/** + * @defgroup NULL_Pointer NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define ADC_NULL ((void *)0) /*!< NULL Pointer. */ +/** + * @} + */ /* End of group NULL_Pointer */ + +/** + * @defgroup Parameter_Result Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group Parameter_Result */ + +/** + * @defgroup ADxCR0 ADxCR0 + * @brief ADxCR0 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ADEN | + * | 6-3 | - | + * | 2 | HPSGL | + * | 1 | SGL | + * | 0 | CNT | + * @{ + */ +/* ADEN */ +#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */ +#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */ +/* HPSGL */ +#define ADxCR0_HPSGL_ENABLE ((uint32_t)0x00000004) /*!< HPSGL :Enable */ +/* SGL */ +#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */ +/* CNT */ +#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */ +#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */ +#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */ +/** + * @} + */ /* End of group ADxCR0 */ + +/** + * @defgroup ADxCR1 ADxCR1 + * @brief ADxCR1 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | HPDMEN | + * | 6 | CNTDMEN | + * | 5 | SGLDMEN | + * | 4 | TRGDMEN | + * | 3:2 | - | + * | 1 | HPTRGEN | + * | 0 | TRGEN | + * @{ + */ +/* HPDMEN */ +#define ADxCR1_HPDMEN_DISABLE ((uint32_t)0x00000000) /*!< HPDMEN :Disable */ +#define ADxCR1_HPDMEN_ENABLE ((uint32_t)0x00000080) /*!< HPDMEN :Enable */ +/* CNTDMEN */ +#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */ +#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */ +/* SGLDMEN */ +#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */ +#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */ +/* TRGDMEN */ +#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */ +#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */ +/* HPTRGEN */ +#define ADxCR1_HPTRGEN_DISABLE ((uint32_t)0x00000000) /*!< HPTRGEN :Disable */ +#define ADxCR1_HPTRGEN_ENABLE ((uint32_t)0x00000002) /*!< HPTRGEN :Enable */ +/* TRGEN */ +#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */ +#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */ +/** + * @} + */ /* End of group ADxCR1 */ + +/** + * @defgroup ADxST ADxST + * @brief ADxST Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ADBF | + * | 6-4 | - | + * | 3 | CNTF | + * | 2 | SNGF | + * | 1 | TRGF | + * | 0 | HPF | + * @{ + */ +/* ADBF */ +#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */ +#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */ +#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */ +/* CNTF */ +#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */ +#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */ +#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */ +/* SNGF */ +#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */ +#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */ +#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */ +/* TRGF */ +#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */ +#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */ +#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */ +/* PMDF */ +#define ADxST_HPF_MASK ((uint32_t)0x00000001) /*!< HPF :Mask. */ +#define ADxST_HPF_IDLE ((uint32_t)0x00000000) /*!< HPF :Idle. */ +#define ADxST_HPF_RUN ((uint32_t)0x00000001) /*!< HPF :Running. */ +/** + * @} + */ /* End of group ADxST */ + +/** + * @defgroup ADxMOD0 ADxMOD0. + * @brief ADxMOD0 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | RCUT | + * | 0 | DACON | + * @{ + */ +/* RCUT */ +#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */ +#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */ +/* DACON */ +#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */ +#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */ +/** + * @} + */ /* End of group ADxMOD0 */ + +/** + * @name ADxCMPEN Macro Definition. + * @brief ADxCMPEN Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | CMP3EN | + * | 2 | CMP2EN | + * | 1 | CMP1EN | + * | 0 | CMP0EN | + * @{ + */ +/* CMP3EN */ +#define ADxCMPEN_CMP3EN_DISABLE ((uint32_t)0x00000000) /*!< CMP3EN :Disable */ +#define ADxCMPEN_CMP3EN_ENABLE ((uint32_t)0x00000008) /*!< CMP3EN :Enable */ +/* CMP2EN */ +#define ADxCMPEN_CMP2EN_DISABLE ((uint32_t)0x00000000) /*!< CMP2EN :Disable */ +#define ADxCMPEN_CMP2EN_ENABLE ((uint32_t)0x00000004) /*!< CMP2EN :Enable */ +/* CMP1EN */ +#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */ +#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */ +/* CMP0EN */ +#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */ +#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */ +/** + * @} + */ /* End of name ADxCMPEN Macro Definition */ + +/** + * @name ADxTSETn Macro Definition. + * @brief ADxTSETn Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ENINT0 | + * | 6-5 | TRGS0[1:0] | + * | 4-0 | AINST0[4:0]| + * @{ + */ +/* ENINT0 */ +#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */ +#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */ +#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */ +/* TRGS0[1:0] */ +#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */ +#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000100) /*!< TRGS :Continuation */ +#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000200) /*!< TRGS :Single */ +#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000300) /*!< TRGS :Universal Trigger */ +#define ADxTSETn_TRGS_PRI ((uint32_t)0x00000400) /*!< TRGS :Priority Trigger */ +/** + * @} + */ /* End of name ADxTSETn Macro Definition */ + +/** + * @name ADxREGn Macro Definition. + * @brief ADxREGn Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-30 | - | + * | 29 | ADOVRF_Mn | + * | 28 | ADRF_Mn | + * | 27-16 | ADR_Mn[11:0] | + * | 15-4 | ADRn[11:0] | + * | 3-2 | - | + * | 1 | ADOVRFn | + * | 0 | ADRFn | + * @{ + */ +/* ADOVRF_Mn */ +#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */ +#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ +#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */ +/* ADRF_Mn */ +#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */ +#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */ +#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */ +/* ADR_Mn */ +#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */ +/* ADRn */ +#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */ +/* ADOVRFn */ +#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */ +#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ +#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */ +/* ADRFn */ +#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */ +#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */ +#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */ +/** + * @} + */ /* End of name ADxREGn Macro Definition */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_functions ADC Private Functions + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group ADC_Private_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_INCLUDE_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h new file mode 100644 index 0000000..2abb195 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_cg.h @@ -0,0 +1,111 @@ +/** + ******************************************************************************* + * @file txz_cg.h + * @brief This file provides all the functions prototypes for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __CG_H +#define __CG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup CG CG + * @brief CG Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_typedef CG Exported Typedef + * @{ + */ +/** + * @brief CG member. +*/ +/*----------------------------------*/ +typedef struct { + TSB_CG_TypeDef *p_instance; /*!< Registers base address. */ +} cg_t; + +/** + * @} + */ /* End of group CG_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ +uint32_t cg_get_fsysm(cg_t *p_obj); +uint32_t cg_get_phyt0(cg_t *p_obj); +uint32_t cg_get_mphyt0(cg_t *p_obj); +TXZ_Result cg_ihosc_enable(cg_t *p_obj); +TXZ_Result cg_ihosc_disable(cg_t *p_obj); +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __CG_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_driver_def.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_driver_def.h new file mode 100644 index 0000000..95428ec --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_driver_def.h @@ -0,0 +1,96 @@ +/** + ******************************************************************************* + * @file txz_driver_def.h + * @brief All common macro and definition for TXZ peripheral drivers + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TXZ_DRIVER_DEF_H +#define __TXZ_DRIVER_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF + * @brief All common macro and definition for TXZ peripheral drivers + * @{ + */ + +/** @defgroup Device_Header_Included Device Header Included + * @brief Include the Device header file of a Target. + * @{ + */ +#include "TMPM4GR.h" /*!< TMPM4GR Header file. */ + +/** + * @} + */ /* End of group Device_Header */ + + +/** @defgroup TXZ_Exported_typedef TXZ Exported typedef + * @{ + */ +typedef enum { + TXZ_SUCCESS = 0U, + TXZ_ERROR = 1U +} TXZ_Result; + +typedef enum { + TXZ_BUSY = 0U, + TXZ_DONE = 1U +} TXZ_WorkState; + +typedef enum { + TXZ_DISABLE = 0U, + TXZ_ENABLE = 1U +} TXZ_FunctionalState; +/** + * @} + */ /* End of group TXZ_Exported_typedef */ + +/** @defgroup TXZ_Exported_macro TXZ Exported macro + * @{ + */ +#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) + +/** + * @brief To report the name of the source file and source line number where the + * assert_param error has occurred, "__DEBUG__" must be defined. And detailed + * definition of assert_failed() is needed to be implemented, which can be + * done, for example, in the main.c file. + */ +#ifdef __DEBUG__ +void assert_failed(char *file, int32_t line); +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) +#else +#define assert_param(expr) +#endif /* __DEBUG__ */ +/** + * @} + */ /* End of group TXZ_Exported_macro */ + +/** + * @} + */ /* End of group Periph_Driver */ + +/** + * @} + */ /* End of group TXZ_DRIVER_DEF */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h new file mode 100644 index 0000000..7477f13 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fc.h @@ -0,0 +1,136 @@ +/** + ******************************************************************************* + * @file txz_fc.h + * @brief This file provides all the functions prototypes for FLASH. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FC_H +#define __FC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +#if defined(__FC_H) +/** @addtogroup Periph driver + * @{ + */ + +/** @defgroup fc + * @brief fc + * @{ + */ + + +/** @defgroup FlashApi_Exported_Types + * @{ + */ + +/** + * @enum fc_sr0_t + * @brief Enumerated type definition of the FCSR0 register. + */ +typedef enum { + FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */ +} fc_sr0_t; + +/*----------------------------------*/ +/** + * @enum fc_erase_kind_t + * @brief FC Erase Flash Kind structure definenition. +*/ +/*----------------------------------*/ +typedef enum { + FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */ + FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Block Erase */ +} fc_erase_kind_t; + +typedef enum { + FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */ + FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */ + FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */ + FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */ + FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */ + FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */ + FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */ + FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */ + FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */ + FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */ + FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */ + FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */ + FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */ + FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */ + FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */ + FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */ + FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */ + FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */ + FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */ + FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */ + FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */ + FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */ + FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */ + FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */ + FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */ + FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */ + FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */ + FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */ + FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */ + FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */ + FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */ + FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */ +} fc_code_flash_page_number_t; + +/** @} */ +/* End of group FlashApi_Exported_Types */ + +/** @defgroup FlashApi_Exported_Constants + * @{ + */ + +//#define FC_RAMADDRESSTOP (0x20000000UL) /*!< RAM Address Top */ +//#define FC_RAMADDRESSEND (0x20003fffUL) /*!< RAM Address End */ +#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */ +//#define FC_CODEFLASHADDRESSEND (0x5E01FFFFUL) /*!< CODE FLASH Address End */ +#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */ +//#define FC_CODEFLASHPAGESIZE (0x1000) /*!< CODE FLASH PAGE SIZE */ +#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */ + +/** @} */ +/* End of group FlashApi_Exported_Constants */ + + + +/** @weakgroup FlashApi_Exported_FunctionPrototypes + * @{ + */ +TXZ_WorkState fc_get_status(fc_sr0_t status); +TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages); +TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page); +TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr); + +/** @} */ +/* End of group FlashApi_Exported_FunctionPrototypes */ + + +/** @} */ +/* End of group fc */ + +/** @} */ +/* End of group Periph_driver */ + +#endif /* defined(__FC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FC_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_flash.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_flash.h new file mode 100644 index 0000000..110a5f1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_flash.h @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * @file txz_flash.h + * @brief This file provides all the functions prototypes for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FLASH_H +#define __FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup FLASH FLASH + * @brief FLASH Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_macro FLASH Exported Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_define FLASH Exported Define + * @{ + */ +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_define FLASH Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_typedef FLASH Exported Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_functions FLASH Exported Functions + * @{ + */ + +void fc_read_clock_set(uint32_t sysclock); + +/** + * @} + */ /* End of group FLASH_Exported_functions */ + +/** + * @} + */ /* End of group FLASH */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FLASH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart.h new file mode 100644 index 0000000..313c4d0 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart.h @@ -0,0 +1,542 @@ +/** + ******************************************************************************* + * @file txz_fuart.h + * @brief This file provides all the functions prototypes for FUART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_H +#define __FUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup FUART FUART + * @brief FUART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_define FUART Exported Define + * @{ + */ + +/** + * @defgroup FUART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define FUART_TX_FIFO_MAX ((uint32_t)0x00000020) /*!< TX FIFO Max. */ +#define FUART_RX_FIFO_MAX ((uint32_t)0x00000020) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup FUART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definition. + * @{ + */ +#define FUART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_CTS_ENABLE ((uint32_t)0x00008000) /*!< Available. */ +/** + * @} + */ /* End of group FUART_CTSHandshake */ + + +/** + * @defgroup FUART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definition. + * @{ + */ +#define FUART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_RTS_ENABLE ((uint32_t)0x00004000) /*!< Available. */ +/** + * @} + */ /* End of group FUART_RTSHandshake */ + +/** + * @defgroup FUART_FIFO FIFO Enable + * @brief FIFO Enable Bit Macro Definition. + * @{ + */ +#define FUART_FIFO_DISABLE ((uint32_t)0x00000000) /*!< Disable. */ +#define FUART_FIFO_ENABLE ((uint32_t)0x00000010) /*!< Enable. */ +/** + * @} + */ /* End of group FUART_FIFO */ + + +/** + * @defgroup FUART_StopBit Stop Bit + * @brief Stop Bit Macro Definition. + * @{ + */ +#define FUART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define FUART_STOP_BIT_2 ((uint32_t)0x00000008) /*!< 2 bit */ +/** + * @} + */ /* End of group FUART_StopBit */ + + +/** + * @defgroup FUART_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define FUART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define FUART_PARITY_BIT_EVEN ((uint32_t)0x00000004) /*!< Even Parity */ +/** + * @} + */ /* End of group FUART_ParityBit */ + + +/** + * @defgroup FUART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define FUART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group FUART_ParityEnable */ + +/** + * @defgroup FUART_StaticParityEnable Static Parity Enable + * @brief Enable/Disable Static Parity Macro Definition. + * @{ + */ +#define FUART_STATIC_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_STATIC_PARITY_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group FUART_ParityEnable */ + +/** + * @defgroup FUART_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define FUART_DATA_LENGTH_5 ((uint32_t)0x00000000) /*!< 5 bit */ +#define FUART_DATA_LENGTH_6 ((uint32_t)0x00000020) /*!< 6 bit */ +#define FUART_DATA_LENGTH_7 ((uint32_t)0x00000040) /*!< 7 bit */ +#define FUART_DATA_LENGTH_8 ((uint32_t)0x00000060) /*!< 8 bit */ +/** + * @} + */ /* End of group FUART_DataLength */ + +/** + * @defgroup FUART_FIFO_Level FIFO Level + * @brief FIFO Level Macro Definition. + * @{ + */ +#define FUART_FIFO_LEVEL_4 ((uint32_t)0x00000000) /*!< 4 level */ +#define FUART_FIFO_LEVEL_8 ((uint32_t)0x00000001) /*!< 8 level */ +#define FUART_FIFO_LEVEL_16 ((uint32_t)0x00000002) /*!< 16 level */ +#define FUART_FIFO_LEVEL_24 ((uint32_t)0x00000003) /*!< 24 level */ +#define FUART_FIFO_LEVEL_28 ((uint32_t)0x00000004) /*!< 28 level */ + +/** + * @} + */ /* End of group FUART_DataLength */ + +/** + * @defgroup FUART_TxInterrupt Tx Interrupt + * @brief Available Transmit Interrupt Macro Definition. + * @{ + */ +#define FUART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_TX_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group FUART_TxInterrupt */ + + +/** + * @defgroup FUART_RxInterrupt Rx Interrupt + * @brief Available Receive Interrupt Macro Definition. + * @{ + */ +#define FUART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group FUART_RxInterrupt */ + + +/** + * @defgroup FUART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +/** + * @defgroup FUART_OVER_RUN_ErrorInterrupt Over Run Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_OV_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_OV_ERR_INT_ENABLE ((uint32_t)0x00000400) /*!< Enable */ +/** + * @} + */ /* End of group FUART_OVER_RUN_ErrorInterrupt */ + +/** + * @defgroup FUART_BREAK_ErrorInterrupt Break Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_BK_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_BK_ERR_INT_ENABLE ((uint32_t)0x00000200) /*!< Enable */ +/** + * @} + */ /* End of group FUART_BREAK_ErrorInterrupt */ + +/** + * @defgroup FUART_PARITY_ErrorInterrupt Parity Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_PA_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_PA_ERR_INT_ENABLE ((uint32_t)0x00000100) /*!< Enable */ +/** + * @} + */ /* End of group FUART_PARITY_ErrorInterrupt */ + +/** + * @defgroup FUART_FRAMING_ErrorInterrupt Framing Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_FR_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_FR_ERR_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group FUART_FRAMING_ErrorInterrupt */ + +/** + * @defgroup FUART_RX_TIMEOUT_ErrorInterrupt Rx Timeout Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_TO_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_TO_ERR_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group FUART_RX_TIMEOUT_RUN_ErrorInterrupt */ +/** + * @} + */ /* End of group FUART_ErrorInterrupt */ + + +/** + * @defgroup FUART_RangeK Range K + * @brief Range of K Macro Definition. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= FUART_RANGE_K_MAX)". + * @{ + */ +#define FUART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define FUART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group FUART_RangeK */ + + +/** + * @defgroup FUART_RangeN Range N + * @brief Range of N Macro Definition. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= FUART_RANGE_N_MAX)". + * @{ + */ +#define FUART_RANGE_N_MIN ((uint32_t)0x00000002) /*!< Minimum Value :N=2 */ +#define FUART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group FUART_RangeN */ + + +/** + * @defgroup FUART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define FUART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group FUART_OverrunErr */ + + +/** + * @defgroup FUART_BreakErr Break Error + * @brief Break Error Macro Definition. + * @{ + */ +#define FUART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_BREAK_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group FUART_BreakErr */ + + +/** + * @defgroup FUART_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define FUART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_PARITY_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group FUART_ParityErr */ + + +/** + * @defgroup FUART_FramingErr Framing Error + * @brief Framing Error Macro Definition. + * @{ + */ +#define FUART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_FRAMING_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group FUART_FramingErr */ + +/** + * @defgroup FUARTxFR FUARTxFR Register + * @brief FUARTxFR Register Definition. + * @{ + */ +/* FR */ +#define FUARTxFR_TXFE_MASK ((uint32_t)0x00000080) /*!< TXFE :Mask */ +#define FUARTxFR_RXFF_MASK ((uint32_t)0x00000040) /*!< RXFF :Mask */ +#define FUARTxFR_TXFF_MASK ((uint32_t)0x00000020) /*!< TXFF :Mask */ +#define FUARTxFR_RXFE_MASK ((uint32_t)0x00000010) /*!< RXFE :Mask */ +#define FUARTxFR_BUSY_MASK ((uint32_t)0x00000008) /*!< BUSY :Mask */ +#define FUARTxFR_CTS_MASK ((uint32_t)0x00000001) /*!< CTS :Mask */ + +#define FUARTxFR_TXFE_FLAG_SET ((uint32_t)0x00000080) /*!< TXFE :Flag Set */ +#define FUARTxFR_RXFF_FLAG_SET ((uint32_t)0x00000040) /*!< RXFF :Flag Set */ +#define FUARTxFR_TXFF_FLAG_SET ((uint32_t)0x00000020) /*!< TXFF :Flag Set */ +#define FUARTxFR_RXFE_FLAG_SET ((uint32_t)0x00000010) /*!< RXFE :Flag Set */ +#define FUARTxFR_BUSY_FLAG_SET ((uint32_t)0x00000008) /*!< BUSY :Flag Set */ +#define FUARTxFR_CTS_FLAG_SET ((uint32_t)0x00000001) /*!< CTS :Flag Set */ + +#define FUARTxFR_TXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFE :Flag Clear */ +#define FUARTxFR_RXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFF :Flag Clear */ +#define FUARTxFR_TXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFF :Flag Clear */ +#define FUARTxFR_RXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFE :Flag Clear */ +#define FUARTxFR_BUSY_FLAG_CLR ((uint32_t)0x00000000) /*!< BUSY :Flag Clear */ +#define FUARTxFR_CTS_FLAG_CLR ((uint32_t)0x00000000) /*!< CTS :Flag Clear */ +/** + * @} + */ /* End of group FUARTxFR */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_define FUART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_typedef FUART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} fuart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} fuart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brk; /*!< Division Value K. + : K Range ( FUART_RANGE_K_MIN <= K =< FUART_RANGE_K_MAX ) @ref FUART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( FUART_RANGE_N_MIN <= N =< FUART_RANGE_N_MAX ) @ref FUART_RangeN */ +} fuart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref FUART_TxInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Use @ref FUART_FIFO_Level */ +} fuart_tx_int_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref FUART_RxInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Use @ref FUART_FIFO_Level */ +} fuart_rx_int_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + fuart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref fuart_boudrate_t */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref FUART_ErrorInterrupt */ + fuart_tx_int_t tx_int; /*!< Transmit Interrupt setting. + : Use @ref fuart_tx_int_t */ + fuart_rx_int_t rx_int; /*!< Receive Interrupt setting. + : Use @ref fuart_rx_int_t */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref FUART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref FUART_RTSHandshake */ + uint32_t stpa; /*!< Enable/Disable Static Parity. + : Use @ref FUART_StaticParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref FUART_DataLength */ + uint32_t fifo; /*!< Available FIFO. + : Use @ref FUART_FIFO */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref FUART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref FUART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref FUART_ParityEnable */ +} fuart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief FUART handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_FURT_TypeDef *p_instance; /*!< Registers base address. */ + fuart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + fuart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + uint32_t wp; /*!< Num of received data. */ + fuart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, fuart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} fuart_t; + +/** + * @} + */ /* End of group FUART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_functions FUART Exported Functions + * @{ + */ +TXZ_Result fuart_init(fuart_t *p_obj); +TXZ_Result fuart_deinit(fuart_t *p_obj); +TXZ_Result fuart_discard_transmit(fuart_t *p_obj); +TXZ_Result fuart_discard_receive(fuart_t *p_obj); +TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info); +TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info); +void fuart_transmit_irq_handler(fuart_t *p_obj); +void fuart_receive_irq_handler(fuart_t *p_obj); +void fuart_error_irq_handler(fuart_t *p_obj); +void fuart_irq_handler(fuart_t *p_obj); +TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status); +TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error); +TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_setting); +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_ex.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_ex.h new file mode 100644 index 0000000..d35c9c3 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_ex.h @@ -0,0 +1,109 @@ +/** + ******************************************************************************* + * @file txz_fuart_ex.h + * @brief This file provides all the functions prototypes for FUART driver. + * @brief Extended functionality. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_EX_H +#define __FUART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_fuart.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +TXZ_Result fuart_send_break(fuart_t *p_obj); +TXZ_Result fuart_stop_break(fuart_t *p_obj); +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FUART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_include.h new file mode 100644 index 0000000..d4e3b95 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_fuart_include.h @@ -0,0 +1,385 @@ +/** + ******************************************************************************* + * @file txz_fuart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_INCLUDE_H +#define __FUART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/** + * @defgroup FUART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define FUART_NULL ((void *)0) /*!< Null Pointer. */ +/** + * @} + */ /* End of group FUART_NullPointer */ + +/** + * @defgroup FUART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define FUART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define FUART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group FUART_ParameterResult */ + +/** + * @defgroup FUARTxDR FUARTxDR Register + * @brief FUARTxDR Register Definition. + * @{ + */ +/* DR */ +#define FUARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of group FUARTxDR */ + +/** + * @defgroup FUARTxCR FUARTxCR Register + * @brief FUARTxCR Register Definition. + * @{ + */ +#define FUARTxCR_CTSEN_MASK ((uint32_t)0x00008000) /*!< CTSEN :MASK. */ +#define FUARTxCR_RTSEN_MASK ((uint32_t)0x00004000) /*!< RTSEN :MASK. */ +#define FUARTxCR_RXE_MASK ((uint32_t)0x00000200) /*!< RXE :MASK. */ +#define FUARTxCR_TXE_MASK ((uint32_t)0x00000100) /*!< TXE :MASK. */ +#define FUARTxCR_UARTEN_MSK ((uint32_t)0x00000001) /*!< UARTEN :MASK. */ + +#define FUARTxCR_CTSEN_DISABLE ((uint32_t)0x00000000) /*!< CTSEN :Not Available. */ +#define FUARTxCR_RTSEN_DISABLE ((uint32_t)0x00000000) /*!< RTSEN :Not Available. */ +#define FUARTxCR_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable. */ +#define FUARTxCR_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable. */ +#define FUARTxCR_UARTEN_DISABLE ((uint32_t)0x00000000) /*!< UARTEN :Disable. */ + +#define FUARTxCR_CTSEN_ENABLE ((uint32_t)0x00008000) /*!< CTSEN :Available. */ +#define FUARTxCR_RTSEN_ENABLE ((uint32_t)0x00004000) /*!< RTSEN :Available. */ +#define FUARTxCR_RXE_ENABLE ((uint32_t)0x00000200) /*!< RXE :Enable. */ +#define FUARTxCR_TXE_ENABLE ((uint32_t)0x00000100) /*!< TXE :Enable. */ +#define FUARTxCR_UARTEN_ENABLE ((uint32_t)0x00000001) /*!< UARTEN :Enable. */ +/** + * @} + */ /* End of group FUARTxRSR */ + +/** + * @defgroup FUARTxRSR FUARTxRSR Register + * @brief FUARTxRSR Register Definition. + * @{ + */ +#define FUARTxRSR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ +#define FUARTxRSR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ +#define FUARTxRSR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ +#define FUARTxRSR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ + +#define FUARTxRSR_OE_ERR ((uint32_t)0x00000008) /*!< OE :Error */ +#define FUARTxRSR_BE_ERR ((uint32_t)0x00000004) /*!< BE :Error */ +#define FUARTxRSR_PE_ERR ((uint32_t)0x00000002) /*!< PE :Error */ +#define FUARTxRSR_FE_ERR ((uint32_t)0x00000001) /*!< FE :Error */ +/** + * @} + */ /* End of group FUARTxRSR */ + +/** + * @defgroup FUARTxECR FUARTxECR Register + * @brief FUARTxECR Register Definition. + * @{ + */ +/* ECR */ +#define FUARTxECR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ +#define FUARTxECR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ +#define FUARTxECR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ +#define FUARTxECR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ + +#define FUARTxECR_OE_CLR ((uint32_t)0x00000008) /*!< OE :Clear */ +#define FUARTxECR_BE_CLR ((uint32_t)0x00000004) /*!< BE :Clear */ +#define FUARTxECR_PE_CLR ((uint32_t)0x00000002) /*!< PE :Clear */ +#define FUARTxECR_FE_CLR ((uint32_t)0x00000001) /*!< FE :Clear */ + +/** + * @} + */ /* End of group FUARTxECR */ + +/** + * @defgroup FUARTxLCR_H FUARTxRSR Register + * @brief FUARTxLCR_H Register Definition. + * @{ + */ +#define FUARTxLCR_H_BRK_MASK ((uint32_t)0x00000001) /*!< BRK :Mask */ + +#define FUARTxLCR_H_BRK_SEND ((uint32_t)0x00000001) /*!< BRK :Send */ +#define FUARTxLCR_H_BRK_STOP ((uint32_t)0x00000000) /*!< BRK :Stop */ +/** + * @} + */ /* End of group FUARTxLCR_H */ + +/** + * @defgroup FUARTxRIS FUARTxRIS Register + * @brief FUARTxRIS Register Definition. + * @{ + */ +#define FUARTxRIS_OERIS_MASK ((uint32_t)0x00000400) /*!< OERIS :Mask */ +#define FUARTxRIS_BERIS_MASK ((uint32_t)0x00000200) /*!< BERIS :Mask */ +#define FUARTxRIS_PERIS_MASK ((uint32_t)0x00000100) /*!< PRRIS :Mask */ +#define FUARTxRIS_FERIS_MASK ((uint32_t)0x00000080) /*!< FERIS :Mask */ +#define FUARTxRIS_RTRIS_MASK ((uint32_t)0x00000040) /*!< RTRIS :Mask */ +#define FUARTxRIS_TXRIS_MASK ((uint32_t)0x00000020) /*!< TXRIS :Mask */ +#define FUARTxRIS_RXRIS_MASK ((uint32_t)0x00000010) /*!< RXRIS :Mask */ + +#define FUARTxRIS_OERIS_REQ ((uint32_t)0x00000400) /*!< OERIS :Request */ +#define FUARTxRIS_BERIS_REQ ((uint32_t)0x00000200) /*!< BERIS :Request */ +#define FUARTxRIS_PERIS_REQ ((uint32_t)0x00000100) /*!< PRRIS :Request */ +#define FUARTxRIS_FERIS_REQ ((uint32_t)0x00000080) /*!< FERIS :Request */ +#define FUARTxRIS_RTRIS_REQ ((uint32_t)0x00000040) /*!< RTRIS :Request */ +#define FUARTxRIS_TXRIS_REQ ((uint32_t)0x00000020) /*!< TXRIS :Request */ +#define FUARTxRIS_RXRIS_REQ ((uint32_t)0x00000010) /*!< RXRIS :Request */ + +/** + * @} + */ /* End of group FUARTxRIS */ + +/** + * @defgroup FUARTxMIS FUARTxMIS Register + * @brief FUARTxMIS Register Definition. + * @{ + */ +#define FUARTxMIS_OEMIS_MASK ((uint32_t)0x00000400) /*!< OEMIS :Mask */ +#define FUARTxMIS_BEMIS_MASK ((uint32_t)0x00000200) /*!< BEMIS :Mask */ +#define FUARTxMIS_PEMIS_MASK ((uint32_t)0x00000100) /*!< PRMIS :Mask */ +#define FUARTxMIS_FEMIS_MASK ((uint32_t)0x00000080) /*!< FEMIS :Mask */ +#define FUARTxMIS_RTMIS_MASK ((uint32_t)0x00000040) /*!< RTMIS :Mask */ +#define FUARTxMIS_TXMIS_MASK ((uint32_t)0x00000020) /*!< TXMIS :Mask */ +#define FUARTxMIS_RXMIS_MASK ((uint32_t)0x00000010) /*!< RXMIS :Mask */ + +#define FUARTxMIS_OEMIS_REQ ((uint32_t)0x00000400) /*!< OEMIS :Request */ +#define FUARTxMIS_BEMIS_REQ ((uint32_t)0x00000200) /*!< BEMIS :Request */ +#define FUARTxMIS_PEMIS_REQ ((uint32_t)0x00000100) /*!< PRMIS :Request */ +#define FUARTxMIS_FEMIS_REQ ((uint32_t)0x00000080) /*!< FEMIS :Request */ +#define FUARTxMIS_RTMIS_REQ ((uint32_t)0x00000040) /*!< RTMIS :Request */ +#define FUARTxMIS_TXMIS_REQ ((uint32_t)0x00000020) /*!< TXMIS :Request */ +#define FUARTxMIS_RXMIS_REQ ((uint32_t)0x00000010) /*!< RXMIS :Request */ + +/** + * @} + */ /* End of group FUARTxMIS */ + +/** + * @defgroup FUARTxICR FUARTxICR Register + * @brief FUARTxICR Register Definition. + * @{ + */ +#define FUARTxICR_OEIC_MASK ((uint32_t)0x00000400) /*!< OEIC :Mask */ +#define FUARTxICR_BEIC_MASK ((uint32_t)0x00000200) /*!< BEIC :Mask */ +#define FUARTxICR_PEIC_MASK ((uint32_t)0x00000100) /*!< PRIC :Mask */ +#define FUARTxICR_FEIC_MASK ((uint32_t)0x00000080) /*!< FEIC :Mask */ +#define FUARTxICR_RTIC_MASK ((uint32_t)0x00000040) /*!< RTIC :Mask */ +#define FUARTxICR_TXIC_MASK ((uint32_t)0x00000020) /*!< TXIC :Mask */ +#define FUARTxICR_RXIC_MASK ((uint32_t)0x00000010) /*!< RXIC :Mask */ + +#define FUARTxICR_OEIC_CLR ((uint32_t)0x00000400) /*!< OEIC :Request */ +#define FUARTxICR_BEIC_CLR ((uint32_t)0x00000200) /*!< BEIC :Request */ +#define FUARTxICR_PEIC_CLR ((uint32_t)0x00000100) /*!< PRIC :Request */ +#define FUARTxICR_FEIC_CLR ((uint32_t)0x00000080) /*!< FEIC :Request */ +#define FUARTxICR_RTIC_CLR ((uint32_t)0x00000040) /*!< RTIC :Request */ +#define FUARTxICR_TXIC_CLR ((uint32_t)0x00000020) /*!< TXIC :Request */ +#define FUARTxICR_RXIC_CLR ((uint32_t)0x00000010) /*!< RXIC :Request */ + +/** + * @} + */ /* End of group FUARTxICR */ + +/** + * @defgroup FUARTxDMACR FUARTxDMACR Register + * @brief FUARTxDMACR Register Definition. + * @{ + */ +#define FUARTxDMACR_RXDMAE_MASK ((uint32_t)0x00000001) /*!< RXDMAE :Mask */ +#define FUARTxDMACR_TXDMAE_MASK ((uint32_t)0x00000002) /*!< TXDMAE :Mask */ + +#define FUARTxDMACR_RXDMAE_ENABLE ((uint32_t)0x00000001) /*!< RXDMAE :Enable */ +#define FUARTxDMACR_TXDMAE_ENABLE ((uint32_t)0x00000002) /*!< TXDMAE :Enable */ + +#define FUARTxDMACR_RXDMAE_DISABLE ((uint32_t)0x00000000) /*!< RXDMAE :Disable */ +#define FUARTxDMACR_TXDMAE_DISABLE ((uint32_t)0x00000000) /*!< TXDMAE :Disable */ +/** + * @} + */ /* End of group FUARTxDMACR */ + + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_functions + * @{ + */ +__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable FUARTxCR TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable FUARTxCR TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable FUARTxCR RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable FUARTxCR RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1; +#endif +} + + +/** + * @} + */ /* End of group FUART_Private_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio.h new file mode 100644 index 0000000..ce1926f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio.h @@ -0,0 +1,178 @@ +/** + ******************************************************************************* + * @file txz_gpio.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_H +#define __GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +/** @defgroup Device_Included Device Included + * @{ + */ +#include "txz_gpio_M4GR.h" + +/** + * @} + */ /* End of group Device_Included */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ +#define CHECK_MASK(mode, mask) ((1 << ((mode)/4)) & (mask)) +#define WRITE_PORT(mode, addr, val, mask) \ + do { \ + if(CHECK_MASK(mode, mask)) *((uint32_t*)(addr) + (mode)/4) = (val); \ + }while(0) +#define READ_PORT(mode, addr, val, mask) \ + do { \ + if(CHECK_MASK(mode, mask)) (*(val)) = (*((uint32_t*)(addr) + (mode)/4)); \ + }while(0) + +/** + * @defgroup GPIO_Result Result + * @brief GPIO Result Macro Definition. + * @{ + */ +#define GPIO_RESULT_SUCCESS (0) /*!< Success */ +#define GPIO_RESULT_FAILURE (-1) /*!< Failure */ +#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group GPIO_Result */ + +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_pinstate_t + * @brief Pin State Reset/Set Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_RESET = 0, /*!< 0: Clear */ + GPIO_PIN_SET, /*!< 1: Set */ +} gpio_pinstate_t; + +/** + * @enum gpio_pininout_t + * @brief Pin Input/Output Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_INPUT = 0, /*!< 0: Input */ + GPIO_PIN_OUTPUT, /*!< 1: Output */ + GPIO_PIN_INOUT, /*!< 2: Input/Output */ + GPIO_PIN_NOTINOUT, /*!< 3: Not Input/Output */ +} gpio_pininout_t; + +/** + * @enum gpio_mode_t + * @brief Port Mode Enumerated Type Definition. + */ +typedef enum { + GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */ + GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */ + GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */ + GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */ + GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */ + GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */ + GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */ + GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */ + GPIO_Mode_FR7 = 0x20, /*!< 0x20: PxFR7 */ + GPIO_Mode_FR8 = 0x24, /*!< 0x24: PxFR8 */ + GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */ + GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */ + GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */ + GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */ +} gpio_mode_t; + +/** + * @enum gpio_mode_num + * @brief Port Mode Enumerated Num(bit num). + */ +typedef enum { + GPIO_ModeNum_DATA = 0, /*!< 0: PxDATA */ + GPIO_ModeNum_CR, /*!< 1: PxCR */ + GPIO_ModeNum_FR1, /*!< 2: PxFR1 */ + GPIO_ModeNum_FR2, /*!< 3: PxFR2 */ + GPIO_ModeNum_FR3, /*!< 4: PxFR3 */ + GPIO_ModeNum_FR4, /*!< 5: PxFR4 */ + GPIO_ModeNum_FR5, /*!< 6: PxFR5 */ + GPIO_ModeNum_FR6, /*!< 7: PxFR6 */ + GPIO_ModeNum_FR7, /*!< 8: PxFR7 */ + GPIO_ModeNum_FR8, /*!< 9: PxFR8 */ + GPIO_ModeNum_OD, /*!< 10: PxOD */ + GPIO_ModeNum_PUP, /*!< 11: PxPUP */ + GPIO_ModeNum_PDN, /*!< 12: PxPDN */ + GPIO_ModeNum_IE, /*!< 13: PxIE */ + GPIO_ModeNum_Max, /*!< 14: Max */ +} gpio_mode_num; +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_functions GPIO Exported Functions + * @{ + */ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val); +TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout); +TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate); + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +#ifdef __cplusplus +} +#endif +#endif /* __GPIO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio_M4GR.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio_M4GR.h new file mode 100644 index 0000000..f42e9b7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_gpio_M4GR.h @@ -0,0 +1,2731 @@ +/** + ******************************************************************************* + * @file txz_gpio_M4GR.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_M4GR_H +#define __GPIO_M4GR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup GPIO GPIO + * @brief GPIO Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ +/*PinExist define*/ +/* PortA */ +#define GPIO_PORT_A_0 (0x3DDF) +#define GPIO_PORT_A_1 (0x3D57) +#define GPIO_PORT_A_2 (0x3D17) +#define GPIO_PORT_A_3 (0x3DDF) +#define GPIO_PORT_A_4 (0x3DDF) +#define GPIO_PORT_A_5 (0x3DD7) +#define GPIO_PORT_A_6 (0x3D97) +#define GPIO_PORT_A_7 (0x3DDF) +/* PortB */ +#define GPIO_PORT_B_0 (0x3C7F) +#define GPIO_PORT_B_1 (0x3CDF) +#define GPIO_PORT_B_2 (0x3C57) +#define GPIO_PORT_B_3 (0x3C17) +#define GPIO_PORT_B_4 (0x3C77) +#define GPIO_PORT_B_5 (0x3C37) +#define GPIO_PORT_B_6 (0x3C7F) +#define GPIO_PORT_B_7 (0x3C7F) +/* PortC */ +#define GPIO_PORT_C_0 (0x3C77) +#define GPIO_PORT_C_1 (0x3C77) +#define GPIO_PORT_C_2 (0x3C77) +#define GPIO_PORT_C_3 (0x3C37) +#define GPIO_PORT_C_4 (0x3C57) +#define GPIO_PORT_C_5 (0x3C17) +#define GPIO_PORT_C_6 (0x3C07) +#define GPIO_PORT_C_7 (0x3C07) +/* PortD */ +#define GPIO_PORT_D_0 (0x3DFF) +#define GPIO_PORT_D_1 (0x3D7F) +#define GPIO_PORT_D_2 (0x3F77) +#define GPIO_PORT_D_3 (0x3F37) +#define GPIO_PORT_D_4 (0x3FD7) +#define GPIO_PORT_D_5 (0x3F97) +#define GPIO_PORT_D_6 (0x3FDF) +#define GPIO_PORT_D_7 (0x3FDF) +/* PortE */ +#define GPIO_PORT_E_0 (0x3F7F) +#define GPIO_PORT_E_1 (0x3F77) +#define GPIO_PORT_E_2 (0x3F77) +#define GPIO_PORT_E_3 (0x3F77) +#define GPIO_PORT_E_4 (0x3EF7) +#define GPIO_PORT_E_5 (0x3EF7) +#define GPIO_PORT_E_6 (0x3EF7) +#define GPIO_PORT_E_7 (0x3EFF) +/* PortF */ +#define GPIO_PORT_F_0 (0x3C07) +#define GPIO_PORT_F_1 (0x3C07) +#define GPIO_PORT_F_2 (0x3D83) +#define GPIO_PORT_F_3 (0x3D83) +#define GPIO_PORT_F_4 (0x3C07) +#define GPIO_PORT_F_5 (0x3C07) +#define GPIO_PORT_F_6 (0x3C07) +#define GPIO_PORT_F_7 (0x3C67) +/* PortG */ +#define GPIO_PORT_G_0 (0x3C57) +#define GPIO_PORT_G_1 (0x3C57) +#define GPIO_PORT_G_2 (0x3DF3) +#define GPIO_PORT_G_3 (0x3DF3) +#define GPIO_PORT_G_4 (0x3DEB) +#define GPIO_PORT_G_5 (0x3DFB) +#define GPIO_PORT_G_6 (0x3CE7) +#define GPIO_PORT_G_7 (0x3C67) +/* PortH */ +#define GPIO_PORT_H_0 (0x3C77) +#define GPIO_PORT_H_1 (0x3C77) +#define GPIO_PORT_H_2 (0x3C77) +#define GPIO_PORT_H_3 (0x3C77) +#define GPIO_PORT_H_4 (0x3C57) +#define GPIO_PORT_H_5 (0x3C57) +#define GPIO_PORT_H_6 (0x3C57) +#define GPIO_PORT_H_7 (0x3C57) +/* PortJ */ +#define GPIO_PORT_J_0 (0x3C53) +#define GPIO_PORT_J_1 (0x3C53) +#define GPIO_PORT_J_2 (0x3DD3) +#define GPIO_PORT_J_3 (0x3DD3) +#define GPIO_PORT_J_4 (0x3C5B) +#define GPIO_PORT_J_5 (0x3C5B) +#define GPIO_PORT_J_6 (0x3DC3) +#define GPIO_PORT_J_7 (0x3DC3) +/* PortK */ +#define GPIO_PORT_K_0 (0x3C9F) +#define GPIO_PORT_K_1 (0x3CFF) +#define GPIO_PORT_K_2 (0x3C87) +#define GPIO_PORT_K_3 (0x3C87) +#define GPIO_PORT_K_4 (0x3CA7) +#define GPIO_PORT_K_5 (0x3CA7) +#define GPIO_PORT_K_6 (0x3CBF) +#define GPIO_PORT_K_7 (0x3DBB) +/* PortL */ +#define GPIO_PORT_L_0 (0x3DDB) +#define GPIO_PORT_L_1 (0x3D43) +#define GPIO_PORT_L_2 (0x3D43) +#define GPIO_PORT_L_3 (0x3DDB) +#define GPIO_PORT_L_4 (0x3C1B) +#define GPIO_PORT_L_5 (0x3C0B) +#define GPIO_PORT_L_6 (0x3C1B) +#define GPIO_PORT_L_7 (0x3C0F) +/* PortM */ +#define GPIO_PORT_M_0 (0x3DE7) +#define GPIO_PORT_M_1 (0x3DE7) +#define GPIO_PORT_M_2 (0x3DDB) +#define GPIO_PORT_M_3 (0x3DEB) +#define GPIO_PORT_M_4 (0x3DAB) +#define GPIO_PORT_M_5 (0x3D9B) +#define GPIO_PORT_M_6 (0x3DFF) +#define GPIO_PORT_M_7 (0x3DEF) +/* PortN */ +#define GPIO_PORT_N_0 (0x3C03) +#define GPIO_PORT_N_1 (0x3C03) +#define GPIO_PORT_N_2 (0x3C03) +#define GPIO_PORT_N_3 (0x3C03) +#define GPIO_PORT_N_4 (0x3C03) +#define GPIO_PORT_N_5 (0x3C03) +#define GPIO_PORT_N_6 (0x3C03) +#define GPIO_PORT_N_7 (0x3C03) +/* PortP */ +#define GPIO_PORT_P_0 (0x3C5B) +#define GPIO_PORT_P_1 (0x3C5B) +#define GPIO_PORT_P_2 (0x3C5B) +#define GPIO_PORT_P_3 (0x3C5B) +#define GPIO_PORT_P_4 (0x3C5B) +#define GPIO_PORT_P_5 (0x3C5B) +#define GPIO_PORT_P_6 (0x3C5B) +#define GPIO_PORT_P_7 (0x3C5B) +/* PortR */ +#define GPIO_PORT_R_0 (0x3C1B) +#define GPIO_PORT_R_1 (0x3C1B) +#define GPIO_PORT_R_2 (0x3C1B) +#define GPIO_PORT_R_3 (0x3C1B) +#define GPIO_PORT_R_4 (0x3C1B) +#define GPIO_PORT_R_5 (0x3C1B) +#define GPIO_PORT_R_6 (0x3C1B) +#define GPIO_PORT_R_7 (0x3C1B) +/* PortT */ +#define GPIO_PORT_T_0 (0x3C03) +#define GPIO_PORT_T_1 (0x3C03) +#define GPIO_PORT_T_2 (0x3D03) +#define GPIO_PORT_T_3 (0x3C9F) +#define GPIO_PORT_T_4 (0x3C03) +#define GPIO_PORT_T_5 (0x3C0B) +#define GPIO_PORT_T_6 (0x0000) +#define GPIO_PORT_T_7 (0x0000) +/* PortU */ +#define GPIO_PORT_U_0 (0x3D1B) +#define GPIO_PORT_U_1 (0x3D0B) +#define GPIO_PORT_U_2 (0x3D9B) +#define GPIO_PORT_U_3 (0x3D9B) +#define GPIO_PORT_U_4 (0x3D9B) +#define GPIO_PORT_U_5 (0x3D9B) +#define GPIO_PORT_U_6 (0x3D9B) +#define GPIO_PORT_U_7 (0x3D8B) +/* PortV */ +#define GPIO_PORT_V_0 (0x3DDB) +#define GPIO_PORT_V_1 (0x3DDB) +#define GPIO_PORT_V_2 (0x3DDB) +#define GPIO_PORT_V_3 (0x3DCB) +#define GPIO_PORT_V_4 (0x3DEF) +#define GPIO_PORT_V_5 (0x3DFF) +#define GPIO_PORT_V_6 (0x3D7B) +#define GPIO_PORT_V_7 (0x3DEB) +/* PortW */ +#define GPIO_PORT_W_0 (0x3CE3) +#define GPIO_PORT_W_1 (0x3D63) +#define GPIO_PORT_W_2 (0x3D63) +#define GPIO_PORT_W_3 (0x3C63) +#define GPIO_PORT_W_4 (0x3D53) +#define GPIO_PORT_W_5 (0x3D43) +#define GPIO_PORT_W_6 (0x3D43) +#define GPIO_PORT_W_7 (0x3D53) +/* PortY */ +#define GPIO_PORT_Y_0 (0x3801) +#define GPIO_PORT_Y_1 (0x3801) +#define GPIO_PORT_Y_2 (0x3801) +#define GPIO_PORT_Y_3 (0x3801) +#define GPIO_PORT_Y_4 (0x1C27) +#define GPIO_PORT_Y_5 (0x0000) +#define GPIO_PORT_Y_6 (0x0000) +#define GPIO_PORT_Y_7 (0x0000) + +/* Port Register setting */ +#define PORT_CLOCK_DISABLE_PORTA(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTB(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTC(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTD(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTE(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTF(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTG(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTH(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTJ(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTK(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTL(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTM(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTN(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTP(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTR(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTT(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTU(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTV(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTW(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTY(var) ((var) = 0U) + +#define PORT_CLOCK_ENABLE_PORTA(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTB(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTC(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTD(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTE(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTF(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTG(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTH(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTJ(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTK(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTL(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTM(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTN(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTP(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTR(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTT(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTU(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTV(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTW(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTY(var) ((var) = 1U) + +/* PortA */ +#define INIT_GPIO_PORT_A_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR4(var) +#define INIT_GPIO_PORT_A_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR8(var) +#define INIT_GPIO_PORT_A_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_IE(var) ((var) = 0x00) +/* PortB */ +#define INIT_GPIO_PORT_B_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR7(var) +#define INIT_GPIO_PORT_B_FR8(var) +#define INIT_GPIO_PORT_B_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_IE(var) ((var) = 0x00) +/* PortC */ +#define INIT_GPIO_PORT_C_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR2(var) +#define INIT_GPIO_PORT_C_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR6(var) +#define INIT_GPIO_PORT_C_FR7(var) +#define INIT_GPIO_PORT_C_FR8(var) +#define INIT_GPIO_PORT_C_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_IE(var) ((var) = 0x00) +/* PortD */ +#define INIT_GPIO_PORT_D_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_IE(var) ((var) = 0x00) +/* PortE */ +#define INIT_GPIO_PORT_E_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_IE(var) ((var) = 0x00) +/* PortF */ +#define INIT_GPIO_PORT_F_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR2(var) +#define INIT_GPIO_PORT_F_FR3(var) +#define INIT_GPIO_PORT_F_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR8(var) +#define INIT_GPIO_PORT_F_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_IE(var) ((var) = 0x00) +/* PortG */ +#define INIT_GPIO_PORT_G_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR8(var) +#define INIT_GPIO_PORT_G_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_IE(var) ((var) = 0x00) +/* PortH */ +#define INIT_GPIO_PORT_H_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_CR(var) ((var) = 0x50) +#define INIT_GPIO_PORT_H_FR1(var) ((var) = 0xF8) +#define INIT_GPIO_PORT_H_FR2(var) +#define INIT_GPIO_PORT_H_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR6(var) +#define INIT_GPIO_PORT_H_FR7(var) +#define INIT_GPIO_PORT_H_FR8(var) +#define INIT_GPIO_PORT_H_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_PUP(var) ((var) = 0x98) +#define INIT_GPIO_PORT_H_PDN(var) ((var) = 0x20) +#define INIT_GPIO_PORT_H_IE(var) ((var) = 0xB8) +/* PortJ */ +#define INIT_GPIO_PORT_J_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR1(var) +#define INIT_GPIO_PORT_J_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR4(var) +#define INIT_GPIO_PORT_J_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR8(var) +#define INIT_GPIO_PORT_J_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_IE(var) ((var) = 0x00) +/* PortK */ +#define INIT_GPIO_PORT_K_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR8(var) +#define INIT_GPIO_PORT_K_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_IE(var) ((var) = 0x00) +/* PortL */ +#define INIT_GPIO_PORT_L_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR4(var) +#define INIT_GPIO_PORT_L_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR8(var) +#define INIT_GPIO_PORT_L_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_IE(var) ((var) = 0x00) +/* PortM */ +#define INIT_GPIO_PORT_M_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR8(var) +#define INIT_GPIO_PORT_M_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_IE(var) ((var) = 0x00) +/* PortN */ +#define INIT_GPIO_PORT_N_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_FR1(var) +#define INIT_GPIO_PORT_N_FR2(var) +#define INIT_GPIO_PORT_N_FR3(var) +#define INIT_GPIO_PORT_N_FR4(var) +#define INIT_GPIO_PORT_N_FR5(var) +#define INIT_GPIO_PORT_N_FR6(var) +#define INIT_GPIO_PORT_N_FR7(var) +#define INIT_GPIO_PORT_N_FR8(var) +#define INIT_GPIO_PORT_N_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_IE(var) ((var) = 0x00) +/* PortP */ +#define INIT_GPIO_PORT_P_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR1(var) +#define INIT_GPIO_PORT_P_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR4(var) +#define INIT_GPIO_PORT_P_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR6(var) +#define INIT_GPIO_PORT_P_FR7(var) +#define INIT_GPIO_PORT_P_FR8(var) +#define INIT_GPIO_PORT_P_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_IE(var) ((var) = 0x00) +/* PortR */ +#define INIT_GPIO_PORT_R_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR1(var) +#define INIT_GPIO_PORT_R_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR4(var) +#define INIT_GPIO_PORT_R_FR5(var) +#define INIT_GPIO_PORT_R_FR6(var) +#define INIT_GPIO_PORT_R_FR7(var) +#define INIT_GPIO_PORT_R_FR8(var) +#define INIT_GPIO_PORT_R_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_IE(var) ((var) = 0x00) +/* PortT */ +#define INIT_GPIO_PORT_T_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR4(var) +#define INIT_GPIO_PORT_T_FR5(var) +#define INIT_GPIO_PORT_T_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR8(var) +#define INIT_GPIO_PORT_T_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_IE(var) ((var) = 0x00) +/* PortU */ +#define INIT_GPIO_PORT_U_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR1(var) +#define INIT_GPIO_PORT_U_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR4(var) +#define INIT_GPIO_PORT_U_FR5(var) +#define INIT_GPIO_PORT_U_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR8(var) +#define INIT_GPIO_PORT_U_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_IE(var) ((var) = 0x00) +/* PortV */ +#define INIT_GPIO_PORT_V_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR8(var) +#define INIT_GPIO_PORT_V_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_IE(var) ((var) = 0x00) +/* PortW */ +#define INIT_GPIO_PORT_W_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR1(var) +#define INIT_GPIO_PORT_W_FR2(var) +#define INIT_GPIO_PORT_W_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR8(var) +#define INIT_GPIO_PORT_W_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_IE(var) ((var) = 0x00) +/* PortY */ +#define INIT_GPIO_PORT_Y_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR2(var) +#define INIT_GPIO_PORT_Y_FR3(var) +#define INIT_GPIO_PORT_Y_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR5(var) +#define INIT_GPIO_PORT_Y_FR6(var) +#define INIT_GPIO_PORT_Y_FR7(var) +#define INIT_GPIO_PORT_Y_FR8(var) +#define INIT_GPIO_PORT_Y_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_IE(var) ((var) = 0x00) +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_gr_t + * @brief Port Group Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_A = 0x0, /*!< 0: PA */ + GPIO_PORT_B, /*!< 1: PB */ + GPIO_PORT_C, /*!< 2: PC */ + GPIO_PORT_D, /*!< 3: PD */ + GPIO_PORT_E, /*!< 4: PE */ + GPIO_PORT_F, /*!< 5: PF */ + GPIO_PORT_G, /*!< 6: PG */ + GPIO_PORT_H, /*!< 7: PH */ + GPIO_PORT_J, /*!< 8: PJ */ + GPIO_PORT_K, /*!< 9: PK */ + GPIO_PORT_L, /*!< 10:PL */ + GPIO_PORT_M, /*!< 11: PM */ + GPIO_PORT_N, /*!< 12: PN */ + GPIO_PORT_P, /*!< 13: PP */ + GPIO_PORT_R, /*!< 14: PR */ + GPIO_PORT_T, /*!< 15: PT */ + GPIO_PORT_U, /*!< 16: PU */ + GPIO_PORT_V, /*!< 17: PV */ + GPIO_PORT_W, /*!< 18: PW */ + GPIO_PORT_Y, /*!< 19: PY */ + GPIO_GROUP_Max /*!< Max Number */ +} gpio_gr_t; + +/** + * @enum gpio_num_t + * @brief Port Number Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_0 = 0x0, /*!< 0: Port0 */ + GPIO_PORT_1, /*!< 1: Port1 */ + GPIO_PORT_2, /*!< 2: Port2 */ + GPIO_PORT_3, /*!< 3: Port3 */ + GPIO_PORT_4, /*!< 4: Port4 */ + GPIO_PORT_5, /*!< 5: Port5 */ + GPIO_PORT_6, /*!< 6: Port6 */ + GPIO_PORT_7, /*!< 7: Port7 */ + GPIO_PORT_Max /*!< Max Number */ +} gpio_num_t; + +/** + * @enum gpio_fr_t + * @brief Port Function Number Enumerated Type Definition. + */ +typedef enum { + GPIO_FR_1 = 1, /*!< 1: PxFR1 */ + GPIO_FR_2, /*!< 2: PxFR2 */ + GPIO_FR_3, /*!< 3: PxFR3 */ + GPIO_FR_4, /*!< 4: PxFR4 */ + GPIO_FR_5, /*!< 5: PxFR5 */ + GPIO_FR_6, /*!< 6: PxFR6 */ + GPIO_FR_7, /*!< 7: PxFR7 */ + GPIO_FR_8, /*!< 8: PxFR8 */ + GPIO_FR_NA, /*!< 9: N/A */ + GPIO_FR_Max, /*!< Max Number */ +} gpio_fr_t; + +/** + * @enum gpio_pa0_func_t + * @brief PortA0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA0_INT02a = 0, /*!< 0: INT02a */ + GPIO_PA0_EA00 = GPIO_FR_1, /*!< PAFR1: EA00 */ + GPIO_PA0_T32A00INB1 = GPIO_FR_2, /*!< PAFR2: T32A00INB1 */ + GPIO_PA0_T32A00INA0 = GPIO_FR_3, /*!< PAFR3: T32A00INA0 */ + GPIO_PA0_T32A00INC0 = GPIO_FR_5, /*!< PAFR5: T32A00INC0 */ + GPIO_PA0_TSPI0CSIN = GPIO_FR_6, /*!< PAFR6: TSPI0CSIN */ + GPIO_PA0_TSPI0CS0 = GPIO_FR_7, /*!< PAFR7: TSPI0CS0 */ +} gpio_pa0_func_t; + +/** + * @enum gpio_pa1_func_t + * @brief PortA1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA1_EA01 = GPIO_FR_1, /*!< PAFR1: EA01 */ + GPIO_PA1_T32A00OUTA = GPIO_FR_3, /*!< PAFR3: T32A00OUTA */ + GPIO_PA1_T32A00OUTC = GPIO_FR_5, /*!< PAFR5: T32A00OUTC */ + GPIO_PA1_TSPI0SCK = GPIO_FR_7, /*!< PAFR7: TSPI0SCK */ +} gpio_pa1_func_t; + +/** + * @enum gpio_pa2_func_t + * @brief PortA2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA2_EA02 = GPIO_FR_1, /*!< PAFR1: EA02 */ + GPIO_PA2_T32A00OUTB = GPIO_FR_3, /*!< PAFR3: T32A00OUTB */ + GPIO_PA2_TSPI0RXD = GPIO_FR_7, /*!< PAFR7: TSPI0RXD */ +} gpio_pa2_func_t; + +/** +* @enum gpio_pa3_func_t +* @brief PortA3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PA3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA3_EA03 = GPIO_FR_1, /*!< PAFR1: EA03 */ + GPIO_PA3_T32A00INA1 = GPIO_FR_2, /*!< PAFR2: T32A00INA1 */ + GPIO_PA3_T32A00INB0 = GPIO_FR_3, /*!< PAFR3: T32A00INB0 */ + GPIO_PA3_T32A00INC1 = GPIO_FR_5, /*!< PAFR5: T32A00INC1 */ + GPIO_PA3_TSPI2CS1 = GPIO_FR_6, /*!< PAFR6: TSPI2CS1 */ + GPIO_PA3_TSPI0TXD = GPIO_FR_7, /*!< PAFR7: TSPI0TXD */ +} gpio_pa3_func_t; + +/** +* @enum gpio_pa4_func_t +* @brief PortA4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PA4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA4_EA04 = GPIO_FR_1, /*!< PAFR1: EA04 */ + GPIO_PA4_T32A01INB1 = GPIO_FR_2, /*!< PAFR2: T32A01INB1 */ + GPIO_PA4_T32A01INA0 = GPIO_FR_3, /*!< PAFR3: T32A01INA0 */ + GPIO_PA4_T32A01INC0 = GPIO_FR_5, /*!< PAFR5: T32A01INC0 */ + GPIO_PA4_TSPI0CS1 = GPIO_FR_6, /*!< PAFR6: TSPI0CS1 */ + GPIO_PA4_TSPI2TXD = GPIO_FR_7, /*!< PAFR7: TSPI2TXD */ +} gpio_pa4_func_t; + +/** + * @enum gpio_pa5_func_t + * @brief PortA5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA5_EA05 = GPIO_FR_1, /*!< PAFR1: EA05 */ + GPIO_PA5_T32A01OUTA = GPIO_FR_3, /*!< PAFR3: T32A01OUTA */ + GPIO_PA5_T32A01OUTC = GPIO_FR_5, /*!< PAFR5: T32A01OUTC */ + GPIO_PA5_TSPI0CS2 = GPIO_FR_6, /*!< PAFR6: TSPI0CS2 */ + GPIO_PA5_TSPI2RXD = GPIO_FR_7, /*!< PAFR7: TSPI2RXD */ +} gpio_pa5_func_t; + +/** + * @enum gpio_pa6_func_t + * @brief PortA6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA6_EA06 = GPIO_FR_1, /*!< PAFR1: EA06 */ + GPIO_PA6_T32A01OUTB = GPIO_FR_3, /*!< PAFR3: T32A01OUTB */ + GPIO_PA6_TSPI0CS3 = GPIO_FR_6, /*!< PAFR6: TSPI0CS3 */ + GPIO_PA6_TSPI2SCK = GPIO_FR_7, /*!< PAFR7: TSPI2SCK */ +} gpio_pa6_func_t; + + +/** + * @enum gpio_pa7_func_t + * @brief PortA6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA7_INT03a = 0, /*!< 0: INT03a */ + GPIO_PA7_EA07 = GPIO_FR_1, /*!< PAFR1: EA07 */ + GPIO_PA7_T32A01INA1 = GPIO_FR_2, /*!< PAFR2: T32A01INA1 */ + GPIO_PA7_T32A01INB0 = GPIO_FR_3, /*!< PAFR3: T32A01INB0 */ + GPIO_PA7_T32A01INC1 = GPIO_FR_5, /*!< PAFR5: T32A01INC1 */ + GPIO_PA7_TSPI2CSIN = GPIO_FR_6, /*!< PAFR6: TSPI2CSIN */ + GPIO_PA7_TSPI2CS0 = GPIO_FR_7, /*!< PAFR7: TSPI2CS0 */ +} gpio_pa7_func_t; + + + +/** + * @enum gpio_pb0_func_t + * @brief PortB0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB0_INT04a = 0, /*!< 0: INT04a */ + GPIO_PB0_EA08 = GPIO_FR_1, /*!< PBFR1: EA08 */ + GPIO_PB0_T32A02INB1 = GPIO_FR_2, /*!< PBFR2: T32A02INB1 */ + GPIO_PB0_T32A02INA0 = GPIO_FR_3, /*!< PBFR3: T32A02INA0 */ + GPIO_PB0_I2S0MCKIO = GPIO_FR_4, /*!< PBFR4: I2S0MCKI/O */ + GPIO_PB0_T32A02INC0 = GPIO_FR_5, /*!< PBFR5: T32A02INC0 */ +} gpio_pb0_func_t; + +/** + * @enum gpio_pb1_func_t + * @brief PortB1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB1_INT05a = 0, /*!< 0: INT05a */ + GPIO_PB1_EA09 = GPIO_FR_1, /*!< PBFR1: EA09 */ + GPIO_PB1_T32A02INA1 = GPIO_FR_2, /*!< PBFR2: T32A02INA1 */ + GPIO_PB1_T32A02INB0 = GPIO_FR_3, /*!< PBFR3: T32A02INB0 */ + GPIO_PB1_T32A02INC1 = GPIO_FR_5, /*!< PBFR5: T32A02INC1 */ + GPIO_PB1_HDMAREQA = GPIO_FR_6, /*!< PBFR6: HDMAREQA */ +} gpio_pb1_func_t; + +/** + * @enum gpio_pb2_func_t + * @brief PortB2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB2_EA10 = GPIO_FR_1, /*!< PBFR1: EA10 */ + GPIO_PB2_T32A02OUTA = GPIO_FR_3, /*!< PBFR3: T32A02OUTA */ + GPIO_PB2_T32A02OUTC = GPIO_FR_5, /*!< PBFR5: T32A02OUTC */ +} gpio_pb2_func_t; + +/** +* @enum gpio_pb3_func_t +* @brief PortB3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PB3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB3_EA11 = GPIO_FR_1, /*!< PBFR1: EA11 */ + GPIO_PB3_T32A02OUTB = GPIO_FR_3, /*!< PBFR3: T32A02OUTB */ +} gpio_pb3_func_t; + +/** +* @enum gpio_pb4_func_t +* @brief PortB4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PB4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB4_EA12 = GPIO_FR_1, /*!< PBFR1: EA12 */ + GPIO_PB4_T32A03OUTA = GPIO_FR_3, /*!< PBFR3: T32A03OUTA */ + GPIO_PB4_I2S0LRCK = GPIO_FR_4, /*!< PBFR4: I2S0LRCK */ + GPIO_PB4_T32A03OUTC = GPIO_FR_5, /*!< PBFR5: T32A03OUTC */ +} gpio_pb4_func_t; + +/** + * @enum gpio_pb5_func_t + * @brief PortB5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB5_EA13 = GPIO_FR_1, /*!< PBFR1: EA13 */ + GPIO_PB5_T32A03OUTB = GPIO_FR_3, /*!< PBFR3: T32A03OUTB */ + GPIO_PB5_I2S0BCK = GPIO_FR_4, /*!< PBFR4: I2S0BCK */ +} gpio_pb5_func_t; + +/** + * @enum gpio_pb6_func_t + * @brief PortB6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB6_INT06a = 0, /*!< 0: INT06a */ + GPIO_PB6_EA14 = GPIO_FR_1, /*!< PBFR1: EA14 */ + GPIO_PB6_T32A03INB1 = GPIO_FR_2, /*!< PBFR2: T32A03INB1 */ + GPIO_PB6_T32A03INA0 = GPIO_FR_3, /*!< PBFR3: T32A03INA0 */ + GPIO_PB6_I2S0DI = GPIO_FR_4, /*!< PBFR4: I2S0DI */ + GPIO_PB6_T32A03INC0 = GPIO_FR_5, /*!< PBFR5: T32A03INC0 */ +} gpio_pb6_func_t; + +/** + * @enum gpio_pb7_func_t + * @brief PortB7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB7_INT07a = 0, /*!< 0: INT07a */ + GPIO_PB7_EA15 = GPIO_FR_1, /*!< PBFR1: EA15 */ + GPIO_PB7_T32A03INA1 = GPIO_FR_2, /*!< PBFR2: T32A03INA1 */ + GPIO_PB7_T32A03INB0 = GPIO_FR_3, /*!< PBFR3: T32A03INB0 */ + GPIO_PB7_I2S0DO = GPIO_FR_4, /*!< PBFR4: I2S0DO */ + GPIO_PB7_T32A03INC1 = GPIO_FR_5, /*!< PBFR5: T32A03INC1 */ +} gpio_pb7_func_t; + +/** + * @enum gpio_pc0_func_t + * @brief PortC0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC0_INT12a = 0, /*!< 0: INT12a */ + GPIO_PC0_EA16 = GPIO_FR_1, /*!< PCFR1: EA16 */ + GPIO_PC0_T32A08INA0 = GPIO_FR_3, /*!< PCFR3: T32A08INA0 */ + GPIO_PC0_I2S1DO = GPIO_FR_4, /*!< PCFR4: I2S1DO */ + GPIO_PC0_T32A08INC0 = GPIO_FR_5, /*!< PCFR5: T32A08INC0 */ +} gpio_pc0_func_t; + +/** + * @enum gpio_pc1_func_t + * @brief PortC1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC1_INT13a = 0, /*!< 0: INT13a */ + GPIO_PC1_EA17 = GPIO_FR_1, /*!< PCFR1: EA17 */ + GPIO_PC1_T32A08INB0 = GPIO_FR_3, /*!< PCFR3: T32A08INB0 */ + GPIO_PC1_I2S1DI = GPIO_FR_4, /*!< PCFR4: I2S1DI */ + GPIO_PC1_T32A08INC1 = GPIO_FR_5, /*!< PCFR5: T32A08INC1 */ +} gpio_pc1_func_t; + +/** + * @enum gpio_pc2_func_t + * @brief PortC2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC2_EA18 = GPIO_FR_1, /*!< PCFR1: UT4TXDB */ + GPIO_PC2_T32A08OUTA = GPIO_FR_3, /*!< PCFR3: T32A08OUTA */ + GPIO_PC2_I2S1BCK = GPIO_FR_4, /*!< PCFR4: I2S1BCK */ + GPIO_PC2_T32A08OUTC = GPIO_FR_5, /*!< PCFR5: T32A08OUTC */ +} gpio_pc2_func_t; + +/** +* @enum gpio_pc3_func_t +* @brief PortC3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PC3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC3_EA19 = GPIO_FR_1, /*!< PCFR1: EA19 */ + GPIO_PC3_T32A08OUTB = GPIO_FR_3, /*!< PCFR3: T32A08OUTB */ + GPIO_PC3_I2S1LRCK = GPIO_FR_4, /*!< PCFR4: I2S1LRCK */ +} gpio_pc3_func_t; + +/** +* @enum gpio_pc4_func_t +* @brief PortC4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PC4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC4_EA20 = GPIO_FR_1, /*!< PCFR1: EA20 */ + GPIO_PC4_T32A10OUTA = GPIO_FR_3, /*!< PCFR3: T32A10OUTA */ + GPIO_PC4_T32A10OUTC = GPIO_FR_5, /*!< PCFR5: T32A10OUTC */ +} gpio_pc4_func_t; + +/** + * @enum gpio_pc5_func_t + * @brief PortC5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC5_EA21 = GPIO_FR_1, /*!< PCFR1: EA21 */ + GPIO_PC5_T32A10OUTB = GPIO_FR_3, /*!< PCFR3: T32A10OUTB */ +} gpio_pc5_func_t; + +/** + * @enum gpio_pc6_func_t + * @brief PortC6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC6_INT14a = 0, /*!< 0: INT14a */ + GPIO_PC6_EA22 = GPIO_FR_1, /*!< PCFR1: EA22 */ +} gpio_pc6_func_t; + +/** + * @enum gpio_pc7_func_t + * @brief PortC7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC7_INT15a = 0, /*!< 0: INT15a */ + GPIO_PC7_EA23 = GPIO_FR_1, /*!< PCFR1: EA23 */ +} gpio_pc7_func_t; + +/** + * @enum gpio_pd0_func_t + * @brief PortD0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD0_ED00 = GPIO_FR_1, /*!< PCFR1: ED00 */ + GPIO_PD0_T32A04INB1 = GPIO_FR_2, /*!< PCFR2: T32A04INB1 */ + GPIO_PD0_T32A04INA0 = GPIO_FR_3, /*!< PCFR3: T32A04INA0 */ + GPIO_PD0_TSPI4CS0 = GPIO_FR_4, /*!< PCFR4: TSPI4CS0 */ + GPIO_PD0_T32A04INC0 = GPIO_FR_5, /*!< PCFR5: T32A04INC0 */ + GPIO_PD0_TSPI4CSIN = GPIO_FR_6, /*!< PCFR6: TSPI4CSIN */ + GPIO_PD0_UO0 = GPIO_FR_7, /*!< PCFR7: UO0 */ +} gpio_pd0_func_t; + +/** + * @enum gpio_pd1_func_t + * @brief PortD1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD1_ED01 = GPIO_FR_1, /*!< PCFR1: ED01 */ + GPIO_PD1_T32A04INA1 = GPIO_FR_2, /*!< PCFR2: T32A04INA1 */ + GPIO_PD1_T32A04INB0 = GPIO_FR_3, /*!< PCFR3: T32A04INB0 */ + GPIO_PD1_TSPI4SCK = GPIO_FR_4, /*!< PCFR4: TSPI4SCK */ + GPIO_PD1_T32A04INC1 = GPIO_FR_5, /*!< PCFR5: T32A04INC1 */ + GPIO_PD1_XO0 = GPIO_FR_7, /*!< PCFR7: XO0 */ +} gpio_pd1_func_t; + +/** + * @enum gpio_pd2_func_t + * @brief PortD2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD2_ED02 = GPIO_FR_1, /*!< PCFR1: ED02 */ + GPIO_PD2_T32A04OUTA = GPIO_FR_3, /*!< PCFR3: T32A04OUTA */ + GPIO_PD2_TSPI4RXD = GPIO_FR_4, /*!< PCFR4: TSPI4RXD */ + GPIO_PD2_T32A04OUTC = GPIO_FR_5, /*!< PCFR5: T32A04OUTC */ + GPIO_PD2_VO0 = GPIO_FR_7, /*!< PCFR7: VO0 */ + GPIO_PD2_TSSI0TCK = GPIO_FR_8, /*!< PCFR8: TSSI0TCK */ +} gpio_pd2_func_t; + +/** +* @enum gpio_pd3_func_t +* @brief PortD3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PD3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD3_ED03 = GPIO_FR_1, /*!< PCFR1: ED03 */ + GPIO_PD3_T32A04OUTB = GPIO_FR_3, /*!< PCFR3: T32A04OUTB */ + GPIO_PD3_TSPI4TXD = GPIO_FR_4, /*!< PCFR4: TSPI4TXD */ + GPIO_PD3_YO0 = GPIO_FR_7, /*!< PCFR7: YO0 */ + GPIO_PD3_TSSI0TFS = GPIO_FR_8, /*!< PCFR8: TSSI0TFS */ +} gpio_pd3_func_t; + +/** + * @enum gpio_pd4_func_t + * @brief PortD4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD4_ED04 = GPIO_FR_1, /*!< PCFR1: ED04 */ + GPIO_PD4_T32A05OUTA = GPIO_FR_3, /*!< PCFR3: T32A05OUTA */ + GPIO_PD4_T32A05OUTC = GPIO_FR_5, /*!< PCFR5: T32A05OUTC */ + GPIO_PD4_I2S0LRCK = GPIO_FR_6, /*!< PCFR6: I2S0LRCK */ + GPIO_PD4_WO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ + GPIO_PD4_TSSI0TXD = GPIO_FR_8, /*!< PCFR8: TSSI0TXD */ +} gpio_pd4_func_t; + +/** + * @enum gpio_pd5_func_t + * @brief PortD5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD5_ED05 = GPIO_FR_1, /*!< PCFR1: ED05 */ + GPIO_PD5_T32A05OUTB = GPIO_FR_3, /*!< PCFR3: T32A05OUTB */ + GPIO_PD5_I2S0BCK = GPIO_FR_6, /*!< PCFR6: I2S0BCK */ + GPIO_PD5_ZO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ + GPIO_PD5_TSSI0RXD = GPIO_FR_8, /*!< PCFR8: TSSI0RXD */ +} gpio_pd5_func_t; + +/** + * @enum gpio_pd6_func_t + * @brief PortD6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD6_ED06 = GPIO_FR_1, /*!< PCFR1: ED06 */ + GPIO_PD6_T32A05INB1 = GPIO_FR_2, /*!< PCFR2: T32A05INB1 */ + GPIO_PD6_T32A05INA0 = GPIO_FR_3, /*!< PCFR3: T32A05INA0 */ + GPIO_PD6_T32A05INC0 = GPIO_FR_5, /*!< PCFR5: T32A05INC0 */ + GPIO_PD6_I2S0DI = GPIO_FR_6, /*!< PCFR6: I2S0DI */ + GPIO_PD6_EMG0 = GPIO_FR_7, /*!< PCFR7: EMG0 */ + GPIO_PD6_TSSI0RFS = GPIO_FR_8, /*!< PCFR8: TSSI0RFS */ +} gpio_pd6_func_t; + +/** + * @enum gpio_pd7_func_t + * @brief PortD7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD7_ED07 = GPIO_FR_1, /*!< PCFR1: ED07 */ + GPIO_PD7_T32A05INA1 = GPIO_FR_2, /*!< PCFR2: T32A05INA1 */ + GPIO_PD7_T32A05INB0 = GPIO_FR_3, /*!< PCFR3: T32A05INB0 */ + GPIO_PD7_T32A05INC1 = GPIO_FR_5, /*!< PCFR5: T32A05INC1 */ + GPIO_PD7_I2S0DO = GPIO_FR_6, /*!< PCFR6: I2S0DO */ + GPIO_PD7_OVV0 = GPIO_FR_7, /*!< PCFR7: OVV0 */ + GPIO_PD7_TSSI0RCK = GPIO_FR_8, /*!< PCFR8: TSSI0RCK */ +} gpio_pd7_func_t; + +/** + * @enum gpio_pe0_func_t + * @brief PortE0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE0_ED08 = GPIO_FR_1, /*!< PCFR1: ED08 */ + GPIO_PE0_T32A06INB1 = GPIO_FR_2, /*!< PCFR2: T32A06INB1 */ + GPIO_PE0_T32A06OUTB = GPIO_FR_3, /*!< PCFR3: T32A06OUTB */ + GPIO_PE0_EA23 = GPIO_FR_4, /*!< PCFR4: EA23 */ + GPIO_PE0_T32A06INA1 = GPIO_FR_5, /*!< PCFR5: T32A06INA1 */ + GPIO_PE0_UT0RTS_N = GPIO_FR_7, /*!< PCFR7: UT0RTS_N */ + GPIO_PE0_EA15 = GPIO_FR_8, /*!< PCFR8: EA15 */ +} gpio_pe0_func_t; + +/** + * @enum gpio_pe1_func_t + * @brief PortE1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE1_ED09 = GPIO_FR_1, /*!< PCFR1: ED09 */ + GPIO_PE1_T32A06OUTA = GPIO_FR_3, /*!< PCFR3: T32A06OUTA */ + GPIO_PE1_EA22 = GPIO_FR_4, /*!< PCFR4: EA22 */ + GPIO_PE1_T32A06OUTC = GPIO_FR_5, /*!< PCFR5: T32A06OUTC */ + GPIO_PE1_UT0CTS_N = GPIO_FR_7, /*!< PCFR7: UT0CTS_N */ + GPIO_PE1_EA14 = GPIO_FR_8, /*!< PCFR8: EA14 */ +} gpio_pe1_func_t; + +/** + * @enum gpio_pe2_func_t + * @brief PortE2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE2_ED10 = GPIO_FR_1, /*!< PCFR1: ED10 */ + GPIO_PE2_T32A06INA0 = GPIO_FR_3, /*!< PCFR3: T32A06INA0 */ + GPIO_PE2_EA21 = GPIO_FR_4, /*!< PCFR4: EA21 */ + GPIO_PE2_T32A06INC0 = GPIO_FR_5, /*!< PCFR5: T32A06INC0 */ + GPIO_PE2_UT0RXD = GPIO_FR_7, /*!< PCFR7: UT0RXD */ + GPIO_PE2_EA13 = GPIO_FR_8, /*!< PCFR8: EA13 */ +} gpio_pe2_func_t; + +/** +* @enum gpio_pe3_func_t +* @brief PortE3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE3_ED11 = GPIO_FR_1, /*!< PCFR1: ED11 */ + GPIO_PE3_T32A06INB0 = GPIO_FR_3, /*!< PCFR3: T32A06INB0 */ + GPIO_PE3_EA20 = GPIO_FR_4, /*!< PCFR4: EA20 */ + GPIO_PE3_T32A06INC1 = GPIO_FR_5, /*!< PCFR5: T32A06INC1 */ + GPIO_PE3_UT0TXDA = GPIO_FR_7, /*!< PCFR7: UT0TXDA */ + GPIO_PE3_EA12 = GPIO_FR_8, /*!< PCFR8: EA12 */ +} gpio_pe3_func_t; + +/** +* @enum gpio_pe4_func_t +* @brief PortE4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE4_ED12 = GPIO_FR_1, /*!< PCFR1: ED12 */ + GPIO_PE4_T32A07INA0 = GPIO_FR_3, /*!< PCFR3: T32A07INA0 */ + GPIO_PE4_EA19 = GPIO_FR_4, /*!< PCFR4: EA19 */ + GPIO_PE4_T32A07INC0 = GPIO_FR_5, /*!< PCFR5: T32A07INC0 */ + GPIO_PE4_I2S1DO = GPIO_FR_6, /*!< PCFR6: I2S1DO */ + GPIO_PE4_ISDAIN0 = 0, /*!< 0: ISDAIN0 */ + GPIO_PE4_EA11 = GPIO_FR_8, /*!< PCFR8: EA11 */ +} gpio_pe4_func_t; + +/** + * @enum gpio_pe5_func_t + * @brief PortE5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE5_ED13 = GPIO_FR_1, /*!< PCFR1: ED13 */ + GPIO_PE5_T32A07INB0 = GPIO_FR_3, /*!< PCFR3: T32A07INB0 */ + GPIO_PE5_EA18 = GPIO_FR_4, /*!< PCFR4: EA18 */ + GPIO_PE5_T32A07INC1 = GPIO_FR_5, /*!< PCFR5: T32A07INC1 */ + GPIO_PE5_I2S1DI = GPIO_FR_6, /*!< PCFR6: I2S1DI */ + GPIO_PE5_ISDAIN1 = 0, /*!< 0: ISDAIN1 */ + GPIO_PE5_EA10 = GPIO_FR_8, /*!< PCFR8: EA10 */ +} gpio_pe5_func_t; + +/** + * @enum gpio_pe6_func_t + * @brief PortE6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE6_ED14 = GPIO_FR_1, /*!< PCFR1: ED14 */ + GPIO_PE6_T32A07OUTA = GPIO_FR_3, /*!< PCFR3: T32A07OUTA */ + GPIO_PE6_EA17 = GPIO_FR_4, /*!< PCFR4: EA17 */ + GPIO_PE6_T32A07OUTC = GPIO_FR_5, /*!< PCFR5: T32A07OUTC */ + GPIO_PE6_I2S1BCK = GPIO_FR_6, /*!< PCFR6: I2S1BCK */ + GPIO_PE6_ISDAIN2 = 0, /*!< 0: ISDAIN2 */ + GPIO_PE6_EA09 = GPIO_FR_8, /*!< PCFR8: EA09 */ +} gpio_pe6_func_t; + +/** + * @enum gpio_pe7_func_t + * @brief PortE7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE7_ED15 = GPIO_FR_1, /*!< PCFR1: ED15 */ + GPIO_PE7_T32A07INB1 = GPIO_FR_2, /*!< PCFR2: T32A07INB1 */ + GPIO_PE7_T32A07OUTB = GPIO_FR_3, /*!< PCFR3: T32A07OUTB */ + GPIO_PE7_EA16 = GPIO_FR_4, /*!< PCFR4: EA16 */ + GPIO_PE7_T32A07INA1 = GPIO_FR_5, /*!< PCFR5: T32A07INA1 */ + GPIO_PE7_I2S1LRCK = GPIO_FR_6, /*!< PCFR6: I2S1LRCK */ + GPIO_PE7_ISDAIN3 = 0, /*!< 0: ISDAIN3 */ + GPIO_PE7_EA08 = GPIO_FR_8, /*!< PCFR8: EA08 */ +} gpio_pe7_func_t; + +/** + * @enum gpio_pf0_func_t + * @brief PortF0 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF0_INT04b = 0, /*!< 0: INT04b */ + GPIO_PF0_ERD_N = GPIO_FR_1, /*!< PCFR1: ERD_N */ +} gpio_pf0_func_t; + +/** + * @enum gpio_pf1_func_t + * @brief PortF1 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF1_EWR_N = GPIO_FR_1, /*!< PCFR1: EWR_N */ +} gpio_pf1_func_t; + +/** + * @enum gpio_pf2_func_t + * @brief PortF2 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF2_EI2C1SDA = GPIO_FR_6, /*!< PCFR6: EI2C1SDA */ + GPIO_PF2_I2C1SDA = GPIO_FR_7, /*!< PCFR7: I2C1SDA */ +} gpio_pf2_func_t; + +/** +* @enum gpio_pf3_func_t +* @brief PortF3 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF3_EI2C1SCL = GPIO_FR_6, /*!< PCFR6: EI2C1SCL */ + GPIO_PF3_I2C1SCL = GPIO_FR_7, /*!< PCFR7: I2C1SCL */ +} gpio_pf3_func_t; + +/** +* @enum gpio_pf4_func_t +* @brief PortF4 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF4_ECS2_N = GPIO_FR_1, /*!< PCFR1: ECS2_N */ +} gpio_pf4_func_t; + +/** +* @enum gpio_pf5_func_t +* @brief PortF5 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF5_ECS3_N = GPIO_FR_1, /*!< PCFR1: ECS3_N */ +} gpio_pf5_func_t; + +/** +* @enum gpio_pf6_func_t +* @brief PortF6 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF6_EBELL_N = GPIO_FR_1, /*!< PCFR1: EBELL_N */ +} gpio_pf6_func_t; + +/** +* @enum gpio_pf7_func_t +* @brief PortF7 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF7_INT05b = 0, /*!< 0: INT05b */ + GPIO_PF7_EBELH_N = GPIO_FR_1, /*!< PCFR1: EBELH_N */ + GPIO_PF7_TSPI2CSIN = GPIO_FR_4, /*!< PCFR4: TSPI2CSIN */ + GPIO_PF7_TSPI2CS0 = GPIO_FR_5, /*!< PCFR5: TSPI2CS0 */ +} gpio_pf7_func_t; + +/** + * @enum gpio_pg0_func_t + * @brief PortG0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG0_INT08a = 0, /*!< 0: INT08a */ + GPIO_PG0_EALE = GPIO_FR_1, /*!< PCFR1: EALE */ + GPIO_PG0_UT2RXD = GPIO_FR_3, /*!< PCFR3: UT2RXD */ + GPIO_PG0_UT2TXDA = GPIO_FR_5, /*!< PCFR5: UT2TXDA */ +} gpio_pg0_func_t; + +/** + * @enum gpio_pg1_func_t + * @brief PortG1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG1_INT09a = 0, /*!< 0: INT09a */ + GPIO_PG1_EWAIT_N = GPIO_FR_1, /*!< PCFR1: EWAIT_N */ + GPIO_PG1_UT2TXDA = GPIO_FR_3, /*!< PCFR3: UT2TXDA */ + GPIO_PG1_UT2RXD = GPIO_FR_5, /*!< PCFR5: UT2RXD */ +} gpio_pg1_func_t; + +/** + * @enum gpio_pg2_func_t + * @brief PortG2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG2_UT2RTS_N = GPIO_FR_3, /*!< PCFR3: UT2RTS_N */ + GPIO_PG2_ALARM_N = GPIO_FR_4, /*!< PCFR4: ALARM_N */ + GPIO_PG2_UT2CTS_N = GPIO_FR_5, /*!< PCFR5: UT2CTS_N */ + GPIO_PG2_EI2C0SDA = GPIO_FR_6, /*!< PCFR6: EI2C0SDA */ + GPIO_PG2_I2C0SDA = GPIO_FR_7, /*!< PCFR7: I2C0SDA */ +} gpio_pg2_func_t; + +/** + * @enum gpio_pg3_func_t + * @brief PortG3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG3_UT2CTS_N = GPIO_FR_3, /*!< PCFR3: UT2CTS_N */ + GPIO_PG3_TRGIN0 = GPIO_FR_4, /*!< PCFR4: TRGIN0 */ + GPIO_PG3_UT2RTS_N = GPIO_FR_5, /*!< PCFR5: UT2RTS_N */ + GPIO_PG3_EI2C0SCL = GPIO_FR_6, /*!< PCFR6: EI2C0SCL */ + GPIO_PG3_I2C0SCL = GPIO_FR_7, /*!< PCFR7: I2C0SCL */ +} gpio_pg3_func_t; + +/** + * @enum gpio_pg4_func_t + * @brief PortG4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG4_T32A02OUTB = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ + GPIO_PG4_FUT0IROUT = GPIO_FR_4, /*!< PCF41: FUT0IROUT */ + GPIO_PG4_FUT0TXD = GPIO_FR_5, /*!< PCFR5: FUT0TXD */ + GPIO_PG4_EI2C2SDA = GPIO_FR_6, /*!< PCFR6: EI2C2SDA */ + GPIO_PG4_I2C2SDA = GPIO_FR_7, /*!< PCFR7: I2C2SDA */ +} gpio_pg4_func_t; + +/** + * @enum gpio_pg5_func_t + * @brief PortG5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG5_T32A02OUTA = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ + GPIO_PG5_T32A02OUTC = GPIO_FR_3, /*!< PCFR3: T32A02OUTC */ + GPIO_PG5_FUT0IRIN = GPIO_FR_4, /*!< PCFR4: FUT0IRIN */ + GPIO_PG5_FUT0RXD = GPIO_FR_5, /*!< PCFR5: FUT0RXD */ + GPIO_PG5_EI2C2SCL = GPIO_FR_6, /*!< PCFR6: EI2C2SCL */ + GPIO_PG5_I2C2SCL = GPIO_FR_7, /*!< PCFR7: I2C2SCL */ +} gpio_pg5_func_t; + +/** + * @enum gpio_pg6_func_t + * @brief PortG6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG6_TRACECLK = GPIO_FR_1, /*!< PCFR1: TRACECLK */ + GPIO_PG6_NBDCLK = GPIO_FR_4, /*!< PCFR4: NBDCLK */ + GPIO_PG6_FUT0RTS_N = GPIO_FR_5, /*!< PCFR5: FUT0RTS_N */ + GPIO_PG6_I2S1MCKIO = GPIO_FR_6, /*!< PCFR6: I2S1MCKIO */ +} gpio_pg6_func_t; + +/** + * @enum gpio_pg7_func_t + * @brief PortG7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG7_TRACEDATA0 = GPIO_FR_1, /*!< PCFR1: TRACEDATA0 */ + GPIO_PG7_NBDDATA0 = GPIO_FR_4, /*!< PCFR4: NBDDATA0 */ + GPIO_PG7_FUT0CTS_N = GPIO_FR_5, /*!< PCFR5: FUT0CTS_N */ +} gpio_pg7_func_t; + +/** + * @enum gpio_ph0_func_t + * @brief PortH0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH0_TRACEDATA1 = GPIO_FR_1, /*!< PCFR1: TRACEDATA1 */ + GPIO_PH0_UT1RXD = GPIO_FR_3, /*!< PCFR3: UT1RXD */ + GPIO_PH0_NBDDATA1 = GPIO_FR_4, /*!< PCFR4: NBDDATA1 */ + GPIO_PH0_UT1TXDA = GPIO_FR_5, /*!< PCFR5: UT1TXDA */ +} gpio_ph0_func_t; + +/** + * @enum gpio_ph1_func_t + * @brief PortH1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH1_TRACEDATA2 = GPIO_FR_1, /*!< PCFR1: TRACEDATA2 */ + GPIO_PH1_UT1TXDA = GPIO_FR_3, /*!< PCFR3: UT1TXDA */ + GPIO_PH1_NBDDATA2 = GPIO_FR_4, /*!< PCFR4: NBDDATA2 */ + GPIO_PH1_UT1RXD = GPIO_FR_5, /*!< PCFR5: UT1RXD */ +} gpio_ph1_func_t; + +/** + * @enum gpio_ph2_func_t + * @brief PortH2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH2_TRACEDATA3 = GPIO_FR_1, /*!< PCFR1: TRACEDATA3 */ + GPIO_PH2_UT1RTS_N = GPIO_FR_3, /*!< PCFR3: UT1RTS_N */ + GPIO_PH2_NBDDATA3 = GPIO_FR_4, /*!< PCFR4: NBDDATA3 */ + GPIO_PH2_UT1CTS_N = GPIO_FR_5, /*!< PCFR5: UT1CTS_N */ +} gpio_ph2_func_t; + +/** +* @enum gpio_ph3_func_t +* @brief PortH3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH3_TDI = GPIO_FR_1, /*!< PCFR1: TDI */ + GPIO_PH3_UT1CTS_N = GPIO_FR_3, /*!< PCFR3: UT1CTS_N */ + GPIO_PH3_NBDSYNC = GPIO_FR_4, /*!< PCFR4: NBDSYNC */ + GPIO_PH3_UT1RTS_N = GPIO_FR_5, /*!< PCFR5: UT1RTS_N */ +} gpio_ph3_func_t; + +/** +* @enum gpio_ph4_func_t +* @brief PortH4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH4_SWDIO = GPIO_FR_1, /*!< PCFR1: SWDIO */ + GPIO_PH4_UT0RXD = GPIO_FR_3, /*!< PCFR3: UT0RXD */ + GPIO_PH4_UT0TXDA = GPIO_FR_5, /*!< PCFR5: UT0TXDA */ +} gpio_ph4_func_t; + +/** +* @enum gpio_ph5_func_t +* @brief PortH5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH5_TCK = GPIO_FR_1, /*!< PCFR1: TCK */ + GPIO_PH5_UT0TXDA = GPIO_FR_3, /*!< PCFR3: UT0TXDA */ + GPIO_PH5_UT0RXD = GPIO_FR_5, /*!< PCFR5: UT0RXD */ +} gpio_ph5_func_t; + +/** +* @enum gpio_ph6_func_t +* @brief PortH6 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH6_TDO = GPIO_FR_1, /*!< PCFR1: TDO */ + GPIO_PH6_UT0RTS_N = GPIO_FR_3, /*!< PCFR3: UT0RTS_N */ + GPIO_PH6_UT0CTS_N = GPIO_FR_5, /*!< PCFR5: UT0CTS_N */ +} gpio_ph6_func_t; + +/** +* @enum gpio_ph7_func_t +* @brief PortH7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH7_TRST_N = GPIO_FR_1, /*!< PCFR1: TRST_N */ + GPIO_PH7_UT0CTS_N = GPIO_FR_3, /*!< PCFR3: UT0CTS_N */ + GPIO_PH7_UT0RTS_N = GPIO_FR_5, /*!< PCFR5: UT0RTS_N */ +} gpio_ph7_func_t; + +/** + * @enum gpio_pj0_func_t + * @brief PortJ0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ0_UT5RXD = GPIO_FR_3, /*!< PJFR3: UT5RXD */ + GPIO_PJ0_UT5TXDA = GPIO_FR_5, /*!< PJFR5: UT5TXDA */ +} gpio_pj0_func_t; + +/** + * @enum gpio_pj1_func_t + * @brief PortJ1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ1_UT5TXDA = GPIO_FR_3, /*!< PJFR3: UT5TXDA */ + GPIO_PJ1_UT5RXD = GPIO_FR_5, /*!< PJFR5: UT5RXD */ +} gpio_pj1_func_t; + +/** + * @enum gpio_pj2_func_t + * @brief PortJ2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ2_UT5RTS_N = GPIO_FR_3, /*!< PJFR3: UT5RTS_N */ + GPIO_PJ2_UT5CTS_N = GPIO_FR_5, /*!< PJFR5: UT5CTS_N */ + GPIO_PJ2_EI2C4SCL = GPIO_FR_6, /*!< PJFR6: EI2C4SCL */ + GPIO_PJ2_I2C4SCL = GPIO_FR_7, /*!< PJFR7: I2C4SCL */ +} gpio_pj2_func_t; + +/** +* @enum gpio_pj3_func_t +* @brief PortJ3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ3_UT5CTS_N = GPIO_FR_3, /*!< PJFR3: UT5CTS_N */ + GPIO_PJ3_UT5RTS_N = GPIO_FR_5, /*!< PJFR5: UT5RTS_N */ + GPIO_PJ3_EI2C4SDA = GPIO_FR_6, /*!< PJFR6: EI2C4SDA */ + GPIO_PJ3_I2C4SDA = GPIO_FR_7, /*!< PJFR7: I2C4SDA */ +} gpio_pj3_func_t; + +/** +* @enum gpio_pj4_func_t +* @brief PortJ4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ4_T32A03INA0 = GPIO_FR_2, /*!< PJFR2: T32A03INA0 */ + GPIO_PJ4_T32A03INC0 = GPIO_FR_3, /*!< PJFR3: T32A03INC0 */ + GPIO_PJ4_FUT0TXD = GPIO_FR_5, /*!< PJFR5: FUT0TXD */ +} gpio_pj4_func_t; + +/** + * @enum gpio_pj5_func_t + * @brief PortJ5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ5_T32A03INB0 = GPIO_FR_2, /*!< PJFR2: T32A03INB0 */ + GPIO_PJ5_T32A03INC1 = GPIO_FR_3, /*!< PJFR3: T32A03INC1 */ + GPIO_PJ5_FUT0RXD = GPIO_FR_5, /*!< PJFR5: FUT0RXD */ +} gpio_pj5_func_t; + +/** + * @enum gpio_pj6_func_t + * @brief PortJ6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ6_FUT1TXD = GPIO_FR_5, /*!< PJFR5: FUT1TXD */ + GPIO_PJ6_EI2C3SDA = GPIO_FR_6, /*!< PJFR6: EI2C3SDA */ + GPIO_PJ6_I2C3SDA = GPIO_FR_7, /*!< PJFR7: I2C3SDA */ +} gpio_pj6_func_t; + +/** + * @enum gpio_pj7_func_t + * @brief PortJ7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ7_FUT1RXD = GPIO_FR_5, /*!< PJFR5: FUT1RXD */ + GPIO_PJ7_EI2C3SCL = GPIO_FR_6, /*!< PJFR6: EI2C3SCL */ + GPIO_PJ7_I2C3SCL = GPIO_FR_7, /*!< PJFR7: I2C3SCL */ +} gpio_pj7_func_t; + +/** + * @enum gpio_pk0_func_t + * @brief PortK0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK0_INT10a = 0, /*!< 0: INT10a */ + GPIO_PK0_ISDAOUT = GPIO_FR_1, /*!< PKFR1: ISDAOUT */ + GPIO_PK0_T32A00INA0 = GPIO_FR_2, /*!< PKFR2: T32A00INA0 */ + GPIO_PK0_T32A00INC0 = GPIO_FR_3, /*!< PKFR3: T32A00INC0 */ + GPIO_PK0_SMI0CS1_N = GPIO_FR_6, /*!< PKFR6: ISDAOUT */ +} gpio_pk0_func_t; + +/** + * @enum gpio_pk1_func_t + * @brief PortK1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK1_INT11a = 0, /*!< 0: INT11a */ + GPIO_PK1_ISDBOUT = GPIO_FR_1, /*!< PKFR1: ISDBOUT */ + GPIO_PK1_T32A00INB0 = GPIO_FR_2, /*!< PKFR2: T32A00INB0 */ + GPIO_PK1_T32A00INC1 = GPIO_FR_3, /*!< PKFR3: T32A00INC1 */ + GPIO_PK1_HDMAREQB = GPIO_FR_4, /*!< PKFR4: HDMAREQB */ + GPIO_PK1_TSPI3CS0 = GPIO_FR_5, /*!< PKFR5: TSPI3CS0 */ + GPIO_PK1_TSPI3CSIN = GPIO_FR_6, /*!< PKFR6: TSPI3CSIN */ +} gpio_pk1_func_t; + +/** + * @enum gpio_pk2_func_t + * @brief PortK2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK2_ECS0_N = GPIO_FR_1, /*!< PKFR1: ECS0_N */ + GPIO_PK2_SMI0D0 = GPIO_FR_6, /*!< PKFR6: SMI0D0 */ +} gpio_pk2_func_t; + +/** +* @enum gpio_pk3_func_t +* @brief PortK3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK3_ECS1_N = GPIO_FR_1, /*!< PKFR1: ECS1_N */ + GPIO_PK3_SMI0D1 = GPIO_FR_6, /*!< PKFR6: SMI0D1 */ +} gpio_pk3_func_t; + +/** +* @enum gpio_pk4_func_t +* @brief PortK4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK4_TSPI1CS1 = GPIO_FR_1, /*!< PKFR1: TSPI1CS1 */ + GPIO_PK4_TSPI3TXD = GPIO_FR_4, /*!< PKFR4: TSPI3TXD */ + GPIO_PK4_SMI0D2 = GPIO_FR_6, /*!< PKFR6: SMI0D2 */ +} gpio_pk4_func_t; + +/** + * @enum gpio_pk5_func_t + * @brief PortK5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK5_TSPI1CS2 = GPIO_FR_1, /*!< PKFR1: TSPI1CS2 */ + GPIO_PK5_TSPI3RXD = GPIO_FR_4, /*!< PKFR4: TSPI3RXD */ + GPIO_PK5_SMI0D3 = GPIO_FR_6, /*!< PKFR6: SMI0D3 */ +} gpio_pk5_func_t; + +/** + * @enum gpio_pk6_func_t + * @brief PortK6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK6_TSPI1CS3 = GPIO_FR_1, /*!< PKFR1: TSPI1CS3 */ + GPIO_PK6_T32A01INA0 = GPIO_FR_2, /*!< PKFR2: T32A01INA0 */ + GPIO_PK6_T32A01INC0 = GPIO_FR_3, /*!< PKFR3: T32A01INC0 */ + GPIO_PK6_TSPI3SCK = GPIO_FR_4, /*!< PKFR4: TSPI3SCK */ + GPIO_PK6_SMI0CLK = GPIO_FR_6, /*!< PKFR6: SMI0CLK */ +} gpio_pk6_func_t; + +/** + * @enum gpio_pk7_func_t + * @brief PortK7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK7_INT00a = 0, /*!< 0: INT00a */ + GPIO_PK7_T32A01INB0 = GPIO_FR_2, /*!< PKFR2: T32A01INB0 */ + GPIO_PK7_T32A01INC1 = GPIO_FR_3, /*!< PKFR3: T32A01INC1 */ + GPIO_PK7_TSPI3CS0 = GPIO_FR_4, /*!< PKFR4: TSPI3CS0 */ + GPIO_PK7_SMI0CS0_N = GPIO_FR_6, /*!< PKFR6: SMI0CS0_N */ + GPIO_PK7_TSPI3CSIN = GPIO_FR_7, /*!< PKFR7: TSPI3CSIN */ +} gpio_pk7_func_t; + +/** + * @enum gpio_pl0_func_t + * @brief PortL0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL0_INT01a = 0, /*!< 0: INT01a */ + GPIO_PL0_T32A02INA0 = GPIO_FR_2, /*!< PLFR2: T32A02INA0 */ + GPIO_PL0_T32A02INC0 = GPIO_FR_3, /*!< PLFR3: T32A02INC0 */ + GPIO_PL0_SMI0D4 = GPIO_FR_5, /*!< PLFR5: SMI0D4 */ + GPIO_PL0_TSPI1CSIN = GPIO_FR_6, /*!< PLFR6: TSPI1CSIN */ + GPIO_PL0_TSPI1CS0 = GPIO_FR_7, /*!< PLFR7: TSPI1CS0 */ +} gpio_pl0_func_t; + +/** + * @enum gpio_pl1_func_t + * @brief PortL1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL1_SMI0D5 = GPIO_FR_5, /*!< PLFR5: SMI0D5 */ + GPIO_PL1_TSPI1SCK = GPIO_FR_7, /*!< PLFR7: TSPI1SCK */ +} gpio_pl1_func_t; + +/** + * @enum gpio_pl2_func_t + * @brief PortL2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL2_SMI0D6 = GPIO_FR_5, /*!< PLFR5: SMI0D6 */ + GPIO_PL2_TSPI1RXD = GPIO_FR_7, /*!< PLFR7: TSPI1RXD */ +} gpio_pl2_func_t; + +/** +* @enum gpio_pl3_func_t +* @brief PortL3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL3_T32A02INB0 = GPIO_FR_2, /*!< PLFR2: T32A02INB0 */ + GPIO_PL3_T32A02INC1 = GPIO_FR_3, /*!< PLFR3: T32A02INC1 */ + GPIO_PL3_SMI0D7 = GPIO_FR_5, /*!< PLFR5: SMI0D7 */ + GPIO_PL3_TSPI3CS1 = GPIO_FR_6, /*!< PLFR6: TSPI3CS1 */ + GPIO_PL3_TSPI1TXD = GPIO_FR_7, /*!< PLFR7: TSPI1TXD */ +} gpio_pl3_func_t; + +/** +* @enum gpio_pl4_func_t +* @brief PortL4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL4_INT12b = 0, /*!< 0: IN112b */ + GPIO_PL4_T32A08OUTA = GPIO_FR_2, /*!< PLFR2: T32A08OUTA */ + GPIO_PL4_T32A08OUTC = GPIO_FR_3, /*!< PLFR3: T32A08OUTC */ +} gpio_pl4_func_t; + +/** + * @enum gpio_pl5_func_t + * @brief PortL5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL5_INT13b = 0, /*!< 0: INT13b */ + GPIO_PL5_T32A08OUTB = GPIO_FR_2, /*!< PLFR2: T32A08OUTB */ +} gpio_pl5_func_t; + +/** + * @enum gpio_pl6_func_t + * @brief PortL6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL6_INT03b = 0, /*!< 0: INT03b */ + GPIO_PL6_T32A09OUTA = GPIO_FR_2, /*!< PLFR2: T32A09OUTA */ + GPIO_PL6_T32A09OUTC = GPIO_FR_3, /*!< PLFR3: T32A09OUTC */ +} gpio_pl6_func_t; + +/** + * @enum gpio_pl7_func_t + * @brief PortL7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL7_TRGIN1 = GPIO_FR_1, /*!< PLFR1: TRGIN1 */ + GPIO_PL7_T32A09OUTB = GPIO_FR_2, /*!< PLFR2: T32A09OUTB */ +} gpio_pl7_func_t; + +/** + * @enum gpio_pm0_func_t + * @brief PortM0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM0_EI2C3SDA = GPIO_FR_1, /*!< PMFR1: EI2C3SDA */ + GPIO_PM0_I2C3SDA = GPIO_FR_4, /*!< PMFR4: I2C3SDA */ + GPIO_PM0_UT4RXD = GPIO_FR_5, /*!< PMFR5: UT4RXD */ + GPIO_PM0_TSPI6TXD = GPIO_FR_6, /*!< PMFR6: TSPI6TXD */ + GPIO_PM0_UT4TXDA = GPIO_FR_7, /*!< PMFR7: UT4TXDA */ +} gpio_pm0_func_t; + +/** + * @enum gpio_pm1_func_t + * @brief PortM1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM1_EI2C3SCL = GPIO_FR_1, /*!< PMFR1: EI2C3SCL */ + GPIO_PM1_I2C3SCL = GPIO_FR_4, /*!< PMFR4: I2C3SCL */ + GPIO_PM1_UT4TXDA = GPIO_FR_5, /*!< PMFR5: UT4TXDA */ + GPIO_PM1_TSPI6RXD = GPIO_FR_6, /*!< PMFR6: TSPI6RXD */ + GPIO_PM1_UT4RXD = GPIO_FR_7, /*!< PMFR7: UT4RXD */ +} gpio_pm1_func_t; + +/** + * @enum gpio_pm2_func_t + * @brief PortM2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM2_T32A11OUTA = GPIO_FR_2, /*!< PMFR2: T32A11OUTA */ + GPIO_PM2_T32A11OUTC = GPIO_FR_3, /*!< PMFR3: T32A11OUTC */ + GPIO_PM2_UT4RTS_N = GPIO_FR_5, /*!< PMFR5: UT4RTS_N */ + GPIO_PM2_TSPI6SCK = GPIO_FR_6, /*!< PMFR6: TSPI6SCK */ + GPIO_PM2_UT4CTS_N = GPIO_FR_7, /*!< PMFR7: UT4CTS_N */ +} gpio_pm2_func_t; + +/** +* @enum gpio_pm3_func_t +* @brief PortM3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM3_INT14b = 0, /*!< 0: INT14b */ + GPIO_PM3_T32A11OUTB = GPIO_FR_2, /*!< PMFR2: T32A11OUTB */ + GPIO_PM3_TSPI6CSIN = GPIO_FR_4, /*!< PMFR4: TSPI6CSIN */ + GPIO_PM3_UT4CTS_N = GPIO_FR_5, /*!< PMFR5: UT4CTS_N */ + GPIO_PM3_TSPI6CS0 = GPIO_FR_6, /*!< PMFR6: TSPI6CS0 */ + GPIO_PM3_UT4RTS_N = GPIO_FR_7, /*!< PMFR7: UT4RTS_N */ +} gpio_pm3_func_t; + +/** +* @enum gpio_pm4_func_t +* @brief PortM4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM4_INT15b = 0, /*!< 0: INT15b */ + GPIO_PM4_T32A06OUTB = GPIO_FR_2, /*!< PMFR2: T32A06OUTB */ + GPIO_PM4_TSPI7CSIN = GPIO_FR_4, /*!< PMFR4: TSPI7CSIN */ + GPIO_PM4_TSPI7CS0 = GPIO_FR_6, /*!< PMFR6: TSPI7CS0 */ + GPIO_PM4_FUT1CTS_N = GPIO_FR_7, /*!< PMFR7: FUT1CTS_N */ +} gpio_pm4_func_t; + +/** + * @enum gpio_pm5_func_t + * @brief PortM5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM5_T32A06OUTA = GPIO_FR_2, /*!< PMFR2: T32A06OUTA */ + GPIO_PM5_T32A06OUTC = GPIO_FR_3, /*!< PMFR3: T32A06OUTC */ + GPIO_PM5_TSPI7SCK = GPIO_FR_6, /*!< PMFR6: TSPI7SCK */ + GPIO_PM5_FUT1RTS_N = GPIO_FR_7, /*!< PMFR7: FUT1RTS_N */ +} gpio_pm5_func_t; + +/** + * @enum gpio_pm6_func_t + * @brief PortM6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM6_EI2C4SDA = GPIO_FR_1, /*!< PMFR1: EI2C4SDA */ + GPIO_PM6_T32A07OUTA = GPIO_FR_2, /*!< PMFR2: T32A07OUTA */ + GPIO_PM6_T32A07OUTC = GPIO_FR_3, /*!< PMFR3: T32A07OUTC */ + GPIO_PM6_I2C4SDA = GPIO_FR_4, /*!< PMFR4: I2C4SDA */ + GPIO_PM6_FUT1IRIN = GPIO_FR_5, /*!< PMFR5: FUT1IRIN */ + GPIO_PM6_TSPI7RXD = GPIO_FR_6, /*!< PMFR6: TSPI7RXD */ + GPIO_PM6_FUT1RXD = GPIO_FR_7, /*!< PMFR7: FUT1RXD */ +} gpio_pm6_func_t; + +/** + * @enum gpio_pm7_func_t + * @brief PortM7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM7_EI2C4SCL = GPIO_FR_1, /*!< PMFR1: EI2C4SCL */ + GPIO_PM7_T32A07OUTB = GPIO_FR_2, /*!< PMFR2: T32A07OUTB */ + GPIO_PM7_I2C4SCL = GPIO_FR_4, /*!< PMFR4: I2C4SCL */ + GPIO_PM7_FUT1IROUT = GPIO_FR_5, /*!< PMFR5: FUT1IROUT */ + GPIO_PM7_TSPI7TXD = GPIO_FR_6, /*!< PMFR6: TSPI7TXD */ + GPIO_PM7_FUT1TXD = GPIO_FR_7, /*!< PMFR7: FUT1TXD */ +} gpio_pm7_func_t; + +/** + * @enum gpio_pn0_func_t + * @brief PortN0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN0_AINA00 = GPIO_FR_NA, /*!< N/A: AINA00 */ +} gpio_pn0_func_t; + +/** + * @enum gpio_pn1_func_t + * @brief PortN1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN1_AINA01 = GPIO_FR_NA, /*!< N/A: AINA01 */ +} gpio_pn1_func_t; + +/** + * @enum gpio_pn2_func_t + * @brief PortN2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN2_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN2_AINA02 = GPIO_FR_NA, /*!< N/A: AINA02 */ +} gpio_pn2_func_t; + +/** + * @enum gpio_pn3_func_t + * @brief PortN3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN3_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN3_AINA03 = GPIO_FR_NA, /*!< N/A: AINA03 */ +} gpio_pn3_func_t; + +/** +* @enum gpio_pn4_func_t +* @brief PortN4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PN4_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN4_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN4_AINA04 = GPIO_FR_NA, /*!< N/A: AINA04 */ +} gpio_pn4_func_t; + +/** + * @enum gpio_pn5_func_t + * @brief PortN5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN5_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN5_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN5_AINA05 = GPIO_FR_NA, /*!< N/A: AINA05 */ +} gpio_pn5_func_t; + +/** + * @enum gpio_pn6_func_t + * @brief PortN6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN6_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN6_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN6_AINA06 = GPIO_FR_NA, /*!< N/A: AINA06 */ +} gpio_pn6_func_t; + +/** + * @enum gpio_pn7_func_t + * @brief PortN7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN7_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN7_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN7_AINA07 = GPIO_FR_NA, /*!< N/A: AINA07 */ +} gpio_pn7_func_t; + +/** + * @enum gpio_pp0_func_t + * @brief PortP0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP0_AINA08 = 0, /*!< 0: AINA08 */ + GPIO_PP0_T32A04INA0 = GPIO_FR_2, /*!< PPFR2: T32A04INA0 */ + GPIO_PP0_T32A04INC0 = GPIO_FR_3, /*!< PPFR3: T32A04INC0 */ + GPIO_PP0_T32A04INB1 = GPIO_FR_5, /*!< PPFR5: T32A04INB1 */ +} gpio_pp0_func_t; + +/** + * @enum gpio_pp1_func_t + * @brief PortP1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP1_AINA09 = 0, /*!< 0: AINA09 */ + GPIO_PP1_T32A04INB0 = GPIO_FR_2, /*!< PPFR2: T32A04INB0 */ + GPIO_PP1_T32A04INC1 = GPIO_FR_3, /*!< PPFR3: T32A04INC1 */ + GPIO_PP1_T32A04INA1 = GPIO_FR_5, /*!< PPFR5: T32A04INA1 */ +} gpio_pp1_func_t; + +/** + * @enum gpio_pp2_func_t + * @brief PortP2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP2_AINA10 = 0, /*!< 0: AINA10 */ + GPIO_PP2_T32A05INA0 = GPIO_FR_2, /*!< PPFR2: T32A05INA0 */ + GPIO_PP2_T32A05INC0 = GPIO_FR_3, /*!< PPFR3: T32A05INC0 */ + GPIO_PP2_T32A05INB1 = GPIO_FR_5, /*!< PPFR5: T32A05INB1 */ +} gpio_pp2_func_t; + +/** +* @enum gpio_pp3_func_t +* @brief PortP3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP3_AINA11 = 0, /*!< 0: AINA11 */ + GPIO_PP3_T32A05INB0 = GPIO_FR_2, /*!< PPFR2: T32A05INB0 */ + GPIO_PP3_T32A05INC1 = GPIO_FR_3, /*!< PPFR3: T32A05INC1 */ + GPIO_PP3_T32A05INA1 = GPIO_FR_5, /*!< PPFR5: T32A05INA1 */ +} gpio_pp3_func_t; + +/** +* @enum gpio_pp4_func_t +* @brief PortP4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP4_AINA12 = 0, /*!< 0: AINA12 */ + GPIO_PP4_T32A06INA0 = GPIO_FR_2, /*!< PPFR2: T32A06INA0 */ + GPIO_PP4_T32A06INC0 = GPIO_FR_3, /*!< PPFR3: T32A06INC0 */ + GPIO_PP4_T32A06INB1 = GPIO_FR_5, /*!< PPFR5: T32A06INB1 */ +} gpio_pp4_func_t; + +/** +* @enum gpio_pp5_func_t +* @brief PortP5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP5_AINA13 = 0, /*!< 0: AINA13 */ + GPIO_PP5_T32A06INB0 = GPIO_FR_2, /*!< PPFR2: T32A06INB0 */ + GPIO_PP5_T32A06INC1 = GPIO_FR_3, /*!< PPFR3: T32A06INC1 */ + GPIO_PP5_T32A06INA1 = GPIO_FR_5, /*!< PPFR5: T32A06INA1 */ +} gpio_pp5_func_t; + +/** + * @enum gpio_pp6_func_t + * @brief PortP6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP6_AINA14 = 0, /*!< 0: AINA14 */ + GPIO_PP6_INT10b = 0, /*!< 0: INT10b */ + GPIO_PP6_T32A07INA0 = GPIO_FR_2, /*!< PPFR2: T32A07INA0 */ + GPIO_PP6_T32A07INC0 = GPIO_FR_3, /*!< PPFR3: T32A07INC0 */ + GPIO_PP6_T32A07INB1 = GPIO_FR_5, /*!< PPFR5: T32A07INB1 */ +} gpio_pp6_func_t; + +/** +* @enum gpio_pp7_func_t +* @brief PortP7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP7_AINA15 = 0, /*!< 0: AINA15 */ + GPIO_PP7_INT11b = 0, /*!< 0: INT11b */ + GPIO_PP7_T32A07INB0 = GPIO_FR_2, /*!< PPFR2: T32A07INB0 */ + GPIO_PP7_T32A07INC1 = GPIO_FR_3, /*!< PPFR3: T32A07INC1 */ + GPIO_PP7_T32A07INA1 = GPIO_FR_5, /*!< PPFR5: T32A07INA1 */ +} gpio_pp7_func_t; + +/** + * @enum gpio_pr0_func_t + * @brief PortR0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR0_AINA16 = 0, /*!< 0: AINA16 */ + GPIO_PR0_T32A08INA0 = GPIO_FR_2, /*!< PRFR2: T32A08INA0 */ + GPIO_PR0_T32A08INC0 = GPIO_FR_3, /*!< PRFR3: T32A08INC0 */ +} gpio_pr0_func_t; + +/** + * @enum gpio_pr1_func_t + * @brief PortR1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR1_AINA17 = 0, /*!< 0: AINA17 */ + GPIO_PR1_T32A08INB0 = GPIO_FR_2, /*!< PRFR2: T32A08INB0 */ + GPIO_PR1_T32A08INC1 = GPIO_FR_3, /*!< PRFR3: T32A08INC1 */ +} gpio_pr1_func_t; + +/** + * @enum gpio_pr2_func_t + * @brief PortR2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR2_AINA18 = 0, /*!< 0: AINA18 */ + GPIO_PR2_T32A09INA0 = GPIO_FR_2, /*!< PRFR2: T32A09INA0 */ + GPIO_PR2_T32A09INC0 = GPIO_FR_3, /*!< PRFR3: T32A09INC0 */ +} gpio_pr2_func_t; + +/** + * @enum gpio_pr3_func_t + * @brief PortR3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR3_AINA19 = 0, /*!< 0: AINA19 */ + GPIO_PR3_T32A09INB0 = GPIO_FR_2, /*!< PRFR2: T32A09INB0 */ + GPIO_PR3_T32A09INC1 = GPIO_FR_3, /*!< PRFR3: T32A09INC1 */ +} gpio_pr3_func_t; + +/** + * @enum gpio_pr4_func_t + * @brief PortR4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR4_AINA20 = 0, /*!< 0: AINA20 */ + GPIO_PR4_T32A10INA0 = GPIO_FR_2, /*!< PRFR2: T32A10INA0 */ + GPIO_PR4_T32A10INC0 = GPIO_FR_3, /*!< PRFR3: T32A10INC0 */ +} gpio_pr4_func_t; + +/** + * @enum gpio_pr5_func_t + * @brief PortR5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR5_AINA21 = 0, /*!< 0: AINA21 */ + GPIO_PR5_T32A10INB0 = GPIO_FR_2, /*!< PRFR2: T32A10INB0 */ + GPIO_PR5_T32A10INC1 = GPIO_FR_3, /*!< PRFR3: T32A10INC1 */ +} gpio_pr5_func_t; + +/** + * @enum gpio_pr6_func_t + * @brief PortR6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR6_AINA22 = 0, /*!< 0: AINA22 */ + GPIO_PR6_T32A11INA0 = GPIO_FR_2, /*!< PRFR2: T32A11INA0 */ + GPIO_PR6_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC0 */ +} gpio_pr6_func_t; + +/** + * @enum gpio_pr7_func_t + * @brief PortR7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR7_AINA23 = 0, /*!< 0: AINA23 */ + GPIO_PR7_T32A11INB0 = GPIO_FR_2, /*!< PRFR2: T32A11INB0 */ + GPIO_PR7_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC1 */ +} gpio_pr7_func_t; + + +/** + * @enum gpio_pt0_func_t + * @brief PortT0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PT0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PT0_DAC0 = GPIO_FR_NA, /*!< N/A: DAC0 */ +} gpio_pt0_func_t; + +/** + * @enum gpio_pt1_func_t + * @brief PortT1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PT1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PT1_DAC1 = GPIO_FR_NA, /*!< N/A: DAC1 */ +} gpio_pt1_func_t; + +/** + * @enum gpio_pt2_func_t + * @brief PortT2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT2_CEC0 = GPIO_FR_7, /*!< PTFR1: CEC0 Input/Output */ +} gpio_pt2_func_t; + +/** + * @enum gpio_pt3_func_t + * @brief PortT3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT3_INT00b = 0, /*!< 0: INT00b */ + GPIO_PT3_RTCOUT = GPIO_FR_1, /*!< PTFR1: RTCOUT */ + GPIO_PT3_T32A03OUTA = GPIO_FR_2, /*!< PTFR2: T32A03OUTA */ + GPIO_PT3_T32A03OUTC = GPIO_FR_3, /*!< PTFR3: T32A03OUTC */ + GPIO_PT3_RXIN0 = 0, /*!< 0: RXIN0 */ + GPIO_PT3_TRGIN2 = GPIO_FR_6, /*!< PTFR6: TRGIN2 */ +} gpio_pt3_func_t; + +/** + * @enum gpio_pt4_func_t + * @brief PortT4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT4_INT01b = 0, /*!< 0: INT01b */ + GPIO_PT4_RXIN1 = 0, /*!< 0: RXIN1 */ +} gpio_pt4_func_t; + +/** + * @enum gpio_pt5_func_t + * @brief PortT5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT5_INT02b = 0, /*!< 0: INT02b */ + GPIO_PT5_T32A03OUTB = GPIO_FR_2, /*!< PTFR2: T32A03OUTB */ +} gpio_pt5_func_t; + +/** + * @enum gpio_pu0_func_t + * @brief PortU0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU0_T32A12OUTA = GPIO_FR_2, /*!< PUFR2: T32A12OUTA */ + GPIO_PU0_T32A12OUTC = GPIO_FR_3, /*!< PUFR3: T32A12OUTC */ + GPIO_PU0_UT4TXDA = GPIO_FR_7, /*!< PUFR7: UT4TXDA */ +} gpio_pu0_func_t; + +/** + * @enum gpio_pu1_func_t + * @brief PortU1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU1_T32A12OUTB = GPIO_FR_2, /*!< PUFR2: T32A12OUTB */ + GPIO_PU1_UT4RXD = GPIO_FR_7, /*!< PUFR7: UT4RXD */ +} gpio_pu1_func_t; + +/** + * @enum gpio_pu2_func_t + * @brief PortU2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU2_INT06b = 0, /*!< 0: INT06b */ + GPIO_PU2_T32A12INA0 = GPIO_FR_2, /*!< PUFR2: T32A12INA0 */ + GPIO_PU2_T32A12INC0 = GPIO_FR_3, /*!< PUFR3: T32A12INC0 */ + GPIO_PU2_TSSI1TCK = GPIO_FR_6, /*!< PUFR6: TSSI1TCK */ + GPIO_PU2_UT4CTS_N = GPIO_FR_7, /*!< PUFR7: UT4CTS_N */ +} gpio_pu2_func_t; + +/** + * @enum gpio_pu3_func_t + * @brief PortU3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU3_INT07b = 0, /*!< 0: INT07b */ + GPIO_PU3_T32A12INB0 = GPIO_FR_2, /*!< PUFR2: T32A12INB0 */ + GPIO_PU3_T32A12INC1 = GPIO_FR_3, /*!< PUFR3: T32A12INC1 */ + GPIO_PU3_TSSI1TFS = GPIO_FR_6, /*!< PUFR6: TSSI1TFS */ + GPIO_PU3_UT4RTS_N = GPIO_FR_7, /*!< PUFR7: UT4RTS_N */ +} gpio_pu3_func_t; + +/** + * @enum gpio_pu4_func_t + * @brief PortU4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU4_INT08b = 0, /*!< 0: INT08b */ + GPIO_PU4_T32A13INB0 = GPIO_FR_2, /*!< PUFR2: T32A13INB0 */ + GPIO_PU4_T32A13INC1 = GPIO_FR_3, /*!< PUFR3: T32A13INC1 */ + GPIO_PU4_TSSI1TXD = GPIO_FR_6, /*!< PUFR6: TSSI1TXD */ + GPIO_PU4_UT3RTS_N = GPIO_FR_7, /*!< PUFR7: UT3RTS_N */ +} gpio_pu4_func_t; + +/** + * @enum gpio_pu5_func_t + * @brief PortU5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU5_INT09b = 0, /*!< 0: INT09b */ + GPIO_PU5_T32A13INA0 = GPIO_FR_2, /*!< PUFR2: T32A13INA0 */ + GPIO_PU5_T32A13INC0 = GPIO_FR_3, /*!< PUFR3: T32A13INC0 */ + GPIO_PU5_TSSI1RXD = GPIO_FR_6, /*!< PUFR6: TSSI1RXD */ + GPIO_PU5_UT3CTS_N = GPIO_FR_7, /*!< PUFR7: UT3CTS_N */ +} gpio_pu5_func_t; + +/** + * @enum gpio_pu6_func_t + * @brief PortU6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU6_T32A13OUTA = GPIO_FR_2, /*!< PUFR2: T32A13OUTA */ + GPIO_PU6_T32A13OUTC = GPIO_FR_3, /*!< PUFR3: T32A13OUTC */ + GPIO_PU6_TSSI1RFS = GPIO_FR_6, /*!< PUFR6: TSSI1RFS */ + GPIO_PU6_UT3RXD = GPIO_FR_7, /*!< PUFR7: UT3RXD */ +} gpio_pu6_func_t; + +/** + * @enum gpio_pu7_func_t + * @brief PortU7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU7_T32A13OUTB = GPIO_FR_2, /*!< PUFR2: T32A13OUTB */ + GPIO_PU7_TSSI1RCK = GPIO_FR_6, /*!< PUFR6: TSSI1RCK */ + GPIO_PU7_UT3TXDA = GPIO_FR_7, /*!< PUFR7: UT3TXDA */ +} gpio_pu7_func_t; + +/** + * @enum gpio_pv0_func_t + * @brief PortV0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV0_T32A09INA0 = GPIO_FR_2, /*!< PVFR2: T32A09INA0 */ + GPIO_PV0_T32A09INC0 = GPIO_FR_3, /*!< PVFR3: T32A09INC0 */ + GPIO_PV0_ISDBIN0 = 0, /*!< 0: ISDBIN0 */ + GPIO_PV0_UO0 = GPIO_FR_5, /*!< PVFR5: UO0 */ + GPIO_PV0_UT3RXD = GPIO_FR_6, /*!< PVFR6: UT3RXD */ + GPIO_PV0_UT3TXDA = GPIO_FR_7, /*!< PVFR7: UT3TXDA */ +} gpio_pv0_func_t; + +/** + * @enum gpio_pv1_func_t + * @brief PortV1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV1_T32A09INB0 = GPIO_FR_2, /*!< PVFR2: T32A09INB0 */ + GPIO_PV1_T32A09INC1 = GPIO_FR_3, /*!< PVFR3: T32A09INC1 */ + GPIO_PV1_ISDBIN1 = 0, /*!< 0: ISDBIN1 */ + GPIO_PV1_XO0 = GPIO_FR_5, /*!< PVFR5: XO0 */ + GPIO_PV1_UT3TXDA = GPIO_FR_6, /*!< PVFR6: UT3TXDA */ + GPIO_PV1_UT3RXD = GPIO_FR_7, /*!< PVFR7: UT3RXD */ +} gpio_pv1_func_t; + +/** + * @enum gpio_pv2_func_t + * @brief PortV2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV2_T32A09OUTA = GPIO_FR_2, /*!< PVFR2: T32A09OUTA */ + GPIO_PV2_T32A09OUTC = GPIO_FR_3, /*!< PVFR3: T32A09OUTC */ + GPIO_PV2_ISDBIN2 = 0, /*!< 0: ISDBIN2 */ + GPIO_PV2_VO0 = GPIO_FR_5, /*!< PVFR5: VO0 */ + GPIO_PV2_UT3RTS_N = GPIO_FR_6, /*!< PVFR6: UT3RTS_N */ + GPIO_PV2_UT3CTS_N = GPIO_FR_7, /*!< PVFR7: UT3CTS_N */ +} gpio_pv2_func_t; + +/** + * @enum gpio_pv3_func_t + * @brief PortV3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV3_T32A09OUTB = GPIO_FR_2, /*!< PVFR2: T32A09OUTB */ + GPIO_PV3_ISDBIN3 = 0, /*!< 0: ISDBIN3 */ + GPIO_PV3_YO0 = GPIO_FR_5, /*!< PVFR5: YO0 */ + GPIO_PV3_UT3CTS_N = GPIO_FR_6, /*!< PVFR6: UT3CTS_N */ + GPIO_PV3_UT3RTS_N = GPIO_FR_7, /*!< PVFR7: UT3RTS_N */ +} gpio_pv3_func_t; + +/** + * @enum gpio_pv4_func_t + * @brief PortV4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV4_EI2C2SCL = GPIO_FR_1, /*!< PVFR1: EI2C2SCL */ + GPIO_PV4_T32A04OUTB = GPIO_FR_2, /*!< PVFR2: T32A04OUTB */ + GPIO_PV4_TSPI5RXD = GPIO_FR_4, /*!< PVFR4: TSPI5RXD */ + GPIO_PV4_WO0 = GPIO_FR_5, /*!< PVFR5: WO0 */ + GPIO_PV4_I2C2SCL = GPIO_FR_6, /*!< PVFR6: I2C2SCL */ + GPIO_PV4_UT1RXD = GPIO_FR_7, /*!< PVFR7: UT1RXD */ +} gpio_pv4_func_t; + +/** + * @enum gpio_pv5_func_t + * @brief PortV5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV5_EI2CSDA = GPIO_FR_1, /*!< PVFR1: EI2CSDA */ + GPIO_PV5_T32A04OUTA = GPIO_FR_2, /*!< PVFR2: T32A04OUTA */ + GPIO_PV5_T32A04OUTC = GPIO_FR_3, /*!< PVFR3: T32A04OUTC */ + GPIO_PV5_TSPI5TXD = GPIO_FR_4, /*!< PVFR4: TSPI5TXD */ + GPIO_PV5_ZO0 = GPIO_FR_5, /*!< PVFR5: ZO0 */ + GPIO_PV5_I2C2SDA = GPIO_FR_6, /*!< PVFR6: I2C2SDA */ + GPIO_PV5_UT1TXDA = GPIO_FR_7, /*!< PVFR7: UT1TXDA */ +} gpio_pv5_func_t; + +/** + * @enum gpio_pv6_func_t + * @brief PortV6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV6_T32A05OUTA = GPIO_FR_2, /*!< PVFR2: T32A05OUTA */ + GPIO_PV6_T32A05OUTC = GPIO_FR_3, /*!< PVFR3: T32A05OUTC */ + GPIO_PV6_TSPI5SCK = GPIO_FR_4, /*!< PVFR4: TSPI5SCK */ + GPIO_PV6_EMG0 = GPIO_FR_5, /*!< PVFR5: EMG0 */ + GPIO_PV6_UT1CTS_N = GPIO_FR_7, /*!< PVFR7: UT1CTS_N */ +} gpio_pv6_func_t; + +/** + * @enum gpio_pv7_func_t + * @brief PortV7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV7_T32A05OUTB = GPIO_FR_2, /*!< PVFR2: T32A05OUTB */ + GPIO_PV7_TSPI5CS0 = GPIO_FR_4, /*!< PVFR4: TSPI5CS0 */ + GPIO_PV7_OVV0 = GPIO_FR_5, /*!< PVFR5: OVV0 */ + GPIO_PV7_TSPI5CSIN = GPIO_FR_6, /*!< PVFR6: TSPI5CSIN */ + GPIO_PV7_UT1RTS_N = GPIO_FR_7, /*!< PVFR7: UT1RTS_N */ +} gpio_pv7_func_t; + +/** + * @enum gpio_pw0_func_t + * @brief PortW0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW0_TSPI8CS0 = GPIO_FR_4, /*!< PWFR4: TSPI8CS0 */ + GPIO_PW0_T32A00OUTB = GPIO_FR_5, /*!< PWFR5: T32A00OUTB */ + GPIO_PW0_TSPI8CSIN = GPIO_FR_6, /*!< PWFR6: TSPI8CSIN */ +} gpio_pw0_func_t; + +/** + * @enum gpio_pw1_func_t + * @brief PortW1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW1_TSPI8SCK = GPIO_FR_4, /*!< PWFR4: TSPI8SCK */ + GPIO_PW1_T32A00OUTA = GPIO_FR_5, /*!< PWFR5: T32A00OUTA */ + GPIO_PW1_T32A00OUTC = GPIO_FR_7, /*!< PWFR7: T32A00OUTC */ +} gpio_pw1_func_t; + +/** + * @enum gpio_pw2_func_t + * @brief PortW2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW2_TSPI8RXD = GPIO_FR_4, /*!< PWFR4: TSPI8RXD */ + GPIO_PW2_T32A01OUTA = GPIO_FR_5, /*!< PWFR5: T32A01OUTA */ + GPIO_PW2_T32A01OUTC = GPIO_FR_7, /*!< PWFR7: T32A01OUTC */ +} gpio_pw2_func_t; + +/** + * @enum gpio_pw3_func_t + * @brief PortW3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW3_TSPI8TXD = GPIO_FR_4, /*!< PWFR4: TSPI8TXD */ + GPIO_PW3_T32A01OUTB = GPIO_FR_5, /*!< PWFR5: T32A01OUTB */ +} gpio_pw3_func_t; + +/** + * @enum gpio_pw4_func_t + * @brief PortW4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW4_T32A11INA1 = GPIO_FR_3, /*!< PWFR3: T32A11INA1 */ + GPIO_PW4_T32A10OUTB = GPIO_FR_5, /*!< PWFR5: T32A10OUTB */ + GPIO_PW4_ISDCIN0 = 0, /*!< 0: ISDCIN0 */ + GPIO_PW4_T32A10INA0 = GPIO_FR_7, /*!< PWFR7: T32A10INA0 */ +} gpio_pw4_func_t; + +/** + * @enum gpio_pw5_func_t + * @brief PortW5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW5_T32A10OUTA = GPIO_FR_5, /*!< PWFR5: T32A10OUTA */ + GPIO_PW5_ISDCIN1 = 0, /*!< 0: ISDCIN1 */ + GPIO_PW5_T32A10OUTC = GPIO_FR_7, /*!< PWFR7: T32A10OUTC */ +} gpio_pw5_func_t; + +/** + * @enum gpio_pw6_func_t + * @brief PortW6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW6_T32A11OUTA = GPIO_FR_5, /*!< PWFR5: T32A11OUTA */ + GPIO_PW6_ISDCIN2 = 0, /*!< 0: ISDCIN2 */ + GPIO_PW6_T32A11OUTC = GPIO_FR_7, /*!< PWFR7: T32A11OUTC */ +} gpio_pw6_func_t; + +/** + * @enum gpio_pw7_func_t + * @brief PortW7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW7_T32A10INA1 = GPIO_FR_3, /*!< PWFR3: T32A10INA1 */ + GPIO_PW7_T32A11OUTB = GPIO_FR_5, /*!< PWFR5: T32A11OUTB */ + GPIO_PW7_ISDCIN3 = 0, /*!< 0: ISDCIN3 */ + GPIO_PW7_T32A11INA0 = GPIO_FR_7, /*!< PWFR7: T32A11INA0 */ +} gpio_pw7_func_t; + +/** + * @enum gpio_py0_func_t + * @brief PortY0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY0_X1 = GPIO_FR_NA, /*!< N/A: X1 */ +} gpio_py0_func_t; + +/** + * @enum gpio_py1_func_t + * @brief PortY1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY1_X2 = GPIO_FR_NA, /*!< N/A: X2 */ +} gpio_py1_func_t; + +/** + * @enum gpio_py2_func_t + * @brief PortY2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY2_XT1 = GPIO_FR_NA, /*!< N/A: XT1 */ +} gpio_py2_func_t; + +/** + * @enum gpio_py3_func_t + * @brief PortY3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY3_XT2 = GPIO_FR_NA, /*!< N/A: XT2 */ +} gpio_py3_func_t; + +/** + * @enum gpio_py4_func_t + * @brief PortY4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PY4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PY4_ISDCOUT = GPIO_FR_1, /*!< PYFR1: ISDCOUT */ + GPIO_PY4_EEXBCLK = GPIO_FR_4, /*!< PYFR4: EEXBCLK */ +} gpio_py4_func_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ +/*! + * @brief Pin Exist Table + * @details Bit0 :GPIO_Mode_DATA + * @details Bit1 :GPIO_Mode_CR + * @details Bit2 :GPIO_Mode_FR1 + * @details Bit3 :GPIO_Mode_FR2 + * @details Bit4 :GPIO_Mode_FR3 + * @details Bit5 :GPIO_Mode_FR4 + * @details Bit6 :GPIO_Mode_FR5 + * @details Bit7 :GPIO_Mode_FR6 + * @details Bit8 :GPIO_Mode_FR7 + * @details Bit9 :GPIO_Mode_FR8 + * @details Bit10 :GPIO_Mode_OD + * @details Bit11 :GPIO_Mode_PUP + * @details Bit12 :GPIO_Mode_PDN + * @details Bit13 :GPIO_Mode_IE + */ +static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = { + /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ + { GPIO_PORT_A_0, GPIO_PORT_A_1, GPIO_PORT_A_2, GPIO_PORT_A_3, GPIO_PORT_A_4, GPIO_PORT_A_5, GPIO_PORT_A_6, GPIO_PORT_A_7 }, /** GPIO_PORT_A */ + { GPIO_PORT_B_0, GPIO_PORT_B_1, GPIO_PORT_B_2, GPIO_PORT_B_3, GPIO_PORT_B_4, GPIO_PORT_B_5, GPIO_PORT_B_6, GPIO_PORT_B_7 }, /** GPIO_PORT_B */ + { GPIO_PORT_C_0, GPIO_PORT_C_1, GPIO_PORT_C_2, GPIO_PORT_C_3, GPIO_PORT_C_4, GPIO_PORT_C_5, GPIO_PORT_C_6, GPIO_PORT_C_7 }, /** GPIO_PORT_C */ + { GPIO_PORT_D_0, GPIO_PORT_D_1, GPIO_PORT_D_2, GPIO_PORT_D_3, GPIO_PORT_D_4, GPIO_PORT_D_5, GPIO_PORT_D_6, GPIO_PORT_D_7 }, /** GPIO_PORT_D */ + { GPIO_PORT_E_0, GPIO_PORT_E_1, GPIO_PORT_E_2, GPIO_PORT_E_3, GPIO_PORT_E_4, GPIO_PORT_E_5, GPIO_PORT_E_6, GPIO_PORT_E_7 }, /** GPIO_PORT_E */ + { GPIO_PORT_F_0, GPIO_PORT_F_1, GPIO_PORT_F_2, GPIO_PORT_F_3, GPIO_PORT_F_4, GPIO_PORT_F_5, GPIO_PORT_F_6, GPIO_PORT_F_7 }, /** GPIO_PORT_F */ + { GPIO_PORT_G_0, GPIO_PORT_G_1, GPIO_PORT_G_2, GPIO_PORT_G_3, GPIO_PORT_G_4, GPIO_PORT_G_5, GPIO_PORT_G_6, GPIO_PORT_G_7 }, /** GPIO_PORT_G */ + { GPIO_PORT_H_0, GPIO_PORT_H_1, GPIO_PORT_H_2, GPIO_PORT_H_3, GPIO_PORT_H_4, GPIO_PORT_H_5, GPIO_PORT_H_6, GPIO_PORT_H_7 }, /** GPIO_PORT_H */ + { GPIO_PORT_J_0, GPIO_PORT_J_1, GPIO_PORT_J_2, GPIO_PORT_J_3, GPIO_PORT_J_4, GPIO_PORT_J_5, GPIO_PORT_J_6, GPIO_PORT_J_7 }, /** GPIO_PORT_J */ + { GPIO_PORT_K_0, GPIO_PORT_K_1, GPIO_PORT_K_2, GPIO_PORT_K_3, GPIO_PORT_K_4, GPIO_PORT_K_5, GPIO_PORT_K_6, GPIO_PORT_K_7 }, /** GPIO_PORT_K */ + { GPIO_PORT_L_0, GPIO_PORT_L_1, GPIO_PORT_L_2, GPIO_PORT_L_3, GPIO_PORT_L_4, GPIO_PORT_L_5, GPIO_PORT_L_6, GPIO_PORT_L_7 }, /** GPIO_PORT_L */ + { GPIO_PORT_M_0, GPIO_PORT_M_1, GPIO_PORT_M_2, GPIO_PORT_M_3, GPIO_PORT_M_4, GPIO_PORT_M_5, GPIO_PORT_M_6, GPIO_PORT_M_7 }, /** GPIO_PORT_M */ + { GPIO_PORT_N_0, GPIO_PORT_N_1, GPIO_PORT_N_2, GPIO_PORT_N_3, GPIO_PORT_N_4, GPIO_PORT_N_5, GPIO_PORT_N_6, GPIO_PORT_N_7 }, /** GPIO_PORT_N */ + { GPIO_PORT_P_0, GPIO_PORT_P_1, GPIO_PORT_P_2, GPIO_PORT_P_3, GPIO_PORT_P_4, GPIO_PORT_P_5, GPIO_PORT_P_6, GPIO_PORT_P_7 }, /** GPIO_PORT_P */ + { GPIO_PORT_R_0, GPIO_PORT_R_1, GPIO_PORT_R_2, GPIO_PORT_R_3, GPIO_PORT_R_4, GPIO_PORT_R_5, GPIO_PORT_R_6, GPIO_PORT_R_7 }, /** GPIO_PORT_R */ + { GPIO_PORT_T_0, GPIO_PORT_T_1, GPIO_PORT_T_2, GPIO_PORT_T_3, GPIO_PORT_T_4, GPIO_PORT_T_5, GPIO_PORT_T_6, GPIO_PORT_T_7 }, /** GPIO_PORT_T */ + { GPIO_PORT_U_0, GPIO_PORT_U_1, GPIO_PORT_U_2, GPIO_PORT_U_3, GPIO_PORT_U_4, GPIO_PORT_U_5, GPIO_PORT_U_6, GPIO_PORT_U_7 }, /** GPIO_PORT_U */ + { GPIO_PORT_V_0, GPIO_PORT_V_1, GPIO_PORT_V_2, GPIO_PORT_V_3, GPIO_PORT_V_4, GPIO_PORT_V_5, GPIO_PORT_V_6, GPIO_PORT_V_7 }, /** GPIO_PORT_V */ + { GPIO_PORT_W_0, GPIO_PORT_W_1, GPIO_PORT_W_2, GPIO_PORT_W_3, GPIO_PORT_W_4, GPIO_PORT_W_5, GPIO_PORT_W_6, GPIO_PORT_W_7 }, /** GPIO_PORT_W */ + { GPIO_PORT_Y_0, GPIO_PORT_Y_1, GPIO_PORT_Y_2, GPIO_PORT_Y_3, GPIO_PORT_Y_4, GPIO_PORT_Y_5, GPIO_PORT_Y_6, GPIO_PORT_Y_7 }, /** GPIO_PORT_Y */ +}; +/** + * @} + */ /* End of group GPIO_Private_typedef */ +/*----------------------------------*/ +/** + * @brief GPIO handle structure definition. +*/ +/*----------------------------------*/ +typedef struct gpio_pa_handle { + TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ + TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ + TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ + TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ + TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ + TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ + TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ + TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ + TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */ + TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ + TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ + TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ + TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ + TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ + TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ + TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ + TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */ + TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ + TSB_PW_TypeDef *p_pw_instance; /*!< Registers base address. */ + TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ +} _gpio_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __GPIO_M4GR_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_hal.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_hal.h new file mode 100644 index 0000000..6df6fc1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_hal.h @@ -0,0 +1,147 @@ +/** + ******************************************************************************* + * @file txz_hal.h + * @brief This file provides all the functions prototypes for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __HAL_H +#define __HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup HAL HAL + * @brief HAL Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_macro HAL Exported Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_define HAL Exported Define + * @{ + */ +#if defined ( __CC_ARM ) /* RealView Compiler */ +extern uint32_t Load$$FLASH_CODE_RAM$$Base; +extern uint32_t Image$$FLASH_CODE_RAM$$Base; +extern uint32_t Load$$FLASH_CODE_RAM$$Length; + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma section = "FLASH_CODE_RAM" +#pragma section = "FLASH_CODE_ROM" +#endif + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base +#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base +#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM")) +#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM")) +#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM")) +#endif + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_define HAL Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_typedef HAL Exported Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_functions HAL Exported Functions + * @{ + */ + +void hal_inc_tick(void); +uint32_t hal_get_tick(void); +void wait(uint32_t count); +void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size); +void fc_ram_con_reg_set(uint32_t sysclock); + +/** + * @} + */ /* End of group HAL_Exported_functions */ + +/** + * @} + */ /* End of group HAL */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __HAL_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c.h new file mode 100644 index 0000000..df0a5e9 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c.h @@ -0,0 +1,805 @@ +/** + ******************************************************************************* + * @file txz_i2c.h + * @brief This file provides all the functions prototypes for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __I2C_H +#define __I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +#ifdef __DEBUG__ +/** + * @name I2C_NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of name I2C_NULL Pointer */ +#endif + +/** + * @name I2CxST Macro Definition. + * @brief I2CxST Register Macro Definition. + * @{ + */ +#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */ +#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */ +#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */ +#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */ +#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */ +/** + * @} + */ /* End of name I2CxST Macro Definition */ + +/** + * @name I2CxCR1 Macro Definition. + * @brief I2CxCR1 Register Macro Definition. + * @{ + */ +#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */ +#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */ +#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */ + +/** + * @} + */ /* End of name I2CxCR1 Macro Definition */ + +/** + * @name I2CxDBR Macro Definition. + * @brief I2CxDBR Register Macro Definition. + * @{ + */ +#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ +/** + * @} + */ /* End of name I2CxDBR Macro Definition */ + + +/** + * @name I2CxCR2 Macro Definition. + * @brief I2CxCR2 Register Macro Definition. + * @{ + */ +#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */ +#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */ +#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */ +#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */ +#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */ +#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */ +#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */ +#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */ + +/** + * @} + */ /* End of name I2CxCR2 Macro Definition */ + +/** + * @name I2CxSR Macro Definition. + * @brief I2CxSR Register Macro Definition. + * @{ + */ +#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */ +#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */ +#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */ +#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */ +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */ +#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */ +#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */ +/** + * @} + */ /* End of name I2CxSR Macro Definition */ + +/** + * @name I2CxPRS Macro Definition. + * @brief I2CxPRS Register Macro Definition. + * @{ + */ +#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */ +/** + * @} + */ /* End of name I2CxPRS Macro Definition */ + +/** + * @name I2CxIE Macro Definition. + * @brief I2CxIE Register Macro Definition. + * @{ + */ +#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */ +#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */ +#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */ +#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */ +#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */ + +/** + * @} + */ /* End of name I2CxIE Macro Definition */ + + +/** + * @name I2CxOP Macro Definition. + * @brief I2CxOP Register Macro Definition. + * @{ + */ +#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */ +#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */ +#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */ +#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */ +#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */ +#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */ +#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */ +#ifndef I2C_MULTI_MASTER +#define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */ +#else +#define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */ +#endif +#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */ +/** + * @} + */ /* End of name I2CxOP Macro Definition */ + +/** + * @name I2CxAR Macro Definition. + * @brief I2CxAR Register Macro Definition. + * @{ + */ +#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */ +#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ +#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ + +/** + * @} + */ /* End of name I2CxAR Macro Definition */ + + +/** + * @name I2CxPM Macro Definition. + * @brief I2CxPM Register Macro Definition. + * @{ + */ +#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ +/** + * @} + */ /* End of name I2CxPM Macro Definition */ + +/** + * @name I2CxWUPCR_INT Macro Definition. + * @brief I2CxWUPCR_INT Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ +#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ +/** + * @} + */ /* End of name I2CxWUPCR_INT Macro Definition */ + +/** + * @name I2CxWUPCR_RST Macro Definition. + * @brief I2CxWUPCR_RST Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ +#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ + + +/** + * @name I2CxWUPCR_ACK Macro Definition. + * @brief I2CxWUPCR_ACK Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ +#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sck; /*!< Select internal SCL output clock frequency. */ + uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */ +} I2C_clock_setting_t; + +/*----------------------------------*/ +/** + * @brief Wakeup Control setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sgcdi; /*!< Select general call detect ON/OFF. */ + uint32_t ack; /*!< Select ACK output. */ + uint32_t reset; /*!< I2C BUS Rest. */ + uint32_t intend; /*!< Interrupt release. */ +} I2CS_wup_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_clock_setting_t clock; /*!< Serial clock setting. */ +} I2C_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */ +} I2CS_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */ + I2C_initial_setting_t init; /*!< Initial setting. */ +} I2C_t; +#if defined(I2CSxWUP_EN) +/*----------------------------------*/ +/** + * @brief I2CS handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */ + I2CS_initial_setting_t init; /*!< Initial setting. */ +} I2CS_t; +#endif +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj); +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj); +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj); +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data); +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack); +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx); +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr); +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj); + +/*--------------------------------------------------*/ +/** + * @brief I2C software reset. + * @param p_obj :I2C object. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief I2C bus port high + * @param p_obj :I2C object. + * @retval true :SDA and SCL Port High. + * @retval false :Bus Error. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); + } + return (0); +#else + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Generate stop condition. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Read from Data buffer + * @param p_obj :I2C object. + * @retval result :Read data. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); + } + return (0); +#else + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Write to Data buffer. + * @param p_obj :I2C object. + * @param data :Write data. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + } +#else + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return restart condition + * @param p_obj :I2C object. + * @retval true :Restart Detected. + * @retval false :Restart Non-Detected. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); + } + return (0); +#else + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set Ack condition + * @param p_obj :I2C object. + * @param nack :1 NACK, 0 ACK. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } + } +#else + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return received Ack condition + * @param p_obj :I2C object. + * @retval true :NACK Received. + * @retval false :ACK Received. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return Busy condition + * @param p_obj :I2C object. + * @retval true :I2C bus busy. + * @retval false :I2C bus free. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Master status + * @param p_obj :I2C object. + * @retval true :Master mode. + * @retval false :Slave mode. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Transmitter + * @param p_obj :I2C object. + * @retval true :Transmitter. + * @retval false :Receiver. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status + * @param p_obj :I2C object. + * @retval true :Interrupt Occurred. + * @retval false :No Interrupt Occurred. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); + } + return (0); +#else + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status Clear + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->ST = I2CxST_CLEAR; + } +#else + p_obj->p_instance->ST = I2CxST_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_I2C; + } +#else + p_obj->p_instance->IE = I2CxIE_I2C; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @param tx :Direction of transfer(1=tx 0=rx). + * @retval - + * @note For DMA transfer. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } + } +#else + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_CLEAR; + } +#else + p_obj->p_instance->IE = I2CxIE_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set slave address. + * @param p_obj :I2C object. + * @param addr :slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; + } +#else + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Detecting Slave Address + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); + } + return (0); +#else + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); +#endif +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +void I2C_init(I2C_t *p_obj); +void I2C_start_condition(I2C_t *p_obj, uint32_t data); +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting); +void I2C_slave_init(I2C_t *p_obj); +#if defined(I2CSxWUP_EN) +void I2CS_init(I2CS_t *p_obj); +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c_api.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c_api.h new file mode 100644 index 0000000..e279430 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_i2c_api.h @@ -0,0 +1,308 @@ +/** + ******************************************************************************* + * @file i2c_api.h + * @brief This file provides all the functions prototypes for I2C Driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __BSP_I2C_H +#define __BSP_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ +/** + * @defgroup I2C_NullPointer Null Pointer + * @brief I2C NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of group I2C_NullPointer */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/** + * @defgroup I2C_ACK I2C ACK Macros + * @brief I2C Type of Acknowledge. + * @{ + */ +#define I2C_NACK (0) /*!< NACK Received. */ +#define I2C_ACK (1) /*!< ACK Received. */ +/** + * @} + */ /* End of group I2C_ACK */ + + +/** + * @defgroup I2C_ERROR I2C ERROR Macros + * @brief I2C Error definitions. + * @{ + */ +#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */ +#if 0 +#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */ +#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */ +#endif +#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */ +#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */ +#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */ +/** + * @} + */ /* End of group I2C_ERROR */ + + +/** + * @defgroup I2C_Events I2C Events Macros + * @brief I2C Asynch Events. + * @{ + */ +#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */ +#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */ +#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */ +#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */ +#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) +/** + * @} + */ /* End of group I2C_Events */ + +/** + * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros + * @brief I2C Received Contents of Slave. + * @{ + */ +#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */ +#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */ +#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */ +#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */ +/** + * @} + */ /* End of group I2C_SlaveReceive */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/*----------------------------------*/ +/** + * @brief i2c Port Enumerated Type Definition. +*/ +/*----------------------------------*/ +typedef enum { + I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */ + I2C_PORT_PG3, /*!< 1: PG3 I2C0 */ + I2C_PORT_PF2, /*!< 2: PF2 I2C1 */ + I2C_PORT_PF3, /*!< 3: PF3 I2C1 */ + I2C_PORT_PG4, /*!< 4: PG4 I2C2 */ + I2C_PORT_PG5, /*!< 5: PG5 I2C2 */ + I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */ + I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */ + I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */ + I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */ +} +i2c_port_t; + +/*----------------------*/ +/* I2C Setting */ +/*----------------------*/ +/* #define I2C_CHANNEL0 */ +#define I2C_CHANNEL3 +/* #define I2C_CHANNEL2 */ +/* #define I2C_CHANNEL3 */ +/* #define I2C_CHANNEL4 */ +#if defined(I2C_CHANNEL0) +#define I2Cx_TEXT "I2C0" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL1) +#define I2Cx_TEXT "I2C1" +#define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL2) +#define I2Cx_TEXT "I2C2" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL3) +#define I2Cx_TEXT "I2C3" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL4) +#define I2Cx_TEXT "I2C4" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */ +#else +#error "target channel is non-select." +#endif + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief I2C internal information structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t bus_free; /*!< Bus free information. */ + uint8_t start; /*!< Start condition information. */ + uint32_t irqn; /*!< IRQ number table pointer. */ + struct { + uint32_t address; /*!< Slave address. */ + uint32_t stop; /*!< Stop control */ + uint32_t event; /*!< I2C Event information. */ + uint32_t state; /*!< Transfer State. */ + } asynch; +} i2c_internal_info_t; + +/*----------------------------------*/ +/** + * @brief I2C buffer structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_buffer; /*!< Buffer address. */ + uint32_t length; /*!< Buffer length. */ + uint32_t pos; /*!< Buffer pointer. */ +} i2c_buffer_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_t i2c; /*!< I2C class structure. */ + i2c_internal_info_t info; /*!< Internal Information. */ + i2c_buffer_t tx_buff; /*!< Tx buffer structure. */ + i2c_buffer_t rx_buff; /*!< Rx buffer structure. */ +} _i2c_t; + +/** + * @} + */ /* End of group UTILITIES_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl); +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz); +void i2c_reset_t(_i2c_t *p_obj); +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj); +TXZ_Result i2c_start_t(_i2c_t *p_obj); +TXZ_Result i2c_stop_t(_i2c_t *p_obj); +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last); +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data); +uint8_t i2c_active_t(_i2c_t *p_obj); +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop); +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_abort_asynch_t(_i2c_t *p_obj); +uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn); + +/* For slave */ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave); +int32_t i2c_slave_receive_t(_i2c_t *p_obj); +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address); +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length); +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_slave_abort_asynch_t(_i2c_t *p_obj); + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __BSP_I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_t32a.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_t32a.h new file mode 100644 index 0000000..9d27b63 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_t32a.h @@ -0,0 +1,1000 @@ +/** + ******************************************************************************* + * @file txz_t32a.h + * @brief This file provides all the functions prototypes for T32A driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __T32A_H +#define __T32A_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup T32A T32A + * @brief T32A Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_define T32A Exported Define + * @{ + */ + +/** + * @defgroup T32A_Result Result + * @brief T32A Result Macro Definition. + * @{ + */ +#define T32A_RESULT_SUCCESS (0) /*!< Success */ +#define T32A_RESULT_FAILURE (-1) /*!< Failure */ +#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group T32A_Result */ + +/** + * @defgroup T32A_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */ +/** + * @} + */ /* End of group T32A_NullPointer */ + +/** +* @defgroup T32A_HALT T32A Debug HALT Control +* @brief Debug HALT Control Run/Stop HALT Macro Definition. +* @{ +*/ +#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */ +#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */ +/** + * @} + */ /* End of group T32A_HALT */ + +/** +* @defgroup T32A_MODE32 T32A 16bit/32bit MODE +* @brief T32A 16bit/32bit MODE MODE32 Macro Definition. +* @{ +*/ +#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */ +#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */ +/** + * @} + */ /* End of group T32A_MODE32 */ + +/** +* @defgroup T32A_RUNFLGx T32A RUNFLG Control +* @brief Run/Stop RUNFLGx Macro Definition. +* @{ +*/ +#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */ +#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */ +/** + * @} + */ /* End of group T32A_RUNFLGx */ + +/** + * @defgroup T32A_SFTSTPx T32A SW STOP Control + * @brief T32A SW STOPx SFTSTPx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */ +/** + * @} + */ /* End of group T32A_SFTSTPx */ + +/** + * @defgroup T32A_SFTSTAx T32A SW START Control + * @brief T32A SW STARTx SFTSTAx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */ +/** + * @} + */ /* End of group T32A_SFTSTAx */ + +/** + * @defgroup T32A_RUNx T32A RUN Disable/Enable Control + * @brief RUN Disable/Enable RUNx Macro Definition. + * @{ + */ +#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group T32A_RUNx */ + + +/** + * @defgroup T32A_PRSCLx T32A PRESCALER Control + * @brief PRESCALER Control PRSCLx Macro Definition. + * @{ + */ +#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */ +#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */ +#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */ +#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */ +#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */ +#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */ +#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */ +/** + * @} + */ /* End of group T32A_PRSCLx */ + +/** + * @defgroup T32A_CLKx T32A COLCK Control + * @brief CLOCK Control CLKA Macro Definition. + * @{ + */ +#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */ +#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */ +#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */ +#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */ +#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */ +#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */ +/** + * @} + */ /* End of group T32A_CLKx */ + +/** + * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control + * @brief Double Buffer Disable/Enable WBFx Macro Definition. + * @{ + */ +#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */ +/** + * @} + */ /* End of group T32A_WBFx */ + +/** +* @defgroup T32A_UPDNx T32A Counter Up/Down Control +* @brief Counter Up/Down Control UPDNx Macro Definition. +* @{ +*/ +#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */ +#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */ +#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */ +#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */ +/** + * @} + */ /* End of group T32A_UPDNx */ + +/** +* @defgroup T32A_RELDx T32A Counter Reload Control +* @brief Counter Reload Control RELDx Macro Definition. +* @{ +*/ +#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */ +#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */ +#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */ +#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */ +#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */ +#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */ +#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */ +#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */ +/** + * @} + */ /* End of group T32A_RELDx */ + +/** +* @defgroup T32A_STOPx T32A Counter Stop Control +* @brief Counter Stop Control STOPx Macro Definition. +* @{ +*/ +#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */ +#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */ +#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */ +#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */ +#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */ +#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */ +/** + * @} + */ /* End of group T32A_STOPx */ + + +/** +* @defgroup T32A_STARTx T32A Counter Start Control +* @brief Counter Start Control STARTx Macro Definition. +* @{ +*/ +#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */ +#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */ +#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */ +#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */ +#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */ +#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */ +/** + * @} + */ /* End of group T32A_STARTx */ + +/** + * @defgroup T32A_OCRx T32AxOUTA Control + * @brief T32AxOUTA Control OCRx Macro Definition. + * @{ + */ +#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRx */ + +/** + * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 + * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */ +#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */ +#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx1 */ + +/** + * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value + * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */ +#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */ +#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx0 */ + +/** + * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value + * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */ +#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */ +#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx1 */ + +/** + * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value + * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx0 */ + +/** + * @defgroup T32A_RGx0 T32A Timer Register x0 MASK + * @brief T32A Timer Register A0 MASK RGx0 Macro Definition. + * @{ + */ +#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_RGx1 T32A Timer Register x1 MASK + * @brief T32A Timer Register A1 MASK RGx1 Macro Definition. + * @{ + */ +#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_TMRx T32A Counter Capture Register x MASK + * @brief T32A Counter Capture Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_TMRx */ + +/** + * @defgroup T32A_RELD T32A Counter Reload Register x MASK + * @brief T32A Counter Reload Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RELD */ + +/** +* @defgroup T32A_CAPMx1 T32A Capture Control Register x1 +* @brief Capture Control Register A1 CAPMx1 Macro Definition. +* @{ +*/ +#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */ +#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */ +#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */ +#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */ +#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */ +#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx1 */ + +/** +* @defgroup T32A_CAPMx0 T32A Capture Control Register x0 +* @brief Capture Control Register x0 CAPMx0 Macro Definition. +* @{ +*/ +#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */ +#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */ +#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */ +#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */ +#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */ +#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx0 */ + +/** + * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK + * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition. + * @{ + */ +#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx0 */ + +/** + * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK + * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition. + * @{ + */ +#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx1 */ + +/** + * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK + * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition. + * @{ + */ +#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) +#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_IMSTERR */ + +/** + * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK + * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition. + * @{ + */ +#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */ +/** + * @} + */ /* End of group T32A_IMUFx */ + +/** + * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK + * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition. + * @{ + */ +#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */ +/** + * @} + */ /* End of group T32A_IMOFx */ + +/** + * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition. + * @{ + */ +#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx1 */ + +/** + * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition. + * @{ + */ +#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx0 */ + +/** + * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status + * @brief T32A Statuserr Flag Status INTSTERR Macro Definition. + * @{ + */ +#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) +#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_INTSTERR */ + +/** + * @defgroup T32A_INTUFA T32A Underflow Flag Status + * @brief T32A Underflow Flag Status INTUFA Macro Definition. + * @{ + */ +#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */ +#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTUFA */ + +/** + * @defgroup T32A_INTOFA T32A Overflow Flag Status + * @brief T32A Overflow Flag Status INTOFA Macro Definition. + * @{ + */ +#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */ +#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTOFA */ + +/** + * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status + * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition. + * @{ + */ +#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */ +#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA1 */ + +/** + * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status + * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition. + * @{ + */ +#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */ +#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA0 */ + +/** + * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control + * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition. + * @{ + */ +#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx2 */ + +/** + * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control + * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition. + * @{ + */ +#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx1 */ + +/** + * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control + * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition. + * @{ + */ +#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx0 */ + +/** +* @defgroup T32A_PDN T32A Pulse Mode Count Down Control +* @brief Pulse Mode Count Down Control PDN Macro Definition. +* @{ +*/ +#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */ +#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */ +#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */ +#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */ +#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */ +#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */ +#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PDN */ + +/** +* @defgroup T32A_PUP T32A Pulse Mode Count UP Control +* @brief Pulse Mode Count UP Control PUP Macro Definition. +* @{ +*/ +#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */ +#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */ +#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */ +#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */ +#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */ +#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */ +#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PUP */ + +/** +* @defgroup T32A_NF T32A Noise Filter control +* @brief Noise Filter control NF Macro Definition. +* @{ +*/ +#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/ PhiT0 */ +#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/ PhiT0 */ +#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/ PhiT0 */ +/** + * @} + */ /* End of group T32A_NF */ + +/** + * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control + * @brief Phase 2 Pulse Direction control PDIR Macro Definition. + * @{ + */ +#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */ +#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */ +/** + * @} + */ /* End of group T32A_PDIR */ + +/** + * @defgroup T32A_PMODE T32A Pulse Count Mode control + * @brief Pulse Count Mode control PDIR Macro Definition. + * @{ + */ +#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */ +#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */ +/** + * @} + */ /* End of group T32A_PMODE */ + +/** + * @} + */ /* End of group T32A_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ + +/** + * @enum t32_type_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_TIMERA = 0, /*!< 0: Timer A */ + T32A_TIMERB, /*!< 1: Timer B */ + T32A_TIMERC, /*!< 2: Timer C */ + T32A_TIMERMAX, +} t32_type_t; + +/** + * @enum t32_regnum_t + * @brief Use of Timer register number. + */ +typedef enum { + T32A_REG0 = 0, /*!< 0: Register 0 */ + T32A_REG1, /*!< 1: Register 1 */ + T32A_RELOAD, /*!< 2: Reload Register */ +} t32_regnum_t; +/** + * @enum t32_mode_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_MATCH = 0, /*!< 0: compare match detection 0 */ + T32A_OVERFLOW, /*!< 1: Overfloe detection */ + T32A_UNDERFLOW, /*!< 2: Underflow detection */ + T32A_CAPTURE0, /*!< 3: Capture 0 */ + T32A_CAPTURE1, /*!< 4: Capture 0 */ +} t32_mode_t; + +/** + * @enum t32_triger_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_INTRG = 0, /*!< 0: internal triger */ + T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */ + T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */ + T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */ + T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */ +} t32_triger_t; +/** + * @} + */ /* End of group T32A_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct t32a_mode_t + * @brief TimerA Mode Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t halt; /*!< T32A Debug HALT Control. + : Use @ref T32A_HALT */ + uint32_t mode; /*!< T32A 16bit/32bit MODE . + : Use @ref T32A_MODE32 */ +} t32a_mode_t; + +/*----------------------------------*/ +/** + * @struct t32a_runx_t + * @brief TimerA Run Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t runflg; /*!< TimerA Run Control Flag. + : Use @ref T32A_RUNFLGx */ + uint32_t sftstp; /*!< SW Counter STOP Control. + : Use @ref T32A_SFTSTPx */ + uint32_t sftsta; /*!< SW Counter START Control. + : Use @ref T32A_SFTSTAx */ + uint32_t run; /*!< TimerA Run Control. + : Use @ref T32A_RUNx */ +} t32a_runx_t; + +/*----------------------------------*/ +/** + * @struct t32a_crx_t + * @brief Counter Register Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prscl; /*!< T32A PRESCALER Control. + : Use @ref T32A_PRSCLx */ + uint32_t clk; /*!< T32A COLCK Control. + : Use @ref T32A_CLKx */ + uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control. + : Use @ref T32A_WBFx */ + uint32_t updn; /*!< T32A Counter Up/Down Control. + : Use @ref T32A_UPDNx */ + uint32_t reld; /*!< T32A Counter Reload Control. + : Use @ref T32A_RELDx */ + uint32_t stop; /*!< T32A Counter Stop Control. + : Use @ref T32A_STOPx */ + uint32_t start; /*!< T32A Counter Start Controlc. + : Use @ref T32A_STARTx */ +} t32a_crx_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx0_t + * @brief TimerA Output Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocr; /*!< T32AxOUTA Control. + : Use @ref T32A_OCRx */ +} t32a_outcrx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx1_t + * @brief T32AxOUTA Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1. + : Use @ref T32A_OCRCAPx1 */ + uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1. + : Use @ref T32A_OCRCAPx0 */ + uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value + : Use @ref T32A_OCRCMPx1 */ + uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value + : Use @ref T32A_OCRCMPx0 */ +} t32a_outcrx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_capcrx_t + * @brief Capture Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capmx1; /*!< T32A Capture Control Register x1. + : Use @ref T32A_CAPMx1 */ + uint32_t capmx0; /*!< T32A Capture Control Register A0. + : Use @ref T32A_CAPMx0 */ +} t32a_capcrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx0_t + * @brief T32A Timer Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx0; /*!< T32A Timer Register x0. + : Use @ref T32A_RGx0 */ +} t32a_rgx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx1_t + * @brief T32A Timer Register x1 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx1; /*!< T32A Timer Register x1. + : Use @ref T32A_RGx1 */ +} t32a_rgx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_tmrx_t + * @brief T32A Counter Capture Register A Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tmrx; /*!< T32A Counter Capture Register x. + : Use @ref T32A_TMRx */ +} t32a_tmrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_reldx_t + * @brief T32A Counter Reload Register Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reld; /*!< T32A Counter Reload Register. + : Use @ref T32A_RELD */ +} t32a_reldx_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx0_t + * @brief T32A Capture Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx0; /*!< T32A Capture Register x0. + : Use @ref T32A_CAPx0 */ +} t32a_capx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx1_t + * @brief T32A Capture Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx1; /*!< T32A Capture Register x1. + : Use @ref T32A_CAPx1 */ +} t32a_capx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_imx_t + * @brief Interrupt mask register Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C). + : Use @ref T32A_IMSTERR */ + uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMUFx */ + uint32_t imof; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMOFx */ + uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK. + : Use @ref T32A_IMx1 */ + uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK. + : Use @ref T32A_IMx0 */ +} t32a_imx_t; + +/*----------------------------------*/ +/** + * @struct t32a_stx_t + * @brief Status register structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C). + : Use @ref T32A_INTSTERR */ + uint32_t intuf; /*!< T32A Underflow Flag Status. + : Use @ref T32A_INTUFA */ + uint32_t intof; /*!< T32A Overflow Flag Status. + : Use @ref T32A_INTOFA */ + uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status. + : Use @ref T32A_INTA1 */ + uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status. + : Use @ref T32A_INTA0 */ +} t32a_stx_t; + +/*----------------------------------*/ +/** + * @struct t32a_dma_req_t + * @brief DMA Request register setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control. + : Use @ref T32A_DMAENx2 */ + uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control. + : Use @ref T32A_DMAENx1 */ + uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control. + : Use @ref T32A_DMAENx0 */ +} t32a_dma_req_t; + +/*----------------------------------*/ +/** + * @struct t32a_pulse_cr_t + * @brief Pulse Count Control register setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t pdn; /*!< Pulse Mode Count Down Control. + : Use @ref T32A_PDN */ + uint32_t pup; /*!< Pulse Mode Count UP Control. + : Use @ref T32A_PUP */ + uint32_t nf; /*!< Noise Filter control. + : Use @ref T32A_NF */ + uint32_t pdir; /*!< Phase 2 Pulse Direction control. + : Use @ref T32A_PDIR */ + uint32_t pmode; /*!< Pulse Count Mode control. + : Use @ref T32A_PMODE */ +} t32a_pulse_cr_t; + +/** + * @struct t32a_initial_setting_t + * @brief Initial Timer setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + t32a_runx_t runx; /*!< Timer Run Control Setting */ + t32a_crx_t crx; /*!< Counter Register Control Setting */ + t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */ + t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */ + t32a_capcrx_t capcrx; /*!< Capture Control Setting */ + t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */ + t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */ + t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */ + t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */ + t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */ + t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */ + t32a_imx_t imx; /*!< Interrupt mask register Setting */ + t32a_dma_req_t dma_req; /*!< DMA Request register Setting */ + t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */ + void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */ + void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */ + void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */ +} t32a_initial_setting_t; + +/** + * @struct t32a_initial_mode_t + * @brief Initial Mode setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + t32a_mode_t mode; /*!< Timer Mode Setting */ +} t32a_initial_mode_t; + + +/*----------------------------------*/ +/** + * @brief T32A handle structure definition. +*/ +/*----------------------------------*/ +typedef struct t32a_handle { + TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */ + t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */ + t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */ +} t32a_t; + +/** @} */ +/* End of group T32A_Exported_Types */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_functions T32A Exported Functions + * @{ + */ +TXZ_Result t32a_mode_init(t32a_t *p_obj); +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value); +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val); +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type); +void t32a_timer_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj); +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __T32A_H */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_tspi.h new file mode 100644 index 0000000..1f05751 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_tspi.h @@ -0,0 +1,1378 @@ +/** + ******************************************************************************* + * @file txz_tspi.h + * @brief This file provides all the functions prototypes for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __TSPI_H +#define __TSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup TSPI TSPI + * @brief TSPI Driver. + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_define TSPI Exported Define + * @{ + */ +/** + * @defgroup TSPI_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define TSPI_NULL ((void *)0) +/** + * @} + */ /* End of group TSPI_NullPointer */ + +/** + * @defgroup TSPI_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group TSPI_ParameterResult */ + + +/** + * @defgroup TSPI_Result Result + * @brief TSPI Result Macro Definition. + * @{ + */ +#define TSPI_RESULT_SUCCESS (0) /*!< Success */ +#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ +/** + * @} + */ /* End of group TSPI_Result */ + +/** + * @defgroup TSPI_SW_Reset SW Reset + * @brief Software Rest Macro Definition. + * @{ + */ +#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattern 10 */ +#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattern 01 */ +/** + * @} + */ /* End of group TSPI_SW_Reset */ + + +/** + * @defgroup TSPI_Enable TSPI Enable/Disable Control + * @brief Enable/Disable TSPIE Macro Definition. + * @{ + */ +#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Enable */ + +/** + * @defgroup TSPI_Infinity_Control Frame infinity Control + * @brief Frame infinity Enable/Disable Macro Definition. + * @{ + */ +#define TSPI_INF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_INF_ENABLE ((uint32_t)0x00010000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Infinity_Control */ + +/** + * @defgroup TSPI_Trigger_Control Trigger Control + * @brief Enable/Disable TRGEN Macro Definition. + * @{ + */ +#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Control Transmission Control + * @brief Enable/Disable TRXE Macro Definition. + * @{ + */ +#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ +#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Mode Transmission Mode + * @brief TSPIIMS Mode Macro Definition. + * @{ + */ +#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ +#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ +/** + * @} + */ /* End of group TSPI_Transmission_Mode */ + + +/** + * @defgroup TSPI_Operation_Select Operation Select + * @brief Master/Slave MSTR Operation Macro Definition. + * @{ + */ +#define TSPI_MASTER_OPERATION ((uint32_t)0x00001000) /*!< MASTER MODE */ +#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ +/** + * @} + */ /* End of group TSPI_Operation_Select */ + + +/** + * @defgroup TSPI_Transfer_Mode Transfer Mode + * @brief Transfer Mode TMMD Macro Definition. + * @{ + */ +#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ +#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ +#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ +#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ +/** + * @} + */ /* End of group TSPI_Transfer_Mode */ + + +/** + * @defgroup TSPI_CSSEL_Select CSSEL Select + * @brief TSPIIxCS0/1/2/3 Select Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ +#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ +#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ +#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ +/** + * @} + */ /* End of group TSPI_CSSEL_Select */ + +/** + * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range + * @brief Transfer Frame Range Macro Definition. + * @{ + */ +#define TSPI_TRANS_RANGE_CONTINUE ((uint32_t)0x00000000) /*!< Continue Transfer Frame :0 */ +#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000001) /*!< Single Transfer Frame :1 */ +#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ +/** + * @} + */ /* End of group TSPI_Transfer_Frame_Range */ +/** + * @defgroup TSPI_IDLE_Output_value IDLE Output Value + * @brief IDLE time Output Value TIDLE Macro Definition. + * @{ + */ +#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ +#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ +#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ +#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_IDLE_Output_value */ + +/** + * @defgroup TSPI_RXDLY_value RXDLY Value + * @brief IDLE time Output Value TIDLE Macro Definition. + * @{ + */ +#define TSPI_RXDLY_1CLK ((uint32_t)0x00000000) /*!< RXDLY 1CLK */ +#define TSPI_RXDLY_2CLK ((uint32_t)0x00010000) /*!< RXDLY 2CLK */ +#define TSPI_RXDLY_3CLK ((uint32_t)0x00020000) /*!< RXDLY 3CLK */ +#define TSPI_RXDLY_4CLK ((uint32_t)0x00030000) /*!< RXDLY 4CLK */ +#define TSPI_RXDLY_5CLK ((uint32_t)0x00040000) /*!< RXDLY 5CLK */ +#define TSPI_RXDLY_6CLK ((uint32_t)0x00050000) /*!< RXDLY 6CLK */ +#define TSPI_RXDLY_7CLK ((uint32_t)0x00060000) /*!< RXDLY 7CLK */ +#define TSPI_RXDLY_8CLK ((uint32_t)0x00070000) /*!< RXDLY 8CLK */ +/** + * @} + */ /* End of group TSPI_RXDLY_value*/ + + +/** +* @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value +* @brief In case of Under Run Output Value TXDEMP Macro Definition. +* @{ +*/ +#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ +#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_Underrun_Output_value */ + + +/** + * @defgroup TSPI_TxFillLevel Tx Fill Level + * @brief Transmit Fill Level Macro Definition. + * @{ + */ +#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ +#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ +#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ +#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ +#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ +#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ +#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ +#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ +/*! + * @} + */ /* End of group TSPI_TxFillLevel */ + + +/** + * @defgroup TSPI_RxFillLevel Rx Fill Level + * @brief Receive Fill Level Macro Definition. + * @{ + */ +#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ +#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ +#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ +#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ +#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ +#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ +#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ +#define TSPI_RX_FILL_LEVEL_8 ((uint32_t)0x00000800) /*!< 8 */ +#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000F00) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RxFillLevel */ + + +/** + * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrupt + * @brief Enable/Disable Transmit FIFO Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterrupt */ + + +/** + * @defgroup TSPI_TxInterrupt Tx Interrupt + * @brief Enable/Disable Transmit Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxInterrupt */ + + +/** + * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrupt + * @brief Enable/Disable Receive FIFO Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterrupt */ + + +/** + * @defgroup TSPI_RxInterrupt Rx Interrupt + * @brief Enable/Disable Receive Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxInterrupt */ + + +/** + * @defgroup TSPI_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ErrorInterrupt */ + + +/** + * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt + * @brief Enable/Disable Transmit DMA Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ +#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxDMAInterrupt */ + + +/** + * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt + * @brief Enable/Disable Receive DMA Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ +#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxDMAInterrupt */ + + +/** + * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear + * @brief Tx Buffer Clear Macro Definition. + * @{ + */ +#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Tx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear + * @brief Rx Buffer Clear Macro Definition. + * @{ + */ +#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Rx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock + * @brief Baudrate Input Clock Macro Definition. + * @{ + */ +#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ +#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ +#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ +#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ +#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ +#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ +#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ +#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ +#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ +#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Clock */ + + +/** + * @defgroup TSPI_Baudrate_Divider Baudrate Divider + * @brief Baudrate IDivider Macro Definition. + * @{ + */ +#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ +#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ +#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ +#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ +#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ +#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ +#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ +#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ +#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ +#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ +#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ +#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ +#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ +#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ +#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ +#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Divider */ + + +/** + * @defgroup TSPI_DataDirection Data Direction + * @brief Data Direction Macro Definition. + * @{ + */ +#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ +/*! + * @} + */ /* End of group TSPI_DataDirection */ + + +/** + * @defgroup TSPI_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ +#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ +#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ +#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ +#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ +#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ +#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ +#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ +#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ +#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ +#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ +#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ +#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ +#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ +#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ +#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ +#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ +#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ +#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ +#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ +#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ +#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ +#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ +#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ +#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ +#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ +/** + * @} + */ /* End of group TSPI_DataLength */ + + +/** + * @defgroup TSPI_Frame_Interval_Time Frame Interval time + * @brief Frame Interval time Macro Definition. + * @{ + */ +#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Frame_Interval_Time */ + + +/** + * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity + * @brief TSPIxCS3 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS3_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity + * @brief TSPIxCS2 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS2_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity + * @brief TSPIxCS1 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS1_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity + * @brief TSPIxCS0 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS0_Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity + * @brief Serial Clock Polarity Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ +#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ +/** + * @} + */ /* End of group Serial Clock Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity + * @brief Serial Clock IDLE Polarity Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ +#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ + + +/** + * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time + * @brief Minimum IDLE Time Macro Definition. + * @{ + */ +#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Minimum_IDLE_Time */ + + +/** + * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay + * @brief Serial Clock Delay Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_Delay */ + + +/** + * @defgroup TSPI_Negate_Delay Negate Delay + * @brief Negate Delay Macro Definition. + * @{ + */ +#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ +#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ +#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ +#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ +#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ +#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ +#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ +#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ +#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ +#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ +#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ +#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ +#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ +#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ +#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Negate_Delay */ + + +/** + * @defgroup TSPI_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ParityEnable */ + + +/** + * @defgroup TSPI_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ +/** + * @} + */ /* End of group TSPI_ParityBit */ + + +/** + * @defgroup TSPI_SECT_MODE Sect mode setting + * @brief Sect mode Macro Definition. + * @{ + */ +#define TSPI_SECT_MODE_FRAME ((uint32_t)0x00000000) /*!< Frame Mode */ +#define TSPI_SECT_MODE_SECT ((uint32_t)0x00000001) /*!< Sect Mode */ +/** + * @} + */ /* End of group TSPI_SECT_MODE */ + + +/** + * @defgroup TSPI_SECT_VALUE Sect bit length setting + * @brief Sect bit length Macro Definition. + * @{ + */ +#define TSPI_SECT_VALUE_0 ((uint32_t)0x00000000) /*!< length:0 */ +#define TSPI_SECT_VALUE_1 ((uint32_t)0x00000001) /*!< length:1 */ +#define TSPI_SECT_VALUE_MAX ((uint32_t)0x00000020) /*!< MAX:32 */ +/** + * @} + */ /* End of group TSPI_SECT_VALUE */ + +/** + * @defgroup TSPI_Status_Setting_flag Status Setting Flag + * @brief Enable/Disable Status Setting Flag Macro Definition. + * @{ + */ +#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group TSPI_Status_Setting_flag */ + + +/** + * @defgroup TSPI_TxState Transmitting State Flag + * @brief Transmitting State Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ +#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_TxState */ + + +/** + * @defgroup TSPI_TxDone Transmitting Complete Flag + * @brief Transmitting Complete Flag Macro Definition. + * @{ + */ +#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ +#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ +#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxDone */ + + +/** + * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrupt Flag + * @brief Transmitting FIFO Interrupt Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ +#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag + * @brief Transmitting FIFO Empty Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_TxFIFOEmptyFlag */ + +/** + * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level + * @brief Current Transmitting FIFO Level Macro Definition. + * @{ + */ +#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ +#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ +#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ +#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ +#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ +#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ +#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ +#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_TxReachFillLevel */ + + +/** + * @defgroup TSPI_RxState Receive State Flag + * @brief Receive State Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ +#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_RxState */ + + +/** + * @defgroup TSPI_RxDone Receive Complete Flag + * @brief Receive Complete Flag Macro Definition. + * @{ + */ +#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ +#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ +#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxDone */ + + +/** + * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrupt Flag + * @brief Rx FIFO Interrupt Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ +#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag + * @brief Receiving FIFO Full Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_RxFIFOFullFlag */ + + +/** + * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level + * @brief Current Receive FIFO Level Macro Definition. + * @{ + */ +#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ +#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ +#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ +#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ +#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ +#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ +#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ +#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_RxReachFillLevel */ + + +/** + * @defgroup TSPI_TRGErr Trigger Error + * @brief Trigger Error Macro Definition. + * @{ + */ +#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ +#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_TRGErr */ + +/** + * @defgroup TSPI_UnderrunErr Underrun Error + * @brief Underrun Error Macro Definition. + * @{ + */ +#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ +#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_UnderrunErr */ + +/** + * @defgroup TSPI_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ +#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_OverrunErr */ + + +/** + * @defgroup TSPI_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ +#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_ParityErr */ + +/** +* @defgroup TSPI_Data_allign Data allign +* @brief Data allign Macro Definition. +* @{ +*/ +#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ +#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ +#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ +/** + * @} + */ /* End of group TSPI_Data_allign */ + +/** +* @defgroup TSPI_FifoMax FIFO MAX +* @brief FIFO MAX LEVEL +* @{ +*/ +#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ +/** + * @} + */ /* End of group TSPI_FifoMax */ + +/** +* @defgroup TSPI_ErrCode Error Code +* @brief Error Code Macro Definition. +* @{ +*/ +#define NOERROR ((uint32_t)0x00000000) /*!< no error */ +#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ +#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ +#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ +#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ +#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ +#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ +#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ +#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ +#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ +#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ +/** +* @} + */ /* End of group TSPI_ErrCode */ + +/** +* @defgroup TSPI_Buffer_Size Receive Buffer size +* @brief Error Code Macro Definition. +* @{ +*/ +#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ +/** +* @} + */ /* End of group TSPI_Buffer_Size */ +/** + * @} + */ /* End of group TSPI_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/* No define */ +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct tspi_receive8_t + * @brief Receive event information structure definition. + * @brief When data length definition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive8_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive16_t + * @brief Receive event information structure definition. + * @brief When data length definition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive16_t; + +/** + * @struct tspi_receive32_t + * @brief Receive event information structure definition. + * @brief When data length definition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive32_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive_t + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef union { + tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ + tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ + tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ +} tspi_receive_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit8_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit8_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit16_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit16_t; +/*----------------------------------*/ +/** + * @struct tspi_transmit32_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit32_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit_t + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef union { + tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ + tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ + tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ +} tspi_transmit_t; + +/*----------------------------------*/ +/** + * @struct tspi_control1_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inf; /*!< INF Transmission Infinity Control. + : Use @ref TSPI_Infinity_Control */ + uint32_t trgen; /*!< TRGEN Transmission Trigger Control. + : Use @ref TSPI_Trigger_Control */ + uint32_t trxe; /*!< TRXE Transmission Control. + : Use @ref TSPI_Transmission_Control */ + uint32_t tspims; /*!< TSPI/SIO Transmission Mode. + : Use @ref TSPI_Transmission_Mode */ + uint32_t mstr; /*!< Master/Slave Operation Select. + : Use @ref TSPI_Operation_Select */ + uint32_t tmmd; /*!< Transfer Mode Select. + : Use @ref TSPI_Transfer_Mode */ + uint32_t cssel; /*!< CSSEL Select. + : Use @ref TSPI_CSSEL_Select */ + uint32_t fc; /*!< Transfer Frame Value. + : Range ( TSPI_TRANS_RANGE_CONTINUE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ +} tspi_control1_t; + +/*----------------------------------*/ +/** + * @struct tspi_control2_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tidle; /*!< IDLE Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t txdemp; /*!< Under Run Occur Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t rxdly; /*!< Fsys Select. + : Use @ref TSPI_RXDLY_value */ + uint32_t til; /*!< Transmit Fill Level. + : Use @ref TSPI_TxFillLevel */ + uint32_t ril; /*!< Receive Fill Level. + : Use @ref TSPI_RxFillLevel */ + uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. + : Use @ref TSPI_TxFIFOInterrupt */ + uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. + : Use @ref TSPI_TxInterrupt */ + uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. + : Use @ref TSPI_RxFIFOInterrupt */ + uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. + : Use @ref TSPI_RxInterrupt */ + uint32_t interr; /*!< Enable/Disable Error Interrupt. + : Use @ref TSPI_ErrorInterrupt */ + uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. + : Use @ref TSPI_TxDMAInterrupt */ + uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. + : Use @ref TSPI_RxDMAInterrupt */ +} tspi_control2_t; + +/*----------------------------------*/ +/** + * @struct tspi_control3_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tfempclr; /*!< Transmit Buffer Clear. + : Use @ref TSPI_Tx_Buffer_Clear */ + uint32_t rffllclr; /*!< Receive Buffer Clear. + : Use @ref TSPI_Rx_Buffer_Clear */ +} tspi_control3_t; + +/*----------------------------------*/ +/** + * @struct tspi_baudrate_t + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brck; /*!< Baudrate Input Clock. + : Use @ref TSPI_Baudrate_Clock */ + uint32_t brs; /*!< Baudrate Divider. + : Use @ref TSPI_Baudrate_Divider */ +} tspi_baudrate_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr0_t + * @brief Format control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dir; /*!< Data Direction. + : Use @ref TSPI_DataDirection */ + uint32_t fl; /*!< Data Length. + : Use @ref TSPI_DataLength */ + uint32_t fint; /*!< Frame Interval time. + : Use @ref TSPI_Frame_Interval_Time */ + uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS3_Polarity */ + uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS2_Polarity */ + uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS1_Polarity */ + uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS0_Polarity */ + uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. + : Use @ref TSPI_Serial_Clock_Polarity */ + uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. + : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ + uint32_t csint; /*!< Minimum IDLE Time. + : Use @ref TSPI_Minimum_IDLE_Time */ + uint32_t cssckdl; /*!< Serial Clock Delay. + : Use @ref TSPI_Serial_Clock_Delay */ + uint32_t sckcsdl; /*!< Negate Delay. + : Use @ref TSPI_Negate_Delay */ +} tspi_fmtr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr1_t + * @brief Format control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reserved; /*!< SIO Slave Mode. + : */ + uint32_t vpe; /*!< Enable/Disable Parity Function. + : Use @ref TSPI_ParityEnable */ + uint32_t vpm; /*!< Odd/Even Parity Bit. + : Use @ref TSPI_ParityBit */ +} tspi_fmtr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr0_t + * @brief Sect control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sect; /*!< Sect mode settings. + : Use @ref TSPI_SECT_MODE */ +} tspi_sectcr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr1_t + * @brief Sect control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sectl3; /*!< SECTL3 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl2; /*!< SECTL2 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl1; /*!< SECTL1 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl0; /*!< SECTL0 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ +} tspi_sectcr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_status_t + * @brief Status register. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. + : Use @ref TSPI_Status_Setting_flag */ + uint32_t txrun; /*!< Stop/Active Tx Active Flag. + : Use @ref TSPI_TxState */ + uint32_t txend; /*!< Tx Data Send Complete Flag. + : Use @ref TSPI_TxDone */ + uint32_t inttxwf; /*!< Tx FIFO Interrupt Flag. + : Use @ref TSPI_TxFIFOInterruptFlag */ + uint32_t tfemp; /*!< Tx FIFO Empty Flag. + : Use @ref TSPI_TxFIFOEmptyFlag */ + uint32_t tlvll; /*!< Tx Reach Fill Level + : Use @ref TSPI_TxReachFillLevel */ + uint32_t rxrun; /*!< Stop/Active Rx Active Flag. + : Use @ref TSPI_RxState */ + uint32_t rxend; /*!< Rx Data Receive Complete Flag. + : Use @ref TSPI_RxDone */ + uint32_t intrxff; /*!< Rx FIFO Interrupt Flag + : Use @ref TSPI_RxFIFOInterruptFlag */ + uint32_t rffll; /*!< Rx FIFO Full Flag + : Use @ref TSPI_RxFIFOFullFlag */ + uint32_t rlvl; /*!< Rx Reach Fill Level + : Use @ref TSPI_RxReachFillLevel */ +} tspi_status_t; + +/*----------------------------------*/ +/** + * @struct tspi_error_t + * @brief Error flag. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t udrerr; /*!< Underrun Error. + : Use @ref TSPI_UnderrunErr */ + uint32_t ovrerr; /*!< Overrun Error. + : Use @ref TSPI_OverrunErr */ + uint32_t perr; /*!< Parity Error. + : Use @ref TSPI_ParityErr */ +} tspi_error_t; + + +/*----------------------------------*/ +/** + * @struct tspi_initial_setting_t + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + tspi_control1_t cnt1; /*!< Control1 setting. + : Use @ref tspi_control1_t */ + tspi_control2_t cnt2; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_control3_t cnt3; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_baudrate_t brd; /*!< Baudrate setting. + : Use @ref tspi_baudrate_t */ + tspi_fmtr0_t fmr0; /*!< Format control0 setting. + : Use @ref tspi_fmtr0_t */ + tspi_fmtr1_t fmr1; /*!< Format control1 setting. + : Use @ref tspi_fmtr1_t */ + tspi_sectcr0_t scr0; /*!< Sect control0 setting. + : Use @ref tspi_sectcr0_t */ + tspi_sectcr1_t scr1; /*!< Sect control1 setting. + : Use @ref tspi_sectcr1_t */ +} tspi_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief TSPI handle structure definition. +*/ +/*----------------------------------*/ +typedef struct tspi_handle { + TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ + tspi_initial_setting_t init; /*!< Initial setting. */ + uint32_t errcode; /*!< ErrorCode */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + tspi_transmit_t info; /*!< Transmit Data Information. */ + uint8_t tx_allign; /*!< Transmit Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + tspi_receive_t info; /*!< Receive Data Information. */ + uint8_t rx_allign; /*!< Receive Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} tspi_t; +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_functions TSPI Exported Functions + * @{ + */ +TXZ_Result tspi_init(tspi_t *p_obj); +TXZ_Result tspi_deinit(tspi_t *p_obj); +TXZ_Result tspi_format(tspi_t *p_obj); +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); +TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info); +void tspi_irq_handler_transmit(tspi_t *p_obj); +void tspi_irq_handler_receive(tspi_t *p_obj); +void tspi_error_irq_handler(tspi_t *p_obj); +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); +TXZ_Result tspi_error_clear(tspi_t *p_obj); +TXZ_Result tspi_discard_transmit(tspi_t *p_obj); +TXZ_Result tspi_discard_receive(tspi_t *p_obj); +/** + * @} + */ /* End of group TSPI_Exported_functions */ +/** + * @} + */ /* End of group TSPI */ +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TSPI_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart.h new file mode 100644 index 0000000..2a0663a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart.h @@ -0,0 +1,797 @@ +/** + ******************************************************************************* + * @file txz_uart.h + * @brief This file provides all the functions prototypes for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_H +#define __UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup UART UART + * @brief UART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/** + * @defgroup UART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */ +#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup UART_HalfClockSelect Half Clock Select + * @brief Output Terminal Select + * @{ + */ +#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */ +#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */ +/** + * @} + */ /* End of group UART_HalfClockSelect */ + +/** + * @defgroup UART_HalfClockMode Half Clock Mode + * @brief Half Clock Mode Setting. + * @{ + */ +#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */ +#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */ +/** + * @} + */ /* End of group UART_HalfClockMode */ + +/** + * @defgroup UART_HalfClockCTR Half Clock Mode Control + * @brief Half Clock Control. + * @{ + */ +#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */ +#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */ +/** + * @} + */ /* End of group UART_HalfClockCTR */ + +/** + * @defgroup UART_LoopBack Loop Back Function + * @brief Half Clock Control. + * @{ + */ +#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */ +#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */ +/** + * @} + */ /* End of group UART_LoopBack */ + + +/** + * @defgroup UART_NoiseFilter Noise Filter + * @brief Noise Filter Setting. + * @{ + */ +#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */ +#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */ +/** + * @} + */ /* End of group UART_NoiseFilter */ + + +/** + * @defgroup UART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definition. + * @{ + */ +#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */ +/** + * @} + */ /* End of group UART_CTSHandshake */ + + +/** + * @defgroup UART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definition. + * @{ + */ +#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */ +/** + * @} + */ /* End of group UART_RTSHandshake */ + + +/** + * @defgroup UART_DataComplementation Data Complementation + * @brief Enable/Disable Data Signal Complementation Macro Definition. + * @{ + */ +#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group UART_DataComplementation */ + + +/** + * @defgroup UART_DataDirection Data Direction + * @brief Data Direction Macro Definition. + * @{ + */ +#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */ +/*! + * @} + */ /* End of group UART_DataDirection */ + + +/** + * @defgroup UART_StopBit Stop Bit + * @brief Stop Bit Macro Definition. + * @{ + */ +#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */ +/** + * @} + */ /* End of group UART_StopBit */ + + +/** + * @defgroup UART_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */ +/** + * @} + */ /* End of group UART_ParityBit */ + + +/** + * @defgroup UART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ParityEnable */ + + +/** + * @defgroup UART_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */ +#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */ +#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */ +/** + * @} + */ /* End of group UART_DataLength */ + + +/** + * @defgroup UART_TxFillLevelRange Tx Fill Level Range + * @brief Transmit Fill Level Range Macro Definition. + * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */ +#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */ +/*! + * @} + */ /* End of group UART_TxFillLevelRange */ + + +/** + * @defgroup UART_RxFillLevelRange Rx Fill Level Range + * @brief Receive Fill Level Range Macro Definition. + * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */ +#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */ +/** + * @} + */ /* End of group UART_RxFillLevelRange */ + + +/** + * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrupt + * @brief Available Transmit FIFO Interrupt Macro Definition. + * @{ + */ +#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxFIFOInterrupt */ + + +/** + * @defgroup UART_TxInterrupt Tx Interrupt + * @brief Available Transmit Interrupt Macro Definition. + * @{ + */ +#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxInterrupt */ + + +/** + * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrupt + * @brief Available Receive FIFO Interrupt Macro Definition. + * @{ + */ +#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxFIFOInterrupt */ + + +/** + * @defgroup UART_RxInterrupt Rx Interrupt + * @brief Available Receive Interrupt Macro Definition. + * @{ + */ +#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxInterrupt */ + + +/** + * @defgroup UART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ErrorInterrupt */ + + +/** + * @defgroup UART_Prescaler Prescaler + * @brief Prescaler Macro Definition. + * @{ + */ +#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */ +#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */ +#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */ +#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */ +#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */ +#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */ +#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */ +#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */ +#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */ +/** + * @} + */ /* End of group UART_Prescaler */ + + +/** + * @defgroup UART_Clock_Mask Clock Mask + * @brief Clock Mask Macro Definition. + * @{ + */ +#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */ +/** + * @} + */ /* End of group UART_Clock_Mask */ + + +/** + * @defgroup UART_Division Division + * @brief Enable/Disable Division Macro Definition. + * @{ + */ +#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */ +/** + * @} + */ /* End of group UART_Division */ + + +/** + * @defgroup UART_RangeK Range K + * @brief Range of K Macro Definition. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)". + * @{ + */ +#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group UART_RangeK */ + + +/** + * @defgroup UART_RangeN Range N + * @brief Range of N Macro Definition. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)". + * @{ + */ +#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */ +#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group UART_RangeN */ + + +/** + * @defgroup UART_SettingEnable Setting Enable + * @brief Enable/Disable Setting Macro Definition. + * @{ + */ +#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */ +#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group UART_SettingEnable */ + + +/** + * @defgroup UART_TxState Tx State + * @brief Transmitting State Macro Definition. + * @{ + */ +#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */ +#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */ +/** + * @} + */ /* End of group UART_TxState */ + + +/** + * @defgroup UART_TxDone Transmitting Done + * @brief Transmitting Done Macro Definition. + * @{ + */ +#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */ +#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */ +/** + * @} + */ /* End of group UART_TxDone */ + + +/** + * @defgroup UART_TxReachFillLevel Tx Reach Fill Level + * @brief Reach Transmitting Fill Level Macro Definition. + * @{ + */ +#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */ +#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */ +/** + * @} + */ /* End of group UART_TxReachFillLevel */ + + +/** + * @defgroup UART_TxFifoLevel Tx FIFO Fill Level + * @brief Transmitting FIFO Fill Level Macro Definition. + * @{ + */ +#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */ +/** + * @} + */ /* End of group UART_TxFifoLevel */ + + +/** + * @defgroup UART_RxState Rx State + * @brief Receive State Macro Definition. + * @{ + */ +#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */ +#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */ +/** + * @} + */ /* End of group UART_RxState */ + + +/** + * @defgroup UART_RxDone Rx Done + * @brief Receive Done Macro Definition. + * @{ + */ +#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */ +#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */ +/** + * @} + */ /* End of group UART_RxDone */ + + +/** + * @defgroup UART_RxReachFillLevel Rx Reach Fill Level + * @brief Reach Receive Fill Level Macro Definition. + * @{ + */ +#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */ +#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */ +/** + * @} + */ /* End of group UART_RxReachFillLevel */ + + +/** + * @defgroup UART_RxFifoLevel Rx FIFO Fill Level + * @brief Receive FIFO Fill Level Macro Definition. + * @{ + */ +#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */ +/** + * @} + */ /* End of group UART_RxFifoLevel */ + + +/** + * @defgroup UART_TriggerErr Trigger Error + * @brief Trigger Error Macro Definition. + * @{ + */ +#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */ +/** + * @} + */ /* End of group UART_TxTriggerErr */ + + +/** + * @defgroup UART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group UART_OverrunErr */ + + +/** + * @defgroup UART_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group UART_ParityErr */ + + +/** + * @defgroup UART_FramingErr Framing Error + * @brief Framing Error Macro Definition. + * @{ + */ +#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group UART_FramingErr */ + + +/** + * @defgroup UART_BreakErr Break Error + * @brief Break Error Macro Definition. + * @{ + */ +#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group UART_BreakErr */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_typedef UART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. + * @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this. + * @attention "num" must be over FIFO max num. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive8_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. + * @brief When data length definition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive16_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef union { + uart_receive8_t rx8; /*!< @ref uart_receive8_t */ + uart_receive16_t rx16; /*!< @ref uart_receive16_t */ +} uart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. + * @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit8_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. + * @brief When data length definition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. + Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit16_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef union { + uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */ + uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */ +} uart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prsel; /*!< Prescaler. + : Use @ref UART_Prescaler */ +} uart_clock_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ken; /*!< Enable/Disable Division Definition. + : Use @ref UART_Division */ + uint32_t brk; /*!< Division Value K. + : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */ +} uart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit FIFO Interrupt. + : Use @ref UART_TxFIFOInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */ +} uart_tx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive FIFO Interrupt. + : Use @ref UART_RxFIFOInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */ +} uart_rx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + uart_clock_t clock; /*!< Clock setting. + : Use @ref uart_clock_t */ + uart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref uart_boudrate_t */ + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref UART_TxInterrupt */ + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref UART_RxInterrupt */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref UART_ErrorInterrupt */ + uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting. + : Use @ref uart_tx_fifo_t */ + uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting. + : Use @ref uart_rx_fifo_t */ + uint32_t hct; /*!< Half Clock Terminal Select. + : Use @ref UART_HalfClockSelect */ + uint32_t hcm; /*!< Half Clock Mode Select. + : Use @ref UART_HalfClockMode */ + uint32_t hcc; /*!< Half Clock Control. + : Use @ref UART_HalfClockCTR */ + uint32_t lbc; /*!< Loop Back Control. + : Use @ref UART_LoopBack */ + uint32_t nf; /*!< UTxRXD Noise Filter. + : Use @ref UART_NoiseFilter */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref UART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref UART_RTSHandshake */ + uint32_t iv; /*!< Data Signal Complementation. + : Use @ref UART_DataComplementation */ + uint32_t dir; /*!< Data Direction. + : Use @ref UART_DataDirection */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref UART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref UART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref UART_ParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref UART_DataLength */ +} uart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief UART handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_UART_TypeDef *p_instance; /*!< Registers base address. */ + uart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + uart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + uart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} uart_t; + +/** + * @} + */ /* End of group UART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_functions UART Exported Functions + * @{ + */ +TXZ_Result uart_init(uart_t *p_obj); +TXZ_Result uart_deinit(uart_t *p_obj); +TXZ_Result uart_discard_transmit(uart_t *p_obj); +TXZ_Result uart_discard_receive(uart_t *p_obj); +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info); +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info); +void uart_transmit_irq_handler(uart_t *p_obj); +void uart_receive_irq_handler(uart_t *p_obj); +void uart_error_irq_handler(uart_t *p_obj); +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status); +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error); +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting); +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart_include.h new file mode 100644 index 0000000..c404645 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/inc/txz_uart_include.h @@ -0,0 +1,471 @@ +/** + ******************************************************************************* + * @file txz_uart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_INCLUDE_H +#define __UART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/** + * @defgroup UART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define UART_NULL ((void *)0) +/** + * @} + */ /* End of group UART_NullPointer */ + +/** + * @defgroup UART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group UART_ParameterResult */ + +/** + * @defgroup UARTxSWRST UARTxSWRST Register + * @brief UARTxSWRST Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | SWRSTF | + * | 6:2 | - | + * | 1:0 | SWRST | + * @{ + */ +/* SWRSTF */ +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */ +#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */ +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */ +/* SWRST */ +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */ +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */ +/** + * @} + */ /* End of group UARTxSWRST */ + +/** + * @defgroup UARTxCR0 UARTxCR0 Register + * @brief UARTxCR0 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | HBSST | + * | 17 | HBSMD | + * | 16 | HBSEN | + * | 15 | LPB | + * | 14-12 | NF[2:0] | + * | 11 | - | + * | 10 | CTSE | + * | 9 | RTSE | + * | 8 | WU | + * | 7 | - | + * | 6 | IV | + * | 5 | DIR | + * | 4 | SBLEN | + * | 3 | EVEN | + * | 2 | PE | + * | 1-0 | SM[1:0] | + * @{ + */ +/* HBSST */ +#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */ +/* HBSMD */ +#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */ +/* HBSEN */ +#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */ +#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */ +#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */ +/* LPB */ +#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */ +#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */ +#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */ +/* WU */ +#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */ +#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */ +#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */ +/** + * @} + */ /* End of group UARTxCR0 */ + +/** + * @defgroup UARTxCR1 UARTxCR1 Register + * @brief UARTxCR1 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-15 | - | + * | 14-12 | TIL[2:0] | + * | 11 | - | + * | 10-8 | RIL[2:0] | + * | 7 | INTTXFE | + * | 6 | INTTXWE | + * | 5 | INTRXFE | + * | 4 | INTRXWE | + * | 3 | - | + * | 2 | INTERR | + * | 1 | DMATE | + * | 0 | DMARE | + * @{ + */ +/* RIL */ +#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */ +/* DMATE */ +#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */ +#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */ +#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */ +/* DMARE */ +#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */ +#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */ +#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */ +/** + * @} + */ /* End of group UARTxCR1 */ + +/** + * @defgroup UARTxTRANS UARTxTRANS Register + * @brief UARTxTRANS Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | BK | + * | 2 | TXTRG | + * | 1 | TXE | + * | 0 | RXE | + * @{ + */ +/* BK */ +#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */ +#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */ +#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */ +/* TXTRG */ +#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */ +#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */ +#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */ +/* TXE */ +#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */ +#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */ +#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */ +/* RXE */ +#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */ +#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */ +#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */ +/* TXE,RXE */ +#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */ +/** + * @} + */ /* End of group UARTxTRANS */ + +/** + * @defgroup UARTxDR UARTxDR Register + * @brief UARTxDR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | PERR | + * | 17 | FERR | + * | 16 | BERR | + * | 15:9 | - | + * | 8:0 | DR | + * @{ + */ +/* DR */ +#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */ +#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */ +/** + * @} + */ /* End of group UARTxDR */ + +/** + * @defgroup UARTxSR UARTxSR Register + * @brief UARTxSR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31 | SUE | + * | 30:16 | - | + * | 15 | TXRUN | + * | 14 | TXEND | + * | 13 | TXFF | + * | 12 | - | + * | 11:8 | TLVL | + * | 7 | RXRUN | + * | 6 | RXEND | + * | 5 | RXFF | + * | 4 | - | + * | 3:0 | RLVL | + * @{ + */ +/* SUE */ +#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */ +/* TXEND */ +#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */ +#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */ +#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */ +/* TXFF */ +#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */ +#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */ +#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */ +/* TLVL */ +#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */ +/* RXEND */ +#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */ +#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */ +#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */ +/* RXFF */ +#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */ +#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */ +#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */ +/* RLVL */ +#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */ +/** + * @} + */ /* End of group UARTxSR */ + +/** + * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register + * @brief UARTxFIFOCLR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | TFCLR | + * | 0 | RFCLR | + * @{ + */ +/* TFCLR */ +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */ +/* RFCLR */ +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */ +/** + * @} + */ /* End of group UARTxFIFOCLR */ + +/** + * @defgroup UARTxERR UARTxERR Register + * @brief UARTxERR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-5 | - | + * | 4 | TRGERR | + * | 3 | OVRERR | + * | 2 | PERR | + * | 1 | FERR | + * | 0 | BERR | + * @{ + */ +/* TRGERR */ +#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */ +#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */ +#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */ +#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */ +/* OVRERR */ +#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */ +#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */ +#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */ +#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */ +/* PERR */ +#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */ +#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */ +#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */ +#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */ +/* FERR */ +#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */ +#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */ +#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */ +#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */ +/* BERR */ +#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */ +#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */ +#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */ +#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */ +/** + * @} + */ /* End of group UARTxERR */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_functions + * @{ + */ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; +#endif +} + + +/** + * @} + */ /* End of group UART_Private_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc.c new file mode 100644 index 0000000..e7f2ca4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc.c @@ -0,0 +1,1067 @@ +/** + ******************************************************************************* + * @file txz_adc.c + * @brief This file provides API functions for ADC driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_adc_include.h" +#include "txz_adc_ch.h" +#include "txz_adc.h" + +#if defined(__ADC_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_macro ADC Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_Enumeration ADC Private Enumeration + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_Enumeration */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Variable Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_variable ADC Private Variable Definition + * @{ + */ +static adc_t *p_AdcObj; +/** + * @} + */ /* End of group ADC_Private_variable */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +static int32_t check_param_sampling_period0(adc_sampling_period0_t param); +static int32_t check_param_sampling_period1(adc_sampling_period1_t param); +static int32_t check_param_prescaler_output(adc_sclk_t param); +static int32_t check_param_interrupt(adc_int_t param); +static int32_t check_param_type(adc_conversion_t param); +static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max); +static void clear_ch_instance_info(adc_ch_t *p_ch); + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_sampling_period0(adc_sampling_period0_t param) + * @brief Check the Sampling Period's parameter. + * @param[in] param :Sampling Period's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_sampling_period0(adc_sampling_period0_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SAMPLING_PERIOD0_XN: + case ADC_SAMPLING_PERIOD0_X2N: + case ADC_SAMPLING_PERIOD0_X3N: + case ADC_SAMPLING_PERIOD0_X4N: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_sampling_period1(adc_sampling_period1_t param) + * @brief Check the Sampling Period's parameter. + * @param[in] param :Sampling Period's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_sampling_period1(adc_sampling_period1_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SAMPLING_PERIOD1_XN: + case ADC_SAMPLING_PERIOD1_X2N: + case ADC_SAMPLING_PERIOD1_X3N: + case ADC_SAMPLING_PERIOD1_X4N: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_prescaler_output(adc_sclk_t param) + * @brief Check the AD Prescaler Output's parameter. + * @param[in] param :AD Prescaler Output's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SCLK"ADC_SCLK_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_prescaler_output(adc_sclk_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SCLK_2: + case ADC_SCLK_4: + case ADC_SCLK_8: + case ADC_SCLK_16: + case ADC_SCLK_3: + case ADC_SCLK_5: + case ADC_SCLK_6: + case ADC_SCLK_10: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_interrupt(adc_int_t param) + * @brief Check the Interrupt's parameter. + * @param[in] param :Interrupt's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_IntEnable"ADC_INT_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_interrupt(adc_int_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_INT_DISABLE: + case ADC_INT_ENABLE: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_type(adc_conversion_t param) + * @brief Check the Conversion Type's parameter. + * @param[in] param :Conversion Type's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_Conversion"ADC_CONVERSION_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_type(adc_conversion_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_CONVERSION_DISABLE: + case ADC_CONVERSION_CNT: + case ADC_CONVERSION_SGL: + case ADC_CONVERSION_TRG: + case ADC_CONVERSION_HPTG: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) + * @brief Check the AIN Range's parameter. + * @param[in] ain :AIN Range's parameter + * @param[in] min :Range Min. + * @param[in] max :Range Max. + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note - + */ +/*--------------------------------------------------*/ +static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) +{ + int32_t result = ADC_PARAM_NG; + + if (min == 0) { + if (ain <= max) { + result = ADC_PARAM_OK; + } + } else { + if ((min <= ain) && (ain <= max)) { + result = ADC_PARAM_OK; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static void clear_ch_instance_info(adc_ch_t *p_ch) + * @brief Channel Instance Information Clear. + * @param[in] p_ch :Channel Instance Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +static void clear_ch_instance_info(adc_ch_t *p_ch) +{ + p_ch->p_tset = ADC_NULL; + p_ch->p_reg = ADC_NULL; + p_ch->init.type = ADC_CONVERSION_DISABLE; +} +/*--------------------------------------------------*/ +/*! + * @fn static void adc_compa_irq_handler( void ) + * @brief IRQ Handler for Compare_A done. + * @param - + * @retval - + * @note Call by Compare_A Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_compa_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->init.CMPxEN[0].handle != ADC_NULL)) { + p_AdcObj->init.CMPxEN[0].handle(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_compb_irq_handler( void ) + * @brief IRQ Handler for Compare_B done. + * @param - + * @retval - + * @note Call by Compare_B Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_compb_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->init.CMPxEN[1].handle != ADC_NULL)) { + p_AdcObj->init.CMPxEN[1].handle(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_single_irq_handler( void ) + * @brief IRQ Handler for single conversion done. + * @param - + * @retval - + * @note Call by Single Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_single_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.single != ADC_NULL)) { + p_AdcObj->handler.single(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_continuity_irq_handler( void ) + * @brief IRQ Handler for continuity conversion done. + * @param - + * @retval - + * @note Call by Continuity Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_continuity_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.continuity != ADC_NULL)) { + p_AdcObj->handler.continuity(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_trigger_irq_handler( void ) + * @brief IRQ Handler for trigger conversion done. + * @param - + * @retval - + * @note Call by Trigger Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_trigger_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.trigger != ADC_NULL)) { + p_AdcObj->handler.trigger(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_highpriority_irq_handler( void ) + * @brief IRQ Handler for highpriority conversion done. + * @param - + * @retval - + * @note Call by HigPriority Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_highpriority_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.highpriority != ADC_NULL)) { + p_AdcObj->handler.highpriority(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_init(adc_t *p_obj) + * @brief Initialize the ADC object. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_init(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + /* Check the parameter. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if ((void *)(p_obj->p_instance) == (void *)0) { + result = TXZ_ERROR; + } + if (check_param_sampling_period0(p_obj->init.clk.exaz0) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_sampling_period1(p_obj->init.clk.exaz1) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (p_obj->init.clk.sampling_select > 0x0100000) { + result = TXZ_ERROR; + } + if (check_param_prescaler_output(p_obj->init.clk.vadcld) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (result == TXZ_SUCCESS) { + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + uint32_t i; + + for (i = 0; i < ADC_NUM_MAX; i++) { + clear_ch_instance_info(&p_obj->info.ch[i]); + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCLK ---*/ + p_obj->p_instance->CLK = ((uint32_t)p_obj->init.clk.exaz0 | (uint32_t)p_obj->init.clk.exaz1 | (uint32_t)p_obj->init.clk.vadcld); + /*--- ADxEXAZSEL ---*/ + p_obj->p_instance->EXAZSEL = (uint32_t)p_obj->init.clk.sampling_select; + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); + /* wait 3us after set the MOD0 to 1 */ + wait(3); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->MOD1 = p_obj->init.mod1; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = p_obj->init.mod2; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_deinit(adc_t *p_obj) + * @brief Release the ADC object. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_deinit(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t i; + adc_ch_t *p_ch; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) { + clear_ch_instance_info(p_ch); + } + } + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCMPEN ---*/ + p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE); + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->MOD1 = ADC_MOD1_SCLK_3; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADC_MOD2_CLEAR; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) + * @brief ADC Channel Setting + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @param[in] p_setting :Channel Setting Source Address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_setting) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } + if (check_param_interrupt((adc_int_t)p_setting->interrupt) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_type((adc_conversion_t)p_setting->type) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_ain((adc_ain_range_t)p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (result == TXZ_SUCCESS) { + /*------------------------------*/ + /* Channel Class Construct */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch); + p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch); + p_ch->init.interrupt = p_setting->interrupt; + p_ch->init.type = p_setting->type; + p_ch->init.ain = p_setting->ain; + result = adc_ch_init(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) + * @brief ADC Channel Clear + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_deinit(p_ch); + /* Init Variable */ + clear_ch_instance_info(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) + * @brief Initialize the ADC Compare register + * @param[in] p_obj :ADC object. + * @param[in] p_cmpx_t :Clock information structure. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_cmpx_t) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) { + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; + } + if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) { + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_ENABLE) { + p_obj->init.CMPxEN[0].CMPEN = p_cmpx_t->CMPEN; + p_obj->init.CMPxEN[0].CMPCNT = p_cmpx_t->CMPCNT; + p_obj->init.CMPxEN[0].CMPCond = p_cmpx_t->CMPCond; + p_obj->init.CMPxEN[0].CMPBigSml = p_cmpx_t->CMPBigSml; + p_obj->init.CMPxEN[0].StrReg = p_cmpx_t->StrReg; + p_obj->init.CMPxEN[0].ADComp = p_cmpx_t->ADComp; + p_obj->init.CMPxEN[0].handle = p_cmpx_t->handle; + p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; + p_obj->p_instance->CMPCR0 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; + p_obj->p_instance->CMP0 = p_cmpx_t->ADComp; + } else if (p_cmpx_t->CMPEN == ADCMP1EN_ENABLE) { + p_obj->init.CMPxEN[1].CMPEN = p_cmpx_t->CMPEN; + p_obj->init.CMPxEN[1].CMPCNT = p_cmpx_t->CMPCNT; + p_obj->init.CMPxEN[1].CMPCond = p_cmpx_t->CMPCond; + p_obj->init.CMPxEN[1].CMPBigSml = p_cmpx_t->CMPBigSml; + p_obj->init.CMPxEN[1].StrReg = p_cmpx_t->StrReg; + p_obj->init.CMPxEN[1].ADComp = p_cmpx_t->ADComp; + p_obj->init.CMPxEN[1].handle = p_cmpx_t->handle; + p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; + p_obj->p_instance->CMPCR1 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; + p_obj->p_instance->CMP1 = p_cmpx_t->ADComp; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) + * @brief Release the ADC Compare register + * @param[in] p_obj :ADC object. + * @param[in] p_cmpx_t :Clock information structure. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_cmpx_t) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) { + p_obj->init.CMPxEN[0].CMPEN = 0; + p_obj->init.CMPxEN[0].CMPCNT = 0; + p_obj->init.CMPxEN[0].CMPCond = 0; + p_obj->init.CMPxEN[0].CMPBigSml = 0; + p_obj->init.CMPxEN[0].StrReg = 0; + p_obj->init.CMPxEN[0].ADComp = 0; + p_obj->init.CMPxEN[0].handle = (void *)0; + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; + p_obj->p_instance->CMPCR0 = 0; + p_obj->p_instance->CMP0 = 0; + } else if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) { + p_obj->init.CMPxEN[1].CMPEN = 0; + p_obj->init.CMPxEN[1].CMPCNT = 0; + p_obj->init.CMPxEN[1].CMPCond = 0; + p_obj->init.CMPxEN[1].CMPBigSml = 0; + p_obj->init.CMPxEN[1].StrReg = 0; + p_obj->init.CMPxEN[1].ADComp = 0; + p_obj->init.CMPxEN[1].handle = (void *)0; + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; + p_obj->p_instance->CMPCR1 = 0; + p_obj->p_instance->CMP1 = 0; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) + * @brief Get AD value + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_value) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Get Value */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_get_value(p_ch, p_value); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_start(adc_t *p_obj) + * @brief Start Conversion. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_start(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Enable Conversion */ + /*------------------------------*/ + uint32_t i; + adc_ch_t *p_ch; + uint32_t cr0 = (ADxCR0_ADEN_ENABLE | ADxCR0_CNT_DISABLE); + uint32_t cr1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + switch (p_ch->init.type) { + case ADC_CONVERSION_CNT: + cr0 |= ADxCR0_CNT_ENABLE; + break; + case ADC_CONVERSION_SGL: + cr0 |= ADxCR0_SGL_ENABLE; + break; + case ADC_CONVERSION_TRG: + cr1 |= ADxCR1_TRGEN_ENABLE; + break; + case ADC_CONVERSION_HPTG: + cr1 |= ADxCR1_HPTRGEN_ENABLE; + break; + default: + /* no processing */ + break; + } + } + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = cr1; + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = cr0; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_stop(adc_t *p_obj) + * @brief Stop Conversion. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_stop(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t i; + adc_ch_t *p_ch; + uint32_t value; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Disable Conversion */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Dummy Read */ + /*------------------------------*/ + /* Read is needed before the next convertion. */ + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) { + /* no processing */ + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) + * @brief Wait for single conversion to be completed + * @param[in] p_obj :ADC object. + * @param[in] timeout :Timeout(tick). + * @retval TXZ_DONE :Success. + * @retval TXZ_BUSY :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) +{ + TXZ_WorkState result = TXZ_BUSY; + TXZ_WorkState loopBreak = TXZ_BUSY; + uint32_t base = hal_get_tick(); + uint32_t current = 0; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_DONE; + } else { + /*------------------------------*/ + /* Check Status */ + /*------------------------------*/ + while (loopBreak == TXZ_BUSY) { + /*--- Check Status ---*/ + /* Read status. */ + status = p_obj->p_instance->ST; + /* Check status. */ + if ((status & ADxST_SNGF_MASK) == ADxST_SNGF_IDLE) { + result = TXZ_DONE; + loopBreak = TXZ_DONE; + } else { + /*--- Check Timeout ---*/ + if (timeout == 0) { + loopBreak = TXZ_DONE; + } else { + current = hal_get_tick(); + if (current > base) { + if ((current - base) >= timeout) { + loopBreak = TXZ_DONE; + } + } else { + base = current; + } + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @fn TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) + * @brief Get Conversion Status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-8 | - | - | + * | 7 | ADBF | AD Running Flag. Use @ref adc_status_t. | + * | 6-4 | - | - | + * | 3 | CNTF | Continuity Conversion Running Flag. Use @ref adc_cnt_status_t. | + * | 2 | SNGF | Single Conversion Running Flag. Use @ref adc_sgl_status_t. | + * | 1 | TRGF | Trigger Conversion Running Flag. Use @ref adc_trg_status_t. | + * | 0 | - | - | + * + * @param[in] p_obj :ADC object. + * @param[out] p_status :Conversion Status. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_status) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Read Register */ + /*------------------------------*/ + *p_status = p_obj->p_instance->ST; + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc_ch.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc_ch.c new file mode 100644 index 0000000..0c0241f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_adc_ch.c @@ -0,0 +1,347 @@ +/** + ******************************************************************************* + * @file txz_adc_ch.c + * @brief This file provides API functions for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_adc_include.h" +#include "txz_adc_ch.h" + +#if defined(__ADC_CH_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +/* no define */ +#endif + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn static uint32_t get_conversion_data(uint32_t reg) + * @brief Get convertion data from ADxREGn. + * @param[in] reg :ADxREGn data. + * @retval Convertion data. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t get_conversion_data(uint32_t reg) +{ + uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4); + + return (result); +} +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_init(adc_ch_t *p_obj) + * @brief Initialize the ADC Channel object. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_init(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + /*--- ADxTSET ---*/ + *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) + * @brief Release the ADC Channel object. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0); + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) + * @brief Enable Interrupt. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) + * @brief Disable Interrupt. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) + * @brief Get conversion value. + * @param p_obj :ADC Channel object. + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has done. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + reg = *p_obj->p_reg; + /*------------------------------*/ + /* Check Result */ + /*------------------------------*/ + if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { + *p_value = get_conversion_data(reg); + result = TXZ_SUCCESS; + } + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_cg.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_cg.c new file mode 100644 index 0000000..440e012 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_cg.c @@ -0,0 +1,498 @@ +/** + ******************************************************************************* + * @file txz_cg.c + * @brief This file provides API functions for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_cg.h" + +#if defined(__CG_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup CG + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */ + +#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */ +#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */ +#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */ +#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */ +#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */ + +#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */ +#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */ +#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */ +#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */ +#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */ + +#define CG_PRCK_MASK ((uint32_t)0x00000F00) /*!< CG PRCK mask */ + +#define CG_PRCK_1 ((uint32_t)0x00000000) /*!< CG PhiT0 fc register value */ +#define CG_PRCK_2 ((uint32_t)0x00000100) /*!< CG PhiT0 fc/2 register value */ +#define CG_PRCK_4 ((uint32_t)0x00000200) /*!< CG PhiT0 fc/4 register value */ +#define CG_PRCK_8 ((uint32_t)0x00000300) /*!< CG PhiT0 fc/8 register value */ +#define CG_PRCK_16 ((uint32_t)0x00000400) /*!< CG PhiT0 fc/16 register value */ +#define CG_PRCK_32 ((uint32_t)0x00000500) /*!< CG PhiT0 fc/32 register value */ +#define CG_PRCK_64 ((uint32_t)0x00000600) /*!< CG PhiT0 fc/64 register value */ +#define CG_PRCK_128 ((uint32_t)0x00000700) /*!< CG PhiT0 fc/128 register value */ +#define CG_PRCK_256 ((uint32_t)0x00000800) /*!< CG PhiT0 fc/256 register value */ +#define CG_PRCK_512 ((uint32_t)0x00000900) /*!< CG PhiT0 fc/512 register value */ + +#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */ + +#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG PhiT0 fc register status */ +#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG PhiT0 fc/2 register status */ +#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG PhiT0 fc/4 register status */ +#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG PhiT0 fc/8 register status */ +#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG PhiT0 fc/16 register status */ +#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG PhiT0 fc/32 register status */ +#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG PhiT0 fc/64 register status */ +#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG PhiT0 fc/128 register status */ +#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG PhiT0 fc/256 register status */ +#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG PhiT0 fc/512 register status */ + +#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG PhiT0 fc division value */ +#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG PhiT0 fc/2 division value */ +#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG PhiT0 fc/4 division value */ +#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG PhiT0 fc/8 division value */ +#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG PhiT0 fc/16 division value */ +#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG PhiT0 fc/32 division value */ +#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG PhiT0 fc/64 division value */ +#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG PhiT0 fc/128 division value */ +#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG PhiT0 fc/256 division value */ +#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG PhiT0 fc/512 division value */ + + +#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */ + +#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG PhiT0 fc/PRCK value */ +#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG PhiT0 fc/PRCK/2 value */ +#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG PhiT0 fc/PRCK/4 value */ + +#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm PhiT0 division value */ +#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm PhiT0/2 division value */ +#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm PhiT0/4 division value */ + +#define CG_IHOSC_DISABLE ((uint32_t)0x00000000) /*!< Internal high-speed oscillator disable */ +#define CG_IHOSC_ENABLE ((uint32_t)0x00000001) /*!< Internal high-speed oscillator enable */ + +#define CG_IHOSC1EN ((uint32_t)0x00000000) /*!< CG OSCCR bit0 */ + +#define CG_MCKSELGST_MASK ((uint32_t)0x00C00000) /*!< CG MCKSELGST mask */ +#define CG_MCKSELGST_1 ((uint32_t)0x00000000) /*!< CG fsysm fc/PRCK value */ +#define CG_MCKSELGST_2 ((uint32_t)0x00400000) /*!< CG fsysm fc/PRCK/2 value */ +#define CG_MCKSELGST_4 ((uint32_t)0x00800000) /*!< CG fsysm fc/PRCK/4 value */ + + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_typedef CG Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_fuctions CG Private Fuctions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_fsysm(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + switch (p_obj->p_instance->SYSCR & CG_MCKSELGST_MASK) { + case CG_MCKSELGST_1: /* fsysm -> fc/PRCK */ + result = SystemCoreClock / CG_FSYSM_1_DIV; + break; + case CG_MCKSELGST_2: /* fsysm -> fc/PRCK/2 */ + result = SystemCoreClock / CG_FSYSM_2_DIV; + break; + case CG_MCKSELGST_4: /* fsysm -> fc/PRCK/4 */ + result = SystemCoreClock / CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); + +} + +/*--------------------------------------------------*/ +/** + * @brief Update PrescalerClock according register values. + * @param p_obj :CG object. + * @retval PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_phyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* PhiT0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* PhiT0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* PhiT0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* PhiT0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* PhiT0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* PhiT0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* PhiT0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* PhiT0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* PhiT0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* PhiT0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_mphyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* PhiT0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* PhiT0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* PhiT0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* PhiT0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* PhiT0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* PhiT0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* PhiT0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* PhiT0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* PhiT0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* PhiT0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) { + case CG_MCKSELPST_1: /* PhiT0 -> fc/PRCK */ + result /= CG_FSYSM_1_DIV; + break; + case CG_MCKSELPST_2: /* PhiT0 -> fc/PRCK/2 */ + result /= CG_FSYSM_2_DIV; + break; + case CG_MCKSELPST_4: /* PhiT0 -> fc/PRCK/4 */ + result /= CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Internal high-speed oscillator enable. + * @param p_obj :CG object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result cg_ihosc_enable(cg_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* Internal high-speed oscillator is enable. */ + (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Internal high-speed oscillator disable. + * @param p_obj :CG object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result cg_ihosc_disable(cg_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* Internal high-speed oscillator is disable. */ + (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_DISABLE; + + return (result); +} +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__CG_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fc.c new file mode 100644 index 0000000..e849f1c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fc.c @@ -0,0 +1,695 @@ +/** + ******************************************************************************* + * @file flash512ud32_b.c + * @brief This file provides API functions for FLASH. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include +#include "txz_fc.h" +//#include "txz_sample_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @defgroup Flash_Userboot Flash_Userboot Sample Appli + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ +#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */ +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ +#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */ +#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ +#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ +#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ + +/****************** Changed by TSIP *************************************/ +///* Area Selection All */ +#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) +#define FC_AREASEL_EXPECT_AREA1 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area1 */ +#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) //select Area 0 +#define FC_AREASEL_AREA1 (uint32_t)(0x00000070UL) /*!< RW, Selects area1 */ +#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0FF8UL) //mask Area 0 +#define FC_AREASEL_MASK_AREA1 (uint32_t)(0xFF8F0F8FUL) /*!< RW, Selects area1 */ +#define FC_AREASEL_WRITEA0_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode(area0) */ +#define FC_AREASEL_WRITEA1_MODE (uint32_t)(0x08000000UL) /*!< R, Write Mode(area1) */ +static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { + (0x5E000000UL), /*!< CODE FLASH Page0 */ + (0x5E001000UL), /*!< CODE FLASH Page1 */ + (0x5E002000UL), /*!< CODE FLASH Page2 */ + (0x5E003000UL), /*!< CODE FLASH Page3 */ + (0x5E004000UL), /*!< CODE FLASH Page4 */ + (0x5E005000UL), /*!< CODE FLASH Page5 */ + (0x5E006000UL), /*!< CODE FLASH Page6 */ + (0x5E007000UL), /*!< CODE FLASH Page7 */ + (0x5E008000UL), /*!< CODE FLASH Page8 */ + (0x5E009000UL), /*!< CODE FLASH Page9 */ + (0x5E00A000UL), /*!< CODE FLASH Page10 */ + (0x5E00B000UL), /*!< CODE FLASH Page11 */ + (0x5E00C000UL), /*!< CODE FLASH Page12 */ + (0x5E00D000UL), /*!< CODE FLASH Page13 */ + (0x5E00E000UL), /*!< CODE FLASH Page14 */ + (0x5E00F000UL), /*!< CODE FLASH Page15 */ + (0x5E010000UL), /*!< CODE FLASH Page16 */ + (0x5E011000UL), /*!< CODE FLASH Page17 */ + (0x5E012000UL), /*!< CODE FLASH Page18 */ + (0x5E013000UL), /*!< CODE FLASH Page19 */ + (0x5E014000UL), /*!< CODE FLASH Page20 */ + (0x5E015000UL), /*!< CODE FLASH Page21 */ + (0x5E016000UL), /*!< CODE FLASH Page22 */ + (0x5E017000UL), /*!< CODE FLASH Page23 */ + (0x5E018000UL), /*!< CODE FLASH Page24 */ + (0x5E019000UL), /*!< CODE FLASH Page25 */ + (0x5E01A000UL), /*!< CODE FLASH Page26 */ + (0x5E01B000UL), /*!< CODE FLASH Page27 */ + (0x5E01C000UL), /*!< CODE FLASH Page28 */ + (0x5E01D000UL), /*!< CODE FLASH Page29 */ + (0x5E01E000UL), /*!< CODE FLASH Page30 */ + (0x5E01F000UL) /*!< CODE FLASH Page31 */ +}; + +/** + * @} + */ /* End of group Flash_Userboot_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ +/** + * @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef + * @{ + */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables + * @{ + */ +/** + * @} + */ /* End of group Flash_Userboot_Private_variables */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions + * @{ + */ +__STATIC_INLINE TXZ_Result fc_enable_areasel0(void); +__STATIC_INLINE TXZ_Result fc_disable_areasel0(void); +__STATIC_INLINE TXZ_Result fc_enable_areasel1(void); +__STATIC_INLINE TXZ_Result fc_disable_areasel1(void); +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind); +static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size); + +/*--------------------------------------------------*/ +/** + * @brief Enables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_enable_areasel0(void) +{ + TXZ_Result retval = TXZ_ERROR; + + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + reg |= FC_AREASEL_AREA0; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the FCAREASEL register the SSF0 was set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA0_MODE) == FC_AREASEL_WRITEA0_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Disables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_disable_areasel0(void) +{ + TXZ_Result retval = TXZ_ERROR; + + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + reg |= FC_AREASEL_EXPECT_AREA0; + + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the SSF0 of the FCAREASEL register is not set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA0_MODE) != FC_AREASEL_WRITEA0_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + return (retval); +} +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_enable_areasel1(void) +{ + TXZ_Result retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1; + reg |= FC_AREASEL_AREA1; + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->AREASEL = reg; + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA1_MODE) == FC_AREASEL_WRITEA1_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + return (retval); +} +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_disable_areasel1(void) +{ + TXZ_Result retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1; + reg |= FC_AREASEL_EXPECT_AREA1; + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->AREASEL = reg; + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA1_MODE) != FC_AREASEL_WRITEA1_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Writes data of the Flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval1; + uint32_t retval0; + volatile uint32_t *addr1; + volatile uint32_t *addr2; + volatile uint32_t *addr3; + uint32_t *source = (uint32_t *) src_address; + + addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + addr3 = (uint32_t *)((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP); + /* Enables the AREA0. Write Mode. */ + retval0 = fc_enable_areasel0(); + retval1 = fc_enable_areasel1(); + + if ((retval0 == TXZ_SUCCESS) + && (retval1 == TXZ_SUCCESS)) { + uint32_t i; + + *addr1 = (0x000000AAUL); /* bus cycle 1 */ + *addr2 = (0x00000055UL); /* bus cycle 2 */ + *addr1 = (0x000000A0UL); /* bus cycle 3 */ + for (i = (0UL); i < size; i += (0x4UL)) { + *addr3 = *source; + source++; + } + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + }; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { + }; + } + + /* Disables the AREA0. Read Mode. */ + retval0 = fc_disable_areasel0(); + retval1 = fc_disable_areasel1(); +} + +/*--------------------------------------------------*/ +/** + * @brief Verifies data of the Flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + TXZ_Result retval = TXZ_ERROR; + int res = memcmp(src_address, dst_address, size); + if (res == 0) { + retval = TXZ_SUCCESS; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the flash ROM. + * @param uint32_t* flash_top_address : flash top address + * @param uint32_t* erase_top_address : erase top address + * @param fc_erase_kind_t kind : Chip, Area, Block, Page, etc. + * @return - + * @note This function erases specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +//TXZ_Result fc_erase_pages_flash(uint32_t* top_address, uint32_t* erase_top_address) +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind) +{ + TXZ_Result retval0; + + TXZ_Result retval1; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC2_ADDR); + + volatile uint32_t *addr3 = (uint32_t *) erase_top_address; + + /* Enables the AREA0. Write Mode. */ + retval0 = fc_enable_areasel0(); + retval1 = fc_enable_areasel1(); + + if ((retval0 == TXZ_SUCCESS) + && (retval1 == TXZ_SUCCESS)) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x00000080UL); + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr3 = kind; + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + }; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { + }; + } + + /* Disables the AREA0. Read Mode. */ + retval0 = fc_disable_areasel0(); + retval1 = fc_disable_areasel1(); +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the Flash ROM every 4bytes. + * @param uint32_t* : addrress + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size) +{ + TXZ_Result retval = TXZ_SUCCESS; + + uint32_t i; + + for (i = 0; i < (size / sizeof(uint32_t)); i++) { + uint32_t *addr = &address[i]; + if (*addr != FC_BRANK_VALUE) { + retval = TXZ_ERROR; + break; + } + } + + return (retval); +} + +/** + * @} + */ /* End of group Flash_Userboot_Private_fuctions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Exported_functions Flash_Userboot Exported Functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Get the status of the flash auto operation. + * @param fc_sr0_t : status + * @return Result. + * @retval TXZ_BUSY : Busy. + * @retval TXZ_DONE : Done. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_WorkState fc_get_status(fc_sr0_t status) +{ + TXZ_WorkState retval = TXZ_BUSY; + uint32_t work32; + + /* Reads the FCSR0. Masks the other specfic status */ + work32 = TSB_FC->SR0 & (uint32_t)status; + + /* Confirms the specific status of the flash ROM */ + if (work32 == (uint32_t)status) { + retval = TXZ_DONE; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the code flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the code Flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + TXZ_Result retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + + uint32_t i; + /* Checks the code Flash ROM status */ + for (i = 0; i < size; i += (uint32_t)(0x10UL)) { + /* Writes 16bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), (uint32_t *)((uint32_t)dst_address + i), (uint32_t)(0x10UL)); + } + + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, dst_address, size); + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the code flash ROM. + * @param first_page : The first page to erase + * @param num_of_pages : The number of pages to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages) +{ + TXZ_Result retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum pages. */ + if ((first_page + num_of_pages) <= FC_MAX_PAGES) { + uint8_t i; + for (i = 0; i < num_of_pages ; i++) { + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_code_flash_address[first_page + i], + FC_ERASE_KIND_PAGE); + } + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)fc_const_code_flash_address[first_page], FC_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the code Flash ROM of specified pages. + * @param first_page : The first page which checks a blank. + * @param last_page : The last page which checks a blank.. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t last_page) +{ + TXZ_Result retval; + + uint32_t *address = (uint32_t *)fc_const_code_flash_address[first_page]; + uint32_t size = ((uint32_t)(last_page - first_page + 1) * (uint32_t)FC_PAGE_SIZE); + + retval = fc_blank_check(address, size); + + return (retval); +} + +/*--------------------------------------------------*/ +/*************** written by TSIP ******************/ +/** + * @brief Erases the entire block of code Flash ROM of specified address. + * @param uint32_t *top_addr : top address of Flash ROM. + * @param uint32_t *blk_addr : start address of block to be erased. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr) +{ + TXZ_Result retval = TXZ_SUCCESS; + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, blk_addr, FC_ERASE_KIND_BLOCK); + /* Checks a blank of the specific block. */ + if (fc_blank_check(blk_addr, (uint32_t)0x8000) == TXZ_ERROR) { + retval = TXZ_ERROR; + } else { + // do nothing + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + + +/** + * @} + */ /* End of group Flash_Userboot_Exported_functions */ + +/** + * @} + */ /* End of group Flash_Userboot */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_flash.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_flash.c new file mode 100644 index 0000000..a35f254 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_flash.c @@ -0,0 +1,219 @@ +/** + ******************************************************************************* + * @file txz_flash.c + * @brief This file provides API functions for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_flash.h" + +#if defined(__FLASH_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FLASH + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_macro FLASH Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ +/** + * @defgroup wait Configuration + * @brief wait Configuration. + * @{ + */ +/* FC ACCR setting configration */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_ACCR_CODE_7CLK (0x00000006UL) /*!< 7clock(less than 200MHZ). */ +#define FC_ACCR_CODE_6CLK (0x00000005UL) /*!< 6clock(less than 160MHZ). */ +#define FC_ACCR_CODE_5CLK (0x00000004UL) /*!< 5clock(less than 120MHZ). */ +#define FC_ACCR_CODE_4CLK (0x00000003UL) /*!< 4clock(less than 100MHZ). */ +#define FC_ACCR_CODE_3CLK (0x00000002UL) /*!< 3clock(less than 80MHZ). */ +#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */ +#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */ +#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */ +#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */ +#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */ + +#define FC_ACCR_DATA (FC_ACCR_DATA_7CLK) +#define FC_ACCR_DATA_7CLK (0x00000600UL) /*!< 7clock(Must). */ + +/** + * @} + */ /* End of group waitConfiguration */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_typedef FLASH Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_fuctions FLASH Private Fuctions + * @{ + */ + +/** + * @} + */ /* End of group FLASH_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FLASH_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Raed clock set. + * @param none. + * @retval none. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_read_clock_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock <= FC_ACCR_80MHZ) { /* less than 80MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_100MHZ) { /* less than 100MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_120MHZ) { /* less than 120MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA); + } else if (sysclock <= FC_ACCR_200MHZ) { /* less than 200MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA); + } + + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->ACCR = regval; + while ((TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA)) + && (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA))) { + /* no processing */ + } +} + +/** + * @} + */ /* End of group FLASH_Exported_functions */ + +/** + * @} + */ /* End of group FLASH */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__FLASH_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart.c new file mode 100644 index 0000000..73d1061 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart.c @@ -0,0 +1,1384 @@ +/** + ******************************************************************************* + * @file txz_fuart.c + * @brief This file provides API functions for FUART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_fuart_include.h" +#include "txz_fuart.h" + +#if defined(__FUART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/** + * @defgroup FUART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define FUART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define FUART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define FUART_CFG_GET_BOUDRATE FUART_CFG_GET_BOUDRATE_ENABLE /*!< Disable/Enable Get Bourate Setting */ + +#define FUART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define FUART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define FUART_CFG_GET_BOUDRATE_TYPE FUART_CFG_GET_BOUDRATE_TYPE_ALL /*!< Get Bourate Type Setting */ + +#define FUART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)1) /*!< Error Margin(%). */ +#define FUART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group FUART_BourateConfig */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_typedef FUART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_fuctions FUART Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef __DEBUG__ */ +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_CTS_DISABLE: + case FUART_CTS_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_RTS_DISABLE: + case FUART_RTS_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_STOP_BIT_1: + case FUART_STOP_BIT_2: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_PARITY_BIT_ODD: + case FUART_PARITY_BIT_EVEN: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_PARITY_DISABLE: + case FUART_PARITY_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_DATA_LENGTH_5: + case FUART_DATA_LENGTH_6: + case FUART_DATA_LENGTH_7: + case FUART_DATA_LENGTH_8: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_FIFO_LEVEL_4: + case FUART_FIFO_LEVEL_8: + case FUART_FIFO_LEVEL_16: + case FUART_FIFO_LEVEL_24: + case FUART_FIFO_LEVEL_28: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_FIFO_LEVEL_4: + case FUART_FIFO_LEVEL_8: + case FUART_FIFO_LEVEL_16: + case FUART_FIFO_LEVEL_24: + case FUART_FIFO_LEVEL_28: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_TX_INT_DISABLE: + case FUART_TX_INT_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_RX_INT_DISABLE: + case FUART_RX_INT_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrpt's parameter. + * @param param :Error Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + param &= ~(FUART_OV_ERR_INT_ENABLE | FUART_BK_ERR_INT_ENABLE | FUART_PA_ERR_INT_ENABLE | FUART_FR_ERR_INT_ENABLE | FUART_TO_ERR_INT_ENABLE); + + if (param == 0) { + result = FUART_PARAM_OK; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + /*--- Now, FUART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((FUART_RANGE_K_MIN <= param) && (param <= FUART_RANGE_K_MAX)) +#else + if (param <= FUART_RANGE_K_MAX) +#endif + { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if ((FUART_RANGE_N_MIN <= param) && (param <= FUART_RANGE_N_MAX)) { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if (param != 0) { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if (param != 0) { + result = FUART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef __DEBUG__ */ + +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi T0 */ + tx64 = (uint64_t)((uint64_t)clock << (FUART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * FUART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (uint64_t)k); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group FUART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the FUART object. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_init(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.tx_int.inttx)); + assert_param(check_param_rx_int(p_obj->init.rx_int.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fill_level_range(p_obj->init.tx_int.level)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rx_int.level)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable FUART */ + /*------------------------------*/ + p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | + FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); + /*------------------------------*/ + /* Interrupt Disable */ + /*------------------------------*/ + p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | + FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | + FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | + FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | + FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); + + /*------------------------------*/ + /* FIFO Disable */ + /*------------------------------*/ + p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + p_obj->p_instance->BRD = p_obj->init.boudrate.brn; + p_obj->p_instance->FBRD = p_obj->init.boudrate.brk; + p_obj->p_instance->LCR_H = (p_obj->init.stpa | p_obj->init.sm | + p_obj->init.fifo | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe); + p_obj->p_instance->IFLS = ((p_obj->init.rx_int.level << 3) | p_obj->init.tx_int.level); + p_obj->p_instance->IMSC = (p_obj->init.interr | p_obj->init.tx_int.inttx | p_obj->init.rx_int.intrx); + p_obj->p_instance->CR = (p_obj->init.ctse | p_obj->init.rtse | FUARTxCR_UARTEN_ENABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the FUART object. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_deinit(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable FUART */ + /*------------------------------*/ + p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | + FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); + /*------------------------------*/ + /* Interrupt Disable */ + /*------------------------------*/ + p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | + FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | + FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | + FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | + FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); + /*------------------------------*/ + /* FIFO Disable */ + /*------------------------------*/ + p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_discard_transmit(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + disable_FUARTxCR_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = FUARTxICR_TXIC_CLR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_discard_receive(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + disable_FUARTxCR_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = FUARTxICR_RXIC_CLR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :FUART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); + assert_param(check_param_tx_buff_num(p_info->num)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + p_obj->transmit.info.p_data = p_info->p_data; + p_obj->transmit.info.num = p_info->num; + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + volatile uint32_t fr_reg; + + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- FUARTxDR ---*/ + if (p_obj->transmit.info.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_FUARTxCR_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :FUART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref FUART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + volatile uint8_t dummy; + volatile uint32_t fr_reg; + uint32_t rx_count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); + assert_param(check_param_rx_buff_num(p_info->num)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_RXE(p_obj->p_instance); + /* FIFO CLR */ + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) { + dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + if (p_obj->init.fifo == 1) { + if (++rx_count > FUART_RX_FIFO_MAX) { + break; + } + } else { + if (++rx_count > 1) { + break; + } + } + fr_reg = p_obj->p_instance->FR; + } + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->receive.wp = 0; + p_obj->receive.info.p_data = p_info->p_data; + p_obj->receive.info.num = p_info->num; + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_FUARTxCR_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_transmit_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + volatile uint32_t fr_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_TXE_MASK) == FUARTxCR_TXE_ENABLE) { + if (p_obj->transmit.info.num <= p_obj->transmit.rp) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + /* disable_FUARTxCR_TXE(p_obj->p_instance); */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != FUART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- FUARTxDR ---*/ + if (p_obj->transmit.info.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_receive_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + volatile uint32_t fr_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) { + uint32_t rx_count = 0; + + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) { + *(p_obj->receive.info.p_data + p_obj->receive.wp) = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + p_obj->receive.wp += 1; + if (p_obj->receive.wp >= p_obj->receive.info.num) { + break; + } + if (p_obj->init.fifo == 1) { + if (++rx_count >= FUART_RX_FIFO_MAX) { + break; + } + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.wp >= p_obj->receive.info.num) { + if (p_obj->receive.handler != FUART_NULL) { + fuart_receive_t param; + param.p_data = p_obj->receive.info.p_data; + param.num = p_obj->receive.wp; + p_obj->receive.wp = 0; + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_error_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + uint32_t error; + uint32_t ecr_reg = 0x00; + uint32_t icr_reg = 0x00; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current FUARTxRSR. */ + error = p_obj->p_instance->RSR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- FUARTxRSR ---*/ + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVER RUN */ + if ((error & FUARTxRSR_OE_MASK) == FUARTxRSR_OE_ERR) { + volatile uint8_t dummy; + + icr_reg |= FUARTxICR_OEIC_CLR; + ecr_reg |= FUARTxECR_OE_CLR; + dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + err = TXZ_ERROR; + } + /* BREAK */ + if ((error & FUARTxRSR_BE_MASK) == FUARTxRSR_BE_ERR) { + icr_reg |= FUARTxICR_BEIC_CLR; + ecr_reg |= FUARTxECR_BE_CLR; + err = TXZ_ERROR; + } + /* PARITY */ + if ((error & FUARTxRSR_PE_MASK) == FUARTxRSR_PE_ERR) { + icr_reg |= FUARTxICR_PEIC_CLR; + ecr_reg |= FUARTxECR_PE_CLR; + err = TXZ_ERROR; + } + /* FRAMING */ + if ((error & FUARTxRSR_FE_MASK) == FUARTxRSR_FE_ERR) { + icr_reg |= FUARTxICR_FEIC_CLR; + ecr_reg |= FUARTxECR_FE_CLR; + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + p_obj->p_instance->ICR = icr_reg; + p_obj->p_instance->ECR = ecr_reg; + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != FUART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for timeout error. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_timeout_error_irq_handler(fuart_t *p_obj) +{ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != FUART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler . + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_irq_handler(fuart_t *p_obj) +{ + uint32_t interrupt_status = p_obj->p_instance->MIS; + if ((interrupt_status & FUARTxMIS_RXMIS_MASK) == FUARTxMIS_RXMIS_REQ) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RXMIS_MASK; + fuart_receive_irq_handler(p_obj); + } + if ((interrupt_status & FUARTxMIS_TXMIS_MASK) == FUARTxMIS_TXMIS_REQ) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_TXMIS_MASK; + fuart_transmit_irq_handler(p_obj); + } + if ((interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK)) != 0) { + p_obj->p_instance->ICR = interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK); + fuart_error_irq_handler(p_obj); + } + if ((interrupt_status & FUARTxMIS_RTMIS_MASK) != 0) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RTMIS_MASK; + fuart_timeout_error_irq_handler(p_obj); + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | 31-8 | - | - | + * | 7 | TXFE | Transmit FIFO Empty Flag. | + * | 6 | RXFF | Reach Receive Fill Level Flag. | + * | 5 | TXFF | Reach Transmit Fill Level Flag. | | + * | 4 | RXFE | Receive FIFO Empty Flag. | + * | 3 | BUSY | Transmit BUSY Flag. | + * | 2-1 | - | - | + * | 0 | CTS | FUTxCTS Flag. | + * + * @param p_obj :FUART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- FUARTxFR ---*/ + /* Read current FUARTxFR. */ + *p_status = p_obj->p_instance->FR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | OVRERR | Overrun Error. Use @ref FUART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref FUART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref FUART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref FUART_BreakErr. | + * + * @param p_obj :FUART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- FUARTxRSR ---*/ + /* Read current FUARTxRSR. */ + *p_error = p_obj->p_instance->RSR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of FUARTxCLK. */ +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi T0 ---*/ + tx = (uint64_t)((uint64_t)clock << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); + + /*--- N+(K/64) division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = FUART_RANGE_K_MIN; (k <= FUART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx - (uint64_t)k; + work >>= FUART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((FUART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= FUART_RANGE_N_MAX)) { + uint64_t workRange = 0; + /* Verification */ + if (verification_boudrate64(clock, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (FUART_CFG_GET_BOUDRATE_TYPE == FUART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } +#endif /* (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart_ex.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart_ex.c new file mode 100644 index 0000000..22d0cec --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_fuart_ex.c @@ -0,0 +1,218 @@ +/** + ******************************************************************************* + * @file txz_fuart_ex.c + * @brief This file provides API functions for FUART driver. + * @brief Extended functionality. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_fuart_include.h" +#include "txz_fuart_ex.h" + +#if defined(__FUART_EX_H) + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_fuctions + * @{ + */ + +/** + * @} + */ /* End of group FUART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Send Break. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_send_break(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Set Break */ + /*------------------------------*/ + { + uint32_t trans = p_obj->p_instance->LCR_H; + + trans &= ~FUARTxLCR_H_BRK_MASK; + trans |= FUARTxLCR_H_BRK_SEND; + p_obj->p_instance->LCR_H = trans; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Stop Break. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_stop_break(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Set Break */ + /*------------------------------*/ + { + uint32_t trans = p_obj->p_instance->LCR_H; + + trans &= ~FUARTxLCR_H_BRK_MASK; + trans |= FUARTxLCR_H_BRK_STOP; + p_obj->p_instance->LCR_H = trans; + } + + return (result); +} + + +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_EX_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_gpio.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_gpio.c new file mode 100644 index 0000000..74907e1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_gpio.c @@ -0,0 +1,1831 @@ +/** + ******************************************************************************* + * @file txz_gpio.c + * @brief This file provides API functions for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_gpio.h" + +#if defined(__GPIO_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup GPIO + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name Bit Operation Macro + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */ +#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */ +#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (uint32_t)(gr)) ) /*!< Operational target Port Adress */ +#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */ +#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) /*!< Target Pin Bit set */ +#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) /*!< Target Pin Bit clear */ +#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) /*!< Target Pin Bit read */ +/** + * @} + */ /* End of Bit Operation Macro */ +/** + * @} + */ /* End of group GPIO_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group GPIO_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group GPIO_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_fuctions GPIO Private Fuctions + * @{ + */ + +static uint8_t change_mode_to_num(uint32_t mode); +static uint8_t change_func_to_num(uint32_t func); +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func); + +static uint8_t change_mode_to_num(uint32_t mode) +{ + uint8_t retVal = 0; + + if (mode == GPIO_Mode_DATA) { + retVal = GPIO_ModeNum_DATA; + } else if (mode == GPIO_Mode_CR) { + retVal = GPIO_ModeNum_CR; + } else if (mode == GPIO_Mode_FR1) { + retVal = GPIO_ModeNum_FR1; + } else if (mode == GPIO_Mode_FR2) { + retVal = GPIO_ModeNum_FR2; + } else if (mode == GPIO_Mode_FR3) { + retVal = GPIO_ModeNum_FR3; + } else if (mode == GPIO_Mode_FR4) { + retVal = GPIO_ModeNum_FR4; + } else if (mode == GPIO_Mode_FR5) { + retVal = GPIO_ModeNum_FR5; + } else if (mode == GPIO_Mode_FR6) { + retVal = GPIO_ModeNum_FR6; + } else if (mode == GPIO_Mode_FR7) { + retVal = GPIO_ModeNum_FR7; + } else if (mode == GPIO_Mode_FR8) { + retVal = GPIO_ModeNum_FR8; + } else if (mode == GPIO_Mode_OD) { + retVal = GPIO_ModeNum_OD; + } else if (mode == GPIO_Mode_PUP) { + retVal = GPIO_ModeNum_PUP; + } else if (mode == GPIO_Mode_PDN) { + retVal = GPIO_ModeNum_PDN; + } else if (mode == GPIO_Mode_IE) { + retVal = GPIO_ModeNum_IE; + } else { + retVal = GPIO_ModeNum_Max; + } + + return retVal; +} + +static uint8_t change_func_to_num(uint32_t func) +{ + uint8_t retVal = 0; + + if (func == GPIO_FR_1) { + retVal = GPIO_ModeNum_FR1; + } else if (func == GPIO_FR_2) { + retVal = GPIO_ModeNum_FR2; + } else if (func == GPIO_FR_3) { + retVal = GPIO_ModeNum_FR3; + } else if (func == GPIO_FR_4) { + retVal = GPIO_ModeNum_FR4; + } else if (func == GPIO_FR_5) { + retVal = GPIO_ModeNum_FR5; + } else if (func == GPIO_FR_6) { + retVal = GPIO_ModeNum_FR6; + } else if (func == GPIO_FR_7) { + retVal = GPIO_ModeNum_FR7; + } else if (func == GPIO_FR_8) { + retVal = GPIO_ModeNum_FR8; + } else if (func == GPIO_FR_NA) { + retVal = GPIO_ModeNum_CR; + } else if (func == 0) { + retVal = GPIO_ModeNum_CR; + } else { + retVal = GPIO_ModeNum_Max; + } + + return retVal; +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) + * @brief Check the Pin Exist. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + */ +/*--------------------------------------------------*/ +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) +{ + int32_t result = PARAM_NG; + uint8_t chgmode; + uint16_t tmp; + + chgmode = change_mode_to_num(mode); + if ((chgmode < GPIO_ModeNum_Max) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgmode) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func) +{ + int32_t result = PARAM_NG; + uint8_t chgfunc; + uint16_t tmp; + + chgfunc = change_func_to_num(func); + /* param check skip if func is INPUT or OUTPUT */ + if (chgfunc == GPIO_ModeNum_CR) { + return (PARAM_OK); + } + if ((chgfunc < GPIO_ModeNum_Max) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +/** + * @} + */ /* End of group GPIO_Private_functions */ + + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) + * @brief Initialize the GPIO object. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; + + /* Check the NULL of address. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + /* PA Clock Enable */ + PORT_CLOCK_ENABLE_PORTA(TSB_CG_FSYSMENB_IPMENB02); + INIT_GPIO_PORT_A_DATA(p_obj->p_pa_instance->DATA); + INIT_GPIO_PORT_A_CR(p_obj->p_pa_instance->CR); + INIT_GPIO_PORT_A_FR1(p_obj->p_pa_instance->FR1); + INIT_GPIO_PORT_A_FR2(p_obj->p_pa_instance->FR2); + INIT_GPIO_PORT_A_FR3(p_obj->p_pa_instance->FR3); + INIT_GPIO_PORT_A_FR4(p_obj->p_pa_instance->FR4); + INIT_GPIO_PORT_A_FR5(p_obj->p_pa_instance->FR5); + INIT_GPIO_PORT_A_FR6(p_obj->p_pa_instance->FR6); + INIT_GPIO_PORT_A_FR7(p_obj->p_pa_instance->FR7); + INIT_GPIO_PORT_A_FR8(p_obj->p_pa_instance->FR8); + INIT_GPIO_PORT_A_OD(p_obj->p_pa_instance->OD); + INIT_GPIO_PORT_A_PUP(p_obj->p_pa_instance->PUP); + INIT_GPIO_PORT_A_PDN(p_obj->p_pa_instance->PDN); + INIT_GPIO_PORT_A_IE(p_obj->p_pa_instance->IE); + break; + case GPIO_PORT_B: + /* PB Clock Enable */ + PORT_CLOCK_ENABLE_PORTB(TSB_CG_FSYSMENB_IPMENB03); + INIT_GPIO_PORT_B_DATA(p_obj->p_pb_instance->DATA); + INIT_GPIO_PORT_B_CR(p_obj->p_pb_instance->CR); + INIT_GPIO_PORT_B_FR1(p_obj->p_pb_instance->FR1); + INIT_GPIO_PORT_B_FR2(p_obj->p_pb_instance->FR2); + INIT_GPIO_PORT_B_FR3(p_obj->p_pb_instance->FR3); + INIT_GPIO_PORT_B_FR4(p_obj->p_pb_instance->FR4); + INIT_GPIO_PORT_B_FR5(p_obj->p_pb_instance->FR5); + INIT_GPIO_PORT_B_FR6(p_obj->p_pb_instance->FR6); + INIT_GPIO_PORT_B_FR7(p_obj->p_pb_instance->FR7); + INIT_GPIO_PORT_B_FR8(p_obj->p_pb_instance->FR8); + INIT_GPIO_PORT_B_OD(p_obj->p_pb_instance->OD); + INIT_GPIO_PORT_B_PUP(p_obj->p_pb_instance->PUP); + INIT_GPIO_PORT_B_PDN(p_obj->p_pb_instance->PDN); + INIT_GPIO_PORT_B_IE(p_obj->p_pb_instance->IE); + break; + case GPIO_PORT_C: + /* PC Clock Enable */ + PORT_CLOCK_ENABLE_PORTC(TSB_CG_FSYSMENB_IPMENB04); + INIT_GPIO_PORT_C_DATA(p_obj->p_pc_instance->DATA); + INIT_GPIO_PORT_C_CR(p_obj->p_pc_instance->CR); + INIT_GPIO_PORT_C_FR1(p_obj->p_pc_instance->FR1); + INIT_GPIO_PORT_C_FR2(p_obj->p_pc_instance->FR2); + INIT_GPIO_PORT_C_FR3(p_obj->p_pc_instance->FR3); + INIT_GPIO_PORT_C_FR4(p_obj->p_pc_instance->FR4); + INIT_GPIO_PORT_C_FR5(p_obj->p_pc_instance->FR5); + INIT_GPIO_PORT_C_FR6(p_obj->p_pc_instance->FR6); + INIT_GPIO_PORT_C_FR7(p_obj->p_pc_instance->FR7); + INIT_GPIO_PORT_C_FR8(p_obj->p_pc_instance->FR8); + INIT_GPIO_PORT_C_OD(p_obj->p_pc_instance->OD); + INIT_GPIO_PORT_C_PUP(p_obj->p_pc_instance->PUP); + INIT_GPIO_PORT_C_PDN(p_obj->p_pc_instance->PDN); + INIT_GPIO_PORT_C_IE(p_obj->p_pc_instance->IE); + break; + case GPIO_PORT_D: + /* PD Clock Enable */ + PORT_CLOCK_ENABLE_PORTD(TSB_CG_FSYSMENB_IPMENB05); + INIT_GPIO_PORT_D_DATA(p_obj->p_pd_instance->DATA); + INIT_GPIO_PORT_D_CR(p_obj->p_pd_instance->CR); + INIT_GPIO_PORT_D_FR1(p_obj->p_pd_instance->FR1); + INIT_GPIO_PORT_D_FR2(p_obj->p_pd_instance->FR2); + INIT_GPIO_PORT_D_FR3(p_obj->p_pd_instance->FR3); + INIT_GPIO_PORT_D_FR4(p_obj->p_pd_instance->FR4); + INIT_GPIO_PORT_D_FR5(p_obj->p_pd_instance->FR5); + INIT_GPIO_PORT_D_FR6(p_obj->p_pd_instance->FR6); + INIT_GPIO_PORT_D_FR7(p_obj->p_pd_instance->FR7); + INIT_GPIO_PORT_D_FR8(p_obj->p_pd_instance->FR8); + INIT_GPIO_PORT_D_OD(p_obj->p_pd_instance->OD); + INIT_GPIO_PORT_D_PUP(p_obj->p_pd_instance->PUP); + INIT_GPIO_PORT_D_PDN(p_obj->p_pd_instance->PDN); + INIT_GPIO_PORT_D_IE(p_obj->p_pd_instance->IE); + break; + case GPIO_PORT_E: + /* PE Clock Enable */ + PORT_CLOCK_ENABLE_PORTE(TSB_CG_FSYSMENB_IPMENB06); + INIT_GPIO_PORT_E_DATA(p_obj->p_pe_instance->DATA); + INIT_GPIO_PORT_E_CR(p_obj->p_pe_instance->CR); + INIT_GPIO_PORT_E_FR1(p_obj->p_pe_instance->FR1); + INIT_GPIO_PORT_E_FR2(p_obj->p_pe_instance->FR2); + INIT_GPIO_PORT_E_FR3(p_obj->p_pe_instance->FR3); + INIT_GPIO_PORT_E_FR4(p_obj->p_pe_instance->FR4); + INIT_GPIO_PORT_E_FR5(p_obj->p_pe_instance->FR5); + INIT_GPIO_PORT_E_FR6(p_obj->p_pe_instance->FR6); + INIT_GPIO_PORT_E_FR7(p_obj->p_pe_instance->FR7); + INIT_GPIO_PORT_E_FR8(p_obj->p_pe_instance->FR8); + INIT_GPIO_PORT_E_OD(p_obj->p_pe_instance->OD); + INIT_GPIO_PORT_E_PUP(p_obj->p_pe_instance->PUP); + INIT_GPIO_PORT_E_PDN(p_obj->p_pe_instance->PDN); + INIT_GPIO_PORT_E_IE(p_obj->p_pe_instance->IE); + break; + case GPIO_PORT_F: + /* PF Clock Enable */ + PORT_CLOCK_ENABLE_PORTF(TSB_CG_FSYSMENB_IPMENB07); + INIT_GPIO_PORT_F_DATA(p_obj->p_pf_instance->DATA); + INIT_GPIO_PORT_F_CR(p_obj->p_pf_instance->CR); + INIT_GPIO_PORT_F_FR1(p_obj->p_pf_instance->FR1); + INIT_GPIO_PORT_F_FR2(p_obj->p_pf_instance->FR2); + INIT_GPIO_PORT_F_FR3(p_obj->p_pf_instance->FR3); + INIT_GPIO_PORT_F_FR4(p_obj->p_pf_instance->FR4); + INIT_GPIO_PORT_F_FR5(p_obj->p_pf_instance->FR5); + INIT_GPIO_PORT_F_FR6(p_obj->p_pf_instance->FR6); + INIT_GPIO_PORT_F_FR7(p_obj->p_pf_instance->FR7); + INIT_GPIO_PORT_F_FR8(p_obj->p_pf_instance->FR8); + INIT_GPIO_PORT_F_OD(p_obj->p_pf_instance->OD); + INIT_GPIO_PORT_F_PUP(p_obj->p_pf_instance->PUP); + INIT_GPIO_PORT_F_PDN(p_obj->p_pf_instance->PDN); + INIT_GPIO_PORT_F_IE(p_obj->p_pf_instance->IE); + break; + case GPIO_PORT_G: + /* PG Clock Enable */ + PORT_CLOCK_ENABLE_PORTG(TSB_CG_FSYSMENB_IPMENB08); + INIT_GPIO_PORT_G_DATA(p_obj->p_pg_instance->DATA); + INIT_GPIO_PORT_G_CR(p_obj->p_pg_instance->CR); + INIT_GPIO_PORT_G_FR1(p_obj->p_pg_instance->FR1); + INIT_GPIO_PORT_G_FR2(p_obj->p_pg_instance->FR2); + INIT_GPIO_PORT_G_FR3(p_obj->p_pg_instance->FR3); + INIT_GPIO_PORT_G_FR4(p_obj->p_pg_instance->FR4); + INIT_GPIO_PORT_G_FR6(p_obj->p_pg_instance->FR6); + INIT_GPIO_PORT_G_FR5(p_obj->p_pg_instance->FR5); + INIT_GPIO_PORT_G_FR7(p_obj->p_pg_instance->FR7); + INIT_GPIO_PORT_G_FR8(p_obj->p_pg_instance->FR8); + INIT_GPIO_PORT_G_OD(p_obj->p_pg_instance->OD); + INIT_GPIO_PORT_G_PUP(p_obj->p_pg_instance->PUP); + INIT_GPIO_PORT_G_PDN(p_obj->p_pg_instance->PDN); + INIT_GPIO_PORT_G_IE(p_obj->p_pg_instance->IE); + break; + case GPIO_PORT_H: + /* PH Clock Enable */ + PORT_CLOCK_ENABLE_PORTH(TSB_CG_FSYSMENB_IPMENB09); + INIT_GPIO_PORT_H_DATA(p_obj->p_ph_instance->DATA); + INIT_GPIO_PORT_H_CR(p_obj->p_ph_instance->CR); + INIT_GPIO_PORT_H_FR1(p_obj->p_ph_instance->FR1); + INIT_GPIO_PORT_H_FR2(p_obj->p_ph_instance->FR2); + INIT_GPIO_PORT_H_FR3(p_obj->p_ph_instance->FR3); + INIT_GPIO_PORT_H_FR4(p_obj->p_ph_instance->FR4); + INIT_GPIO_PORT_H_FR5(p_obj->p_ph_instance->FR5); + INIT_GPIO_PORT_H_FR6(p_obj->p_ph_instance->FR6); + INIT_GPIO_PORT_H_FR7(p_obj->p_ph_instance->FR7); + INIT_GPIO_PORT_H_FR8(p_obj->p_ph_instance->FR8); + INIT_GPIO_PORT_H_OD(p_obj->p_ph_instance->OD); + INIT_GPIO_PORT_H_PUP(p_obj->p_ph_instance->PUP); + INIT_GPIO_PORT_H_PDN(p_obj->p_ph_instance->PDN); + INIT_GPIO_PORT_H_IE(p_obj->p_ph_instance->IE); + break; + case GPIO_PORT_J: + /* PJ Clock Enable */ + PORT_CLOCK_ENABLE_PORTJ(TSB_CG_FSYSMENB_IPMENB10); + INIT_GPIO_PORT_J_DATA(p_obj->p_pj_instance->DATA); + INIT_GPIO_PORT_J_CR(p_obj->p_pj_instance->CR); + INIT_GPIO_PORT_J_FR1(p_obj->p_pj_instance->FR1); + INIT_GPIO_PORT_J_FR2(p_obj->p_pj_instance->FR2); + INIT_GPIO_PORT_J_FR3(p_obj->p_pj_instance->FR3); + INIT_GPIO_PORT_J_FR4(p_obj->p_pj_instance->FR4); + INIT_GPIO_PORT_J_FR5(p_obj->p_pj_instance->FR5); + INIT_GPIO_PORT_J_FR6(p_obj->p_pj_instance->FR6); + INIT_GPIO_PORT_J_FR7(p_obj->p_pj_instance->FR7); + INIT_GPIO_PORT_J_FR8(p_obj->p_pj_instance->FR8); + INIT_GPIO_PORT_J_OD(p_obj->p_pj_instance->OD); + INIT_GPIO_PORT_J_PUP(p_obj->p_pj_instance->PUP); + INIT_GPIO_PORT_J_PDN(p_obj->p_pj_instance->PDN); + INIT_GPIO_PORT_J_IE(p_obj->p_pj_instance->IE); + break; + case GPIO_PORT_K: + /* PK Clock Enable */ + PORT_CLOCK_ENABLE_PORTK(TSB_CG_FSYSMENB_IPMENB11); + INIT_GPIO_PORT_K_DATA(p_obj->p_pk_instance->DATA); + INIT_GPIO_PORT_K_CR(p_obj->p_pk_instance->CR); + INIT_GPIO_PORT_K_FR1(p_obj->p_pk_instance->FR1); + INIT_GPIO_PORT_K_FR2(p_obj->p_pk_instance->FR2); + INIT_GPIO_PORT_K_FR3(p_obj->p_pk_instance->FR3); + INIT_GPIO_PORT_K_FR4(p_obj->p_pk_instance->FR4); + INIT_GPIO_PORT_K_FR5(p_obj->p_pk_instance->FR5); + INIT_GPIO_PORT_K_FR6(p_obj->p_pk_instance->FR6); + INIT_GPIO_PORT_K_FR7(p_obj->p_pk_instance->FR7); + INIT_GPIO_PORT_K_FR8(p_obj->p_pk_instance->FR8); + INIT_GPIO_PORT_K_OD(p_obj->p_pk_instance->OD); + INIT_GPIO_PORT_K_PUP(p_obj->p_pk_instance->PUP); + INIT_GPIO_PORT_K_PDN(p_obj->p_pk_instance->PDN); + INIT_GPIO_PORT_K_IE(p_obj->p_pk_instance->IE); + break; + case GPIO_PORT_L: + /* PL Clock Enable */ + PORT_CLOCK_ENABLE_PORTL(TSB_CG_FSYSMENB_IPMENB12); + INIT_GPIO_PORT_L_DATA(p_obj->p_pl_instance->DATA); + INIT_GPIO_PORT_L_CR(p_obj->p_pl_instance->CR); + INIT_GPIO_PORT_L_FR1(p_obj->p_pl_instance->FR1); + INIT_GPIO_PORT_L_FR2(p_obj->p_pl_instance->FR2); + INIT_GPIO_PORT_L_FR3(p_obj->p_pl_instance->FR3); + INIT_GPIO_PORT_L_FR4(p_obj->p_pl_instance->FR4); + INIT_GPIO_PORT_L_FR5(p_obj->p_pl_instance->FR5); + INIT_GPIO_PORT_L_FR6(p_obj->p_pl_instance->FR6); + INIT_GPIO_PORT_L_FR7(p_obj->p_pl_instance->FR7); + INIT_GPIO_PORT_L_FR8(p_obj->p_pl_instance->FR8); + INIT_GPIO_PORT_L_OD(p_obj->p_pl_instance->OD); + INIT_GPIO_PORT_L_PUP(p_obj->p_pl_instance->PUP); + INIT_GPIO_PORT_L_PDN(p_obj->p_pl_instance->PDN); + INIT_GPIO_PORT_L_IE(p_obj->p_pl_instance->IE); + break; + case GPIO_PORT_M: + /* PM Clock Enable */ + PORT_CLOCK_ENABLE_PORTM(TSB_CG_FSYSMENB_IPMENB13); + INIT_GPIO_PORT_M_DATA(p_obj->p_pm_instance->DATA); + INIT_GPIO_PORT_M_CR(p_obj->p_pm_instance->CR); + INIT_GPIO_PORT_M_FR1(p_obj->p_pm_instance->FR1); + INIT_GPIO_PORT_M_FR2(p_obj->p_pm_instance->FR2); + INIT_GPIO_PORT_M_FR3(p_obj->p_pm_instance->FR3); + INIT_GPIO_PORT_M_FR4(p_obj->p_pm_instance->FR4); + INIT_GPIO_PORT_M_FR5(p_obj->p_pm_instance->FR5); + INIT_GPIO_PORT_M_FR6(p_obj->p_pm_instance->FR6); + INIT_GPIO_PORT_M_FR7(p_obj->p_pm_instance->FR7); + INIT_GPIO_PORT_M_FR8(p_obj->p_pm_instance->FR8); + INIT_GPIO_PORT_M_OD(p_obj->p_pm_instance->OD); + INIT_GPIO_PORT_M_PUP(p_obj->p_pm_instance->PUP); + INIT_GPIO_PORT_M_PDN(p_obj->p_pm_instance->PDN); + INIT_GPIO_PORT_M_IE(p_obj->p_pm_instance->IE); + break; + case GPIO_PORT_N: + /* PN Clock Enable */ + PORT_CLOCK_ENABLE_PORTN(TSB_CG_FSYSMENB_IPMENB14); + INIT_GPIO_PORT_N_DATA(p_obj->p_pn_instance->DATA); + INIT_GPIO_PORT_N_CR(p_obj->p_pn_instance->CR); + INIT_GPIO_PORT_N_FR1(p_obj->p_pn_instance->FR1); + INIT_GPIO_PORT_N_FR2(p_obj->p_pn_instance->FR2); + INIT_GPIO_PORT_N_FR3(p_obj->p_pn_instance->FR3); + INIT_GPIO_PORT_N_FR4(p_obj->p_pn_instance->FR4); + INIT_GPIO_PORT_N_FR5(p_obj->p_pn_instance->FR5); + INIT_GPIO_PORT_N_FR6(p_obj->p_pn_instance->FR6); + INIT_GPIO_PORT_N_FR7(p_obj->p_pn_instance->FR7); + INIT_GPIO_PORT_N_FR8(p_obj->p_pn_instance->FR8); + INIT_GPIO_PORT_N_OD(p_obj->p_pn_instance->OD); + INIT_GPIO_PORT_N_PUP(p_obj->p_pn_instance->PUP); + INIT_GPIO_PORT_N_PDN(p_obj->p_pn_instance->PDN); + INIT_GPIO_PORT_N_IE(p_obj->p_pn_instance->IE); + break; + case GPIO_PORT_P: + /* PP Clock Enable */ + PORT_CLOCK_ENABLE_PORTP(TSB_CG_FSYSMENB_IPMENB15); + INIT_GPIO_PORT_P_DATA(p_obj->p_pp_instance->DATA); + INIT_GPIO_PORT_P_CR(p_obj->p_pp_instance->CR); + INIT_GPIO_PORT_P_FR1(p_obj->p_pp_instance->FR1); + INIT_GPIO_PORT_P_FR2(p_obj->p_pp_instance->FR2); + INIT_GPIO_PORT_P_FR3(p_obj->p_pp_instance->FR3); + INIT_GPIO_PORT_P_FR4(p_obj->p_pp_instance->FR4); + INIT_GPIO_PORT_P_FR5(p_obj->p_pp_instance->FR5); + INIT_GPIO_PORT_P_FR6(p_obj->p_pp_instance->FR6); + INIT_GPIO_PORT_P_FR7(p_obj->p_pp_instance->FR7); + INIT_GPIO_PORT_P_FR8(p_obj->p_pp_instance->FR8); + INIT_GPIO_PORT_P_OD(p_obj->p_pp_instance->OD); + INIT_GPIO_PORT_P_PUP(p_obj->p_pp_instance->PUP); + INIT_GPIO_PORT_P_PDN(p_obj->p_pp_instance->PDN); + INIT_GPIO_PORT_P_IE(p_obj->p_pp_instance->IE); + break; + case GPIO_PORT_R: + /* PR Clock Enable */ + PORT_CLOCK_ENABLE_PORTR(TSB_CG_FSYSMENB_IPMENB16); + INIT_GPIO_PORT_R_DATA(p_obj->p_pr_instance->DATA); + INIT_GPIO_PORT_R_CR(p_obj->p_pr_instance->CR); + INIT_GPIO_PORT_R_FR1(p_obj->p_pr_instance->FR1); + INIT_GPIO_PORT_R_FR2(p_obj->p_pr_instance->FR2); + INIT_GPIO_PORT_R_FR3(p_obj->p_pr_instance->FR3); + INIT_GPIO_PORT_R_FR4(p_obj->p_pr_instance->FR4); + INIT_GPIO_PORT_R_FR5(p_obj->p_pr_instance->FR5); + INIT_GPIO_PORT_R_FR6(p_obj->p_pr_instance->FR6); + INIT_GPIO_PORT_R_FR7(p_obj->p_pr_instance->FR7); + INIT_GPIO_PORT_R_FR8(p_obj->p_pr_instance->FR8); + INIT_GPIO_PORT_R_OD(p_obj->p_pr_instance->OD); + INIT_GPIO_PORT_R_PUP(p_obj->p_pr_instance->PUP); + INIT_GPIO_PORT_R_PDN(p_obj->p_pr_instance->PDN); + INIT_GPIO_PORT_R_IE(p_obj->p_pr_instance->IE); + break; + case GPIO_PORT_T: + /* PT Clock Enable */ + PORT_CLOCK_ENABLE_PORTT(TSB_CG_FSYSMENB_IPMENB17); + INIT_GPIO_PORT_T_DATA(p_obj->p_pt_instance->DATA); + INIT_GPIO_PORT_T_CR(p_obj->p_pt_instance->CR); + INIT_GPIO_PORT_T_FR1(p_obj->p_pt_instance->FR1); + INIT_GPIO_PORT_T_FR2(p_obj->p_pt_instance->FR2); + INIT_GPIO_PORT_T_FR3(p_obj->p_pt_instance->FR3); + INIT_GPIO_PORT_T_FR4(p_obj->p_pt_instance->FR4); + INIT_GPIO_PORT_T_FR5(p_obj->p_pt_instance->FR5); + INIT_GPIO_PORT_T_FR6(p_obj->p_pt_instance->FR6); + INIT_GPIO_PORT_T_FR7(p_obj->p_pt_instance->FR7); + INIT_GPIO_PORT_T_FR8(p_obj->p_pt_instance->FR8); + INIT_GPIO_PORT_T_OD(p_obj->p_pt_instance->OD); + INIT_GPIO_PORT_T_PUP(p_obj->p_pt_instance->PUP); + INIT_GPIO_PORT_T_PDN(p_obj->p_pt_instance->PDN); + INIT_GPIO_PORT_T_IE(p_obj->p_pt_instance->IE); + break; + case GPIO_PORT_U: + /* PU Clock Enable */ + PORT_CLOCK_ENABLE_PORTU(TSB_CG_FSYSMENB_IPMENB18); + INIT_GPIO_PORT_U_DATA(p_obj->p_pu_instance->DATA); + INIT_GPIO_PORT_U_CR(p_obj->p_pu_instance->CR); + INIT_GPIO_PORT_U_FR1(p_obj->p_pu_instance->FR1); + INIT_GPIO_PORT_U_FR2(p_obj->p_pu_instance->FR2); + INIT_GPIO_PORT_U_FR3(p_obj->p_pu_instance->FR3); + INIT_GPIO_PORT_U_FR4(p_obj->p_pu_instance->FR4); + INIT_GPIO_PORT_U_FR5(p_obj->p_pu_instance->FR5); + INIT_GPIO_PORT_U_FR6(p_obj->p_pu_instance->FR6); + INIT_GPIO_PORT_U_FR7(p_obj->p_pu_instance->FR7); + INIT_GPIO_PORT_U_FR8(p_obj->p_pu_instance->FR8); + INIT_GPIO_PORT_U_OD(p_obj->p_pu_instance->OD); + INIT_GPIO_PORT_U_PUP(p_obj->p_pu_instance->PUP); + INIT_GPIO_PORT_U_PDN(p_obj->p_pu_instance->PDN); + INIT_GPIO_PORT_U_IE(p_obj->p_pu_instance->IE); + break; + case GPIO_PORT_V: + /* PV Clock Enable */ + PORT_CLOCK_ENABLE_PORTV(TSB_CG_FSYSMENB_IPMENB19); + INIT_GPIO_PORT_V_DATA(p_obj->p_pv_instance->DATA); + INIT_GPIO_PORT_V_CR(p_obj->p_pv_instance->CR); + INIT_GPIO_PORT_V_FR1(p_obj->p_pv_instance->FR1); + INIT_GPIO_PORT_V_FR2(p_obj->p_pv_instance->FR2); + INIT_GPIO_PORT_V_FR3(p_obj->p_pv_instance->FR3); + INIT_GPIO_PORT_V_FR4(p_obj->p_pv_instance->FR4); + INIT_GPIO_PORT_V_FR5(p_obj->p_pv_instance->FR5); + INIT_GPIO_PORT_V_FR6(p_obj->p_pv_instance->FR6); + INIT_GPIO_PORT_V_FR7(p_obj->p_pv_instance->FR7); + INIT_GPIO_PORT_V_FR8(p_obj->p_pv_instance->FR8); + INIT_GPIO_PORT_V_OD(p_obj->p_pv_instance->OD); + INIT_GPIO_PORT_V_PUP(p_obj->p_pv_instance->PUP); + INIT_GPIO_PORT_V_PDN(p_obj->p_pv_instance->PDN); + INIT_GPIO_PORT_V_IE(p_obj->p_pv_instance->IE); + break; + case GPIO_PORT_W: + /* PW Clock Enable */ + PORT_CLOCK_ENABLE_PORTW(TSB_CG_FSYSMENB_IPMENB20); + INIT_GPIO_PORT_W_DATA(p_obj->p_pw_instance->DATA); + INIT_GPIO_PORT_W_CR(p_obj->p_pw_instance->CR); + INIT_GPIO_PORT_W_FR1(p_obj->p_pw_instance->FR1); + INIT_GPIO_PORT_W_FR2(p_obj->p_pw_instance->FR2); + INIT_GPIO_PORT_W_FR3(p_obj->p_pw_instance->FR3); + INIT_GPIO_PORT_W_FR4(p_obj->p_pw_instance->FR4); + INIT_GPIO_PORT_W_FR5(p_obj->p_pw_instance->FR5); + INIT_GPIO_PORT_W_FR6(p_obj->p_pw_instance->FR6); + INIT_GPIO_PORT_W_FR7(p_obj->p_pw_instance->FR7); + INIT_GPIO_PORT_W_FR8(p_obj->p_pw_instance->FR8); + INIT_GPIO_PORT_W_OD(p_obj->p_pw_instance->OD); + INIT_GPIO_PORT_W_PUP(p_obj->p_pw_instance->PUP); + INIT_GPIO_PORT_W_PDN(p_obj->p_pw_instance->PDN); + INIT_GPIO_PORT_W_IE(p_obj->p_pw_instance->IE); + break; + case GPIO_PORT_Y: + /* PY Clock Enable */ + PORT_CLOCK_ENABLE_PORTY(TSB_CG_FSYSMENB_IPMENB21); + INIT_GPIO_PORT_Y_DATA(p_obj->p_py_instance->DATA); + INIT_GPIO_PORT_Y_CR(p_obj->p_py_instance->CR); + INIT_GPIO_PORT_Y_FR1(p_obj->p_py_instance->FR1); + INIT_GPIO_PORT_Y_FR2(p_obj->p_py_instance->FR2); + INIT_GPIO_PORT_Y_FR3(p_obj->p_py_instance->FR3); + INIT_GPIO_PORT_Y_FR4(p_obj->p_py_instance->FR4); + INIT_GPIO_PORT_Y_FR5(p_obj->p_py_instance->FR5); + INIT_GPIO_PORT_Y_FR6(p_obj->p_py_instance->FR6); + INIT_GPIO_PORT_Y_FR7(p_obj->p_py_instance->FR7); + INIT_GPIO_PORT_Y_FR8(p_obj->p_py_instance->FR8); + INIT_GPIO_PORT_Y_OD(p_obj->p_py_instance->OD); + INIT_GPIO_PORT_Y_PUP(p_obj->p_py_instance->PUP); + INIT_GPIO_PORT_Y_PDN(p_obj->p_py_instance->PDN); + INIT_GPIO_PORT_Y_IE(p_obj->p_py_instance->IE); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) + * @brief Release the GPIO object. + * @param p_obj :GPIO object. + * @param group :GPIO Port Group.: Use @ref gpio_gr_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; + + /* Check the NULL of address. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + /* Disable the selected GPIO peripheral */ + switch (group) { + case GPIO_PORT_A: + INIT_GPIO_PORT_A_DATA(p_obj->p_pa_instance->DATA); + INIT_GPIO_PORT_A_CR(p_obj->p_pa_instance->CR); + INIT_GPIO_PORT_A_FR1(p_obj->p_pa_instance->FR1); + INIT_GPIO_PORT_A_FR2(p_obj->p_pa_instance->FR2); + INIT_GPIO_PORT_A_FR3(p_obj->p_pa_instance->FR3); + INIT_GPIO_PORT_A_FR4(p_obj->p_pa_instance->FR4); + INIT_GPIO_PORT_A_FR5(p_obj->p_pa_instance->FR5); + INIT_GPIO_PORT_A_FR6(p_obj->p_pa_instance->FR6); + INIT_GPIO_PORT_A_FR7(p_obj->p_pa_instance->FR7); + INIT_GPIO_PORT_A_FR8(p_obj->p_pa_instance->FR8); + INIT_GPIO_PORT_A_OD(p_obj->p_pa_instance->OD); + INIT_GPIO_PORT_A_PUP(p_obj->p_pa_instance->PUP); + INIT_GPIO_PORT_A_PDN(p_obj->p_pa_instance->PDN); + INIT_GPIO_PORT_A_IE(p_obj->p_pa_instance->IE); + /* PA Clock Disable */ + PORT_CLOCK_DISABLE_PORTA(TSB_CG_FSYSMENB_IPMENB02); + break; + case GPIO_PORT_B: + INIT_GPIO_PORT_B_DATA(p_obj->p_pb_instance->DATA); + INIT_GPIO_PORT_B_CR(p_obj->p_pb_instance->CR); + INIT_GPIO_PORT_B_FR1(p_obj->p_pb_instance->FR1); + INIT_GPIO_PORT_B_FR2(p_obj->p_pb_instance->FR2); + INIT_GPIO_PORT_B_FR3(p_obj->p_pb_instance->FR3); + INIT_GPIO_PORT_B_FR4(p_obj->p_pb_instance->FR4); + INIT_GPIO_PORT_B_FR5(p_obj->p_pb_instance->FR5); + INIT_GPIO_PORT_B_FR6(p_obj->p_pb_instance->FR6); + INIT_GPIO_PORT_B_FR7(p_obj->p_pb_instance->FR7); + INIT_GPIO_PORT_B_FR8(p_obj->p_pb_instance->FR8); + INIT_GPIO_PORT_B_OD(p_obj->p_pb_instance->OD); + INIT_GPIO_PORT_B_PUP(p_obj->p_pb_instance->PUP); + INIT_GPIO_PORT_B_PDN(p_obj->p_pb_instance->PDN); + INIT_GPIO_PORT_B_IE(p_obj->p_pb_instance->IE); + /* PB Clock Disable */ + PORT_CLOCK_DISABLE_PORTB(TSB_CG_FSYSMENB_IPMENB03); + break; + case GPIO_PORT_C: + INIT_GPIO_PORT_C_DATA(p_obj->p_pc_instance->DATA); + INIT_GPIO_PORT_C_CR(p_obj->p_pc_instance->CR); + INIT_GPIO_PORT_C_FR1(p_obj->p_pc_instance->FR1); + INIT_GPIO_PORT_C_FR2(p_obj->p_pc_instance->FR2); + INIT_GPIO_PORT_C_FR3(p_obj->p_pc_instance->FR3); + INIT_GPIO_PORT_C_FR4(p_obj->p_pc_instance->FR4); + INIT_GPIO_PORT_C_FR5(p_obj->p_pc_instance->FR5); + INIT_GPIO_PORT_C_FR6(p_obj->p_pc_instance->FR6); + INIT_GPIO_PORT_C_FR7(p_obj->p_pc_instance->FR7); + INIT_GPIO_PORT_C_FR8(p_obj->p_pc_instance->FR8); + INIT_GPIO_PORT_C_OD(p_obj->p_pc_instance->OD); + INIT_GPIO_PORT_C_PUP(p_obj->p_pc_instance->PUP); + INIT_GPIO_PORT_C_PDN(p_obj->p_pc_instance->PDN); + INIT_GPIO_PORT_C_IE(p_obj->p_pc_instance->IE); + /* PC Clock Disable */ + PORT_CLOCK_DISABLE_PORTC(TSB_CG_FSYSMENB_IPMENB04); + break; + case GPIO_PORT_D: + INIT_GPIO_PORT_D_DATA(p_obj->p_pd_instance->DATA); + INIT_GPIO_PORT_D_CR(p_obj->p_pd_instance->CR); + INIT_GPIO_PORT_D_FR1(p_obj->p_pd_instance->FR1); + INIT_GPIO_PORT_D_FR2(p_obj->p_pd_instance->FR2); + INIT_GPIO_PORT_D_FR3(p_obj->p_pd_instance->FR3); + INIT_GPIO_PORT_D_FR4(p_obj->p_pd_instance->FR4); + INIT_GPIO_PORT_D_FR5(p_obj->p_pd_instance->FR5); + INIT_GPIO_PORT_D_FR6(p_obj->p_pd_instance->FR6); + INIT_GPIO_PORT_D_FR7(p_obj->p_pd_instance->FR7); + INIT_GPIO_PORT_D_FR8(p_obj->p_pd_instance->FR8); + INIT_GPIO_PORT_D_OD(p_obj->p_pd_instance->OD); + INIT_GPIO_PORT_D_PUP(p_obj->p_pd_instance->PUP); + INIT_GPIO_PORT_D_PDN(p_obj->p_pd_instance->PDN); + INIT_GPIO_PORT_D_IE(p_obj->p_pd_instance->IE); + /* PD Clock Disable */ + PORT_CLOCK_DISABLE_PORTD(TSB_CG_FSYSMENB_IPMENB05); + break; + case GPIO_PORT_E: + INIT_GPIO_PORT_E_DATA(p_obj->p_pe_instance->DATA); + INIT_GPIO_PORT_E_CR(p_obj->p_pe_instance->CR); + INIT_GPIO_PORT_E_FR1(p_obj->p_pe_instance->FR1); + INIT_GPIO_PORT_E_FR2(p_obj->p_pe_instance->FR2); + INIT_GPIO_PORT_E_FR3(p_obj->p_pe_instance->FR3); + INIT_GPIO_PORT_E_FR4(p_obj->p_pe_instance->FR4); + INIT_GPIO_PORT_E_FR5(p_obj->p_pe_instance->FR5); + INIT_GPIO_PORT_E_FR6(p_obj->p_pe_instance->FR6); + INIT_GPIO_PORT_E_FR7(p_obj->p_pe_instance->FR7); + INIT_GPIO_PORT_E_FR8(p_obj->p_pe_instance->FR8); + INIT_GPIO_PORT_E_OD(p_obj->p_pe_instance->OD); + INIT_GPIO_PORT_E_PUP(p_obj->p_pe_instance->PUP); + INIT_GPIO_PORT_E_PDN(p_obj->p_pe_instance->PDN); + INIT_GPIO_PORT_E_IE(p_obj->p_pe_instance->IE); + /* PE Clock Disable */ + PORT_CLOCK_DISABLE_PORTE(TSB_CG_FSYSMENB_IPMENB06); + break; + case GPIO_PORT_F: + INIT_GPIO_PORT_F_DATA(p_obj->p_pf_instance->DATA); + INIT_GPIO_PORT_F_CR(p_obj->p_pf_instance->CR); + INIT_GPIO_PORT_F_FR1(p_obj->p_pf_instance->FR1); + INIT_GPIO_PORT_F_FR2(p_obj->p_pf_instance->FR2); + INIT_GPIO_PORT_F_FR3(p_obj->p_pf_instance->FR3); + INIT_GPIO_PORT_F_FR4(p_obj->p_pf_instance->FR4); + INIT_GPIO_PORT_F_FR5(p_obj->p_pf_instance->FR5); + INIT_GPIO_PORT_F_FR6(p_obj->p_pf_instance->FR6); + INIT_GPIO_PORT_F_FR7(p_obj->p_pf_instance->FR7); + INIT_GPIO_PORT_F_FR8(p_obj->p_pf_instance->FR8); + INIT_GPIO_PORT_F_OD(p_obj->p_pf_instance->OD); + INIT_GPIO_PORT_F_PUP(p_obj->p_pf_instance->PUP); + INIT_GPIO_PORT_F_PDN(p_obj->p_pf_instance->PDN); + INIT_GPIO_PORT_F_IE(p_obj->p_pf_instance->IE); + /* PF Clock Disable */ + PORT_CLOCK_DISABLE_PORTF(TSB_CG_FSYSMENB_IPMENB07); + break; + case GPIO_PORT_G: + INIT_GPIO_PORT_G_DATA(p_obj->p_pg_instance->DATA); + INIT_GPIO_PORT_G_CR(p_obj->p_pg_instance->CR); + INIT_GPIO_PORT_G_FR1(p_obj->p_pg_instance->FR1); + INIT_GPIO_PORT_G_FR2(p_obj->p_pg_instance->FR2); + INIT_GPIO_PORT_G_FR3(p_obj->p_pg_instance->FR3); + INIT_GPIO_PORT_G_FR4(p_obj->p_pg_instance->FR4); + INIT_GPIO_PORT_G_FR5(p_obj->p_pg_instance->FR5); + INIT_GPIO_PORT_G_FR6(p_obj->p_pg_instance->FR6); + INIT_GPIO_PORT_G_FR7(p_obj->p_pg_instance->FR7); + INIT_GPIO_PORT_G_FR8(p_obj->p_pg_instance->FR8); + INIT_GPIO_PORT_G_OD(p_obj->p_pg_instance->OD); + INIT_GPIO_PORT_G_PUP(p_obj->p_pg_instance->PUP); + INIT_GPIO_PORT_G_PDN(p_obj->p_pg_instance->PDN); + INIT_GPIO_PORT_G_IE(p_obj->p_pg_instance->IE); + /* PG Clock Disable */ + PORT_CLOCK_DISABLE_PORTG(TSB_CG_FSYSMENB_IPMENB08); + break; + case GPIO_PORT_H: + INIT_GPIO_PORT_H_DATA(p_obj->p_ph_instance->DATA); + INIT_GPIO_PORT_H_CR(p_obj->p_ph_instance->CR); + INIT_GPIO_PORT_H_FR1(p_obj->p_ph_instance->FR1); + INIT_GPIO_PORT_H_FR2(p_obj->p_ph_instance->FR2); + INIT_GPIO_PORT_H_FR3(p_obj->p_ph_instance->FR3); + INIT_GPIO_PORT_H_FR4(p_obj->p_ph_instance->FR4); + INIT_GPIO_PORT_H_FR5(p_obj->p_ph_instance->FR5); + INIT_GPIO_PORT_H_FR6(p_obj->p_ph_instance->FR6); + INIT_GPIO_PORT_H_FR7(p_obj->p_ph_instance->FR7); + INIT_GPIO_PORT_H_FR8(p_obj->p_ph_instance->FR8); + INIT_GPIO_PORT_H_OD(p_obj->p_ph_instance->OD); + INIT_GPIO_PORT_H_PUP(p_obj->p_ph_instance->PUP); + INIT_GPIO_PORT_H_PDN(p_obj->p_ph_instance->PDN); + INIT_GPIO_PORT_H_IE(p_obj->p_ph_instance->IE); + /* PH Clock Disable */ + PORT_CLOCK_DISABLE_PORTH(TSB_CG_FSYSMENB_IPMENB09); + break; + case GPIO_PORT_J: + INIT_GPIO_PORT_J_DATA(p_obj->p_pj_instance->DATA); + INIT_GPIO_PORT_J_CR(p_obj->p_pj_instance->CR); + INIT_GPIO_PORT_J_FR1(p_obj->p_pj_instance->FR1); + INIT_GPIO_PORT_J_FR2(p_obj->p_pj_instance->FR2); + INIT_GPIO_PORT_J_FR3(p_obj->p_pj_instance->FR3); + INIT_GPIO_PORT_J_FR4(p_obj->p_pj_instance->FR4); + INIT_GPIO_PORT_J_FR5(p_obj->p_pj_instance->FR5); + INIT_GPIO_PORT_J_FR6(p_obj->p_pj_instance->FR6); + INIT_GPIO_PORT_J_FR7(p_obj->p_pj_instance->FR7); + INIT_GPIO_PORT_J_FR8(p_obj->p_pj_instance->FR8); + INIT_GPIO_PORT_J_OD(p_obj->p_pj_instance->OD); + INIT_GPIO_PORT_J_PUP(p_obj->p_pj_instance->PUP); + INIT_GPIO_PORT_J_PDN(p_obj->p_pj_instance->PDN); + INIT_GPIO_PORT_J_IE(p_obj->p_pj_instance->IE); + /* PJ Clock Disable */ + PORT_CLOCK_DISABLE_PORTJ(TSB_CG_FSYSMENB_IPMENB10); + break; + case GPIO_PORT_K: + INIT_GPIO_PORT_K_DATA(p_obj->p_pk_instance->DATA); + INIT_GPIO_PORT_K_CR(p_obj->p_pk_instance->CR); + INIT_GPIO_PORT_K_FR1(p_obj->p_pk_instance->FR1); + INIT_GPIO_PORT_K_FR2(p_obj->p_pk_instance->FR2); + INIT_GPIO_PORT_K_FR3(p_obj->p_pk_instance->FR3); + INIT_GPIO_PORT_K_FR4(p_obj->p_pk_instance->FR4); + INIT_GPIO_PORT_K_FR5(p_obj->p_pk_instance->FR5); + INIT_GPIO_PORT_K_FR6(p_obj->p_pk_instance->FR6); + INIT_GPIO_PORT_K_FR7(p_obj->p_pk_instance->FR7); + INIT_GPIO_PORT_K_FR8(p_obj->p_pk_instance->FR8); + INIT_GPIO_PORT_K_OD(p_obj->p_pk_instance->OD); + INIT_GPIO_PORT_K_PUP(p_obj->p_pk_instance->PUP); + INIT_GPIO_PORT_K_PDN(p_obj->p_pk_instance->PDN); + INIT_GPIO_PORT_K_IE(p_obj->p_pk_instance->IE); + /* PK Clock Disable */ + PORT_CLOCK_DISABLE_PORTK(TSB_CG_FSYSMENB_IPMENB11); + break; + case GPIO_PORT_L: + INIT_GPIO_PORT_L_DATA(p_obj->p_pl_instance->DATA); + INIT_GPIO_PORT_L_CR(p_obj->p_pl_instance->CR); + INIT_GPIO_PORT_L_FR1(p_obj->p_pl_instance->FR1); + INIT_GPIO_PORT_L_FR2(p_obj->p_pl_instance->FR2); + INIT_GPIO_PORT_L_FR3(p_obj->p_pl_instance->FR3); + INIT_GPIO_PORT_L_FR4(p_obj->p_pl_instance->FR4); + INIT_GPIO_PORT_L_FR5(p_obj->p_pl_instance->FR5); + INIT_GPIO_PORT_L_FR6(p_obj->p_pl_instance->FR6); + INIT_GPIO_PORT_L_FR7(p_obj->p_pl_instance->FR7); + INIT_GPIO_PORT_L_FR8(p_obj->p_pl_instance->FR8); + INIT_GPIO_PORT_L_OD(p_obj->p_pl_instance->OD); + INIT_GPIO_PORT_L_PUP(p_obj->p_pl_instance->PUP); + INIT_GPIO_PORT_L_PDN(p_obj->p_pl_instance->PDN); + INIT_GPIO_PORT_L_IE(p_obj->p_pl_instance->IE); + /* PL Clock Disable */ + PORT_CLOCK_DISABLE_PORTL(TSB_CG_FSYSMENB_IPMENB12); + break; + case GPIO_PORT_M: + INIT_GPIO_PORT_M_DATA(p_obj->p_pm_instance->DATA); + INIT_GPIO_PORT_M_CR(p_obj->p_pm_instance->CR); + INIT_GPIO_PORT_M_FR1(p_obj->p_pm_instance->FR1); + INIT_GPIO_PORT_M_FR2(p_obj->p_pm_instance->FR2); + INIT_GPIO_PORT_M_FR3(p_obj->p_pm_instance->FR3); + INIT_GPIO_PORT_M_FR4(p_obj->p_pm_instance->FR4); + INIT_GPIO_PORT_M_FR5(p_obj->p_pm_instance->FR5); + INIT_GPIO_PORT_M_FR6(p_obj->p_pm_instance->FR6); + INIT_GPIO_PORT_M_FR7(p_obj->p_pm_instance->FR7); + INIT_GPIO_PORT_M_FR8(p_obj->p_pm_instance->FR8); + INIT_GPIO_PORT_M_OD(p_obj->p_pm_instance->OD); + INIT_GPIO_PORT_M_PUP(p_obj->p_pm_instance->PUP); + INIT_GPIO_PORT_M_PDN(p_obj->p_pm_instance->PDN); + INIT_GPIO_PORT_M_IE(p_obj->p_pm_instance->IE); + /* PM Clock Disable */ + PORT_CLOCK_DISABLE_PORTM(TSB_CG_FSYSMENB_IPMENB13); + break; + case GPIO_PORT_N: + INIT_GPIO_PORT_N_DATA(p_obj->p_pn_instance->DATA); + INIT_GPIO_PORT_N_CR(p_obj->p_pn_instance->CR); + INIT_GPIO_PORT_N_FR1(p_obj->p_pn_instance->FR1); + INIT_GPIO_PORT_N_FR2(p_obj->p_pn_instance->FR2); + INIT_GPIO_PORT_N_FR3(p_obj->p_pn_instance->FR3); + INIT_GPIO_PORT_N_FR4(p_obj->p_pn_instance->FR4); + INIT_GPIO_PORT_N_FR5(p_obj->p_pn_instance->FR5); + INIT_GPIO_PORT_N_FR6(p_obj->p_pn_instance->FR6); + INIT_GPIO_PORT_N_FR7(p_obj->p_pn_instance->FR7); + INIT_GPIO_PORT_N_FR8(p_obj->p_pn_instance->FR8); + INIT_GPIO_PORT_N_OD(p_obj->p_pn_instance->OD); + INIT_GPIO_PORT_N_PUP(p_obj->p_pn_instance->PUP); + INIT_GPIO_PORT_N_PDN(p_obj->p_pn_instance->PDN); + INIT_GPIO_PORT_N_IE(p_obj->p_pn_instance->IE); + /* PN Clock Disable */ + PORT_CLOCK_DISABLE_PORTN(TSB_CG_FSYSMENB_IPMENB14); + break; + case GPIO_PORT_P: + INIT_GPIO_PORT_P_DATA(p_obj->p_pp_instance->DATA); + INIT_GPIO_PORT_P_CR(p_obj->p_pp_instance->CR); + INIT_GPIO_PORT_P_FR1(p_obj->p_pp_instance->FR1); + INIT_GPIO_PORT_P_FR2(p_obj->p_pp_instance->FR2); + INIT_GPIO_PORT_P_FR3(p_obj->p_pp_instance->FR3); + INIT_GPIO_PORT_P_FR4(p_obj->p_pp_instance->FR4); + INIT_GPIO_PORT_P_FR5(p_obj->p_pp_instance->FR5); + INIT_GPIO_PORT_P_FR6(p_obj->p_pp_instance->FR6); + INIT_GPIO_PORT_P_FR7(p_obj->p_pp_instance->FR7); + INIT_GPIO_PORT_P_FR8(p_obj->p_pp_instance->FR8); + INIT_GPIO_PORT_P_OD(p_obj->p_pp_instance->OD); + INIT_GPIO_PORT_P_PUP(p_obj->p_pp_instance->PUP); + INIT_GPIO_PORT_P_PDN(p_obj->p_pp_instance->PDN); + INIT_GPIO_PORT_P_IE(p_obj->p_pp_instance->IE); + /* PP Clock Disable */ + PORT_CLOCK_DISABLE_PORTP(TSB_CG_FSYSMENB_IPMENB15); + break; + case GPIO_PORT_R: + INIT_GPIO_PORT_R_DATA(p_obj->p_pr_instance->DATA); + INIT_GPIO_PORT_R_CR(p_obj->p_pr_instance->CR); + INIT_GPIO_PORT_R_FR1(p_obj->p_pr_instance->FR1); + INIT_GPIO_PORT_R_FR2(p_obj->p_pr_instance->FR2); + INIT_GPIO_PORT_R_FR3(p_obj->p_pr_instance->FR3); + INIT_GPIO_PORT_R_FR4(p_obj->p_pr_instance->FR4); + INIT_GPIO_PORT_R_FR5(p_obj->p_pr_instance->FR5); + INIT_GPIO_PORT_R_FR6(p_obj->p_pr_instance->FR6); + INIT_GPIO_PORT_R_FR7(p_obj->p_pr_instance->FR7); + INIT_GPIO_PORT_R_FR8(p_obj->p_pr_instance->FR8); + INIT_GPIO_PORT_R_OD(p_obj->p_pr_instance->OD); + INIT_GPIO_PORT_R_PUP(p_obj->p_pr_instance->PUP); + INIT_GPIO_PORT_R_PDN(p_obj->p_pr_instance->PDN); + INIT_GPIO_PORT_R_IE(p_obj->p_pr_instance->IE); + /* PR Clock Disable */ + PORT_CLOCK_DISABLE_PORTR(TSB_CG_FSYSMENB_IPMENB16); + break; + case GPIO_PORT_T: + INIT_GPIO_PORT_T_DATA(p_obj->p_pt_instance->DATA); + INIT_GPIO_PORT_T_CR(p_obj->p_pt_instance->CR); + INIT_GPIO_PORT_T_FR1(p_obj->p_pt_instance->FR1); + INIT_GPIO_PORT_T_FR2(p_obj->p_pt_instance->FR2); + INIT_GPIO_PORT_T_FR3(p_obj->p_pt_instance->FR3); + INIT_GPIO_PORT_T_FR4(p_obj->p_pt_instance->FR4); + INIT_GPIO_PORT_T_FR5(p_obj->p_pt_instance->FR5); + INIT_GPIO_PORT_T_FR6(p_obj->p_pt_instance->FR6); + INIT_GPIO_PORT_T_FR7(p_obj->p_pt_instance->FR7); + INIT_GPIO_PORT_T_FR8(p_obj->p_pt_instance->FR8); + INIT_GPIO_PORT_T_OD(p_obj->p_pt_instance->OD); + INIT_GPIO_PORT_T_PUP(p_obj->p_pt_instance->PUP); + INIT_GPIO_PORT_T_PDN(p_obj->p_pt_instance->PDN); + INIT_GPIO_PORT_T_IE(p_obj->p_pt_instance->IE); + /* PT Clock Disable */ + PORT_CLOCK_DISABLE_PORTT(TSB_CG_FSYSMENB_IPMENB17); + break; + case GPIO_PORT_U: + INIT_GPIO_PORT_U_DATA(p_obj->p_pu_instance->DATA); + INIT_GPIO_PORT_U_CR(p_obj->p_pu_instance->CR); + INIT_GPIO_PORT_U_FR1(p_obj->p_pu_instance->FR1); + INIT_GPIO_PORT_U_FR2(p_obj->p_pu_instance->FR2); + INIT_GPIO_PORT_U_FR3(p_obj->p_pu_instance->FR3); + INIT_GPIO_PORT_U_FR4(p_obj->p_pu_instance->FR4); + INIT_GPIO_PORT_U_FR5(p_obj->p_pu_instance->FR5); + INIT_GPIO_PORT_U_FR6(p_obj->p_pu_instance->FR6); + INIT_GPIO_PORT_U_FR7(p_obj->p_pu_instance->FR7); + INIT_GPIO_PORT_U_FR8(p_obj->p_pu_instance->FR8); + INIT_GPIO_PORT_U_OD(p_obj->p_pu_instance->OD); + INIT_GPIO_PORT_U_PUP(p_obj->p_pu_instance->PUP); + INIT_GPIO_PORT_U_PDN(p_obj->p_pu_instance->PDN); + INIT_GPIO_PORT_U_IE(p_obj->p_pu_instance->IE); + /* PU Clock Disable */ + PORT_CLOCK_DISABLE_PORTU(TSB_CG_FSYSMENB_IPMENB18); + break; + case GPIO_PORT_V: + INIT_GPIO_PORT_V_DATA(p_obj->p_pv_instance->DATA); + INIT_GPIO_PORT_V_CR(p_obj->p_pv_instance->CR); + INIT_GPIO_PORT_V_FR1(p_obj->p_pv_instance->FR1); + INIT_GPIO_PORT_V_FR2(p_obj->p_pv_instance->FR2); + INIT_GPIO_PORT_V_FR3(p_obj->p_pv_instance->FR3); + INIT_GPIO_PORT_V_FR4(p_obj->p_pv_instance->FR4); + INIT_GPIO_PORT_V_FR5(p_obj->p_pv_instance->FR5); + INIT_GPIO_PORT_V_FR6(p_obj->p_pv_instance->FR6); + INIT_GPIO_PORT_V_FR7(p_obj->p_pv_instance->FR7); + INIT_GPIO_PORT_V_FR8(p_obj->p_pv_instance->FR8); + INIT_GPIO_PORT_V_OD(p_obj->p_pv_instance->OD); + INIT_GPIO_PORT_V_PUP(p_obj->p_pv_instance->PUP); + INIT_GPIO_PORT_V_PDN(p_obj->p_pv_instance->PDN); + INIT_GPIO_PORT_V_IE(p_obj->p_pv_instance->IE); + /* PV Clock Disable */ + PORT_CLOCK_DISABLE_PORTV(TSB_CG_FSYSMENB_IPMENB19); + break; + case GPIO_PORT_W: + INIT_GPIO_PORT_W_DATA(p_obj->p_pw_instance->DATA); + INIT_GPIO_PORT_W_CR(p_obj->p_pw_instance->CR); + INIT_GPIO_PORT_W_FR1(p_obj->p_pw_instance->FR1); + INIT_GPIO_PORT_W_FR2(p_obj->p_pw_instance->FR2); + INIT_GPIO_PORT_W_FR3(p_obj->p_pw_instance->FR3); + INIT_GPIO_PORT_W_FR4(p_obj->p_pw_instance->FR4); + INIT_GPIO_PORT_W_FR5(p_obj->p_pw_instance->FR5); + INIT_GPIO_PORT_W_FR6(p_obj->p_pw_instance->FR6); + INIT_GPIO_PORT_W_FR7(p_obj->p_pw_instance->FR7); + INIT_GPIO_PORT_W_FR8(p_obj->p_pw_instance->FR8); + INIT_GPIO_PORT_W_OD(p_obj->p_pw_instance->OD); + INIT_GPIO_PORT_W_PUP(p_obj->p_pw_instance->PUP); + INIT_GPIO_PORT_W_PDN(p_obj->p_pw_instance->PDN); + INIT_GPIO_PORT_W_IE(p_obj->p_pw_instance->IE); + /* PW Clock Disable */ + PORT_CLOCK_DISABLE_PORTW(TSB_CG_FSYSMENB_IPMENB20); + break; + case GPIO_PORT_Y: + INIT_GPIO_PORT_Y_DATA(p_obj->p_py_instance->DATA); + INIT_GPIO_PORT_Y_CR(p_obj->p_py_instance->CR); + INIT_GPIO_PORT_Y_FR1(p_obj->p_py_instance->FR1); + INIT_GPIO_PORT_Y_FR2(p_obj->p_py_instance->FR2); + INIT_GPIO_PORT_Y_FR3(p_obj->p_py_instance->FR3); + INIT_GPIO_PORT_Y_FR4(p_obj->p_py_instance->FR4); + INIT_GPIO_PORT_Y_FR5(p_obj->p_py_instance->FR5); + INIT_GPIO_PORT_Y_FR6(p_obj->p_py_instance->FR6); + INIT_GPIO_PORT_Y_FR7(p_obj->p_py_instance->FR7); + INIT_GPIO_PORT_Y_FR8(p_obj->p_py_instance->FR8); + INIT_GPIO_PORT_Y_OD(p_obj->p_py_instance->OD); + INIT_GPIO_PORT_Y_PUP(p_obj->p_py_instance->PUP); + INIT_GPIO_PORT_Y_PDN(p_obj->p_py_instance->PDN); + INIT_GPIO_PORT_Y_IE(p_obj->p_py_instance->IE); + /* PY Clock Disable */ + PORT_CLOCK_DISABLE_PORTY(TSB_CG_FSYSMENB_IPMENB21); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) + * @brief Port Mode Write + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[in] val :value + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t i; + int32_t param_result = PARAM_NG; + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + WRITE_PORT(mode, p_obj->p_pa_instance, val, PinExistTbl[GPIO_PORT_A][i]); + break; + case GPIO_PORT_B: + WRITE_PORT(mode, p_obj->p_pb_instance, val, PinExistTbl[GPIO_PORT_B][i]); + break; + case GPIO_PORT_C: + WRITE_PORT(mode, p_obj->p_pc_instance, val, PinExistTbl[GPIO_PORT_C][i]); + break; + case GPIO_PORT_D: + WRITE_PORT(mode, p_obj->p_pd_instance, val, PinExistTbl[GPIO_PORT_D][i]); + break; + case GPIO_PORT_E: + WRITE_PORT(mode, p_obj->p_pe_instance, val, PinExistTbl[GPIO_PORT_E][i]); + break; + case GPIO_PORT_F: + WRITE_PORT(mode, p_obj->p_pf_instance, val, PinExistTbl[GPIO_PORT_F][i]); + break; + case GPIO_PORT_G: + WRITE_PORT(mode, p_obj->p_pg_instance, val, PinExistTbl[GPIO_PORT_G][i]); + break; + case GPIO_PORT_H: + WRITE_PORT(mode, p_obj->p_ph_instance, val, PinExistTbl[GPIO_PORT_H][i]); + break; + case GPIO_PORT_J: + WRITE_PORT(mode, p_obj->p_pj_instance, val, PinExistTbl[GPIO_PORT_J][i]); + break; + case GPIO_PORT_K: + WRITE_PORT(mode, p_obj->p_pk_instance, val, PinExistTbl[GPIO_PORT_K][i]); + break; + case GPIO_PORT_L: + WRITE_PORT(mode, p_obj->p_pl_instance, val, PinExistTbl[GPIO_PORT_L][i]); + break; + case GPIO_PORT_M: + WRITE_PORT(mode, p_obj->p_pm_instance, val, PinExistTbl[GPIO_PORT_M][i]); + break; + case GPIO_PORT_N: + WRITE_PORT(mode, p_obj->p_pn_instance, val, PinExistTbl[GPIO_PORT_N][i]); + break; + case GPIO_PORT_P: + WRITE_PORT(mode, p_obj->p_pp_instance, val, PinExistTbl[GPIO_PORT_P][i]); + break; + case GPIO_PORT_R: + WRITE_PORT(mode, p_obj->p_pr_instance, val, PinExistTbl[GPIO_PORT_R][i]); + break; + case GPIO_PORT_T: + WRITE_PORT(mode, p_obj->p_pt_instance, val, PinExistTbl[GPIO_PORT_T][i]); + break; + case GPIO_PORT_U: + WRITE_PORT(mode, p_obj->p_pu_instance, val, PinExistTbl[GPIO_PORT_U][i]); + break; + case GPIO_PORT_V: + WRITE_PORT(mode, p_obj->p_pv_instance, val, PinExistTbl[GPIO_PORT_V][i]); + break; + case GPIO_PORT_W: + WRITE_PORT(mode, p_obj->p_pw_instance, val, PinExistTbl[GPIO_PORT_W][i]); + break; + case GPIO_PORT_Y: + WRITE_PORT(mode, p_obj->p_py_instance, val, PinExistTbl[GPIO_PORT_Y][i]); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) + * @brief Port Mode Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[out] val :Store of value + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t param_result = PARAM_NG; + int32_t i; + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + READ_PORT(mode, p_obj->p_pa_instance, val, PinExistTbl[GPIO_PORT_A][i]); + break; + case GPIO_PORT_B: + READ_PORT(mode, p_obj->p_pb_instance, val, PinExistTbl[GPIO_PORT_B][i]); + break; + case GPIO_PORT_C: + READ_PORT(mode, p_obj->p_pc_instance, val, PinExistTbl[GPIO_PORT_C][i]); + break; + case GPIO_PORT_D: + READ_PORT(mode, p_obj->p_pd_instance, val, PinExistTbl[GPIO_PORT_D][i]); + break; + case GPIO_PORT_E: + READ_PORT(mode, p_obj->p_pe_instance, val, PinExistTbl[GPIO_PORT_E][i]); + break; + case GPIO_PORT_F: + READ_PORT(mode, p_obj->p_pf_instance, val, PinExistTbl[GPIO_PORT_F][i]); + break; + case GPIO_PORT_G: + READ_PORT(mode, p_obj->p_pg_instance, val, PinExistTbl[GPIO_PORT_G][i]); + break; + case GPIO_PORT_H: + READ_PORT(mode, p_obj->p_ph_instance, val, PinExistTbl[GPIO_PORT_H][i]); + break; + case GPIO_PORT_J: + READ_PORT(mode, p_obj->p_pj_instance, val, PinExistTbl[GPIO_PORT_J][i]); + break; + case GPIO_PORT_K: + READ_PORT(mode, p_obj->p_pk_instance, val, PinExistTbl[GPIO_PORT_K][i]); + break; + case GPIO_PORT_L: + READ_PORT(mode, p_obj->p_pl_instance, val, PinExistTbl[GPIO_PORT_L][i]); + break; + case GPIO_PORT_M: + READ_PORT(mode, p_obj->p_pm_instance, val, PinExistTbl[GPIO_PORT_M][i]); + break; + case GPIO_PORT_N: + READ_PORT(mode, p_obj->p_pn_instance, val, PinExistTbl[GPIO_PORT_N][i]); + break; + case GPIO_PORT_P: + READ_PORT(mode, p_obj->p_pp_instance, val, PinExistTbl[GPIO_PORT_P][i]); + break; + case GPIO_PORT_R: + READ_PORT(mode, p_obj->p_pr_instance, val, PinExistTbl[GPIO_PORT_R][i]); + break; + case GPIO_PORT_T: + READ_PORT(mode, p_obj->p_pt_instance, val, PinExistTbl[GPIO_PORT_T][i]); + break; + case GPIO_PORT_U: + READ_PORT(mode, p_obj->p_pu_instance, val, PinExistTbl[GPIO_PORT_U][i]); + break; + case GPIO_PORT_V: + READ_PORT(mode, p_obj->p_pv_instance, val, PinExistTbl[GPIO_PORT_V][i]); + break; + case GPIO_PORT_W: + READ_PORT(mode, p_obj->p_pw_instance, val, PinExistTbl[GPIO_PORT_W][i]); + break; + case GPIO_PORT_Y: + READ_PORT(mode, p_obj->p_py_instance, val, PinExistTbl[GPIO_PORT_Y][i]); + break; + default: + result = TXZ_ERROR; + break; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Port Function switching + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t + * @param inout :GPIO Input/Output.: Use @ref gpio_pininout_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + int32_t param_result = PARAM_NG; + + /* Check the parameters, the NULL of address */ + param_result = check_param_func_pin_exist(p_obj, group, num, func); + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + port_base = (uint32_t)p_obj->p_pa_instance; + break; + case GPIO_PORT_B: + port_base = (uint32_t)p_obj->p_pb_instance; + break; + case GPIO_PORT_C: + port_base = (uint32_t)p_obj->p_pc_instance; + break; + case GPIO_PORT_D: + port_base = (uint32_t)p_obj->p_pd_instance; + break; + case GPIO_PORT_E: + port_base = (uint32_t)p_obj->p_pe_instance; + break; + case GPIO_PORT_F: + port_base = (uint32_t)p_obj->p_pf_instance; + break; + case GPIO_PORT_G: + port_base = (uint32_t)p_obj->p_pg_instance; + break; + case GPIO_PORT_H: + port_base = (uint32_t)p_obj->p_ph_instance; + break; + case GPIO_PORT_J: + port_base = (uint32_t)p_obj->p_pj_instance; + break; + case GPIO_PORT_K: + port_base = (uint32_t)p_obj->p_pk_instance; + break; + case GPIO_PORT_L: + port_base = (uint32_t)p_obj->p_pl_instance; + break; + case GPIO_PORT_M: + port_base = (uint32_t)p_obj->p_pm_instance; + break; + case GPIO_PORT_N: + port_base = (uint32_t)p_obj->p_pn_instance; + break; + case GPIO_PORT_P: + port_base = (uint32_t)p_obj->p_pp_instance; + break; + case GPIO_PORT_R: + port_base = (uint32_t)p_obj->p_pr_instance; + break; + case GPIO_PORT_T: + port_base = (uint32_t)p_obj->p_pt_instance; + break; + case GPIO_PORT_U: + port_base = (uint32_t)p_obj->p_pu_instance; + break; + case GPIO_PORT_V: + port_base = (uint32_t)p_obj->p_pv_instance; + break; + case GPIO_PORT_W: + port_base = (uint32_t)p_obj->p_pw_instance; + break; + case GPIO_PORT_Y: + port_base = (uint32_t)p_obj->p_py_instance; + break; + default: + result = TXZ_ERROR; + break; + } + if (result == TXZ_ERROR) { + return (result); + } + + /* Initialization PxFR OFF */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_CLR(mode_base, num); + + /* Initialize Input/Output */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + + switch (func) { + case 0: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_1: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_2: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_3: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_4: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_5: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case GPIO_FR_6: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_7: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_8: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_NA: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Pull up mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PUP) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PUP); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Set Pull down mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PDN) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PDN); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Set Open drain mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_OD) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_OD); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) + * @brief Port Bit Write + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param val :GPIO Pin Reset/Set. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + + /* Check the parameters */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + } else { + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(base, num); + } else { + result = TXZ_ERROR; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) + * @brief Port Bit Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + uint32_t val; + + /* Check the parameters */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + } else { + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + BITBAND_PORT_READ(val, base, num); + if (val == GPIO_PIN_RESET) { + *pinstate = GPIO_PIN_RESET; + } else if (val == GPIO_PIN_SET) { + *pinstate = GPIO_PIN_SET; + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__GPIO_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_hal.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_hal.c new file mode 100644 index 0000000..fda615a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_hal.c @@ -0,0 +1,297 @@ +/** + ******************************************************************************* + * @file txz_hal.c + * @brief This file provides API functions for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_hal.h" + +#if defined(__HAL_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup HAL + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_macro HAL Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ +/** + * @defgroup wait Configuration + * @brief wait Configuration. + * @{ + */ +#define WAIT_UNIT_1US ((uint32_t)(1000000)) /*!< 1S-1us transfor unit. */ +#define WAIT_FORLOOP_STEPS ((uint32_t)(5)) /*!< for loop steps. */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */ +#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */ +#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */ +#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */ +#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */ +/* FC RACCR setting configration */ +#define FC_RACCR_RAMLC_1CLK (0x00000000UL) /*!< 1clock(less than 160MHZ). */ +#define FC_RACCR_RAMLC_2CLK (0x00000010UL) /*!< 2clock(more than 160MHZ). */ + +/** + * @} + */ /* End of group waitConfiguration */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_typedef HAL Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_fuctions HAL Private Fuctions + * @{ + */ + +static uint32_t tick; + +/** + * @} + */ /* End of group HAL_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup HAL_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Increment a tick value. + * @param - + * @retval - + * @note Please call by user. + * @note In the sample, this variable is incremented each 1ms timer interrupt. + */ +/*--------------------------------------------------*/ +void hal_inc_tick(void) +{ + tick++; +} + +/*--------------------------------------------------*/ +/** + * @brief Provides a tick value. + * @param - + * @return Tick value. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +uint32_t hal_get_tick(void) +{ + return (tick); +} + +/*--------------------------------------------------*/ +/** + * @brief wait Function(us) + * @param uint32_t :count(unit:us). + * @return void + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void wait(uint32_t count) +{ + uint32_t i, steps; + + /*-----------------------------------------*/ + /* step : 1000000us = fsys :1 */ + /* step = EOSC_SYS_CLOCK/1000000 */ + /*-----------------------------------------*/ + /* system core clock update */ + SystemCoreClockUpdate(); + steps = count * (SystemCoreClock / WAIT_UNIT_1US) / WAIT_FORLOOP_STEPS; + + for (i = 0; i < steps; ++i) { + __NOP(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief copy 32-bit data from source to dest + * @param the address of source and dast, the data size + * @retval None. + * @note - + */ +/*--------------------------------------------------*/ +void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size) +{ + uint32_t *dest_addr, *source_addr, tmpsize; + uint32_t i, tmps, tmpd, mask; + + dest_addr = dest; + source_addr = source; + + tmpsize = size >> 2U; + for (i = 0U; i < tmpsize; i++) { /* 32bits copy */ + *dest_addr = *source_addr; + dest_addr++; + source_addr++; + } + if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */ + mask = 0xFFFFFF00U; + i = size & 0x00000003U; + tmps = *source_addr; + tmpd = *dest_addr; + while (i - 1U) { + mask = mask << 8U; + i--; + } + tmps = tmps & (~mask); + tmpd = tmpd & (mask); + *dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */ + } else { + /* Do nothing */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief RAM register set. + * @param none. + * @retval none. + * @note - + */ +/*--------------------------------------------------*/ +void fc_ram_con_reg_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */ + regval = (uint32_t)FC_RACCR_RAMLC_1CLK; + } else { /* more than 160MHZ */ + regval = (uint32_t)FC_RACCR_RAMLC_2CLK; + } + + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->RACCR = regval; + while ((TSB_FC->RACCR != FC_RACCR_RAMLC_1CLK) && (TSB_FC->RACCR != FC_RACCR_RAMLC_2CLK)) { + /* no processing */ + } +} + +/** + * @} + */ /* End of group HAL_Exported_functions */ + +/** + * @} + */ /* End of group HAL */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__HAL_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c.c new file mode 100644 index 0000000..c48c4f9 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c.c @@ -0,0 +1,414 @@ +/** + ******************************************************************************* + * @file txz_i2c.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c.h" + +#if defined(__I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief SCK Divider value table. + * @details SCK = b000 - b111. + * @note NFSEL=0 (Digital Setting) Divider value. +*/ +/*----------------------------------*/ +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528 }; +static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 }; + +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initializing I2C Regester + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE; + p_obj->p_instance->OP = I2CxOP_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->AR = I2CxAR_INIT; + p_obj->p_instance->AR2 = I2CxAR2_INIT; + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); + p_obj->p_instance->IE = I2CxIE_CLEAR; +} + +/*--------------------------------------------------*/ +/** + * @brief Generate start condition + * @param p_obj :I2C object. + * @param data :Slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_start_condition(I2C_t *p_obj, uint32_t data) +{ + __IO uint32_t opreg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + opreg = p_obj->p_instance->OP; + opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); + if (I2C_master(p_obj)) { + if ((p_obj->p_instance->SR & I2CxSR_BB)) { + opreg |= I2CxOP_SREN; + } + } + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->OP = opreg; + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION; +} + +/*--------------------------------------------------*/ +/** + * @brief Return the I2c clock setting + * @param p_obj :I2C object. + * @param frequency :Maximum frequency. + * @param fsys :SystemCoreClock. + * @param p_setting :Clock data pointer. + * @retval Non-zero :Scl frequency. + * @retval 0 :Error. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting) +{ + uint32_t result = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_setting)); +#endif /* #ifdef __DEBUG__ */ + + if (frequency <= 1000000) { + uint64_t sck, tmp_sck; + uint64_t prsck, tmp_prsck; + uint64_t fscl, tmp_fscl; + uint64_t fx; + uint64_t max_fx, min_fx; + uint64_t low_width, low_width_min; + + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + + if (frequency <= 400000) { + max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */ + min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */ + low_width_min = 1600; + } else { + max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */ + min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */ + low_width_min = 675; + } + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)fsys / prsck); + + if ((fx < max_fx) && (fx >= min_fx)) { + for (sck = 0; sck <= 7; sck++) { + low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys; + if (low_width < low_width_min) { + continue; + } + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + + if ((fscl <= frequency) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32) ? prsck : 0; + } + } + } + } + result = (uint32_t)tmp_fscl; + p_setting->sck = (uint32_t)tmp_sck; + p_setting->prsck = (tmp_prsck < 32) ? (uint32_t)tmp_prsck : 0; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Slave mode setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_slave_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->OP = I2CxOP_SLAVE_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck); + p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); +} +#if defined(I2CSxWUP_EN) +/*--------------------------------------------------*/ +/** + * @brief I2C Wakeup Control setting. + * @param p_obj :I2CS object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_init(I2CS_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR1 = (p_obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend); +} + +/*--------------------------------------------------*/ +/** + * @brief Primary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Primary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR2 = (0x0000000E & adr); +} + +/*--------------------------------------------------*/ +/** + * @brief Secondary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Secondary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR3 = (0x0000000E & adr); + p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */ +} +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c_api.c new file mode 100644 index 0000000..a30079d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_i2c_api.c @@ -0,0 +1,1721 @@ +/** + ******************************************************************************* + * @file i2c_b.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c_api.h" + +#if defined(__BSP_I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name timeout + * @brief This timeouts are not based on accurate values, this just guarantee that + the application will not remain stuck if the I2C communication is corrupted. + * @{ + */ +#define I2C_TIMEOUT (100000) /*>! fail safe. */ + +/** + * @} + */ /* End of name timeout */ + +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +#define I2C_CH0 (0) /*!< I2C Channel 0. */ +#define I2C_CH1 (1) /*!< I2C Channel 1. */ +#define I2C_CH2 (2) /*!< I2C Channel 2. */ +#define I2C_CH3 (3) /*!< I2C Channel 3. */ +#define I2C_CH4 (4) /*!< I2C Channel 3. */ +#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +/*----------------------------------*/ +/** + * @brief Transfer State. +*/ +/*----------------------------------*/ +enum { + I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */ + I2C_TRANSFER_STATE_BUSY /*!< Busy. */ +} TransferState; + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief For IRQn_Type number definition. +*/ +/*----------------------------------*/ +typedef struct { + IRQn_Type i2c; + IRQn_Type al; + IRQn_Type bf; + IRQn_Type na; +} i2c_irq_t; + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief Channel 0 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = { + { INTI2C0NST_IRQn, INTI2C0ATX_IRQn, INTI2C0BRX_IRQn, INTI2C0NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 1 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = { + { INTI2C1NST_IRQn, INTI2C1ATX_IRQn, INTI2C1BRX_IRQn, INTI2C1NA_IRQn } +}; + +/*----------------------------------*/ +/** + * @brief Channel 2 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = { + { INTI2C2NST_IRQn, INTI2C2ATX_IRQn, INTI2C2BRX_IRQn, INTI2C2NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 3 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH3_IRQN_TBL[1] = { + {INTI2C3NST_IRQn, INTI2C3ATX_IRQn, INTI2C3BRX_IRQn, INTI2C3NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 4 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH4_IRQN_TBL[1] = { + { INTI2C4NST_IRQn, INTI2C4ATX_IRQn, INTI2C4BRX_IRQn, INTI2C4NA_IRQn} +}; +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn); +__STATIC_INLINE int32_t check_param_address(int32_t address); +#endif +__STATIC_INLINE void enable_irq(uint32_t irqn); +__STATIC_INLINE void disable_irq(uint32_t irqn); +__STATIC_INLINE void clear_irq(uint32_t irqn); +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj); +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj); +static void i2c_irq_handler(_i2c_t *p_obj); +static void i2c_slave_irq_handler(_i2c_t *p_obj); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Compare the IRQn's parameter. + * @param irqn :I2C IRQn List. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note -. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn) +{ + int32_t result = I2C_PARAM_NG; + + if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL) { + result = I2C_PARAM_OK; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Compare the Slave address's parameter. + * @param address :Address. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note Here, 10bit address has not supported. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_address(int32_t address) +{ + int32_t result = I2C_PARAM_NG; + + if ((address >= 0) && (address <= 255)) { + result = I2C_PARAM_OK; + } + return (result); +} +#endif + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_EnableIRQ(p_irqn->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_DisableIRQ(p_irqn->i2c); + NVIC_DisableIRQ(p_irqn->al); + NVIC_DisableIRQ(p_irqn->bf); + NVIC_DisableIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief ClearPending I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void clear_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_ClearPendingIRQ(p_irqn->i2c); + NVIC_ClearPendingIRQ(p_irqn->al); + NVIC_ClearPendingIRQ(p_irqn->bf); + NVIC_ClearPendingIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PG2, PG3) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) { + /* Port G */ + + /* SCL */ + TSB_PG_IE_PG3IE = 0; /* Input :Disable */ + TSB_PG_CR_PG3C = 0; /* Output :Disable */ + TSB_PG_OD_PG3OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG3UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG3DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG3 = 0; /* Data :0 */ + TSB_PG_FR7_PG3F7 = 1; /* Function :I2C0SCL */ + TSB_PG_IE_PG3IE = 1; /* Input :Enable */ + TSB_PG_CR_PG3C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PG_IE_PG2IE = 0; /* Input :Disable */ + TSB_PG_CR_PG2C = 0; /* Output :Disable */ + TSB_PG_OD_PG2OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG2UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG2DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG2 = 0; /* Data :0 */ + TSB_PG_FR7_PG2F7 = 1; /* Function :I2C0SDA */ + TSB_PG_IE_PG2IE = 1; /* Input :Enable */ + TSB_PG_CR_PG2C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PF2, PF3) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) { + /* Port F */ + + /* SCL */ + TSB_PF_IE_PF3IE = 0; /* Input :Disable */ + TSB_PF_CR_PF3C = 0; /* Output :Disable */ + TSB_PF_OD_PF3OD = 1; /* OD Control :Open Drain */ + TSB_PF_PUP_PF3UP = 0; /* Pull-up :Disable */ + TSB_PF_PDN_PF3DN = 0; /* Pull-down :Disable */ + TSB_PF_DATA_PF3 = 0; /* Data :0 */ + TSB_PF_FR7_PF3F7 = 1; /* Function :I2C0SCL */ + TSB_PF_IE_PF3IE = 1; /* Input :Enable */ + TSB_PF_CR_PF3C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PF_IE_PF2IE = 0; /* Input :Disable */ + TSB_PF_CR_PF2C = 0; /* Output :Disable */ + TSB_PF_OD_PF2OD = 1; /* OD Control :Open Drain */ + TSB_PF_PUP_PF2UP = 0; /* Pull-up :Disable */ + TSB_PF_PDN_PF2DN = 0; /* Pull-down :Disable */ + TSB_PF_DATA_PF2 = 0; /* Data :0 */ + TSB_PF_FR7_PF2F7 = 1; /* Function :I2C0SDA */ + TSB_PF_IE_PF2IE = 1; /* Input :Enable */ + TSB_PF_CR_PF2C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PG4, PG5) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) { + /* Port G */ + + /* SCL */ + TSB_PG_IE_PG5IE = 0; /* Input :Disable */ + TSB_PG_CR_PG5C = 0; /* Output :Disable */ + TSB_PG_OD_PG5OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG5UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG5DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG5 = 0; /* Data :0 */ + TSB_PG_FR7_PG5F7 = 1; /* Function :I2C0SCL */ + TSB_PG_IE_PG5IE = 1; /* Input :Enable */ + TSB_PG_CR_PG5C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PG_IE_PG4IE = 0; /* Input :Disable */ + TSB_PG_CR_PG4C = 0; /* Output :Disable */ + TSB_PG_OD_PG4OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG4UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG4DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG4 = 0; /* Data :0 */ + TSB_PG_FR7_PG4F7 = 1; /* Function :I2C0SDA */ + TSB_PG_IE_PG4IE = 1; /* Input :Enable */ + TSB_PG_CR_PG4C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PM0, PM1) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) { + /* Port M */ + + /* SCL */ + TSB_PJ_IE_PJ6IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ6C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ6OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ6UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ6DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ6 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ6F7 = 1; /* Function :I2C3SCL */ + TSB_PJ_IE_PJ6IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ6C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PJ_IE_PJ7IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ7C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ7OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ7UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ7DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ7 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ7F7 = 1; /* Function :I2C3SDA */ + TSB_PJ_IE_PJ7IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ7C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PM6, PM7) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) { + /* Port M */ + + /* SCL */ + TSB_PJ_IE_PJ2IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ2C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ2OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ2UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ2DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ2 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ2F7 = 1; /* Function :I2C3SCL */ + TSB_PJ_IE_PJ2IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ2C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PJ_IE_PJ3IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ3C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ3OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ3UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ3DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ3 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ3F7 = 1; /* Function :I2C3SDA */ + TSB_PJ_IE_PJ3IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ3C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Setting + * @param ch :I2C Channel. + * @param p_irqn :Destination Address of a I2C IRQn List. + * @retval non-zero :Instance Address. + * @retval zero :Channel not supported. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn) +{ + uint32_t instance = 0; + + switch (ch) { + case I2C_CH0: + instance = (uint32_t)TSB_I2C0; + *p_irqn = (uint32_t)&I2C_CH0_IRQN_TBL; + break; + + case I2C_CH1: + instance = (uint32_t)TSB_I2C1; + *p_irqn = (uint32_t)&I2C_CH1_IRQN_TBL; + break; + + case I2C_CH2: + instance = (uint32_t)TSB_I2C2; + *p_irqn = (uint32_t)&I2C_CH2_IRQN_TBL; + break; + + case I2C_CH3: + instance = (uint32_t)TSB_I2C3; + *p_irqn = (uint32_t)&I2C_CH3_IRQN_TBL; + break; + + case I2C_CH4: + instance = (uint32_t)TSB_I2C4; + *p_irqn = (uint32_t)&I2C_CH4_IRQN_TBL; + break; + + default: + break; + } + return (instance); +} + +/*--------------------------------------------------*/ +/** + * @brief Reset Asynch Transfer + * @param p_obj :i2c object + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); + I2C_disable_interrupt(&p_obj->i2c); +} + +__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); +#endif +} +/*--------------------------------------------------*/ +/** + * @brief Waiting i2c status + * @param p_obj :i2c object + * @retval 0 :Success. + * @retval -1 :Failure. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj) +{ + int32_t timeout; + + timeout = I2C_TIMEOUT; + while (!I2C_int_status(&p_obj->i2c)) { + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + (void)dummy; + return (-5); + } + if ((timeout--) == 0) { + return (-1); + } + } + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + (void)dummy; + return (-5); + } + return (0); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + if (I2C_transmitter(&p_obj->i2c)) { + int32_t start = I2C_restart(&p_obj->i2c); + (void)start; + + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if ((p_obj->tx_buff.pos < p_obj->tx_buff.length) || (p_obj->tx_buff.length == 0)) { + if (p_obj->tx_buff.pos == 0) { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } else { + int32_t start = I2C_restart(&p_obj->i2c); + + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_slave_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_slave_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + int32_t start = I2C_slave_detected(&p_obj->i2c); + if (start) { + uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c); + (void)sa; + } + if (I2C_transmitter(&p_obj->i2c)) { + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else { + /* dummy, wait nack */ + I2C_write_data(&p_obj->i2c, 0); + } + } else { + /* error event not be set */ + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_slave_init(&p_obj->i2c); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_enable_irq(_i2c_t *p_obj) +{ + enable_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_disable_irq(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initialize the I2C Driver + * @param p_obj :i2c object. + * @param sda :SDA port. + * @param scl :SCL port. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t instance = 0; + uint32_t irqn = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* ch0 */ + if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) { + set_port_ch0(sda, scl); + instance = set_i2c(I2C_CH0, &irqn); + } + /* ch1 */ + if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) { + set_port_ch1(sda, scl); + instance = set_i2c(I2C_CH1, &irqn); + } + /* ch2 */ + if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) { + set_port_ch2(sda, scl); + instance = set_i2c(I2C_CH2, &irqn); + } + /* ch3 */ + if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) { + set_port_ch3(sda, scl); + instance = set_i2c(I2C_CH3, &irqn); + } + /* ch4 */ + if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) { + set_port_ch4(sda, scl); + instance = set_i2c(I2C_CH3, &irqn); + } + + if ((instance != 0) && (irqn != 0)) { + disable_irq(irqn); + clear_irq(irqn); + + /* Set irqn table */ + p_obj->info.irqn = irqn; + + /* Set instance */ + p_obj->i2c.p_instance = (TSB_I2C_TypeDef *)instance; + + /* I2C Reset */ + i2c_reset_t(p_obj); + + /* Set Frequency Default at 100KHz */ + if (i2c_frequency_t(p_obj, 100000) == TXZ_SUCCESS) { + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Reset I2C peripheral + * @param p_obj :i2c object. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_reset_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* Software reset */ + I2C_reset(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure the I2C frequency + * @param p_obj :i2c object. + * @param hz :frequency in Hz. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_port_high(&p_obj->i2c)) { + uint32_t fval; + + SystemCoreClockUpdate(); + + fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock); + if (fval != 0) { + //I2C_init(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + p_obj->info.asynch.address = 0; + p_obj->info.asynch.stop = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + p_obj->info.asynch.event = 0; + p_obj->tx_buff.p_buffer = I2C_NULL; + p_obj->tx_buff.length = 0; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = I2C_NULL; + p_obj->rx_buff.length = 0; + p_obj->rx_buff.pos = 0; + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check bus free on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.bus_free = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a start condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure.(now, not use) + * @note Start condition is not generate yet, after this function returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_start_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.start = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a stop condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_stop_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_stop_condition(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + result = TXZ_ERROR; + break; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Address of Read data. + * @param length :Number of the bytes to read. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of read bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (length > 0) { + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U)); + if (result == I2C_ACK) { + /* Read all bytes */ + while (count < length) { + int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1)) ? 0 : 1)); + if (data < 0) { + result = data; + break; + } + p_data[count++] = (uint8_t)data; + } + result = count; + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1) ;//I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Destination address of Write data. + * @param length :Number of the bytes to write. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of write bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, address); + if (result == I2C_ACK) { + /* Write all bytes */ + while (count < length) { + int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]); + if (data < I2C_ACK) { + result = data; + break; + } + } + if (result >= 0) { + result = count; + } + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1); //I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Read one byte + * @param p_obj :i2c object. + * @param last :last acknowledge. + * @retval The read byte (but -1 is timout error). + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last) +{ + int32_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, last); + I2C_write_data(&p_obj->i2c, 0); + result = wait_status(p_obj); + if (result < 0) { + // result = -1; + } else { + result = (int32_t)I2C_read_data(&p_obj->i2c); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Write one byte + * @param p_obj :i2c object. + * @param data :Write data. + * @retval 0 :NACK was received. + * @retval 1 :ACK was received. + * @retval -1 :Timout error. + * @note Macro definition of return values is @ref I2C_ACK. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data) +{ + int32_t result; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + if (p_obj->info.start == 1) { + p_obj->info.start = 0; + if (p_obj->info.bus_free == 1) { + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + p_obj->info.bus_free = 0; + return (-1); + } + } + } + /* Start Condition */ + I2C_start_condition(&p_obj->i2c, (uint32_t)data); + if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c))) { + p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->info.bus_free = 0; + if (I2C_status_arbitration(&p_obj->i2c)) { + return (-5); + } + return (-2); + } + } else { + I2C_write_data(&p_obj->i2c, (uint32_t)data); + } + p_obj->info.bus_free = 0; + result = wait_status(p_obj); + if (result < 0) { + return (result); + } + if (!I2C_get_ack(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Attempts to determine if the I2C bus is already in use + * @param p_obj :i2c object. + * @retval 0 :Non-active. + * @retval 1 :Active. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint8_t i2c_active_t(_i2c_t *p_obj) +{ + uint8_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_status_busy(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @param address :Slave address(7-bit) and last bit is 0. + * @param stop :Stop to be generated after the transfer is done. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and non-blocking function. + * @note Events of this function will be notified on i2c_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = (uint32_t)address; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = (uint32_t)stop; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + if ((tx_length == 0) && (rx_length != 0)) { + I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U)); + } else { + I2C_start_condition(&p_obj->i2c, (uint32_t)address); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note After error event occurred on i2c_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C as slave or master. + * @param p_obj :i2c object. + * @param enable_slave :Enable slave mode. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + disable_irq(p_obj->info.irqn); + + if (enable_slave) { + I2C_slave_init(&p_obj->i2c); + } else { + /* Slave Disable Settings. */ + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + I2C_clear_int_status(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Check to see if the I2C slave has been addressed. + * @param p_obj :i2c object. + * @retval I2C_NO_DATA :The slave has not been addressed. + * @retval I2C_READ_ADDRESSED :Read addresses. + * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support). + * @retval I2C_WRITE_ADDRESSED :Write addressed. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_receive_t(_i2c_t *p_obj) +{ + int32_t result = I2C_NO_DATA; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_slave_detected(&p_obj->i2c)) { + uint32_t sa = I2C_read_data(&p_obj->i2c); + (void)sa; + + if (!I2C_transmitter(&p_obj->i2c)) { + result = I2C_WRITE_ADDRESSED; + } else { + result = I2C_READ_ADDRESSED; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data. + * @param p_obj :i2c object. + * @param p_data :Destination address of read data. + * @param length :Number of bytes to read. + * @retval Number of read bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Read all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, ((count < (length - 1)) ? 0 : 1)); + I2C_write_data(&p_obj->i2c, 0); + if (wait_status(p_obj) < 0) { + break; + } + if (I2C_slave_detected(&p_obj->i2c)) { + return (count); + } + p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data. + * @param p_obj :i2c object. + * @param p_data :Source address of write data. + * @param length :Number of bytes to write. + * @retval Number of written bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Write all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]); + if (wait_status(p_obj) < 0) { + break; + } + if (!I2C_get_ack(&p_obj->i2c)) { + /* continue */ + } else { + break; + } + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C slave address. + * @param p_obj :i2c object. + * @param address :Address to be set. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address((int32_t)address)); +#endif /* #ifdef DEBUG */ + + I2C_set_address(&p_obj->i2c, address); +} + + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Slave and non-blocking function. + * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = 0; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = 0; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_slave_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note For a non-blocking function. + * @note After error event occurred on i2c_slave_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + I2C_slave_init(&p_obj->i2c); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__BSP_I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_t32a.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_t32a.c new file mode 100644 index 0000000..58225fa --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_t32a.c @@ -0,0 +1,1998 @@ +/** +******************************************************************************* +* @file txz_t32a.c +* @brief This file provides API functions for T32A driver. +* @version V1.0.0 +* +* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +* +* Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +******************************************************************************* +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_t32a.h" + +#if defined(__T32A_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup T32A + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ +/** + * @} + */ /* End of group T32A_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_typedef T32A Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Private_member T32A Private Member + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_member */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_fuctions TSPI Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__INLINE static int32_t check_param_mode_halt(uint32_t param); +__INLINE static int32_t check_param_mode_mode32(uint32_t param); +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param); +__INLINE static int32_t check_param_runx_sftstax(uint32_t param); +__INLINE static int32_t check_param_runx_runx(uint32_t param); +__INLINE static int32_t check_param_crx_prsclx(uint32_t param); +__INLINE static int32_t check_param_crx_clkx(uint32_t param); +__INLINE static int32_t check_param_crx_wbfx(uint32_t param); +__INLINE static int32_t check_param_crx_updnx(uint32_t param); +__INLINE static int32_t check_param_crx_reldx(uint32_t param); +__INLINE static int32_t check_param_crx_stopx(uint32_t param); +__INLINE static int32_t check_param_crx_startx(uint32_t param); +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param); +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param); +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param); +__INLINE static int32_t check_param_reldx_reld(uint32_t param); +__INLINE static int32_t check_param_imx_imsterr(uint32_t param); +__INLINE static int32_t check_param_imx_imufx(uint32_t param); +__INLINE static int32_t check_param_imx_imofx(uint32_t param); +__INLINE static int32_t check_param_imx_imx1(uint32_t param); +__INLINE static int32_t check_param_imx_imx0(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param); +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param); +#endif + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Mode HALT's parameter. + * @param param :Mode HALT's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_HALT + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_halt(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DBG_HALT_RUN: + case T32A_DBG_HALT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Mode mode32's parameter. + * @param param :Mode mode32's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_MODE32 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_mode32(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_MODE_16: + case T32A_MODE_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW Counter STOP Control's parameter. + * @param param :SW Counter STOP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_STOP: + case T32A_COUNT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW START Control's parameter. + * @param param :SW START Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTAx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstax(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_START: + case T32A_COUNT_START: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A RUN Disable/Enable Control's parameter. + * @param param :T32A RUN Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_runx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RUN_DISABLE: + case T32A_RUN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_prsclx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PRSCLx_1: + case T32A_PRSCLx_2: + case T32A_PRSCLx_8: + case T32A_PRSCLx_32: + case T32A_PRSCLx_128: + case T32A_PRSCLx_256: + case T32A_PRSCLx_512: + case T32A_PRSCLx_1024: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CLKx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_clkx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CLKx_PRSCLx: + case T32A_CLKx_INTRG: + case T32A_CLKx_TIM_RISING_EDGE: + case T32A_CLKx_TIM_TRAILING_EDGE: + case T32A_CLKx_EXTTRG_RISING_EDGE: + case T32A_CLKx_EXTTRG_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Double Buffer Disable/Enable Control's parameter. + * @param param :Double Buffer Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_WBFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_wbfx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_WBF_DISABLE: + case T32A_WBF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Up/Down Control's parameter. + * @param param :T32A Counter Up/Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_UPDNx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_updnx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_UP: + case T32A_COUNT_DOWN: + case T32A_COUNT_UPDOWN: + case T32A_COUNT_PLS: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Control's parameter. + * @param param :T32A Counter Reload Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELDx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_reldx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RELOAD_NON: + case T32A_RELOAD_INTRG: + case T32A_RELOAD_EXTTRG_RISING_EDGE: + case T32A_RELOAD_EXTTRG_TRAILING_EDGE: + case T32A_RELOAD_TIM_RISING_EDGE: + case T32A_RELOAD_TIM_TRAILING_EDGE: + case T32A_RELOAD_SYNC: + case T32A_RELOAD_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Stop Control's parameter. + * @param param :T32A Counter Stop Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STOPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_stopx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_STOP_NON: + case T32A_STOP_INTRG: + case T32A_STOP_EXTTRG_RISING_EDGE: + case T32A_STOP_EXTTRG_TRAILING_EDGE: + case T32A_STOP_TIM_RISING_EDGE: + case T32A_STOP_TIM_TRAILING_EDGE: + case T32A_STOP_SYNC: + case T32A_STOP_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Start Control's parameter. + * @param param :T32A Counter Start Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STARTx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_startx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_START_NON: + case T32A_START_INTRG: + case T32A_START_EXTTRG_RISING_EDGE: + case T32A_START_EXTTRG_TRAILING_EDGE: + case T32A_START_TIM_RISING_EDGE: + case T32A_START_TIM_TRAILING_EDGE: + case T32A_START_SYNC: + result = PARAM_OK; + break; + case T32A_START_Rsvd: + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control's parameter. + * @param param :T32AxOUTA Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCR_DISABLE: + case T32A_OCR_SET: + case T32A_OCR_CLR: + case T32A_OCR_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx1_DISABLE: + case T32A_OCRCAPx1_SET: + case T32A_OCRCAPx1_CLR: + case T32A_OCRCAPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx0_DISABLE: + case T32A_OCRCAPx0_SET: + case T32A_OCRCAPx0_CLR: + case T32A_OCRCAPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx1_DISABLE: + case T32A_OCRCMPx1_SET: + case T32A_OCRCMPx1_CLR: + case T32A_OCRCMPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx0_DISABLE: + case T32A_OCRCMPx0_SET: + case T32A_OCRCMPx0_CLR: + case T32A_OCRCMPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A1's parameter. + * @param param :T32A Capture Control Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx1_DISABLE: + case T32A_CAPMx1_INTRG: + case T32A_CAPMx1_INx0_RISING_EDGE: + case T32A_CAPMx1_INx0_TRAILING_EDGE: + case T32A_CAPMx1_INx1_RISING_EDGE: + case T32A_CAPMx1_INx1_TRAILING_EDGE: + case T32A_CAPMx1_TIM_RISING_EDGE: + case T32A_CAPMx1_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A0's parameter. + * @param param :T32A Capture Control Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx0_DISABLE: + case T32A_CAPMx0_INTRG: + case T32A_CAPMx0_INx0_RISING_EDGE: + case T32A_CAPMx0_INx0_TRAILING_EDGE: + case T32A_CAPMx0_INx1_RISING_EDGE: + case T32A_CAPMx0_INx1_TRAILING_EDGE: + case T32A_CAPMx0_TIM_RISING_EDGE: + case T32A_CAPMx0_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A0's parameter. + * @param param :T32A Timer Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx0_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A1's parameter. + * @param param :T32A Timer Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx1_MASK) { + result = PARAM_OK; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Register A's parameter. + * @param param :T32A Counter Reload Register A's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELD + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_reldx_reld(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RELDx_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Statuserr Interrupt Request MASK's parameter. + * @param param :T32A Statuserr Interrupt Request MASK's parameter. + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMSTEER + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imsterr(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMSTERR_MASK_NOREQ: + case T32A_IMSTERR_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMUFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imufx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMOFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imofx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx1_MASK_NOREQ: + case T32A_IMx1_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx0_MASK_NOREQ: + case T32A_IMx0_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA Converter1 Request control's parameter. + * @param param :T32A DMA Converter1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx2 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx2_DISABLE: + case T32A_DMAENx2_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture1 Request control's parameter. + * @param param :T32A DMA InputCapture1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx1_DISABLE: + case T32A_DMAENx1_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture0 Request control's parameter. + * @param param :T32A DMA InputCapture0 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx0_DISABLE: + case T32A_DMAENx0_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count Down Control's parameter. + * @param param :T32A Pulse Mode Count Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDN + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDN_NON0: + case T32A_PDN_NON1: + case T32A_PDN_INC0_RISING_EDGE: + case T32A_PDN_INC0_TRAILING_EDGE: + case T32A_PDN_INC1_RISING_EDGE: + case T32A_PDN_INC1_TRAILING_EDGE: + case T32A_PDN_INC0_BOTH_EDGE: + case T32A_PDN_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count UP Control's parameter. + * @param param :T32A Pulse Mode Count UP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PUP + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PUP_NON0: + case T32A_PUP_NON1: + case T32A_PUP_INC0_RISING_EDGE: + case T32A_PUP_INC0_TRAILING_EDGE: + case T32A_PUP_INC1_RISING_EDGE: + case T32A_PUP_INC1_TRAILING_EDGE: + case T32A_PUP_INC0_BOTH_EDGE: + case T32A_PUP_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Noise Filter control's parameter. + * @param param :T32A Noise Filter control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_NF + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_NF_NON: + case T32A_NF_2: + case T32A_NF_4: + case T32A_NF_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Phase 2 Pulse Direction control's parameter. + * @param param :T32A Phase 2 Pulse Direction control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDIR + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDIR_FORWARD: + case T32A_PDIR_BACKWARD: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Count Mode control's parameter. + * @param param :T32A Pulse Count Mode control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PMODE + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PMODE_PHASE_2: + case T32A_PMODE_PHASE_1: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + + + +#endif +/** + * @} + */ /* End of group T32A_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_functions + + */ +/*--------------------------------------------------*/ +/** + * @brief Mode Initialize the T32A object. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_mode_init(t32a_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); +#endif /* __DEBUG__ */ + /* Timer Mode Set */ + p_obj->p_instance->MOD = 0; + p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Initialize the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter of TimerA Mode Set */ + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); + /* Check the parameter of TimerA Run Control Set */ + check_param_runx_sftstpx(p_obj->init[type].runx.sftstp); + check_param_runx_sftstax(p_obj->init[type].runx.sftsta); + check_param_runx_runx(p_obj->init[type].runx.run); + /* Check the parameter of Counter Register Control Set */ + check_param_crx_prsclx(p_obj->init[type].crx.prscl); + check_param_crx_clkx(p_obj->init[type].crx.clk); + check_param_crx_wbfx(p_obj->init[type].crx.wbf); + check_param_crx_updnx(p_obj->init[type].crx.updn); + check_param_crx_reldx(p_obj->init[type].crx.reld); + check_param_crx_stopx(p_obj->init[type].crx.stop); + check_param_crx_startx(p_obj->init[type].crx.start); + /* Check the parameter of TimerA Output Control Set */ + check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr); + /* Check the parameter of T32AxOUTA Control Set */ + check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1); + check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0); + check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1); + check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0); + /* Check the parameter of Capture Control Set */ + check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1); + check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0); + /* Check the parameter of T32A Timer Register 0 Set */ + check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0); + /* Check the parameter of T32A Timer Register 1 Set */ + check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1); + /* Check the parameter of T32A Counter Reload Register Set */ + check_param_reldx_reld(p_obj->init[type].reldx.reld); + /* Check the parameter of Interrupt mask register Set */ + check_param_imx_imsterr(p_obj->init[type].imx.imsterr); + check_param_imx_imufx(p_obj->init[type].imx.imuf); + check_param_imx_imofx(p_obj->init[type].imx.imof); + check_param_imx_imx1(p_obj->init[type].imx.imx1); + check_param_imx_imx0(p_obj->init[type].imx.imx0); + /* Check the parameter of DMA Request register Set */ + check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2); + check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1); + check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0); +#endif + + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerA Run Control Disable */ + p_obj->p_instance->RUNA = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRA = 0; + p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerA Output Control Set */ + p_obj->p_instance->OUTCRA0 = 0; + p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTA Control Set */ + p_obj->p_instance->OUTCRA1 = 0; + p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register A0 Set */ + p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register A1 Set */ + p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDA = 0; + p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMA = 0; + p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAA = 0; + p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerA Run Control Set */ + p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERB: + /* Timer B */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerB Run Control Disable */ + p_obj->p_instance->RUNB = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRB = 0; + p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerB Output Control Set */ + p_obj->p_instance->OUTCRB0 = 0; + p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTB Control Set */ + p_obj->p_instance->OUTCRB1 = 0; + p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register B0 Set */ + p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register B1 Set */ + p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDB = 0; + p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMB = 0; + p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAB = 0; + p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerB Run Control Set */ + p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERC: + /* Timer C */ + if (p_obj->init_mode.mode.mode != T32A_MODE_32) { + result = TXZ_ERROR; + return (result); + } + /* TimerC Run Control Disable */ + p_obj->p_instance->RUNC = 0; +#ifdef __DEBUG__ + /* Pulse Count Control register Set */ + check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn); + check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup); + check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf); + check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir); + check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode); +#endif + /* Counter Register Control Set */ + p_obj->p_instance->CRC = 0; + p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerC Output Control Set */ + p_obj->p_instance->OUTCRC0 = 0; + p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTC Control Set */ + p_obj->p_instance->OUTCRC1 = 0; + p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register C0 Set */ + p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register C1 Set */ + p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDC = 0; + p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld; + /* TimerC Capture Control Set */ + p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMC = 0; + p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAC = 0; + p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* Pulse Count Control register Set */ + p_obj->p_instance->PLSCR = 0; + p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \ + p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode); + /* TimerC Run Control Set */ + p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* Timer C */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A RUN */ + p_obj->p_instance->RUNA |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer B RUN */ + p_obj->p_instance->RUNB |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C RUN */ + p_obj->p_instance->RUNC |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A Stop */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B Stop */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* SW Counter Stop & Timer C Stop */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A SW Counter start */ + p_obj->p_instance->RUNA |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer SW Counter start */ + p_obj->p_instance->RUNB |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C SW Counter start */ + p_obj->p_instance->RUNC |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* TimerA SW Counter Stop */ + p_obj->p_instance->RUNA = T32A_COUNT_STOP; + break; + case T32A_TIMERB: + /* Timer B SW Counter Stop */ + p_obj->p_instance->RUNB = T32A_COUNT_STOP; + break; + case T32A_TIMERC: + /* Timer C SW Counter Stop */ + p_obj->p_instance->RUNC = T32A_COUNT_STOP; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Setting + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param num :T32A Register Number. : Use @ref t32_regnum_t + * @param value :Setting Value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (num == T32A_REG0) { + p_obj->p_instance->RGA0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGA1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDA = value; + } + break; + case T32A_TIMERB: + /* Timer B */ + if (num == T32A_REG0) { + p_obj->p_instance->RGB0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGB1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDB = value; + } + break; + case T32A_TIMERC: + /* Timer C */ + if (num == T32A_REG0) { + p_obj->p_instance->RGC0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGC1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDC = value; + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Read + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param p_val :Save area for register value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val) +{ + TXZ_Result result = TXZ_SUCCESS; + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_val = p_obj->p_instance->TMRA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_val = p_obj->p_instance->TMRB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_val = p_obj->p_instance->TMRC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. | + * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. | + * + * @param p_obj :T32A object. + * @param p_status :Save area for status. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_status = p_obj->p_instance->STA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_status = p_obj->p_instance->STB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_status = p_obj->p_instance->STC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for Timer interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Calculate timer value to set timer register. + * @param p_value: time value store pointer. + * @param time: The require period which the uint is us. + * @param prescaler: System Clock Freq + * @param prscl: Select the division for source clock @ref T32A_PRSCLx. + * @retval the value set to Tmrb timer register. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) +{ + TXZ_Result result = TXZ_SUCCESS; + uint64_t denominator; + uint64_t numerator; + uint32_t div; + + /* div */ + switch (prscl) { + case T32A_PRSCLx_1: + div = 1; + break; + case T32A_PRSCLx_2: + div = 2; + break; + case T32A_PRSCLx_8: + div = 8; + break; + case T32A_PRSCLx_32: + div = 32; + break; + case T32A_PRSCLx_128: + div = 128; + break; + case T32A_PRSCLx_256: + div = 256; + break; + case T32A_PRSCLx_512: + div = 512; + break; + case T32A_PRSCLx_1024: + div = 1024; + break; + default: + div = 1; + break; + } + /*-----------------------------------------------*/ + /* "1"counter (s) = 1 / fs */ + /* "1"counter (s) = 1 / (prescaler / div) */ + /* "1"counter (us) = (10^6) / (prescaler / div) */ + /* "1"counter (us) = ((10^6) * div)/prescaler */ + /* "x"counter (us) = time */ + /*-----------------------------------------------*/ + /* x : time = 1 : ((10^6) * div)/prescaler */ + /*-----------------------------------------------*/ + /* x = time / (((10^6) * div)/prescaler) */ + /* = (prescaler * time) / ((10^6) * div) */ + /*-----------------------------------------------*/ + denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time)); + numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div); + denominator = (uint64_t)(denominator / numerator); + /* result */ + if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF))) { + result = TXZ_ERROR; + } else { + *p_value = (uint32_t)denominator; + } + + return (result); +} + +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__T32A_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_tspi.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_tspi.c new file mode 100644 index 0000000..b84b926 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_tspi.c @@ -0,0 +1,2895 @@ +/** + ******************************************************************************* + * @file txz_tspi.c + * @brief This file provides API functions for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_tspi.h" + +#if defined(__TSPI_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup TSPI + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ +/** + * @name TSPI NULL Pointer + * @brief Null Pointer for TSPI + * @{ + */ +#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ +/** + * @} + */ /* End of name TSPI NULL Pointer */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name FIFO Max Num. + * @brief Transfer's/Receive's FIFO Max Num. + * @{ + */ +#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ +#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ +/** + * @} + */ /* End of name FIFO Max Num */ + +/** + * @name TSPIxDR_MASK Macro Definition. + * @brief TSPIxDR_MASK Macro Definition. + * @{ + */ +/* DR */ +#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of name TSPIxDR_MASK Macro Definition */ + +/** + * @name TSPI _DATA_LENGTH Macro Definition. + * @brief TSPI DATA LENGTH Macro Definition. + * @{ + */ +#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ +#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ +#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ +#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ +#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ +#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ +#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ +#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ +#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ +#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ +#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ +#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ +#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ +#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ +#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ +#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ +#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ +#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ +#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ +#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ +#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ +#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ +#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ +#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ +#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ +/** + * @} + */ /* End of name TSPI _DATA_LENGTH Macro Definition */ +/** + * @} + */ /* End of group TSPI_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group TSPI_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_typedef TSPI Private Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief TSPI mask array. +*/ +/*----------------------------------*/ +static uint32_t mask[32] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TSPI_DR_8BIT_MASK, + TSPI_DR_9BIT_MASK, + TSPI_DR_10BIT_MASK, + TSPI_DR_11BIT_MASK, + TSPI_DR_12BIT_MASK, + TSPI_DR_13BIT_MASK, + TSPI_DR_14BIT_MASK, + TSPI_DR_15BIT_MASK, + TSPI_DR_16BIT_MASK, + TSPI_DR_17BIT_MASK, + TSPI_DR_18BIT_MASK, + TSPI_DR_19BIT_MASK, + TSPI_DR_20BIT_MASK, + TSPI_DR_21BIT_MASK, + TSPI_DR_22BIT_MASK, + TSPI_DR_23BIT_MASK, + TSPI_DR_24BIT_MASK, + TSPI_DR_25BIT_MASK, + TSPI_DR_26BIT_MASK, + TSPI_DR_27BIT_MASK, + TSPI_DR_28BIT_MASK, + TSPI_DR_29BIT_MASK, + TSPI_DR_30BIT_MASK, + TSPI_DR_31BIT_MASK +}; + +/** + * @} + */ /* End of group TSPI_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_fuctions TSPI Private Fuctions + * @{ + */ + +#ifdef __DEBUG__ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param); +__INLINE static int32_t check_param_trgen_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); +__INLINE static int32_t check_param_transmit_master(uint32_t param); +__INLINE static int32_t check_param_transmit_mode(uint32_t param); +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param); +__INLINE static int32_t check_param_frame_range(uint32_t param); +__INLINE static int32_t check_param_idle_imp(uint32_t param); +__INLINE static int32_t check_param_underrun_imp(uint32_t param); +__INLINE static int32_t check_param_rxdly_value(uint32_t param); +__INLINE static int32_t check_param_tx_fill_level(uint32_t param); +__INLINE static int32_t check_param_rx_fill_level(uint32_t param); +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_err_int(uint32_t param); +__INLINE static int32_t check_param_tx_dma_int(uint32_t param); +__INLINE static int32_t check_param_rx_dma_int(uint32_t param); +__INLINE static int32_t check_param_input_clock(uint32_t param); +__INLINE static int32_t check_param_input_divider(uint32_t param); +__INLINE static int32_t check_param_data_direction(uint32_t param); +__INLINE static int32_t check_param_frame_length(uint32_t param); +__INLINE static int32_t check_param_frame_interval(uint32_t param); +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param); +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param); +__INLINE static int32_t check_param_min_idle_time(uint32_t param); +__INLINE static int32_t check_param_clock_delay(uint32_t param); +__INLINE static int32_t check_param_negate_delay(uint32_t param); +__INLINE static int32_t check_param_parity_enable(uint32_t param); +__INLINE static int32_t check_param_parity_bit(uint32_t param); +__INLINE static int32_t check_param_sect_mode(uint32_t param); +__INLINE static int32_t check_param_sectl0_value(uint32_t param); +__INLINE static int32_t check_param_sectl1_value(uint32_t param); +__INLINE static int32_t check_param_sectl2_value(uint32_t param); +__INLINE static int32_t check_param_sectl3_value(uint32_t param); +#endif + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit frame infinity Enable's parameter. + * @param param :Transmit frame infinity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Infinity_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INF_DISABLE: + case TSPI_INF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Trgen Enable's parameter. + * @param param :Trgen Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Trigger_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_trgen_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRGEN_DISABLE: + case TSPI_TRGEN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Enable's parameter. + * @param param :Transmit Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRXE_DISABLE: + case TSPI_TRXE_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Mode's parameter. + * @param param :Transmit Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SPI_MODE: + case TSPI_SIO_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Master/Slave parameter. + * @param param :Transmit Master/Slave parameter (Only support Master mode) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Operation_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_master(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MASTER_OPERATION: + case TSPI_SLAVE_OPERATION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transfer Mode's parameter. + * @param param :Transfer Mode's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TWO_WAY: + case TSPI_TX_ONLY: + case TSPI_RX_ONLY: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Sel Select's parameter. + * @param param :Transmit Sel Select's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_CSSEL_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_ENABLE: + case TSPI_TSPIxCS1_ENABLE: + case TSPI_TSPIxCS2_ENABLE: + case TSPI_TSPIxCS3_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Frame Range's parameter. + * @param param :TransmitFrame Range's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Frame_Range + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_range(uint32_t param) + +{ + int32_t result = PARAM_NG; + + if ((TSPI_TRANS_RANGE_CONTINUE == param) || (TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the IDLE Output Value's parameter. + * @param param :IDLE Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_IDLE_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TIDLE_Hiz: + case TSPI_TIDLE_LAST_DATA: + case TSPI_TIDLE_LOW: + case TSPI_TIDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_underrun_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TXDEMP_LOW: + case TSPI_TXDEMP_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rxdly_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RXDLY_1CLK: + case TSPI_RXDLY_2CLK: + case TSPI_RXDLY_3CLK: + case TSPI_RXDLY_4CLK: + case TSPI_RXDLY_5CLK: + case TSPI_RXDLY_6CLK: + case TSPI_RXDLY_7CLK: + case TSPI_RXDLY_8CLK: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level's parameter. + * @param param :Tx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FILL_LEVEL_0: + case TSPI_TX_FILL_LEVEL_1: + case TSPI_TX_FILL_LEVEL_2: + case TSPI_TX_FILL_LEVEL_3: + case TSPI_TX_FILL_LEVEL_4: + case TSPI_TX_FILL_LEVEL_5: + case TSPI_TX_FILL_LEVEL_6: + case TSPI_TX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FILL_LEVEL_1: + case TSPI_RX_FILL_LEVEL_2: + case TSPI_RX_FILL_LEVEL_3: + case TSPI_RX_FILL_LEVEL_4: + case TSPI_RX_FILL_LEVEL_5: + case TSPI_RX_FILL_LEVEL_6: + case TSPI_RX_FILL_LEVEL_7: + case TSPI_RX_FILL_LEVEL_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FIFO_INT_DISABLE: + case TSPI_TX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_INT_DISABLE: + case TSPI_TX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFIFOInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FIFO_INT_DISABLE: + case TSPI_RX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_INT_DISABLE: + case TSPI_RX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ErrorInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_err_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_ERR_INT_DISABLE: + case TSPI_ERR_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx DMA Interrupt's parameter. + * @param param :Tx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_DMA_INT_DISABLE: + case TSPI_TX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx DMA Interrupt's parameter. + * @param param :Rx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_DMA_INT_DISABLE: + case TSPI_RX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Input Clock's parameter. + * @param param :Input Clock's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_clock(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_CLOCK_0: + case TSPI_BR_CLOCK_1: + case TSPI_BR_CLOCK_2: + case TSPI_BR_CLOCK_4: + case TSPI_BR_CLOCK_8: + case TSPI_BR_CLOCK_16: + case TSPI_BR_CLOCK_32: + case TSPI_BR_CLOCK_64: + case TSPI_BR_CLOCK_128: + case TSPI_BR_CLOCK_256: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Baudrate Divider's parameter. + * @param param :Baudrate Divider's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_divider(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_DIVIDER_16: + case TSPI_BR_DIVIDER_1: + case TSPI_BR_DIVIDER_2: + case TSPI_BR_DIVIDER_3: + case TSPI_BR_DIVIDER_4: + case TSPI_BR_DIVIDER_5: + case TSPI_BR_DIVIDER_6: + case TSPI_BR_DIVIDER_7: + case TSPI_BR_DIVIDER_8: + case TSPI_BR_DIVIDER_9: + case TSPI_BR_DIVIDER_10: + case TSPI_BR_DIVIDER_11: + case TSPI_BR_DIVIDER_12: + case TSPI_BR_DIVIDER_13: + case TSPI_BR_DIVIDER_14: + case TSPI_BR_DIVIDER_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_DIRECTION_LSB: + case TSPI_DATA_DIRECTION_MSB: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter (Only support 8bit DATA) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_length(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_LENGTH_8: + case TSPI_DATA_LENGTH_9: + case TSPI_DATA_LENGTH_10: + case TSPI_DATA_LENGTH_11: + case TSPI_DATA_LENGTH_12: + case TSPI_DATA_LENGTH_13: + case TSPI_DATA_LENGTH_14: + case TSPI_DATA_LENGTH_15: + case TSPI_DATA_LENGTH_16: + case TSPI_DATA_LENGTH_17: + case TSPI_DATA_LENGTH_18: + case TSPI_DATA_LENGTH_19: + case TSPI_DATA_LENGTH_20: + case TSPI_DATA_LENGTH_21: + case TSPI_DATA_LENGTH_22: + case TSPI_DATA_LENGTH_23: + case TSPI_DATA_LENGTH_24: + case TSPI_DATA_LENGTH_25: + case TSPI_DATA_LENGTH_26: + case TSPI_DATA_LENGTH_27: + case TSPI_DATA_LENGTH_28: + case TSPI_DATA_LENGTH_29: + case TSPI_DATA_LENGTH_30: + case TSPI_DATA_LENGTH_31: + case TSPI_DATA_LENGTH_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Frame Interval's parameter. + * @param param :Frame Interval's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Frame_Interval_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_interval(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INTERVAL_TIME_0: + case TSPI_INTERVAL_TIME_1: + case TSPI_INTERVAL_TIME_2: + case TSPI_INTERVAL_TIME_3: + case TSPI_INTERVAL_TIME_4: + case TSPI_INTERVAL_TIME_5: + case TSPI_INTERVAL_TIME_6: + case TSPI_INTERVAL_TIME_7: + case TSPI_INTERVAL_TIME_8: + case TSPI_INTERVAL_TIME_9: + case TSPI_INTERVAL_TIME_10: + case TSPI_INTERVAL_TIME_11: + case TSPI_INTERVAL_TIME_12: + case TSPI_INTERVAL_TIME_13: + case TSPI_INTERVAL_TIME_14: + case TSPI_INTERVAL_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS3 Polarity's parameter. + * @param param :TTSPIxCS3 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS3_NEGATIVE: + case TSPI_TSPIxCS3_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS2 Polarity's parameter. + * @param param :TTSPIxCS2 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS2_NEGATIVE: + case TSPI_TSPIxCS2_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS1 Polarity's parameter. + * @param param :TTSPIxCS1 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS1_NEGATIVE: + case TSPI_TSPIxCS1_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS0 Polarity's parameter. + * @param param :TTSPIxCS0 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_NEGATIVE: + case TSPI_TSPIxCS0_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Polarity's parameter. + * @param param :Serial Clock Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_1ST_EDGE: + case TSPI_SERIAL_CK_2ND_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock IDLE Polarity's parameter. + * @param param :Serial Clock IDLE Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_IDLE_LOW: + case TSPI_SERIAL_CK_IDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Minimum IDLE Time's parameter. + * @param param :Minimum IDLE Time's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Minimum_IDLE_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_min_idle_time(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MIN_IDLE_TIME_1: + case TSPI_MIN_IDLE_TIME_2: + case TSPI_MIN_IDLE_TIME_3: + case TSPI_MIN_IDLE_TIME_4: + case TSPI_MIN_IDLE_TIME_5: + case TSPI_MIN_IDLE_TIME_6: + case TSPI_MIN_IDLE_TIME_7: + case TSPI_MIN_IDLE_TIME_8: + case TSPI_MIN_IDLE_TIME_9: + case TSPI_MIN_IDLE_TIME_10: + case TSPI_MIN_IDLE_TIME_11: + case TSPI_MIN_IDLE_TIME_12: + case TSPI_MIN_IDLE_TIME_13: + case TSPI_MIN_IDLE_TIME_14: + case TSPI_MIN_IDLE_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Delay's parameter. + * @param param :Serial Clock Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_DELAY_1: + case TSPI_SERIAL_CK_DELAY_2: + case TSPI_SERIAL_CK_DELAY_3: + case TSPI_SERIAL_CK_DELAY_4: + case TSPI_SERIAL_CK_DELAY_5: + case TSPI_SERIAL_CK_DELAY_6: + case TSPI_SERIAL_CK_DELAY_7: + case TSPI_SERIAL_CK_DELAY_8: + case TSPI_SERIAL_CK_DELAY_9: + case TSPI_SERIAL_CK_DELAY_10: + case TSPI_SERIAL_CK_DELAY_11: + case TSPI_SERIAL_CK_DELAY_12: + case TSPI_SERIAL_CK_DELAY_13: + case TSPI_SERIAL_CK_DELAY_14: + case TSPI_SERIAL_CK_DELAY_15: + case TSPI_SERIAL_CK_DELAY_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Negate Delay's parameter. + * @param param :Negate Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Negate_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_negate_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_NEGATE_1: + case TSPI_NEGATE_2: + case TSPI_NEGATE_3: + case TSPI_NEGATE_4: + case TSPI_NEGATE_5: + case TSPI_NEGATE_6: + case TSPI_NEGATE_7: + case TSPI_NEGATE_8: + case TSPI_NEGATE_9: + case TSPI_NEGATE_10: + case TSPI_NEGATE_11: + case TSPI_NEGATE_12: + case TSPI_NEGATE_13: + case TSPI_NEGATE_14: + case TSPI_NEGATE_15: + case TSPI_NEGATE_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_DISABLE: + case TSPI_PARITY_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_BIT_ODD: + case TSPI_PARITY_BIT_EVEN: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sect Mode's parameter. + * @param param :Sect Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_MODE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sect_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SECT_MODE_FRAME: + case TSPI_SECT_MODE_SECT: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl0 bit length's parameter. + * @param param :Sectl0 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl0_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + /* 1~32:setting enable */ + if ((param >= TSPI_SECT_VALUE_1) && (param <= TSPI_SECT_VALUE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl1 bit length's parameter. + * @param param :Sectl1 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl1_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl1_value = (param >> 8); + + /* 1~32:setting enable */ + if ((sectl1_value >= TSPI_SECT_VALUE_1) && (sectl1_value <= TSPI_SECT_VALUE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl2 bit length's parameter. + * @param param :Sectl2 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl2_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl2_value = (param >> 16); + + /* 0~32:setting enable */ + if (sectl2_value <= TSPI_SECT_VALUE_MAX) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl3 bit length's parameter. + * @param param :Sectl3 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl3_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl3_value = (param >> 24); + + /* 0~32:setting enable */ + if (sectl3_value <= TSPI_SECT_VALUE_MAX) { + result = PARAM_OK; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group TSPI_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_init(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxCR1. */ + assert_param(check_param_frameinf_enable(p_obj->init.cnt1.inf)); + assert_param(check_param_trgen_enable(p_obj->init.cnt1.trgen)); + assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); + assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); + assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); + assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); + assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); + assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); + /* Check the parameter of TTSPIxCR2 */ + assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); + assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); + assert_param(check_param_rxdly_value(p_obj->init.cnt2.rxdly)); + assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); + assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); + assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); + assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); + assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); + assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); + assert_param(check_param_err_int(p_obj->init.cnt2.interr)); + assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); + assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); + /* Check the parameter of TTSPIxBR */ + assert_param(check_param_input_clock(p_obj->init.brd.brck)); + assert_param(check_param_input_divider(p_obj->init.brd.brs)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); + /* Check the parameter of TSPISECTCR0 */ + assert_param(check_param_sect_mode(p_obj->init.scr0.sect)); + /* Check the parameter of TSPISECTCR1 */ + assert_param(check_param_sectl0_value(p_obj->init.scr1.sectl0)); + assert_param(check_param_sectl1_value(p_obj->init.scr1.sectl1)); + assert_param(check_param_sectl2_value(p_obj->init.scr1.sectl2)); + assert_param(check_param_sectl3_value(p_obj->init.scr1.sectl3)); +#endif + + + /* TSPI Software Reset */ + p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); + p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE);; + + /* Wait for 2 clocks of reset completion */ + __NOP(); + __NOP(); + + /* Enable the selected TSPI peripheral (TSPIE)*/ + p_obj->p_instance->CR0 = TSPI_ENABLE; + + /* Control1 Register1 Set*/ + p_obj->p_instance->CR1 = 0x00001C01U; + p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ + p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims | p_obj->init.cnt1.trgen | p_obj->init.cnt1.inf); + /* Control2 Register Set */ + p_obj->p_instance->CR2 = 0x00E10100U; + p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ + p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe | p_obj->init.cnt2.inttxwe | \ + p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare); + + /* Control3 Register is FIFO clear, do nothing */ + + /* Baudrate Register Set */ + p_obj->p_instance->BR = 0U; + p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); + + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = 0x8800C400U; + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = 0U; + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + + /* Sect control0 Register Set*/ + p_obj->p_instance->SECTCR0 = 0U; + p_obj->p_instance->SECTCR0 = p_obj->init.scr0.sect; + + /* Sect control1 Register Set*/ + p_obj->p_instance->SECTCR1 = 0x00000101U; + p_obj->p_instance->SECTCR1 = (p_obj->init.scr1.sectl3 | p_obj->init.scr1.sectl2 | p_obj->init.scr1.sectl1 | p_obj->init.scr1.sectl0); + + /* not created */ + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_deinit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Disable the selected TSPI peripheral */ + p_obj->p_instance->CR0 = TSPI_DISABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data.. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + + /* Transmit data check*/ + if ((p_info->tx8.p_data == TSPI_NULL) || (p_info->tx8.num == 0)) { + p_obj->errcode = DATABUFEMPERR; + result = TXZ_ERROR; + return (result); + } + + /* FIFO Cear */ + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + /* Transmit Data write to D ata Register */ + while (p_info->tx8.num > 0) { + /* Check the current fill level */ + if (((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { + *((__IO uint8_t *)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); + p_info->tx8.num--; + /* check complete transmit */ + if ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } else { + /* Enable TSPI Transmission Control */ + if (p_info->tx8.num == 0) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + return (result); + } else { + /* Next transmit data sending */ + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + } + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + + } + /* check complete transmit */ + while ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + /* Check Error Flag */ + if ((tspi_get_error(p_obj, &err)) != TXZ_ERROR) { + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + } else { + result = TXZ_ERROR; + return (result); + } + if (p_obj->errcode == NOERROR) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + uint32_t count = 0; + uint32_t index = 0; + + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + /* Transmit data check*/ + if ((p_info->rx8.p_data == TSPI_NULL) || (p_info->rx8.num == 0)) { + result = TXZ_ERROR; + return (result); + } + count = p_info->rx8.num; + + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + while (timeout > 0) { + /* Wait until Receive Complete Flag is set to receive data */ + if ((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { + while (count > 0) { + /* Check the remain data exist */ + if ((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { + p_info->rx8.p_data[index] = (*((__IO uint8_t *)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); + count--; + index++; + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + } + /* Receive Complete Flag is clear */ + p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; + /* FIFO Cear */ + p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + timeout--; + } + } + /* Timeout management */ + p_obj->errcode = TIMEOUTERR; + + /* Check Error Flag set */ + if ((tspi_get_error(p_obj, &err)) != TXZ_ERROR) { + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + } else { + result = TXZ_ERROR; + return (result); + } + + result = TXZ_ERROR; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + + + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data DMA. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Write to DMATE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR2 & TSPI_TX_DMA_INT_ENABLE) != TSPI_TX_DMA_INT_ENABLE) { + p_obj->p_instance->CR2 |= TSPI_TX_DMA_INT_ENABLE; + } + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data DMA. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Write to DMARE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR2 & TSPI_RX_DMA_INT_ENABLE) != TSPI_RX_DMA_INT_ENABLE) { + p_obj->p_instance->CR2 |= TSPI_RX_DMA_INT_ENABLE; + } + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_transmit(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + /* Check the transmit's end flag. */ + if (((status & TSPI_TX_DONE_FLAG) == TSPI_TX_DONE) || + ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Get the empty num in FIFO. */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + if (tlvl == TRANSFER_FIFO_MAX_NUM) { + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.tx_allign = 8; + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.tx_allign = 16; + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else { + /* 17 - 32 bit */ + p_obj->transmit.tx_allign = 32; + if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } +#if 0 + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; +#endif + } + } +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_receive(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.rx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + /* Check the receive's end flag. */ + if (((status & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) || + ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) { + /* Read FIFO fill level. */ + __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); + /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ + if (rlvl > RECEIVE_FIFO_MAX_NUM) { + rlvl = RECEIVE_FIFO_MAX_NUM; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->receive.rx_allign) { + case 8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); + break; + case 16: + *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + case 32: + *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + tspi_receive_t param; + + switch (p_obj->receive.rx_allign) { + case 8: + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + break; + case 16: + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + break; + case 32: + param.rx32.p_data = p_obj->receive.info.rx32.p_data; + param.rx32.num = rlvl; + break; + default: + /* no process */ + break; + } + /* Call the receive handler with SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_error_irq_handler(tspi_t *p_obj) +{ + __IO uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current TSPIxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- TSPIxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with FAILURE. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* UNDERERR */ + if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) { + err = TXZ_ERROR; + } + /* OVRERR */ + if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + /* Call the receive handler with FAILURE. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); + } + } + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Data Format setting + * @param p_obj :TSPI object. + * @retval - + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_format(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); +#endif + + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | + * | 30-24 | - | - | + * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | + * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | + * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | + * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | + * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | + * | 15-8 | - | - | + * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | + * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | + * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | + * + * @param p_obj :TSPI object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_status is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI state */ + *p_status = p_obj->p_instance->SR; + if (p_status != TSPI_NULL) { + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI ERROR */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Error information clear. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_error_clear(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + p_obj->p_instance->ERR = (TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_transmit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_receive(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + + +/** + * @} + */ /* End of group TSPI_Exported_functions */ + +/** + * @} + */ /* End of group TSPI */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__TSPI_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_uart.c new file mode 100644 index 0000000..95f315a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/Periph_driver/src/txz_uart.c @@ -0,0 +1,1805 @@ +/** + ******************************************************************************* + * @file txz_uart.c + * @brief This file provides API functions for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_uart_include.h" +#include "txz_uart.h" + +#if defined(__UART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/** + * @defgroup UART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */ + +#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL + +#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */ +#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group UART_BourateConfig */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_typedef UART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_fuctions UART Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param); +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param); +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param); +__STATIC_INLINE int32_t check_param_division(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef __DEBUG__ */ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level); +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level); +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Noize Fileter's parameter. + * @param param :Noize fileter's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_NOISE_FILTER_NON: + case UART_NOISE_FILTER_2_T0: + case UART_NOISE_FILTER_4_T0: + case UART_NOISE_FILTER_8_T0: + case UART_NOISE_FILTER_2_CLOCK: + case UART_NOISE_FILTER_3_CLOCK: + case UART_NOISE_FILTER_4_CLOCK: + case UART_NOISE_FILTER_5_CLOCK: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_CTS_DISABLE: + case UART_CTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RTS_DISABLE: + case UART_RTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Complementation's parameter. + * @param param :Data Complementation's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_COMPLEMENTION_DISABLE: + case UART_DATA_COMPLEMENTION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_DIRECTION_LSB: + case UART_DATA_DIRECTION_MSB: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_STOP_BIT_1: + case UART_STOP_BIT_2: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_BIT_ODD: + case UART_PARITY_BIT_EVEN: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_DISABLE: + case UART_PARITY_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_LENGTH_7: + case UART_DATA_LENGTH_8: + case UART_DATA_LENGTH_9: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/ +#if 0 + if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX)) +#else + if (param <= UART_TX_FILL_RANGE_MAX) +#endif + { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX)) { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_FIFO_INT_DISABLE: + case UART_TX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_INT_DISABLE: + case UART_TX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_FIFO_INT_DISABLE: + case UART_RX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_INT_DISABLE: + case UART_RX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_ERR_INT_DISABLE: + case UART_ERR_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Prescaler's parameter. + * @param param :Prescaler's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PLESCALER_1: + case UART_PLESCALER_2: + case UART_PLESCALER_4: + case UART_PLESCALER_8: + case UART_PLESCALER_16: + case UART_PLESCALER_32: + case UART_PLESCALER_64: + case UART_PLESCALER_128: + case UART_PLESCALER_256: + case UART_PLESCALER_512: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Division's parameter. + * @param param :Division's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_division(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DIVISION_DISABLE: + case UART_DIVISION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX)) +#else + if (param <= UART_RANGE_K_MAX) +#endif + { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX)) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param != 0) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param >= 8) { + result = UART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef __DEBUG__ */ + +/*--------------------------------------------------*/ +/** + * @brief Convert Tx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result = (level << 12); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Convert Rx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result; + + if (level < 8) { + result = (level << 8); + } else { + result = 0; + } + + return (result); +} + +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi Tx */ + uint32_t prescaler = (p_clk->prsel >> 4); + + work64 = (uint64_t)((uint64_t)1 << prescaler); + tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + tx64 /= work64; + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * UART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group UART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_init(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_prescaler(p_obj->init.clock.prsel)); + assert_param(check_param_division(p_obj->init.boudrate.ken)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.inttx)); + assert_param(check_param_rx_int(p_obj->init.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx)); + assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level)); + assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level)); + assert_param(check_param_noize_filter(p_obj->init.nf)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_data_complemention(p_obj->init.iv)); + assert_param(check_param_data_direction(p_obj->init.dir)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* SW Reset */ + /*------------------------------*/ + /*--- UARTxSWRST ---*/ + /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */ + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /* Write to SWRST(=10). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10; + /* Write to SWRST(=01). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01; + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /*------------------------------*/ + /* FIFO Clear */ + /*------------------------------*/ + /*--- UARTxFIFOCLR ---*/ + /* Write to TFCLR(=1), and RFCLR(=1) */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- UARTxCLK ---*/ + /* Reflecting "p_obj->init.clk" */ + p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK); + /*--- UARTxBRD ---*/ + /* Reflecting "p_obj->init.brd" */ + /* Be careful, BRK needs to bit shit. */ + { + uint32_t brk = (p_obj->init.boudrate.brk << 16); + p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn); + } + /*--- UARTxCR0 ---*/ + /* Reflecting "p_obj->init.cnt0" */ + p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm | + p_obj->init.hcc | p_obj->init.lbc | + p_obj->init.nf | p_obj->init.ctse | + p_obj->init.rtse | p_obj->init.iv | + p_obj->init.dir | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe | + p_obj->init.sm); + /*--- UARTxCR1 ---*/ + /* Reflecting "p_obj->init.cnt1" */ + /* Fixed: "DMATE=0", "DMARE=0". */ + /* Be careful, "TIL", "RIL" need to bit shit. */ + p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) | + convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) | + p_obj->init.txfifo.inttx | p_obj->init.inttx | + p_obj->init.rxfifo.intrx | p_obj->init.intrx | + p_obj->init.interr); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_deinit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*--- UARTxCR1 ---*/ + p_obj->p_instance->CR1 = 0; + /*--- UARTxCR0 ---*/ + p_obj->p_instance->CR0 = 0; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_transmit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR); + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR); + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Return RXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_receive(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the receive's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */ + p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR | + UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Return TXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK)); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx8.num)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + } else { + /* 7/8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /*--- UARTxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Empty FIFO Num */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx8.num)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + } else { + /* 7/8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_transmit_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*---- UARTxSR ---*/ + /* Check the transmit's end flag. */ + if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) || + ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + uint32_t tlvl = (status & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Get the empty num in FIFO. */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + if (tlvl == UART_TX_FIFO_MAX) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + default: + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_receive_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /* Check the receive's end flag. */ + if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) || + ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED)) { + /* Read FIFO fill level. */ + uint32_t rlvl = (status & UARTxSR_RLVL_MASK); + /* FIFO Max = UART_RX_FIFO_MAX */ + if (rlvl > UART_RX_FIFO_MAX) { + rlvl = UART_RX_FIFO_MAX; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK); + break; + case UART_DATA_LENGTH_8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK); + break; + case UART_DATA_LENGTH_7: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + uart_receive_t param; + + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + } else { + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + } + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_error_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current UARTxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR) { + /*------------------------------*/ + /* Transmit Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_ERROR. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVRERR */ + if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR) { + err = TXZ_ERROR; + } + /* FERR */ + if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR) { + err = TXZ_ERROR; + } + /* BERR */ + if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. | + * | 30-16 | - | - | + * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. | + * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. | + * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. | + * | 12 | - | - | + * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel | + * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. | + * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel | + * | 4 | - | - | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel | + * + * @param p_obj :UART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Read current UARTxSR. */ + *p_status = p_obj->p_instance->SR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-5 | - | - | + * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. | + * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. | + * + * @param p_obj :UART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Read current UARTxERR. */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_clk)); + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of UARTxCLK. */ +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi Tx ---*/ + uint32_t prescaler = (p_clk->prsel >> 4); + + work = (uint64_t)((uint64_t)1 << prescaler); + tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + tx /= work; + + /*--- N+(64-K)/64 division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx + (uint64_t)k; + if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT)) { + work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { + uint64_t workRange = 0; + + /* Verification */ + if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } + } +#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PeripheralNames.h new file mode 100644 index 0000000..532e9d6 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PeripheralNames.h @@ -0,0 +1,193 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + SERIAL_2, + SERIAL_3, + SERIAL_4, + SERIAL_5, + SERIAL_6, + SERIAL_7, + INVALID_SERIAL = (int)NC +} UARTName; + +typedef enum { + DAC_0 = 0, + DAC_1, + INVALID_DAC = (int)NC +} DACName; + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11, + PWM_12, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + ADC_A0 = 0, + ADC_A1, + ADC_A2, + ADC_A3, + ADC_A4, + ADC_A5, + ADC_A6, + ADC_A7, + ADC_A8, + ADC_A9, + ADC_A10, + ADC_A11, + ADC_A12, + ADC_A13, + ADC_A14, + ADC_A15, + ADC_A16, + ADC_A17, + ADC_A18, + ADC_A19, + ADC_A20, + ADC_A21, + ADC_A22, + ADC_A23, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3, + I2C_4, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + SPI_0 = 0, + SPI_1, + SPI_2, + SPI_3, + SPI_4, + SPI_5, + SPI_6, + SPI_7, + SPI_8, + INVALID_SPI = (int)NC +} SPIName; + +typedef enum { + GPIO_IRQ_0 = 0, + GPIO_IRQ_1, + GPIO_IRQ_2, + GPIO_IRQ_3, + GPIO_IRQ_4, + GPIO_IRQ_5, + GPIO_IRQ_6, + GPIO_IRQ_7, + GPIO_IRQ_8, + GPIO_IRQ_9, + GPIO_IRQ_A, + GPIO_IRQ_B, + GPIO_IRQ_C, + GPIO_IRQ_D, + GPIO_IRQ_E, + GPIO_IRQ_F, + INVALID_GPIO_IRQ = (int)NC +} GPIO_IRQName; + +// DAP UART +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +#define SERIAL_TX PU0 +#define SERIAL_RX PU1 + +#define STDIO_UART SERIAL_4 + +// TxD RxD +#define MBED_UART0 PE3, PE2 +#define MBED_UART1 PH1, PH0 +#define MBED_UART2 PG1, PG0 +#define MBED_UART3 PU7, PU6 +#define MBED_UART4 PM1, PM0 +#define MBED_UART5 PJ1, PJ0 +#define MBED_UART6 PG4, PG5 +#define MBED_UART7 PJ6, PJ7 +#define MBED_UARTUSB USBTX, USBRX + +// SDA SCK +#define MBED_I2C0 PG2, PG3 +#define MBED_I2C1 PF2, PF3 +#define MBED_I2C2 PG4, PG5 +#define MBED_I2C3 PJ6, PJ7 +#define MBED_I2C4 PJ3, PJ2 + +// MOSI, MISO, SCLK SS +#define MBED_SPI0 PA3, PA2, PA1, PA0 +#define MBED_SPI1 PL3, PL2, PL1, PL0 +#define MBED_SPI2 PA4, PA5, PA6, PA7 +#define MBED_SPI3 PK4, PK5, PK6, PK7 +#define MBED_SPI4 PD3, PD2, PD1, PD0 +#define MBED_SPI5 PV5, PV4, PV6, PV7 +#define MBED_SPI6 PM0, PM1, PM2, PM3 +#define MBED_SPI7 PM7, PM6, PM5, PM4 +#define MBED_SPI8 PW3, PW2, PW1, PW0 + +#define MBED_ANALOGIN0 A0 +#define MBED_ANALOGIN1 A1 +#define MBED_ANALOGIN2 A2 +#define MBED_ANALOGIN3 A3 +#define MBED_ANALOGIN4 A4 +#define MBED_ANALOGIN5 A5 + +#define MBED_PWMOUT0 PA5 +#define MBED_PWMOUT1 PB2 +#define MBED_PWMOUT2 PB4 +#define MBED_PWMOUT3 PD2 +#define MBED_PWMOUT4 PD4 +#define MBED_PWMOUT5 PE1 +#define MBED_PWMOUT6 PE6 +#define MBED_PWMOUT7 PC2 +#define MBED_PWMOUT8 PL6 +#define MBED_PWMOUT9 PC4 +#define MBED_PWMOUT10 PM2 +#define MBED_PWMOUT11 PU0 +#define MBED_PWMOUT12 PU6 + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h new file mode 100644 index 0000000..5257e5c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PinNames.h @@ -0,0 +1,144 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) + +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) +#define PIN_DIR(X) ((X) & 0xffff) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM4G9 Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, + PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, + PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, + PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, PN6, PN7, + PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, + PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, + PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, + PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7, + PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, + PW0 = 18 << 3, PW1, PW2, PW3, PW4, PW5, PW6, PW7, + PY0 = 19 << 3, PY1, PY2, PY3, PY4, + + // External data bus Pin Names + D0 = PJ1, + D1 = PJ0, + D2 = PF4, + D3 = PB2, + D4 = PF5, + D5 = PB4, + D6 = PC2, + D7 = PF6, + D8 = PA4, + D9 = PC4, + D10 = PA0, + D11 = PA3, + D12 = PA2, + D13 = PA1, + D14 = PG2, + D15 = PG3, + + // Analogue in pins + A0 = PN0, + A1 = PN1, + A2 = PN2, + A3 = PN3, + A4 = PN4, + A5 = PN5, + + // USB2_UART + CONSOLE_TX = PU0, + CONSOLE_RX = PU1, + MBEDIF_TXD = CONSOLE_TX, + MBEDIF_RXD = CONSOLE_RX, + + MBED_CONF_APP_UART0_TX = PE3, + MBED_CONF_APP_UART0_RX = PE2, + + // Switches + SW1 = PL4, + SW2 = PL5, + SW3 = PV0, + SW4 = PV1, + + // I2C pins + SDA = PG2, + SCL = PG3, + + // Analogue out + DAC0 = PT0, + DAC1 = PT1, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +// LED definitions +#define LED1 PE4 +#define LED2 PE5 +#define LED3 PE6 +#define LED4 PE7 + +// Standardized button names +#define BUTTON1 SW1 +#define BUTTON2 SW2 +#define BUTTON3 SW3 +#define BUTTON4 SW4 + +//I2C +#define I2C_SDA SDA +#define I2C_SCL SCL + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h new file mode 100644 index 0000000..3ccc362 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/PortNames.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ, + PortK, + PortL, + PortM, + PortN, + PortP, + PortR, + PortT, + PortU, + PortV, + PortW, + PortY +} PortName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogin_api.c new file mode 100644 index 0000000..1341823 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogin_api.c @@ -0,0 +1,146 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "txz_adc_include.h" + +#define ADC_12BIT_RANGE 0xFFF +#define CONVERSION_FLAG 0x4 + +static const PinMap PinMap_ADC[] = { + {PN0, ADC_A0, PIN_DATA(0, 0)}, + {PN1, ADC_A1, PIN_DATA(0, 0)}, + {PN2, ADC_A2, PIN_DATA(0, 0)}, + {PN3, ADC_A3, PIN_DATA(0, 0)}, + {PN4, ADC_A4, PIN_DATA(0, 0)}, + {PN5, ADC_A5, PIN_DATA(0, 0)}, + {PN6, ADC_A6, PIN_DATA(0, 0)}, + {PN7, ADC_A7, PIN_DATA(0, 0)}, + {PP0, ADC_A8, PIN_DATA(0, 0)}, + {PP1, ADC_A9, PIN_DATA(0, 0)}, + {PP2, ADC_A10, PIN_DATA(0, 0)}, + {PP3, ADC_A11, PIN_DATA(0, 0)}, + {PP4, ADC_A12, PIN_DATA(0, 0)}, + {PP5, ADC_A13, PIN_DATA(0, 0)}, + {PP6, ADC_A14, PIN_DATA(0, 0)}, + {PP7, ADC_A15, PIN_DATA(0, 0)}, + {PR0, ADC_A16, PIN_DATA(0, 0)}, + {PR1, ADC_A17, PIN_DATA(0, 0)}, + {PR2, ADC_A18, PIN_DATA(0, 0)}, + {PR3, ADC_A19, PIN_DATA(0, 0)}, + {PR4, ADC_A20, PIN_DATA(0, 0)}, + {PR5, ADC_A21, PIN_DATA(0, 0)}, + {PR6, ADC_A22, PIN_DATA(0, 0)}, + {PR7, ADC_A23, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Enable ADC clock supply + TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; + TSB_CG_SPCLKEN_ADCKEN = TXZ_ENABLE; + TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE; + + // Enable clock for GPIO + if (obj->adc <= ADC_A7) { + TSB_CG_FSYSMENB_IPMENB14 = TXZ_ENABLE; + } else if (obj->adc <= ADC_A15) { + TSB_CG_FSYSMENB_IPMENB15 = TXZ_ENABLE; + } else { + TSB_CG_FSYSMENB_IPMENB16 = TXZ_ENABLE; + } + + // Set pin function as ADC + pinmap_pinout(pin, PinMap_ADC); + + // Initialize + obj->p_adc.p_instance = TSB_ADA; + obj->p_adc.init.clk.exaz0 = ADC_SAMPLING_PERIOD0_XN; + obj->p_adc.init.clk.exaz1 = ADC_SAMPLING_PERIOD1_XN; + obj->p_adc.init.clk.vadcld = ADC_SCLK_5; /*less than 40MHz*/ + obj->p_adc.init.clk.sampling_select = 0; + obj->p_adc.init.mod1 = ADC_MOD1_SCLK_4; + obj->p_adc.init.mod2 = ADC_MOD2_SET; + obj->p_adc.handler.single = NULL; + obj->p_adc.handler.continuity = NULL; + obj->p_adc.handler.trigger = NULL; + obj->p_adc.handler.highpriority = NULL; + + if (adc_init(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : ADC Initialization"); + } + + // ADC channel setting + obj->param.interrupt = ADC_INT_DISABLE; + obj->param.type = ADC_CONVERSION_SGL; + obj->param.ain = obj->adc; + + if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) { + error("Failed : ADC channel setting"); + } +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint32_t adc_result = 0; + + wait_us(700); // Wait at least 700us to ensure the voltage is stable + // Assert that ADC channel is valid + MBED_ASSERT(obj->adc != (ADCName)NC); + + if (adc_start(&obj->p_adc) == TXZ_SUCCESS) { + // adc started + } + + // Wait for Continuous conversion program flag clear. + while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) { + // Do nothing + } + + if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) { + error("Failed : To read ADC converted result"); + } + + if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : To Stop ADC Conversion"); + } + + return (uint16_t)adc_result; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = 0; + + value = analogin_read_u16(obj); + + return (float)(value * (1.0f / (float)ADC_12BIT_RANGE)); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogout_api.c new file mode 100644 index 0000000..d40de12 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/analogout_api.c @@ -0,0 +1,129 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "cmsis.h" +#include "analogout_api.h" +#include "pinmap.h" + +#define REG_DAC_DAxCR_REN_DISABLE ((uint32_t)0x00000000) // DAC Control Disable. +#define REG_DAC_DAxCR_REN_ENABLE ((uint32_t)0x00000001) // DAC Control Enable. +#define DAC0_CLR_IN_CLR_OUT (1) // As per TRM DAC pin inout mode should be neither in nor out +#define DAC1_CLR_IN_CLR_OUT (2) +#define MAX_ANALOG_VAL (1.0f) +#define MIN_ANALOG_VAL (0.0f) + + +static const PinMap PinMap_DAC[] = { + {PT0, DAC_0, PIN_DATA(0, 1)}, + {PT1, DAC_1, PIN_DATA(0, 1)}, + {NC, NC, 0} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + DACName dac_name = (DACName)pinmap_peripheral(pin, PinMap_DAC); + + MBED_ASSERT(dac_name != (DACName)NC); + + obj->dac = dac_name; + + switch (dac_name) { + case DAC_0: + obj->DACx = TSB_DA0; + // Enable clock for DAC0 and Port T + TSB_CG_FSYSMENA_IPMENA04 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; + break; + case DAC_1: + obj->DACx = TSB_DA1; + // Enable clock for DAC1 and Port T + TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; + break; + default: + break; + } + + + pinmap_pinout(pin, PinMap_DAC); + + // DAC pins as neither input and nor output + if (dac_name == DAC_0) { + TSB_PT->CR &= ~(DAC0_CLR_IN_CLR_OUT); + TSB_PT->IE &= ~(DAC0_CLR_IN_CLR_OUT); + } else if (dac_name == DAC_1) { + TSB_PT->CR &= ~(DAC1_CLR_IN_CLR_OUT); + TSB_PT->IE &= ~(DAC1_CLR_IN_CLR_OUT); + } else { + return; + } + + obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; +} + +void analogout_free(dac_t *obj) +{ + obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; + obj->dac = (DACName)NC; +} + +void analogout_write(dac_t *obj, float value) +{ + uint8_t outputcode = 0; + obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; + if (value < 0.0f) { + value = 0.0f; + } else { + if (value >= 1.0f) { + value = 1.0f; + } + } + outputcode = (uint8_t)(value * 255.0f); + obj->DACx->REG = outputcode; +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + // Writing higher 8-bits to Data Register + obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; + obj->DACx->REG = (uint8_t)(value & 0xFF); +} + +float analogout_read(dac_t *obj) +{ + float result = 0.0; + uint32_t value = 0; + + value = ((obj->DACx->REG) & (0xFF)); + result = ((float)value / 255.0f); + + return result; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + uint16_t value = 0; + + value = (uint16_t)((obj->DACx->REG) & (0xFF)); + return value; + // Upper and lower byte stored with read value +} + +const PinMap *analogout_pinmap() +{ + return PinMap_DAC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device.h new file mode 100644 index 0000000..3390d2b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device.h @@ -0,0 +1,26 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define TRANSACTION_QUEUE_SIZE_SPI 4 +#define DEVICE_ID_LENGTH 32 + +#include +#include "objects.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TMPM4GR.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TMPM4GR.h new file mode 100644 index 0000000..f8dae22 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TMPM4GR.h @@ -0,0 +1,7346 @@ +/** + ******************************************************************************* + * @file TMPM4GR.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4GR' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM4GR + * @{ + */ + +#ifndef __TMPM4GR_H__ +#define __TMPM4GR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** TMPM4GR Specific Interrupt Numbers *******************************************************************/ + INT00_IRQn = 0, /*!< Interrupt pin 00a/00b */ + INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */ + INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */ + INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */ + INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */ + INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */ + INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */ + INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */ + INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */ + INT09_IRQn = 9, /*!< Interrupt pin 09a/09b */ + INT10_IRQn = 10, /*!< Interrupt pin 10a/10b */ + INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */ + INT12_IRQn = 12, /*!< Interrupt pin 12a/12b */ + INT13_IRQn = 13, /*!< Interrupt pin 13a/13b */ + INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */ + INT15_IRQn = 15, /*!< Interrupt pin 15a/15b */ + INTRTC_IRQn = 16, /*!< Real time clock(XHz) interrupt */ + INTCEC0RX_IRQn = 17, /*!< CEC reception interrupt (channel 0) */ + INTCEC0TX_IRQn = 18, /*!< CEC transmission interrupt (channel 0) */ + INTISDA_IRQn = 19, /*!< Interval Sensing Detector interrupt (Unit A) */ + INTISDB_IRQn = 20, /*!< Interval Sensing Detector interrupt (Unit B) */ + INTISDC_IRQn = 21, /*!< Interval Sensing Detector interrupt (Unit C) */ + INTRMC0_IRQn = 22, /*!< Remote control reception interrupt 0 */ + INTRMC1_IRQn = 23, /*!< Remote control reception interrupt 1 */ + INTLTTMR0_IRQn = 24, /*!< Long Term Timer Interrupt(channel 0) */ + INTHDMAATC_IRQn = 25, /*!< HDMA complete of transfer(Unit A) */ + INTHDMAAERR_IRQn = 26, /*!< HDMA transfer error(Unit A) */ + INTHDMABTC_IRQn = 27, /*!< HDMA end of transfer(Unit B) */ + INTHDMABERR_IRQn = 28, /*!< HDMA transfer error(Unit B) */ + INTMDMAATC_IRQn = 29, /*!< MDMA complete of transfer(Unit A) */ + INTT32A00_A_CT_IRQn = 30, /*!< T32A00 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A00_B_C01_CPC_IRQn = 31, /*!< T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A01_A_CT_IRQn = 32, /*!< T32A01 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A01_B_C01_CPC_IRQn = 33, /*!< T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A02_A_CT_IRQn = 34, /*!< T32A02 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A02_B_C01_CPC_IRQn = 35, /*!< T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A03_A_CT_IRQn = 36, /*!< T32A03 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A03_B_C01_CPC_IRQn = 37, /*!< T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A04_A_CT_IRQn = 38, /*!< T32A04 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A04_B_C01_CPC_IRQn = 39, /*!< T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A05_A_CT_IRQn = 40, /*!< T32A05 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A05_B_C01_CPC_IRQn = 41, /*!< T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A06_A_CT_IRQn = 42, /*!< T32A06 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A06_B_C01_CPC_IRQn = 43, /*!< T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A07_A_CT_IRQn = 44, /*!< T32A07 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A07_B_C01_CPC_IRQn = 45, /*!< T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A08_A_CT_IRQn = 46, /*!< T32A08 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A08_B_C01_CPC_IRQn = 47, /*!< T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A09_A_CT_IRQn = 48, /*!< T32A09 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A09_B_C01_CPC_IRQn = 49, /*!< T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A10_A_CT_IRQn = 50, /*!< T32A10 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A10_B_C01_CPC_IRQn = 51, /*!< T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A11_A_CT_IRQn = 52, /*!< T32A11 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A11_B_C01_CPC_IRQn = 53, /*!< T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A12_A_CT_IRQn = 54, /*!< T32A12 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A12_B_C01_CPC_IRQn = 55, /*!< T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A13_A_CT_IRQn = 56, /*!< T32A13 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A13_B_C01_CPC_IRQn = 57, /*!< T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTEMG0_IRQn = 58, /*!< PMD0 EMG interrupt */ + INTOVV0_IRQn = 59, /*!< PMD0 OVV interrupt */ + INTPWM0_IRQn = 60, /*!< PMD0 interrupt */ + INTT0RX_IRQn = 61, /*!< TSPI/SIO reception (channel 0) interrupt */ + INTT0TX_IRQn = 62, /*!< TSPI/SIO transmit (channel 0) interrupt */ + INTT0ERR_IRQn = 63, /*!< TSPI/SIO error (channel 0) interrupt */ + INTT1RX_IRQn = 64, /*!< TSPI/SIO reception (channel 1) interrupt */ + INTT1TX_IRQn = 65, /*!< TSPI/SIO transmit (channel 1) interrupt */ + INTT1ERR_IRQn = 66, /*!< TSPI/SIO error (channel 1) interrupt */ + INTT2RX_IRQn = 67, /*!< TSPI/SIO reception (channel 2) interrupt */ + INTT2TX_IRQn = 68, /*!< TSPI/SIO transmit (channel 2) interrupt */ + INTT2ERR_IRQn = 69, /*!< TSPI/SIO error (channel 2) interrupt */ + INTT3RX_IRQn = 70, /*!< TSPI/SIO reception (channel 3) interrupt */ + INTT3TX_IRQn = 71, /*!< TSPI/SIO transmit (channel 3) interrupt */ + INTT3ERR_IRQn = 72, /*!< TSPI/SIO error (channel 3) interrupt */ + INTT4RX_IRQn = 73, /*!< TSPI/SIO reception (channel 4) interrupt */ + INTT4TX_IRQn = 74, /*!< TSPI/SIO transmit (channel 4) interrupt */ + INTT4ERR_IRQn = 75, /*!< TSPI/SIO error (channel 4) interrupt */ + INTT5RX_IRQn = 76, /*!< TSPI/SIO reception (channel 5) interrupt */ + INTT5TX_IRQn = 77, /*!< TSPI/SIO transmit (channel 5) interrupt */ + INTT5ERR_IRQn = 78, /*!< TSPI/SIO error (channel 5) interrupt */ + INTT6RX_IRQn = 79, /*!< TSPI/SIO reception (channel 6) interrupt */ + INTT6TX_IRQn = 80, /*!< TSPI/SIO transmit (channel 6) interrupt */ + INTT6ERR_IRQn = 81, /*!< TSPI/SIO error (channel 6) interrupt */ + INTT7RX_IRQn = 82, /*!< TSPI/SIO reception (channel 7) interrupt */ + INTT7TX_IRQn = 83, /*!< TSPI/SIO transmit (channel 7) interrupt */ + INTT7ERR_IRQn = 84, /*!< TSPI/SIO error (channel 7) interrupt */ + INTT8RX_IRQn = 85, /*!< TSPI/SIO reception (channel 8) interrupt */ + INTT8TX_IRQn = 86, /*!< TSPI/SIO transmit (channel 8) interrupt */ + INTT8ERR_IRQn = 87, /*!< TSPI/SIO error (channel 8) interrupt */ + INTSMI0_IRQn = 88, /*!< Serial Memory Interface interrupt */ + INTUART0RX_IRQn = 89, /*!< UART reception (channel 0) interrupt */ + INTUART0TX_IRQn = 90, /*!< UART transmit (channel 0) interrupt */ + INTUART0ERR_IRQn = 91, /*!< UART error (channel 0) interrupt */ + INTUART1RX_IRQn = 92, /*!< UART reception (channel 1) interrupt */ + INTUART1TX_IRQn = 93, /*!< UART transmit (channel 1) interrupt */ + INTUART1ERR_IRQn = 94, /*!< UART error (channel 1) interrupt */ + INTUART2RX_IRQn = 95, /*!< UART reception (channel 2) interrupt */ + INTUART2TX_IRQn = 96, /*!< UART transmit (channel 2) interrupt */ + INTUART2ERR_IRQn = 97, /*!< UART error (channel 2) interrupt */ + INTUART3RX_IRQn = 98, /*!< UART reception (channel 3) interrupt */ + INTUART3TX_IRQn = 99, /*!< UART transmit (channel 3) interrupt */ + INTUART3ERR_IRQn = 100, /*!< UART error (channel 3) interrupt */ + INTUART4RX_IRQn = 101, /*!< UART reception (channel 4) interrupt */ + INTUART4TX_IRQn = 102, /*!< UART transmit (channel 4) interrupt */ + INTUART4ERR_IRQn = 103, /*!< UART error (channel 4) interrupt */ + INTUART5RX_IRQn = 104, /*!< UART reception (channel 5) interrupt */ + INTUART5TX_IRQn = 105, /*!< UART transmit (channel 5) interrupt */ + INTUART5ERR_IRQn = 106, /*!< UART error (channel 5) interrupt */ + INTFUART0_IRQn = 107, /*!< FUART interrupt(channel 0) */ + INTFUART1_IRQn = 108, /*!< FUART interrupt(channel 1) */ + INTI2C0NST_IRQn = 109, /*!< I2C0 interrupt / EI2C0 status interrupt */ + INTI2C0ATX_IRQn = 110, /*!< I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C0BRX_IRQn = 111, /*!< I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C0NA_IRQn = 112, /*!< I2C0 NACK detection interrupt */ + INTI2C1NST_IRQn = 113, /*!< I2C1 interrupt / EI2C0 status interrupt */ + INTI2C1ATX_IRQn = 114, /*!< I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C1BRX_IRQn = 115, /*!< I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C1NA_IRQn = 116, /*!< I2C1 NACK detection interrupt */ + INTI2C2NST_IRQn = 117, /*!< I2C2 interrupt / EI2C0 status interrupt */ + INTI2C2ATX_IRQn = 118, /*!< I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C2BRX_IRQn = 119, /*!< I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C2NA_IRQn = 120, /*!< I2C2 NACK detection interrupt */ + INTI2C3NST_IRQn = 121, /*!< I2C3 interrupt / EI2C0 status interrupt */ + INTI2C3ATX_IRQn = 122, /*!< I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C3BRX_IRQn = 123, /*!< I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C3NA_IRQn = 124, /*!< I2C3 NACK detection interrupt */ + INTI2C4NST_IRQn = 125, /*!< I2C4 interrupt / EI2C0 status interrupt */ + INTI2C4ATX_IRQn = 126, /*!< I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C4BRX_IRQn = 127, /*!< I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C4NA_IRQn = 128, /*!< I2C4 NACK detection interrupt */ + INTADACP0_IRQn = 129, /*!< ADC conversion monitoring function interrupt 0 */ + INTADACP1_IRQn = 130, /*!< ADC conversion monitoring function interrupt 1 */ + INTADATRG_IRQn = 131, /*!< ADC conversion triggered by General purpose is finished */ + INTADASGL_IRQn = 132, /*!< ADC conversion triggered by Single program is finished */ + INTADACNT_IRQn = 133, /*!< ADC conversion triggered by Continuity program is finished */ + INTADAHP_IRQn = 134, /*!< ADC high priority AD conversion interrupt */ + INTFLDRDY_IRQn = 135, /*!< Data FLASH Ready interrupt */ + INTFLCRDY_IRQn = 136, /*!< Code FLASH Area0/1 Ready interrupt */ + INTMDMAABERR_IRQn = 139, /*!< MDMA bus error(Unit A) interrupt */ + INTMDMAADERR_IRQn = 140, /*!< MDMA descriptor error(Unit A) interrupt */ + INTI2S0SI_IRQn = 141, /*!< I2S ch0 SI transfer end interrupt */ + INTI2S0SIERR_IRQn = 142, /*!< I2S ch0 SI error interrupt */ + INTI2S0SO_IRQn = 143, /*!< I2S ch0 SO transfer end interrupt */ + INTI2S0SOERR_IRQn = 144, /*!< I2S ch0 SO error interrupt */ + INTI2S1SI_IRQn = 145, /*!< I2S ch1 SI transfer end interrupt */ + INTI2S1SIERR_IRQn = 146, /*!< I2S ch1 SI error interrupt */ + INTI2S1SO_IRQn = 147, /*!< I2S ch1 SO transfer end interrupt */ + INTI2S1SOERR_IRQn = 148, /*!< I2S ch1 SO error interrupt */ + INTFIR0_IRQn = 149, /*!< FIR ch0 interrupt */ + INTTSSI0RX_IRQn = 150, /*!< TSSI ch0 receive interrupt */ + INTTSSI0TX_IRQn = 151, /*!< TSSI ch0 transmission interrupt */ + INTTSSI0ERR_IRQn = 152, /*!< TSSI ch0 error interrupt */ + INTTSSI1RX_IRQn = 153, /*!< TSSI ch1 receive interrupt */ + INTTSSI1TX_IRQn = 154, /*!< TSSI ch1 transmission interrupt */ + INTTSSI1ERR_IRQn = 155, /*!< TSSI ch1 error interrupt */ + INTT32A14_A_IRQn = 168, /*!< T32A14 TimerA all interrupt */ + INTT32A14_B_IRQn = 169, /*!< T32A14 TimerB all interrupt */ + INTT32A14_CT_IRQn = 170, /*!< T32A14 TimerC match, overflow, and underflow Interrupt */ + INTT32A15_A_IRQn = 171, /*!< T32A15 TimerA all interrupt */ + INTT32A15_B_IRQn = 172, /*!< T32A15 TimerB all interrupt */ + INTT32A15_C_IRQn = 173, /*!< T32A15 TimerC all interrupt */ + INTMDMAADISR_IRQn = 174 /*!< MDMAC unit A Descriptor interrupt */ +} IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_TMPM4Gx.h" /* TMPM4Gx System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief DMA Controller + */ +typedef struct { + __I uint32_t INTSTATUS; /*!< DMAC Interrupt Status Register */ + __I uint32_t INTTCSTATUS; /*!< DMAC Transfer Completion Interrupt Status Register*/ + __O uint32_t INTTCCLEAR; /*!< DMAC Transfer Completion Interrupt Clear Register*/ + __I uint32_t INTERRORSTATUS; /*!< DMAC Error Interrupt Status Register */ + __O uint32_t INTERRCLR; /*!< DMAC Error Interrupt Clear Register */ + __I uint32_t RAWINTTCSTATUS; /*!< DMAC Raw Transfer Completion Interrupt Status Register*/ + __I uint32_t RAWINTERRORSTATUS; /*!< DMAC Raw Error Interrupt Status Register */ + __I uint32_t ENBLDCHNS; /*!< DMAC Channel Enable Register */ + __IO uint32_t SOFTBREQ; /*!< DMAC Software Burst Transfer Request Register*/ + __IO uint32_t SOFTSREQ; /*!< DMAC Software Single Transfer Request Register*/ + uint32_t RESERVED0[2]; + __IO uint32_t CONFIGURATION; /*!< DMAC Configuration Register */ + uint32_t RESERVED1[51]; + __IO uint32_t C0SRCADDR; /*!< DMAC Channel 0 Transfer Source Address Register*/ + __IO uint32_t C0DESTADDR; /*!< DMAC Channel 0 Transfer Destination Address Register*/ + __IO uint32_t C0LLI; /*!< DMAC Channel 0 Linked List Item Register */ + __IO uint32_t C0CONTROL; /*!< DMAC Channel 0 Control Register */ + __IO uint32_t C0CONFIGURATION; /*!< DMAC Channel 0 Configuration Register */ + uint32_t RESERVED2[3]; + __IO uint32_t C1SRCADDR; /*!< DMAC Channel 1 Transfer Source Address Register*/ + __IO uint32_t C1DESTADDR; /*!< DMAC Channel 1 Transfer Destination Address Register*/ + __IO uint32_t C1LLI; /*!< DMAC Channel 1 Linked List Item Register */ + __IO uint32_t C1CONTROL; /*!< DMAC Channel 1 Control Register */ + __IO uint32_t C1CONFIGURATION; /*!< DMAC Channel 1 Configuration Register */ +} TSB_DMAC_TypeDef; + +/** + * @brief SMIF + */ +typedef struct { + __IO uint32_t MAP0; /*!< SMIF Address Map Control Register 0 */ + __IO uint32_t MAP1; /*!< SMIF Address Map Control Register 1 */ + __IO uint32_t DACR0; /*!< SMIF Direct Access Control Register 0 */ + __IO uint32_t DACR1; /*!< SMIF Direct Access Control Register 1 */ + __IO uint32_t DRCR0; /*!< SMIF Direct Read Control Register 0 */ + __IO uint32_t DRCR1; /*!< SMIF Direct Read Control Register 1 */ + __IO uint32_t DWCR0; /*!< SMIF Direct Write Control Register 0 */ + __IO uint32_t DWCR1; /*!< SMIF Direct Write Control Register 1 */ + uint32_t RESERVED0[248]; + __IO uint32_t RACR0; /*!< SMIF Indirect Access Control Register 0 */ + __IO uint32_t RACR1; /*!< SMIF Indirect Access Control Register 1 */ + __IO uint32_t IOCR; /*!< SMIF Indirect Access I/O Control Register */ + __IO uint32_t OECR; /*!< SMIF Indirect Access Output Enable Register */ + uint32_t RESERVED1[12]; + __IO uint32_t INT; /*!< SMIF Interrupt Control Register */ + __IO uint32_t STAT; /*!< SMIF Status Register */ + uint32_t RESERVED2[14]; + __IO uint32_t SWR; /*!< SMIF Software Reset Register */ + __IO uint32_t ACKR; /*!< SMIF Additional Clock Control Register */ + __IO uint32_t CCOR; /*!< SMIF Serial Clock, CS pin Direction Control Register*/ + __IO uint32_t STPR; /*!< SMIF Forced Stop Control Register */ + uint32_t RESERVED3[28]; + __IO uint32_t PBUF0; /*!< SMIF Indirect Access Primary Buffer Register 0*/ + __IO uint32_t PBUF1; /*!< SMIF Indirect Access Primary Buffer Register 1*/ + __IO uint32_t PBUF2; /*!< SMIF Indirect Access Primary Buffer Register 2*/ + __IO uint32_t PBUF3; /*!< SMIF Indirect Access Primary Buffer Register 3*/ + __IO uint32_t PBUF4; /*!< SMIF Indirect Access Primary Buffer Register 4*/ + __IO uint32_t PBUF5; /*!< SMIF Indirect Access Primary Buffer Register 5*/ + __IO uint32_t PBUF6; /*!< SMIF Indirect Access Primary Buffer Register 6*/ + __IO uint32_t PBUF7; /*!< SMIF Indirect Access Primary Buffer Register 7*/ + uint32_t RESERVED4[56]; + __IO uint32_t SBUF00; /*!< SMIF Indirect Access Secondary Buffer Register 00*/ + __IO uint32_t SBUF01; /*!< SMIF Indirect Access Secondary Buffer Register 01*/ + __IO uint32_t SBUF02; /*!< SMIF Indirect Access Secondary Buffer Register 02*/ + __IO uint32_t SBUF03; /*!< SMIF Indirect Access Secondary Buffer Register 03*/ + __IO uint32_t SBUF04; /*!< SMIF Indirect Access Secondary Buffer Register 04*/ + __IO uint32_t SBUF05; /*!< SMIF Indirect Access Secondary Buffer Register 05*/ + __IO uint32_t SBUF06; /*!< SMIF Indirect Access Secondary Buffer Register 06*/ + __IO uint32_t SBUF07; /*!< SMIF Indirect Access Secondary Buffer Register 07*/ + __IO uint32_t SBUF08; /*!< SMIF Indirect Access Secondary Buffer Register 08*/ + __IO uint32_t SBUF09; /*!< SMIF Indirect Access Secondary Buffer Register 09*/ + __IO uint32_t SBUF10; /*!< SMIF Indirect Access Secondary Buffer Register 10*/ + __IO uint32_t SBUF11; /*!< SMIF Indirect Access Secondary Buffer Register 11*/ + __IO uint32_t SBUF12; /*!< SMIF Indirect Access Secondary Buffer Register 12*/ + __IO uint32_t SBUF13; /*!< SMIF Indirect Access Secondary Buffer Register 13*/ + __IO uint32_t SBUF14; /*!< SMIF Indirect Access Secondary Buffer Register 14*/ + __IO uint32_t SBUF15; /*!< SMIF Indirect Access Secondary Buffer Register 15*/ + __IO uint32_t SBUF16; /*!< SMIF Indirect Access Secondary Buffer Register 16*/ + __IO uint32_t SBUF17; /*!< SMIF Indirect Access Secondary Buffer Register 17*/ + __IO uint32_t SBUF18; /*!< SMIF Indirect Access Secondary Buffer Register 18*/ + __IO uint32_t SBUF19; /*!< SMIF Indirect Access Secondary Buffer Register 19*/ + __IO uint32_t SBUF20; /*!< SMIF Indirect Access Secondary Buffer Register 20*/ + __IO uint32_t SBUF21; /*!< SMIF Indirect Access Secondary Buffer Register 21*/ + __IO uint32_t SBUF22; /*!< SMIF Indirect Access Secondary Buffer Register 22*/ + __IO uint32_t SBUF23; /*!< SMIF Indirect Access Secondary Buffer Register 23*/ + __IO uint32_t SBUF24; /*!< SMIF Indirect Access Secondary Buffer Register 24*/ + __IO uint32_t SBUF25; /*!< SMIF Indirect Access Secondary Buffer Register 25*/ + __IO uint32_t SBUF26; /*!< SMIF Indirect Access Secondary Buffer Register 26*/ + __IO uint32_t SBUF27; /*!< SMIF Indirect Access Secondary Buffer Register 27*/ + __IO uint32_t SBUF28; /*!< SMIF Indirect Access Secondary Buffer Register 28*/ + __IO uint32_t SBUF29; /*!< SMIF Indirect Access Secondary Buffer Register 29*/ + __IO uint32_t SBUF30; /*!< SMIF Indirect Access Secondary Buffer Register 30*/ + __IO uint32_t SBUF31; /*!< SMIF Indirect Access Secondary Buffer Register 31*/ + __IO uint32_t SBUF32; /*!< SMIF Indirect Access Secondary Buffer Register 32*/ + __IO uint32_t SBUF33; /*!< SMIF Indirect Access Secondary Buffer Register 33*/ + __IO uint32_t SBUF34; /*!< SMIF Indirect Access Secondary Buffer Register 34*/ + __IO uint32_t SBUF35; /*!< SMIF Indirect Access Secondary Buffer Register 35*/ + __IO uint32_t SBUF36; /*!< SMIF Indirect Access Secondary Buffer Register 36*/ + __IO uint32_t SBUF37; /*!< SMIF Indirect Access Secondary Buffer Register 37*/ + __IO uint32_t SBUF38; /*!< SMIF Indirect Access Secondary Buffer Register 38*/ + __IO uint32_t SBUF39; /*!< SMIF Indirect Access Secondary Buffer Register 39*/ + __IO uint32_t SBUF40; /*!< SMIF Indirect Access Secondary Buffer Register 40*/ + __IO uint32_t SBUF41; /*!< SMIF Indirect Access Secondary Buffer Register 41*/ + __IO uint32_t SBUF42; /*!< SMIF Indirect Access Secondary Buffer Register 42*/ + __IO uint32_t SBUF43; /*!< SMIF Indirect Access Secondary Buffer Register 43*/ + __IO uint32_t SBUF44; /*!< SMIF Indirect Access Secondary Buffer Register 44*/ + __IO uint32_t SBUF45; /*!< SMIF Indirect Access Secondary Buffer Register 45*/ + __IO uint32_t SBUF46; /*!< SMIF Indirect Access Secondary Buffer Register 46*/ + __IO uint32_t SBUF47; /*!< SMIF Indirect Access Secondary Buffer Register 47*/ + __IO uint32_t SBUF48; /*!< SMIF Indirect Access Secondary Buffer Register 48*/ + __IO uint32_t SBUF49; /*!< SMIF Indirect Access Secondary Buffer Register 49*/ + __IO uint32_t SBUF50; /*!< SMIF Indirect Access Secondary Buffer Register 50*/ + __IO uint32_t SBUF51; /*!< SMIF Indirect Access Secondary Buffer Register 51*/ + __IO uint32_t SBUF52; /*!< SMIF Indirect Access Secondary Buffer Register 52*/ + __IO uint32_t SBUF53; /*!< SMIF Indirect Access Secondary Buffer Register 53*/ + __IO uint32_t SBUF54; /*!< SMIF Indirect Access Secondary Buffer Register 54*/ + __IO uint32_t SBUF55; /*!< SMIF Indirect Access Secondary Buffer Register 55*/ + __IO uint32_t SBUF56; /*!< SMIF Indirect Access Secondary Buffer Register 56*/ + __IO uint32_t SBUF57; /*!< SMIF Indirect Access Secondary Buffer Register 57*/ + __IO uint32_t SBUF58; /*!< SMIF Indirect Access Secondary Buffer Register 58*/ + __IO uint32_t SBUF59; /*!< SMIF Indirect Access Secondary Buffer Register 59*/ + __IO uint32_t SBUF60; /*!< SMIF Indirect Access Secondary Buffer Register 60*/ + __IO uint32_t SBUF61; /*!< SMIF Indirect Access Secondary Buffer Register 61*/ + __IO uint32_t SBUF62; /*!< SMIF Indirect Access Secondary Buffer Register 62*/ + __IO uint32_t SBUF63; /*!< SMIF Indirect Access Secondary Buffer Register 63*/ +} TSB_SMI_TypeDef; + +/** + * @brief Interrupt Control Registers A + */ +typedef struct { + __IO uint8_t NIC00; /*!< Non-maskable Interrupt A Control Register 00 */ + uint8_t RESERVED0[31]; + __IO uint8_t IMC00; /*!< Interrupt A Mode Control Register 00 */ + __IO uint8_t IMC01; /*!< Interrupt A Mode Control Register 01 */ + __IO uint8_t IMC02; /*!< Interrupt A Mode Control Register 02 */ + __IO uint8_t IMC03; /*!< Interrupt A Mode Control Register 03 */ + __IO uint8_t IMC04; /*!< Interrupt A Mode Control Register 04 */ + __IO uint8_t IMC05; /*!< Interrupt A Mode Control Register 05 */ + __IO uint8_t IMC06; /*!< Interrupt A Mode Control Register 06 */ + __IO uint8_t IMC07; /*!< Interrupt A Mode Control Register 07 */ + __IO uint8_t IMC08; /*!< Interrupt A Mode Control Register 08 */ + __IO uint8_t IMC09; /*!< Interrupt A Mode Control Register 09 */ + __IO uint8_t IMC10; /*!< Interrupt A Mode Control Register 10 */ + __IO uint8_t IMC11; /*!< Interrupt A Mode Control Register 11 */ + __IO uint8_t IMC12; /*!< Interrupt A Mode Control Register 12 */ + __IO uint8_t IMC13; /*!< Interrupt A Mode Control Register 13 */ + __IO uint8_t IMC14; /*!< Interrupt A Mode Control Register 14 */ + __IO uint8_t IMC15; /*!< Interrupt A Mode Control Register 15 */ + __IO uint8_t IMC16; /*!< Interrupt A Mode Control Register 16 */ + __IO uint8_t IMC17; /*!< Interrupt A Mode Control Register 17 */ + __IO uint8_t IMC18; /*!< Interrupt A Mode Control Register 18 */ + __IO uint8_t IMC19; /*!< Interrupt A Mode Control Register 19 */ + __IO uint8_t IMC20; /*!< Interrupt A Mode Control Register 20 */ + __IO uint8_t IMC21; /*!< Interrupt A Mode Control Register 21 */ + __IO uint8_t IMC22; /*!< Interrupt A Mode Control Register 22 */ + __IO uint8_t IMC23; /*!< Interrupt A Mode Control Register 23 */ + __IO uint8_t IMC24; /*!< Interrupt A Mode Control Register 24 */ + __IO uint8_t IMC25; /*!< Interrupt A Mode Control Register 25 */ + __IO uint8_t IMC26; /*!< Interrupt A Mode Control Register 26 */ + __IO uint8_t IMC27; /*!< Interrupt A Mode Control Register 27 */ + __IO uint8_t IMC28; /*!< Interrupt A Mode Control Register 28 */ + __IO uint8_t IMC29; /*!< Interrupt A Mode Control Register 29 */ + __IO uint8_t IMC30; /*!< Interrupt A Mode Control Register 30 */ + __IO uint8_t IMC31; /*!< Interrupt A Mode Control Register 31 */ + uint8_t RESERVED1[17]; + __IO uint8_t IMC49; /*!< Interrupt A Mode Control Register 49 */ + __IO uint8_t IMC50; /*!< Interrupt A Mode Control Register 50 */ + __IO uint8_t IMC51; /*!< Interrupt A Mode Control Register 51 */ + __IO uint8_t IMC52; /*!< Interrupt A Mode Control Register 52 */ + __IO uint8_t IMC53; /*!< Interrupt A Mode Control Register 53 */ + __IO uint8_t IMC54; /*!< Interrupt A Mode Control Register 54 */ + __IO uint8_t IMC55; /*!< Interrupt A Mode Control Register 55 */ + __IO uint8_t IMC56; /*!< Interrupt A Mode Control Register 56 */ + __IO uint8_t IMC57; /*!< Interrupt A Mode Control Register 57 */ +} TSB_IA_TypeDef; + +/** + * @brief Low speed oscillation/power control/reset + */ +typedef struct { + __IO uint8_t LOSCCR; /*!< Low speed oscillation and Internal High speed oscillation 2 clock control register*/ + __IO uint8_t SHTDNOP; /*!< Power supply cut off control register */ + __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ + __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ + uint8_t RESERVED0[11]; + __IO uint8_t PROTECT; /*!< RLM write protection register */ +} TSB_RLM_TypeDef; + +/** + * @brief LVD0 + */ +typedef struct { + __IO uint8_t CR1; /*!< LVD Control Register1 */ + __IO uint8_t CR2; /*!< LVD Control Register2 */ + __IO uint8_t LVL1; /*!< LVD Detection Voltage Select Register 1 */ + uint8_t RESERVED0; + __I uint8_t SR; /*!< LVD Status Register */ +} TSB_LVD_TypeDef; + +/** + * @brief TRGSEL + */ +typedef struct { + __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ + __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ + __IO uint32_t CR2; /*!< TSEL Control register 2 */ + __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ + __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ + __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ + __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ + __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ + __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ + __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ + __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ + __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ + __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ + __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ + __IO uint32_t CR14; /*!< TRGSEL Control register 14 */ +} TSB_TSEL_TypeDef; + +/** + * @brief Long Term Timer(LTTMR) + */ +typedef struct { + __IO uint8_t CR0; /*!< LTTMR Control Register */ + __IO uint8_t VALL; /*!< LTTMR Data Register (Lower) */ + __IO uint8_t VALH; /*!< LTTMR Data Register (Upper) */ +} TSB_LTT_TypeDef; + +/** + * @brief Serial Interface (TSPI) + */ +typedef struct { + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + __IO uint32_t SECTCR0; /*!< TSPI Sector mode Control Register 0 */ + __IO uint32_t SECTCR1; /*!< TSPI Sector mode Control Register 1 */ + uint32_t RESERVED0[55]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Error Flag Register */ +} TSB_TSPI_TypeDef; + +/** + * @brief External Bus Interface(EXB) + */ +typedef struct { + __IO uint32_t MOD; /*!< EBIF Mode Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t AS0; /*!< EBIF Area and Start Address Configuration Register 0*/ + __IO uint32_t AS1; /*!< EBIF Area and Start Address Configuration Register 1*/ + __IO uint32_t AS2; /*!< EBIF Area and Start Address Configuration Register 2*/ + __IO uint32_t AS3; /*!< EBIF Area and Start Address Configuration Register 3*/ + uint32_t RESERVED1[8]; + __IO uint32_t CS0; /*!< EBIF Chip Select Control Register 0 */ + __IO uint32_t CS1; /*!< EBIF Chip Select Control Register 1 */ + __IO uint32_t CS2; /*!< EBIF Chip Select Control Register 2 */ + __IO uint32_t CS3; /*!< EBIF Chip Select Control Register 3 */ + uint32_t RESERVED2[4]; + __IO uint32_t CLKCTL; /*!< EBIF Clock Output Control Register */ +} TSB_EXB_TypeDef; + +/** + * @brief Clock Generator (CG) + */ +typedef struct { + __IO uint32_t PROTECT; /*!< CG write protection register */ + __IO uint32_t OSCCR; /*!< CG Oscillation control register */ + __IO uint32_t SYSCR; /*!< CG System clock control register */ + __IO uint32_t STBYCR; /*!< CG Standby control register */ + uint32_t RESERVED0[4]; + __IO uint32_t PLL0SEL; /*!< CG PLL selection register for fsys */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< CG High speed oscillation warming up register*/ + __IO uint32_t WUPLCR; /*!< CG Low speed oscillation warming up register */ + uint32_t RESERVED2[3]; + __IO uint32_t FSYSMENC; /*!< CG Middle speed clock supply and stop register C for fsys*/ + __IO uint32_t FSYSMENA; /*!< CG Middle speed clock supply and stop register A for fsys*/ + __IO uint32_t FSYSMENB; /*!< CG Middle speed clock supply and stop register B for fsys*/ + __IO uint32_t FSYSENA; /*!< CG High speed clock supply and stop register A for fsys*/ + uint32_t RESERVED3; + __IO uint32_t FCEN; /*!< CG Clock supply and stop register for fc */ + __IO uint32_t SPCLKEN; /*!< CG Clock supply for ADC and Trace Register */ + uint32_t RESERVED4[2]; + __IO uint32_t EXTEND2; /*!< CG Function extension register 2 */ +} TSB_CG_TypeDef; + +/** + * @brief Interrupt Control Register B + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint8_t NIC00; /*!< Non-maskable Interrupt B Control Register 00 */ + uint8_t RESERVED1[79]; + __IO uint8_t IMC000; /*!< Interrupt B Mode Control Register 000 */ + __IO uint8_t IMC001; /*!< Interrupt B Mode Control Register 001 */ + __IO uint8_t IMC002; /*!< Interrupt B Mode Control Register 002 */ + __IO uint8_t IMC003; /*!< Interrupt B Mode Control Register 003 */ + __IO uint8_t IMC004; /*!< Interrupt B Mode Control Register 004 */ + __IO uint8_t IMC005; /*!< Interrupt B Mode Control Register 005 */ + __IO uint8_t IMC006; /*!< Interrupt B Mode Control Register 006 */ + __IO uint8_t IMC007; /*!< Interrupt B Mode Control Register 007 */ + __IO uint8_t IMC008; /*!< Interrupt B Mode Control Register 008 */ + __IO uint8_t IMC009; /*!< Interrupt B Mode Control Register 009 */ + __IO uint8_t IMC010; /*!< Interrupt B Mode Control Register 010 */ + __IO uint8_t IMC011; /*!< Interrupt B Mode Control Register 011 */ + __IO uint8_t IMC012; /*!< Interrupt B Mode Control Register 012 */ + __IO uint8_t IMC013; /*!< Interrupt B Mode Control Register 013 */ + __IO uint8_t IMC014; /*!< Interrupt B Mode Control Register 014 */ + __IO uint8_t IMC015; /*!< Interrupt B Mode Control Register 015 */ + __IO uint8_t IMC016; /*!< Interrupt B Mode Control Register 016 */ + __IO uint8_t IMC017; /*!< Interrupt B Mode Control Register 017 */ + __IO uint8_t IMC018; /*!< Interrupt B Mode Control Register 018 */ + __IO uint8_t IMC019; /*!< Interrupt B Mode Control Register 019 */ + __IO uint8_t IMC020; /*!< Interrupt B Mode Control Register 020 */ + __IO uint8_t IMC021; /*!< Interrupt B Mode Control Register 021 */ + __IO uint8_t IMC022; /*!< Interrupt B Mode Control Register 022 */ + __IO uint8_t IMC023; /*!< Interrupt B Mode Control Register 023 */ + __IO uint8_t IMC024; /*!< Interrupt B Mode Control Register 024 */ + __IO uint8_t IMC025; /*!< Interrupt B Mode Control Register 025 */ + __IO uint8_t IMC026; /*!< Interrupt B Mode Control Register 026 */ + __IO uint8_t IMC027; /*!< Interrupt B Mode Control Register 027 */ + __IO uint8_t IMC028; /*!< Interrupt B Mode Control Register 028 */ + __IO uint8_t IMC029; /*!< Interrupt B Mode Control Register 029 */ + __IO uint8_t IMC030; /*!< Interrupt B Mode Control Register 030 */ + __IO uint8_t IMC031; /*!< Interrupt B Mode Control Register 031 */ + __IO uint8_t IMC032; /*!< Interrupt B Mode Control Register 032 */ + __IO uint8_t IMC033; /*!< Interrupt B Mode Control Register 033 */ + __IO uint8_t IMC034; /*!< Interrupt B Mode Control Register 034 */ + __IO uint8_t IMC035; /*!< Interrupt B Mode Control Register 035 */ + __IO uint8_t IMC036; /*!< Interrupt B Mode Control Register 036 */ + __IO uint8_t IMC037; /*!< Interrupt B Mode Control Register 037 */ + __IO uint8_t IMC038; /*!< Interrupt B Mode Control Register 038 */ + __IO uint8_t IMC039; /*!< Interrupt B Mode Control Register 039 */ + __IO uint8_t IMC040; /*!< Interrupt B Mode Control Register 040 */ + __IO uint8_t IMC041; /*!< Interrupt B Mode Control Register 041 */ + __IO uint8_t IMC042; /*!< Interrupt B Mode Control Register 042 */ + __IO uint8_t IMC043; /*!< Interrupt B Mode Control Register 043 */ + __IO uint8_t IMC044; /*!< Interrupt B Mode Control Register 044 */ + __IO uint8_t IMC045; /*!< Interrupt B Mode Control Register 045 */ + __IO uint8_t IMC046; /*!< Interrupt B Mode Control Register 046 */ + __IO uint8_t IMC047; /*!< Interrupt B Mode Control Register 047 */ + __IO uint8_t IMC048; /*!< Interrupt B Mode Control Register 048 */ + __IO uint8_t IMC049; /*!< Interrupt B Mode Control Register 049 */ + __IO uint8_t IMC050; /*!< Interrupt B Mode Control Register 050 */ + __IO uint8_t IMC051; /*!< Interrupt B Mode Control Register 051 */ + __IO uint8_t IMC052; /*!< Interrupt B Mode Control Register 052 */ + __IO uint8_t IMC053; /*!< Interrupt B Mode Control Register 053 */ + __IO uint8_t IMC054; /*!< Interrupt B Mode Control Register 054 */ + __IO uint8_t IMC055; /*!< Interrupt B Mode Control Register 055 */ + __IO uint8_t IMC056; /*!< Interrupt B Mode Control Register 056 */ + __IO uint8_t IMC057; /*!< Interrupt B Mode Control Register 057 */ + __IO uint8_t IMC058; /*!< Interrupt B Mode Control Register 058 */ + __IO uint8_t IMC059; /*!< Interrupt B Mode Control Register 059 */ + __IO uint8_t IMC060; /*!< Interrupt B Mode Control Register 060 */ + __IO uint8_t IMC061; /*!< Interrupt B Mode Control Register 061 */ + __IO uint8_t IMC062; /*!< Interrupt B Mode Control Register 062 */ + __IO uint8_t IMC063; /*!< Interrupt B Mode Control Register 063 */ + __IO uint8_t IMC064; /*!< Interrupt B Mode Control Register 064 */ + __IO uint8_t IMC065; /*!< Interrupt B Mode Control Register 065 */ + __IO uint8_t IMC066; /*!< Interrupt B Mode Control Register 066 */ + __IO uint8_t IMC067; /*!< Interrupt B Mode Control Register 067 */ + __IO uint8_t IMC068; /*!< Interrupt B Mode Control Register 068 */ + __IO uint8_t IMC069; /*!< Interrupt B Mode Control Register 069 */ + __IO uint8_t IMC070; /*!< Interrupt B Mode Control Register 070 */ + __IO uint8_t IMC071; /*!< Interrupt B Mode Control Register 071 */ + __IO uint8_t IMC072; /*!< Interrupt B Mode Control Register 072 */ + __IO uint8_t IMC073; /*!< Interrupt B Mode Control Register 073 */ + __IO uint8_t IMC074; /*!< Interrupt B Mode Control Register 074 */ + __IO uint8_t IMC075; /*!< Interrupt B Mode Control Register 075 */ + __IO uint8_t IMC076; /*!< Interrupt B Mode Control Register 076 */ + __IO uint8_t IMC077; /*!< Interrupt B Mode Control Register 077 */ + __IO uint8_t IMC078; /*!< Interrupt B Mode Control Register 078 */ + __IO uint8_t IMC079; /*!< Interrupt B Mode Control Register 079 */ + __IO uint8_t IMC080; /*!< Interrupt B Mode Control Register 080 */ + __IO uint8_t IMC081; /*!< Interrupt B Mode Control Register 081 */ + __IO uint8_t IMC082; /*!< Interrupt B Mode Control Register 082 */ + __IO uint8_t IMC083; /*!< Interrupt B Mode Control Register 083 */ + __IO uint8_t IMC084; /*!< Interrupt B Mode Control Register 084 */ + __IO uint8_t IMC085; /*!< Interrupt B Mode Control Register 085 */ + __IO uint8_t IMC086; /*!< Interrupt B Mode Control Register 086 */ + __IO uint8_t IMC087; /*!< Interrupt B Mode Control Register 087 */ + __IO uint8_t IMC088; /*!< Interrupt B Mode Control Register 088 */ + __IO uint8_t IMC089; /*!< Interrupt B Mode Control Register 089 */ + __IO uint8_t IMC090; /*!< Interrupt B Mode Control Register 090 */ + __IO uint8_t IMC091; /*!< Interrupt B Mode Control Register 091 */ + __IO uint8_t IMC092; /*!< Interrupt B Mode Control Register 092 */ + __IO uint8_t IMC093; /*!< Interrupt B Mode Control Register 093 */ + __IO uint8_t IMC094; /*!< Interrupt B Mode Control Register 094 */ + __IO uint8_t IMC095; /*!< Interrupt B Mode Control Register 095 */ + __IO uint8_t IMC096; /*!< Interrupt B Mode Control Register 096 */ + __IO uint8_t IMC097; /*!< Interrupt B Mode Control Register 097 */ + __IO uint8_t IMC098; /*!< Interrupt B Mode Control Register 098 */ + __IO uint8_t IMC099; /*!< Interrupt B Mode Control Register 099 */ + __IO uint8_t IMC100; /*!< Interrupt B Mode Control Register 100 */ + __IO uint8_t IMC101; /*!< Interrupt B Mode Control Register 101 */ + __IO uint8_t IMC102; /*!< Interrupt B Mode Control Register 102 */ + __IO uint8_t IMC103; /*!< Interrupt B Mode Control Register 103 */ + __IO uint8_t IMC104; /*!< Interrupt B Mode Control Register 104 */ + __IO uint8_t IMC105; /*!< Interrupt B Mode Control Register 105 */ + __IO uint8_t IMC106; /*!< Interrupt B Mode Control Register 106 */ + __IO uint8_t IMC107; /*!< Interrupt B Mode Control Register 107 */ + __IO uint8_t IMC108; /*!< Interrupt B Mode Control Register 108 */ + __IO uint8_t IMC109; /*!< Interrupt B Mode Control Register 109 */ + __IO uint8_t IMC110; /*!< Interrupt B Mode Control Register 110 */ + __IO uint8_t IMC111; /*!< Interrupt B Mode Control Register 111 */ + __IO uint8_t IMC112; /*!< Interrupt B Mode Control Register 112 */ + __IO uint8_t IMC113; /*!< Interrupt B Mode Control Register 113 */ + __IO uint8_t IMC114; /*!< Interrupt B Mode Control Register 114 */ + __IO uint8_t IMC115; /*!< Interrupt B Mode Control Register 115 */ + __IO uint8_t IMC116; /*!< Interrupt B Mode Control Register 116 */ + __IO uint8_t IMC117; /*!< Interrupt B Mode Control Register 117 */ + __IO uint8_t IMC118; /*!< Interrupt B Mode Control Register 118 */ + __IO uint8_t IMC119; /*!< Interrupt B Mode Control Register 119 */ + __IO uint8_t IMC120; /*!< Interrupt B Mode Control Register 120 */ + __IO uint8_t IMC121; /*!< Interrupt B Mode Control Register 121 */ + __IO uint8_t IMC122; /*!< Interrupt B Mode Control Register 122 */ + __IO uint8_t IMC123; /*!< Interrupt B Mode Control Register 123 */ + __IO uint8_t IMC124; /*!< Interrupt B Mode Control Register 124 */ + __IO uint8_t IMC125; /*!< Interrupt B Mode Control Register 125 */ + __IO uint8_t IMC126; /*!< Interrupt B Mode Control Register 126 */ + __IO uint8_t IMC127; /*!< Interrupt B Mode Control Register 127 */ + __IO uint8_t IMC128; /*!< Interrupt B Mode Control Register 128 */ + __IO uint8_t IMC129; /*!< Interrupt B Mode Control Register 129 */ + __IO uint8_t IMC130; /*!< Interrupt B Mode Control Register 130 */ + __IO uint8_t IMC131; /*!< Interrupt B Mode Control Register 131 */ + __IO uint8_t IMC132; /*!< Interrupt B Mode Control Register 132 */ + __IO uint8_t IMC133; /*!< Interrupt B Mode Control Register 133 */ + __IO uint8_t IMC134; /*!< Interrupt B Mode Control Register 134 */ + __IO uint8_t IMC135; /*!< Interrupt B Mode Control Register 135 */ + __IO uint8_t IMC136; /*!< Interrupt B Mode Control Register 136 */ + __IO uint8_t IMC137; /*!< Interrupt B Mode Control Register 137 */ + __IO uint8_t IMC138; /*!< Interrupt B Mode Control Register 138 */ + __IO uint8_t IMC139; /*!< Interrupt B Mode Control Register 139 */ + __IO uint8_t IMC140; /*!< Interrupt B Mode Control Register 140 */ + __IO uint8_t IMC141; /*!< Interrupt B Mode Control Register 141 */ + uint8_t RESERVED2[3]; + __IO uint8_t IMC145; /*!< Interrupt B Mode Control Register 145 */ + __IO uint8_t IMC146; /*!< Interrupt B Mode Control Register 146 */ + __IO uint8_t IMC147; /*!< Interrupt B Mode Control Register 147 */ + __IO uint8_t IMC148; /*!< Interrupt B Mode Control Register 148 */ + __IO uint8_t IMC149; /*!< Interrupt B Mode Control Register 149 */ + __IO uint8_t IMC150; /*!< Interrupt B Mode Control Register 150 */ + __IO uint8_t IMC151; /*!< Interrupt B Mode Control Register 151 */ + __IO uint8_t IMC152; /*!< Interrupt B Mode Control Register 152 */ + __IO uint8_t IMC153; /*!< Interrupt B Mode Control Register 153 */ + __IO uint8_t IMC154; /*!< Interrupt B Mode Control Register 154 */ + __IO uint8_t IMC155; /*!< Interrupt B Mode Control Register 155 */ + __IO uint8_t IMC156; /*!< Interrupt B Mode Control Register 156 */ + __IO uint8_t IMC157; /*!< Interrupt B Mode Control Register 157 */ + __IO uint8_t IMC158; /*!< Interrupt B Mode Control Register 158 */ + __IO uint8_t IMC159; /*!< Interrupt B Mode Control Register 159 */ +} TSB_IB_TypeDef; + +/** + * @brief Interrupt Monitor Register + */ +typedef struct { + __I uint32_t FLGNMI; /*!< Non-maskable Interrupt Monitor Flag Register Register*/ + __I uint32_t FLG1; /*!< Interrupt Monitor Flag Register 1 (032 - 063)*/ + __I uint32_t FLG2; /*!< Interrupt Monitor Flag Register 2 (064 - 095)*/ + __I uint32_t FLG3; /*!< Interrupt Monitor Flag Register 3 (096 - 127)*/ + __I uint32_t FLG4; /*!< Interrupt Monitor Flag Register 4 (128 - 159)*/ + __I uint32_t FLG5; /*!< Interrupt Monitor Flag Register 5 (160 - 191)*/ + __I uint32_t FLG6; /*!< Interrupt Monitor Flag Register 6 (192 - 223)*/ + __I uint32_t FLG7; /*!< Interrupt Monitor Flag Register 7 (224 - 255)*/ +} TSB_IMN_TypeDef; + +/** + * @brief DNF + */ +typedef struct { + __IO uint32_t CKCR; /*!< DNF Unit A Noise Filter Control Register */ + __IO uint32_t ENCR; /*!< DNF Unit A Noise Filter Enable Register */ +} TSB_DNF_TypeDef; + +/** + * @brief Watchdog Timer (SIWDT) + */ +typedef struct { + __IO uint32_t PRO; /*!< SIWDT Protect Register */ + __IO uint32_t EN; /*!< SIWDT Enable Register */ + __O uint32_t CR; /*!< SIWDT Control Register */ + __IO uint32_t MOD; /*!< SIWDT Mode Register */ + __I uint32_t MONI; /*!< SIWDT Count Monitor Register */ +} TSB_SIWD_TypeDef; + +/** + * @brief NBDIF + */ +typedef struct { + __IO uint32_t CR0; /*!< NBDIF control register 0 */ + __IO uint32_t CR1; /*!< NBDIF control register 1 */ +} TSB_NBD_TypeDef; + +/** + * @brief Malti Porpose Direct Memory Accsess(MDMA) + */ +typedef struct { + uint32_t RESERVED0; + __IO uint32_t CEN; /*!< MDMA Transfer Channel Enable Register */ + __IO uint32_t REQ; /*!< MDMA Transfer Request Register */ + __IO uint32_t SUS; /*!< MDMA Transfer Suspension Register */ + __IO uint32_t ACT; /*!< MDMA Transfer Active Register */ + __IO uint32_t END; /*!< MDMA Transfer End Register */ + __IO uint32_t PRI; /*!< MDMA Transfer Priority Setting Register */ + __IO uint32_t ENE; /*!< MDMA Transfer Completion Interrupt Enable Register*/ + __IO uint32_t DTAB; /*!< MDMA Transfer Descriptor Table Start Address Register*/ + uint32_t RESERVED1; + __I uint32_t CHN; /*!< MDMA Transfer Execution Channel Number Register*/ + __I uint32_t XFTYP; /*!< MDMA Transfer Type Register */ + __I uint32_t XFSAD; /*!< MDMA Transfer Source Address Register */ + __I uint32_t XFDAD; /*!< MDMA Transfer Destination Address Register */ + __I uint32_t XFSIZ; /*!< MDMA Transfer Size Register */ + __I uint32_t DSADS; /*!< MDMA Transfer Descriptor Storage Address Register*/ + __I uint32_t DSNUM; /*!< MDMA Transfer Descriptor Count Register */ + uint32_t RESERVED2; + __IO uint32_t DEND; /*!< MDMA Descriptor End Register */ + __IO uint32_t DENE; /*!< MDMA Descriptor Completion Interrupt Enable Register*/ + __I uint32_t C00XFTYP; /*!< MDMA ch 00 Transfer Type Saving Register */ + __I uint32_t C00XFSAD; /*!< MDMA ch 00 Transfer Source Address Saving Register*/ + __I uint32_t C00XFDAD; /*!< MDMA ch 00 Transfer Destination Address Saving Register*/ + __I uint32_t C00XFSIZ; /*!< MDMA ch 00 Transfer Size Saving Register */ + __I uint32_t C00DSADS; /*!< MDMA ch 00 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C00DSNUM; /*!< MDMA ch 00 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED3[2]; + __I uint32_t C01XFTYP; /*!< MDMA ch 01 Transfer Type Saving Register */ + __I uint32_t C01XFSAD; /*!< MDMA ch 01 Transfer Source Address Saving Register*/ + __I uint32_t C01XFDAD; /*!< MDMA ch 01 Transfer Destination Address Saving Register*/ + __I uint32_t C01XFSIZ; /*!< MDMA ch 01 Transfer Size Saving Register */ + __I uint32_t C01DSADS; /*!< MDMA ch 01 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C01DSNUM; /*!< MDMA ch 01 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED4[2]; + __I uint32_t C02XFTYP; /*!< MDMA ch 02 Transfer Type Saving Register */ + __I uint32_t C02XFSAD; /*!< MDMA ch 02 Transfer Source Address Saving Register*/ + __I uint32_t C02XFDAD; /*!< MDMA ch 02 Transfer Destination Address Saving Register*/ + __I uint32_t C02XFSIZ; /*!< MDMA ch 02 Transfer Size Saving Register */ + __I uint32_t C02DSADS; /*!< MDMA ch 02 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C02DSNUM; /*!< MDMA ch 02 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED5[2]; + __I uint32_t C03XFTYP; /*!< MDMA ch 03 Transfer Type Saving Register */ + __I uint32_t C03XFSAD; /*!< MDMA ch 03 Transfer Source Address Saving Register*/ + __I uint32_t C03XFDAD; /*!< MDMA ch 03 Transfer Destination Address Saving Register*/ + __I uint32_t C03XFSIZ; /*!< MDMA ch 03 Transfer Size Saving Register */ + __I uint32_t C03DSADS; /*!< MDMA ch 03 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C03DSNUM; /*!< MDMA ch 03 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED6[2]; + __I uint32_t C04XFTYP; /*!< MDMA ch 04 Transfer Type Saving Register */ + __I uint32_t C04XFSAD; /*!< MDMA ch 04 Transfer Source Address Saving Register*/ + __I uint32_t C04XFDAD; /*!< MDMA ch 04 Transfer Destination Address Saving Register*/ + __I uint32_t C04XFSIZ; /*!< MDMA ch 04 Transfer Size Saving Register */ + __I uint32_t C04DSADS; /*!< MDMA ch 04 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C04DSNUM; /*!< MDMA ch 04 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED7[2]; + __I uint32_t C05XFTYP; /*!< MDMA ch 05 Transfer Type Saving Register */ + __I uint32_t C05XFSAD; /*!< MDMA ch 05 Transfer Source Address Saving Register*/ + __I uint32_t C05XFDAD; /*!< MDMA ch 05 Transfer Destination Address Saving Register*/ + __I uint32_t C05XFSIZ; /*!< MDMA ch 05 Transfer Size Saving Register */ + __I uint32_t C05DSADS; /*!< MDMA ch 05 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C05DSNUM; /*!< MDMA ch 05 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED8[2]; + __I uint32_t C06XFTYP; /*!< MDMA ch 06 Transfer Type Saving Register */ + __I uint32_t C06XFSAD; /*!< MDMA ch 06 Transfer Source Address Saving Register*/ + __I uint32_t C06XFDAD; /*!< MDMA ch 06 Transfer Destination Address Saving Register*/ + __I uint32_t C06XFSIZ; /*!< MDMA ch 06 Transfer Size Saving Register */ + __I uint32_t C06DSADS; /*!< MDMA ch 06 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C06DSNUM; /*!< MDMA ch 06 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED9[2]; + __I uint32_t C07XFTYP; /*!< MDMA ch 07 Transfer Type Saving Register */ + __I uint32_t C07XFSAD; /*!< MDMA ch 07 Transfer Source Address Saving Register*/ + __I uint32_t C07XFDAD; /*!< MDMA ch 07 Transfer Destination Address Saving Register*/ + __I uint32_t C07XFSIZ; /*!< MDMA ch 07 Transfer Size Saving Register */ + __I uint32_t C07DSADS; /*!< MDMA ch 07 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C07DSNUM; /*!< MDMA ch 07 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED10[2]; + __I uint32_t C08XFTYP; /*!< MDMA ch 08 Transfer Type Saving Register */ + __I uint32_t C08XFSAD; /*!< MDMA ch 08 Transfer Source Address Saving Register*/ + __I uint32_t C08XFDAD; /*!< MDMA ch 08 Transfer Destination Address Saving Register*/ + __I uint32_t C08XFSIZ; /*!< MDMA ch 08 Transfer Size Saving Register */ + __I uint32_t C08DSADS; /*!< MDMA ch 08 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C08DSNUM; /*!< MDMA ch 08 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED11[2]; + __I uint32_t C09XFTYP; /*!< MDMA ch n Transfer Type Saving Register */ + __I uint32_t C09XFSAD; /*!< MDMA ch n Transfer Source Address Saving Register*/ + __I uint32_t C09XFDAD; /*!< MDMA ch n Transfer Destination Address Saving Register*/ + __I uint32_t C09XFSIZ; /*!< MDMA ch n Transfer Size Saving Register */ + __I uint32_t C09DSADS; /*!< MDMA ch n Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C09DSNUM; /*!< MDMA ch n Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED12[2]; + __I uint32_t C10XFTYP; /*!< MDMA ch 10 Transfer Type Saving Register */ + __I uint32_t C10XFSAD; /*!< MDMA ch 10 Transfer Source Address Saving Register*/ + __I uint32_t C10XFDAD; /*!< MDMA ch 10 Transfer Destination Address Saving Register*/ + __I uint32_t C10XFSIZ; /*!< MDMA ch 10 Transfer Size Saving Register */ + __I uint32_t C10DSADS; /*!< MDMA ch 10 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C10DSNUM; /*!< MDMA ch 10 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED13[2]; + __I uint32_t C11XFTYP; /*!< MDMA ch 11 Transfer Type Saving Register */ + __I uint32_t C11XFSAD; /*!< MDMA ch 11 Transfer Source Address Saving Register*/ + __I uint32_t C11XFDAD; /*!< MDMA ch 11 Transfer Destination Address Saving Register*/ + __I uint32_t C11XFSIZ; /*!< MDMA ch 11 Transfer Size Saving Register */ + __I uint32_t C11DSADS; /*!< MDMA ch 11 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C11DSNUM; /*!< MDMA ch 11 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED14[2]; + __I uint32_t C12XFTYP; /*!< MDMA ch 12 Transfer Type Saving Register */ + __I uint32_t C12XFSAD; /*!< MDMA ch 12 Transfer Source Address Saving Register*/ + __I uint32_t C12XFDAD; /*!< MDMA ch 12 Transfer Destination Address Saving Register*/ + __I uint32_t C12XFSIZ; /*!< MDMA ch 12 Transfer Size Saving Register */ + __I uint32_t C12DSADS; /*!< MDMA ch 12 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C12DSNUM; /*!< MDMA ch 12 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED15[2]; + __I uint32_t C13XFTYP; /*!< MDMA ch 13 Transfer Type Saving Register */ + __I uint32_t C13XFSAD; /*!< MDMA ch 13 Transfer Source Address Saving Register*/ + __I uint32_t C13XFDAD; /*!< MDMA ch 13 Transfer Destination Address Saving Register*/ + __I uint32_t C13XFSIZ; /*!< MDMA ch 13 Transfer Size Saving Register */ + __I uint32_t C13DSADS; /*!< MDMA ch 13 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C13DSNUM; /*!< MDMA ch 13 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED16[2]; + __I uint32_t C14XFTYP; /*!< MDMA ch 14 Transfer Type Saving Register */ + __I uint32_t C14XFSAD; /*!< MDMA ch 14 Transfer Source Address Saving Register*/ + __I uint32_t C14XFDAD; /*!< MDMA ch 14 Transfer Destination Address Saving Register*/ + __I uint32_t C14XFSIZ; /*!< MDMA ch 14 Transfer Size Saving Register */ + __I uint32_t C14DSADS; /*!< MDMA ch 14 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C14DSNUM; /*!< MDMA ch 14 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED17[2]; + __I uint32_t C15XFTYP; /*!< MDMA ch 15 Transfer Type Saving Register */ + __I uint32_t C15XFSAD; /*!< MDMA ch 15 Transfer Source Address Saving Register*/ + __I uint32_t C15XFDAD; /*!< MDMA ch 15 Transfer Destination Address Saving Register*/ + __I uint32_t C15XFSIZ; /*!< MDMA ch 15 Transfer Size Saving Register */ + __I uint32_t C15DSADS; /*!< MDMA ch 15 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C15DSNUM; /*!< MDMA ch 15 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED18[2]; + __I uint32_t C16XFTYP; /*!< MDMA ch 16 Transfer Type Saving Register */ + __I uint32_t C16XFSAD; /*!< MDMA ch 16 Transfer Source Address Saving Register*/ + __I uint32_t C16XFDAD; /*!< MDMA ch 16 Transfer Destination Address Saving Register*/ + __I uint32_t C16XFSIZ; /*!< MDMA ch 16 Transfer Size Saving Register */ + __I uint32_t C16DSADS; /*!< MDMA ch 16 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C16DSNUM; /*!< MDMA ch 16 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED19[2]; + __I uint32_t C17XFTYP; /*!< MDMA ch 17 Transfer Type Saving Register */ + __I uint32_t C17XFSAD; /*!< MDMA ch 17 Transfer Source Address Saving Register*/ + __I uint32_t C17XFDAD; /*!< MDMA ch 17 Transfer Destination Address Saving Register*/ + __I uint32_t C17XFSIZ; /*!< MDMA ch 17 Transfer Size Saving Register */ + __I uint32_t C17DSADS; /*!< MDMA ch 17 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C17DSNUM; /*!< MDMA ch 17 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED20[2]; + __I uint32_t C18XFTYP; /*!< MDMA ch 18 Transfer Type Saving Register */ + __I uint32_t C18XFSAD; /*!< MDMA ch 18 Transfer Source Address Saving Register*/ + __I uint32_t C18XFDAD; /*!< MDMA ch 18 Transfer Destination Address Saving Register*/ + __I uint32_t C18XFSIZ; /*!< MDMA ch 18 Transfer Size Saving Register */ + __I uint32_t C18DSADS; /*!< MDMA ch 18 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C18DSNUM; /*!< MDMA ch 18 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED21[2]; + __I uint32_t C19XFTYP; /*!< MDMA ch 19 Transfer Type Saving Register */ + __I uint32_t C19XFSAD; /*!< MDMA ch 19 Transfer Source Address Saving Register*/ + __I uint32_t C19XFDAD; /*!< MDMA ch 19 Transfer Destination Address Saving Register*/ + __I uint32_t C19XFSIZ; /*!< MDMA ch 19 Transfer Size Saving Register */ + __I uint32_t C19DSADS; /*!< MDMA ch 19 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C19DSNUM; /*!< MDMA ch 19 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED22[2]; + __I uint32_t C20XFTYP; /*!< MDMA ch 20 Transfer Type Saving Register */ + __I uint32_t C20XFSAD; /*!< MDMA ch 20 Transfer Source Address Saving Register*/ + __I uint32_t C20XFDAD; /*!< MDMA ch 20 Transfer Destination Address Saving Register*/ + __I uint32_t C20XFSIZ; /*!< MDMA ch 20 Transfer Size Saving Register */ + __I uint32_t C20DSADS; /*!< MDMA ch 20 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C20DSNUM; /*!< MDMA ch 20 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED23[2]; + __I uint32_t C21XFTYP; /*!< MDMA ch 21 Transfer Type Saving Register */ + __I uint32_t C21XFSAD; /*!< MDMA ch 21 Transfer Source Address Saving Register*/ + __I uint32_t C21XFDAD; /*!< MDMA ch 21 Transfer Destination Address Saving Register*/ + __I uint32_t C21XFSIZ; /*!< MDMA ch 21 Transfer Size Saving Register */ + __I uint32_t C21DSADS; /*!< MDMA ch 21 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C21DSNUM; /*!< MDMA ch 21 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED24[2]; + __I uint32_t C22XFTYP; /*!< MDMA ch 22 Transfer Type Saving Register */ + __I uint32_t C22XFSAD; /*!< MDMA ch 22 Transfer Source Address Saving Register*/ + __I uint32_t C22XFDAD; /*!< MDMA ch 22 Transfer Destination Address Saving Register*/ + __I uint32_t C22XFSIZ; /*!< MDMA ch 22 Transfer Size Saving Register */ + __I uint32_t C22DSADS; /*!< MDMA ch 22 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C22DSNUM; /*!< MDMA ch 22 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED25[2]; + __I uint32_t C23XFTYP; /*!< MDMA ch 23 Transfer Type Saving Register */ + __I uint32_t C23XFSAD; /*!< MDMA ch 23 Transfer Source Address Saving Register*/ + __I uint32_t C23XFDAD; /*!< MDMA ch 23 Transfer Destination Address Saving Register*/ + __I uint32_t C23XFSIZ; /*!< MDMA ch 23 Transfer Size Saving Register */ + __I uint32_t C23DSADS; /*!< MDMA ch 23 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C23DSNUM; /*!< MDMA ch 23 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED26[2]; + __I uint32_t C24XFTYP; /*!< MDMA ch 24 Transfer Type Saving Register */ + __I uint32_t C24XFSAD; /*!< MDMA ch 24 Transfer Source Address Saving Register*/ + __I uint32_t C24XFDAD; /*!< MDMA ch 24 Transfer Destination Address Saving Register*/ + __I uint32_t C24XFSIZ; /*!< MDMA ch 24 Transfer Size Saving Register */ + __I uint32_t C24DSADS; /*!< MDMA ch 24 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C24DSNUM; /*!< MDMA ch 24 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED27[2]; + __I uint32_t C25XFTYP; /*!< MDMA ch 25 Transfer Type Saving Register */ + __I uint32_t C25XFSAD; /*!< MDMA ch 25 Transfer Source Address Saving Register*/ + __I uint32_t C25XFDAD; /*!< MDMA ch 25 Transfer Destination Address Saving Register*/ + __I uint32_t C25XFSIZ; /*!< MDMA ch 25 Transfer Size Saving Register */ + __I uint32_t C25DSADS; /*!< MDMA ch 25 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C25DSNUM; /*!< MDMA ch 25 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED28[2]; + __I uint32_t C26XFTYP; /*!< MDMA ch 26 Transfer Type Saving Register */ + __I uint32_t C26XFSAD; /*!< MDMA ch 26 Transfer Source Address Saving Register*/ + __I uint32_t C26XFDAD; /*!< MDMA ch 26 Transfer Destination Address Saving Register*/ + __I uint32_t C26XFSIZ; /*!< MDMA ch 26 Transfer Size Saving Register */ + __I uint32_t C26DSADS; /*!< MDMA ch 26 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C26DSNUM; /*!< MDMA ch 26 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED29[2]; + __I uint32_t C27XFTYP; /*!< MDMA ch 27 Transfer Type Saving Register */ + __I uint32_t C27XFSAD; /*!< MDMA ch 27 Transfer Source Address Saving Register*/ + __I uint32_t C27XFDAD; /*!< MDMA ch 27 Transfer Destination Address Saving Register*/ + __I uint32_t C27XFSIZ; /*!< MDMA ch 27 Transfer Size Saving Register */ + __I uint32_t C27DSADS; /*!< MDMA ch 27 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C27DSNUM; /*!< MDMA ch 27 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED30[2]; + __I uint32_t C28XFTYP; /*!< MDMA ch 28 Transfer Type Saving Register */ + __I uint32_t C28XFSAD; /*!< MDMA ch 28 Transfer Source Address Saving Register*/ + __I uint32_t C28XFDAD; /*!< MDMA ch 28 Transfer Destination Address Saving Register*/ + __I uint32_t C28XFSIZ; /*!< MDMA ch 28 Transfer Size Saving Register */ + __I uint32_t C28DSADS; /*!< MDMA ch 28 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C28DSNUM; /*!< MDMA ch 28 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED31[2]; + __I uint32_t C29XFTYP; /*!< MDMA ch 29 Transfer Type Saving Register */ + __I uint32_t C29XFSAD; /*!< MDMA ch 29 Transfer Source Address Saving Register*/ + __I uint32_t C29XFDAD; /*!< MDMA ch 29 Transfer Destination Address Saving Register*/ + __I uint32_t C29XFSIZ; /*!< MDMA ch 29 Transfer Size Saving Register */ + __I uint32_t C29DSADS; /*!< MDMA ch 29 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C29DSNUM; /*!< MDMA ch 29 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED32[2]; + __I uint32_t C30XFTYP; /*!< MDMA ch 30 Transfer Type Saving Register */ + __I uint32_t C30XFSAD; /*!< MDMA ch 30 Transfer Source Address Saving Register*/ + __I uint32_t C30XFDAD; /*!< MDMA ch 30 Transfer Destination Address Saving Register*/ + __I uint32_t C30XFSIZ; /*!< MDMA ch 30 Transfer Size Saving Register */ + __I uint32_t C30DSADS; /*!< MDMA ch 30 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C30DSNUM; /*!< MDMA ch 30 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED33[2]; + __I uint32_t C31XFTYP; /*!< MDMA ch 31 Transfer Type Saving Register */ + __I uint32_t C31XFSAD; /*!< MDMA ch 31 Transfer Source Address Saving Register*/ + __I uint32_t C31XFDAD; /*!< MDMA ch 31 Transfer Destination Address Saving Register*/ + __I uint32_t C31XFSIZ; /*!< MDMA ch 31 Transfer Size Saving Register */ + __I uint32_t C31DSADS; /*!< MDMA ch 31 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C31DSNUM; /*!< MDMA ch 31 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED34[238]; + __IO uint32_t MSK; /*!< MDMA Transfer Request Mask Register */ +} TSB_MDMA_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief ARM Prime Cell PL011 + */ +typedef struct { + __IO uint32_t DR; /*!< FUART Data Register */ + union { + __I uint32_t RSR; /*!< FUART Receive Status Register */ + __O uint32_t ECR; /*!< FUART Error Clear Register */ + }; + uint32_t RESERVED0[4]; + __I uint32_t FR; /*!< FUART Flag Register */ + uint32_t RESERVED1; + __IO uint32_t ILPR; /*!< FUART IrDA Low-power Counter register */ + __IO uint32_t BRD; /*!< FUART Integer Baud Rate Register */ + __IO uint32_t FBRD; /*!< FUART Fractional Baud Rate Register */ + __IO uint32_t LCR_H; /*!< FUART Line Control Register */ + __IO uint32_t CR; /*!< FUART Cntrol Register */ + __IO uint32_t IFLS; /*!< FUART Interrupt FIFO Level Select Register */ + __IO uint32_t IMSC; /*!< FUART Interrupt Mask Set/Clear Register */ + __I uint32_t RIS; /*!< FUART Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< FUART Masked Interrupt Status Register */ + __O uint32_t ICR; /*!< FUART Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< FUART DMA Control Register */ +} TSB_FURT_TypeDef; + +/** + * @brief ADC + */ +typedef struct { + __IO uint32_t CR0; /*!< AD Control Register 0 */ + __IO uint32_t CR1; /*!< AD Control Register 1 */ + __I uint32_t ST; /*!< AD Status Register */ + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Setting Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Setting Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Setting Register 2 */ + uint32_t RESERVED0; + __IO uint32_t CMPEN; /*!< Monitor function Enable Register */ + __IO uint32_t CMPCR0; /*!< AD Monitor function Setting Register 0 */ + __IO uint32_t CMPCR1; /*!< AD Monitor function Setting Register 1 */ + __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ + __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ + uint32_t RESERVED1[34]; + __IO uint32_t EXAZSEL; /*!< AD External AIN sampling period selection Register*/ + __IO uint32_t TSET0; /*!< AD Start-up Factor Program Register 0 */ + __IO uint32_t TSET1; /*!< AD Start-up Factor Program Register 1 */ + __IO uint32_t TSET2; /*!< AD Start-up Factor Program Register 2 */ + __IO uint32_t TSET3; /*!< AD Start-up Factor Program Register 3 */ + __IO uint32_t TSET4; /*!< AD Start-up Factor Program Register 4 */ + __IO uint32_t TSET5; /*!< AD Start-up Factor Program Register 5 */ + __IO uint32_t TSET6; /*!< AD Start-up Factor Program Register 6 */ + __IO uint32_t TSET7; /*!< AD Start-up Factor Program Register 7 */ + __IO uint32_t TSET8; /*!< AD Start-up Factor Program Register 8 */ + __IO uint32_t TSET9; /*!< AD Start-up Factor Program Register 9 */ + __IO uint32_t TSET10; /*!< AD Start-up Factor Program Register 10 */ + __IO uint32_t TSET11; /*!< AD Start-up Factor Program Register 11 */ + __IO uint32_t TSET12; /*!< AD Start-up Factor Program Register 12 */ + __IO uint32_t TSET13; /*!< AD Start-up Factor Program Register 13 */ + __IO uint32_t TSET14; /*!< AD Start-up Factor Program Register 14 */ + __IO uint32_t TSET15; /*!< AD Start-up Factor Program Register 15 */ + __IO uint32_t TSET16; /*!< AD Start-up Factor Program Register 16 */ + __IO uint32_t TSET17; /*!< AD Start-up Factor Program Register 17 */ + __IO uint32_t TSET18; /*!< AD Start-up Factor Program Register 18 */ + __IO uint32_t TSET19; /*!< AD Start-up Factor Program Register 19 */ + __IO uint32_t TSET20; /*!< AD Start-up Factor Program Register 20 */ + __IO uint32_t TSET21; /*!< AD Start-up Factor Program Register 21 */ + __IO uint32_t TSET22; /*!< AD Start-up Factor Program Register 22 */ + __IO uint32_t TSET23; /*!< AD Start-up Factor Program Register 23 */ + uint32_t RESERVED2[8]; + __I uint32_t REG0; /*!< AD Conversion Result Storage Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Storage Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Storage Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Storage Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Storage Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Storage Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Storage Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Storage Register 7 */ + __I uint32_t REG8; /*!< AD Conversion Result Storage Register 8 */ + __I uint32_t REG9; /*!< AD Conversion Result Storage Register 9 */ + __I uint32_t REG10; /*!< AD Conversion Result Storage Register 10 */ + __I uint32_t REG11; /*!< AD Conversion Result Storage Register 11 */ + __I uint32_t REG12; /*!< AD Conversion Result Storage Register 12 */ + __I uint32_t REG13; /*!< AD Conversion Result Storage Register 13 */ + __I uint32_t REG14; /*!< AD Conversion Result Storage Register 14 */ + __I uint32_t REG15; /*!< AD Conversion Result Storage Register 15 */ + __I uint32_t REG16; /*!< AD Conversion Result Storage Register 16 */ + __I uint32_t REG17; /*!< AD Conversion Result Storage Register 17 */ + __I uint32_t REG18; /*!< AD Conversion Result Storage Register 18 */ + __I uint32_t REG19; /*!< AD Conversion Result Storage Register 19 */ + __I uint32_t REG20; /*!< AD Conversion Result Storage Register 20 */ + __I uint32_t REG21; /*!< AD Conversion Result Storage Register 21 */ + __I uint32_t REG22; /*!< AD Conversion Result Storage Register 22 */ + __I uint32_t REG23; /*!< AD Conversion Result Storage Register 23 */ +} TSB_AD_TypeDef; + +/** + * @brief Digital analog converter (DAC) + */ +typedef struct { + __IO uint32_t CR; /*!< DAC Control Register */ + __IO uint32_t REG; /*!< DAC Converted Value Setting Register */ +} TSB_DA_TypeDef; + +/** + * @brief 16-bit Timer/Event Counter (TB) + */ +typedef struct { + __IO uint32_t MOD; /*!< T32A Mode Register */ + uint32_t RESERVED0[15]; + __IO uint32_t RUNA; /*!< T32A Run Register A */ + __IO uint32_t CRA; /*!< T32A Counter Control Register A */ + __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */ + __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */ + __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */ + __IO uint32_t STA; /*!< T32A Status Register A */ + __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */ + __I uint32_t TMRA; /*!< T32A Counter Capture Register A */ + __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ + __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ + __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ + __I uint32_t CAPA0; /*!< T32A Timer Capture A0 Register */ + __I uint32_t CAPA1; /*!< T32A Timer Cupture A1 Register */ + __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */ + uint32_t RESERVED1[2]; + __IO uint32_t RUNB; /*!< T32A Run Register B */ + __IO uint32_t CRB; /*!< T32A Counter Control Register B */ + __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */ + __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */ + __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */ + __IO uint32_t STB; /*!< T32A Status Register B */ + __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */ + __I uint32_t TMRB; /*!< T32A Counter Capture Register B */ + __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ + __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ + __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ + __I uint32_t CAPB0; /*!< T32A Timer Capture B0 Register */ + __I uint32_t CAPB1; /*!< T32A Timer Capture B1 Register */ + __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ + uint32_t RESERVED2[2]; + __IO uint32_t RUNC; /*!< T32A Run Register C */ + __IO uint32_t CRC; /*!< T32A Counter Control Register C */ + __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */ + __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */ + __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */ + __IO uint32_t STC; /*!< T32A Status Register C */ + __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */ + __I uint32_t TMRC; /*!< T32A Counter Capture Register C */ + __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ + __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ + __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ + __I uint32_t CAPC0; /*!< T32A Timer Capture C0 Register */ + __I uint32_t CAPC1; /*!< T32A Capture Register C1 */ + __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */ + __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */ +} TSB_T32A_TypeDef; + +/** + * @brief TSSI + */ +typedef struct { + __IO uint32_t CR0; /*!< TSSI Control Register 0 */ + __IO uint32_t CR1; /*!< TSSI Control Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t CPR; /*!< TSSI Clock Divider Register */ + uint32_t RESERVED1[11]; + __IO uint32_t RCMR; /*!< TSSI Receive Clock / Mode Control Register */ + __IO uint32_t RFMR; /*!< TSSI Receive Data Frame Control Register */ + __IO uint32_t RCR; /*!< TSSI Receive Data Comparison Register */ + __IO uint32_t RDMACR; /*!< TSSI Receive DMA Control Register */ + uint32_t RESERVED2[4]; + __IO uint32_t RSR; /*!< TSSI Reception Status Register */ + __IO uint32_t RIER; /*!< TSSI Receive Interrupt Enable Register */ + uint32_t RESERVED3[2]; + __IO uint32_t RFTLR; /*!< TSSI Receive FIFO Threshold Register */ + __I uint32_t RFLR; /*!< TSSI Receive FIFO Entry Register */ + uint32_t RESERVED4[2]; + __I uint32_t RDR0; /*!< TSSI Receive Data Register 0 */ + __I uint32_t RDR1; /*!< TSSI Receive Data Register 1 */ + __I uint32_t RDR2; /*!< TSSI Receive Data Register 2 */ + __I uint32_t RDR3; /*!< TSSI Receive Data Register 3 */ + uint32_t RESERVED5[4]; + __IO uint32_t TCMR; /*!< TSSI Transmit Clock / Mode Control Register */ + __IO uint32_t TFMR; /*!< TSSI Transmit Data Frame Control Register */ + uint32_t RESERVED6; + __IO uint32_t TDMACR; /*!< TSSI Transmit DMA Control Register */ + uint32_t RESERVED7[4]; + __IO uint32_t TSR; /*!< TSSI Transmission Status Register */ + __IO uint32_t TIER; /*!< TSSI Transmission Interrupt Enable Register */ + uint32_t RESERVED8[2]; + __IO uint32_t TFTLR; /*!< TSSI Transmit FIFO Threshold Register */ + __I uint32_t TFLR; /*!< TSSI Transmit FIFO Entry Register */ + uint32_t RESERVED9[2]; + __O uint32_t TDR0; /*!< TSSI Transmission Data Register 0 */ + __O uint32_t TDR1; /*!< TSSI Transmission Data Register 1 */ + __O uint32_t TDR2; /*!< TSSI Transmission Data Register 2 */ + __O uint32_t TDR3; /*!< TSSI Transmission Data Register 3 */ +} TSB_TSSI_TypeDef; + +/** + * @brief UART + */ +typedef struct { + __IO uint32_t SWRST; /*!< UART Software Reset Register */ + __IO uint32_t CR0; /*!< UART Control Register 0 */ + __IO uint32_t CR1; /*!< UART Control Register 1 */ + __IO uint32_t CLK; /*!< UART Clock Control Register */ + __IO uint32_t BRD; /*!< UART Baud Rate Register */ + __IO uint32_t TRANS; /*!< UART Transfer Enable Register */ + __IO uint32_t DR; /*!< UART Data Register */ + __IO uint32_t SR; /*!< UART Status Register */ + __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */ + __IO uint32_t ERR; /*!< UART Error Register */ +} TSB_UART_TypeDef; + +/** + * @brief I2S interface + */ +typedef struct { + uint32_t RESERVED0; + __IO uint32_t CSTART; /*!< I2S Clock LRCK Generation Start Register */ + __I uint32_t CBUSY; /*!< I2S Clock LRCK Generation Status Register */ + __IO uint32_t CSTOP; /*!< I2S Clock LRCK Generation Stop Register */ + __IO uint32_t CAUDIOSET; /*!< I2S Clock AUDIOSET Register */ + uint32_t RESERVED1[11]; + __I uint32_t CREGBUSY; /*!< I2S Clock REGBUSY Register */ + uint32_t RESERVED2[45]; + __IO uint32_t CMODESET; /*!< I2S Clock Audio Data Format Setting Register */ + uint32_t RESERVED3[65]; + __IO uint32_t CMS_SEL; /*!< I2S Clock Master/Slave Select Register */ + __IO uint32_t CMCLK_IO_SEL; /*!< I2S Clock MCLK pin input/output Selection Register*/ + uint32_t RESERVED4[3]; + __IO uint32_t CPHT_DIV; /*!< I2S Clock Phi T0 Frequency Division Setting Register*/ + __IO uint32_t CPHT_DIVOUT_EN; /*!< I2S Clock Phi T0 Divided Clock Output Enable Register*/ + uint32_t RESERVED5; + __IO uint32_t CBCK_SRC_SEL; /*!< I2S Clock BCK Source Clock Select Register */ + __IO uint32_t CBCK_DIV; /*!< I2S Clock BCK Frequency Division Setting Register*/ + __IO uint32_t CBCK_DIVOUT_EN; /*!< I2S Clock BCK Output Enable Register */ + uint32_t RESERVED6[118]; + __IO uint32_t ISTART; /*!< I2S Receive Control Start Register */ + __I uint32_t IBUSY; /*!< I2S Receive Operation Status Register */ + __IO uint32_t ISTOP; /*!< I2S Data Receive Stop Register */ + __IO uint32_t IAUDIOSET; /*!< I2S Receive AUDIOSET Register */ + __I uint32_t IINTSTAT; /*!< I2S Receive Control Interrupt Status Register*/ + __IO uint32_t IINTMASK; /*!< I2S Receive Control Interrupt Mask Register */ + __IO uint32_t IINTCLR; /*!< I2S Receive Control Interrupt Clear Register */ + uint32_t RESERVED7; + __IO uint32_t IMUTE; /*!< I2S Receive Mute Setting Register */ + __I uint32_t IEPTR; /*!< I2S Receive Control Error Occurrence Address Storage Register*/ + uint32_t RESERVED8[5]; + __I uint32_t IREGBUSY; /*!< I2S Receive REGBUSY register */ + uint32_t RESERVED9[3]; + __IO uint32_t ITHRESHOLD; /*!< I2S Receive Threshold Setting Register */ + __I uint32_t IFIFO_STS; /*!< I2S Receive FIFO Status Register */ + uint32_t RESERVED10[40]; + __IO uint32_t IMODESET; /*!< I2S Receive Audio Data Format Setting Register*/ + uint32_t RESERVED11; + __I uint32_t ILMEM00; /*!< I2S Receive Data Storage Register 00 */ + __I uint32_t ILMEM01; /*!< I2S Receive Data Storage Register 01 */ + __I uint32_t ILMEM02; /*!< I2S Receive Data Storage Register 02 */ + __I uint32_t ILMEM03; /*!< I2S Receive Data Storage Register 03 */ + __I uint32_t ILMEM04; /*!< I2S Receive Data Storage Register 04 */ + __I uint32_t ILMEM05; /*!< I2S Receive Data Storage Register 05 */ + __I uint32_t ILMEM06; /*!< I2S Receive Data Storage Register 06 */ + __I uint32_t ILMEM07; /*!< I2S Receive Data Storage Register 07 */ + __I uint32_t ILMEM08; /*!< I2S Receive Data Storage Register 08 */ + __I uint32_t ILMEM09; /*!< I2S Receive Data Storage Register 09 */ + __I uint32_t ILMEM10; /*!< I2S Receive Data Storage Register 10 */ + __I uint32_t ILMEM11; /*!< I2S Receive Data Storage Register 11 */ + __I uint32_t ILMEM12; /*!< I2S Receive Data Storage Register 12 */ + __I uint32_t ILMEM13; /*!< I2S Receive Data Storage Register 13 */ + __I uint32_t ILMEM14; /*!< I2S Receive Data Storage Register 14 */ + __I uint32_t ILMEM15; /*!< I2S Receive Data Storage Register 15 */ + __I uint32_t ILMEM16; /*!< I2S Receive Data Storage Register 16 */ + __I uint32_t ILMEM17; /*!< I2S Receive Data Storage Register 17 */ + __I uint32_t ILMEM18; /*!< I2S Receive Data Storage Register 18 */ + __I uint32_t ILMEM19; /*!< I2S Receive Data Storage Register 19 */ + __I uint32_t ILMEM20; /*!< I2S Receive Data Storage Register 20 */ + __I uint32_t ILMEM21; /*!< I2S Receive Data Storage Register 21 */ + __I uint32_t ILMEM22; /*!< I2S Receive Data Storage Register 22 */ + __I uint32_t ILMEM23; /*!< I2S Receive Data Storage Register 23 */ + __I uint32_t ILMEM24; /*!< I2S Receive Data Storage Register 24 */ + __I uint32_t ILMEM25; /*!< I2S Receive Data Storage Register 25 */ + __I uint32_t ILMEM26; /*!< I2S Receive Data Storage Register 26 */ + __I uint32_t ILMEM27; /*!< I2S Receive Data Storage Register 27 */ + __I uint32_t ILMEM28; /*!< I2S Receive Data Storage Register 28 */ + __I uint32_t ILMEM29; /*!< I2S Receive Data Storage Register 29 */ + __I uint32_t ILMEM30; /*!< I2S Receive Data Storage Register 30 */ + __I uint32_t ILMEM31; /*!< I2S Receive Data Storage Register 31 */ + __I uint32_t ILMEM32; /*!< I2S Receive Data Storage Register 32 */ + __I uint32_t ILMEM33; /*!< I2S Receive Data Storage Register 33 */ + __I uint32_t ILMEM34; /*!< I2S Receive Data Storage Register 34 */ + __I uint32_t ILMEM35; /*!< I2S Receive Data Storage Register 35 */ + __I uint32_t ILMEM36; /*!< I2S Receive Data Storage Register 36 */ + __I uint32_t ILMEM37; /*!< I2S Receive Data Storage Register 37 */ + __I uint32_t ILMEM38; /*!< I2S Receive Data Storage Register 38 */ + __I uint32_t ILMEM39; /*!< I2S Receive Data Storage Register 39 */ + __I uint32_t ILMEM40; /*!< I2S Receive Data Storage Register 40 */ + __I uint32_t ILMEM41; /*!< I2S Receive Data Storage Register 41 */ + __I uint32_t ILMEM42; /*!< I2S Receive Data Storage Register 42 */ + __I uint32_t ILMEM43; /*!< I2S Receive Data Storage Register 43 */ + __I uint32_t ILMEM44; /*!< I2S Receive Data Storage Register 44 */ + __I uint32_t ILMEM45; /*!< I2S Receive Data Storage Register 45 */ + __I uint32_t ILMEM46; /*!< I2S Receive Data Storage Register 46 */ + __I uint32_t ILMEM47; /*!< I2S Receive Data Storage Register 47 */ + __I uint32_t ILMEM48; /*!< I2S Receive Data Storage Register 48 */ + __I uint32_t ILMEM49; /*!< I2S Receive Data Storage Register 49 */ + __I uint32_t ILMEM50; /*!< I2S Receive Data Storage Register 50 */ + __I uint32_t ILMEM51; /*!< I2S Receive Data Storage Register 51 */ + __I uint32_t ILMEM52; /*!< I2S Receive Data Storage Register 52 */ + __I uint32_t ILMEM53; /*!< I2S Receive Data Storage Register 53 */ + __I uint32_t ILMEM54; /*!< I2S Receive Data Storage Register 54 */ + __I uint32_t ILMEM55; /*!< I2S Receive Data Storage Register 55 */ + __I uint32_t ILMEM56; /*!< I2S Receive Data Storage Register 56 */ + __I uint32_t ILMEM57; /*!< I2S Receive Data Storage Register 57 */ + __I uint32_t ILMEM58; /*!< I2S Receive Data Storage Register 58 */ + __I uint32_t ILMEM59; /*!< I2S Receive Data Storage Register 59 */ + __I uint32_t ILMEM60; /*!< I2S Receive Data Storage Register 60 */ + __I uint32_t ILMEM61; /*!< I2S Receive Data Storage Register 61 */ + __I uint32_t ILMEM62; /*!< I2S Receive Data Storage Register 62 */ + __I uint32_t ILMEM63; /*!< I2S Receive Data Storage Register 63 */ + uint32_t RESERVED12; + __IO uint32_t OSTART; /*!< I2S Transmit Control Start Register */ + __I uint32_t OBUSY; /*!< I2S Transmit Operation Status Register */ + __IO uint32_t OSTOP; /*!< I2S Data Transmit Stop Register */ + __IO uint32_t OAUDIOSET; /*!< I2S Transmit AUDIOSET Register */ + __I uint32_t OINTSTAT; /*!< I2S Transmit Control Interrupt Status Register*/ + __IO uint32_t OINTMASK; /*!< I2S Transmit Control Interrupt Mask Register */ + __IO uint32_t OINTCLR; /*!< I2S Transmit Control Interrupt Clear Register*/ + uint32_t RESERVED13; + __IO uint32_t OMUTE; /*!< I2S Transmit Mute Setting Register */ + __I uint32_t OEPTR; /*!< I2S Transmit Control Error Occurrence Address Storage Register*/ + uint32_t RESERVED14; + __IO uint32_t OTX_SSIZE; /*!< I2S TX_SSIZE Register */ + uint32_t RESERVED15[3]; + __I uint32_t OREGBUSY; /*!< I2S Transmit REGBUSY Register */ + uint32_t RESERVED16[3]; + __IO uint32_t OTHRESHOLD; /*!< I2S Transmit Threshold Setting Register */ + __I uint32_t OFIFO_STS; /*!< I2S Transmit FIFO Status Register */ + uint32_t RESERVED17[40]; + __IO uint32_t OMODESET; /*!< I2S Transmit Audio Data Format Setting Register*/ + uint32_t RESERVED18; + __O uint32_t OLMEM00; /*!< I2S Transmit Data Storage Register 00 */ + __O uint32_t OLMEM01; /*!< I2S Transmit Data Storage Register 01 */ + __O uint32_t OLMEM02; /*!< I2S Transmit Data Storage Register 02 */ + __O uint32_t OLMEM03; /*!< I2S Transmit Data Storage Register 03 */ + __O uint32_t OLMEM04; /*!< I2S Transmit Data Storage Register 04 */ + __O uint32_t OLMEM05; /*!< I2S Transmit Data Storage Register 05 */ + __O uint32_t OLMEM06; /*!< I2S Transmit Data Storage Register 06 */ + __O uint32_t OLMEM07; /*!< I2S Transmit Data Storage Register 07 */ + __O uint32_t OLMEM08; /*!< I2S Transmit Data Storage Register 08 */ + __O uint32_t OLMEM09; /*!< I2S Transmit Data Storage Register 09 */ + __O uint32_t OLMEM10; /*!< I2S Transmit Data Storage Register 10 */ + __O uint32_t OLMEM11; /*!< I2S Transmit Data Storage Register 11 */ + __O uint32_t OLMEM12; /*!< I2S Transmit Data Storage Register 12 */ + __O uint32_t OLMEM13; /*!< I2S Transmit Data Storage Register 13 */ + __O uint32_t OLMEM14; /*!< I2S Transmit Data Storage Register 14 */ + __O uint32_t OLMEM15; /*!< I2S Transmit Data Storage Register 15 */ + __O uint32_t OLMEM16; /*!< I2S Transmit Data Storage Register 16 */ + __O uint32_t OLMEM17; /*!< I2S Transmit Data Storage Register 17 */ + __O uint32_t OLMEM18; /*!< I2S Transmit Data Storage Register 18 */ + __O uint32_t OLMEM19; /*!< I2S Transmit Data Storage Register 19 */ + __O uint32_t OLMEM20; /*!< I2S Transmit Data Storage Register 20 */ + __O uint32_t OLMEM21; /*!< I2S Transmit Data Storage Register 21 */ + __O uint32_t OLMEM22; /*!< I2S Transmit Data Storage Register 22 */ + __O uint32_t OLMEM23; /*!< I2S Transmit Data Storage Register 23 */ + __O uint32_t OLMEM24; /*!< I2S Transmit Data Storage Register 24 */ + __O uint32_t OLMEM25; /*!< I2S Transmit Data Storage Register 25 */ + __O uint32_t OLMEM26; /*!< I2S Transmit Data Storage Register 26 */ + __O uint32_t OLMEM27; /*!< I2S Transmit Data Storage Register 27 */ + __O uint32_t OLMEM28; /*!< I2S Transmit Data Storage Register 28 */ + __O uint32_t OLMEM29; /*!< I2S Transmit Data Storage Register 29 */ + __O uint32_t OLMEM30; /*!< I2S Transmit Data Storage Register 30 */ + __O uint32_t OLMEM31; /*!< I2S Transmit Data Storage Register 31 */ + __O uint32_t OLMEM32; /*!< I2S Transmit Data Storage Register 32 */ + __O uint32_t OLMEM33; /*!< I2S Transmit Data Storage Register 33 */ + __O uint32_t OLMEM34; /*!< I2S Transmit Data Storage Register 34 */ + __O uint32_t OLMEM35; /*!< I2S Transmit Data Storage Register 35 */ + __O uint32_t OLMEM36; /*!< I2S Transmit Data Storage Register 36 */ + __O uint32_t OLMEM37; /*!< I2S Transmit Data Storage Register 37 */ + __O uint32_t OLMEM38; /*!< I2S Transmit Data Storage Register 38 */ + __O uint32_t OLMEM39; /*!< I2S Transmit Data Storage Register 39 */ + __O uint32_t OLMEM40; /*!< I2S Transmit Data Storage Register 40 */ + __O uint32_t OLMEM41; /*!< I2S Transmit Data Storage Register 41 */ + __O uint32_t OLMEM42; /*!< I2S Transmit Data Storage Register 42 */ + __O uint32_t OLMEM43; /*!< I2S Transmit Data Storage Register 43 */ + __O uint32_t OLMEM44; /*!< I2S Transmit Data Storage Register 44 */ + __O uint32_t OLMEM45; /*!< I2S Transmit Data Storage Register 45 */ + __O uint32_t OLMEM46; /*!< I2S Transmit Data Storage Register 46 */ + __O uint32_t OLMEM47; /*!< I2S Transmit Data Storage Register 47 */ + __O uint32_t OLMEM48; /*!< I2S Transmit Data Storage Register 48 */ + __O uint32_t OLMEM49; /*!< I2S Transmit Data Storage Register 49 */ + __O uint32_t OLMEM50; /*!< I2S Transmit Data Storage Register 50 */ + __O uint32_t OLMEM51; /*!< I2S Transmit Data Storage Register 51 */ + __O uint32_t OLMEM52; /*!< I2S Transmit Data Storage Register 52 */ + __O uint32_t OLMEM53; /*!< I2S Transmit Data Storage Register 53 */ + __O uint32_t OLMEM54; /*!< I2S Transmit Data Storage Register 54 */ + __O uint32_t OLMEM55; /*!< I2S Transmit Data Storage Register 55 */ + __O uint32_t OLMEM56; /*!< I2S Transmit Data Storage Register 56 */ + __O uint32_t OLMEM57; /*!< I2S Transmit Data Storage Register 57 */ + __O uint32_t OLMEM58; /*!< I2S Transmit Data Storage Register 58 */ + __O uint32_t OLMEM59; /*!< I2S Transmit Data Storage Register 59 */ + __O uint32_t OLMEM60; /*!< I2S Transmit Data Storage Register 60 */ + __O uint32_t OLMEM61; /*!< I2S Transmit Data Storage Register 61 */ + __O uint32_t OLMEM62; /*!< I2S Transmit Data Storage Register 62 */ + __O uint32_t OLMEM63; /*!< I2S Transmit Data Storage Register 63 */ +} TSB_I2S_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< I2C Data Buffer Register */ + __IO uint32_t AR; /*!< I2C Bus address Register */ + union { + __O uint32_t CR2; /*!< I2C Control Register 2 */ + __I uint32_t SR; /*!< I2C Status Register */ + }; + __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ + __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ + __IO uint32_t ST; /*!< I2C Interruption Status Register */ + __IO uint32_t OP; /*!< I2C Expanded function setting Register */ + __I uint32_t PM; /*!< I2C Bus pin Monitor Register */ + __IO uint32_t AR2; /*!< I2C 2nd address Register */ +} TSB_I2C_TypeDef; + +/** + * @brief EI2C + */ +typedef struct { + __IO uint32_t ARST; /*!< I2C Reset Register */ + __IO uint32_t AEN; /*!< I2C Bus Enable Register */ + __IO uint32_t ACR0; /*!< I2C Control Register 0 */ + __IO uint32_t ACR1; /*!< I2C Control Register 1 */ + __IO uint32_t ADBRT; /*!< I2C Transmit Data Buffer Register */ + __I uint32_t ADBRR; /*!< I2C Receive Data Buffer Register */ + __I uint32_t ASR0; /*!< I2C Status Register 0 */ + __IO uint32_t ASR1; /*!< I2C Status Register 1 */ + __IO uint32_t APRS; /*!< I2C Prescaler Clock Setting Register */ + __IO uint32_t ASCL; /*!< I2C SCL Wdth Setting Register */ + __IO uint32_t AAR1; /*!< I2C 1st Slave Address Register */ + __IO uint32_t AAR2; /*!< I2C 2nd Slave Address Register */ + __IO uint32_t AIE; /*!< I2C Interrupt DMA Setting Register */ + __I uint32_t APM; /*!< I2C Bus Terminal Monitor Setting Register */ +} TSB_EI2C_TypeDef; + +/** + * @brief Finite Impulse Response + */ +typedef struct { + __IO uint32_t START; /*!< FIR Start Register */ + __IO uint32_t CTRL; /*!< FIR Control Register */ + __IO uint32_t INITIALIZE; /*!< FIR Initialize Register */ + __IO uint32_t INITDATA; /*!< FIR Init data Register */ + __IO uint32_t INTEN; /*!< FIR Interrupt Enable Register */ + __IO uint32_t DMAEN; /*!< FIR DMA Enable Register */ + __IO uint32_t RAWINTSTAT; /*!< FIR Raw Interrupt Status Register */ + __I uint32_t SEQSTAT; /*!< FIR Sequencer Status Register */ + __IO uint32_t DBUFWPTR; /*!< FIR Data Buffer Write Pointer Register */ + __IO uint32_t DBUFRPTR; /*!< FIR Data Buffer Read Pointer Register */ + uint32_t RESERVED0[2]; + __IO uint32_t IDATA; /*!< FIR Input Data Register */ + __I uint32_t ODATA; /*!< FIR Output Data Register */ + uint32_t RESERVED1[2]; + __IO uint32_t COEF0; /*!< FIR Coefficient Register0 */ + __IO uint32_t COEF1; /*!< FIR Coefficient Register1 */ + __IO uint32_t COEF2; /*!< FIR Coefficient Register2 */ + __IO uint32_t COEF3; /*!< FIR Coefficient Register3 */ + __IO uint32_t COEF4; /*!< FIR Coefficient Register4 */ + __IO uint32_t COEF5; /*!< FIR Coefficient Register5 */ + __IO uint32_t COEF6; /*!< FIR Coefficient Register6 */ + __IO uint32_t COEF7; /*!< FIR Coefficient Register7 */ + __IO uint32_t COEF8; /*!< FIR Coefficient Register8 */ + __IO uint32_t COEF9; /*!< FIR Coefficient Register9 */ + __IO uint32_t COEF10; /*!< FIR Coefficient Register10 */ + __IO uint32_t COEF11; /*!< FIR Coefficient Register11 */ + __IO uint32_t COEF12; /*!< FIR Coefficient Register12 */ + __IO uint32_t COEF13; /*!< FIR Coefficient Register13 */ + __IO uint32_t COEF14; /*!< FIR Coefficient Register14 */ + __IO uint32_t COEF15; /*!< FIR Coefficient Register15 */ + __IO uint32_t COEF16; /*!< FIR Coefficient Register16 */ + __IO uint32_t COEF17; /*!< FIR Coefficient Register17 */ + __IO uint32_t COEF18; /*!< FIR Coefficient Register18 */ + __IO uint32_t COEF19; /*!< FIR Coefficient Register19 */ + __IO uint32_t COEF20; /*!< FIR Coefficient Register20 */ + __IO uint32_t COEF21; /*!< FIR Coefficient Register21 */ + __IO uint32_t COEF22; /*!< FIR Coefficient Register22 */ + __IO uint32_t COEF23; /*!< FIR Coefficient Register23 */ + __IO uint32_t COEF24; /*!< FIR Coefficient Register24 */ + __IO uint32_t COEF25; /*!< FIR Coefficient Register25 */ + __IO uint32_t COEF26; /*!< FIR Coefficient Register26 */ + __IO uint32_t COEF27; /*!< FIR Coefficient Register27 */ + __IO uint32_t COEF28; /*!< FIR Coefficient Register28 */ + __IO uint32_t COEF29; /*!< FIR Coefficient Register29 */ + __IO uint32_t COEF30; /*!< FIR Coefficient Register30 */ + __IO uint32_t COEF31; /*!< FIR Coefficient Register31 */ + __IO uint32_t COEF32; /*!< FIR Coefficient Register32 */ + __IO uint32_t COEF33; /*!< FIR Coefficient Register33 */ + __IO uint32_t COEF34; /*!< FIR Coefficient Register34 */ + __IO uint32_t COEF35; /*!< FIR Coefficient Register35 */ + __IO uint32_t COEF36; /*!< FIR Coefficient Register36 */ + __IO uint32_t COEF37; /*!< FIR Coefficient Register37 */ + __IO uint32_t COEF38; /*!< FIR Coefficient Register38 */ + __IO uint32_t COEF39; /*!< FIR Coefficient Register39 */ + __IO uint32_t COEF40; /*!< FIR Coefficient Register40 */ + __IO uint32_t COEF41; /*!< FIR Coefficient Register41 */ + __IO uint32_t COEF42; /*!< FIR Coefficient Register42 */ + __IO uint32_t COEF43; /*!< FIR Coefficient Register43 */ + __IO uint32_t COEF44; /*!< FIR Coefficient Register44 */ + __IO uint32_t COEF45; /*!< FIR Coefficient Register45 */ + __IO uint32_t COEF46; /*!< FIR Coefficient Register46 */ + __IO uint32_t COEF47; /*!< FIR Coefficient Register47 */ + __IO uint32_t COEF48; /*!< FIR Coefficient Register48 */ + __IO uint32_t COEF49; /*!< FIR Coefficient Register49 */ + __IO uint32_t COEF50; /*!< FIR Coefficient Register50 */ + __IO uint32_t COEF51; /*!< FIR Coefficient Register51 */ + __IO uint32_t COEF52; /*!< FIR Coefficient Register52 */ + __IO uint32_t COEF53; /*!< FIR Coefficient Register53 */ + __IO uint32_t COEF54; /*!< FIR Coefficient Register54 */ + __IO uint32_t COEF55; /*!< FIR Coefficient Register55 */ + __IO uint32_t COEF56; /*!< FIR Coefficient Register56 */ + __IO uint32_t COEF57; /*!< FIR Coefficient Register57 */ + __IO uint32_t COEF58; /*!< FIR Coefficient Register58 */ + __IO uint32_t COEF59; /*!< FIR Coefficient Register59 */ + __IO uint32_t COEF60; /*!< FIR Coefficient Register60 */ + __IO uint32_t COEF61; /*!< FIR Coefficient Register61 */ + __IO uint32_t COEF62; /*!< FIR Coefficient Register62 */ + __IO uint32_t COEF63; /*!< FIR Coefficient Register63 */ + __IO uint32_t COEF64; /*!< FIR Coefficient Register64 */ + __IO uint32_t COEF65; /*!< FIR Coefficient Register65 */ + __IO uint32_t COEF66; /*!< FIR Coefficient Register66 */ + __IO uint32_t COEF67; /*!< FIR Coefficient Register67 */ + __IO uint32_t COEF68; /*!< FIR Coefficient Register68 */ + __IO uint32_t COEF69; /*!< FIR Coefficient Register69 */ + __IO uint32_t COEF70; /*!< FIR Coefficient Register70 */ + __IO uint32_t COEF71; /*!< FIR Coefficient Register71 */ + __IO uint32_t COEF72; /*!< FIR Coefficient Register72 */ + __IO uint32_t COEF73; /*!< FIR Coefficient Register73 */ + __IO uint32_t COEF74; /*!< FIR Coefficient Register74 */ + __IO uint32_t COEF75; /*!< FIR Coefficient Register75 */ + __IO uint32_t COEF76; /*!< FIR Coefficient Register76 */ + __IO uint32_t COEF77; /*!< FIR Coefficient Register77 */ + __IO uint32_t COEF78; /*!< FIR Coefficient Register78 */ + __IO uint32_t COEF79; /*!< FIR Coefficient Register79 */ + __IO uint32_t COEF80; /*!< FIR Coefficient Register80 */ + __IO uint32_t COEF81; /*!< FIR Coefficient Register81 */ + __IO uint32_t COEF82; /*!< FIR Coefficient Register82 */ + __IO uint32_t COEF83; /*!< FIR Coefficient Register83 */ + __IO uint32_t COEF84; /*!< FIR Coefficient Register84 */ + __IO uint32_t COEF85; /*!< FIR Coefficient Register85 */ + __IO uint32_t COEF86; /*!< FIR Coefficient Register86 */ + __IO uint32_t COEF87; /*!< FIR Coefficient Register87 */ + __IO uint32_t COEF88; /*!< FIR Coefficient Register88 */ + __IO uint32_t COEF89; /*!< FIR Coefficient Register89 */ + __IO uint32_t COEF90; /*!< FIR Coefficient Register90 */ + __IO uint32_t COEF91; /*!< FIR Coefficient Register91 */ + __IO uint32_t COEF92; /*!< FIR Coefficient Register92 */ + __IO uint32_t COEF93; /*!< FIR Coefficient Register93 */ + __IO uint32_t COEF94; /*!< FIR Coefficient Register94 */ + __IO uint32_t COEF95; /*!< FIR Coefficient Register95 */ + __IO uint32_t COEF96; /*!< FIR Coefficient Register96 */ + __IO uint32_t COEF97; /*!< FIR Coefficient Register97 */ + __IO uint32_t COEF98; /*!< FIR Coefficient Register98 */ + __IO uint32_t COEF99; /*!< FIR Coefficient Register99 */ + __IO uint32_t COEF100; /*!< FIR Coefficient Register100 */ + __IO uint32_t COEF101; /*!< FIR Coefficient Register101 */ + __IO uint32_t COEF102; /*!< FIR Coefficient Register102 */ + __IO uint32_t COEF103; /*!< FIR Coefficient Register103 */ + __IO uint32_t COEF104; /*!< FIR Coefficient Register104 */ + __IO uint32_t COEF105; /*!< FIR Coefficient Register105 */ + __IO uint32_t COEF106; /*!< FIR Coefficient Register106 */ + __IO uint32_t COEF107; /*!< FIR Coefficient Register107 */ + __IO uint32_t COEF108; /*!< FIR Coefficient Register108 */ + __IO uint32_t COEF109; /*!< FIR Coefficient Register109 */ + __IO uint32_t COEF110; /*!< FIR Coefficient Register110 */ + __IO uint32_t COEF111; /*!< FIR Coefficient Register111 */ + __IO uint32_t COEF112; /*!< FIR Coefficient Register112 */ + __IO uint32_t COEF113; /*!< FIR Coefficient Register113 */ + __IO uint32_t COEF114; /*!< FIR Coefficient Register114 */ + __IO uint32_t COEF115; /*!< FIR Coefficient Register115 */ + __IO uint32_t COEF116; /*!< FIR Coefficient Register116 */ + __IO uint32_t COEF117; /*!< FIR Coefficient Register117 */ + __IO uint32_t COEF118; /*!< FIR Coefficient Register118 */ + __IO uint32_t COEF119; /*!< FIR Coefficient Register119 */ + __IO uint32_t COEF120; /*!< FIR Coefficient Register120 */ + __IO uint32_t COEF121; /*!< FIR Coefficient Register121 */ + __IO uint32_t COEF122; /*!< FIR Coefficient Register122 */ + __IO uint32_t COEF123; /*!< FIR Coefficient Register123 */ + __IO uint32_t COEF124; /*!< FIR Coefficient Register124 */ + __IO uint32_t COEF125; /*!< FIR Coefficient Register125 */ + __IO uint32_t COEF126; /*!< FIR Coefficient Register126 */ + __IO uint32_t COEF127; /*!< FIR Coefficient Register127 */ +} TSB_FIR_TypeDef; + +/** + * @brief Port A + */ +typedef struct { + __IO uint32_t DATA; /*!< Port A Data Register */ + __IO uint32_t CR; /*!< Port A Output Control Register */ + __IO uint32_t FR1; /*!< Port A Function Register 1 */ + __IO uint32_t FR2; /*!< Port A Function Register 2 */ + __IO uint32_t FR3; /*!< Port A Function Register 3 */ + uint32_t RESERVED0; + __IO uint32_t FR5; /*!< Port A Function Register 5 */ + __IO uint32_t FR6; /*!< Port A Function Register 6 */ + __IO uint32_t FR7; /*!< Port A Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port A Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port A Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port A Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port A Input Control Register */ +} TSB_PA_TypeDef; + +/** + * @brief Port B + */ +typedef struct { + __IO uint32_t DATA; /*!< Port B Data Register */ + __IO uint32_t CR; /*!< Port B Output Control Register */ + __IO uint32_t FR1; /*!< Port B Function Register 1 */ + __IO uint32_t FR2; /*!< Port B Function Register 2 */ + __IO uint32_t FR3; /*!< Port B Function Register 3 */ + __IO uint32_t FR4; /*!< Port B Function Register 4 */ + __IO uint32_t FR5; /*!< Port B Function Register 5 */ + __IO uint32_t FR6; /*!< Port B Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< Port B Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port B Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port B Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port B Input Control Register */ +} TSB_PB_TypeDef; + +/** + * @brief Port C + */ +typedef struct { + __IO uint32_t DATA; /*!< Port C Data Register */ + __IO uint32_t CR; /*!< Port C Output Control Register */ + __IO uint32_t FR1; /*!< Port C Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< Port C Function Register 3 */ + __IO uint32_t FR4; /*!< Port C Function Register 4 */ + __IO uint32_t FR5; /*!< Port C Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port C Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port C Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port C Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port C Input Control Register */ +} TSB_PC_TypeDef; + +/** + * @brief Port D + */ +typedef struct { + __IO uint32_t DATA; /*!< Port D Data Register */ + __IO uint32_t CR; /*!< Port D Output Control Register */ + __IO uint32_t FR1; /*!< Port D Function Register 1 */ + __IO uint32_t FR2; /*!< Port D Function Register 2 */ + __IO uint32_t FR3; /*!< Port D Function Register 3 */ + __IO uint32_t FR4; /*!< Port D Function Register 4 */ + __IO uint32_t FR5; /*!< Port D Function Register 5 */ + __IO uint32_t FR6; /*!< Port D Function Register 6 */ + __IO uint32_t FR7; /*!< Port D Function Register 7 */ + __IO uint32_t FR8; /*!< Port D Function Register 8 */ + __IO uint32_t OD; /*!< Port D Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port D Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port D Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port D Input Control Register */ +} TSB_PD_TypeDef; + +/** + * @brief Port E + */ +typedef struct { + __IO uint32_t DATA; /*!< Port E Data Register */ + __IO uint32_t CR; /*!< Port E Output Control Register */ + __IO uint32_t FR1; /*!< Port E Function Register 1 */ + __IO uint32_t FR2; /*!< Port E Function Register 2 */ + __IO uint32_t FR3; /*!< Port E Function Register 3 */ + __IO uint32_t FR4; /*!< Port E Function Register 4 */ + __IO uint32_t FR5; /*!< Port E Function Register 5 */ + __IO uint32_t FR6; /*!< Port E Function Register 6 */ + __IO uint32_t FR7; /*!< Port E Function Register 7 */ + __IO uint32_t FR8; /*!< Port E Function Register 8 */ + __IO uint32_t OD; /*!< Port E Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port E Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port E Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port E Input Control Register */ +} TSB_PE_TypeDef; + +/** + * @brief Port F + */ +typedef struct { + __IO uint32_t DATA; /*!< Port F Data Register */ + __IO uint32_t CR; /*!< Port F Output Control Register */ + __IO uint32_t FR1; /*!< Port F Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port F Function Register 4 */ + __IO uint32_t FR5; /*!< Port F Function Register 5 */ + __IO uint32_t FR6; /*!< Port F Function Register 6 */ + __IO uint32_t FR7; /*!< Port F Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port F Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port F Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port F Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port F Input Control Register */ +} TSB_PF_TypeDef; + +/** + * @brief Port G + */ +typedef struct { + __IO uint32_t DATA; /*!< Port G Data Register */ + __IO uint32_t CR; /*!< Port G Output Control Register */ + __IO uint32_t FR1; /*!< Port G Function Register 1 */ + __IO uint32_t FR2; /*!< Port G Function Register 2 */ + __IO uint32_t FR3; /*!< Port G Function Register 3 */ + __IO uint32_t FR4; /*!< Port G Function Register 4 */ + __IO uint32_t FR5; /*!< Port G Function Register 5 */ + __IO uint32_t FR6; /*!< Port G Function Register 6 */ + __IO uint32_t FR7; /*!< Port G Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port G Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port G Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port G Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port G Input Control Register */ +} TSB_PG_TypeDef; + +/** + * @brief Port H + */ +typedef struct { + __IO uint32_t DATA; /*!< Port H Data Register */ + __IO uint32_t CR; /*!< Port H Output Control Register */ + __IO uint32_t FR1; /*!< Port H Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< Port H Function Register 3 */ + __IO uint32_t FR4; /*!< Port H Function Register 4 */ + __IO uint32_t FR5; /*!< Port H Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port H Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port H Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port H Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port H Input Control Register */ +} TSB_PH_TypeDef; + +/** + * @brief Port J + */ +typedef struct { + __IO uint32_t DATA; /*!< Port J Data Register */ + __IO uint32_t CR; /*!< Port J Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port J Function Register 2 */ + __IO uint32_t FR3; /*!< Port J Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port J Function Register 5 */ + __IO uint32_t FR6; /*!< Port J Function Register 6 */ + __IO uint32_t FR7; /*!< Port J Function Register 7 */ + uint32_t RESERVED2; + __IO uint32_t OD; /*!< Port J Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port J Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port J Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port J Input Control Register */ +} TSB_PJ_TypeDef; + +/** + * @brief Port K + */ +typedef struct { + __IO uint32_t DATA; /*!< Port K Data Register */ + __IO uint32_t CR; /*!< Port K Output Control Register */ + __IO uint32_t FR1; /*!< Port K Function Register 1 */ + __IO uint32_t FR2; /*!< Port K Function Register 2 */ + __IO uint32_t FR3; /*!< Port K Function Register 3 */ + __IO uint32_t FR4; /*!< Port K Function Register 4 */ + __IO uint32_t FR5; /*!< Port K Function Register 5 */ + __IO uint32_t FR6; /*!< Port K Function Register 6 */ + __IO uint32_t FR7; /*!< Port K Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port K Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port K Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port K Pull-up Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port K Input Control Register */ +} TSB_PK_TypeDef; + +/** + * @brief Port L + */ +typedef struct { + __IO uint32_t DATA; /*!< Port L Data Register */ + __IO uint32_t CR; /*!< Port L Output Control Register */ + __IO uint32_t FR1; /*!< Port L Function Register 1 */ + __IO uint32_t FR2; /*!< Port L Function Register 2 */ + __IO uint32_t FR3; /*!< Port L Function Register 3 */ + uint32_t RESERVED0; + __IO uint32_t FR5; /*!< Port L Function Register 5 */ + __IO uint32_t FR6; /*!< Port L Function Register 6 */ + __IO uint32_t FR7; /*!< Port L Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port L Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port L Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port L Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port L Input Control Register */ +} TSB_PL_TypeDef; + +/** + * @brief Port M + */ +typedef struct { + __IO uint32_t DATA; /*!< Port M Data Register */ + __IO uint32_t CR; /*!< Port M Output Control Register */ + __IO uint32_t FR1; /*!< Port M Function Register 1 */ + __IO uint32_t FR2; /*!< Port M Function Register 2 */ + __IO uint32_t FR3; /*!< Port M Function Register 3 */ + __IO uint32_t FR4; /*!< Port M Function Register 4 */ + __IO uint32_t FR5; /*!< Port M Function Register 5 */ + __IO uint32_t FR6; /*!< Port M Function Register 6 */ + __IO uint32_t FR7; /*!< Port M Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port M Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port M Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port M Pull-up Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port M Input Control Register */ +} TSB_PM_TypeDef; + +/** + * @brief Port N + */ +typedef struct { + __IO uint32_t DATA; /*!< Port N Data Register */ + __IO uint32_t CR; /*!< Port N Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port N Opend Drain Control Register */ + __IO uint32_t PUP; /*!< Port N Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port N Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port N Input Control Register */ +} TSB_PN_TypeDef; + +/** + * @brief Port P + */ +typedef struct { + __IO uint32_t DATA; /*!< Port P Data Register */ + __IO uint32_t CR; /*!< Port P Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port P Function Register 2 */ + __IO uint32_t FR3; /*!< Port P Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port P Function Register 5 */ + uint32_t RESERVED2[3]; + __IO uint32_t OD; /*!< Port P Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port P Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port P Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port P Input Control Register */ +} TSB_PP_TypeDef; + +/** + * @brief Port R + */ +typedef struct { + __IO uint32_t DATA; /*!< Port R Data Register */ + __IO uint32_t CR; /*!< Port R Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port R Function Register 2 */ + __IO uint32_t FR3; /*!< Port R Function Register 3 */ + uint32_t RESERVED1[5]; + __IO uint32_t OD; /*!< Port R Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port R Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port R Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port R Input Control Register */ +} TSB_PR_TypeDef; + +/** + * @brief Port T + */ +typedef struct { + __IO uint32_t DATA; /*!< Port T Data Register */ + __IO uint32_t CR; /*!< Port T Output Control Register */ + __IO uint32_t FR1; /*!< Port T Function Register 1 */ + __IO uint32_t FR2; /*!< Port T Function Register 2 */ + __IO uint32_t FR3; /*!< Port T Function Register 3 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR6; /*!< Port T Function Register 6 */ + __IO uint32_t FR7; /*!< Port T Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port T Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port T Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port T Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port T Input Control Register */ +} TSB_PT_TypeDef; + +/** + * @brief Port U + */ +typedef struct { + __IO uint32_t DATA; /*!< Port U Data Register */ + __IO uint32_t CR; /*!< Port U Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port U Function Register 2 */ + __IO uint32_t FR3; /*!< Port U Function Register 3 */ + uint32_t RESERVED1[2]; + __IO uint32_t FR6; /*!< Port U Function Register 6 */ + __IO uint32_t FR7; /*!< Port U Function Register 7 */ + uint32_t RESERVED2; + __IO uint32_t OD; /*!< Port U Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port U Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port U Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port U Input Control Register */ +} TSB_PU_TypeDef; + +/** + * @brief Port V + */ +typedef struct { + __IO uint32_t DATA; /*!< Port V Data Register */ + __IO uint32_t CR; /*!< Port V OutPut Control Register */ + __IO uint32_t FR1; /*!< Port V Function Register 1 */ + __IO uint32_t FR2; /*!< Port V Function Register 2 */ + __IO uint32_t FR3; /*!< Port V Function Register 3 */ + __IO uint32_t FR4; /*!< Port V Function Register 4 */ + __IO uint32_t FR5; /*!< Port V Function Register 5 */ + __IO uint32_t FR6; /*!< Port V Function Register 6 */ + __IO uint32_t FR7; /*!< Port V Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port V Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port V Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port V Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port V InPut Control Register */ +} TSB_PV_TypeDef; + +/** + * @brief Port W + */ +typedef struct { + __IO uint32_t DATA; /*!< Port W Data Register */ + __IO uint32_t CR; /*!< Port W OutPut Control Register */ + uint32_t RESERVED0[2]; + __IO uint32_t FR3; /*!< Port W Function Register 3 */ + __IO uint32_t FR4; /*!< Port W Function Register 4 */ + __IO uint32_t FR5; /*!< Port W Function Register 5 */ + __IO uint32_t FR6; /*!< Port W Function Register 6 */ + __IO uint32_t FR7; /*!< Port W Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port W Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port W Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port W Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port W InPut Control Register */ +} TSB_PW_TypeDef; + +/** + * @brief Port Y + */ +typedef struct { + __IO uint32_t DATA; /*!< Port Y Data Register */ + __IO uint32_t CR; /*!< Port Y OutPut Control Register */ + __IO uint32_t FR1; /*!< Port Y Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port Y Function Register 4 */ + uint32_t RESERVED1[4]; + __IO uint32_t OD; /*!< Port Y Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port Y Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port Y Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port Y InPut Control Register */ +} TSB_PY_TypeDef; + +/** + * @brief Internal High-speed Oscillation Adjustment + */ +typedef struct { + __IO uint32_t OSCPRO; /*!< TRM Protection Register */ + __IO uint32_t OSCEN; /*!< TRM User Trimming Value Enable Register */ + uint32_t RESERVED0[2]; + __I uint32_t OSCINIT0; /*!< TRM Initial trimming level monitor register0 */ + __I uint32_t OSCINIT1; /*!< TRM Initial trimming level monitor register1 */ + __I uint32_t OSCINIT2; /*!< TRM Initial trimming level monitor register2 */ + uint32_t RESERVED1; + __IO uint32_t OSCSET0; /*!< TRM Trimming level setting register0 for User*/ + __IO uint32_t OSCSET1; /*!< TRM Trimming level setting register1 for User*/ + __IO uint32_t OSCSET2; /*!< TRM Trimming level setting register2 for User*/ +} TSB_TRM_TypeDef; + +/** + * @brief Oscillation Frequency Detector (OFD) + */ +typedef struct { + __IO uint32_t CR1; /*!< OFD Frequency Detection Control Register 1 */ + __IO uint32_t CR2; /*!< OFD Frequency Detection Control Register 2 */ + __IO uint32_t MN0; /*!< OFD Minimum Detection Frequency Setting Register 0 (EHOSC)*/ + __IO uint32_t MN1; /*!< OFD Minimum Detection Frequency Setting Register 1 (fc)*/ + __IO uint32_t MX0; /*!< OFD Maximum Detection Frequency Setting Register 0 (EHOSC)*/ + __IO uint32_t MX1; /*!< OFD Maximum Detection Frequency Setting Register 1 (fc)*/ + __IO uint32_t RST; /*!< OFD Reset Control Register */ + __I uint32_t STAT; /*!< OFD Status Register */ + __IO uint32_t MON; /*!< OFD Detection Target Clock 1 Monitor Setting Register*/ +} TSB_OFD_TypeDef; + +/** + * @brief Real Time Clock (RTC) + */ +typedef struct { + __IO uint8_t SECR; /*!< RTC Second column register (PAGE0) */ + __IO uint8_t MINR; /*!< RTC Minute column register (PAGE0/1) */ + __IO uint8_t HOURR; /*!< RTC Hour column register (PAGE0/1) */ + uint8_t RESERVED0; + __IO uint8_t DAYR; /*!< RTC Day of the week column register (PAGE0/1)*/ + __IO uint8_t DATER; /*!< RTC Day column register (PAGE0/1) */ + __IO uint8_t MONTHR; /*!< RTC Month column register (PAGE0) */ + __IO uint8_t YEARR; /*!< RTC Year column register (PAGE0) */ + __IO uint8_t PAGER; /*!< RTC PAGE register (PAGE0/1) */ + uint8_t RESERVED1[3]; + __IO uint8_t RESTR; /*!< RTC Reset register (PAGE0/1) */ + uint8_t RESERVED2; + __IO uint8_t PROTECT; /*!< RTC Protect register */ + __IO uint8_t ADJCTL; /*!< RTC Correction Function Control Register */ + __IO uint8_t ADJDAT; /*!< RTC Correction Value Register */ + __IO uint8_t ADJSIGN; /*!< RTC Correction Value sign Register */ +} TSB_RTC_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct { + __IO uint32_t EN; /*!< CEC Enable Register */ + __IO uint32_t ADD; /*!< CEC Logical Address Register */ + __O uint32_t RESET; /*!< CEC Software Reset Register */ + __IO uint32_t REN; /*!< CEC Receive Enable Register */ + __I uint32_t RBUF; /*!< CEC Receive Buffer Register */ + __IO uint32_t RCR1; /*!< CEC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< CEC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< CEC Receive Control Register 3 */ + __IO uint32_t TEN; /*!< CEC Transmit Enable Register */ + __IO uint32_t TBUF; /*!< CEC Transmit Buffer Register */ + __IO uint32_t TCR; /*!< CEC Transmit Control Register */ + __I uint32_t RSTAT; /*!< CEC Receive Interrupt Status Register */ + __I uint32_t TSTAT; /*!< CEC Transmit Interrupt Status Register */ + __IO uint32_t FSSEL; /*!< CEC sampling clock select Register */ +} TSB_CEC_TypeDef; + +/** + * @brief Remote Control Signal Preprocessor (RMC) + */ +typedef struct { + __IO uint32_t EN; /*!< RMC Enable Register */ + __IO uint32_t REN; /*!< RMC Receive Enable Register */ + __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ + __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ + __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ + __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ + __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ + __I uint32_t RSTAT; /*!< RMC Receive Status Register */ + __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ + __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ + __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ + __IO uint32_t FSSEL; /*!< RMC Sampling Clock Selection Register */ +} TSB_RMC_TypeDef; + +/** + * @brief + */ +typedef struct { + __IO uint32_t MDEN; /*!< PMD Enable Register */ + __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ + __IO uint32_t MDCR; /*!< PMD Control Register */ + __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ + __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ + __IO uint32_t RATE; /*!< PWM Frequency Register */ + __IO uint32_t CMPU; /*!< PMD PWM duty comparison U Register */ + __IO uint32_t CMPV; /*!< PMD PWM duty comparison V Register */ + __IO uint32_t CMPW; /*!< PMD PWM duty comparison W Register */ + __IO uint32_t MODESEL; /*!< PMD Mode Select Register */ + __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ + __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ + __O uint32_t EMGREL; /*!< PMD EMG Release Register */ + __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ + __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ + __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ + __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ + __IO uint32_t DTR; /*!< PMD Dead Time Register */ + __IO uint32_t TRGCMP0; /*!< PMD Trigger comparison Register 0 */ + __IO uint32_t TRGCMP1; /*!< PMD Trigger comparison Register 1 */ + __IO uint32_t TRGCMP2; /*!< PMD Trigger comparison Register 2 */ + __IO uint32_t TRGCMP3; /*!< PMD Trigger comparison Register 3 */ + __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ + __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ + __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ + __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ + __IO uint32_t VPWMPH; /*!< PMD V-phase phase difference register */ + __IO uint32_t WPWMPH; /*!< PMD W-phase phase difference register */ + __IO uint32_t MBUFCR; /*!< PMD Intermediate buffer control register */ + __IO uint32_t SYNCCR; /*!< Synchronization control between the PMD channel*/ +} TSB_PMD_TypeDef; + +/** + * @brief + */ +typedef struct { + __IO uint32_t EN; /*!< Interval Sencing Detector(ISD) */ + __IO uint32_t CLKCR; /*!< ISD Clock Control Register */ + __IO uint32_t OCR0; /*!< ISD Output Control Register 0 */ + __IO uint32_t OCR1; /*!< ISD Output Control Register 1 */ + __IO uint32_t ICR; /*!< ISD Input Control Register */ + __IO uint32_t CR; /*!< ISD Control Register */ + __I uint32_t BR; /*!< ISD Buffer Register */ + __I uint32_t SR; /*!< ISD Status Register */ + __IO uint32_t INTCR; /*!< ISD Interrupt Control Register */ +} TSB_ISD_TypeDef; + +/** + * @brief + */ +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ + __IO uint32_t SSR; /*!< Flash Security Status Register */ + __O uint32_t KCR; /*!< Flash Key Code Register */ + uint32_t RESERVED1; + __IO uint32_t SR0; /*!< Flash Status Register 0 */ + uint32_t RESERVED2[3]; + __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ + __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ + __I uint32_t PSR2; /*!< Flash Protect Status Register 2 */ + uint32_t RESERVED3[3]; + __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ + uint32_t RESERVED4; + __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ + __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ + __IO uint32_t PMR2; /*!< Flash Protect Mask Register 2 */ + uint32_t RESERVED5[3]; + __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ + uint32_t RESERVED6[37]; + __I uint32_t SR1; /*!< Flash Status Register 1 */ + __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ + uint32_t RESERVED7[14]; + __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ + uint32_t RESERVED8; + __IO uint32_t CR; /*!< Flash Control Register */ + __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ + __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ + __IO uint32_t ACCR; /*!< Flash Access Control Register */ + __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ + uint32_t RESERVED9[1071]; + __IO uint32_t RACCR; /*!< RAM Access Control Register */ +} TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_DMACA_BASE (PERI_BASE + 0x0000000UL) +#define TSB_DMACB_BASE (PERI_BASE + 0x0001000UL) +#define TSB_SMI0_BASE (PERI_BASE + 0x000C000UL) +#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) +#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) +#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) +#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL) +#define TSB_LTT0_BASE (PERI_BASE + 0x003FF00UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x006A000UL) +#define TSB_TSPI1_BASE (PERI_BASE + 0x006A400UL) +#define TSB_TSPI2_BASE (PERI_BASE + 0x006A800UL) +#define TSB_TSPI3_BASE (PERI_BASE + 0x006AC00UL) +#define TSB_TSPI4_BASE (PERI_BASE + 0x006B000UL) +#define TSB_TSPI5_BASE (PERI_BASE + 0x006B400UL) +#define TSB_TSPI6_BASE (PERI_BASE + 0x00CB800UL) +#define TSB_TSPI7_BASE (PERI_BASE + 0x00CBC00UL) +#define TSB_TSPI8_BASE (PERI_BASE + 0x00CC000UL) +#define TSB_EXB_BASE (PERI_BASE + 0x0076000UL) +#define TSB_CG_BASE (PERI_BASE + 0x0083000UL) +#define TSB_IB_BASE (PERI_BASE + 0x0083200UL) +#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL) +#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL) +#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL) +#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL) +#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL) +#define TSB_MDMAA_BASE (PERI_BASE + 0x00A4000UL) +#define TSB_FURT0_BASE (PERI_BASE + 0x00A8000UL) +#define TSB_FURT1_BASE (PERI_BASE + 0x00A9000UL) +#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL) +#define TSB_DA0_BASE (PERI_BASE + 0x00BC800UL) +#define TSB_DA1_BASE (PERI_BASE + 0x00BC900UL) +#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL) +#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL) +#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL) +#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL) +#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL) +#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL) +#define TSB_T32A6_BASE (PERI_BASE + 0x00C2800UL) +#define TSB_T32A7_BASE (PERI_BASE + 0x00C2C00UL) +#define TSB_T32A8_BASE (PERI_BASE + 0x00C3000UL) +#define TSB_T32A9_BASE (PERI_BASE + 0x00C3400UL) +#define TSB_T32A10_BASE (PERI_BASE + 0x00C3800UL) +#define TSB_T32A11_BASE (PERI_BASE + 0x00C3C00UL) +#define TSB_T32A12_BASE (PERI_BASE + 0x00C4000UL) +#define TSB_T32A13_BASE (PERI_BASE + 0x00C4400UL) +#define TSB_T32A14_BASE (PERI_BASE + 0x00C4800UL) +#define TSB_T32A15_BASE (PERI_BASE + 0x00C4C00UL) +#define TSB_TSSI0_BASE (PERI_BASE + 0x00CD000UL) +#define TSB_TSSI1_BASE (PERI_BASE + 0x00CD400UL) +#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL) +#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL) +#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL) +#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL) +#define TSB_UART4_BASE (PERI_BASE + 0x00CF000UL) +#define TSB_UART5_BASE (PERI_BASE + 0x00CF400UL) +#define TSB_I2S0_BASE (PERI_BASE + 0x00D0000UL) +#define TSB_I2S1_BASE (PERI_BASE + 0x00D0800UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL) +#define TSB_I2C2_BASE (PERI_BASE + 0x00D3000UL) +#define TSB_I2C3_BASE (PERI_BASE + 0x00D4000UL) +#define TSB_I2C4_BASE (PERI_BASE + 0x00D5000UL) +#define TSB_EI2C0_BASE (PERI_BASE + 0x00D8000UL) +#define TSB_EI2C1_BASE (PERI_BASE + 0x00D9000UL) +#define TSB_EI2C2_BASE (PERI_BASE + 0x00DA000UL) +#define TSB_EI2C3_BASE (PERI_BASE + 0x00DB000UL) +#define TSB_EI2C4_BASE (PERI_BASE + 0x00DC000UL) +#define TSB_FIRnore_BASE (PERI_BASE + 0x00DD000UL) +#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL) +#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL) +#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL) +#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL) +#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL) +#define TSB_PP_BASE (PERI_BASE + 0x00E0D00UL) +#define TSB_PR_BASE (PERI_BASE + 0x00E0E00UL) +#define TSB_PT_BASE (PERI_BASE + 0x00E0F00UL) +#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL) +#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL) +#define TSB_PW_BASE (PERI_BASE + 0x00E1200UL) +#define TSB_PY_BASE (PERI_BASE + 0x00E1300UL) +#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL) +#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL) +#define TSB_RTC_BASE (PERI_BASE + 0x00E4800UL) +#define TSB_CEC0_BASE (PERI_BASE + 0x00E8000UL) +#define TSB_RMC0_BASE (PERI_BASE + 0x00E8100UL) +#define TSB_RMC1_BASE (PERI_BASE + 0x00E8200UL) +#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL) +#define TSB_ISDA_BASE (PERI_BASE + 0x00F0000UL) +#define TSB_ISDB_BASE (PERI_BASE + 0x00F0100UL) +#define TSB_ISDC_BASE (PERI_BASE + 0x00F0200UL) +#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) + + +/* Peripheral declaration */ +#define TSB_DMACA (( TSB_DMAC_TypeDef *) TSB_DMACA_BASE) +#define TSB_DMACB (( TSB_DMAC_TypeDef *) TSB_DMACB_BASE) +#define TSB_SMI0 (( TSB_SMI_TypeDef *) TSB_SMI0_BASE) +#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) +#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) +#define TSB_LTT0 (( TSB_LTT_TypeDef *) TSB_LTT0_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) +#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) +#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) +#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) +#define TSB_TSPI5 (( TSB_TSPI_TypeDef *) TSB_TSPI5_BASE) +#define TSB_TSPI6 (( TSB_TSPI_TypeDef *) TSB_TSPI6_BASE) +#define TSB_TSPI7 (( TSB_TSPI_TypeDef *) TSB_TSPI7_BASE) +#define TSB_TSPI8 (( TSB_TSPI_TypeDef *) TSB_TSPI8_BASE) +#define TSB_EXB (( TSB_EXB_TypeDef *) TSB_EXB_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) +#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) +#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) +#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) +#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) +#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE) +#define TSB_MDMAA (( TSB_MDMA_TypeDef *) TSB_MDMAA_BASE) +#define TSB_FURT0 (( TSB_FURT_TypeDef *) TSB_FURT0_BASE) +#define TSB_FURT1 (( TSB_FURT_TypeDef *) TSB_FURT1_BASE) +#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) +#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) +#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) +#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) +#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) +#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) +#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) +#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) +#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) +#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) +#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) +#define TSB_T32A8 (( TSB_T32A_TypeDef *) TSB_T32A8_BASE) +#define TSB_T32A9 (( TSB_T32A_TypeDef *) TSB_T32A9_BASE) +#define TSB_T32A10 (( TSB_T32A_TypeDef *)TSB_T32A10_BASE) +#define TSB_T32A11 (( TSB_T32A_TypeDef *)TSB_T32A11_BASE) +#define TSB_T32A12 (( TSB_T32A_TypeDef *)TSB_T32A12_BASE) +#define TSB_T32A13 (( TSB_T32A_TypeDef *)TSB_T32A13_BASE) +#define TSB_T32A14 (( TSB_T32A_TypeDef *)TSB_T32A14_BASE) +#define TSB_T32A15 (( TSB_T32A_TypeDef *)TSB_T32A15_BASE) +#define TSB_TSSI0 (( TSB_TSSI_TypeDef *) TSB_TSSI0_BASE) +#define TSB_TSSI1 (( TSB_TSSI_TypeDef *) TSB_TSSI1_BASE) +#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) +#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) +#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) +#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) +#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) +#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) +#define TSB_I2S0 (( TSB_I2S_TypeDef *) TSB_I2S0_BASE) +#define TSB_I2S1 (( TSB_I2S_TypeDef *) TSB_I2S1_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) +#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) +#define TSB_I2C4 (( TSB_I2C_TypeDef *) TSB_I2C4_BASE) +#define TSB_EI2C0 (( TSB_EI2C_TypeDef *) TSB_EI2C0_BASE) +#define TSB_EI2C1 (( TSB_EI2C_TypeDef *) TSB_EI2C1_BASE) +#define TSB_EI2C2 (( TSB_EI2C_TypeDef *) TSB_EI2C2_BASE) +#define TSB_EI2C3 (( TSB_EI2C_TypeDef *) TSB_EI2C3_BASE) +#define TSB_EI2C4 (( TSB_EI2C_TypeDef *) TSB_EI2C4_BASE) +#define TSB_FIRnore (( TSB_FIR_TypeDef *)TSB_FIRnore_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) +#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) +#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) +#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) +#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) +#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) +#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) +#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) +#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) +#define TSB_PW (( TSB_PW_TypeDef *) TSB_PW_BASE) +#define TSB_PY (( TSB_PY_TypeDef *) TSB_PY_BASE) +#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) +#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) +#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) +#define TSB_CEC0 (( TSB_CEC_TypeDef *) TSB_CEC0_BASE) +#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) +#define TSB_RMC1 (( TSB_RMC_TypeDef *) TSB_RMC1_BASE) +#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) +#define TSB_ISDA (( TSB_ISD_TypeDef *) TSB_ISDA_BASE) +#define TSB_ISDB (( TSB_ISD_TypeDef *) TSB_ISDB_BASE) +#define TSB_ISDC (( TSB_ISD_TypeDef *) TSB_ISDC_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + +/* DMA Controller */ +#define TSB_DMACA_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,0))) +#define TSB_DMACA_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,1))) +#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,0))) +#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,1))) +#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,0))) +#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,1))) +#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,0))) +#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,1))) +#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,0))) +#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,1))) +#define TSB_DMACA_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,0))) +#define TSB_DMACA_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,1))) +#define TSB_DMACA_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->CONFIGURATION,0))) +#define TSB_DMACA_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,26))) +#define TSB_DMACA_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,27))) +#define TSB_DMACA_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,31))) +#define TSB_DMACA_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,0))) +#define TSB_DMACA_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,14))) +#define TSB_DMACA_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,15))) +#define TSB_DMACA_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,16))) +#define TSB_DMACA_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,17))) +#define TSB_DMACA_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,18))) +#define TSB_DMACA_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,26))) +#define TSB_DMACA_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,27))) +#define TSB_DMACA_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,31))) +#define TSB_DMACA_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,0))) +#define TSB_DMACA_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,14))) +#define TSB_DMACA_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,15))) +#define TSB_DMACA_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,16))) +#define TSB_DMACA_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,17))) +#define TSB_DMACA_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,18))) + +#define TSB_DMACB_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,0))) +#define TSB_DMACB_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,1))) +#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,0))) +#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,1))) +#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,0))) +#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,1))) +#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,0))) +#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,1))) +#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,0))) +#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,1))) +#define TSB_DMACB_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,0))) +#define TSB_DMACB_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,1))) +#define TSB_DMACB_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->CONFIGURATION,0))) +#define TSB_DMACB_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,26))) +#define TSB_DMACB_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,27))) +#define TSB_DMACB_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,31))) +#define TSB_DMACB_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,0))) +#define TSB_DMACB_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,14))) +#define TSB_DMACB_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,15))) +#define TSB_DMACB_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,16))) +#define TSB_DMACB_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,17))) +#define TSB_DMACB_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,18))) +#define TSB_DMACB_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,26))) +#define TSB_DMACB_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,27))) +#define TSB_DMACB_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,31))) +#define TSB_DMACB_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,0))) +#define TSB_DMACB_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,14))) +#define TSB_DMACB_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,15))) +#define TSB_DMACB_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,16))) +#define TSB_DMACB_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,17))) +#define TSB_DMACB_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,18))) + + +/* SMIF */ +#define TSB_SMI0_MAP0_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,0))) +#define TSB_SMI0_MAP0_WE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,1))) +#define TSB_SMI0_MAP1_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP1,0))) +#define TSB_SMI0_DACR0_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR0,6))) +#define TSB_SMI0_DACR1_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR1,6))) +#define TSB_SMI0_DRCR0_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DRCR0,8))) +#define TSB_SMI0_DRCR1_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DRCR1,8))) +#define TSB_SMI0_DWCR0_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DWCR0,8))) +#define TSB_SMI0_DWCR1_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DWCR1,8))) +#define TSB_SMI0_RACR1_CYCGO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,0))) +#define TSB_SMI0_RACR1_CSNUM (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,1))) +#define TSB_SMI0_RACR1_PBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,4))) +#define TSB_SMI0_RACR1_SBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,5))) +#define TSB_SMI0_OECR_PBUFOCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->OECR,0))) +#define TSB_SMI0_INT_SCDINTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,0))) +#define TSB_SMI0_INT_SDINTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,4))) +#define TSB_SMI0_STAT_CYCDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,0))) +#define TSB_SMI0_STAT_CYCPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,1))) +#define TSB_SMI0_STAT_STPPROGDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,4))) +#define TSB_SMI0_STAT_DIACCINPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,6))) +#define TSB_SMI0_SWR_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->SWR,0))) +#define TSB_SMI0_ACKR_FRCCLKOUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->ACKR,0))) +#define TSB_SMI0_ACKR_ADDCLKTGLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->ACKR,8))) +#define TSB_SMI0_CCOR_CLKOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,0))) +#define TSB_SMI0_CCOR_CS0OE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,4))) +#define TSB_SMI0_CCOR_CS1OE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,5))) +#define TSB_SMI0_STPR_STOPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STPR,0))) + + + +/* Low speed oscillation/power control/reset */ +#define TSB_RLM_LOSCCR_DRCOSCL (*((__IO uint32_t *)BITBAND_PERI(&TSB_RLM->LOSCCR,2))) + + +/* LVD0 */ +#define TSB_LVD_CR1_LVDNEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0))) +#define TSB_LVD_CR1_LVDSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,4))) +#define TSB_LVD_CR2_LVDOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR2,0))) +#define TSB_LVD_SR_LVDNS (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->SR,0))) + + +/* TRGSEL */ +#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) +#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) +#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) +#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) +#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) +#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) +#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) +#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) +#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) +#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) +#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) +#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) +#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) +#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) +#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) +#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) +#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) +#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) +#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) +#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) +#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) +#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) +#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) +#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) +#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) +#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) +#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) +#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) +#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) +#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) +#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) +#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) +#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) +#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) +#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) +#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) +#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) +#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) +#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) +#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) +#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) +#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) +#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) +#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) +#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) +#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) +#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) +#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) +#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) +#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) +#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) +#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) +#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) +#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) +#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) +#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) +#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) +#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) +#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) +#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) +#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) +#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) +#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) +#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) +#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) +#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) +#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) +#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) +#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) +#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) +#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) +#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) +#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) +#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) +#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) +#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) +#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) +#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) +#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) +#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) +#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) +#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) +#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) +#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) +#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) +#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) +#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) +#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) +#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) +#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) +#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) +#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) +#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) +#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) +#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) +#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) +#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) +#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) +#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) +#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) +#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) +#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) +#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) +#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) +#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) +#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) +#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) +#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) +#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) +#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) +#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) +#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) +#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) +#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) +#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) +#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) +#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) +#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) +#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) +#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) +#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) +#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) +#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) +#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) +#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) +#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) +#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) +#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) +#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) +#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) +#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) +#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) +#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) +#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) +#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) +#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) +#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) +#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) +#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) +#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) +#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) +#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) +#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) +#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) +#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) +#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) +#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) +#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) +#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) +#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) +#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) +#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) +#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) +#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) +#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) +#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) +#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) +#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) +#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) +#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) +#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) +#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) +#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) +#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) +#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) +#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) +#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) +#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) +#define TSB_TSEL0_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,0))) +#define TSB_TSEL0_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,1))) +#define TSB_TSEL0_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,2))) + + + +/* Serial Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) +#define TSB_TSPI0_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,16))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) +#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) +#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) +#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SECTCR0,0))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) +#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) + +#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) +#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) +#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) +#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) +#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) +#define TSB_TSPI1_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,16))) +#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) +#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) +#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) +#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) +#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) +#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) +#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) +#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) +#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) +#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) +#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) +#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) +#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) +#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) +#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) +#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) +#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) +#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) +#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) +#define TSB_TSPI1_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SECTCR0,0))) +#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) +#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) +#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) +#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) +#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) +#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) +#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) +#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) +#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) +#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) +#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) +#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) +#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) + +#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) +#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) +#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) +#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) +#define TSB_TSPI2_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) +#define TSB_TSPI2_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,16))) +#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) +#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) +#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) +#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) +#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) +#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) +#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) +#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) +#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) +#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) +#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) +#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) +#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) +#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) +#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) +#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) +#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) +#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) +#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) +#define TSB_TSPI2_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SECTCR0,0))) +#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) +#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) +#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) +#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) +#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) +#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) +#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) +#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) +#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) +#define TSB_TSPI2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,0))) +#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) +#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) +#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) + +#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) +#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) +#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) +#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) +#define TSB_TSPI3_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) +#define TSB_TSPI3_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,16))) +#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) +#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) +#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) +#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) +#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) +#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) +#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) +#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) +#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) +#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) +#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) +#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) +#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) +#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) +#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) +#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) +#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) +#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) +#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) +#define TSB_TSPI3_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SECTCR0,0))) +#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) +#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) +#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) +#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) +#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) +#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) +#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) +#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) +#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) +#define TSB_TSPI3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,0))) +#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) +#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) +#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) + +#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) +#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) +#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) +#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) +#define TSB_TSPI4_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) +#define TSB_TSPI4_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,16))) +#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) +#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) +#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) +#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) +#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) +#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) +#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) +#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) +#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) +#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) +#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) +#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) +#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) +#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) +#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) +#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) +#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) +#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) +#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) +#define TSB_TSPI4_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SECTCR0,0))) +#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) +#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) +#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) +#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) +#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) +#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) +#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) +#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) +#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) +#define TSB_TSPI4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,0))) +#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) +#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) +#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) + +#define TSB_TSPI5_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR0,0))) +#define TSB_TSPI5_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,12))) +#define TSB_TSPI5_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,13))) +#define TSB_TSPI5_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,14))) +#define TSB_TSPI5_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,15))) +#define TSB_TSPI5_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,16))) +#define TSB_TSPI5_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,0))) +#define TSB_TSPI5_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,1))) +#define TSB_TSPI5_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,2))) +#define TSB_TSPI5_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,4))) +#define TSB_TSPI5_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,5))) +#define TSB_TSPI5_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,6))) +#define TSB_TSPI5_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,7))) +#define TSB_TSPI5_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,21))) +#define TSB_TSPI5_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,0))) +#define TSB_TSPI5_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,1))) +#define TSB_TSPI5_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,14))) +#define TSB_TSPI5_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,15))) +#define TSB_TSPI5_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,16))) +#define TSB_TSPI5_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,17))) +#define TSB_TSPI5_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,18))) +#define TSB_TSPI5_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,19))) +#define TSB_TSPI5_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,31))) +#define TSB_TSPI5_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,0))) +#define TSB_TSPI5_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,1))) +#define TSB_TSPI5_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SECTCR0,0))) +#define TSB_TSPI5_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,4))) +#define TSB_TSPI5_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,5))) +#define TSB_TSPI5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,6))) +#define TSB_TSPI5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,7))) +#define TSB_TSPI5_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,20))) +#define TSB_TSPI5_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,21))) +#define TSB_TSPI5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,22))) +#define TSB_TSPI5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,23))) +#define TSB_TSPI5_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,31))) +#define TSB_TSPI5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,0))) +#define TSB_TSPI5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,1))) +#define TSB_TSPI5_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,2))) +#define TSB_TSPI5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,3))) + +#define TSB_TSPI6_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR0,0))) +#define TSB_TSPI6_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,12))) +#define TSB_TSPI6_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,13))) +#define TSB_TSPI6_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,14))) +#define TSB_TSPI6_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,15))) +#define TSB_TSPI6_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,16))) +#define TSB_TSPI6_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,0))) +#define TSB_TSPI6_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,1))) +#define TSB_TSPI6_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,2))) +#define TSB_TSPI6_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,4))) +#define TSB_TSPI6_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,5))) +#define TSB_TSPI6_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,6))) +#define TSB_TSPI6_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,7))) +#define TSB_TSPI6_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,21))) +#define TSB_TSPI6_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,0))) +#define TSB_TSPI6_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,1))) +#define TSB_TSPI6_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,14))) +#define TSB_TSPI6_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,15))) +#define TSB_TSPI6_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,16))) +#define TSB_TSPI6_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,17))) +#define TSB_TSPI6_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,18))) +#define TSB_TSPI6_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,19))) +#define TSB_TSPI6_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,31))) +#define TSB_TSPI6_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,0))) +#define TSB_TSPI6_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,1))) +#define TSB_TSPI6_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SECTCR0,0))) +#define TSB_TSPI6_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,4))) +#define TSB_TSPI6_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,5))) +#define TSB_TSPI6_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,6))) +#define TSB_TSPI6_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,7))) +#define TSB_TSPI6_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,20))) +#define TSB_TSPI6_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,21))) +#define TSB_TSPI6_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,22))) +#define TSB_TSPI6_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,23))) +#define TSB_TSPI6_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,31))) +#define TSB_TSPI6_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,0))) +#define TSB_TSPI6_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,1))) +#define TSB_TSPI6_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,2))) +#define TSB_TSPI6_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,3))) + +#define TSB_TSPI7_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR0,0))) +#define TSB_TSPI7_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,12))) +#define TSB_TSPI7_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,13))) +#define TSB_TSPI7_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,14))) +#define TSB_TSPI7_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,15))) +#define TSB_TSPI7_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,16))) +#define TSB_TSPI7_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,0))) +#define TSB_TSPI7_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,1))) +#define TSB_TSPI7_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,2))) +#define TSB_TSPI7_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,4))) +#define TSB_TSPI7_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,5))) +#define TSB_TSPI7_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,6))) +#define TSB_TSPI7_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,7))) +#define TSB_TSPI7_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,21))) +#define TSB_TSPI7_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,0))) +#define TSB_TSPI7_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,1))) +#define TSB_TSPI7_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,14))) +#define TSB_TSPI7_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,15))) +#define TSB_TSPI7_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,16))) +#define TSB_TSPI7_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,17))) +#define TSB_TSPI7_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,18))) +#define TSB_TSPI7_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,19))) +#define TSB_TSPI7_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,31))) +#define TSB_TSPI7_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,0))) +#define TSB_TSPI7_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,1))) +#define TSB_TSPI7_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SECTCR0,0))) +#define TSB_TSPI7_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,4))) +#define TSB_TSPI7_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,5))) +#define TSB_TSPI7_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,6))) +#define TSB_TSPI7_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,7))) +#define TSB_TSPI7_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,20))) +#define TSB_TSPI7_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,21))) +#define TSB_TSPI7_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,22))) +#define TSB_TSPI7_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,23))) +#define TSB_TSPI7_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,31))) +#define TSB_TSPI7_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,0))) +#define TSB_TSPI7_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,1))) +#define TSB_TSPI7_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,2))) +#define TSB_TSPI7_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,3))) + +#define TSB_TSPI8_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR0,0))) +#define TSB_TSPI8_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,12))) +#define TSB_TSPI8_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,13))) +#define TSB_TSPI8_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,14))) +#define TSB_TSPI8_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,15))) +#define TSB_TSPI8_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,16))) +#define TSB_TSPI8_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,0))) +#define TSB_TSPI8_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,1))) +#define TSB_TSPI8_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,2))) +#define TSB_TSPI8_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,4))) +#define TSB_TSPI8_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,5))) +#define TSB_TSPI8_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,6))) +#define TSB_TSPI8_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,7))) +#define TSB_TSPI8_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,21))) +#define TSB_TSPI8_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,0))) +#define TSB_TSPI8_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,1))) +#define TSB_TSPI8_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,14))) +#define TSB_TSPI8_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,15))) +#define TSB_TSPI8_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,16))) +#define TSB_TSPI8_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,17))) +#define TSB_TSPI8_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,18))) +#define TSB_TSPI8_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,19))) +#define TSB_TSPI8_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,31))) +#define TSB_TSPI8_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,0))) +#define TSB_TSPI8_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,1))) +#define TSB_TSPI8_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SECTCR0,0))) +#define TSB_TSPI8_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,4))) +#define TSB_TSPI8_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,5))) +#define TSB_TSPI8_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,6))) +#define TSB_TSPI8_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,7))) +#define TSB_TSPI8_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,20))) +#define TSB_TSPI8_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,21))) +#define TSB_TSPI8_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,22))) +#define TSB_TSPI8_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,23))) +#define TSB_TSPI8_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,31))) +#define TSB_TSPI8_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,0))) +#define TSB_TSPI8_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,1))) +#define TSB_TSPI8_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,2))) +#define TSB_TSPI8_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,3))) + + +/* External Bus Interface(EXB) */ +#define TSB_EXB_MOD_EXBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->MOD,0))) +#define TSB_EXB_CS0_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,0))) +#define TSB_EXB_CS0_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,12))) +#define TSB_EXB_CS0_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,13))) +#define TSB_EXB_CS1_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,0))) +#define TSB_EXB_CS1_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,12))) +#define TSB_EXB_CS1_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,13))) +#define TSB_EXB_CS2_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,0))) +#define TSB_EXB_CS2_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,12))) +#define TSB_EXB_CS2_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,13))) +#define TSB_EXB_CS3_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,0))) +#define TSB_EXB_CS3_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,12))) +#define TSB_EXB_CS3_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,13))) +#define TSB_EXB_CLKCTL_CLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CLKCTL,0))) + + +/* Clock Generator (CG) */ +#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) +#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) +#define TSB_CG_FSYSMENC_IPMENC00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,0))) +#define TSB_CG_FSYSMENC_IPMENC01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,1))) +#define TSB_CG_FSYSMENC_IPMENC02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,2))) +#define TSB_CG_FSYSMENC_IPMENC03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,3))) +#define TSB_CG_FSYSMENC_IPMENC04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,4))) +#define TSB_CG_FSYSMENC_IPMENC05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,5))) +#define TSB_CG_FSYSMENC_IPMENC06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,6))) +#define TSB_CG_FSYSMENC_IPMENC07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,7))) +#define TSB_CG_FSYSMENC_IPMENC08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,8))) +#define TSB_CG_FSYSMENC_IPMENC09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,9))) +#define TSB_CG_FSYSMENC_IPMENC15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,15))) +#define TSB_CG_FSYSMENC_IPMENC16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,16))) +#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0))) +#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1))) +#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2))) +#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3))) +#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4))) +#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5))) +#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6))) +#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7))) +#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8))) +#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9))) +#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10))) +#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11))) +#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12))) +#define TSB_CG_FSYSMENA_IPMENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,13))) +#define TSB_CG_FSYSMENA_IPMENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,14))) +#define TSB_CG_FSYSMENA_IPMENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,15))) +#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16))) +#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17))) +#define TSB_CG_FSYSMENA_IPMENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,18))) +#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19))) +#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20))) +#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21))) +#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22))) +#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23))) +#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24))) +#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25))) +#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26))) +#define TSB_CG_FSYSMENA_IPMENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,27))) +#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28))) +#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29))) +#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30))) +#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31))) +#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0))) +#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1))) +#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2))) +#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3))) +#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4))) +#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5))) +#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6))) +#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7))) +#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8))) +#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9))) +#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10))) +#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11))) +#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12))) +#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13))) +#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14))) +#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15))) +#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16))) +#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17))) +#define TSB_CG_FSYSMENB_IPMENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,18))) +#define TSB_CG_FSYSMENB_IPMENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,19))) +#define TSB_CG_FSYSMENB_IPMENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,20))) +#define TSB_CG_FSYSMENB_IPMENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,21))) +#define TSB_CG_FSYSMENB_IPMENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,22))) +#define TSB_CG_FSYSMENB_IPMENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,23))) +#define TSB_CG_FSYSMENB_IPMENB24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,24))) +#define TSB_CG_FSYSMENB_IPMENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,28))) +#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29))) +#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30))) +#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31))) +#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) +#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) +#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) +#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) +#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) +#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) +#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) +#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) +#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) +#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) +#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23))) +#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26))) +#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27))) +#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) +#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) +#define TSB_CG_EXTEND2_RSV20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,0))) +#define TSB_CG_EXTEND2_RSV21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,1))) +#define TSB_CG_EXTEND2_RSV22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,2))) + + + +/* Interrupt Monitor Register */ +#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) +#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) +#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) +#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) +#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) +#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) +#define TSB_IMN_FLG1_INT036FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,4))) +#define TSB_IMN_FLG1_INT037FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,5))) +#define TSB_IMN_FLG1_INT038FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,6))) +#define TSB_IMN_FLG1_INT039FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,7))) +#define TSB_IMN_FLG1_INT040FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,8))) +#define TSB_IMN_FLG1_INT041FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,9))) +#define TSB_IMN_FLG1_INT042FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,10))) +#define TSB_IMN_FLG1_INT043FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,11))) +#define TSB_IMN_FLG1_INT044FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,12))) +#define TSB_IMN_FLG1_INT045FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,13))) +#define TSB_IMN_FLG1_INT046FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,14))) +#define TSB_IMN_FLG1_INT047FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,15))) +#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) +#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) +#define TSB_IMN_FLG1_INT050FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,18))) +#define TSB_IMN_FLG1_INT051FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,19))) +#define TSB_IMN_FLG1_INT052FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,20))) +#define TSB_IMN_FLG1_INT053FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,21))) +#define TSB_IMN_FLG1_INT054FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,22))) +#define TSB_IMN_FLG1_INT055FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,23))) +#define TSB_IMN_FLG1_INT056FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,24))) +#define TSB_IMN_FLG1_INT057FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,25))) +#define TSB_IMN_FLG1_INT058FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,26))) +#define TSB_IMN_FLG1_INT059FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,27))) +#define TSB_IMN_FLG1_INT060FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,28))) +#define TSB_IMN_FLG1_INT061FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,29))) +#define TSB_IMN_FLG1_INT062FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,30))) +#define TSB_IMN_FLG1_INT063FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,31))) +#define TSB_IMN_FLG2_INT081FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,17))) +#define TSB_IMN_FLG2_INT082FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,18))) +#define TSB_IMN_FLG2_INT083FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,19))) +#define TSB_IMN_FLG2_INT084FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,20))) +#define TSB_IMN_FLG2_INT085FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,21))) +#define TSB_IMN_FLG2_INT086FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,22))) +#define TSB_IMN_FLG2_INT087FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,23))) +#define TSB_IMN_FLG2_INT088FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,24))) +#define TSB_IMN_FLG2_INT089FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,25))) +#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) +#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) +#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) +#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) +#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) +#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) +#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) +#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) +#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) +#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) +#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) +#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) +#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) +#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) +#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) +#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) +#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) +#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) +#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) +#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) +#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) +#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) +#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) +#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) +#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) +#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) +#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) +#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) +#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) +#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) +#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) +#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) +#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) +#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) +#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) +#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) +#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) +#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) +#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) +#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) +#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) +#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) +#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) +#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) +#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) +#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) +#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) +#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) +#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) +#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) +#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) +#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) +#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) +#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) +#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) +#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) +#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) +#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) +#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) +#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) +#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) +#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) +#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) +#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) +#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) +#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) +#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) +#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) +#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) +#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) +#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) +#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) +#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) +#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) +#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) +#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) +#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) +#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) +#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) +#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) +#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) +#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) +#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) +#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) +#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) +#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) +#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) +#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) +#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) +#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) +#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) +#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) +#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) +#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) +#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) +#define TSB_IMN_FLG5_INT191FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,31))) +#define TSB_IMN_FLG6_INT192FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,0))) +#define TSB_IMN_FLG6_INT193FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,1))) +#define TSB_IMN_FLG6_INT194FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,2))) +#define TSB_IMN_FLG6_INT195FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,3))) +#define TSB_IMN_FLG6_INT196FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,4))) +#define TSB_IMN_FLG6_INT197FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,5))) +#define TSB_IMN_FLG6_INT198FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,6))) +#define TSB_IMN_FLG6_INT199FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,7))) +#define TSB_IMN_FLG6_INT200FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,8))) +#define TSB_IMN_FLG6_INT201FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,9))) +#define TSB_IMN_FLG6_INT202FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,10))) +#define TSB_IMN_FLG6_INT203FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,11))) +#define TSB_IMN_FLG6_INT204FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,12))) +#define TSB_IMN_FLG6_INT205FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,13))) +#define TSB_IMN_FLG6_INT206FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,14))) +#define TSB_IMN_FLG6_INT207FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,15))) +#define TSB_IMN_FLG6_INT208FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,16))) +#define TSB_IMN_FLG6_INT209FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,17))) +#define TSB_IMN_FLG6_INT210FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,18))) +#define TSB_IMN_FLG6_INT211FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,19))) +#define TSB_IMN_FLG6_INT212FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,20))) +#define TSB_IMN_FLG6_INT213FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,21))) +#define TSB_IMN_FLG6_INT214FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,22))) +#define TSB_IMN_FLG6_INT215FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,23))) +#define TSB_IMN_FLG6_INT216FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,24))) +#define TSB_IMN_FLG6_INT217FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,25))) +#define TSB_IMN_FLG6_INT218FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,26))) +#define TSB_IMN_FLG6_INT219FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,27))) +#define TSB_IMN_FLG6_INT220FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,28))) +#define TSB_IMN_FLG6_INT221FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,29))) +#define TSB_IMN_FLG6_INT222FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,30))) +#define TSB_IMN_FLG6_INT223FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,31))) +#define TSB_IMN_FLG7_INT224FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,0))) +#define TSB_IMN_FLG7_INT225FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,1))) +#define TSB_IMN_FLG7_INT226FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,2))) +#define TSB_IMN_FLG7_INT227FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,3))) +#define TSB_IMN_FLG7_INT228FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,4))) +#define TSB_IMN_FLG7_INT229FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,5))) +#define TSB_IMN_FLG7_INT230FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,6))) +#define TSB_IMN_FLG7_INT231FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,7))) +#define TSB_IMN_FLG7_INT232FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,8))) +#define TSB_IMN_FLG7_INT233FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,9))) +#define TSB_IMN_FLG7_INT234FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,10))) +#define TSB_IMN_FLG7_INT235FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,11))) +#define TSB_IMN_FLG7_INT236FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,12))) +#define TSB_IMN_FLG7_INT237FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,13))) +#define TSB_IMN_FLG7_INT241FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,17))) +#define TSB_IMN_FLG7_INT242FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,18))) +#define TSB_IMN_FLG7_INT243FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,19))) +#define TSB_IMN_FLG7_INT244FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,20))) +#define TSB_IMN_FLG7_INT245FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,21))) +#define TSB_IMN_FLG7_INT246FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,22))) +#define TSB_IMN_FLG7_INT247FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,23))) +#define TSB_IMN_FLG7_INT248FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,24))) +#define TSB_IMN_FLG7_INT249FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,25))) +#define TSB_IMN_FLG7_INT250FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,26))) +#define TSB_IMN_FLG7_INT251FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,27))) +#define TSB_IMN_FLG7_INT252FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,28))) +#define TSB_IMN_FLG7_INT253FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,29))) +#define TSB_IMN_FLG7_INT254FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,30))) +#define TSB_IMN_FLG7_INT255FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,31))) + + +/* DNF */ +#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) +#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) +#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) +#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) +#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) +#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) +#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) +#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) +#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) +#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) +#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) +#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) +#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) +#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) +#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) +#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) + +#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) +#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) +#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) +#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) +#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) +#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) +#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) +#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) +#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) +#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) +#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) +#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) +#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) +#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) +#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) +#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) + + +/* Watchdog Timer (SIWDT) */ +#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) +#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) +#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) +#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) + + +/* NBDIF */ +#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0))) + + +/* Malti Porpose Direct Memory Accsess(MDMA) */ +#define TSB_MDMAA_XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,16))) +#define TSB_MDMAA_XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,24))) +#define TSB_MDMAA_DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->DSNUM,8))) +#define TSB_MDMAA_C00XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,16))) +#define TSB_MDMAA_C00XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,24))) +#define TSB_MDMAA_C00DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00DSNUM,8))) +#define TSB_MDMAA_C01XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,16))) +#define TSB_MDMAA_C01XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,24))) +#define TSB_MDMAA_C01DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01DSNUM,8))) +#define TSB_MDMAA_C02XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,16))) +#define TSB_MDMAA_C02XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,24))) +#define TSB_MDMAA_C02DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02DSNUM,8))) +#define TSB_MDMAA_C03XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,16))) +#define TSB_MDMAA_C03XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,24))) +#define TSB_MDMAA_C03DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03DSNUM,8))) +#define TSB_MDMAA_C04XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,16))) +#define TSB_MDMAA_C04XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,24))) +#define TSB_MDMAA_C04DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04DSNUM,8))) +#define TSB_MDMAA_C05XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,16))) +#define TSB_MDMAA_C05XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,24))) +#define TSB_MDMAA_C05DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05DSNUM,8))) +#define TSB_MDMAA_C06XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,16))) +#define TSB_MDMAA_C06XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,24))) +#define TSB_MDMAA_C06DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06DSNUM,8))) +#define TSB_MDMAA_C07XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,16))) +#define TSB_MDMAA_C07XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,24))) +#define TSB_MDMAA_C07DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07DSNUM,8))) +#define TSB_MDMAA_C08XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,16))) +#define TSB_MDMAA_C08XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,24))) +#define TSB_MDMAA_C08DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08DSNUM,8))) +#define TSB_MDMAA_C09XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,16))) +#define TSB_MDMAA_C09XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,24))) +#define TSB_MDMAA_C09DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09DSNUM,8))) +#define TSB_MDMAA_C10XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,16))) +#define TSB_MDMAA_C10XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,24))) +#define TSB_MDMAA_C10DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10DSNUM,8))) +#define TSB_MDMAA_C11XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,16))) +#define TSB_MDMAA_C11XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,24))) +#define TSB_MDMAA_C11DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11DSNUM,8))) +#define TSB_MDMAA_C12XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,16))) +#define TSB_MDMAA_C12XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,24))) +#define TSB_MDMAA_C12DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12DSNUM,8))) +#define TSB_MDMAA_C13XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,16))) +#define TSB_MDMAA_C13XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,24))) +#define TSB_MDMAA_C13DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13DSNUM,8))) +#define TSB_MDMAA_C14XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,16))) +#define TSB_MDMAA_C14XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,24))) +#define TSB_MDMAA_C14DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14DSNUM,8))) +#define TSB_MDMAA_C15XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,16))) +#define TSB_MDMAA_C15XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,24))) +#define TSB_MDMAA_C15DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15DSNUM,8))) +#define TSB_MDMAA_C16XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,16))) +#define TSB_MDMAA_C16XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,24))) +#define TSB_MDMAA_C16DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16DSNUM,8))) +#define TSB_MDMAA_C17XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,16))) +#define TSB_MDMAA_C17XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,24))) +#define TSB_MDMAA_C17DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17DSNUM,8))) +#define TSB_MDMAA_C18XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,16))) +#define TSB_MDMAA_C18XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,24))) +#define TSB_MDMAA_C18DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18DSNUM,8))) +#define TSB_MDMAA_C19XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,16))) +#define TSB_MDMAA_C19XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,24))) +#define TSB_MDMAA_C19DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19DSNUM,8))) +#define TSB_MDMAA_C20XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,16))) +#define TSB_MDMAA_C20XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,24))) +#define TSB_MDMAA_C20DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20DSNUM,8))) +#define TSB_MDMAA_C21XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,16))) +#define TSB_MDMAA_C21XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,24))) +#define TSB_MDMAA_C21DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21DSNUM,8))) +#define TSB_MDMAA_C22XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,16))) +#define TSB_MDMAA_C22XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,24))) +#define TSB_MDMAA_C22DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22DSNUM,8))) +#define TSB_MDMAA_C23XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,16))) +#define TSB_MDMAA_C23XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,24))) +#define TSB_MDMAA_C23DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23DSNUM,8))) +#define TSB_MDMAA_C24XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,16))) +#define TSB_MDMAA_C24XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,24))) +#define TSB_MDMAA_C24DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24DSNUM,8))) +#define TSB_MDMAA_C25XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,16))) +#define TSB_MDMAA_C25XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,24))) +#define TSB_MDMAA_C25DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25DSNUM,8))) +#define TSB_MDMAA_C26XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,16))) +#define TSB_MDMAA_C26XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,24))) +#define TSB_MDMAA_C26DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26DSNUM,8))) +#define TSB_MDMAA_C27XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,16))) +#define TSB_MDMAA_C27XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,24))) +#define TSB_MDMAA_C27DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27DSNUM,8))) +#define TSB_MDMAA_C28XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,16))) +#define TSB_MDMAA_C28XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,24))) +#define TSB_MDMAA_C28DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28DSNUM,8))) +#define TSB_MDMAA_C29XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,16))) +#define TSB_MDMAA_C29XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,24))) +#define TSB_MDMAA_C29DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29DSNUM,8))) +#define TSB_MDMAA_C30XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,16))) +#define TSB_MDMAA_C30XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,24))) +#define TSB_MDMAA_C30DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30DSNUM,8))) +#define TSB_MDMAA_C31XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,16))) +#define TSB_MDMAA_C31XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,24))) +#define TSB_MDMAA_C31DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31DSNUM,8))) +#define TSB_MDMAA_MSK_MSK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,0))) +#define TSB_MDMAA_MSK_MSK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,1))) +#define TSB_MDMAA_MSK_MSK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,2))) +#define TSB_MDMAA_MSK_MSK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,3))) +#define TSB_MDMAA_MSK_MSK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,4))) +#define TSB_MDMAA_MSK_MSK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,5))) +#define TSB_MDMAA_MSK_MSK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,6))) +#define TSB_MDMAA_MSK_MSK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,7))) +#define TSB_MDMAA_MSK_MSK8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,8))) +#define TSB_MDMAA_MSK_MSK9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,9))) +#define TSB_MDMAA_MSK_MSK10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,10))) +#define TSB_MDMAA_MSK_MSK11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,11))) +#define TSB_MDMAA_MSK_MSK12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,12))) +#define TSB_MDMAA_MSK_MSK13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,13))) +#define TSB_MDMAA_MSK_MSK14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,14))) +#define TSB_MDMAA_MSK_MSK15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,15))) +#define TSB_MDMAA_MSK_MSK16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,16))) +#define TSB_MDMAA_MSK_MSK17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,17))) +#define TSB_MDMAA_MSK_MSK18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,18))) +#define TSB_MDMAA_MSK_MSK19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,19))) +#define TSB_MDMAA_MSK_MSK20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,20))) +#define TSB_MDMAA_MSK_MSK21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,21))) +#define TSB_MDMAA_MSK_MSK22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,22))) +#define TSB_MDMAA_MSK_MSK23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,23))) +#define TSB_MDMAA_MSK_MSK24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,24))) +#define TSB_MDMAA_MSK_MSK25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,25))) +#define TSB_MDMAA_MSK_MSK26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,26))) +#define TSB_MDMAA_MSK_MSK27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,27))) +#define TSB_MDMAA_MSK_MSK28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,28))) +#define TSB_MDMAA_MSK_MSK29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,29))) +#define TSB_MDMAA_MSK_MSK30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,30))) +#define TSB_MDMAA_MSK_MSK31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,31))) + + +/* ARM Prime Cell PL011 */ +#define TSB_FURT0_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,8))) +#define TSB_FURT0_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,9))) +#define TSB_FURT0_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,10))) +#define TSB_FURT0_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,11))) +#define TSB_FURT0_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,0))) +#define TSB_FURT0_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,1))) +#define TSB_FURT0_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,2))) +#define TSB_FURT0_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,3))) +#define TSB_FURT0_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,0))) +#define TSB_FURT0_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,3))) +#define TSB_FURT0_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,4))) +#define TSB_FURT0_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,5))) +#define TSB_FURT0_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,6))) +#define TSB_FURT0_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,7))) +#define TSB_FURT0_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,0))) +#define TSB_FURT0_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,1))) +#define TSB_FURT0_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,2))) +#define TSB_FURT0_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,3))) +#define TSB_FURT0_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,4))) +#define TSB_FURT0_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,7))) +#define TSB_FURT0_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,0))) +#define TSB_FURT0_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,1))) +#define TSB_FURT0_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,2))) +#define TSB_FURT0_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,8))) +#define TSB_FURT0_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,9))) +#define TSB_FURT0_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,14))) +#define TSB_FURT0_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,15))) +#define TSB_FURT0_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,4))) +#define TSB_FURT0_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,5))) +#define TSB_FURT0_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,6))) +#define TSB_FURT0_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,7))) +#define TSB_FURT0_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,8))) +#define TSB_FURT0_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,9))) +#define TSB_FURT0_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,10))) +#define TSB_FURT0_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,4))) +#define TSB_FURT0_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,5))) +#define TSB_FURT0_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,6))) +#define TSB_FURT0_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,7))) +#define TSB_FURT0_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,8))) +#define TSB_FURT0_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,9))) +#define TSB_FURT0_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,10))) +#define TSB_FURT0_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,4))) +#define TSB_FURT0_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,5))) +#define TSB_FURT0_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,6))) +#define TSB_FURT0_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,7))) +#define TSB_FURT0_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,8))) +#define TSB_FURT0_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,9))) +#define TSB_FURT0_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,10))) +#define TSB_FURT0_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,4))) +#define TSB_FURT0_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,5))) +#define TSB_FURT0_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,6))) +#define TSB_FURT0_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,7))) +#define TSB_FURT0_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,8))) +#define TSB_FURT0_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,9))) +#define TSB_FURT0_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,10))) +#define TSB_FURT0_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,0))) +#define TSB_FURT0_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,1))) +#define TSB_FURT0_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,2))) + +#define TSB_FURT1_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,8))) +#define TSB_FURT1_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,9))) +#define TSB_FURT1_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,10))) +#define TSB_FURT1_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,11))) +#define TSB_FURT1_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,0))) +#define TSB_FURT1_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,1))) +#define TSB_FURT1_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,2))) +#define TSB_FURT1_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,3))) +#define TSB_FURT1_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,0))) +#define TSB_FURT1_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,3))) +#define TSB_FURT1_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,4))) +#define TSB_FURT1_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,5))) +#define TSB_FURT1_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,6))) +#define TSB_FURT1_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,7))) +#define TSB_FURT1_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,0))) +#define TSB_FURT1_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,1))) +#define TSB_FURT1_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,2))) +#define TSB_FURT1_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,3))) +#define TSB_FURT1_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,4))) +#define TSB_FURT1_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,7))) +#define TSB_FURT1_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,0))) +#define TSB_FURT1_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,1))) +#define TSB_FURT1_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,2))) +#define TSB_FURT1_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,8))) +#define TSB_FURT1_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,9))) +#define TSB_FURT1_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,14))) +#define TSB_FURT1_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,15))) +#define TSB_FURT1_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,4))) +#define TSB_FURT1_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,5))) +#define TSB_FURT1_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,6))) +#define TSB_FURT1_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,7))) +#define TSB_FURT1_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,8))) +#define TSB_FURT1_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,9))) +#define TSB_FURT1_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,10))) +#define TSB_FURT1_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,4))) +#define TSB_FURT1_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,5))) +#define TSB_FURT1_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,6))) +#define TSB_FURT1_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,7))) +#define TSB_FURT1_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,8))) +#define TSB_FURT1_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,9))) +#define TSB_FURT1_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,10))) +#define TSB_FURT1_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,4))) +#define TSB_FURT1_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,5))) +#define TSB_FURT1_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,6))) +#define TSB_FURT1_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,7))) +#define TSB_FURT1_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,8))) +#define TSB_FURT1_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,9))) +#define TSB_FURT1_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,10))) +#define TSB_FURT1_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,4))) +#define TSB_FURT1_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,5))) +#define TSB_FURT1_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,6))) +#define TSB_FURT1_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,7))) +#define TSB_FURT1_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,8))) +#define TSB_FURT1_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,9))) +#define TSB_FURT1_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,10))) +#define TSB_FURT1_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,0))) +#define TSB_FURT1_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,1))) +#define TSB_FURT1_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,2))) + + +/* ADC */ +#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) +#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) +#define TSB_ADA_CR0_HPSGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,2))) +#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) +#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) +#define TSB_ADA_CR1_HPTRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,1))) +#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) +#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) +#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) +#define TSB_ADA_CR1_HPDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,7))) +#define TSB_ADA_ST_HPF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) +#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) +#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) +#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) +#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) +#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) +#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) +#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) +#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) +#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) +#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) +#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) +#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) +#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) +#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) +#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) +#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) +#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) +#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) +#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) +#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) +#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) +#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) +#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) +#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) +#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) +#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) +#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) +#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) +#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) +#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) +#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) +#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) +#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) +#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) +#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) +#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) +#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) +#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) +#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) +#define TSB_ADA_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) +#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) +#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) +#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) +#define TSB_ADA_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) +#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) +#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) +#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) +#define TSB_ADA_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) +#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) +#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) +#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) +#define TSB_ADA_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) +#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) +#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) +#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) +#define TSB_ADA_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) +#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) +#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) +#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) +#define TSB_ADA_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) +#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) +#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) +#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) +#define TSB_ADA_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) +#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) +#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) +#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) +#define TSB_ADA_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) +#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) +#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) +#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) +#define TSB_ADA_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) +#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) +#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) +#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) +#define TSB_ADA_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) +#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) +#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) +#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) +#define TSB_ADA_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) +#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) +#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) +#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) +#define TSB_ADA_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) +#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) +#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) +#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) +#define TSB_ADA_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) +#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) +#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) +#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) +#define TSB_ADA_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) +#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) +#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) +#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) +#define TSB_ADA_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) +#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) +#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) +#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) +#define TSB_ADA_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) +#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) +#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) +#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) +#define TSB_ADA_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) +#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) +#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) +#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) +#define TSB_ADA_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) +#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) +#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) +#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) +#define TSB_ADA_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) +#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) +#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) +#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) +#define TSB_ADA_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) +#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) +#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) +#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) +#define TSB_ADA_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) +#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) +#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) +#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) +#define TSB_ADA_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) +#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) +#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) +#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) +#define TSB_ADA_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) +#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) +#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) +#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) +#define TSB_ADA_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) + + +/* Digital analog converter (DAC) */ +#define TSB_DA0_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CR,0))) + +#define TSB_DA1_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CR,0))) + + +/* 16-bit Timer/Event Counter (TB) */ +#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) +#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) +#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) +#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) +#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) +#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) +#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) +#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) +#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) +#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) +#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) +#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) +#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) +#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) +#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) +#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) +#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) +#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) +#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) +#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) +#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) +#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) +#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) +#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) +#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) +#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) +#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) +#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) +#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) +#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) +#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) +#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) +#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) +#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) +#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) +#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) +#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) +#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) +#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) +#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) +#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) +#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) +#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) +#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) +#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) +#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) +#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) +#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) +#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) +#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) +#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) +#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) +#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) +#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) + +#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) +#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) +#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) +#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) +#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) +#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) +#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) +#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) +#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) +#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) +#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) +#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) +#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) +#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) +#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) +#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) +#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) +#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) +#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) +#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) +#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) +#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) +#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) +#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) +#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) +#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) +#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) +#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) +#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) +#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) +#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) +#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) +#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) +#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) +#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) +#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) +#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) +#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) +#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) +#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) +#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) +#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) +#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) +#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) +#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) +#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) +#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) +#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) +#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) +#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) +#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) +#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) +#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) +#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) + +#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) +#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) +#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) +#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) +#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) +#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) +#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) +#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) +#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) +#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) +#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) +#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) +#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) +#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) +#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) +#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) +#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) +#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) +#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) +#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) +#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) +#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) +#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) +#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) +#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) +#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) +#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) +#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) +#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) +#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) +#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) +#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) +#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) +#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) +#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) +#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) +#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) +#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) +#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) +#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) +#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) +#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) +#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) +#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) +#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) +#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) +#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) +#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) +#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) +#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) +#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) +#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) +#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) +#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) + +#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) +#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) +#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) +#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) +#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) +#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) +#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) +#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) +#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) +#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) +#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) +#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) +#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) +#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) +#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) +#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) +#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) +#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) +#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) +#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) +#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) +#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) +#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) +#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) +#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) +#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) +#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) +#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) +#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) +#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) +#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) +#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) +#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) +#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) +#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) +#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) +#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) +#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) +#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) +#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) +#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) +#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) +#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) +#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) +#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) +#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) +#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) +#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) +#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) +#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) +#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) +#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) +#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) +#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) + +#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) +#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) +#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) +#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) +#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) +#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) +#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) +#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) +#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) +#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) +#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) +#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) +#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) +#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) +#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) +#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) +#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) +#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) +#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) +#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) +#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) +#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) +#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) +#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) +#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) +#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) +#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) +#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) +#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) +#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) +#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) +#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) +#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) +#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) +#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) +#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) +#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) +#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) +#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) +#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) +#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) +#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) +#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) +#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) +#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) +#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) +#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) +#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) +#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) +#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) +#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) +#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) +#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) +#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) + +#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) +#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) +#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) +#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) +#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) +#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) +#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) +#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) +#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) +#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) +#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) +#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) +#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) +#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) +#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) +#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) +#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) +#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) +#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) +#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) +#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) +#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) +#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) +#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) +#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) +#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) +#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) +#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) +#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) +#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) +#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) +#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) +#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) +#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) +#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) +#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) +#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) +#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) +#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) +#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) +#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) +#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) +#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) +#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) +#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) +#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) +#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) +#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) +#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) +#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) +#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) +#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) +#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) +#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) + +#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) +#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) +#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) +#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) +#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) +#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) +#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) +#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) +#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) +#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) +#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) +#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) +#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) +#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) +#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) +#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) +#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) +#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) +#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) +#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) +#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) +#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) +#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) +#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) +#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) +#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) +#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) +#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) +#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) +#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) +#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) +#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) +#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) +#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) +#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) +#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) +#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) +#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) +#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) +#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) +#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) +#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) +#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) +#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) +#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) +#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) +#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) +#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) +#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) +#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) +#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) +#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) +#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) +#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) + +#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) +#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) +#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) +#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) +#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) +#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) +#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) +#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) +#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) +#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) +#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) +#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) +#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) +#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) +#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) +#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) +#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) +#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) +#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) +#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) +#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) +#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) +#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) +#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) +#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) +#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) +#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) +#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) +#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) +#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) +#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) +#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) +#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) +#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) +#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) +#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) +#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) +#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) +#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) +#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) +#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) +#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) +#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) +#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) +#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) +#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) +#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) +#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) +#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) +#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) +#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) +#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) +#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) +#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) + +#define TSB_T32A8_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,0))) +#define TSB_T32A8_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,1))) +#define TSB_T32A8_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,0))) +#define TSB_T32A8_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,1))) +#define TSB_T32A8_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,2))) +#define TSB_T32A8_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,4))) +#define TSB_T32A8_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRA,20))) +#define TSB_T32A8_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,0))) +#define TSB_T32A8_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,1))) +#define TSB_T32A8_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,2))) +#define TSB_T32A8_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,3))) +#define TSB_T32A8_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,0))) +#define TSB_T32A8_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,1))) +#define TSB_T32A8_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,2))) +#define TSB_T32A8_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,3))) +#define TSB_T32A8_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,0))) +#define TSB_T32A8_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,1))) +#define TSB_T32A8_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,2))) +#define TSB_T32A8_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,0))) +#define TSB_T32A8_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,1))) +#define TSB_T32A8_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,2))) +#define TSB_T32A8_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,4))) +#define TSB_T32A8_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRB,20))) +#define TSB_T32A8_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,0))) +#define TSB_T32A8_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,1))) +#define TSB_T32A8_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,2))) +#define TSB_T32A8_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,3))) +#define TSB_T32A8_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,0))) +#define TSB_T32A8_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,1))) +#define TSB_T32A8_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,2))) +#define TSB_T32A8_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,3))) +#define TSB_T32A8_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,0))) +#define TSB_T32A8_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,1))) +#define TSB_T32A8_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,2))) +#define TSB_T32A8_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,0))) +#define TSB_T32A8_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,1))) +#define TSB_T32A8_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,2))) +#define TSB_T32A8_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,4))) +#define TSB_T32A8_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRC,20))) +#define TSB_T32A8_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,0))) +#define TSB_T32A8_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,1))) +#define TSB_T32A8_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,2))) +#define TSB_T32A8_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,3))) +#define TSB_T32A8_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,4))) +#define TSB_T32A8_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,0))) +#define TSB_T32A8_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,1))) +#define TSB_T32A8_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,2))) +#define TSB_T32A8_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,3))) +#define TSB_T32A8_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,4))) +#define TSB_T32A8_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,0))) +#define TSB_T32A8_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,1))) +#define TSB_T32A8_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,2))) +#define TSB_T32A8_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,0))) +#define TSB_T32A8_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,1))) + +#define TSB_T32A9_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,0))) +#define TSB_T32A9_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,1))) +#define TSB_T32A9_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,0))) +#define TSB_T32A9_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,1))) +#define TSB_T32A9_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,2))) +#define TSB_T32A9_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,4))) +#define TSB_T32A9_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRA,20))) +#define TSB_T32A9_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,0))) +#define TSB_T32A9_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,1))) +#define TSB_T32A9_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,2))) +#define TSB_T32A9_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,3))) +#define TSB_T32A9_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,0))) +#define TSB_T32A9_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,1))) +#define TSB_T32A9_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,2))) +#define TSB_T32A9_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,3))) +#define TSB_T32A9_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,0))) +#define TSB_T32A9_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,1))) +#define TSB_T32A9_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,2))) +#define TSB_T32A9_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,0))) +#define TSB_T32A9_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,1))) +#define TSB_T32A9_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,2))) +#define TSB_T32A9_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,4))) +#define TSB_T32A9_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRB,20))) +#define TSB_T32A9_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,0))) +#define TSB_T32A9_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,1))) +#define TSB_T32A9_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,2))) +#define TSB_T32A9_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,3))) +#define TSB_T32A9_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,0))) +#define TSB_T32A9_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,1))) +#define TSB_T32A9_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,2))) +#define TSB_T32A9_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,3))) +#define TSB_T32A9_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,0))) +#define TSB_T32A9_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,1))) +#define TSB_T32A9_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,2))) +#define TSB_T32A9_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,0))) +#define TSB_T32A9_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,1))) +#define TSB_T32A9_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,2))) +#define TSB_T32A9_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,4))) +#define TSB_T32A9_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRC,20))) +#define TSB_T32A9_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,0))) +#define TSB_T32A9_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,1))) +#define TSB_T32A9_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,2))) +#define TSB_T32A9_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,3))) +#define TSB_T32A9_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,4))) +#define TSB_T32A9_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,0))) +#define TSB_T32A9_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,1))) +#define TSB_T32A9_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,2))) +#define TSB_T32A9_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,3))) +#define TSB_T32A9_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,4))) +#define TSB_T32A9_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,0))) +#define TSB_T32A9_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,1))) +#define TSB_T32A9_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,2))) +#define TSB_T32A9_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,0))) +#define TSB_T32A9_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,1))) + +#define TSB_T32A10_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,0))) +#define TSB_T32A10_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,1))) +#define TSB_T32A10_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,0))) +#define TSB_T32A10_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,1))) +#define TSB_T32A10_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,2))) +#define TSB_T32A10_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,4))) +#define TSB_T32A10_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRA,20))) +#define TSB_T32A10_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,0))) +#define TSB_T32A10_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,1))) +#define TSB_T32A10_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,2))) +#define TSB_T32A10_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,3))) +#define TSB_T32A10_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,0))) +#define TSB_T32A10_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,1))) +#define TSB_T32A10_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,2))) +#define TSB_T32A10_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,3))) +#define TSB_T32A10_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,0))) +#define TSB_T32A10_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,1))) +#define TSB_T32A10_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,2))) +#define TSB_T32A10_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,0))) +#define TSB_T32A10_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,1))) +#define TSB_T32A10_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,2))) +#define TSB_T32A10_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,4))) +#define TSB_T32A10_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRB,20))) +#define TSB_T32A10_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,0))) +#define TSB_T32A10_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,1))) +#define TSB_T32A10_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,2))) +#define TSB_T32A10_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,3))) +#define TSB_T32A10_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,0))) +#define TSB_T32A10_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,1))) +#define TSB_T32A10_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,2))) +#define TSB_T32A10_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,3))) +#define TSB_T32A10_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,0))) +#define TSB_T32A10_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,1))) +#define TSB_T32A10_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,2))) +#define TSB_T32A10_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,0))) +#define TSB_T32A10_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,1))) +#define TSB_T32A10_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,2))) +#define TSB_T32A10_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,4))) +#define TSB_T32A10_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRC,20))) +#define TSB_T32A10_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,0))) +#define TSB_T32A10_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,1))) +#define TSB_T32A10_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,2))) +#define TSB_T32A10_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,3))) +#define TSB_T32A10_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,4))) +#define TSB_T32A10_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,0))) +#define TSB_T32A10_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,1))) +#define TSB_T32A10_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,2))) +#define TSB_T32A10_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,3))) +#define TSB_T32A10_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,4))) +#define TSB_T32A10_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,0))) +#define TSB_T32A10_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,1))) +#define TSB_T32A10_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,2))) +#define TSB_T32A10_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,0))) +#define TSB_T32A10_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,1))) + +#define TSB_T32A11_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,0))) +#define TSB_T32A11_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,1))) +#define TSB_T32A11_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,0))) +#define TSB_T32A11_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,1))) +#define TSB_T32A11_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,2))) +#define TSB_T32A11_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,4))) +#define TSB_T32A11_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRA,20))) +#define TSB_T32A11_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,0))) +#define TSB_T32A11_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,1))) +#define TSB_T32A11_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,2))) +#define TSB_T32A11_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,3))) +#define TSB_T32A11_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,0))) +#define TSB_T32A11_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,1))) +#define TSB_T32A11_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,2))) +#define TSB_T32A11_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,3))) +#define TSB_T32A11_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,0))) +#define TSB_T32A11_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,1))) +#define TSB_T32A11_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,2))) +#define TSB_T32A11_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,0))) +#define TSB_T32A11_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,1))) +#define TSB_T32A11_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,2))) +#define TSB_T32A11_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,4))) +#define TSB_T32A11_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRB,20))) +#define TSB_T32A11_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,0))) +#define TSB_T32A11_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,1))) +#define TSB_T32A11_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,2))) +#define TSB_T32A11_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,3))) +#define TSB_T32A11_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,0))) +#define TSB_T32A11_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,1))) +#define TSB_T32A11_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,2))) +#define TSB_T32A11_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,3))) +#define TSB_T32A11_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,0))) +#define TSB_T32A11_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,1))) +#define TSB_T32A11_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,2))) +#define TSB_T32A11_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,0))) +#define TSB_T32A11_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,1))) +#define TSB_T32A11_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,2))) +#define TSB_T32A11_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,4))) +#define TSB_T32A11_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRC,20))) +#define TSB_T32A11_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,0))) +#define TSB_T32A11_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,1))) +#define TSB_T32A11_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,2))) +#define TSB_T32A11_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,3))) +#define TSB_T32A11_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,4))) +#define TSB_T32A11_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,0))) +#define TSB_T32A11_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,1))) +#define TSB_T32A11_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,2))) +#define TSB_T32A11_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,3))) +#define TSB_T32A11_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,4))) +#define TSB_T32A11_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,0))) +#define TSB_T32A11_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,1))) +#define TSB_T32A11_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,2))) +#define TSB_T32A11_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,0))) +#define TSB_T32A11_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,1))) + +#define TSB_T32A12_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,0))) +#define TSB_T32A12_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,1))) +#define TSB_T32A12_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,0))) +#define TSB_T32A12_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,1))) +#define TSB_T32A12_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,2))) +#define TSB_T32A12_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,4))) +#define TSB_T32A12_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRA,20))) +#define TSB_T32A12_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,0))) +#define TSB_T32A12_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,1))) +#define TSB_T32A12_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,2))) +#define TSB_T32A12_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,3))) +#define TSB_T32A12_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,0))) +#define TSB_T32A12_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,1))) +#define TSB_T32A12_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,2))) +#define TSB_T32A12_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,3))) +#define TSB_T32A12_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,0))) +#define TSB_T32A12_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,1))) +#define TSB_T32A12_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,2))) +#define TSB_T32A12_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,0))) +#define TSB_T32A12_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,1))) +#define TSB_T32A12_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,2))) +#define TSB_T32A12_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,4))) +#define TSB_T32A12_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRB,20))) +#define TSB_T32A12_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,0))) +#define TSB_T32A12_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,1))) +#define TSB_T32A12_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,2))) +#define TSB_T32A12_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,3))) +#define TSB_T32A12_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,0))) +#define TSB_T32A12_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,1))) +#define TSB_T32A12_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,2))) +#define TSB_T32A12_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,3))) +#define TSB_T32A12_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,0))) +#define TSB_T32A12_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,1))) +#define TSB_T32A12_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,2))) +#define TSB_T32A12_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,0))) +#define TSB_T32A12_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,1))) +#define TSB_T32A12_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,2))) +#define TSB_T32A12_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,4))) +#define TSB_T32A12_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRC,20))) +#define TSB_T32A12_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,0))) +#define TSB_T32A12_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,1))) +#define TSB_T32A12_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,2))) +#define TSB_T32A12_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,3))) +#define TSB_T32A12_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,4))) +#define TSB_T32A12_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,0))) +#define TSB_T32A12_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,1))) +#define TSB_T32A12_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,2))) +#define TSB_T32A12_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,3))) +#define TSB_T32A12_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,4))) +#define TSB_T32A12_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,0))) +#define TSB_T32A12_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,1))) +#define TSB_T32A12_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,2))) +#define TSB_T32A12_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,0))) +#define TSB_T32A12_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,1))) + +#define TSB_T32A13_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,0))) +#define TSB_T32A13_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,1))) +#define TSB_T32A13_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,0))) +#define TSB_T32A13_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,1))) +#define TSB_T32A13_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,2))) +#define TSB_T32A13_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,4))) +#define TSB_T32A13_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRA,20))) +#define TSB_T32A13_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,0))) +#define TSB_T32A13_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,1))) +#define TSB_T32A13_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,2))) +#define TSB_T32A13_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,3))) +#define TSB_T32A13_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,0))) +#define TSB_T32A13_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,1))) +#define TSB_T32A13_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,2))) +#define TSB_T32A13_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,3))) +#define TSB_T32A13_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,0))) +#define TSB_T32A13_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,1))) +#define TSB_T32A13_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,2))) +#define TSB_T32A13_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,0))) +#define TSB_T32A13_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,1))) +#define TSB_T32A13_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,2))) +#define TSB_T32A13_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,4))) +#define TSB_T32A13_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRB,20))) +#define TSB_T32A13_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,0))) +#define TSB_T32A13_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,1))) +#define TSB_T32A13_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,2))) +#define TSB_T32A13_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,3))) +#define TSB_T32A13_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,0))) +#define TSB_T32A13_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,1))) +#define TSB_T32A13_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,2))) +#define TSB_T32A13_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,3))) +#define TSB_T32A13_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,0))) +#define TSB_T32A13_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,1))) +#define TSB_T32A13_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,2))) +#define TSB_T32A13_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,0))) +#define TSB_T32A13_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,1))) +#define TSB_T32A13_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,2))) +#define TSB_T32A13_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,4))) +#define TSB_T32A13_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRC,20))) +#define TSB_T32A13_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,0))) +#define TSB_T32A13_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,1))) +#define TSB_T32A13_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,2))) +#define TSB_T32A13_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,3))) +#define TSB_T32A13_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,4))) +#define TSB_T32A13_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,0))) +#define TSB_T32A13_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,1))) +#define TSB_T32A13_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,2))) +#define TSB_T32A13_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,3))) +#define TSB_T32A13_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,4))) +#define TSB_T32A13_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,0))) +#define TSB_T32A13_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,1))) +#define TSB_T32A13_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,2))) +#define TSB_T32A13_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,0))) +#define TSB_T32A13_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,1))) + +#define TSB_T32A14_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->MOD,0))) +#define TSB_T32A14_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->MOD,1))) +#define TSB_T32A14_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,0))) +#define TSB_T32A14_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,1))) +#define TSB_T32A14_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,2))) +#define TSB_T32A14_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,4))) +#define TSB_T32A14_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRA,20))) +#define TSB_T32A14_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,0))) +#define TSB_T32A14_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,1))) +#define TSB_T32A14_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,2))) +#define TSB_T32A14_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,3))) +#define TSB_T32A14_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,0))) +#define TSB_T32A14_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,1))) +#define TSB_T32A14_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,2))) +#define TSB_T32A14_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,3))) +#define TSB_T32A14_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,0))) +#define TSB_T32A14_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,1))) +#define TSB_T32A14_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,2))) +#define TSB_T32A14_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,0))) +#define TSB_T32A14_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,1))) +#define TSB_T32A14_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,2))) +#define TSB_T32A14_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,4))) +#define TSB_T32A14_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRB,20))) +#define TSB_T32A14_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,0))) +#define TSB_T32A14_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,1))) +#define TSB_T32A14_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,2))) +#define TSB_T32A14_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,3))) +#define TSB_T32A14_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,0))) +#define TSB_T32A14_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,1))) +#define TSB_T32A14_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,2))) +#define TSB_T32A14_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,3))) +#define TSB_T32A14_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,0))) +#define TSB_T32A14_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,1))) +#define TSB_T32A14_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,2))) +#define TSB_T32A14_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,0))) +#define TSB_T32A14_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,1))) +#define TSB_T32A14_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,2))) +#define TSB_T32A14_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,4))) +#define TSB_T32A14_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRC,20))) +#define TSB_T32A14_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,0))) +#define TSB_T32A14_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,1))) +#define TSB_T32A14_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,2))) +#define TSB_T32A14_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,3))) +#define TSB_T32A14_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,4))) +#define TSB_T32A14_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,0))) +#define TSB_T32A14_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,1))) +#define TSB_T32A14_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,2))) +#define TSB_T32A14_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,3))) +#define TSB_T32A14_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,4))) +#define TSB_T32A14_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,0))) +#define TSB_T32A14_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,1))) +#define TSB_T32A14_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,2))) +#define TSB_T32A14_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->PLSCR,0))) +#define TSB_T32A14_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->PLSCR,1))) + +#define TSB_T32A15_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->MOD,0))) +#define TSB_T32A15_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->MOD,1))) +#define TSB_T32A15_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,0))) +#define TSB_T32A15_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,1))) +#define TSB_T32A15_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,2))) +#define TSB_T32A15_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,4))) +#define TSB_T32A15_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRA,20))) +#define TSB_T32A15_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,0))) +#define TSB_T32A15_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,1))) +#define TSB_T32A15_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,2))) +#define TSB_T32A15_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,3))) +#define TSB_T32A15_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,0))) +#define TSB_T32A15_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,1))) +#define TSB_T32A15_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,2))) +#define TSB_T32A15_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,3))) +#define TSB_T32A15_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,0))) +#define TSB_T32A15_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,1))) +#define TSB_T32A15_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,2))) +#define TSB_T32A15_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,0))) +#define TSB_T32A15_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,1))) +#define TSB_T32A15_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,2))) +#define TSB_T32A15_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,4))) +#define TSB_T32A15_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRB,20))) +#define TSB_T32A15_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,0))) +#define TSB_T32A15_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,1))) +#define TSB_T32A15_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,2))) +#define TSB_T32A15_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,3))) +#define TSB_T32A15_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,0))) +#define TSB_T32A15_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,1))) +#define TSB_T32A15_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,2))) +#define TSB_T32A15_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,3))) +#define TSB_T32A15_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,0))) +#define TSB_T32A15_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,1))) +#define TSB_T32A15_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,2))) +#define TSB_T32A15_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,0))) +#define TSB_T32A15_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,1))) +#define TSB_T32A15_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,2))) +#define TSB_T32A15_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,4))) +#define TSB_T32A15_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRC,20))) +#define TSB_T32A15_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,0))) +#define TSB_T32A15_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,1))) +#define TSB_T32A15_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,2))) +#define TSB_T32A15_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,3))) +#define TSB_T32A15_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,4))) +#define TSB_T32A15_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,0))) +#define TSB_T32A15_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,1))) +#define TSB_T32A15_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,2))) +#define TSB_T32A15_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,3))) +#define TSB_T32A15_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,4))) +#define TSB_T32A15_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,0))) +#define TSB_T32A15_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,1))) +#define TSB_T32A15_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,2))) +#define TSB_T32A15_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->PLSCR,0))) +#define TSB_T32A15_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->PLSCR,1))) + + +/* TSSI */ +#define TSB_TSSI0_CR0_RXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,6))) +#define TSB_TSSI0_CR0_RXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,7))) +#define TSB_TSSI0_CR0_TXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,14))) +#define TSB_TSSI0_CR0_TXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,15))) +#define TSB_TSSI0_CR0_SWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,31))) +#define TSB_TSSI0_CR1_RXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR1,2))) +#define TSB_TSSI0_CR1_TXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR1,10))) +#define TSB_TSSI0_RDMACR_RDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RDMACR,0))) +#define TSB_TSSI0_RSR_RBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,0))) +#define TSB_TSSI0_RSR_RFNE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,1))) +#define TSB_TSSI0_RSR_RFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,2))) +#define TSB_TSSI0_RSR_RFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,4))) +#define TSB_TSSI0_RSR_RFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,5))) +#define TSB_TSSI0_RIER_RFNEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,1))) +#define TSB_TSSI0_RIER_RFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,2))) +#define TSB_TSSI0_RIER_RCMIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,3))) +#define TSB_TSSI0_RIER_RFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,4))) +#define TSB_TSSI0_RIER_RFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,5))) +#define TSB_TSSI0_RIER_RFTEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,7))) +#define TSB_TSSI0_TDMACR_TDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TDMACR,0))) +#define TSB_TSSI0_TSR_TBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,0))) +#define TSB_TSSI0_TSR_TFNF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,1))) +#define TSB_TSSI0_TSR_TFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,2))) +#define TSB_TSSI0_TSR_TFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,4))) +#define TSB_TSSI0_TSR_TFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,5))) +#define TSB_TSSI0_TIER_TFNFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,1))) +#define TSB_TSSI0_TIER_TFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,2))) +#define TSB_TSSI0_TIER_TFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,4))) +#define TSB_TSSI0_TIER_TFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,5))) + +#define TSB_TSSI1_CR0_RXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,6))) +#define TSB_TSSI1_CR0_RXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,7))) +#define TSB_TSSI1_CR0_TXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,14))) +#define TSB_TSSI1_CR0_TXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,15))) +#define TSB_TSSI1_CR0_SWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,31))) +#define TSB_TSSI1_CR1_RXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR1,2))) +#define TSB_TSSI1_CR1_TXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR1,10))) +#define TSB_TSSI1_RDMACR_RDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RDMACR,0))) +#define TSB_TSSI1_RSR_RBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,0))) +#define TSB_TSSI1_RSR_RFNE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,1))) +#define TSB_TSSI1_RSR_RFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,2))) +#define TSB_TSSI1_RSR_RFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,4))) +#define TSB_TSSI1_RSR_RFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,5))) +#define TSB_TSSI1_RIER_RFNEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,1))) +#define TSB_TSSI1_RIER_RFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,2))) +#define TSB_TSSI1_RIER_RCMIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,3))) +#define TSB_TSSI1_RIER_RFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,4))) +#define TSB_TSSI1_RIER_RFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,5))) +#define TSB_TSSI1_RIER_RFTEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,7))) +#define TSB_TSSI1_TDMACR_TDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TDMACR,0))) +#define TSB_TSSI1_TSR_TBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,0))) +#define TSB_TSSI1_TSR_TFNF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,1))) +#define TSB_TSSI1_TSR_TFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,2))) +#define TSB_TSSI1_TSR_TFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,4))) +#define TSB_TSSI1_TSR_TFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,5))) +#define TSB_TSSI1_TIER_TFNFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,1))) +#define TSB_TSSI1_TIER_TFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,2))) +#define TSB_TSSI1_TIER_TFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,4))) +#define TSB_TSSI1_TIER_TFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,5))) + + +/* UART */ +#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) +#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) +#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) +#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) +#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) +#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) +#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) +#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) +#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) +#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) +#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) +#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) +#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) +#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) +#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) +#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) +#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) +#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) +#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) +#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) +#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) +#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) +#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) +#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) +#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) +#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) +#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) +#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) +#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) +#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) +#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) +#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) +#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) +#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) +#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) +#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) +#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) +#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) +#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) +#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) +#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) +#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) + +#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) +#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) +#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) +#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) +#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) +#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) +#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) +#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) +#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) +#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) +#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) +#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) +#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) +#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) +#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) +#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) +#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) +#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) +#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) +#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) +#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) +#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) +#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) +#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) +#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) +#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) +#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) +#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) +#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) +#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) +#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) +#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) +#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) +#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) +#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) +#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) +#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) +#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) +#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) +#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) +#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) +#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) + +#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) +#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) +#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) +#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) +#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) +#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) +#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) +#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) +#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) +#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) +#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) +#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) +#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) +#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) +#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) +#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) +#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) +#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) +#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) +#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) +#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) +#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) +#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) +#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) +#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) +#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) +#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) +#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) +#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) +#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) +#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) +#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) +#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) +#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) +#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) +#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) +#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) +#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) +#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) +#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) +#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) +#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) + +#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) +#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) +#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) +#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) +#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) +#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) +#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) +#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) +#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) +#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) +#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) +#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) +#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) +#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) +#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) +#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) +#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) +#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) +#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) +#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) +#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) +#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) +#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) +#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) +#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) +#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) +#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) +#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) +#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) +#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) +#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) +#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) +#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) +#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) +#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) +#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) +#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) +#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) +#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) +#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) +#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) +#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) + +#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) +#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) +#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) +#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) +#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) +#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) +#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) +#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) +#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) +#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) +#define TSB_UART4_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,16))) +#define TSB_UART4_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,17))) +#define TSB_UART4_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,18))) +#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) +#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) +#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) +#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) +#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) +#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) +#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) +#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) +#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) +#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) +#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) +#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) +#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) +#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) +#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) +#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) +#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) +#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) +#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) +#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) +#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) +#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) +#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) +#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) +#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) +#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) +#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) +#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) +#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) + +#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) +#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) +#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) +#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) +#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) +#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) +#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) +#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) +#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) +#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) +#define TSB_UART5_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,16))) +#define TSB_UART5_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,17))) +#define TSB_UART5_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,18))) +#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) +#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) +#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) +#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) +#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) +#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) +#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) +#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) +#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) +#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) +#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) +#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) +#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) +#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) +#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) +#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) +#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) +#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) +#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) +#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) +#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) +#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) +#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) +#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) +#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) +#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) +#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) +#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) +#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) + + +/* I2S interface */ +#define TSB_I2S0_CSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CSTART,8))) +#define TSB_I2S0_CBUSY_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CBUSY,8))) +#define TSB_I2S0_CSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CSTOP,0))) +#define TSB_I2S0_CAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CAUDIOSET,8))) +#define TSB_I2S0_CAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CAUDIOSET,11))) +#define TSB_I2S0_CREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,0))) +#define TSB_I2S0_CREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,3))) +#define TSB_I2S0_CREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,16))) +#define TSB_I2S0_CREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,19))) +#define TSB_I2S0_CMS_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CMS_SEL,0))) +#define TSB_I2S0_CMCLK_IO_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CMCLK_IO_SEL,0))) +#define TSB_I2S0_CPHT_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CPHT_DIVOUT_EN,0))) +#define TSB_I2S0_CBCK_SRC_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CBCK_SRC_SEL,0))) +#define TSB_I2S0_CBCK_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CBCK_DIVOUT_EN,0))) +#define TSB_I2S0_ISTART_MICSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTART,0))) +#define TSB_I2S0_ISTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTART,8))) +#define TSB_I2S0_IBUSY_MICBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,0))) +#define TSB_I2S0_IBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,1))) +#define TSB_I2S0_IBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,16))) +#define TSB_I2S0_IBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,17))) +#define TSB_I2S0_ISTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTOP,0))) +#define TSB_I2S0_IAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,8))) +#define TSB_I2S0_IAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,11))) +#define TSB_I2S0_IAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,12))) +#define TSB_I2S0_IAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,16))) +#define TSB_I2S0_IINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,0))) +#define TSB_I2S0_IINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,1))) +#define TSB_I2S0_IINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,2))) +#define TSB_I2S0_IINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,3))) +#define TSB_I2S0_IINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,0))) +#define TSB_I2S0_IINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,1))) +#define TSB_I2S0_IINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,2))) +#define TSB_I2S0_IINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,3))) +#define TSB_I2S0_IINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,16))) +#define TSB_I2S0_IINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,0))) +#define TSB_I2S0_IINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,1))) +#define TSB_I2S0_IINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,2))) +#define TSB_I2S0_IINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,3))) +#define TSB_I2S0_IMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IMUTE,0))) +#define TSB_I2S0_IREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,0))) +#define TSB_I2S0_IREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,1))) +#define TSB_I2S0_IREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,3))) +#define TSB_I2S0_IREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,16))) +#define TSB_I2S0_IREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,17))) +#define TSB_I2S0_IREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,19))) +#define TSB_I2S0_OSTART_SPKSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTART,0))) +#define TSB_I2S0_OSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTART,8))) +#define TSB_I2S0_OBUSY_SPKBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,0))) +#define TSB_I2S0_OBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,1))) +#define TSB_I2S0_OBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,16))) +#define TSB_I2S0_OBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,17))) +#define TSB_I2S0_OSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTOP,0))) +#define TSB_I2S0_OAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,8))) +#define TSB_I2S0_OAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,11))) +#define TSB_I2S0_OAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,12))) +#define TSB_I2S0_OAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,16))) +#define TSB_I2S0_OINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,0))) +#define TSB_I2S0_OINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,1))) +#define TSB_I2S0_OINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,2))) +#define TSB_I2S0_OINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,3))) +#define TSB_I2S0_OINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,0))) +#define TSB_I2S0_OINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,1))) +#define TSB_I2S0_OINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,2))) +#define TSB_I2S0_OINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,3))) +#define TSB_I2S0_OINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,16))) +#define TSB_I2S0_OINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,0))) +#define TSB_I2S0_OINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,1))) +#define TSB_I2S0_OINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,2))) +#define TSB_I2S0_OINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,3))) +#define TSB_I2S0_OMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OMUTE,0))) +#define TSB_I2S0_OREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,0))) +#define TSB_I2S0_OREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,1))) +#define TSB_I2S0_OREGBUSY_TXSSIZEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,2))) +#define TSB_I2S0_OREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,3))) +#define TSB_I2S0_OREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,16))) +#define TSB_I2S0_OREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,17))) +#define TSB_I2S0_OREGBUSY_TXSSIZEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,18))) +#define TSB_I2S0_OREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,19))) + +#define TSB_I2S1_CSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CSTART,8))) +#define TSB_I2S1_CBUSY_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CBUSY,8))) +#define TSB_I2S1_CSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CSTOP,0))) +#define TSB_I2S1_CAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CAUDIOSET,8))) +#define TSB_I2S1_CAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CAUDIOSET,11))) +#define TSB_I2S1_CREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,0))) +#define TSB_I2S1_CREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,3))) +#define TSB_I2S1_CREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,16))) +#define TSB_I2S1_CREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,19))) +#define TSB_I2S1_CMS_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CMS_SEL,0))) +#define TSB_I2S1_CMCLK_IO_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CMCLK_IO_SEL,0))) +#define TSB_I2S1_CPHT_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CPHT_DIVOUT_EN,0))) +#define TSB_I2S1_CBCK_SRC_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CBCK_SRC_SEL,0))) +#define TSB_I2S1_CBCK_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CBCK_DIVOUT_EN,0))) +#define TSB_I2S1_ISTART_MICSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTART,0))) +#define TSB_I2S1_ISTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTART,8))) +#define TSB_I2S1_IBUSY_MICBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,0))) +#define TSB_I2S1_IBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,1))) +#define TSB_I2S1_IBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,16))) +#define TSB_I2S1_IBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,17))) +#define TSB_I2S1_ISTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTOP,0))) +#define TSB_I2S1_IAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,8))) +#define TSB_I2S1_IAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,11))) +#define TSB_I2S1_IAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,12))) +#define TSB_I2S1_IAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,16))) +#define TSB_I2S1_IINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,0))) +#define TSB_I2S1_IINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,1))) +#define TSB_I2S1_IINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,2))) +#define TSB_I2S1_IINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,3))) +#define TSB_I2S1_IINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,0))) +#define TSB_I2S1_IINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,1))) +#define TSB_I2S1_IINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,2))) +#define TSB_I2S1_IINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,3))) +#define TSB_I2S1_IINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,16))) +#define TSB_I2S1_IINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,0))) +#define TSB_I2S1_IINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,1))) +#define TSB_I2S1_IINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,2))) +#define TSB_I2S1_IINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,3))) +#define TSB_I2S1_IMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IMUTE,0))) +#define TSB_I2S1_IREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,0))) +#define TSB_I2S1_IREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,1))) +#define TSB_I2S1_IREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,3))) +#define TSB_I2S1_IREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,16))) +#define TSB_I2S1_IREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,17))) +#define TSB_I2S1_IREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,19))) +#define TSB_I2S1_OSTART_SPKSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTART,0))) +#define TSB_I2S1_OSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTART,8))) +#define TSB_I2S1_OBUSY_SPKBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,0))) +#define TSB_I2S1_OBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,1))) +#define TSB_I2S1_OBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,16))) +#define TSB_I2S1_OBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,17))) +#define TSB_I2S1_OSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTOP,0))) +#define TSB_I2S1_OAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,8))) +#define TSB_I2S1_OAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,11))) +#define TSB_I2S1_OAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,12))) +#define TSB_I2S1_OAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,16))) +#define TSB_I2S1_OINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,0))) +#define TSB_I2S1_OINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,1))) +#define TSB_I2S1_OINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,2))) +#define TSB_I2S1_OINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,3))) +#define TSB_I2S1_OINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,0))) +#define TSB_I2S1_OINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,1))) +#define TSB_I2S1_OINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,2))) +#define TSB_I2S1_OINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,3))) +#define TSB_I2S1_OINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,16))) +#define TSB_I2S1_OINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,0))) +#define TSB_I2S1_OINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,1))) +#define TSB_I2S1_OINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,2))) +#define TSB_I2S1_OINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,3))) +#define TSB_I2S1_OMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OMUTE,0))) +#define TSB_I2S1_OREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,0))) +#define TSB_I2S1_OREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,1))) +#define TSB_I2S1_OREGBUSY_TXSSIZEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,2))) +#define TSB_I2S1_OREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,3))) +#define TSB_I2S1_OREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,16))) +#define TSB_I2S1_OREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,17))) +#define TSB_I2S1_OREGBUSY_TXSSIZEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,18))) +#define TSB_I2S1_OREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,19))) + + +/* I2C */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + +#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) +#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) +#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) +#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) +#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) +#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) +#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) +#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) +#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) +#define TSB_I2C2_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) +#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) +#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) +#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) +#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) +#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) +#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) +#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) +#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) +#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) +#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) +#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) +#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) +#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) +#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) +#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) +#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) +#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) +#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) +#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) +#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) +#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) +#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) +#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) +#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) +#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) +#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) +#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) +#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) + +#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) +#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) +#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) +#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) +#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) +#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) +#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) +#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) +#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) +#define TSB_I2C3_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) +#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) +#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) +#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) +#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) +#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) +#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) +#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) +#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) +#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) +#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) +#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) +#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) +#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) +#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) +#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) +#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) +#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) +#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) +#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) +#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) +#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) +#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) +#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) +#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) +#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) +#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) +#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) +#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) + +#define TSB_I2C4_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,3))) +#define TSB_I2C4_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,4))) +#define TSB_I2C4_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR,0))) +#define TSB_I2C4_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,3))) +#define TSB_I2C4_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,4))) +#define TSB_I2C4_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,5))) +#define TSB_I2C4_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,6))) +#define TSB_I2C4_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,7))) +#define TSB_I2C4_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,0))) +#define TSB_I2C4_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,1))) +#define TSB_I2C4_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,2))) +#define TSB_I2C4_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,3))) +#define TSB_I2C4_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,4))) +#define TSB_I2C4_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,5))) +#define TSB_I2C4_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,6))) +#define TSB_I2C4_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,7))) +#define TSB_I2C4_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,0))) +#define TSB_I2C4_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,1))) +#define TSB_I2C4_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,2))) +#define TSB_I2C4_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,3))) +#define TSB_I2C4_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,4))) +#define TSB_I2C4_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,5))) +#define TSB_I2C4_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,6))) +#define TSB_I2C4_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,0))) +#define TSB_I2C4_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,1))) +#define TSB_I2C4_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,2))) +#define TSB_I2C4_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,3))) +#define TSB_I2C4_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,0))) +#define TSB_I2C4_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,1))) +#define TSB_I2C4_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,2))) +#define TSB_I2C4_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,3))) +#define TSB_I2C4_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,4))) +#define TSB_I2C4_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,5))) +#define TSB_I2C4_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,6))) +#define TSB_I2C4_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,7))) +#define TSB_I2C4_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,0))) +#define TSB_I2C4_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,1))) +#define TSB_I2C4_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR2,0))) + + +/* EI2C */ +#define TSB_EI2C0_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AEN,0))) +#define TSB_EI2C0_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,0))) +#define TSB_EI2C0_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,1))) +#define TSB_EI2C0_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,2))) +#define TSB_EI2C0_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,3))) +#define TSB_EI2C0_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,4))) +#define TSB_EI2C0_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,8))) +#define TSB_EI2C0_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,11))) +#define TSB_EI2C0_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,0))) +#define TSB_EI2C0_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,1))) +#define TSB_EI2C0_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,2))) +#define TSB_EI2C0_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,3))) +#define TSB_EI2C0_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,4))) +#define TSB_EI2C0_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,10))) +#define TSB_EI2C0_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,0))) +#define TSB_EI2C0_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,1))) +#define TSB_EI2C0_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,2))) +#define TSB_EI2C0_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,3))) +#define TSB_EI2C0_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,0))) +#define TSB_EI2C0_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,1))) +#define TSB_EI2C0_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,2))) +#define TSB_EI2C0_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,3))) +#define TSB_EI2C0_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,4))) +#define TSB_EI2C0_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,5))) +#define TSB_EI2C0_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,6))) +#define TSB_EI2C0_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,7))) +#define TSB_EI2C0_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,8))) +#define TSB_EI2C0_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,9))) +#define TSB_EI2C0_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,10))) +#define TSB_EI2C0_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,11))) +#define TSB_EI2C0_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,12))) +#define TSB_EI2C0_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,13))) +#define TSB_EI2C0_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,0))) +#define TSB_EI2C0_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,15))) +#define TSB_EI2C0_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,0))) +#define TSB_EI2C0_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,15))) +#define TSB_EI2C0_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,0))) +#define TSB_EI2C0_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,1))) +#define TSB_EI2C0_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,2))) +#define TSB_EI2C0_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,6))) +#define TSB_EI2C0_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,7))) +#define TSB_EI2C0_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,8))) +#define TSB_EI2C0_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,9))) +#define TSB_EI2C0_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,11))) +#define TSB_EI2C0_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,12))) +#define TSB_EI2C0_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,13))) +#define TSB_EI2C0_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,14))) +#define TSB_EI2C0_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,15))) +#define TSB_EI2C0_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,0))) +#define TSB_EI2C0_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,1))) +#define TSB_EI2C0_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,2))) +#define TSB_EI2C0_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,3))) + +#define TSB_EI2C1_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AEN,0))) +#define TSB_EI2C1_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,0))) +#define TSB_EI2C1_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,1))) +#define TSB_EI2C1_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,2))) +#define TSB_EI2C1_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,3))) +#define TSB_EI2C1_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,4))) +#define TSB_EI2C1_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,8))) +#define TSB_EI2C1_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,11))) +#define TSB_EI2C1_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,0))) +#define TSB_EI2C1_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,1))) +#define TSB_EI2C1_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,2))) +#define TSB_EI2C1_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,3))) +#define TSB_EI2C1_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,4))) +#define TSB_EI2C1_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,10))) +#define TSB_EI2C1_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,0))) +#define TSB_EI2C1_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,1))) +#define TSB_EI2C1_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,2))) +#define TSB_EI2C1_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,3))) +#define TSB_EI2C1_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,0))) +#define TSB_EI2C1_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,1))) +#define TSB_EI2C1_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,2))) +#define TSB_EI2C1_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,3))) +#define TSB_EI2C1_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,4))) +#define TSB_EI2C1_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,5))) +#define TSB_EI2C1_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,6))) +#define TSB_EI2C1_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,7))) +#define TSB_EI2C1_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,8))) +#define TSB_EI2C1_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,9))) +#define TSB_EI2C1_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,10))) +#define TSB_EI2C1_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,11))) +#define TSB_EI2C1_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,12))) +#define TSB_EI2C1_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,13))) +#define TSB_EI2C1_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,0))) +#define TSB_EI2C1_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,15))) +#define TSB_EI2C1_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,0))) +#define TSB_EI2C1_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,15))) +#define TSB_EI2C1_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,0))) +#define TSB_EI2C1_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,1))) +#define TSB_EI2C1_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,2))) +#define TSB_EI2C1_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,6))) +#define TSB_EI2C1_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,7))) +#define TSB_EI2C1_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,8))) +#define TSB_EI2C1_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,9))) +#define TSB_EI2C1_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,11))) +#define TSB_EI2C1_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,12))) +#define TSB_EI2C1_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,13))) +#define TSB_EI2C1_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,14))) +#define TSB_EI2C1_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,15))) +#define TSB_EI2C1_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,0))) +#define TSB_EI2C1_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,1))) +#define TSB_EI2C1_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,2))) +#define TSB_EI2C1_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,3))) + +#define TSB_EI2C2_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AEN,0))) +#define TSB_EI2C2_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,0))) +#define TSB_EI2C2_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,1))) +#define TSB_EI2C2_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,2))) +#define TSB_EI2C2_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,3))) +#define TSB_EI2C2_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,4))) +#define TSB_EI2C2_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,8))) +#define TSB_EI2C2_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,11))) +#define TSB_EI2C2_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,0))) +#define TSB_EI2C2_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,1))) +#define TSB_EI2C2_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,2))) +#define TSB_EI2C2_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,3))) +#define TSB_EI2C2_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,4))) +#define TSB_EI2C2_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,10))) +#define TSB_EI2C2_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,0))) +#define TSB_EI2C2_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,1))) +#define TSB_EI2C2_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,2))) +#define TSB_EI2C2_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,3))) +#define TSB_EI2C2_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,0))) +#define TSB_EI2C2_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,1))) +#define TSB_EI2C2_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,2))) +#define TSB_EI2C2_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,3))) +#define TSB_EI2C2_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,4))) +#define TSB_EI2C2_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,5))) +#define TSB_EI2C2_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,6))) +#define TSB_EI2C2_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,7))) +#define TSB_EI2C2_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,8))) +#define TSB_EI2C2_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,9))) +#define TSB_EI2C2_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,10))) +#define TSB_EI2C2_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,11))) +#define TSB_EI2C2_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,12))) +#define TSB_EI2C2_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,13))) +#define TSB_EI2C2_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR1,0))) +#define TSB_EI2C2_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR1,15))) +#define TSB_EI2C2_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR2,0))) +#define TSB_EI2C2_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR2,15))) +#define TSB_EI2C2_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,0))) +#define TSB_EI2C2_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,1))) +#define TSB_EI2C2_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,2))) +#define TSB_EI2C2_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,6))) +#define TSB_EI2C2_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,7))) +#define TSB_EI2C2_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,8))) +#define TSB_EI2C2_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,9))) +#define TSB_EI2C2_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,11))) +#define TSB_EI2C2_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,12))) +#define TSB_EI2C2_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,13))) +#define TSB_EI2C2_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,14))) +#define TSB_EI2C2_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,15))) +#define TSB_EI2C2_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,0))) +#define TSB_EI2C2_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,1))) +#define TSB_EI2C2_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,2))) +#define TSB_EI2C2_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,3))) + +#define TSB_EI2C3_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AEN,0))) +#define TSB_EI2C3_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,0))) +#define TSB_EI2C3_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,1))) +#define TSB_EI2C3_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,2))) +#define TSB_EI2C3_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,3))) +#define TSB_EI2C3_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,4))) +#define TSB_EI2C3_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,8))) +#define TSB_EI2C3_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,11))) +#define TSB_EI2C3_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,0))) +#define TSB_EI2C3_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,1))) +#define TSB_EI2C3_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,2))) +#define TSB_EI2C3_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,3))) +#define TSB_EI2C3_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,4))) +#define TSB_EI2C3_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,10))) +#define TSB_EI2C3_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,0))) +#define TSB_EI2C3_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,1))) +#define TSB_EI2C3_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,2))) +#define TSB_EI2C3_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,3))) +#define TSB_EI2C3_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,0))) +#define TSB_EI2C3_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,1))) +#define TSB_EI2C3_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,2))) +#define TSB_EI2C3_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,3))) +#define TSB_EI2C3_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,4))) +#define TSB_EI2C3_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,5))) +#define TSB_EI2C3_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,6))) +#define TSB_EI2C3_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,7))) +#define TSB_EI2C3_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,8))) +#define TSB_EI2C3_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,9))) +#define TSB_EI2C3_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,10))) +#define TSB_EI2C3_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,11))) +#define TSB_EI2C3_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,12))) +#define TSB_EI2C3_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,13))) +#define TSB_EI2C3_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR1,0))) +#define TSB_EI2C3_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR1,15))) +#define TSB_EI2C3_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR2,0))) +#define TSB_EI2C3_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR2,15))) +#define TSB_EI2C3_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,0))) +#define TSB_EI2C3_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,1))) +#define TSB_EI2C3_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,2))) +#define TSB_EI2C3_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,6))) +#define TSB_EI2C3_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,7))) +#define TSB_EI2C3_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,8))) +#define TSB_EI2C3_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,9))) +#define TSB_EI2C3_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,11))) +#define TSB_EI2C3_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,12))) +#define TSB_EI2C3_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,13))) +#define TSB_EI2C3_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,14))) +#define TSB_EI2C3_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,15))) +#define TSB_EI2C3_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,0))) +#define TSB_EI2C3_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,1))) +#define TSB_EI2C3_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,2))) +#define TSB_EI2C3_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,3))) + +#define TSB_EI2C4_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AEN,0))) +#define TSB_EI2C4_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,0))) +#define TSB_EI2C4_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,1))) +#define TSB_EI2C4_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,2))) +#define TSB_EI2C4_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,3))) +#define TSB_EI2C4_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,4))) +#define TSB_EI2C4_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,8))) +#define TSB_EI2C4_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,11))) +#define TSB_EI2C4_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,0))) +#define TSB_EI2C4_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,1))) +#define TSB_EI2C4_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,2))) +#define TSB_EI2C4_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,3))) +#define TSB_EI2C4_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,4))) +#define TSB_EI2C4_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,10))) +#define TSB_EI2C4_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,0))) +#define TSB_EI2C4_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,1))) +#define TSB_EI2C4_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,2))) +#define TSB_EI2C4_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,3))) +#define TSB_EI2C4_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,0))) +#define TSB_EI2C4_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,1))) +#define TSB_EI2C4_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,2))) +#define TSB_EI2C4_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,3))) +#define TSB_EI2C4_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,4))) +#define TSB_EI2C4_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,5))) +#define TSB_EI2C4_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,6))) +#define TSB_EI2C4_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,7))) +#define TSB_EI2C4_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,8))) +#define TSB_EI2C4_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,9))) +#define TSB_EI2C4_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,10))) +#define TSB_EI2C4_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,11))) +#define TSB_EI2C4_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,12))) +#define TSB_EI2C4_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,13))) +#define TSB_EI2C4_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR1,0))) +#define TSB_EI2C4_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR1,15))) +#define TSB_EI2C4_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR2,0))) +#define TSB_EI2C4_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR2,15))) +#define TSB_EI2C4_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,0))) +#define TSB_EI2C4_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,1))) +#define TSB_EI2C4_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,2))) +#define TSB_EI2C4_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,6))) +#define TSB_EI2C4_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,7))) +#define TSB_EI2C4_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,8))) +#define TSB_EI2C4_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,9))) +#define TSB_EI2C4_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,11))) +#define TSB_EI2C4_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,12))) +#define TSB_EI2C4_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,13))) +#define TSB_EI2C4_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,14))) +#define TSB_EI2C4_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,15))) +#define TSB_EI2C4_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,0))) +#define TSB_EI2C4_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,1))) +#define TSB_EI2C4_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,2))) +#define TSB_EI2C4_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,3))) + + +/* Finite Impulse Response */ +#define TSB_FIRnore_START_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->START,0))) +#define TSB_FIRnore_CTRL_ODATAFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->CTRL,28))) +#define TSB_FIRnore_INITIALIZE_INITIALIZE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INITIALIZE,0))) +#define TSB_FIRnore_INTEN_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,0))) +#define TSB_FIRnore_INTEN_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,1))) +#define TSB_FIRnore_INTEN_OVERFLOW (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,2))) +#define TSB_FIRnore_DMAEN_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->DMAEN,0))) +#define TSB_FIRnore_DMAEN_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->DMAEN,1))) +#define TSB_FIRnore_RAWINTSTAT_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,0))) +#define TSB_FIRnore_RAWINTSTAT_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,1))) +#define TSB_FIRnore_RAWINTSTAT_OVERFLOW (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,2))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) +#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) +#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) +#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) +#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) +#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) +#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) +#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) +#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3))) +#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) +#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) +#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) +#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) +#define TSB_PA_FR2_PA0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,0))) +#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) +#define TSB_PA_FR2_PA4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,4))) +#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) +#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) +#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) +#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) +#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) +#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) +#define TSB_PA_FR3_PA5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,5))) +#define TSB_PA_FR3_PA6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,6))) +#define TSB_PA_FR3_PA7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,7))) +#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) +#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) +#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3))) +#define TSB_PA_FR5_PA4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,4))) +#define TSB_PA_FR5_PA5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,5))) +#define TSB_PA_FR5_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,7))) +#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) +#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) +#define TSB_PA_FR6_PA4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,4))) +#define TSB_PA_FR6_PA5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,5))) +#define TSB_PA_FR6_PA6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,6))) +#define TSB_PA_FR6_PA7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,7))) +#define TSB_PA_FR7_PA0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,0))) +#define TSB_PA_FR7_PA1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,1))) +#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2))) +#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3))) +#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4))) +#define TSB_PA_FR7_PA5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,5))) +#define TSB_PA_FR7_PA6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,6))) +#define TSB_PA_FR7_PA7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,7))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) +#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) +#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) +#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) +#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) +#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) +#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) +#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) +#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) +#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) +#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) +#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) +#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) +#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) +#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) +#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) +#define TSB_PB_FR1_PB0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,0))) +#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) +#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) +#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) +#define TSB_PB_FR1_PB4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4))) +#define TSB_PB_FR1_PB5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5))) +#define TSB_PB_FR1_PB6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,6))) +#define TSB_PB_FR1_PB7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,7))) +#define TSB_PB_FR2_PB0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,0))) +#define TSB_PB_FR2_PB1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,1))) +#define TSB_PB_FR2_PB6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,6))) +#define TSB_PB_FR2_PB7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,7))) +#define TSB_PB_FR3_PB0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,0))) +#define TSB_PB_FR3_PB1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,1))) +#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) +#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) +#define TSB_PB_FR3_PB4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4))) +#define TSB_PB_FR3_PB5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5))) +#define TSB_PB_FR3_PB6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,6))) +#define TSB_PB_FR3_PB7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,7))) +#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) +#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) +#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) +#define TSB_PB_FR4_PB6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,6))) +#define TSB_PB_FR4_PB7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,7))) +#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) +#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) +#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) +#define TSB_PB_FR5_PB4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,4))) +#define TSB_PB_FR5_PB6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,6))) +#define TSB_PB_FR5_PB7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7))) +#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) +#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) +#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) +#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) +#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) +#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) +#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) +#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) +#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) +#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) +#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) +#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) +#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) +#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) +#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) + + +/* Port C */ +#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) +#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) +#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) +#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) +#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7))) +#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) +#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) +#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) +#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) +#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7))) +#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) +#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) +#define TSB_PC_FR1_PC2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2))) +#define TSB_PC_FR1_PC3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3))) +#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) +#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) +#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) +#define TSB_PC_FR1_PC7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,7))) +#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) +#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) +#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) +#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) +#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) +#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) +#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) +#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) +#define TSB_PC_FR4_PC2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,2))) +#define TSB_PC_FR4_PC3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,3))) +#define TSB_PC_FR5_PC0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,0))) +#define TSB_PC_FR5_PC1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,1))) +#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) +#define TSB_PC_FR5_PC4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,4))) +#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) +#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) +#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) +#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) +#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7))) +#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) +#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) +#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) +#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) +#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7))) +#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) +#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) +#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) +#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) +#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7))) +#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) +#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) +#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) +#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) +#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) +#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) +#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) +#define TSB_PD_DATA_PD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,6))) +#define TSB_PD_DATA_PD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,7))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) +#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) +#define TSB_PD_CR_PD6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,6))) +#define TSB_PD_CR_PD7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,7))) +#define TSB_PD_FR1_PD0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0))) +#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1))) +#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) +#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) +#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4))) +#define TSB_PD_FR1_PD5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,5))) +#define TSB_PD_FR1_PD6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,6))) +#define TSB_PD_FR1_PD7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,7))) +#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0))) +#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1))) +#define TSB_PD_FR2_PD6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,6))) +#define TSB_PD_FR2_PD7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,7))) +#define TSB_PD_FR3_PD0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,0))) +#define TSB_PD_FR3_PD1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,1))) +#define TSB_PD_FR3_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,2))) +#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3))) +#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4))) +#define TSB_PD_FR3_PD5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,5))) +#define TSB_PD_FR3_PD6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,6))) +#define TSB_PD_FR3_PD7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,7))) +#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0))) +#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1))) +#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2))) +#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3))) +#define TSB_PD_FR5_PD0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,0))) +#define TSB_PD_FR5_PD1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,1))) +#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2))) +#define TSB_PD_FR5_PD4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,4))) +#define TSB_PD_FR5_PD6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,6))) +#define TSB_PD_FR5_PD7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,7))) +#define TSB_PD_FR6_PD0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,0))) +#define TSB_PD_FR6_PD4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,4))) +#define TSB_PD_FR6_PD5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,5))) +#define TSB_PD_FR6_PD6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,6))) +#define TSB_PD_FR6_PD7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,7))) +#define TSB_PD_FR7_PD0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,0))) +#define TSB_PD_FR7_PD1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,1))) +#define TSB_PD_FR7_PD2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,2))) +#define TSB_PD_FR7_PD3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,3))) +#define TSB_PD_FR7_PD4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,4))) +#define TSB_PD_FR7_PD5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,5))) +#define TSB_PD_FR7_PD6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,6))) +#define TSB_PD_FR7_PD7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,7))) +#define TSB_PD_FR8_PD2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,2))) +#define TSB_PD_FR8_PD3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,3))) +#define TSB_PD_FR8_PD4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,4))) +#define TSB_PD_FR8_PD5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,5))) +#define TSB_PD_FR8_PD6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,6))) +#define TSB_PD_FR8_PD7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,7))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) +#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) +#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) +#define TSB_PD_OD_PD6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,6))) +#define TSB_PD_OD_PD7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,7))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) +#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) +#define TSB_PD_PUP_PD6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,6))) +#define TSB_PD_PUP_PD7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,7))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) +#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) +#define TSB_PD_PDN_PD6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,6))) +#define TSB_PD_PDN_PD7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,7))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) +#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) +#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) +#define TSB_PD_IE_PD6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,6))) +#define TSB_PD_IE_PD7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,7))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) +#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) +#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7))) +#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0))) +#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1))) +#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2))) +#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3))) +#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4))) +#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5))) +#define TSB_PE_FR1_PE6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,6))) +#define TSB_PE_FR1_PE7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,7))) +#define TSB_PE_FR2_PE0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,0))) +#define TSB_PE_FR2_PE7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,7))) +#define TSB_PE_FR3_PE0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,0))) +#define TSB_PE_FR3_PE1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,1))) +#define TSB_PE_FR3_PE2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,2))) +#define TSB_PE_FR3_PE3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,3))) +#define TSB_PE_FR3_PE4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,4))) +#define TSB_PE_FR3_PE5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,5))) +#define TSB_PE_FR3_PE6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,6))) +#define TSB_PE_FR3_PE7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,7))) +#define TSB_PE_FR4_PE0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,0))) +#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1))) +#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2))) +#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3))) +#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4))) +#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5))) +#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6))) +#define TSB_PE_FR4_PE7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,7))) +#define TSB_PE_FR5_PE0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,0))) +#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1))) +#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2))) +#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3))) +#define TSB_PE_FR5_PE4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,4))) +#define TSB_PE_FR5_PE5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,5))) +#define TSB_PE_FR5_PE6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,6))) +#define TSB_PE_FR5_PE7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,7))) +#define TSB_PE_FR6_PE4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,4))) +#define TSB_PE_FR6_PE5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,5))) +#define TSB_PE_FR6_PE6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,6))) +#define TSB_PE_FR6_PE7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,7))) +#define TSB_PE_FR7_PE0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,0))) +#define TSB_PE_FR7_PE1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,1))) +#define TSB_PE_FR7_PE2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,2))) +#define TSB_PE_FR7_PE3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,3))) +#define TSB_PE_FR8_PE0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,0))) +#define TSB_PE_FR8_PE1F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,1))) +#define TSB_PE_FR8_PE2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,2))) +#define TSB_PE_FR8_PE3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,3))) +#define TSB_PE_FR8_PE4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,4))) +#define TSB_PE_FR8_PE5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,5))) +#define TSB_PE_FR8_PE6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,6))) +#define TSB_PE_FR8_PE7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,7))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) +#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) +#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) +#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) +#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) +#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7))) + + +/* Port F */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) +#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) +#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) +#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) +#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) +#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) +#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) +#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) +#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5))) +#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6))) +#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7))) +#define TSB_PF_FR4_PF7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,7))) +#define TSB_PF_FR5_PF7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,7))) +#define TSB_PF_FR6_PF2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,2))) +#define TSB_PF_FR6_PF3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,3))) +#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2))) +#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) +#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) +#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) +#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) +#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) +#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) +#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) +#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) +#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) +#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) + + +/* Port G */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) +#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) +#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) +#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) +#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) +#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) +#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) +#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) +#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) +#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) +#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) +#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0))) +#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) +#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6))) +#define TSB_PG_FR1_PG7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,7))) +#define TSB_PG_FR2_PG4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,4))) +#define TSB_PG_FR2_PG5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,5))) +#define TSB_PG_FR3_PG0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,0))) +#define TSB_PG_FR3_PG1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,1))) +#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) +#define TSB_PG_FR3_PG3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) +#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) +#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) +#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) +#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) +#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5))) +#define TSB_PG_FR4_PG6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,6))) +#define TSB_PG_FR4_PG7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,7))) +#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0))) +#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1))) +#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2))) +#define TSB_PG_FR5_PG3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,3))) +#define TSB_PG_FR5_PG4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,4))) +#define TSB_PG_FR5_PG5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,5))) +#define TSB_PG_FR5_PG6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,6))) +#define TSB_PG_FR5_PG7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,7))) +#define TSB_PG_FR6_PG2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,2))) +#define TSB_PG_FR6_PG3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,3))) +#define TSB_PG_FR6_PG4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,4))) +#define TSB_PG_FR6_PG5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,5))) +#define TSB_PG_FR6_PG6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,6))) +#define TSB_PG_FR7_PG2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,2))) +#define TSB_PG_FR7_PG3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,3))) +#define TSB_PG_FR7_PG4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,4))) +#define TSB_PG_FR7_PG5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,5))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) +#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) +#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) +#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) +#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) +#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) +#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) +#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) +#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) +#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) +#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) +#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) +#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) +#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) +#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) +#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) +#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) +#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) +#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) +#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) +#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) +#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) + + +/* Port H */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) +#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) +#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) +#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) +#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) +#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) +#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0))) +#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1))) +#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2))) +#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3))) +#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) +#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) +#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) +#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) +#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0))) +#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1))) +#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2))) +#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3))) +#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) +#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) +#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) +#define TSB_PH_FR1_PH7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,7))) +#define TSB_PH_FR3_PH0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,0))) +#define TSB_PH_FR3_PH1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,1))) +#define TSB_PH_FR3_PH2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,2))) +#define TSB_PH_FR3_PH3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,3))) +#define TSB_PH_FR3_PH4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,4))) +#define TSB_PH_FR3_PH5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,5))) +#define TSB_PH_FR3_PH6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,6))) +#define TSB_PH_FR3_PH7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,7))) +#define TSB_PH_FR4_PH0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,0))) +#define TSB_PH_FR4_PH1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,1))) +#define TSB_PH_FR4_PH2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,2))) +#define TSB_PH_FR4_PH3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,3))) +#define TSB_PH_FR5_PH0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,0))) +#define TSB_PH_FR5_PH1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,1))) +#define TSB_PH_FR5_PH2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,2))) +#define TSB_PH_FR5_PH3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,3))) +#define TSB_PH_FR5_PH4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,4))) +#define TSB_PH_FR5_PH5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,5))) +#define TSB_PH_FR5_PH6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,6))) +#define TSB_PH_FR5_PH7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,7))) +#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0))) +#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1))) +#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2))) +#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3))) +#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) +#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) +#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) +#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) +#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0))) +#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1))) +#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2))) +#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3))) +#define TSB_PH_PUP_PH4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) +#define TSB_PH_PUP_PH5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) +#define TSB_PH_PUP_PH6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) +#define TSB_PH_PUP_PH7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) +#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) +#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) +#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) +#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) +#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) +#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) +#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) +#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) +#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) +#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) +#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) + + +/* Port J */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) +#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) +#define TSB_PJ_DATA_PJ6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,6))) +#define TSB_PJ_DATA_PJ7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,7))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) +#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) +#define TSB_PJ_CR_PJ6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,6))) +#define TSB_PJ_CR_PJ7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,7))) +#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) +#define TSB_PJ_FR2_PJ5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,5))) +#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) +#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) +#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) +#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) +#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) +#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) +#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) +#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) +#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) +#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) +#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) +#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) +#define TSB_PJ_FR5_PJ6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,6))) +#define TSB_PJ_FR5_PJ7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,7))) +#define TSB_PJ_FR6_PJ2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,2))) +#define TSB_PJ_FR6_PJ3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,3))) +#define TSB_PJ_FR6_PJ6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,6))) +#define TSB_PJ_FR6_PJ7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,7))) +#define TSB_PJ_FR7_PJ2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,2))) +#define TSB_PJ_FR7_PJ3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,3))) +#define TSB_PJ_FR7_PJ6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,6))) +#define TSB_PJ_FR7_PJ7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,7))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) +#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) +#define TSB_PJ_OD_PJ6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,6))) +#define TSB_PJ_OD_PJ7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,7))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) +#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) +#define TSB_PJ_PUP_PJ6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,6))) +#define TSB_PJ_PUP_PJ7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,7))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) +#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) +#define TSB_PJ_PDN_PJ6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,6))) +#define TSB_PJ_PDN_PJ7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,7))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) +#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) +#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) +#define TSB_PJ_IE_PJ6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,6))) +#define TSB_PJ_IE_PJ7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,7))) + + +/* Port K */ +#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) +#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) +#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) +#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) +#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) +#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) +#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) +#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) +#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) +#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) +#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) +#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) +#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) +#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) +#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) +#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) +#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) +#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) +#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) +#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) +#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) +#define TSB_PK_FR1_PK5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,5))) +#define TSB_PK_FR1_PK6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,6))) +#define TSB_PK_FR2_PK0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,0))) +#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) +#define TSB_PK_FR2_PK6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,6))) +#define TSB_PK_FR2_PK7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,7))) +#define TSB_PK_FR3_PK0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,0))) +#define TSB_PK_FR3_PK1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,1))) +#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) +#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) +#define TSB_PK_FR4_PK1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,1))) +#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) +#define TSB_PK_FR4_PK5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,5))) +#define TSB_PK_FR4_PK6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,6))) +#define TSB_PK_FR4_PK7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,7))) +#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) +#define TSB_PK_FR6_PK0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,0))) +#define TSB_PK_FR6_PK1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,1))) +#define TSB_PK_FR6_PK2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,2))) +#define TSB_PK_FR6_PK3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,3))) +#define TSB_PK_FR6_PK4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,4))) +#define TSB_PK_FR6_PK5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,5))) +#define TSB_PK_FR6_PK6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,6))) +#define TSB_PK_FR6_PK7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,7))) +#define TSB_PK_FR7_PK7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR7,7))) +#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) +#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) +#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) +#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) +#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) +#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) +#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) +#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) +#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) +#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) +#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) +#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) +#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) +#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) +#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) +#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) +#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) +#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) +#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) +#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) +#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) +#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) +#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) +#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) +#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) +#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) +#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) +#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) +#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) +#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) +#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) +#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) + + +/* Port L */ +#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) +#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) +#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) +#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) +#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) +#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) +#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) +#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) +#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) +#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) +#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) +#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) +#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) +#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) +#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) +#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) +#define TSB_PL_FR1_PL7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,7))) +#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) +#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) +#define TSB_PL_FR2_PL4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,4))) +#define TSB_PL_FR2_PL5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,5))) +#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6))) +#define TSB_PL_FR2_PL7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,7))) +#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) +#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) +#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) +#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) +#define TSB_PL_FR5_PL0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,0))) +#define TSB_PL_FR5_PL1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1))) +#define TSB_PL_FR5_PL2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2))) +#define TSB_PL_FR5_PL3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3))) +#define TSB_PL_FR6_PL0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,0))) +#define TSB_PL_FR6_PL3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,3))) +#define TSB_PL_FR7_PL0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,0))) +#define TSB_PL_FR7_PL1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,1))) +#define TSB_PL_FR7_PL2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,2))) +#define TSB_PL_FR7_PL3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,3))) +#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) +#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) +#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) +#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) +#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) +#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) +#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) +#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) +#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) +#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) +#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) +#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) +#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) +#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) +#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) +#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) +#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) +#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) +#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) +#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) +#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) +#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) +#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) +#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) +#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) +#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) +#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) +#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) +#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) +#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) +#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) +#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) + + +/* Port M */ +#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) +#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) +#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) +#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) +#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) +#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) +#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) +#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) +#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) +#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) +#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) +#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) +#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) +#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) +#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) +#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) +#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) +#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) +#define TSB_PM_FR1_PM6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,6))) +#define TSB_PM_FR1_PM7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,7))) +#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) +#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) +#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) +#define TSB_PM_FR2_PM5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,5))) +#define TSB_PM_FR2_PM6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,6))) +#define TSB_PM_FR2_PM7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,7))) +#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) +#define TSB_PM_FR3_PM5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,5))) +#define TSB_PM_FR3_PM6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,6))) +#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) +#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) +#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) +#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) +#define TSB_PM_FR4_PM6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,6))) +#define TSB_PM_FR4_PM7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,7))) +#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) +#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) +#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) +#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) +#define TSB_PM_FR5_PM6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,6))) +#define TSB_PM_FR5_PM7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,7))) +#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) +#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) +#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) +#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) +#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) +#define TSB_PM_FR6_PM5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,5))) +#define TSB_PM_FR6_PM6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,6))) +#define TSB_PM_FR6_PM7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,7))) +#define TSB_PM_FR7_PM0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,0))) +#define TSB_PM_FR7_PM1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,1))) +#define TSB_PM_FR7_PM2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,2))) +#define TSB_PM_FR7_PM3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,3))) +#define TSB_PM_FR7_PM4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,4))) +#define TSB_PM_FR7_PM5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,5))) +#define TSB_PM_FR7_PM6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,6))) +#define TSB_PM_FR7_PM7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,7))) +#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) +#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) +#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) +#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) +#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) +#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) +#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) +#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) +#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) +#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) +#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) +#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) +#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) +#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) +#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) +#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) +#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) +#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) +#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) +#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) +#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) +#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) +#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) +#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) +#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) +#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) +#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) +#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) +#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) +#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) +#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) +#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) + + +/* Port N */ +#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) +#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) +#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) +#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) +#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) +#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) +#define TSB_PN_DATA_PN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,6))) +#define TSB_PN_DATA_PN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,7))) +#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) +#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) +#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) +#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) +#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) +#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) +#define TSB_PN_CR_PN6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,6))) +#define TSB_PN_CR_PN7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,7))) +#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) +#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) +#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) +#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) +#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) +#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) +#define TSB_PN_OD_PN6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,6))) +#define TSB_PN_OD_PN7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,7))) +#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) +#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) +#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) +#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) +#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) +#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) +#define TSB_PN_PUP_PN6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,6))) +#define TSB_PN_PUP_PN7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,7))) +#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) +#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) +#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) +#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) +#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) +#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) +#define TSB_PN_PDN_PN6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,6))) +#define TSB_PN_PDN_PN7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,7))) +#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) +#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) +#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) +#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) +#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) +#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) +#define TSB_PN_IE_PN6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,6))) +#define TSB_PN_IE_PN7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,7))) + + +/* Port P */ +#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) +#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) +#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) +#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) +#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) +#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) +#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) +#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) +#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) +#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) +#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) +#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) +#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) +#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) +#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) +#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) +#define TSB_PP_FR2_PP0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) +#define TSB_PP_FR2_PP1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) +#define TSB_PP_FR2_PP2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) +#define TSB_PP_FR2_PP3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,3))) +#define TSB_PP_FR2_PP4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,4))) +#define TSB_PP_FR2_PP5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,5))) +#define TSB_PP_FR2_PP6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) +#define TSB_PP_FR2_PP7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,7))) +#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) +#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) +#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) +#define TSB_PP_FR3_PP3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,3))) +#define TSB_PP_FR3_PP4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,4))) +#define TSB_PP_FR3_PP5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,5))) +#define TSB_PP_FR3_PP6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) +#define TSB_PP_FR3_PP7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,7))) +#define TSB_PP_FR5_PP0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,0))) +#define TSB_PP_FR5_PP1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,1))) +#define TSB_PP_FR5_PP2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,2))) +#define TSB_PP_FR5_PP3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,3))) +#define TSB_PP_FR5_PP4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,4))) +#define TSB_PP_FR5_PP5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,5))) +#define TSB_PP_FR5_PP6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,6))) +#define TSB_PP_FR5_PP7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,7))) +#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) +#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) +#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) +#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) +#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) +#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) +#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) +#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) +#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) +#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) +#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) +#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) +#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) +#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) +#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) +#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) +#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) +#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) +#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) +#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) +#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) +#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) +#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) +#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) +#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) +#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) +#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) +#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) +#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) +#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) +#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) +#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) + + +/* Port R */ +#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) +#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) +#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) +#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) +#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) +#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) +#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) +#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) +#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) +#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) +#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) +#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) +#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) +#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) +#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) +#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) +#define TSB_PR_FR2_PR0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,0))) +#define TSB_PR_FR2_PR1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,1))) +#define TSB_PR_FR2_PR2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,2))) +#define TSB_PR_FR2_PR3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,3))) +#define TSB_PR_FR2_PR4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,4))) +#define TSB_PR_FR2_PR5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,5))) +#define TSB_PR_FR2_PR6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,6))) +#define TSB_PR_FR2_PR7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,7))) +#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) +#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) +#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) +#define TSB_PR_FR3_PR3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,3))) +#define TSB_PR_FR3_PR4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,4))) +#define TSB_PR_FR3_PR5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,5))) +#define TSB_PR_FR3_PR6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,6))) +#define TSB_PR_FR3_PR7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,7))) +#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) +#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) +#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) +#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) +#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) +#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) +#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) +#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) +#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) +#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) +#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) +#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) +#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) +#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) +#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) +#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) +#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) +#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) +#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) +#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) +#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) +#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) +#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) +#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) +#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) +#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) +#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) +#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) +#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) +#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) +#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) +#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) + + +/* Port T */ +#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) +#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) +#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) +#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) +#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) +#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) +#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) +#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) +#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) +#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) +#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) +#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) +#define TSB_PT_FR1_PT3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) +#define TSB_PT_FR2_PT3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,3))) +#define TSB_PT_FR2_PT5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,5))) +#define TSB_PT_FR3_PT3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) +#define TSB_PT_FR6_PT3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR6,3))) +#define TSB_PT_FR7_PT2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR7,2))) +#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) +#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) +#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) +#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) +#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) +#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) +#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) +#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) +#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) +#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) +#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) +#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) +#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) +#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) +#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) +#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) +#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) +#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) +#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) +#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) +#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) +#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) +#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) +#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) + + +/* Port U */ +#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) +#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) +#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) +#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) +#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) +#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) +#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6))) +#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7))) +#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) +#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) +#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) +#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) +#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) +#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) +#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6))) +#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7))) +#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0))) +#define TSB_PU_FR2_PU1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,1))) +#define TSB_PU_FR2_PU2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,2))) +#define TSB_PU_FR2_PU3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,3))) +#define TSB_PU_FR2_PU4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,4))) +#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5))) +#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6))) +#define TSB_PU_FR2_PU7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,7))) +#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0))) +#define TSB_PU_FR3_PU2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,2))) +#define TSB_PU_FR3_PU3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,3))) +#define TSB_PU_FR3_PU4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,4))) +#define TSB_PU_FR3_PU5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,5))) +#define TSB_PU_FR3_PU6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,6))) +#define TSB_PU_FR6_PU2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,2))) +#define TSB_PU_FR6_PU3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,3))) +#define TSB_PU_FR6_PU4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,4))) +#define TSB_PU_FR6_PU5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,5))) +#define TSB_PU_FR6_PU6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,6))) +#define TSB_PU_FR6_PU7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,7))) +#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0))) +#define TSB_PU_FR7_PU1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,1))) +#define TSB_PU_FR7_PU2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,2))) +#define TSB_PU_FR7_PU3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,3))) +#define TSB_PU_FR7_PU4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,4))) +#define TSB_PU_FR7_PU5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,5))) +#define TSB_PU_FR7_PU6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,6))) +#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7))) +#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) +#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) +#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) +#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) +#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) +#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) +#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6))) +#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7))) +#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) +#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) +#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) +#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) +#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) +#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) +#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6))) +#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7))) +#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) +#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) +#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) +#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) +#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) +#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) +#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6))) +#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7))) +#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) +#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) +#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) +#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) +#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) +#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) +#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6))) +#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7))) + + +/* Port V */ +#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) +#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) +#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) +#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) +#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) +#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) +#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) +#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) +#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) +#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) +#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) +#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) +#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) +#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) +#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) +#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) +#define TSB_PV_FR1_PV4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,4))) +#define TSB_PV_FR1_PV5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,5))) +#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0))) +#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1))) +#define TSB_PV_FR2_PV2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,2))) +#define TSB_PV_FR2_PV3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,3))) +#define TSB_PV_FR2_PV4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,4))) +#define TSB_PV_FR2_PV5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,5))) +#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) +#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) +#define TSB_PV_FR3_PV0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,0))) +#define TSB_PV_FR3_PV1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,1))) +#define TSB_PV_FR3_PV2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,2))) +#define TSB_PV_FR3_PV5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,5))) +#define TSB_PV_FR3_PV6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,6))) +#define TSB_PV_FR4_PV4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,4))) +#define TSB_PV_FR4_PV5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,5))) +#define TSB_PV_FR4_PV6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,6))) +#define TSB_PV_FR4_PV7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,7))) +#define TSB_PV_FR5_PV0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,0))) +#define TSB_PV_FR5_PV1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,1))) +#define TSB_PV_FR5_PV2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,2))) +#define TSB_PV_FR5_PV3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,3))) +#define TSB_PV_FR5_PV4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,4))) +#define TSB_PV_FR5_PV5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,5))) +#define TSB_PV_FR5_PV6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,6))) +#define TSB_PV_FR5_PV7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,7))) +#define TSB_PV_FR6_PV0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,0))) +#define TSB_PV_FR6_PV1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,1))) +#define TSB_PV_FR6_PV2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,2))) +#define TSB_PV_FR6_PV3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,3))) +#define TSB_PV_FR6_PV4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,4))) +#define TSB_PV_FR6_PV5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,5))) +#define TSB_PV_FR6_PV7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,7))) +#define TSB_PV_FR7_PV0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,0))) +#define TSB_PV_FR7_PV1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,1))) +#define TSB_PV_FR7_PV2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,2))) +#define TSB_PV_FR7_PV3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,3))) +#define TSB_PV_FR7_PV4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,4))) +#define TSB_PV_FR7_PV5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,5))) +#define TSB_PV_FR7_PV6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,6))) +#define TSB_PV_FR7_PV7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,7))) +#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) +#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) +#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) +#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) +#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) +#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) +#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) +#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) +#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) +#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) +#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) +#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) +#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) +#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) +#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) +#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) +#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) +#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) +#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) +#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) +#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) +#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) +#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) +#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) +#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) +#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) +#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) +#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) +#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) +#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) +#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) +#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) + + +/* Port W */ +#define TSB_PW_DATA_PW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,0))) +#define TSB_PW_DATA_PW1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,1))) +#define TSB_PW_DATA_PW2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,2))) +#define TSB_PW_DATA_PW3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,3))) +#define TSB_PW_DATA_PW4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,4))) +#define TSB_PW_DATA_PW5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,5))) +#define TSB_PW_DATA_PW6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,6))) +#define TSB_PW_DATA_PW7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,7))) +#define TSB_PW_CR_PW0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,0))) +#define TSB_PW_CR_PW1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,1))) +#define TSB_PW_CR_PW2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,2))) +#define TSB_PW_CR_PW3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,3))) +#define TSB_PW_CR_PW4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,4))) +#define TSB_PW_CR_PW5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,5))) +#define TSB_PW_CR_PW6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,6))) +#define TSB_PW_CR_PW7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,7))) +#define TSB_PW_FR3_PW4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,4))) +#define TSB_PW_FR3_PW7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,7))) +#define TSB_PW_FR4_PW0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,0))) +#define TSB_PW_FR4_PW1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,1))) +#define TSB_PW_FR4_PW2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,2))) +#define TSB_PW_FR4_PW3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,3))) +#define TSB_PW_FR5_PW0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,0))) +#define TSB_PW_FR5_PW1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,1))) +#define TSB_PW_FR5_PW2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,2))) +#define TSB_PW_FR5_PW3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,3))) +#define TSB_PW_FR5_PW4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,4))) +#define TSB_PW_FR5_PW5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,5))) +#define TSB_PW_FR5_PW6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,6))) +#define TSB_PW_FR5_PW7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,7))) +#define TSB_PW_FR6_PW0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR6,0))) +#define TSB_PW_FR7_PW1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,1))) +#define TSB_PW_FR7_PW2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,2))) +#define TSB_PW_FR7_PW4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,4))) +#define TSB_PW_FR7_PW5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,5))) +#define TSB_PW_FR7_PW6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,6))) +#define TSB_PW_FR7_PW7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,7))) +#define TSB_PW_OD_PW0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,0))) +#define TSB_PW_OD_PW1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,1))) +#define TSB_PW_OD_PW2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,2))) +#define TSB_PW_OD_PW3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,3))) +#define TSB_PW_OD_PW4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,4))) +#define TSB_PW_OD_PW5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,5))) +#define TSB_PW_OD_PW6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,6))) +#define TSB_PW_OD_PW7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,7))) +#define TSB_PW_PUP_PW0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,0))) +#define TSB_PW_PUP_PW1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,1))) +#define TSB_PW_PUP_PW2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,2))) +#define TSB_PW_PUP_PW3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,3))) +#define TSB_PW_PUP_PW4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,4))) +#define TSB_PW_PUP_PW5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,5))) +#define TSB_PW_PUP_PW6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,6))) +#define TSB_PW_PUP_PW7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,7))) +#define TSB_PW_PDN_PW0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,0))) +#define TSB_PW_PDN_PW1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,1))) +#define TSB_PW_PDN_PW2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,2))) +#define TSB_PW_PDN_PW3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,3))) +#define TSB_PW_PDN_PW4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,4))) +#define TSB_PW_PDN_PW5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,5))) +#define TSB_PW_PDN_PW6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,6))) +#define TSB_PW_PDN_PW7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,7))) +#define TSB_PW_IE_PW0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,0))) +#define TSB_PW_IE_PW1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,1))) +#define TSB_PW_IE_PW2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,2))) +#define TSB_PW_IE_PW3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,3))) +#define TSB_PW_IE_PW4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,4))) +#define TSB_PW_IE_PW5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,5))) +#define TSB_PW_IE_PW6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,6))) +#define TSB_PW_IE_PW7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,7))) + + +/* Port Y */ +#define TSB_PY_DATA_PY0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,0))) +#define TSB_PY_DATA_PY1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,1))) +#define TSB_PY_DATA_PY2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,2))) +#define TSB_PY_DATA_PY3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,3))) +#define TSB_PY_DATA_PY4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,4))) +#define TSB_PY_CR_PY4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->CR,4))) +#define TSB_PY_FR1_PY4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR1,4))) +#define TSB_PY_FR4_PY4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR4,4))) +#define TSB_PY_OD_PY4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->OD,4))) +#define TSB_PY_PUP_PY0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,0))) +#define TSB_PY_PUP_PY1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,1))) +#define TSB_PY_PUP_PY2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,2))) +#define TSB_PY_PUP_PY3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,3))) +#define TSB_PY_PUP_PY4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,4))) +#define TSB_PY_PDN_PY0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,0))) +#define TSB_PY_PDN_PY1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,1))) +#define TSB_PY_PDN_PY2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,2))) +#define TSB_PY_PDN_PY3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,3))) +#define TSB_PY_PDN_PY4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,4))) +#define TSB_PY_IE_PY0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,0))) +#define TSB_PY_IE_PY1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,1))) +#define TSB_PY_IE_PY2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,2))) +#define TSB_PY_IE_PY3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,3))) + + +/* Internal High-speed Oscillation Adjustment */ +#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) + + +/* Oscillation Frequency Detector (OFD) */ +#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) +#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) +#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) +#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) + + + +/* Consumer Electronics Control (CEC) */ +#define TSB_CEC0_EN_CECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->EN,0))) +#define TSB_CEC0_RESET_CECRESET (*((__O uint32_t *)BITBAND_PERI(&TSB_CEC0->RESET,0))) +#define TSB_CEC0_REN_CECREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->REN,0))) +#define TSB_CEC0_RBUF_CECEOM (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,8))) +#define TSB_CEC0_RBUF_CECACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,9))) +#define TSB_CEC0_RCR1_CECOTH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,0))) +#define TSB_CEC0_RCR1_CECRIHLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,1))) +#define TSB_CEC0_RCR1_CECACKDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,24))) +#define TSB_CEC0_RCR3_CECWAVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,0))) +#define TSB_CEC0_RCR3_CECRSTAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,1))) +#define TSB_CEC0_TEN_CECTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,0))) +#define TSB_CEC0_TEN_CECTRANS (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,1))) +#define TSB_CEC0_TBUF_CECTEOM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TBUF,8))) +#define TSB_CEC0_TCR_CECBRD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TCR,4))) +#define TSB_CEC0_RSTAT_CECRIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,0))) +#define TSB_CEC0_RSTAT_CECRISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,1))) +#define TSB_CEC0_RSTAT_CECRIMAX (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,2))) +#define TSB_CEC0_RSTAT_CECRIMIN (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,3))) +#define TSB_CEC0_RSTAT_CECRIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,4))) +#define TSB_CEC0_RSTAT_CECRIOR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,5))) +#define TSB_CEC0_RSTAT_CECRIWAV (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,6))) +#define TSB_CEC0_TSTAT_CECTISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,0))) +#define TSB_CEC0_TSTAT_CECTIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,1))) +#define TSB_CEC0_TSTAT_CECTIAL (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,2))) +#define TSB_CEC0_TSTAT_CECTIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,3))) +#define TSB_CEC0_TSTAT_CECTIUR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,4))) +#define TSB_CEC0_FSSEL_CECCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->FSSEL,0))) + + +/* Remote Control Signal Preprocessor (RMC) */ +#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) +#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) +#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) +#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) +#define TSB_RMC0_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,29))) +#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) +#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) +#define TSB_RMC0_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR3,15))) +#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) +#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) +#define TSB_RMC0_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,8))) +#define TSB_RMC0_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,11))) +#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) +#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) +#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) +#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) +#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) + +#define TSB_RMC1_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->EN,0))) +#define TSB_RMC1_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->REN,0))) +#define TSB_RMC1_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,24))) +#define TSB_RMC1_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,25))) +#define TSB_RMC1_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,29))) +#define TSB_RMC1_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,30))) +#define TSB_RMC1_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,31))) +#define TSB_RMC1_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR3,15))) +#define TSB_RMC1_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR4,7))) +#define TSB_RMC1_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,7))) +#define TSB_RMC1_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,8))) +#define TSB_RMC1_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,11))) +#define TSB_RMC1_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,12))) +#define TSB_RMC1_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,13))) +#define TSB_RMC1_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,14))) +#define TSB_RMC1_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,15))) +#define TSB_RMC1_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->FSSEL,0))) + + +/* */ +#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) +#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) +#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) +#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) +#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) +#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) +#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) +#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) +#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) +#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0))) +#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1))) +#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2))) +#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3))) +#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7))) +#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) +#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) +#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) +#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) +#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) +#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) +#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) +#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) +#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) +#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) +#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) +#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14))) +#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15))) +#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) +#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) +#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) +#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) +#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) +#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) +#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) +#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) +#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) +#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) +#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) +#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) +#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) +#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) +#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) +#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) +#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) +#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) +#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0))) + + +/* */ +#define TSB_ISDA_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->EN,0))) +#define TSB_ISDA_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,0))) +#define TSB_ISDA_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,1))) +#define TSB_ISDA_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->OCR0,0))) +#define TSB_ISDA_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CR,0))) +#define TSB_ISDA_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,0))) +#define TSB_ISDA_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,1))) +#define TSB_ISDA_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,2))) +#define TSB_ISDA_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,3))) +#define TSB_ISDA_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,0))) +#define TSB_ISDA_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,1))) +#define TSB_ISDA_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,2))) +#define TSB_ISDA_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,3))) +#define TSB_ISDA_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->INTCR,0))) + +#define TSB_ISDB_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->EN,0))) +#define TSB_ISDB_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,0))) +#define TSB_ISDB_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,1))) +#define TSB_ISDB_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->OCR0,0))) +#define TSB_ISDB_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CR,0))) +#define TSB_ISDB_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,0))) +#define TSB_ISDB_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,1))) +#define TSB_ISDB_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,2))) +#define TSB_ISDB_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,3))) +#define TSB_ISDB_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,0))) +#define TSB_ISDB_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,1))) +#define TSB_ISDB_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,2))) +#define TSB_ISDB_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,3))) +#define TSB_ISDB_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->INTCR,0))) + +#define TSB_ISDC_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->EN,0))) +#define TSB_ISDC_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,0))) +#define TSB_ISDC_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,1))) +#define TSB_ISDC_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->OCR0,0))) +#define TSB_ISDC_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CR,0))) +#define TSB_ISDC_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,0))) +#define TSB_ISDC_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,1))) +#define TSB_ISDC_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,2))) +#define TSB_ISDC_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,3))) +#define TSB_ISDC_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,0))) +#define TSB_ISDC_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,1))) +#define TSB_ISDC_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,2))) +#define TSB_ISDC_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,3))) +#define TSB_ISDC_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->INTCR,0))) + +/** @} */ /* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM4GR_H__ */ + +/** @} */ /* End of group TMPM4GR */ +/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/startup_TMPM4GR.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/startup_TMPM4GR.S new file mode 100644 index 0000000..458a5a4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/startup_TMPM4GR.S @@ -0,0 +1,633 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4GR.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4GR' Device Series +; * @version V1.0.0 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 +; ******************************************************************************* +; */ + + + + + + + + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b + DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b + DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b + DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b + DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b + DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b + DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b + DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b + DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b + DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b + DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b + DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b + DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b + DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b + DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b + DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b + DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt + DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) + DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) + DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector interrupt (Unit A) + DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector interrupt (Unit B) + DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector interrupt (Unit C) + DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 + DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 + DCD INTLTTMR0_IRQHandler ; 24: Long Term Timer Interrupt(channel 0) + DCD INTHDMAATC_IRQHandler ; 25: HDMA complete of transfer(Unit A) + DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) + DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) + DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) + DCD INTMDMAATC_IRQHandler ; 29: MDMA complete of transfer(Unit A) + DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt + DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt + DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) interrupt + DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) interrupt + DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) interrupt + DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) interrupt + DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) interrupt + DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) interrupt + DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) interrupt + DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) interrupt + DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) interrupt + DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) interrupt + DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) interrupt + DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) interrupt + DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) interrupt + DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) interrupt + DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) interrupt + DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) interrupt + DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) interrupt + DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) interrupt + DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) interrupt + DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) interrupt + DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) interrupt + DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) interrupt + DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) interrupt + DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) interrupt + DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) interrupt + DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) interrupt + DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) interrupt + DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface interrupt + DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) interrupt + DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) interrupt + DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) interrupt + DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) interrupt + DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) interrupt + DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) interrupt + DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) interrupt + DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) interrupt + DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) interrupt + DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) interrupt + DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) interrupt + DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) interrupt + DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) interrupt + DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) interrupt + DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) interrupt + DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) interrupt + DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) interrupt + DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) interrupt + DCD INTFUART0_IRQHandler ; 107: FUART interrupt(channel 0) + DCD INTFUART1_IRQHandler ; 108: FUART interrupt(channel 1) + DCD INTI2C0NST_IRQHandler ; 109: I2C0 interrupt / EI2C0 status interrupt + DCD INTI2C0ATX_IRQHandler ; 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C0BRX_IRQHandler ; 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C0NA_IRQHandler ; 112: I2C0 NACK detection interrupt + DCD INTI2C1NST_IRQHandler ; 113: I2C1 interrupt / EI2C0 status interrupt + DCD INTI2C1ATX_IRQHandler ; 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C1BRX_IRQHandler ; 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C1NA_IRQHandler ; 116: I2C1 NACK detection interrupt + DCD INTI2C2NST_IRQHandler ; 117: I2C2 interrupt / EI2C0 status interrupt + DCD INTI2C2ATX_IRQHandler ; 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C2BRX_IRQHandler ; 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C2NA_IRQHandler ; 120: I2C2 NACK detection interrupt + DCD INTI2C3NST_IRQHandler ; 121: I2C3 interrupt / EI2C0 status interrupt + DCD INTI2C3ATX_IRQHandler ; 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C3BRX_IRQHandler ; 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C3NA_IRQHandler ; 124: I2C3 NACK detection interrupt + DCD INTI2C4NST_IRQHandler ; 125: I2C4 interrupt / EI2C0 status interrupt + DCD INTI2C4ATX_IRQHandler ; 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C4BRX_IRQHandler ; 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C4NA_IRQHandler ; 128: I2C4 NACK detection interrupt + DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished + DCD INTADAHP_IRQHandler ; 134: ADC high priority AD conversion interrupt + DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt + DCD INTFLCRDY_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt + DCD 0 ; 137: Reserved + DCD 0 ; 138: Reserved + DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) interrupt + DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) interrupt + DCD INTI2S0SI_IRQHandler ; 141: I2S ch0 SI transfer end interrupt + DCD INTI2S0SIERR_IRQHandler ; 142: I2S ch0 SI error interrupt + DCD INTI2S0SO_IRQHandler ; 143: I2S ch0 SO transfer end interrupt + DCD INTI2S0SOERR_IRQHandler ; 144: I2S ch0 SO error interrupt + DCD INTI2S1SI_IRQHandler ; 145: I2S ch1 SI transfer end interrupt + DCD INTI2S1SIERR_IRQHandler ; 146: I2S ch1 SI error interrupt + DCD INTI2S1SO_IRQHandler ; 147: I2S ch1 SO transfer end interrupt + DCD INTI2S1SOERR_IRQHandler ; 148: I2S ch1 SO error interrupt + DCD INTFIR0_IRQHandler ; 149: FIR ch0 interrupt + DCD INTTSSI0RX_IRQHandler ; 150: TSSI ch0 receive interrupt + DCD INTTSSI0TX_IRQHandler ; 151: TSSI ch0 transmission interrupt + DCD INTTSSI0ERR_IRQHandler ; 152: TSSI ch0 error interrupt + DCD INTTSSI1RX_IRQHandler ; 153: TSSI ch1 receive interrupt + DCD INTTSSI1TX_IRQHandler ; 154: TSSI ch1 transmission interrupt + DCD INTTSSI1ERR_IRQHandler ; 155: TSSI ch1 error interrupt + DCD 0 ; 156: Reserved + DCD 0 ; 157: Reserved + DCD 0 ; 158: Reserved + DCD 0 ; 159: Reserved + DCD 0 ; 160: Reserved + DCD 0 ; 161: Reserved + DCD 0 ; 162: Reserved + DCD 0 ; 163: Reserved + DCD 0 ; 164: Reserved + DCD 0 ; 165: Reserved + DCD 0 ; 166: Reserved + DCD 0 ; 167: Reserved + DCD INTT32A14_A_IRQHandler ; 168: T32A14 TimerA all interrupt + DCD INTT32A14_B_IRQHandler ; 169: T32A14 TimerB all interrupt + DCD INTT32A14_CT_IRQHandler ; 170: T32A14 TimerC match, overflow, and underflow Interrupt + DCD INTT32A15_A_IRQHandler ; 171: T32A15 TimerA all interrupt + DCD INTT32A15_B_IRQHandler ; 172: T32A15 TimerB all interrupt + DCD INTT32A15_C_IRQHandler ; 173: T32A15 TimerC all interrupt + DCD INTMDMAADISR_IRQHandler ; 174: MDMAC unit A Descriptor interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INTRTC_IRQHandler [WEAK] + EXPORT INTCEC0RX_IRQHandler [WEAK] + EXPORT INTCEC0TX_IRQHandler [WEAK] + EXPORT INTISDA_IRQHandler [WEAK] + EXPORT INTISDB_IRQHandler [WEAK] + EXPORT INTISDC_IRQHandler [WEAK] + EXPORT INTRMC0_IRQHandler [WEAK] + EXPORT INTRMC1_IRQHandler [WEAK] + EXPORT INTLTTMR0_IRQHandler [WEAK] + EXPORT INTHDMAATC_IRQHandler [WEAK] + EXPORT INTHDMAAERR_IRQHandler [WEAK] + EXPORT INTHDMABTC_IRQHandler [WEAK] + EXPORT INTHDMABERR_IRQHandler [WEAK] + EXPORT INTMDMAATC_IRQHandler [WEAK] + EXPORT INTT32A00_A_CT_IRQHandler [WEAK] + EXPORT INTT32A00_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A01_A_CT_IRQHandler [WEAK] + EXPORT INTT32A01_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A02_A_CT_IRQHandler [WEAK] + EXPORT INTT32A02_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A03_A_CT_IRQHandler [WEAK] + EXPORT INTT32A03_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A04_A_CT_IRQHandler [WEAK] + EXPORT INTT32A04_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A05_A_CT_IRQHandler [WEAK] + EXPORT INTT32A05_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A06_A_CT_IRQHandler [WEAK] + EXPORT INTT32A06_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A07_A_CT_IRQHandler [WEAK] + EXPORT INTT32A07_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A08_A_CT_IRQHandler [WEAK] + EXPORT INTT32A08_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A09_A_CT_IRQHandler [WEAK] + EXPORT INTT32A09_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A10_A_CT_IRQHandler [WEAK] + EXPORT INTT32A10_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A11_A_CT_IRQHandler [WEAK] + EXPORT INTT32A11_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A12_A_CT_IRQHandler [WEAK] + EXPORT INTT32A12_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A13_A_CT_IRQHandler [WEAK] + EXPORT INTT32A13_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTPWM0_IRQHandler [WEAK] + EXPORT INTT0RX_IRQHandler [WEAK] + EXPORT INTT0TX_IRQHandler [WEAK] + EXPORT INTT0ERR_IRQHandler [WEAK] + EXPORT INTT1RX_IRQHandler [WEAK] + EXPORT INTT1TX_IRQHandler [WEAK] + EXPORT INTT1ERR_IRQHandler [WEAK] + EXPORT INTT2RX_IRQHandler [WEAK] + EXPORT INTT2TX_IRQHandler [WEAK] + EXPORT INTT2ERR_IRQHandler [WEAK] + EXPORT INTT3RX_IRQHandler [WEAK] + EXPORT INTT3TX_IRQHandler [WEAK] + EXPORT INTT3ERR_IRQHandler [WEAK] + EXPORT INTT4RX_IRQHandler [WEAK] + EXPORT INTT4TX_IRQHandler [WEAK] + EXPORT INTT4ERR_IRQHandler [WEAK] + EXPORT INTT5RX_IRQHandler [WEAK] + EXPORT INTT5TX_IRQHandler [WEAK] + EXPORT INTT5ERR_IRQHandler [WEAK] + EXPORT INTT6RX_IRQHandler [WEAK] + EXPORT INTT6TX_IRQHandler [WEAK] + EXPORT INTT6ERR_IRQHandler [WEAK] + EXPORT INTT7RX_IRQHandler [WEAK] + EXPORT INTT7TX_IRQHandler [WEAK] + EXPORT INTT7ERR_IRQHandler [WEAK] + EXPORT INTT8RX_IRQHandler [WEAK] + EXPORT INTT8TX_IRQHandler [WEAK] + EXPORT INTT8ERR_IRQHandler [WEAK] + EXPORT INTSMI0_IRQHandler [WEAK] + EXPORT INTUART0RX_IRQHandler [WEAK] + EXPORT INTUART0TX_IRQHandler [WEAK] + EXPORT INTUART0ERR_IRQHandler [WEAK] + EXPORT INTUART1RX_IRQHandler [WEAK] + EXPORT INTUART1TX_IRQHandler [WEAK] + EXPORT INTUART1ERR_IRQHandler [WEAK] + EXPORT INTUART2RX_IRQHandler [WEAK] + EXPORT INTUART2TX_IRQHandler [WEAK] + EXPORT INTUART2ERR_IRQHandler [WEAK] + EXPORT INTUART3RX_IRQHandler [WEAK] + EXPORT INTUART3TX_IRQHandler [WEAK] + EXPORT INTUART3ERR_IRQHandler [WEAK] + EXPORT INTUART4RX_IRQHandler [WEAK] + EXPORT INTUART4TX_IRQHandler [WEAK] + EXPORT INTUART4ERR_IRQHandler [WEAK] + EXPORT INTUART5RX_IRQHandler [WEAK] + EXPORT INTUART5TX_IRQHandler [WEAK] + EXPORT INTUART5ERR_IRQHandler [WEAK] + EXPORT INTFUART0_IRQHandler [WEAK] + EXPORT INTFUART1_IRQHandler [WEAK] + EXPORT INTI2C0NST_IRQHandler [WEAK] + EXPORT INTI2C0ATX_IRQHandler [WEAK] + EXPORT INTI2C0BRX_IRQHandler [WEAK] + EXPORT INTI2C0NA_IRQHandler [WEAK] + EXPORT INTI2C1NST_IRQHandler [WEAK] + EXPORT INTI2C1ATX_IRQHandler [WEAK] + EXPORT INTI2C1BRX_IRQHandler [WEAK] + EXPORT INTI2C1NA_IRQHandler [WEAK] + EXPORT INTI2C2NST_IRQHandler [WEAK] + EXPORT INTI2C2ATX_IRQHandler [WEAK] + EXPORT INTI2C2BRX_IRQHandler [WEAK] + EXPORT INTI2C2NA_IRQHandler [WEAK] + EXPORT INTI2C3NST_IRQHandler [WEAK] + EXPORT INTI2C3ATX_IRQHandler [WEAK] + EXPORT INTI2C3BRX_IRQHandler [WEAK] + EXPORT INTI2C3NA_IRQHandler [WEAK] + EXPORT INTI2C4NST_IRQHandler [WEAK] + EXPORT INTI2C4ATX_IRQHandler [WEAK] + EXPORT INTI2C4BRX_IRQHandler [WEAK] + EXPORT INTI2C4NA_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTADAHP_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + EXPORT INTFLCRDY_IRQHandler [WEAK] + EXPORT INTMDMAABERR_IRQHandler [WEAK] + EXPORT INTMDMAADERR_IRQHandler [WEAK] + EXPORT INTI2S0SI_IRQHandler [WEAK] + EXPORT INTI2S0SIERR_IRQHandler [WEAK] + EXPORT INTI2S0SO_IRQHandler [WEAK] + EXPORT INTI2S0SOERR_IRQHandler [WEAK] + EXPORT INTI2S1SI_IRQHandler [WEAK] + EXPORT INTI2S1SIERR_IRQHandler [WEAK] + EXPORT INTI2S1SO_IRQHandler [WEAK] + EXPORT INTI2S1SOERR_IRQHandler [WEAK] + EXPORT INTFIR0_IRQHandler [WEAK] + EXPORT INTTSSI0RX_IRQHandler [WEAK] + EXPORT INTTSSI0TX_IRQHandler [WEAK] + EXPORT INTTSSI0ERR_IRQHandler [WEAK] + EXPORT INTTSSI1RX_IRQHandler [WEAK] + EXPORT INTTSSI1TX_IRQHandler [WEAK] + EXPORT INTTSSI1ERR_IRQHandler [WEAK] + EXPORT INTT32A14_A_IRQHandler [WEAK] + EXPORT INTT32A14_B_IRQHandler [WEAK] + EXPORT INTT32A14_CT_IRQHandler [WEAK] + EXPORT INTT32A15_A_IRQHandler [WEAK] + EXPORT INTT32A15_B_IRQHandler [WEAK] + EXPORT INTT32A15_C_IRQHandler [WEAK] + EXPORT INTMDMAADISR_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INTRTC_IRQHandler +INTCEC0RX_IRQHandler +INTCEC0TX_IRQHandler +INTISDA_IRQHandler +INTISDB_IRQHandler +INTISDC_IRQHandler +INTRMC0_IRQHandler +INTRMC1_IRQHandler +INTLTTMR0_IRQHandler +INTHDMAATC_IRQHandler +INTHDMAAERR_IRQHandler +INTHDMABTC_IRQHandler +INTHDMABERR_IRQHandler +INTMDMAATC_IRQHandler +INTT32A00_A_CT_IRQHandler +INTT32A00_B_C01_CPC_IRQHandler +INTT32A01_A_CT_IRQHandler +INTT32A01_B_C01_CPC_IRQHandler +INTT32A02_A_CT_IRQHandler +INTT32A02_B_C01_CPC_IRQHandler +INTT32A03_A_CT_IRQHandler +INTT32A03_B_C01_CPC_IRQHandler +INTT32A04_A_CT_IRQHandler +INTT32A04_B_C01_CPC_IRQHandler +INTT32A05_A_CT_IRQHandler +INTT32A05_B_C01_CPC_IRQHandler +INTT32A06_A_CT_IRQHandler +INTT32A06_B_C01_CPC_IRQHandler +INTT32A07_A_CT_IRQHandler +INTT32A07_B_C01_CPC_IRQHandler +INTT32A08_A_CT_IRQHandler +INTT32A08_B_C01_CPC_IRQHandler +INTT32A09_A_CT_IRQHandler +INTT32A09_B_C01_CPC_IRQHandler +INTT32A10_A_CT_IRQHandler +INTT32A10_B_C01_CPC_IRQHandler +INTT32A11_A_CT_IRQHandler +INTT32A11_B_C01_CPC_IRQHandler +INTT32A12_A_CT_IRQHandler +INTT32A12_B_C01_CPC_IRQHandler +INTT32A13_A_CT_IRQHandler +INTT32A13_B_C01_CPC_IRQHandler +INTEMG0_IRQHandler +INTOVV0_IRQHandler +INTPWM0_IRQHandler +INTT0RX_IRQHandler +INTT0TX_IRQHandler +INTT0ERR_IRQHandler +INTT1RX_IRQHandler +INTT1TX_IRQHandler +INTT1ERR_IRQHandler +INTT2RX_IRQHandler +INTT2TX_IRQHandler +INTT2ERR_IRQHandler +INTT3RX_IRQHandler +INTT3TX_IRQHandler +INTT3ERR_IRQHandler +INTT4RX_IRQHandler +INTT4TX_IRQHandler +INTT4ERR_IRQHandler +INTT5RX_IRQHandler +INTT5TX_IRQHandler +INTT5ERR_IRQHandler +INTT6RX_IRQHandler +INTT6TX_IRQHandler +INTT6ERR_IRQHandler +INTT7RX_IRQHandler +INTT7TX_IRQHandler +INTT7ERR_IRQHandler +INTT8RX_IRQHandler +INTT8TX_IRQHandler +INTT8ERR_IRQHandler +INTSMI0_IRQHandler +INTUART0RX_IRQHandler +INTUART0TX_IRQHandler +INTUART0ERR_IRQHandler +INTUART1RX_IRQHandler +INTUART1TX_IRQHandler +INTUART1ERR_IRQHandler +INTUART2RX_IRQHandler +INTUART2TX_IRQHandler +INTUART2ERR_IRQHandler +INTUART3RX_IRQHandler +INTUART3TX_IRQHandler +INTUART3ERR_IRQHandler +INTUART4RX_IRQHandler +INTUART4TX_IRQHandler +INTUART4ERR_IRQHandler +INTUART5RX_IRQHandler +INTUART5TX_IRQHandler +INTUART5ERR_IRQHandler +INTFUART0_IRQHandler +INTFUART1_IRQHandler +INTI2C0NST_IRQHandler +INTI2C0ATX_IRQHandler +INTI2C0BRX_IRQHandler +INTI2C0NA_IRQHandler +INTI2C1NST_IRQHandler +INTI2C1ATX_IRQHandler +INTI2C1BRX_IRQHandler +INTI2C1NA_IRQHandler +INTI2C2NST_IRQHandler +INTI2C2ATX_IRQHandler +INTI2C2BRX_IRQHandler +INTI2C2NA_IRQHandler +INTI2C3NST_IRQHandler +INTI2C3ATX_IRQHandler +INTI2C3BRX_IRQHandler +INTI2C3NA_IRQHandler +INTI2C4NST_IRQHandler +INTI2C4ATX_IRQHandler +INTI2C4BRX_IRQHandler +INTI2C4NA_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTADAHP_IRQHandler +INTFLDRDY_IRQHandler +INTFLCRDY_IRQHandler +INTMDMAABERR_IRQHandler +INTMDMAADERR_IRQHandler +INTI2S0SI_IRQHandler +INTI2S0SIERR_IRQHandler +INTI2S0SO_IRQHandler +INTI2S0SOERR_IRQHandler +INTI2S1SI_IRQHandler +INTI2S1SIERR_IRQHandler +INTI2S1SO_IRQHandler +INTI2S1SOERR_IRQHandler +INTFIR0_IRQHandler +INTTSSI0RX_IRQHandler +INTTSSI0TX_IRQHandler +INTTSSI0ERR_IRQHandler +INTTSSI1RX_IRQHandler +INTTSSI1TX_IRQHandler +INTTSSI1ERR_IRQHandler +INTT32A14_A_IRQHandler +INTT32A14_B_IRQHandler +INTT32A14_CT_IRQHandler +INTT32A15_A_IRQHandler +INTT32A15_B_IRQHandler +INTT32A15_C_IRQHandler +INTMDMAADISR_IRQHandler + + B . + + ENDP + + + ALIGN + + + + + + + + + + + + END + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct new file mode 100644 index 0000000..72f3717 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_ARM_STD/tmpm4grf20fg.sct @@ -0,0 +1,84 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +/* + * Copyright(C) 2019, Toshiba Electronic Device Solutions Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +;; TMPM4G9F15FG scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) +;; Compatible with ISSM model + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x000200000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x40000 +#endif + + +#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE + +#define VECTOR_SIZE 0x300 + +; TMPM4GR: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x40000) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region +{ + ER_IROM1 MBED_APP_START MBED_APP_SIZE + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 MBED_RAM_START + VECTOR_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - Stack_Size) + { + txz_fc.o (+RO) + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S new file mode 100644 index 0000000..073218e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4GR.S @@ -0,0 +1,586 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4GR.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4GR' Device Series +; * @version V1.0.0 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 +; ******************************************************************************* +; */ +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long INT00_IRQHandler // 0: Interrupt pin 00a/00b + .long INT01_IRQHandler // 1: Interrupt pin 01a/00b + .long INT02_IRQHandler // 2: Interrupt pin 02a/00b + .long INT03_IRQHandler // 3: Interrupt pin 03a/03b + .long INT04_IRQHandler // 4: Interrupt pin 04a/04b + .long INT05_IRQHandler // 5: Interrupt pin 05a/05b + .long INT06_IRQHandler // 6: Interrupt pin 06a/06b + .long INT07_IRQHandler // 7: Interrupt pin 07a/07b + .long INT08_IRQHandler // 8: Interrupt pin 08a/08b + .long INT09_IRQHandler // 9: Interrupt pin 09a/09b + .long INT10_IRQHandler // 10: Interrupt pin 10a/10b + .long INT11_IRQHandler // 11: Interrupt pin 11a/11b + .long INT12_IRQHandler // 12: Interrupt pin 12a/12b + .long INT13_IRQHandler // 13: Interrupt pin 13a/13b + .long INT14_IRQHandler // 14: Interrupt pin 14a/14b + .long INT15_IRQHandler // 15: Interrupt pin 15a/15b + .long INTRTC_IRQHandler // 16: Real time clock(XHz) interrupt + .long INTCEC0RX_IRQHandler // 17: CEC reception interrupt (channel 0) + .long INTCEC0TX_IRQHandler // 18: CEC transmission interrupt (channel 0) + .long INTISDA_IRQHandler // 19: Interval Sensing Detector interrupt (Unit A) + .long INTISDB_IRQHandler // 20: Interval Sensing Detector interrupt (Unit B) + .long INTISDC_IRQHandler // 21: Interval Sensing Detector interrupt (Unit C) + .long INTRMC0_IRQHandler // 22: Remote control reception interrupt 0 + .long INTRMC1_IRQHandler // 23: Remote control reception interrupt 1 + .long INTLTTMR0_IRQHandler // 24: Long Term Timer Interrupt(channel 0) + .long INTHDMAATC_IRQHandler // 25: HDMA complete of transfer(Unit A) + .long INTHDMAAERR_IRQHandler // 26: HDMA transfer error(Unit A) + .long INTHDMABTC_IRQHandler // 27: HDMA end of transfer(Unit B) + .long INTHDMABERR_IRQHandler // 28: HDMA transfer error(Unit B) + .long INTMDMAATC_IRQHandler // 29: MDMA complete of transfer(Unit A) + .long INTT32A00_A_CT_IRQHandler // 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A00_B_C01_CPC_IRQHandler// 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A01_A_CT_IRQHandler // 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A01_B_C01_CPC_IRQHandler// 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A02_A_CT_IRQHandler // 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A02_B_C01_CPC_IRQHandler// 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A03_A_CT_IRQHandler // 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A03_B_C01_CPC_IRQHandler// 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A04_A_CT_IRQHandler // 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A04_B_C01_CPC_IRQHandler// 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A05_A_CT_IRQHandler // 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A05_B_C01_CPC_IRQHandler// 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A06_A_CT_IRQHandler // 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A06_B_C01_CPC_IRQHandler// 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A07_A_CT_IRQHandler // 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A07_B_C01_CPC_IRQHandler// 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A08_A_CT_IRQHandler // 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A08_B_C01_CPC_IRQHandler// 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A09_A_CT_IRQHandler // 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A09_B_C01_CPC_IRQHandler// 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A10_A_CT_IRQHandler // 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A10_B_C01_CPC_IRQHandler// 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A11_A_CT_IRQHandler // 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A11_B_C01_CPC_IRQHandler// 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A12_A_CT_IRQHandler // 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A12_B_C01_CPC_IRQHandler// 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A13_A_CT_IRQHandler // 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A13_B_C01_CPC_IRQHandler// 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTEMG0_IRQHandler // 58: PMD0 EMG interrupt + .long INTOVV0_IRQHandler // 59: PMD0 OVV interrupt + .long INTPWM0_IRQHandler // 60: PMD0 interrupt + .long INTT0RX_IRQHandler // 61: TSPI/SIO reception (channel 0) interrupt + .long INTT0TX_IRQHandler // 62: TSPI/SIO transmit (channel 0) interrupt + .long INTT0ERR_IRQHandler // 63: TSPI/SIO error (channel 0) interrupt + .long INTT1RX_IRQHandler // 64: TSPI/SIO reception (channel 1) interrupt + .long INTT1TX_IRQHandler // 65: TSPI/SIO transmit (channel 1) interrupt + .long INTT1ERR_IRQHandler // 66: TSPI/SIO error (channel 1) interrupt + .long INTT2RX_IRQHandler // 67: TSPI/SIO reception (channel 2) interrupt + .long INTT2TX_IRQHandler // 68: TSPI/SIO transmit (channel 2) interrupt + .long INTT2ERR_IRQHandler // 69: TSPI/SIO error (channel 2) interrupt + .long INTT3RX_IRQHandler // 70: TSPI/SIO reception (channel 3) interrupt + .long INTT3TX_IRQHandler // 71: TSPI/SIO transmit (channel 3) interrupt + .long INTT3ERR_IRQHandler // 72: TSPI/SIO error (channel 3) interrupt + .long INTT4RX_IRQHandler // 73: TSPI/SIO reception (channel 4) interrupt + .long INTT4TX_IRQHandler // 74: TSPI/SIO transmit (channel 4) interrupt + .long INTT4ERR_IRQHandler // 75: TSPI/SIO error (channel 4) interrupt + .long INTT5RX_IRQHandler // 76: TSPI/SIO reception (channel 5) interrupt + .long INTT5TX_IRQHandler // 77: TSPI/SIO transmit (channel 5) interrupt + .long INTT5ERR_IRQHandler // 78: TSPI/SIO error (channel 5) interrupt + .long INTT6RX_IRQHandler // 79: TSPI/SIO reception (channel 6) interrupt + .long INTT6TX_IRQHandler // 80: TSPI/SIO transmit (channel 6) interrupt + .long INTT6ERR_IRQHandler // 81: TSPI/SIO error (channel 6) interrupt + .long INTT7RX_IRQHandler // 82: TSPI/SIO reception (channel 7) interrupt + .long INTT7TX_IRQHandler // 83: TSPI/SIO transmit (channel 7) interrupt + .long INTT7ERR_IRQHandler // 84: TSPI/SIO error (channel 7) interrupt + .long INTT8RX_IRQHandler // 85: TSPI/SIO reception (channel 8) interrupt + .long INTT8TX_IRQHandler // 86: TSPI/SIO transmit (channel 8) interrupt + .long INTT8ERR_IRQHandler // 87: TSPI/SIO error (channel 8) interrupt + .long INTSMI0_IRQHandler // 88: Serial Memory Interface interrupt + .long INTUART0RX_IRQHandler // 89: UART reception (channel 0) interrupt + .long INTUART0TX_IRQHandler // 90: UART transmit (channel 0) interrupt + .long INTUART0ERR_IRQHandler // 91: UART error (channel 0) interrupt + .long INTUART1RX_IRQHandler // 92: UART reception (channel 1) interrupt + .long INTUART1TX_IRQHandler // 93: UART transmit (channel 1) interrupt + .long INTUART1ERR_IRQHandler // 94: UART error (channel 1) interrupt + .long INTUART2RX_IRQHandler // 95: UART reception (channel 2) interrupt + .long INTUART2TX_IRQHandler // 96: UART transmit (channel 2) interrupt + .long INTUART2ERR_IRQHandler // 97: UART error (channel 2) interrupt + .long INTUART3RX_IRQHandler // 98: UART reception (channel 3) interrupt + .long INTUART3TX_IRQHandler // 99: UART transmit (channel 3) interrupt + .long INTUART3ERR_IRQHandler // 100: UART error (channel 3) interrupt + .long INTUART4RX_IRQHandler // 101: UART reception (channel 4) interrupt + .long INTUART4TX_IRQHandler // 102: UART transmit (channel 4) interrupt + .long INTUART4ERR_IRQHandler // 103: UART error (channel 4) interrupt + .long INTUART5RX_IRQHandler // 104: UART reception (channel 5) interrupt + .long INTUART5TX_IRQHandler // 105: UART transmit (channel 5) interrupt + .long INTUART5ERR_IRQHandler // 106: UART error (channel 5) interrupt + .long INTFUART0_IRQHandler // 107: FUART interrupt(channel 0) + .long INTFUART1_IRQHandler // 108: FUART interrupt(channel 1) + .long INTI2C0NST_IRQHandler // 109: I2C0 interrupt / EI2C0 status interrupt + .long INTI2C0ATX_IRQHandler // 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C0BRX_IRQHandler // 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C0NA_IRQHandler // 112: I2C0 NACK detection interrupt + .long INTI2C1NST_IRQHandler // 113: I2C1 interrupt / EI2C0 status interrupt + .long INTI2C1ATX_IRQHandler // 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C1BRX_IRQHandler // 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C1NA_IRQHandler // 116: I2C1 NACK detection interrupt + .long INTI2C2NST_IRQHandler // 117: I2C2 interrupt / EI2C0 status interrupt + .long INTI2C2ATX_IRQHandler // 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C2BRX_IRQHandler // 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C2NA_IRQHandler // 120: I2C2 NACK detection interrupt + .long INTI2C3NST_IRQHandler // 121: I2C3 interrupt / EI2C0 status interrupt + .long INTI2C3ATX_IRQHandler // 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C3BRX_IRQHandler // 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C3NA_IRQHandler // 124: I2C3 NACK detection interrupt + .long INTI2C4NST_IRQHandler // 125: I2C4 interrupt / EI2C0 status interrupt + .long INTI2C4ATX_IRQHandler // 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C4BRX_IRQHandler // 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C4NA_IRQHandler // 128: I2C4 NACK detection interrupt + .long INTADACP0_IRQHandler // 129: ADC conversion monitoring function interrupt 0 + .long INTADACP1_IRQHandler // 130: ADC conversion monitoring function interrupt 1 + .long INTADATRG_IRQHandler // 131: ADC conversion triggered by General purpose is finished + .long INTADASGL_IRQHandler // 132: ADC conversion triggered by Single program is finished + .long INTADACNT_IRQHandler // 133: ADC conversion triggered by Continuity program is finished + .long INTADAHP_IRQHandler // 134: ADC high priority AD conversion interrupt + .long INTFLDRDY_IRQHandler // 135: Data FLASH Ready interrupt + .long INTFLCRDY_IRQHandler // 136: Code FLASH Area0/1 Ready interrupt + .long 0 // 137: Reserved + .long 0 // 138: Reserved + .long INTMDMAABERR_IRQHandler // 139: MDMA bus error(Unit A) interrupt + .long INTMDMAADERR_IRQHandler // 140: MDMA descriptor error(Unit A) interrupt + .long INTI2S0SI_IRQHandler // 141: I2S ch0 SI transfer end interrupt + .long INTI2S0SIERR_IRQHandler // 142: I2S ch0 SI error interrupt + .long INTI2S0SO_IRQHandler // 143: I2S ch0 SO transfer end interrupt + .long INTI2S0SOERR_IRQHandler // 144: I2S ch0 SO error interrupt + .long INTI2S1SI_IRQHandler // 145: I2S ch1 SI transfer end interrupt + .long INTI2S1SIERR_IRQHandler // 146: I2S ch1 SI error interrupt + .long INTI2S1SO_IRQHandler // 147: I2S ch1 SO transfer end interrupt + .long INTI2S1SOERR_IRQHandler // 148: I2S ch1 SO error interrupt + .long INTFIR0_IRQHandler // 149: FIR ch0 interrupt + .long INTTSSI0RX_IRQHandler // 150: TSSI ch0 receive interrupt + .long INTTSSI0TX_IRQHandler // 151: TSSI ch0 transmission interrupt + .long INTTSSI0ERR_IRQHandler // 152: TSSI ch0 error interrupt + .long INTTSSI1RX_IRQHandler // 153: TSSI ch1 receive interrupt + .long INTTSSI1TX_IRQHandler // 154: TSSI ch1 transmission interrupt + .long INTTSSI1ERR_IRQHandler // 155: TSSI ch1 error interrupt + .long 0 // 156: Reserved + .long 0 // 157: Reserved + .long 0 // 158: Reserved + .long 0 // 159: Reserved + .long 0 // 160: Reserved + .long 0 // 161: Reserved + .long 0 // 162: Reserved + .long 0 // 163: Reserved + .long 0 // 164: Reserved + .long 0 // 165: Reserved + .long 0 // 166: Reserved + .long 0 // 167: Reserved + .long INTT32A14_A_IRQHandler // 168: T32A14 TimerA all interrupt + .long INTT32A14_B_IRQHandler // 169: T32A14 TimerB all interrupt + .long INTT32A14_CT_IRQHandler // 170: T32A14 TimerC match, overflow, and underflow Interrupt + .long INTT32A15_A_IRQHandler // 171: T32A15 TimerA all interrupt + .long INTT32A15_B_IRQHandler // 172: T32A15 TimerB all interrupt + .long INTT32A15_C_IRQHandler // 173: T32A15 TimerC all interrupt + .long INTMDMAADISR_IRQHandler // 174: MDMAC unit A Descriptor interrupt + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INTRTC_IRQHandler + def_irq_handler INTCEC0RX_IRQHandler + def_irq_handler INTCEC0TX_IRQHandler + def_irq_handler INTISDA_IRQHandler + def_irq_handler INTISDB_IRQHandler + def_irq_handler INTISDC_IRQHandler + def_irq_handler INTRMC0_IRQHandler + def_irq_handler INTRMC1_IRQHandler + def_irq_handler INTLTTMR0_IRQHandler + def_irq_handler INTHDMAATC_IRQHandler + def_irq_handler INTHDMAAERR_IRQHandler + def_irq_handler INTHDMABTC_IRQHandler + def_irq_handler INTHDMABERR_IRQHandler + def_irq_handler INTMDMAATC_IRQHandler + def_irq_handler INTT32A00_A_CT_IRQHandler + def_irq_handler INTT32A00_B_C01_CPC_IRQHandler + def_irq_handler INTT32A01_A_CT_IRQHandler + def_irq_handler INTT32A01_B_C01_CPC_IRQHandler + def_irq_handler INTT32A02_A_CT_IRQHandler + def_irq_handler INTT32A02_B_C01_CPC_IRQHandler + def_irq_handler INTT32A03_A_CT_IRQHandler + def_irq_handler INTT32A03_B_C01_CPC_IRQHandler + def_irq_handler INTT32A04_A_CT_IRQHandler + def_irq_handler INTT32A04_B_C01_CPC_IRQHandler + def_irq_handler INTT32A05_A_CT_IRQHandler + def_irq_handler INTT32A05_B_C01_CPC_IRQHandler + def_irq_handler INTT32A06_A_CT_IRQHandler + def_irq_handler INTT32A06_B_C01_CPC_IRQHandler + def_irq_handler INTT32A07_A_CT_IRQHandler + def_irq_handler INTT32A07_B_C01_CPC_IRQHandler + def_irq_handler INTT32A08_A_CT_IRQHandler + def_irq_handler INTT32A08_B_C01_CPC_IRQHandler + def_irq_handler INTT32A09_A_CT_IRQHandler + def_irq_handler INTT32A09_B_C01_CPC_IRQHandler + def_irq_handler INTT32A10_A_CT_IRQHandler + def_irq_handler INTT32A10_B_C01_CPC_IRQHandler + def_irq_handler INTT32A11_A_CT_IRQHandler + def_irq_handler INTT32A11_B_C01_CPC_IRQHandler + def_irq_handler INTT32A12_A_CT_IRQHandler + def_irq_handler INTT32A12_B_C01_CPC_IRQHandler + def_irq_handler INTT32A13_A_CT_IRQHandler + def_irq_handler INTT32A13_B_C01_CPC_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTPWM0_IRQHandler + def_irq_handler INTT0RX_IRQHandler + def_irq_handler INTT0TX_IRQHandler + def_irq_handler INTT0ERR_IRQHandler + def_irq_handler INTT1RX_IRQHandler + def_irq_handler INTT1TX_IRQHandler + def_irq_handler INTT1ERR_IRQHandler + def_irq_handler INTT2RX_IRQHandler + def_irq_handler INTT2TX_IRQHandler + def_irq_handler INTT2ERR_IRQHandler + def_irq_handler INTT3RX_IRQHandler + def_irq_handler INTT3TX_IRQHandler + def_irq_handler INTT3ERR_IRQHandler + def_irq_handler INTT4RX_IRQHandler + def_irq_handler INTT4TX_IRQHandler + def_irq_handler INTT4ERR_IRQHandler + def_irq_handler INTT5RX_IRQHandler + def_irq_handler INTT5TX_IRQHandler + def_irq_handler INTT5ERR_IRQHandler + def_irq_handler INTT6RX_IRQHandler + def_irq_handler INTT6TX_IRQHandler + def_irq_handler INTT6ERR_IRQHandler + def_irq_handler INTT7RX_IRQHandler + def_irq_handler INTT7TX_IRQHandler + def_irq_handler INTT7ERR_IRQHandler + def_irq_handler INTT8RX_IRQHandler + def_irq_handler INTT8TX_IRQHandler + def_irq_handler INTT8ERR_IRQHandler + def_irq_handler INTSMI0_IRQHandler + def_irq_handler INTUART0RX_IRQHandler + def_irq_handler INTUART0TX_IRQHandler + def_irq_handler INTUART0ERR_IRQHandler + def_irq_handler INTUART1RX_IRQHandler + def_irq_handler INTUART1TX_IRQHandler + def_irq_handler INTUART1ERR_IRQHandler + def_irq_handler INTUART2RX_IRQHandler + def_irq_handler INTUART2TX_IRQHandler + def_irq_handler INTUART2ERR_IRQHandler + def_irq_handler INTUART3RX_IRQHandler + def_irq_handler INTUART3TX_IRQHandler + def_irq_handler INTUART3ERR_IRQHandler + def_irq_handler INTUART4RX_IRQHandler + def_irq_handler INTUART4TX_IRQHandler + def_irq_handler INTUART4ERR_IRQHandler + def_irq_handler INTUART5RX_IRQHandler + def_irq_handler INTUART5TX_IRQHandler + def_irq_handler INTUART5ERR_IRQHandler + def_irq_handler INTFUART0_IRQHandler + def_irq_handler INTFUART1_IRQHandler + def_irq_handler INTI2C0NST_IRQHandler + def_irq_handler INTI2C0ATX_IRQHandler + def_irq_handler INTI2C0BRX_IRQHandler + def_irq_handler INTI2C0NA_IRQHandler + def_irq_handler INTI2C1NST_IRQHandler + def_irq_handler INTI2C1ATX_IRQHandler + def_irq_handler INTI2C1BRX_IRQHandler + def_irq_handler INTI2C1NA_IRQHandler + def_irq_handler INTI2C2NST_IRQHandler + def_irq_handler INTI2C2ATX_IRQHandler + def_irq_handler INTI2C2BRX_IRQHandler + def_irq_handler INTI2C2NA_IRQHandler + def_irq_handler INTI2C3NST_IRQHandler + def_irq_handler INTI2C3ATX_IRQHandler + def_irq_handler INTI2C3BRX_IRQHandler + def_irq_handler INTI2C3NA_IRQHandler + def_irq_handler INTI2C4NST_IRQHandler + def_irq_handler INTI2C4ATX_IRQHandler + def_irq_handler INTI2C4BRX_IRQHandler + def_irq_handler INTI2C4NA_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTADAHP_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + def_irq_handler INTFLCRDY_IRQHandler + def_irq_handler INTMDMAABERR_IRQHandler + def_irq_handler INTMDMAADERR_IRQHandler + def_irq_handler INTI2S0SI_IRQHandler + def_irq_handler INTI2S0SIERR_IRQHandler + def_irq_handler INTI2S0SO_IRQHandler + def_irq_handler INTI2S0SOERR_IRQHandler + def_irq_handler INTI2S1SI_IRQHandler + def_irq_handler INTI2S1SIERR_IRQHandler + def_irq_handler INTI2S1SO_IRQHandler + def_irq_handler INTI2S1SOERR_IRQHandler + def_irq_handler INTFIR0_IRQHandler + def_irq_handler INTTSSI0RX_IRQHandler + def_irq_handler INTTSSI0TX_IRQHandler + def_irq_handler INTTSSI0ERR_IRQHandler + def_irq_handler INTTSSI1RX_IRQHandler + def_irq_handler INTTSSI1TX_IRQHandler + def_irq_handler INTTSSI1ERR_IRQHandler + def_irq_handler INTT32A14_A_IRQHandler + def_irq_handler INTT32A14_B_IRQHandler + def_irq_handler INTT32A14_CT_IRQHandler + def_irq_handler INTT32A15_A_IRQHandler + def_irq_handler INTT32A15_B_IRQHandler + def_irq_handler INTT32A15_C_IRQHandler + def_irq_handler INTMDMAADISR_IRQHandler + + .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld new file mode 100644 index 0000000..ec14e95 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/TOOLCHAIN_GCC_ARM/tmpm4grf20fg.ld @@ -0,0 +1,197 @@ +/* + * Copyright(C) 2020, Toshiba Electronic Device Solutions Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Linker script for Toshiba TMPM4GR */ + +/* Linker script to configure memory regions. */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + /* 8_byte_aligned((175 + 16) vect * 4 bytes) = 8_byte_aligned(0x2FC) = 0x300 */ + RAM (rwx) : ORIGIN = (0x20000000 + 0x300), LENGTH = (256K - 0x300) +} + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + *(.ram_func*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis.h new file mode 100644 index 0000000..56102df --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM4GR.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis_nvic.h new file mode 100644 index 0000000..fda4e00 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/cmsis_nvic.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + + +#if defined(__ICCARM__) +#pragma section=".intvec" +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) +#elif defined(__CC_ARM) +extern uint32_t Load$$LR$$LR_IROM1$$Base[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) +#elif defined(__GNUC__) +extern uint32_t vectors[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors) +#else +#error "Flash vector address not set for this toolchain" +#endif + + +#define NVIC_NUM_VECTORS (191) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.c new file mode 100644 index 0000000..5372d7f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.c @@ -0,0 +1,343 @@ +/** + ******************************************************************************* + * @file system_TMPM4Gx.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM4Gx' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#include "TMPM4GR.h" +#include "txz_flash.h" +#include "txz_hal.h" + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ +#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ +#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ +#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ +#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ +#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ + +#define STBYCR_Val (0x00000000UL) + +#define CG_8M_MUL_24_FPLL (0x00245030UL<<8U) /* fPLL = 8MHz * 24 */ +#define CG_10M_MUL_19_1875_FPLL (0x002E9626UL<<8U) /* fPLL = 10MHz * 19.1875 */ +#define CG_12M_MUL_16_FPLL (0x0036D020UL<<8U) /* fPLL = 12MHz * 16 */ +#define CG_16M_MUL_12_FPLL (0x00495018UL<<8U) /* fPLL = 16MHz * 12 */ +#define CG_24M_MUL_8_FPLL (0x006D9010UL<<8U) /* fPLL = 24MHz * 8 */ + +#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) +#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) +#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) +#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) + +#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) +#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) +#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) + +#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) +#define CG_OSCCR_EOSCEN_SET (0x00000002UL) +#define CG_OSCCR_OSCSEL_SET (0x00000100UL) + +#define CG_WUPHCR_WUON_START_SET (0x00000001UL) + +#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ +#if (CLOCK_SETUP) +#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_12M_MUL_16_FPLL +#else +#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_10M_MUL_19_1875_FPLL +#endif +#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) +#define PLL0SEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define EOSC_8M (8000000UL) +#define EOSC_12M (12000000UL) +#define EOSC_16M (16000000UL) +#define EOSC_24M (24000000UL) +#define IOSC_10M (10000000UL) +#define EXTALH EOSC_12M /* External high-speed oscillator freq */ +#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ +#define EOSC_8M_DIV2_PLLON (192000000UL) /* 8.00MHz * 48.0000 / 2 */ +#define EOSC_12M_DIV2_PLLON (192000000UL) /* 12.00MHz * 32.0000 / 2 */ +#define EOSC_16M_DIV2_PLLON (192000000UL) /* 16.00MHz * 24.0000 / 2 */ +#define EOSC_24M_DIV2_PLLON (192000000UL) /* 24.00MHz * 16.0000 / 2 */ +#define IOSC_10M_DIV2_PLLON (191875000UL) /* 10.00MHz * 38.3750 / 2 */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ +#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ +#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = (warm-up time(us) * IXTALH - 16) / 16 */ +#if (CLOCK_SETUP) +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#else +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#endif + +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (CLOCK_SETUP) +#define CORE_TALH (EXTALH) +#else +#define CORE_TALH (IXTALH) +#endif + +#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ +#if (CORE_TALH == EOSC_8M) /* If input is 8MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_24_FPLL)) +#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 8MHz */ +#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL) +#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#elif (CORE_TALH == EOSC_16M) /* If input is 16MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL) +#define __CORE_CLK EOSC_16M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 16MHz */ +#elif (CORE_TALH == EOSC_24M) /* If input is 24MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL) +#define __CORE_CLK EOSC_24M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 24MHz */ +#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL) +#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 191.875MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 10MHz */ +#else /* input clock not known */ +#define __CORE_CLK (0U) +#error "Core Oscillator Frequency invalid!" +#endif /* End switch input clock */ +#else +#define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */ +#define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */ +#define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */ +#define __CORE_SYS (__CORE_CLK / 4U ) +#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */ +#define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */ +#define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ +#define __CORE_SYS (0U) +#endif + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ +uint32_t CoreClockInput = 0U; + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ + /* Get Core Clock Frequency */ + uint32_t CoreClock = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pll0sel = 0U; + uint32_t pll0on = 0U; + + CoreClockInput = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = IXTALH; + } + regval = TSB_CG->PLL0SEL; + pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; + pll0on = regval & CG_PLL0SEL_PLL0ON_SET; + if (pll0sel && pll0on) { /* If PLL enabled */ + if (CoreClock == EOSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_24_FPLL) { + CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL) { + CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_16M) { /* If input is 16MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL) { + CoreClockInput = EOSC_16M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_24M) { /* If input is 24MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL) { + CoreClockInput = EOSC_24M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL) { + CoreClockInput = IOSC_10M_DIV2_PLLON; /* output clock is 191.875MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { /* If PLL not used */ + CoreClockInput = CoreClock; + } + + switch (TSB_CG->SYSCR & 7U) { + case 0U: /* Gear -> fc */ + SystemCoreClock = CoreClockInput; + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + SystemCoreClock = CoreClockInput / 8U; + break; + case 4U: /* Gear -> fc/16 */ + SystemCoreClock = CoreClockInput / 16U; + break; + case 5U: + case 6U: + case 7U: + SystemCoreClock = 0U; + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ +#if (SIWD_SETUP) /* Watchdog Setup */ + /* SIWD Disable */ + TSB_SIWD0->EN = SIWDEN_Val; + TSB_SIWD0->CR = SIWDCR_Val; +#else + /* SIWD Enable (Setting after a Reset) */ +#endif +#if defined ( __CC_ARM ) + /* set Flash Access Control Register */ + Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API); /* copy flash API to RAM */ +#endif + fc_read_clock_set(__CORE_SYS); + fc_ram_con_reg_set(__CORE_SYS); + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = SYSCR_GEAR_Val; + + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET); + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + while (!TSB_CG_OSCCR_OSCF) { + ; + } /* Confirm CGOSCCR="1" */ + TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; +#else + /* Internal HOSC Enable (Setting after a Reset) */ +#endif + + TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set */ + while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val)) + != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) { + ; + } + + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLL0SEL_Ready; + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Lockup */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + while (!TSB_CG_PLL0SEL_PLL0ST) { + ; + } /*Confirm CGPLL0SEL = "1" */ +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.h new file mode 100644 index 0000000..d5c53b3 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/device/system_TMPM4Gx.h @@ -0,0 +1,67 @@ +/** + ***************************************************************************** + * @file system_TMPM4Gx.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4Gx' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM4Gx_H +#define __SYSTEM_TMPM4Gx_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CoreClockInput; /*!< High speed Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c new file mode 100644 index 0000000..5f78785 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/flash_api.c @@ -0,0 +1,130 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "flash_api.h" +#include "mbed_critical.h" +#include "txz_fc.h" + +#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once +#define SECTOR_SIZE (0x8000) // 32KB each sectors or block +#define FLASH_CHIP_SIZE (0x00200000) // Flash chip size is 2048 KByte +#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) + +#define SUCCESS (0U) +#define FAIL (-1) +// IHOSC1EN +#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask +#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable +#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable + +static void internal_hosc_enable(void); + +int32_t flash_init(flash_t *obj) +{ + obj->flash_inited = 0; + obj->flash_inited = 1; + internal_hosc_enable(); // Internal HOSC enable + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + obj->flash_inited = 0; + + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + int status = FAIL; + + if (obj->flash_inited == 0) { + flash_init(obj); + } + + // We need to prevent flash accesses during erase operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t *)address)) { + status = SUCCESS; + } else { + // Do nothing + } + + core_util_critical_section_exit(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int status = SUCCESS; + + address &= MASK_CHIP_ID_FROM_ADD; + + // We need to prevent flash accesses during program operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_write_code_flash((uint32_t *)data, (uint32_t *)address, size)) { + // Do nothing + } else { + status = FAIL; + } + + core_util_critical_section_exit(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { + return SECTOR_SIZE; + } else { + // Do nothing + } + + return MBED_FLASH_INVALID_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return PROGRAM_WRITE_MAX; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FC_CODE_FLASH_ADDRESS_TOP; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_CHIP_SIZE; +} + +static void internal_hosc_enable(void) +{ + uint32_t work; + work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); + TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c new file mode 100644 index 0000000..c031b49 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_api.c @@ -0,0 +1,127 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "txz_gpio.h" + +#define GPIO_DATA PIN_DATA(0, 2) +#define ALT_FUNC_GPIO 0 + +_gpio_t gpio_port_add = { + .p_pa_instance = TSB_PA, + .p_pb_instance = TSB_PB, + .p_pc_instance = TSB_PC, + .p_pd_instance = TSB_PD, + .p_pe_instance = TSB_PE, + .p_pf_instance = TSB_PF, + .p_pg_instance = TSB_PG, + .p_ph_instance = TSB_PH, + .p_pj_instance = TSB_PJ, + .p_pk_instance = TSB_PK, + .p_pl_instance = TSB_PL, + .p_pm_instance = TSB_PM, + .p_pn_instance = TSB_PN, + .p_pp_instance = TSB_PP, + .p_pr_instance = TSB_PR, + .p_pt_instance = TSB_PT, + .p_pu_instance = TSB_PU, + .p_pv_instance = TSB_PV, + .p_pw_instance = TSB_PW, + .p_py_instance = TSB_PY +}; + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + + // Return pin mask + return (1 << (pin & 0x07)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + obj->pin_num = PIN_POS(pin); + obj->mask = gpio_set(pin); + obj->port = (PortName) PIN_PORT(pin); + // Enable clock for particular port + TSB_CG->FSYSMENB |= (1 << ((obj->port) + 2)); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + // Set pin mode + pin_mode(obj->pin, mode); +} + +// Set gpio object pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INOUT); + break; + default: + break; + } +} + +void gpio_write(gpio_t *obj, int value) +{ + // Write gpio object pin data + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value); +} + +int gpio_read(gpio_t *obj) +{ + // Read gpio object pin data + gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable + gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val); + return val; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_irq_api.c new file mode 100644 index 0000000..ddbd7a2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_irq_api.c @@ -0,0 +1,297 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_critical.h" +#include "txz_gpio.h" + +#define CHANNEL_NUM (16) +#define DISABLE (0) +#define ENABLE (1) +#define CLR_INT_FLAG (0xC0) + +const PinMap PinMap_GPIO_IRQ[] = { + {PK7, GPIO_IRQ_0, PIN_DATA(0, 0)}, + {PL0, GPIO_IRQ_1, PIN_DATA(0, 0)}, + {PA0, GPIO_IRQ_2, PIN_DATA(0, 0)}, + {PA7, GPIO_IRQ_3, PIN_DATA(0, 0)}, + {PB0, GPIO_IRQ_4, PIN_DATA(0, 0)}, + {PB1, GPIO_IRQ_5, PIN_DATA(0, 0)}, + {PB6, GPIO_IRQ_6, PIN_DATA(0, 0)}, + {PB7, GPIO_IRQ_7, PIN_DATA(0, 0)}, + {PG0, GPIO_IRQ_8, PIN_DATA(0, 0)}, + {PG1, GPIO_IRQ_9, PIN_DATA(0, 0)}, + {PK0, GPIO_IRQ_A, PIN_DATA(0, 0)}, + {PK1, GPIO_IRQ_B, PIN_DATA(0, 0)}, + {PL4, GPIO_IRQ_C, PIN_DATA(0, 0)}, + {PL5, GPIO_IRQ_D, PIN_DATA(0, 0)}, + {PC6, GPIO_IRQ_E, PIN_DATA(0, 0)}, + {PC7, GPIO_IRQ_F, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +extern _gpio_t gpio_port_add; + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; +static CG_INTActiveState CurrentState; + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t); +static void INT_IRQHandler(PinName, uint32_t); + +void INT00_IRQHandler(void) +{ + INT_IRQHandler(PK7, 0); +} + +void INT01_IRQHandler(void) +{ + INT_IRQHandler(PL0, 1); +} + +void INT02_IRQHandler(void) +{ + INT_IRQHandler(PA0, 2); +} + +void INT03_IRQHandler(void) +{ + INT_IRQHandler(PA7, 3); +} + +void INT04_IRQHandler(void) +{ + INT_IRQHandler(PB0, 4); +} + +void INT05_IRQHandler(void) +{ + INT_IRQHandler(PB1, 5); +} + +void INT06_IRQHandler(void) +{ + INT_IRQHandler(PB6, 6); +} + +void INT07_IRQHandler(void) +{ + INT_IRQHandler(PB7, 7); +} + +void INT08_IRQHandler(void) +{ + INT_IRQHandler(PG0, 8); +} + +void INT09_IRQHandler(void) +{ + INT_IRQHandler(PG1, 9); +} + +void INT10_IRQHandler(void) +{ + INT_IRQHandler(PK0, 10); +} + +void INT11_IRQHandler(void) +{ + INT_IRQHandler(PK1, 11); +} + +void INT12_IRQHandler(void) +{ + INT_IRQHandler(PL4, 12); +} +void INT13_IRQHandler(void) +{ + INT_IRQHandler(PL5, 13); +} +void INT14_IRQHandler(void) +{ + INT_IRQHandler(PC6, 14); +} +void INT15_IRQHandler(void) +{ + INT_IRQHandler(PC7, 15); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t id) +{ + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + core_util_critical_section_enter(); + // Get GPIO port and pin num + obj->port = (PortName)PIN_PORT(pin); + obj->pin_num = PIN_POS(pin); + // Set pin level as LOW + gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0); + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + // Get GPIO irq source + obj->irq_src = (CG_INTSrc)obj->irq_id; + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + // Save irq id + channel_ids[obj->irq_src] = id; + // Initialize interrupt event as both edges detection + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + core_util_critical_section_exit(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_ids[obj->irq_src] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + // Disable GPIO interrupt on obj + gpio_irq_disable(obj); + + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else { + error("Not supported event\n"); + } + } + + CurrentState = obj->event; + if (obj->event != CG_INT_ACTIVE_STATE_INVALID) { + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0); + } else { + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1); + } + + // Clear interrupt request + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} + +static void INT_IRQHandler(PinName pin, uint32_t index) +{ + PortName port; + uint8_t pin_num; + + gpio_pinstate_t data = GPIO_PIN_RESET; + pin_num = PIN_POS(pin); + port = (PortName)PIN_PORT(pin); + + // Clear interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE); + // Get pin value + gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data); + + switch (data) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_ids[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_ids[index], IRQ_RISE); + break; + default: + break; + } + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index)); + // Enable interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE); +} + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState) +{ + uint8_t *ptr = NULL; + if ((INTSource == 12) || (INTSource == 13)) { + ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2) + 1); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else { + ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2)); + // Clear pending falling and rising edge bit + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } + { + uint8_t regval = *ptr; + (void)regval; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_object.h new file mode 100644 index 0000000..284f901 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/gpio_object.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t pin_num; + uint32_t mask; + PinName pin; + PortName port; +} gpio_t; + +typedef enum { + CG_INT_SRC_0 = 0U, + CG_INT_SRC_1, + CG_INT_SRC_2, + CG_INT_SRC_3, + CG_INT_SRC_4, + CG_INT_SRC_5, + CG_INT_SRC_6, + CG_INT_SRC_7, + CG_INT_SRC_8, + CG_INT_SRC_9, + CG_INT_SRC_A, + CG_INT_SRC_B, + CG_INT_SRC_C, + CG_INT_SRC_D, + CG_INT_SRC_E, + CG_INT_SRC_F +} CG_INTSrc; + +typedef enum { + CG_INT_ACTIVE_STATE_L = 0x00U, + CG_INT_ACTIVE_STATE_H = 0x02U, + CG_INT_ACTIVE_STATE_FALLING = 0x04U, + CG_INT_ACTIVE_STATE_RISING = 0x06U, + CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, + CG_INT_ACTIVE_STATE_INVALID = 0x0AU +} CG_INTActiveState; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName)NC); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c new file mode 100644 index 0000000..32f333e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/i2c_api.c @@ -0,0 +1,308 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" + +#if DEVICE_I2C + +#include +#include +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "txz_i2c_api.h" + +#define MAX_I2C_FREQ 1000000 +#define I2C_TRANSFER_STATE_IDLE (0x0U) + +#if DEVICE_I2C_ASYNCH +#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) +#else +#define I2C_S(obj) (struct i2c_s *) (obj) +#endif + +static const PinMap PinMap_I2C_SDA[] = { + {PG2, I2C_0, PIN_DATA(7, 2)}, + {PF2, I2C_1, PIN_DATA(7, 2)}, + {PG4, I2C_2, PIN_DATA(7, 2)}, + {PJ6, I2C_3, PIN_DATA(7, 2)}, + {PJ3, I2C_4, PIN_DATA(7, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PG3, I2C_0, PIN_DATA(7, 2)}, + {PF3, I2C_1, PIN_DATA(7, 2)}, + {PG5, I2C_2, PIN_DATA(7, 2)}, + {PJ7, I2C_3, PIN_DATA(7, 2)}, + {PJ2, I2C_4, PIN_DATA(7, 2)}, + {NC, NC, 0} +}; + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + struct i2c_s *obj_s = I2C_S(obj); + MBED_ASSERT(obj_s != NULL); + + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + + MBED_ASSERT((int)i2c_name != NC); + obj_s->index = i2c_name; + obj_s->is_master = 1; + + switch (i2c_name) { + case I2C_0: + TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE; // Enable clock for I2C_0 + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; // Enable clock for GPIO G + obj_s->my_i2c.i2c.p_instance = TSB_I2C0; + obj_s->irqn = INTI2C0NST_IRQn; + break; + case I2C_1: + TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; // Enable clock for I2C_1 + TSB_CG_FSYSMENB_IPMENB07 = TXZ_ENABLE; // Enable clock for GPIO F + obj_s->my_i2c.i2c.p_instance = TSB_I2C1; + obj_s->irqn = INTI2C1NST_IRQn; + break; + case I2C_2: + TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; // Enable clock for I2C_2 + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; // Enable clock for GPIO G + obj_s->my_i2c.i2c.p_instance = TSB_I2C2; + obj_s->irqn = INTI2C2NST_IRQn; + break; + case I2C_3: + TSB_CG_FSYSMENB_IPMENB00 = TXZ_ENABLE; // Enable clock for I2C_3 + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J + obj_s->my_i2c.i2c.p_instance = TSB_I2C3; + obj_s->irqn = INTI2C3NST_IRQn; + break; + case I2C_4: + TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; // Enable clock for I2C_4 + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J + obj_s->my_i2c.i2c.p_instance = TSB_I2C4; + obj_s->irqn = INTI2C3NST_IRQn; + break; + default: + error("I2C is not available"); + break; + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + i2c_reset(obj); + i2c_frequency(obj, 100000); + I2C_init(&obj_s->my_i2c.i2c); +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + struct i2c_s *obj_s = I2C_S(obj); + + if (hz > MAX_I2C_FREQ) { + error("Failed : Max I2C frequency is 1000000"); + } + + i2c_frequency_t(&obj_s->my_i2c, hz); + + if (obj_s->is_master) { + I2C_init(&obj_s->my_i2c.i2c); + } else { + I2C_slave_init(&obj_s->my_i2c.i2c); + } +} + +int i2c_start(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_start_t(&obj_s->my_i2c); + + return TXZ_SUCCESS; +} + +int i2c_stop(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_stop_t(&obj_s->my_i2c); + + return TXZ_SUCCESS; +} + +void i2c_reset(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + // Software reset + i2c_reset_t(&obj_s->my_i2c); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_read_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_write_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t data = 0; + struct i2c_s *obj_s = I2C_S(obj); + + data = i2c_byte_read_t(&obj_s->my_i2c, last); + + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result = 0; + struct i2c_s *obj_s = I2C_S(obj); + + result = i2c_byte_write_t(&obj_s->my_i2c, data); + + return result; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + struct i2c_s *obj_s = I2C_S(obj); + + obj_s->is_master = 0; + i2c_slave_mode_t(&obj_s->my_i2c, enable_slave); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_slave_address_t(&obj_s->my_i2c, address); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = 0; + struct i2c_s *obj_s = I2C_S(obj); + + result = i2c_slave_receive_t(&obj_s->my_i2c); + + return result; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_slave_read_t(&obj_s->my_i2c, (uint8_t *)data, length); + + return count; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_slave_write_t(&obj_s->my_i2c, (uint8_t *)data, length); + + return count; +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if DEVICE_I2C_ASYNCH + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, + uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct i2c_s *obj_s = I2C_S(obj); + + obj_s->event_mask = event; + //Set irqn table for future use + set_i2c(obj_s->index, &obj_s->my_i2c.info.irqn); + NVIC_SetVector(obj_s->irqn, handler); + i2c_transfer_asynch_t(&obj_s->my_i2c, (uint8_t *)tx, tx_length, (uint8_t *)rx, rx_length, address, stop); +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + uint32_t event = 0; + + event = i2c_irq_handler_asynch_t(&obj_s->my_i2c); + + return (event & obj_s->event_mask); +} + +uint8_t i2c_active(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + uint8_t ret = (obj_s->my_i2c.info.asynch.state != I2C_TRANSFER_STATE_IDLE); + + return ret; +} + +void i2c_abort_asynch(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_abort_asynch_t(&obj_s->my_i2c); +} + +#endif // #if DEVICE_I2C_ASYNCH + +#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h new file mode 100644 index 0000000..921a9b9 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/objects.h @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "PortNames.h" +#include "PeripheralNames.h" +#include "gpio_object.h" +#include "txz_uart.h" +#include "txz_fuart.h" +#include "txz_tspi.h" +#include "txz_t32a.h" +#include "txz_cg.h" +#include "txz_driver_def.h" +#include "txz_adc.h" +#include "txz_i2c_api.h" +#include "txz_i2c.h" +#include "txz_fuart_include.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + uint32_t mask; + PortName port; +}; + +struct dac_s { + DACName dac; + TSB_DA_TypeDef *DACx; +}; + +typedef struct { + uint32_t BaudRate; + uint32_t DataBits; + uint32_t StopBits; + uint32_t Parity; + uint32_t Mode; + uint32_t FlowCtrl; +} FUART_InitTypeDef; + +struct serial_s { + uint32_t index; + uint32_t mode; + uint8_t is_using_fuart; + TSB_UART_TypeDef *UARTx; + TSB_FURT_TypeDef *FUARTx; + uart_boudrate_t boud_obj; + fuart_boudrate_t boudrate; + FUART_InitTypeDef fuart_config; +}; + +struct pwmout_s { + uint32_t divisor; + uint32_t type; + uint32_t trailing_timing; + uint32_t leading_timing; + float period; + t32a_t p_t32a; + PinName pin; +}; + +struct spi_s { + tspi_t p_obj; + SPIName module; + uint8_t bits; + PinName Slave_SCK; +#if DEVICE_SPI_ASYNCH + uint32_t irqn; + uint32_t event; + uint32_t max_size; + uint32_t state; +#endif +}; + +struct gpio_irq_s { + PortName port; + uint8_t pin_num; + uint32_t irq_id; + CG_INTSrc irq_src; + CG_INTActiveState event; +}; + +struct flash_s { + int flash_inited; +}; + +struct analogin_s { + adc_t p_adc; + PinName pin; + ADCName adc; + adc_channel_setting_t param; +}; + +struct i2c_s { + uint8_t is_master; + uint32_t index; + IRQn_Type irqn; + _i2c_t my_i2c; +#if DEVICE_I2C_ASYNCH + uint32_t event_mask; +#endif +}; + + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c new file mode 100644 index 0000000..bf96387 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pinmap.c @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "txz_gpio.h" + +#define PIN_FUNC_MAX 8 + +extern _gpio_t gpio_port_add; + +void pin_function(PinName pin, int function) +{ + uint32_t port = 0; + uint8_t bit = 0; + uint8_t func = 0; + uint8_t dir = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Calculate pin function and pin direction + func = PIN_FUNC(function); + dir = PIN_DIR(function); + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Find function is in range or not + if (func <= PIN_FUNC_MAX) { + // Set pin function and direction if direction is in range + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT); + break; + default: + break; + } + } else { + // Do nothing + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + uint32_t port = 0; + uint8_t bit = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Check if function is in range + if (mode > OpenDrain) { + return; + } + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Set pin mode + switch (mode) { + case PullNone: + gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + break; + case PullUp: + gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + case PullDown: + gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + case OpenDrain: + gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + default: + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c new file mode 100644 index 0000000..4aaff9b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/port_api.c @@ -0,0 +1,144 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "txz_gpio.h" +#include "pinmap.h" + +#define PORT_PIN_NUM (8) +#define ALT_FUNC_GPIO (0) + +extern _gpio_t gpio_port_add; +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num); + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName)((port << 3) | pin_n); + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortY); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + + // Enable the clock for particular port + _gpio_init(&gpio_port_add, obj->port); + + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + for (i = 0; i < PORT_PIN_NUM; i++) { + // Set direction for masked pins + if (obj->mask & (1 << i)) { + gpio_pin_dir(obj, dir, i); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + + // Write data to masked pins of the port + gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data); +} + +int port_read(port_t *obj) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data of masked pins + data = port_data & obj->mask; + + return data; +} + +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num) +{ + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT); + break; + default: + // error("Invalid direction\n"); + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pwmout_api.c new file mode 100644 index 0000000..b4fdfa3 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/pwmout_api.c @@ -0,0 +1,240 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define GPIO_CLK_OFFSET 2 +#define CALCULATE_RGC1_VAL 2.95 + +static const PinMap PinMap_PWM[] = { + {PA5, PWM_0, PIN_DATA(5, 1)}, + {PB2, PWM_1, PIN_DATA(5, 1)}, + {PB4, PWM_2, PIN_DATA(5, 1)}, + {PD2, PWM_3, PIN_DATA(5, 1)}, + {PD4, PWM_4, PIN_DATA(5, 1)}, + {PE1, PWM_5, PIN_DATA(5, 1)}, + {PE6, PWM_6, PIN_DATA(5, 1)}, + {PC2, PWM_7, PIN_DATA(5, 1)}, + {PL6, PWM_8, PIN_DATA(3, 1)}, + {PC4, PWM_9, PIN_DATA(5, 1)}, + {PM2, PWM_10, PIN_DATA(3, 1)}, + {PU0, PWM_11, PIN_DATA(3, 1)}, + {PU6, PWM_12, PIN_DATA(3, 1)}, + {NC, NC, 0} +}; + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + // Determine the pwm channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + + // Assert input is valid + MBED_ASSERT(pwm != (PWMName)NC); + + switch (pwm) { + case PWM_0: + obj->p_t32a.p_instance = TSB_T32A1; + // Clock enable of T32A ch01 + TSB_CG_FSYSMENA_IPMENA07 = TXZ_ENABLE; + break; + case PWM_1: + obj->p_t32a.p_instance = TSB_T32A2; + // Clock enable of T32A ch02 + TSB_CG_FSYSMENA_IPMENA08 = TXZ_ENABLE; + break; + case PWM_2: + obj->p_t32a.p_instance = TSB_T32A3; + // Clock enable of T32A ch03 + TSB_CG_FSYSMENA_IPMENA09 = TXZ_ENABLE; + break; + case PWM_3: + obj->p_t32a.p_instance = TSB_T32A4; + // Clock enable of T32A ch04 + TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE; + break; + case PWM_4: + obj->p_t32a.p_instance = TSB_T32A5; + // Clock enable of T32A ch05 + TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE; + break; + case PWM_5: + obj->p_t32a.p_instance = TSB_T32A6; + // Clock enable of T32A ch06 + TSB_CG_FSYSMENA_IPMENA12 = TXZ_ENABLE; + break; + case PWM_6: + obj->p_t32a.p_instance = TSB_T32A7; + // Clock enable of T32A ch07 + TSB_CG_FSYSMENA_IPMENA13 = TXZ_ENABLE; + break; + case PWM_7: + obj->p_t32a.p_instance = TSB_T32A8; + // Clock enable of T32A ch08 + TSB_CG_FSYSMENA_IPMENA14 = TXZ_ENABLE; + break; + case PWM_8: + obj->p_t32a.p_instance = TSB_T32A9; + // Clock enable of T32A ch09 + TSB_CG_FSYSMENA_IPMENA15 = TXZ_ENABLE; + break; + case PWM_9: + obj->p_t32a.p_instance = TSB_T32A10; + // Clock enable of T32A ch10 + TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE; + break; + case PWM_10: + obj->p_t32a.p_instance = TSB_T32A11; + // Clock enable of T32A ch11 + TSB_CG_FSYSMENA_IPMENA17 = TXZ_ENABLE; + break; + case PWM_11: + obj->p_t32a.p_instance = TSB_T32A12; + // Clock enable of T32A ch12 + TSB_CG_FSYSMENA_IPMENA18 = TXZ_ENABLE; + break; + case PWM_12: + obj->p_t32a.p_instance = TSB_T32A13; + // Clock enable of T32A ch13 + TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE; + break; + default: + obj->p_t32a.p_instance = NULL; + break; + } + + if (obj->p_t32a.p_instance == NULL) { + return; + } + + // Enable clock for GPIO port. + TSB_CG->FSYSMENB |= (TXZ_ENABLE << ((PIN_PORT(pin)) + GPIO_CLK_OFFSET)); + + // Set pin function as PWM + pinmap_pinout(pin, PinMap_PWM); + + // Default to 20ms, 0% duty cycle + pwmout_period_ms(obj, 20); +} + +void pwmout_free(pwmout_t *obj) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + obj->trailing_timing = TXZ_DISABLE; + obj->leading_timing = TXZ_DISABLE; + obj->p_t32a.p_instance = NULL; +} + +void pwmout_write(pwmout_t *obj, float value) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + + if (value <= 0.0f) { + value = TXZ_DISABLE; + } else if (value >= 1.0f) { + value = TXZ_ENABLE; + } + + // Store the new leading_timing value + obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value); + + // Setting T32A_RGA0 register + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + + // Start PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +float pwmout_read(pwmout_t *obj) +{ + float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + return duty_cycle; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, (ms * 1000)); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t *obj, int us) +{ + uint32_t prscl = 0; + float duty_cycle = 0; + float seconds = (float)((us) / 1000000.0f); + + obj->period = seconds; + // Restore the duty-cycle + duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + prscl = T32A_PRSCLx_32; + + obj->trailing_timing = (us * CALCULATE_RGC1_VAL); + obj->leading_timing = ((obj->trailing_timing) - (obj->trailing_timing * duty_cycle)); + + obj->p_t32a.p_instance->MOD = T32A_MODE_32; + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx); + obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ | + T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ); + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + obj->p_t32a.p_instance->RGC1 = obj->trailing_timing; + obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE; + obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET); + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->trailing_timing; +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (seconds * 1000000.0f)); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, (ms * 1000)); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + float seconds = 0; + float value = 0; + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + pwmout_write(obj, value); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) +{ + return obj->trailing_timing - obj->leading_timing; +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/reset_reason_api.c new file mode 100644 index 0000000..040a86a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/reset_reason_api.c @@ -0,0 +1,132 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "reset_reason_api.h" + +#ifdef DEVICE_RESET_REASON + +#include "TMPM4GR.h" +#include + +static uint8_t set_bit_count(uint32_t reg); + +typedef enum { + POWER_ON_BIT_POS = 1 << 0, + PIN_RESET_BIT_POS = 1 << 3, + LOW_POWER_BIT_POS = 1 << 4, + BROWN_OUT_BIT_POS = 1 << 5, +} reason_flag0; + +typedef enum { + SOFTWARE_BIT_POS = 1 << 0, + LOCK_BIT_POS = 1 << 1, + WATCHDOG_BIT_POS = 1 << 2, + PLATFORM_BIT_POS = 1 << 3, +} reason_flag1; + +void hal_reset_reason_clear(void) +{ + TSB_RLM->RSTFLG0 = 0; + TSB_RLM->RSTFLG1 = 0; +} + +uint32_t hal_reset_reason_get_raw(void) +{ + uint32_t ret = 0; + + ret = (((TSB_RLM->RSTFLG1 & 0xFF) << 8) | (TSB_RLM->RSTFLG0 & 0xFF)); + + return ret; +} + +reset_reason_t hal_reset_reason_get(void) +{ + reset_reason_t ret; + + uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_RLM->RSTFLG0); + uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_RLM->RSTFLG1); + + if (NoOfSetBitCountReg1 != 0x00) { + if (NoOfSetBitCountReg1 > 0x01) { + ret = RESET_REASON_MULTIPLE; + } else { + if (TSB_RLM->RSTFLG0 & POWER_ON_BIT_POS) { + ret = RESET_REASON_POWER_ON; + } else if (TSB_RLM->RSTFLG0 & PIN_RESET_BIT_POS) { + ret = RESET_REASON_PIN_RESET; + } else if (TSB_RLM->RSTFLG0 & LOW_POWER_BIT_POS) { + ret = RESET_REASON_WAKE_LOW_POWER; + } else if (TSB_RLM->RSTFLG0 & BROWN_OUT_BIT_POS) { + ret = RESET_REASON_BROWN_OUT; + } else { + ret = RESET_REASON_UNKNOWN; + } + } + } else if (NoOfSetBitCountReg2 != 0x00) { + if (NoOfSetBitCountReg2 > 0x01) { + ret = RESET_REASON_MULTIPLE; + } else { + if (TSB_RLM->RSTFLG1 & SOFTWARE_BIT_POS) { + ret = RESET_REASON_SOFTWARE; + } else if (TSB_RLM->RSTFLG1 & LOCK_BIT_POS) { + ret = RESET_REASON_LOCKUP; + } else if (TSB_RLM->RSTFLG1 & WATCHDOG_BIT_POS) { + ret = RESET_REASON_WATCHDOG; + } else if (TSB_RLM->RSTFLG1 & PLATFORM_BIT_POS) { + ret = RESET_REASON_PLATFORM; + } else { + ret = RESET_REASON_UNKNOWN; + } + } + } else { + ret = RESET_REASON_UNKNOWN; + } + + return ret; +} + +void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) +{ + cap->reasons = 1 << RESET_REASON_UNKNOWN; + cap->reasons |= 1 << RESET_REASON_POWER_ON; + cap->reasons |= 1 << RESET_REASON_PIN_RESET; + cap->reasons |= 1 << RESET_REASON_WAKE_LOW_POWER; + cap->reasons |= 1 << RESET_REASON_BROWN_OUT; + cap->reasons |= 1 << RESET_REASON_SOFTWARE; + cap->reasons |= 1 << RESET_REASON_LOCKUP; + cap->reasons |= 1 << RESET_REASON_WATCHDOG; + cap->reasons |= 1 << RESET_REASON_PLATFORM; + cap->reasons |= 1 << RESET_REASON_MULTIPLE; + +} + +static uint8_t set_bit_count(uint32_t reg) +{ + uint8_t count = 0; + uint8_t index = 0; + + for (index = 0; index < (sizeof(uint32_t) * 8); index++) { + if (reg & (1 << index)) { + count++; + if (count > 0x01) { + break; + } + } + } + + return count; +} + +#endif // DEVICE_RESET_REASON diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c new file mode 100644 index 0000000..7255dcb --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/rtc_api.c @@ -0,0 +1,241 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" +#include "mbed_mktime.h" + +#define RTC_24_HOUR_MODE ((uint8_t)0x01) +#define PAGER_PAGE_ONE ((uint8_t)0x01) +#define PAGER_PAGE_ZERO ((uint8_t)0xEE) +#define RTC_CLK_ENABLE ((uint8_t)0x08) +#define RTC_CLK_DISABLE ((uint8_t)0xE7) +#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) +#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) +#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) +#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) +#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) +#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) +#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) +#define RLMLOSCCR_DRCOSCL_RW_ENABLE ((uint32_t)0x00000004) +#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) +#define ELOSC_CFG_CLOCK ((uint64_t)(32768)) +#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro +#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro + +static int rtc_inited = 0; +static int diff_year = 100; //our RTC register only support 2000~2099 +static void external_losc_enable(void); + +void rtc_init(void) +{ + if (!rtc_inited) { + external_losc_enable(); // Enable low-speed oscillator + TSB_RTC->PAGER = 0x00; // Disable clock and alarm + while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { + // Reset RTC sec counter + } + + TSB_RTC->RESTR = 0xE7; + while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { + // Reset RTC sec counter + } + + TSB_RTC->PAGER |= PAGER_PAGE_ONE; + TSB_RTC->YEARR = 0x03; // Set leap year state + TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode + TSB_RTC->YEARR = 0x01; // Set year value + TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value + TSB_RTC->DATER = (uint8_t)0x01; // Set date value + TSB_RTC->DAYR = (uint8_t)0x0; // Set day value + TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value + TSB_RTC->MINR = (uint8_t)0x02; // Set minute value + TSB_RTC->SECR = (uint8_t)0x22; // Set second value + TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock + rtc_inited = 1; // Enable RTC initialzed status + } +} + +void rtc_free(void) +{ + rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE +} + +int rtc_isenabled(void) +{ + return rtc_inited; // Return status of RTC peripheral driver +} + +time_t rtc_read(void) +{ + if (!rtc_inited) { + // Return invalid time for now! + return 0; + } + + struct tm timeinfo; + uint8_t read_1 = 0U; + uint8_t read_2 = 0U; + + timeinfo.tm_isdst = 0; //no summer time + + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; + + read_1 = TSB_RTC->SECR; // Get sec value + timeinfo.tm_sec = HEX2DEC(read_1); + + // Get minute value + do { + read_1 = TSB_RTC->MINR; + read_2 = TSB_RTC->MINR; + } while (read_1 != read_2); + timeinfo.tm_min = HEX2DEC(read_1); + + // Get hour value + do { + read_1 = TSB_RTC->HOURR; + read_2 = TSB_RTC->HOURR; + } while (read_1 != read_2); + timeinfo.tm_hour = HEX2DEC(read_1); + + // Get Month date value + do { + read_1 = TSB_RTC->DATER; + read_2 = TSB_RTC->DATER; + } while (read_1 != read_2); + timeinfo.tm_mday = HEX2DEC(read_1); + + // Get Month value + do { + read_1 = TSB_RTC->MONTHR; + read_2 = TSB_RTC->MONTHR; + } while (read_1 != read_2); + timeinfo.tm_mon = HEX2DEC(read_1) - 1; + + // Get weekday value + do { + read_1 = TSB_RTC->DAYR; + read_2 = TSB_RTC->DAYR; + } while (read_1 != read_2); + timeinfo.tm_wday = HEX2DEC(read_1); + + // Get year value + do { + read_1 = TSB_RTC->YEARR; + read_2 = TSB_RTC->YEARR; + } while (read_1 != read_2); + timeinfo.tm_year = (HEX2DEC(read_1) + diff_year); + + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } + return t; +} + +void rtc_write(time_t t) +{ + if (!rtc_inited) { + // Initialize the RTC as not yet initialized + rtc_init(); + } + + struct tm timeinfo; + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return; + } + + diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100); + TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock + + // Check current year is leap year or not + if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) || + (timeinfo.tm_year % 400) == 0) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year + TSB_RTC->YEARR = 0x00; + } else if ((timeinfo.tm_year % 4) == 1) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year + TSB_RTC->YEARR = 0x01; + } else if ((timeinfo.tm_year % 4) == 2) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year + TSB_RTC->YEARR = 0x02; + } else { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year + TSB_RTC->YEARR = 0x03; + } + + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0 + + TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value + + // Set month value, tm_mon=0 means Jan while 1 is Jan + TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon + 1)); + TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value + TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value + TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value + TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value + TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value + + // Setting Wait + // When stop mode is selected, CaseA or CaseB is need. + // CaseA: Wait for RTC 1Hz interrupt. + // CaseB: Check the clock register setting. + { + uint8_t flag = 1; + time_t time_read = {0}; + while (flag) { + time_read = rtc_read(); + if (time_read == t) { // Wait for setting successfully + flag = 0; + } + } + } + TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock +} + +static void external_losc_enable(void) +{ + uint32_t work; + + // [CGWUPLCR] :Warm up time + //-------------------------------------- + // "1"counter (s) = 1 / ELOSC + // "1"counter (us) = (10^6) / ELOSC + // "x"counter (us) = time + //-------------------------------------- + // x : time = 1 : (10^6) / ELOSC + //-------------------------------------- + { + uint64_t x = (uint64_t)((uint64_t)(ELOSC_CFG_WARM_UP_TIME) * (uint64_t)(ELOSC_CFG_CLOCK)); + x = (uint64_t)(x / (uint64_t)(1000000)); + if (x > (uint64_t)(0x7FFFF)) { + /* invalid value */ + } + work = (uint32_t)x; + } + work &= (uint32_t)(0xFFFFFFF0); + work <<= 8; + TSB_CG->WUPLCR = work; + // [RLMLOSCCR] :LOSC Enable + TSB_RLM->LOSCCR = RLMLOSCCR_DRCOSCL_RW_ENABLE | RLMLOSCCR_XTEN_RW_ENABLE; + // [CGWUPLCR] :Enable + work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK); + TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE); + // [CGWUPLCR] :Read(wait for warm-up) + while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) { + // no processing + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/serial_api.c new file mode 100644 index 0000000..a31c745 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/serial_api.c @@ -0,0 +1,725 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_error.h" +#include "serial_api.h" +#include "pinmap.h" + +#define UART_NUM 8 +#define UART_ENABLE_RX ((uint32_t)0x00000001) +#define UART_ENABLE_TX ((uint32_t)0x00000002) +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) +#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) +#define LCR_H_WLEN_MASK ((uint32_t)0xFFFFFF9F) +#define LCR_H_STP2_MASK ((uint32_t)0xFFFFFFF7) +#define LCR_H_PARITY_MASK ((uint32_t)0xFFFFFF79) +#define CR_FLOW_CTRL_MASK ((uint32_t)0x00000F07) +#define CR_MODE_MASK ((uint32_t)0x0000CC07) +#define FUARTxCR_UARTEN_ENABLE_CLEAR ((uint32_t)0xFFFFFF7E) +#define FUART_CTS_RTS_DISABLE_MASK ((uint32_t)0XFFFF3FFF) +#define BAUDRATE_DEFAULT (9600) +#define CLR_REGISTER (0x00) +#define IMSC_TXIM_RXIM_MASK ((uint32_t)0X000007C0) +#define IMSC_RXIM_CLEAR ((uint32_t)0X000007E0) +#define IMSC_TXIM_CLEAR ((uint32_t)0X000007D0) + +static const PinMap PinMap_UART_TX[] = { + {PE3, SERIAL_0, PIN_DATA(7, 1)}, + {PH1, SERIAL_1, PIN_DATA(3, 1)}, + {PG1, SERIAL_2, PIN_DATA(3, 1)}, + {PU7, SERIAL_3, PIN_DATA(7, 1)}, + {PU0, SERIAL_4, PIN_DATA(7, 1)}, + {PJ1, SERIAL_5, PIN_DATA(3, 1)}, + {PG4, SERIAL_6, PIN_DATA(5, 1)}, + {PM7, SERIAL_7, PIN_DATA(7, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PE2, SERIAL_0, PIN_DATA(7, 0)}, + {PH0, SERIAL_1, PIN_DATA(3, 0)}, + {PG0, SERIAL_2, PIN_DATA(3, 0)}, + {PU6, SERIAL_3, PIN_DATA(7, 0)}, + {PU1, SERIAL_4, PIN_DATA(7, 0)}, + {PJ0, SERIAL_5, PIN_DATA(3, 0)}, + {PG5, SERIAL_6, PIN_DATA(5, 0)}, + {PM6, SERIAL_7, PIN_DATA(7, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RTS[] = { + {PE0, SERIAL_0, PIN_DATA(7, 1)}, + {PH2, SERIAL_1, PIN_DATA(3, 1)}, + {PG2, SERIAL_2, PIN_DATA(3, 1)}, + {PU4, SERIAL_3, PIN_DATA(7, 1)}, + {PU3, SERIAL_4, PIN_DATA(5, 1)}, + {PJ2, SERIAL_5, PIN_DATA(3, 1)}, + {PG6, SERIAL_6, PIN_DATA(5, 1)}, + {PM5, SERIAL_7, PIN_DATA(7, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_CTS[] = { + {PE1, SERIAL_0, PIN_DATA(7, 0)}, + {PH3, SERIAL_1, PIN_DATA(3, 0)}, + {PG3, SERIAL_2, PIN_DATA(3, 0)}, + {PU5, SERIAL_3, PIN_DATA(7, 0)}, + {PU2, SERIAL_4, PIN_DATA(5, 0)}, + {PJ3, SERIAL_5, PIN_DATA(3, 0)}, + {PG7, SERIAL_6, PIN_DATA(5, 0)}, + {PM4, SERIAL_7, PIN_DATA(7, 0)}, + {NC, NC, 0} +}; + +static int serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +static void uart_swreset(TSB_UART_TypeDef *UARTx); +static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + obj->mode = 0; + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal = {0}; + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT((int)uart_name != NC); + + obj->is_using_fuart = 0; + obj->index = uart_name; + // Initialize UART instance + switch (uart_name) { + case SERIAL_0: + obj->UARTx = TSB_UART0; + // Enable clock for UART0 and Port E + TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB06 = TXZ_ENABLE; + break; + case SERIAL_1: + obj->UARTx = TSB_UART1; + // Enable clock for UART1 and Port H + TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB09 = TXZ_ENABLE; + break; + case SERIAL_2: + obj->UARTx = TSB_UART2; + // Enable clock for UART2 and Port G + TSB_CG_FSYSMENA_IPMENA25 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; + break; + case SERIAL_3: + obj->UARTx = TSB_UART3; + // Enable clock for UART3 and Port U + TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; + break; + case SERIAL_4: + obj->UARTx = TSB_UART4; + // Enable clock for UART4 and Port U + TSB_CG_FSYSMENA_IPMENA27 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB18 = TXZ_ENABLE; + break; + case SERIAL_5: + obj->UARTx = TSB_UART5; + // Enable clock for UART5 and Port J + TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; + break; + case SERIAL_6: + obj->FUARTx = TSB_FURT0; + //Enable clock for UART6 and Port G + TSB_CG_FSYSMENA_IPMENA01 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB08 = TXZ_ENABLE; + obj->is_using_fuart = 1; + break; + case SERIAL_7: + obj->FUARTx = TSB_FURT1; + //Enable clock for UART7 and Port M + TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; + obj->is_using_fuart = 1; + break; + default: + break; + } + + // Set alternate function + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (!(obj->is_using_fuart)) { + if (tx != NC && rx != NC) { + obj->mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->mode = UART_ENABLE_RX; + } + } + } + //software reset + uart_swreset(obj->UARTx); + //mbed default configurations + obj->UARTx->CR0 |= (1U); // data lengh 8 bit No parity one stop bit + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj); + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); + obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO + obj->UARTx->TRANS |= obj->mode; // Enable TX RX block. + obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); + } else { + if (tx != NC && rx != NC) { + obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE | FUARTxCR_RXE_ENABLE; + } else if (tx != NC) { + obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE; + } else if (rx != NC) { + obj->fuart_config.Mode = FUARTxCR_RXE_ENABLE; + } + + obj->fuart_config.BaudRate = BAUDRATE_DEFAULT; + obj->fuart_config.DataBits = FUART_DATA_LENGTH_8; + obj->fuart_config.StopBits = FUART_STOP_BIT_1; + obj->fuart_config.Parity = FUART_PARITY_DISABLE; + obj->fuart_config.FlowCtrl = FUART_CTS_DISABLE | FUART_RTS_DISABLE; + + fuart_get_boudrate_setting(cg_get_mphyt0(¶mCG), obj->fuart_config.BaudRate, &obj->boudrate); + + fuart_init_config(obj, &obj->fuart_config); + //Enable FUART + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } + + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS = CLR_REGISTER; + obj->UARTx->CR0 = CLR_REGISTER; + obj->UARTx->CR1 = CLR_REGISTER; + obj->UARTx = CLR_REGISTER; + uart_swreset(obj->UARTx); + } else { + obj->FUARTx->CR = CLR_REGISTER; + obj->FUARTx->IMSC = CLR_REGISTER; + obj->FUARTx->ICR = CLR_REGISTER; + obj->FUARTx->LCR_H = CLR_REGISTER; + obj->FUARTx = CLR_REGISTER; + } + obj->index = (uint32_t)NC; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal; + if (!(obj->is_using_fuart)) { + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj); + obj->UARTx->BRD = CLR_REGISTER; //clear BRD register + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); + } else { + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; + obj->fuart_config.BaudRate = baudrate; + fuart_get_boudrate_setting(cg_get_mphyt0(¶mCG), obj->fuart_config.BaudRate, &obj->boudrate); + fuart_init_config(obj, &obj->fuart_config); + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + + } +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint32_t parity_check = 0; + uint32_t data_length = 0; + uint32_t tmp = 0; + uint32_t sblen = 0; + + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + + if (!(obj->is_using_fuart)) { + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits + parity_check = ((parity == ParityOdd) ? 1 : ((parity == ParityEven) ? 3 : 0)); + data_length = (data_bits == 8 ? 1 : ((data_bits == 7) ? 0 : 2)); + sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits + tmp = ((sblen << 4) | (parity_check << 2) | data_length); + obj->UARTx->CR0 = tmp; + } else { + MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; + // Parity bit update + if (parity == ParityOdd) { + obj->fuart_config.Parity = FUART_PARITY_BIT_ODD | FUART_PARITY_ENABLE; + } else if (parity == ParityEven) { + obj->fuart_config.Parity = FUART_PARITY_BIT_EVEN | FUART_PARITY_ENABLE; + } else { + obj->fuart_config.Parity = FUART_PARITY_DISABLE; + } + // Stop bit update + obj->fuart_config.StopBits = (stop_bits == 1) ? FUART_STOP_BIT_1 : FUART_STOP_BIT_2; + // Data length update + obj->fuart_config.DataBits = (data_bits == 7) ? FUART_DATA_LENGTH_7 : FUART_DATA_LENGTH_8; + + fuart_init_config(obj, &obj->fuart_config); + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } +} + +// INTERRUPT HANDLING +void INTUART0RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], RxIrq); +} + +void INTUART0TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], TxIrq); +} + +void INTUART1RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], RxIrq); +} + +void INTUART1TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], TxIrq); +} + +void INTUART2RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], RxIrq); +} + +void INTUART2TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], TxIrq); +} + +void INTUART3RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], RxIrq); +} + +void INTUART3TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], TxIrq); +} + +void INTUART4RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_4], RxIrq); +} + +void INTUART4TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_4], TxIrq); +} + +void INTUART5RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_5], RxIrq); +} + +void INTUART5TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_5], TxIrq); +} + +void INTFUART0_IRQHandler(void) +{ + uint32_t int_status; + + int_status = TSB_FURT0->MIS; + if (int_status & (1 << 4U)) { + TSB_FURT0->ICR = int_status & FUARTxMIS_RXMIS_MASK; + irq_handler(serial_irq_ids[SERIAL_6], RxIrq); + } else if (int_status & (1 << 5U)) { + TSB_FURT0->ICR = int_status & FUARTxMIS_TXMIS_MASK; + irq_handler(serial_irq_ids[SERIAL_6], TxIrq); + } else { + return; + } +} + +void INTFUART1_IRQHandler(void) +{ + uint32_t int_status; + + int_status = TSB_FURT1->MIS; + if (int_status & (1 << 4U)) { + irq_handler(serial_irq_ids[SERIAL_7], RxIrq); + } else if (int_status & (1 << 5U)) { + irq_handler(serial_irq_ids[SERIAL_7], TxIrq); + } else { + return; + } +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + uint32_t tmp = 0U; + IRQn_Type irq_n = (IRQn_Type)0; + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTUART0RX_IRQn; + } else { + irq_n = INTUART0TX_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTUART1RX_IRQn; + } else { + irq_n = INTUART1TX_IRQn; + } + break; + case SERIAL_2: + if (irq == RxIrq) { + irq_n = INTUART2RX_IRQn; + } else { + irq_n = INTUART2TX_IRQn; + } + break; + case SERIAL_3: + if (irq == RxIrq) { + irq_n = INTUART3RX_IRQn; + } else { + irq_n = INTUART3TX_IRQn; + } + break; + case SERIAL_4: + if (irq == RxIrq) { + irq_n = INTUART4RX_IRQn; + } else { + irq_n = INTUART4TX_IRQn; + } + break; + case SERIAL_5: + if (irq == RxIrq) { + irq_n = INTUART5RX_IRQn; + } else { + irq_n = INTUART5TX_IRQn; + } + break; + case SERIAL_6: + irq_n = INTFUART0_IRQn; + break; + case SERIAL_7: + irq_n = INTFUART1_IRQn; + break; + default: + break; + } + + if (obj->is_using_fuart) { + // Set interrupt mask + if (enable) { + if (irq == RxIrq) { + obj->FUARTx->IMSC |= (1 << 4U); + } else { + obj->FUARTx->IMSC |= (1 << 5U); + } + } else { + if (irq == RxIrq) { + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_RXIM_CLEAR; /* Disable Receive interrupt */ + obj->FUARTx->IMSC = tmp; + } else { + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_TXIM_CLEAR; /* Disable Transmit interrupt */ + obj->FUARTx->IMSC = tmp; + } + } + } + NVIC_ClearPendingIRQ(irq_n); + + if (enable) { + NVIC_EnableIRQ(irq_n); + } else { + if (!obj->is_using_fuart) { + NVIC_DisableIRQ(irq_n); + } + } +} + +int serial_getc(serial_t *obj) +{ + int data = 0; + + while (!serial_readable(obj)) { // Wait until Rx buffer is full + // Do nothing + } + + if (!(obj->is_using_fuart)) { + //Read Data Register + data = (obj->UARTx->DR & 0xFFU); + obj->UARTx->SR |= (1U << 6); // clear RXEND flag + } else { + data = (obj->FUARTx->DR & 0xFFU); + } + + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)) { + // Do nothing + } + + // Write Data Register + if (!(obj->is_using_fuart)) { + obj->UARTx->DR = (c & 0xFF); + + while ((obj->UARTx->SR & (1U << 14)) == 0) { + } + + obj->UARTx->SR |= (1U << 14); // clear TXEND flag + } else { + obj->FUARTx->DR = (c & 0xFF); + } +} + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if (!(obj->is_using_fuart)) { + if ((obj->UARTx->SR & 0x000F) != 0) { + ret = 1; + } + } else { + if (obj->FUARTx->FR & (1 << 6U)) { + ret = 1; + } + } + + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if (!(obj->is_using_fuart)) { + if ((obj->UARTx->SR & 0x8000) == 0) { + ret = 1; + } + } else { + if (obj->FUARTx->FR & (1 << 7U)) { + ret = 1; + } + } + + return ret; +} + +void serial_clear(serial_t *obj) +{ + uint32_t dummy; + if (!(obj->is_using_fuart)) { + obj->UARTx->FIFOCLR = 0x03; + } else { + { + dummy = obj->FUARTx->DR; //dummy read + (void)dummy; + } + } +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +// Set flow control +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts); + + if (!(obj->is_using_fuart)) { + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName) NC); + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pin_mode(txflow, PullUp); // initial state of CTS preferably high + obj->UARTx->CR0 |= (1 << 10); // Enable CTS hardware control + + } else if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName) NC); + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + obj->UARTx->CR0 |= (1 << 9); // Enable RTS hardware control + + } else if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_name != (UARTName) NC); + obj->UARTx->CR0 |= (3 << 9); // Enable CTS and RTS hardware flow control + + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + pin_mode(txflow, PullUp); + } else { + obj->UARTx->CR0 &= (~(3 << 9)); // Disable CTS and RTS hardware flow control + } + } else { + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; // Disable FUART + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName) NC); + obj->FUARTx->CR |= FUART_CTS_ENABLE; // Enable CTS hardware flow control + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS and RTS function + pin_mode(txflow, PullUp); + + } else if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName) NC); + obj->FUARTx->CR |= FUART_RTS_ENABLE; // Enable RTS hardware flow control + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + + } else if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_name != (UARTName) NC); + obj->FUARTx->CR |= (FUART_CTS_ENABLE | FUART_RTS_ENABLE); // Enable CTS and RTS hardware flow control + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + pin_mode(txflow, PullUp); + + } else { + obj->FUARTx->CR &= FUART_CTS_RTS_DISABLE_MASK; // Disable CTS and RTS hardware flow control + } + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } +} + +// Pause transmission +void serial_break_set(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS |= 0x08; + } else { + obj->FUARTx->LCR_H |= FUARTxLCR_H_BRK_SEND; + } +} + +// Switch to normal transmission +void serial_break_clear(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS &= ~(0x08); + } else { + obj->FUARTx->LCR_H &= ~(FUARTxLCR_H_BRK_SEND); + } +} + +static void uart_swreset(TSB_UART_TypeDef *UARTx) +{ + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + + UARTx->SWRST = UARTxSWRST_SWRST_10; + UARTx->SWRST = UARTxSWRST_SWRST_01; + + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } +} + +static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct) +{ + uint32_t tmp = 0U; + + + obj->FUARTx->BRD = obj->boudrate.brn; + obj->FUARTx->FBRD = obj->boudrate.brk; + + tmp = obj->FUARTx->LCR_H; + + tmp &= LCR_H_WLEN_MASK; + tmp |= InitStruct->DataBits; + + tmp &= LCR_H_STP2_MASK; + tmp |= InitStruct->StopBits; + + tmp &= LCR_H_PARITY_MASK; + tmp |= InitStruct->Parity; + + obj->FUARTx->LCR_H = tmp; //Set DataBits, StopBits, Parity + + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_TXIM_RXIM_MASK; + tmp |= (FUART_TX_INT_ENABLE | FUART_RX_INT_ENABLE); + obj->FUARTx->IMSC = tmp; + + tmp = obj->FUARTx->CR; + tmp &= CR_FLOW_CTRL_MASK; + tmp |= InitStruct->FlowCtrl; + + tmp &= CR_MODE_MASK; + tmp |= InitStruct->Mode; + + obj->FUARTx->CR = tmp; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c new file mode 100644 index 0000000..692e941 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/sleep.c @@ -0,0 +1,126 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" + +// Number of warm-up cycle = (warming up time (s) / clock period (s)) - 16 +#define CG_WUODR_INT_5MS ((uint16_t)0x0C34) +#define CG_STBY_MODE_IDLE 0x0 +#define CG_STBY_MODE_STOP1 0x1 +#define EXTERNEL_OSC_MASK 0xFFFFFFF1 +#define SIWDT_DISABLE 0xB1 +#define WUPT_LOWER_MASK 0x000F +#define WUPT_UPPER_MASK 0xFFF0 + +static void external_losc_enable(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + TSB_CG->STBYCR = CG_STBY_MODE_IDLE; + + // Enter idle mode + __DSB(); + __WFI(); +} + +void hal_deepsleep(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + uint32_t tmp = 0; + + TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE; + + TSB_SIWD0->EN = TXZ_DISABLE; + TSB_SIWD0->CR = SIWDT_DISABLE; + + + while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) { + // Flash wait + } + + while (TSB_CG_WUPHCR_WUEF) { + // Wait for end of Warming-up for IHOSC1 + } + + TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE; + wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + TSB_CG->STBYCR = CG_STBY_MODE_STOP1; + TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE; + + + while (TSB_CG_PLL0SEL_PLL0ST) { + // Wait for PLL status of fsys until off state(fosc=0) + } + + // Stop PLL of fsys + TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE; + TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE; + TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE; + + while (TSB_CG_OSCCR_OSCF) { + // Wait for fosc status until IHOSC1 = 0 + } + + tmp = TSB_CG->OSCCR; + tmp &= EXTERNEL_OSC_MASK; + TSB_CG->OSCCR = tmp; + + + // Enter stop1 mode + __DSB(); + __WFI(); + + // Switch over from IHOSC to EHOSC + // After coming out off sleep mode, Restore the clock setting to EHOSC. + external_losc_enable(); +} + +static void external_losc_enable(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + + // Enable high-speed oscillator + TSB_CG->OSCCR |= (TXZ_ENABLE << 1); + + // Select internal(fIHOSC) as warm-up clock + wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + + // Start warm-up + TSB_CG->WUPHCR |= TXZ_ENABLE; + + // Wait until EHOSC become stable + while ((TSB_CG->WUPHCR & 0x0002)) { + // Do nothing + } + + // Set fosc source + TSB_CG->OSCCR |= (1 << 8); + + // Wait for to become "1" + while (!((TSB_CG->OSCCR & 0x200) >> 9)) { + // Do nothing + } + + // Stop IHOSC + TSB_CG->OSCCR &= ~TXZ_ENABLE; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c new file mode 100644 index 0000000..7ebaef7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/spi_api.c @@ -0,0 +1,678 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "spi_api.h" +#include "mbed_error.h" +#include "txz_tspi.h" +#include "pinmap.h" + +#define TIMEOUT 5000 +#define INITIAL_SPI_FREQ 1000000 + +#if DEVICE_SPI_ASYNCH +#define SPI_S(obj) (struct spi_s *) (&((obj)->spi)) +#else +#define SPI_S(obj) (struct spi_s *) (obj) +#endif + +#if DEVICE_SPI_ASYNCH +static void spi_irq_handler(spi_t *obj); +static void disable_irq(uint32_t irqn); +static void clear_irq(uint32_t irqn); +enum { + SPI_TRANSFER_STATE_IDLE = 0U, + SPI_TRANSFER_STATE_BUSY +} SPI_TransferState; +typedef struct { + IRQn_Type Tx; + IRQn_Type Rx; + IRQn_Type Error; +} spi_irq_t; +static const spi_irq_t SPI_CH0_IRQN_TBL[1] = { + { INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn } +}; +static const spi_irq_t SPI_CH1_IRQN_TBL[1] = { + { INTT1RX_IRQn, INTT1TX_IRQn, INTT1ERR_IRQn } +}; +static const spi_irq_t SPI_CH2_IRQN_TBL[1] = { + { INTT2RX_IRQn, INTT2TX_IRQn, INTT2ERR_IRQn } +}; +static const spi_irq_t SPI_CH3_IRQN_TBL[1] = { + { INTT3RX_IRQn, INTT3TX_IRQn, INTT3ERR_IRQn } +}; +static const spi_irq_t SPI_CH4_IRQN_TBL[1] = { + { INTT4RX_IRQn, INTT4TX_IRQn, INTT4ERR_IRQn } +}; +static const spi_irq_t SPI_CH5_IRQN_TBL[1] = { + { INTT5RX_IRQn, INTT5TX_IRQn, INTT5ERR_IRQn } +}; +static const spi_irq_t SPI_CH6_IRQN_TBL[1] = { + { INTT6RX_IRQn, INTT6TX_IRQn, INTT6ERR_IRQn } +}; +static const spi_irq_t SPI_CH7_IRQN_TBL[1] = { + { INTT7RX_IRQn, INTT7TX_IRQn, INTT7ERR_IRQn } +}; +static const spi_irq_t SPI_CH8_IRQN_TBL[1] = { + { INTT8RX_IRQn, INTT8TX_IRQn, INTT8ERR_IRQn } +}; +#endif + +static const PinMap PinMap_SPI_SCLK[] = { + {PA1, SPI_0, PIN_DATA(7, 1)}, + {PL1, SPI_1, PIN_DATA(7, 1)}, + {PA6, SPI_2, PIN_DATA(7, 1)}, + {PK6, SPI_3, PIN_DATA(4, 1)}, + {PD1, SPI_4, PIN_DATA(4, 1)}, + {PV6, SPI_5, PIN_DATA(4, 1)}, + {PM2, SPI_6, PIN_DATA(6, 1)}, + {PM5, SPI_7, PIN_DATA(6, 1)}, + {PW1, SPI_8, PIN_DATA(4, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SLAVE_SCLK[] = { + {PA1, SPI_0, PIN_DATA(7, 0)}, + {PL1, SPI_1, PIN_DATA(7, 0)}, + {PA6, SPI_2, PIN_DATA(7, 0)}, + {PK6, SPI_3, PIN_DATA(4, 0)}, + {PD1, SPI_4, PIN_DATA(4, 0)}, + {PV6, SPI_5, PIN_DATA(4, 0)}, + {PM2, SPI_6, PIN_DATA(6, 0)}, + {PM5, SPI_7, PIN_DATA(6, 0)}, + {PW1, SPI_8, PIN_DATA(4, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {PA3, SPI_0, PIN_DATA(7, 1)}, + {PL3, SPI_1, PIN_DATA(7, 1)}, + {PA4, SPI_2, PIN_DATA(7, 1)}, + {PK4, SPI_3, PIN_DATA(4, 1)}, + {PD3, SPI_4, PIN_DATA(4, 1)}, + {PV5, SPI_5, PIN_DATA(4, 1)}, + {PM0, SPI_6, PIN_DATA(6, 1)}, + {PM7, SPI_7, PIN_DATA(6, 1)}, + {PW3, SPI_8, PIN_DATA(4, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PA2, SPI_0, PIN_DATA(7, 0)}, + {PL2, SPI_1, PIN_DATA(7, 0)}, + {PA5, SPI_2, PIN_DATA(7, 0)}, + {PK5, SPI_3, PIN_DATA(4, 0)}, + {PD2, SPI_4, PIN_DATA(4, 0)}, + {PV4, SPI_5, PIN_DATA(4, 0)}, + {PM1, SPI_6, PIN_DATA(6, 0)}, + {PM6, SPI_7, PIN_DATA(6, 0)}, + {PW2, SPI_8, PIN_DATA(4, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PA0, SPI_0, PIN_DATA(7, 2)}, + {PL0, SPI_1, PIN_DATA(7, 2)}, + {PA7, SPI_2, PIN_DATA(7, 2)}, + {PK7, SPI_3, PIN_DATA(4, 2)}, + {PD0, SPI_4, PIN_DATA(4, 2)}, + {PV7, SPI_5, PIN_DATA(4, 2)}, + {PM3, SPI_6, PIN_DATA(6, 2)}, + {PM4, SPI_7, PIN_DATA(6, 2)}, + {PW0, SPI_8, PIN_DATA(4, 2)}, + {NC, NC, 0} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + struct spi_s *obj_s = SPI_S(obj); + // Check pin parameters + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj_s->module = (SPIName)pinmap_merge(spi_data, spi_sclk); + obj_s->module = (SPIName)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj_s->module != NC); + + // Identify SPI module to use + switch ((int)obj_s->module) { + case SPI_0: + obj_s->p_obj.p_instance = TSB_TSPI0; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH0_IRQN_TBL; +#endif + break; + case SPI_1: + obj_s->p_obj.p_instance = TSB_TSPI1; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA05 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB12 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH1_IRQN_TBL; +#endif + break; + case SPI_2: + obj_s->p_obj.p_instance = TSB_TSPI2; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH2_IRQN_TBL; +#endif + break; + case SPI_3: + obj_s->p_obj.p_instance = TSB_TSPI3; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA07 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB11 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH3_IRQN_TBL; +#endif + break; + case SPI_4: + obj_s->p_obj.p_instance = TSB_TSPI4; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA08 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB05 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH4_IRQN_TBL; +#endif + break; + case SPI_5: + obj_s->p_obj.p_instance = TSB_TSPI5; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA09 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH5_IRQN_TBL; +#endif + break; + case SPI_6: + obj_s->p_obj.p_instance = TSB_TSPI6; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH6_IRQN_TBL; +#endif + break; + case SPI_7: + obj_s->p_obj.p_instance = TSB_TSPI7; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA21 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB13 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH7_IRQN_TBL; +#endif + break; + case SPI_8: + obj_s->p_obj.p_instance = TSB_TSPI8; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA22 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB20 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH8_IRQN_TBL; +#endif + break; + default: + obj_s->p_obj.p_instance = NULL; + obj_s->module = (SPIName)NC; + error("Cannot found SPI module corresponding with input pins."); + break; + } + + // Pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + obj_s->Slave_SCK = sclk; + + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + // Default configurations 8 bit, 1Mhz frequency + // Control 1 configurations + obj_s->p_obj.init.id = (uint32_t)obj_s->module; + obj_s->p_obj.init.cnt1.inf = TSPI_INF_DISABLE; // Infinite Transfer Control disabled + obj_s->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled + obj_s->p_obj.init.cnt1.trxe = TSPI_TRXE_DISABLE; // Enable Communication + obj_s->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode + obj_s->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // master mode operation + obj_s->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) + obj_s->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid + obj_s->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_CONTINUE;// transfer single frame at a time continuously + + //Control 2 configurations + obj_s->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; + obj_s->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low + obj_s->p_obj.init.cnt2.rxdly = TSPI_RXDLY_8CLK; + obj_s->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level + obj_s->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level + obj_s->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; + obj_s->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; + obj_s->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; + obj_s->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; + obj_s->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; + obj_s->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; + obj_s->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; + + //Control 3 configurations + obj_s->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear + obj_s->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear + + //baudrate settings - 1Mhz default + spi_frequency(obj_s, (int)INITIAL_SPI_FREQ); + + //Format Control 0 settings + obj_s->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first + obj_s->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; + obj_s->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; + + //Special control on polarity of signal and generation timing + obj_s->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; + obj_s->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; + obj_s->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; + obj_s->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; + + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + obj_s->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; + obj_s->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; + obj_s->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; + + //Format Control 1 settings tspi_fmtr1_t + obj_s->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; + obj_s->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; + + obj_s->p_obj.init.scr0.sect = TSPI_SECT_MODE_FRAME; + + obj_s->bits = (uint8_t)TSPI_DATA_LENGTH_8; + + //initialize SPI + tspi_init(&obj_s->p_obj); +} + +void spi_free(spi_t *obj) +{ + struct spi_s *obj_s = SPI_S(obj); + + tspi_deinit(&obj_s->p_obj); + obj_s->module = (SPIName)NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + struct spi_s *obj_s = SPI_S(obj); + + MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode + MBED_ASSERT((bits >= 8) && (bits <= 32)); + + obj_s->bits = bits; + obj_s->p_obj.init.fmr0.fl = (bits << 24); + + + if ((mode >> 1) & 0x1) { + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; + } else { + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + } + + if (mode & 0x1) { + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; + } else { + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + } + + if (slave) { + pinmap_pinout(obj_s->Slave_SCK, PinMap_SPI_SLAVE_SCLK); + obj_s->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation + } + tspi_init(&obj_s->p_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + struct spi_s *obj_s = SPI_S(obj); + + + uint8_t brs = 0; + uint8_t brck = 0; + uint16_t prsck = 1; + uint64_t fscl = 0; + uint64_t tmp_fscl = 0; + uint64_t fx = 0; + uint64_t tmpvar = SystemCoreClock; + + SystemCoreClockUpdate(); + tmpvar = tmpvar / 2; + for (prsck = 1; prsck <= 512; prsck *= 2) { + fx = ((uint64_t)tmpvar / prsck); + for (brs = 1; brs <= 16; brs++) { + fscl = fx / brs; + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + obj_s->p_obj.init.brd.brck = (brck << 4); + if (brs == 16) { + obj_s->p_obj.init.brd.brs = 0; + } else { + obj_s->p_obj.init.brd.brs = brs; + } + } + } + brck ++; + } + + tspi_init(&obj_s->p_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + struct spi_s *obj_s = SPI_S(obj); + uint8_t ret_value = 0; + + tspi_transmit_t send_obj; + tspi_receive_t rec_obj; + + // Transmit data + send_obj.tx8.p_data = (uint8_t *)&value; + send_obj.tx8.num = 1; + tspi_master_write(&obj_s->p_obj, &send_obj, TIMEOUT); + + // Read received data + rec_obj.rx8.p_data = &ret_value; + rec_obj.rx8.num = 1; + tspi_master_read(&obj_s->p_obj, &rec_obj, TIMEOUT); + + return ret_value; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_busy(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + int ret = 1; + uint32_t status = 0; + tspi_get_status(&obj->p_obj, &status); + if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { + ret = 0; + } + + return ret; +} + +int spi_slave_receive(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + int ret = 1; + uint32_t status; + + tspi_get_status(&obj->p_obj, &status); + if ((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) { + ret = 0; + } + return ret; +} + +int spi_slave_read(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + uint8_t ret_value = 0; + ret_value = obj->p_obj.p_instance->DR & 0xFF; + obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; + obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + + return ret_value; +} + +void spi_slave_write(spi_t *t_obj, int value) +{ + struct spi_s *obj = SPI_S(t_obj); + + // Enable TSPI Transmission Control. + obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + obj->p_obj.p_instance->DR = value & 0xFF; + +} + +uint8_t spi_get_module(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + return (uint8_t)(obj->module); +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SLAVE_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#if DEVICE_SPI_ASYNCH + +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, + uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn; + + + // check which use-case we have + bool use_tx = (tx != NULL && tx_length > 0); + bool use_rx = (rx != NULL && rx_length > 0); + + // don't do anything, if the buffers aren't valid + if (!use_tx && !use_rx) { + return; + } + + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + + obj->rx_buff.buffer = (void *)rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + spiobj->event = 0; + spiobj->state = SPI_TRANSFER_STATE_IDLE; + + + NVIC_SetVector(p_irqn->Error, (uint32_t)handler); + NVIC_SetVector(p_irqn->Tx, (uint32_t)handler); + NVIC_SetVector(p_irqn->Rx, (uint32_t)handler); + + // Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt + spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE); + + if (use_tx && use_rx) { + spiobj->max_size = tx_length < rx_length ? rx_length : tx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; + } else if (use_tx) { + spiobj->max_size = tx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; + // Enable Interrupt bit in SPI peripheral - Enabled in init() + } else if (use_rx) { + spiobj->max_size = rx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = 0xFF; + } + spiobj->state = SPI_TRANSFER_STATE_BUSY; + NVIC_EnableIRQ(p_irqn->Error); + NVIC_EnableIRQ(p_irqn->Tx); + NVIC_EnableIRQ(p_irqn->Rx); +} +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_irq_handler(obj); + return ((spiobj->event & SPI_EVENT_ALL) | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ; +} + +uint8_t spi_active(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + uint8_t ret_val = 0; + if (spiobj->state != SPI_TRANSFER_STATE_IDLE) { + ret_val = 1; + } + + return ret_val; +} + +void spi_abort_asynch(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + + disable_irq(spiobj->irqn); + clear_irq(spiobj->irqn); + tspi_init(&spiobj->p_obj); +} + +static void spi_irq_handler(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + if ((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) && + (spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) { + uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF; + + while ((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) { + ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF; + rlvl--; + // transmit complete but receive pending - dummy write + } + + if (obj->rx_buff.pos == spiobj->max_size) { + spiobj->state = SPI_TRANSFER_STATE_IDLE; + } + spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE; + } + + if (spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) { + + obj->tx_buff.pos++; + spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; + + if (obj->tx_buff.pos == (spiobj->max_size)) { + spiobj->state = SPI_TRANSFER_STATE_IDLE; + } + if ((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) { + spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF); + } else if (obj->tx_buff.pos < spiobj->max_size) { + spiobj->p_obj.p_instance->DR = 0xFF; + } + } + + if (spiobj->p_obj.p_instance->ERR) { + spiobj->event = SPI_EVENT_ERROR; + spiobj->state = SPI_TRANSFER_STATE_IDLE; + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + return; + } + + if (spiobj->state == SPI_TRANSFER_STATE_IDLE) { + spiobj->event = SPI_EVENT_COMPLETE; + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + } + + +} + +static void disable_irq(uint32_t irqn) +{ + spi_irq_t *p_irqn = (spi_irq_t *)irqn; + NVIC_DisableIRQ(p_irqn->Tx); + NVIC_DisableIRQ(p_irqn->Rx); + NVIC_DisableIRQ(p_irqn->Error); +} + +static void clear_irq(uint32_t irqn) +{ + spi_irq_t *p_irqn = (spi_irq_t *)irqn; + NVIC_ClearPendingIRQ(p_irqn->Tx); + NVIC_ClearPendingIRQ(p_irqn->Rx); + NVIC_ClearPendingIRQ(p_irqn->Error); + + //clean-up +} + +#endif //DEVICE_SPI_ASYNCH diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c new file mode 100644 index 0000000..13caede --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4GR/us_ticker.c @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "TMPM4GR.h" +#include "txz_t32a.h" + +#define CLR_TIMER_INT_FLAG (uint8_t)0x41 + +static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? + +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + 3000000, + 32 + }; + return &info; +} + +// Initialize us_ticker +void us_ticker_init(void) +{ + if (us_ticker_inited) { + us_ticker_disable_interrupt(); + return; + } + us_ticker_inited = 1; + + // Enable clock for T32A0 + TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE; + + // T32A ch0 TimerC Reg Match/Over Flow/Under Flow + TSB_IB->IMC006 = TXZ_ENABLE; + + // Configure Timer T32A0 + TSB_T32A0->MOD = T32A_MODE_32; + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->CRC = T32A_PRSCLx_32; + TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); + + NVIC_SetVector(INTT32A00_A_CT_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); +} + +uint32_t us_ticker_read(void) +{ + uint32_t ret_val = 0; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + ret_val = (TSB_T32A0->TMRC); + return ret_val; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->RGC1 = timestamp ; + NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INTT32A00_A_CT_IRQn); + NVIC_EnableIRQ(INTT32A00_A_CT_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + // Disable interrupts in NVIC + TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); + NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); +} + +void us_ticker_free(void) +{ + TSB_T32A0->RUNC = T32A_RUN_DISABLE; + TSB_IB->IMC006 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A00_A_CT_IRQn); + NVIC_DisableIRQ(INTT32A00_A_CT_IRQn); + TSB_CG_FSYSMENA_IPMENA06 = TXZ_DISABLE; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc.h new file mode 100644 index 0000000..8039d24 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc.h @@ -0,0 +1,476 @@ +/** + ******************************************************************************* + * @file txz_adc.h + * @brief This file provides all the functions prototypes for ADC driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_H +#define __ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_adc_ch.h" +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/** + * @defgroup ADC_ChannelMax Channel Num Max + * @brief Max Num of channel. + * @{ + */ + +#define ADC_NUM_MAX ((uint32_t)24) /*!< Max Num of conversion. */ +/** + * @} + */ /* End of group ADC_ChannelMax */ +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + @defgroup ADC_Exported_define ADC Exported Define + @{ + */ +/** @enum adc_sampling_period0_t + @brief Outside AIN sampling period. + */ +typedef enum { + ADC_SAMPLING_PERIOD0_XN = 0x00, /*!< SCLK Period (1/SCLK)xN */ + ADC_SAMPLING_PERIOD0_X2N = 0x08, /*!< SCLK Period (1/SCLK)x2N */ + ADC_SAMPLING_PERIOD0_X3N = 0x10, /*!< SCLK Period (1/SCLK)x3N */ + ADC_SAMPLING_PERIOD0_X4N = 0x18, /*!< SCLK Period (1/SCLK)x4N */ +} adc_sampling_period0_t; +/** @enum adc_sampling_period1_t + @brief Outside AIN sampling period. + */ +typedef enum { + ADC_SAMPLING_PERIOD1_XN = 0x000, /*!< SCLK Period (1/SCLK)xN */ + ADC_SAMPLING_PERIOD1_X2N = 0x100, /*!< SCLK Period (1/SCLK)x2N */ + ADC_SAMPLING_PERIOD1_X3N = 0x200, /*!< SCLK Period (1/SCLK)x3N */ + ADC_SAMPLING_PERIOD1_X4N = 0x300, /*!< SCLK Period (1/SCLK)x4N */ +} adc_sampling_period1_t; + +/*! @enum adc_sclk_t + @brief Select AD prescaler output (SCLK). + */ +typedef enum { + ADC_SCLK_2 = (0x00000000U), /*!< ADCLK/2 */ + ADC_SCLK_4 = (0x00000001U), /*!< ADCLK/4 */ + ADC_SCLK_8 = (0x00000002U), /*!< ADCLK/8 */ + ADC_SCLK_16 = (0x00000003U), /*!< ADCLK/16 */ + ADC_SCLK_3 = (0x00000004U), /*!< ADCLK/3 */ + ADC_SCLK_5 = (0x00000005U), /*!< ADCLK/5 */ + ADC_SCLK_6 = (0x00000006U), /*!< ADCLK/6 */ + ADC_SCLK_10 = (0x00000007U), /*!< ADCLK/10 */ +} adc_sclk_t; + +/*! @enum adc_mod1_t + @brief Select SCLK Frequency Band (MOD1). + */ +typedef enum { + ADC_MOD1_SCLK_1 = (0x00001000U), /*!< SCLK =< 20MHz > */ + ADC_MOD1_SCLK_2 = (0x00003000U), /*!< 20MHz < SCLK =< 25MHz > */ + ADC_MOD1_SCLK_3 = (0x00004000U), /*!< 25MHz < SCLK =< 30MHz > */ + ADC_MOD1_SCLK_4 = (0x00006011U), /*!< 30MHz < SCLK =< 40MHz > */ +} adc_mod1_t; + +/*! @enum adc_mod2_t + @brief Select ADC Product Setting Value (MOD2). + */ +typedef enum { + ADC_MOD2_SET = (0x00000000U), /*!< SET Value */ + ADC_MOD2_CLEAR = (0x00000000U), /*!< Reset Value */ +} adc_mod2_t; + +/*! @enum adc_int_t + @brief Select Interrupt Enable/Disable. + */ +typedef enum { + ADC_INT_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_INT_ENABLE = (0x00000080U), /*!< Enable. */ +} adc_int_t; + +/*! @enum adc_conversion_t + @brief Select conversion method. + */ +typedef enum { + ADC_CONVERSION_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_CONVERSION_CNT = (0x00000100U), /*!< Continuation. */ + ADC_CONVERSION_SGL = (0x00000200U), /*!< Single. */ + ADC_CONVERSION_TRG = (0x00000300U), /*!< Universal Trigger. */ + ADC_CONVERSION_HPTG = (0x00000400U), /*!< High Priority Trigger. */ +} adc_conversion_t; + +/*! @enum adc_dma_int_t + @brief Select DMA interrupt method. + */ +typedef enum { + ADC_DMA_INT_SGL_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_SGL_ENABLE = (0x00000020U), /*!< DMA Single interrupt Enable. */ + ADC_DMA_INT_CNT_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_CNT_ENABLE = (0x00000040U), /*!< DMA Continuation interrupt Enable. */ + ADC_DMA_INT_TRG_DISABLE = (0x00000000U), /*!< Disable. */ + ADC_DMA_INT_TRG_ENABLE = (0x00000010U), /*!< DMA Universal Trigger interrupt Enable. */ + ADC_TRG_DISABLE = (0x00000000U), /*!< Universal Trigger Disable. */ + ADC_TRG_ENABLE = (0x00000001U), /*!< Universal Trigger Enable. */ + ADC_HPTG_DISABLE = (0x00000000U), /*!< High Priority Trigger Disable. */ + ADC_HPTG_ENABLE = (0x00000002U), /*!< High Priority Trigger Enable. */ +} adc_dma_int_t; + +/*! @enum adc_ain_range_t + @brief Range of AIN Macro Definition. + Range of AIN be set "(ADC_AIN_RANGE_MIN <= Value <= ADC_AIN_RANGE_MAX)". + */ +typedef enum { + ADC_AIN_RANGE_MIN = (0x00000000U), /*!< Minimum Value :AINx00 */ + ADC_AIN_RANGE_MAX = (0x00000017U), /*!< Maximum Value :AINx23 */ +} adc_ain_range_t; + +/*! @enum adc_status_t + @brief AD Running Status. + */ +typedef enum { + ADC_STATUS_MASK = (0x00000080U), /*!< for Mask. */ + ADC_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_STATUS_RUNNING = (0x00000080U), /*!< Running. */ +} adc_status_t; + +/*! @enum adc_cnt_status_t + @brief Continuity Conversion Running Status. + */ +typedef enum { + ADC_CNT_STATUS_MASK = (0x00000008U), /*!< for Mask. */ + ADC_CNT_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_CNT_STATUS_RUNNING = (0x00000008U), /*!< Running. */ +} adc_cnt_status_t; + +/*! @enum adc_sgl_status_t + @brief Single Conversion Running Status. + */ +typedef enum { + ADC_SGL_STATUS_MASK = (0x00000004U), /*!< for Mask. */ + ADC_SGL_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_SGL_STATUS_RUNNING = (0x00000004U), /*!< Running. */ +} adc_sgl_status_t; + +/*! @enum adc_trg_status_t + @brief Trigger Conversion Running Status. + */ +typedef enum { + ADC_TRG_STATUS_MASK = (0x00000002U), /*!< for Mask. */ + ADC_TRG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_TRG_STATUS_RUNNING = (0x00000002U), /*!< Running. */ +} adc_trg_status_t; + +/*! @enum adc_hpri_status_t + @brief Trigger Conversion Running Status. + */ +typedef enum { + ADC_HPTG_STATUS_MASK = (0x00000001U), /*!< for Mask. */ + ADC_HPTG_STATUS_SLEEP = (0x00000000U), /*!< Sleep. */ + ADC_HPTG_STATUS_RUNNING = (0x00000001U), /*!< Running. */ +} adc_hpri_status_t; + +/*! @enum adcmpxen_t + @brief Select Enable, Disable setting(ADxCMPEN). + */ +typedef enum { + ADCMP1EN_DISABLE = (0x00000000U), /*!< Disable. */ + ADCMP1EN_ENABLE = (0x00000002U), /*!< Enable. */ + ADCMP0EN_DISABLE = (0x00000000U), /*!< Disable. */ + ADCMP0EN_ENABLE = (0x00000001U), /*!< Enable. */ +} adcmpxen_t; + +/*! @enum adcmpcnt_t + @brief Select Compare count num. + */ +typedef enum { + ADCMPCNT_1 = (0x00000000U), /*!< 1 time */ + ADCMPCNT_2 = (0x00000100U), /*!< 2 times */ + ADCMPCNT_3 = (0x00000200U), /*!< 3 times */ + ADCMPCNT_4 = (0x00000300U), /*!< 4 times */ + ADCMPCNT_5 = (0x00000400U), /*!< 5 times */ + ADCMPCNT_6 = (0x00000500U), /*!< 6 times */ + ADCMPCNT_7 = (0x00000600U), /*!< 7 times */ + ADCMPCNT_8 = (0x00000700U), /*!< 8 times */ + ADCMPCNT_9 = (0x00000800U), /*!< 9 times */ + ADCMPCNT_10 = (0x00000900U), /*!< 10 times */ + ADCMPCNT_11 = (0x00000a00U), /*!< 11 times */ + ADCMPCNT_12 = (0x00000b00U), /*!< 12 times */ + ADCMPCNT_13 = (0x00000c00U), /*!< 13 times */ + ADCMPCNT_14 = (0x00000d00U), /*!< 14 times */ + ADCMPCNT_15 = (0x00000e00U), /*!< 15 times */ + ADCMPCNT_16 = (0x00000f00U), /*!< 16 times */ +} adcmpcnt_t; + +/*! @enum adcmpcond_t + @brief Compare condition + */ +typedef enum { + ADCMPCond_CNT = (0x00000000U), /*!< Continuous */ + ADCMPCond_ACC = (0x00000040U), /*!< Accumulation */ +} adcmpcond_t; + +/*! @enum adcmpbigsml_t + @brief Compare Big, Small condition + */ +typedef enum { + ADCMPBigSml_Big = (0x00000000U), /*!< Big */ + ADCMPBigSml_Sml = (0x00000020U), /*!< Small */ +} adcmpbigsml_t; + +/*! @enum adcmpstr_t + @brief Select Compare Store register + */ +typedef enum { + ADCMPStr_Reg0 = (0x00000000U), /*!< ADxREG0 */ + ADCMPStr_Reg1 = (0x00000001U), /*!< ADxREG1 */ + ADCMPStr_Reg2 = (0x00000002U), /*!< ADxREG2 */ + ADCMPStr_Reg3 = (0x00000003U), /*!< ADxREG3 */ + ADCMPStr_Reg4 = (0x00000004U), /*!< ADxREG4 */ + ADCMPStr_Reg5 = (0x00000005U), /*!< ADxREG5 */ + ADCMPStr_Reg6 = (0x00000006U), /*!< ADxREG6 */ + ADCMPStr_Reg7 = (0x00000007U), /*!< ADxREG7 */ + ADCMPStr_Reg8 = (0x00000008U), /*!< ADxREG8 */ + ADCMPStr_Reg9 = (0x00000009U), /*!< ADxREG9 */ + ADCMPStr_Reg10 = (0x0000000aU), /*!< ADxREG10 */ + ADCMPStr_Reg11 = (0x0000000bU), /*!< ADxREG11 */ + ADCMPStr_Reg12 = (0x0000000cU), /*!< ADxREG12 */ + ADCMPStr_Reg13 = (0x0000000dU), /*!< ADxREG13 */ + ADCMPStr_Reg14 = (0x0000000eU), /*!< ADxREG14 */ + ADCMPStr_Reg15 = (0x0000000fU), /*!< ADxREG15 */ + ADCMPStr_Reg16 = (0x00000010U), /*!< ADxREG16 */ + ADCMPStr_Reg17 = (0x00000011U), /*!< ADxREG17 */ + ADCMPStr_Reg18 = (0x00000012U), /*!< ADxREG18 */ + ADCMPStr_Reg19 = (0x00000013U), /*!< ADxREG19 */ + ADCMPStr_Reg20 = (0x00000014U), /*!< ADxREG20 */ + ADCMPStr_Reg21 = (0x00000015U), /*!< ADxREG21 */ + ADCMPStr_Reg22 = (0x00000016U), /*!< ADxREG22 */ + ADCMPStr_Reg23 = (0x00000017U), /*!< ADxREG23 */ +} adcmpstr_t; +/*! @enum adcexazain_t + @brief Select AIN no. + */ + +typedef enum { + ADCEXAZSEL_AIN0 = 0, /*!< AIN0 */ + ADCEXAZSEL_AIN1, /*!< AIN1 */ + ADCEXAZSEL_AIN2, /*!< AIN2 */ + ADCEXAZSEL_AIN3, /*!< AIN3 */ + ADCEXAZSEL_AIN4, /*!< AIN4 */ + ADCEXAZSEL_AIN5, /*!< AIN5 */ + ADCEXAZSEL_AIN6, /*!< AIN6 */ + ADCEXAZSEL_AIN7, /*!< AIN7 */ + ADCEXAZSEL_AIN8, /*!< AIN8 */ + ADCEXAZSEL_AIN9, /*!< AIN9 */ + ADCEXAZSEL_AIN10, /*!< AIN10 */ + ADCEXAZSEL_AIN11, /*!< AIN11 */ + ADCEXAZSEL_AIN12, /*!< AIN12 */ + ADCEXAZSEL_AIN13, /*!< AIN13 */ + ADCEXAZSEL_AIN14, /*!< AIN14 */ + ADCEXAZSEL_AIN15, /*!< AIN15 */ + ADCEXAZSEL_AIN16, /*!< AIN16 */ + ADCEXAZSEL_AIN17, /*!< AIN17 */ + ADCEXAZSEL_AIN18, /*!< AIN18 */ + ADCEXAZSEL_AIN19, /*!< AIN19 */ + ADCEXAZSEL_AIN20, /*!< AIN20 */ + ADCEXAZSEL_AIN21, /*!< AIN21 */ + ADCEXAZSEL_AIN22, /*!< AIN22 */ + ADCEXAZSEL_AIN23, /*!< AIN23 */ +} adcexazain_t; +/*! @enum adcexazsel_t + @brief Select sampling period, EXAS0 or EXAS1. + */ +typedef enum { + ADCEXAZSEL_EXAZ0 = (0x00000000), /*< EXAZ0 */ + ADCEXAZSEL_EXAZ1 = (0x00000001), /*< EXAZ1 */ +} adcexazsel_t; + +/*! + @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/*! + @defgroup ADC_Exported_typedef ADC Exported Typedef + @{ + */ + +/*----------------------------------*/ +/*! @struct adc_clock_t + @brief Clock information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + adc_sampling_period0_t exaz0; /*!< Outside AIN0 Sampling period. + : Use @ref adc_sampling_period0_t. */ + adc_sampling_period1_t exaz1; /*!< Outside AIN1 Sampling period. + : Use @ref adc_sampling_period1_t. */ + adc_sclk_t vadcld; /*!< Select AD prescaler output (SCLK). + : Use @ref adc_sclk_t. */ + uint32_t sampling_select; /*!< Sampling period select. : bit0-bit23 */ +} adc_clock_t; + +/*----------------------------------*/ +/*! @struct adc_cmpx_t + @brief Clock information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t CMPEN; /*!< Enable Register status */ + uint32_t CMPCNT; /*!< Compare count num. */ + uint32_t CMPCond; /*!< Compare condition */ + uint32_t CMPBigSml; /*!< Compare Big/Small condition */ + uint32_t StrReg; /*!< Compare Store register */ + uint32_t ADComp; /*!< ADxCMP0 register data */ + void (*handle)(uint32_t id, TXZ_Result result); /*!< Notify Compare Done. */ +} adc_cmpx_t; + +/*----------------------------------*/ +/*! @struct adc_initial_setting_t + @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + adc_clock_t clk; /*!< Clock setting. + : Use @ref adc_clock_t. */ + uint32_t mod1; /*!< AVDD3 voltage band setting. + : Use @ref adc_mod1_t. */ + uint32_t mod2; /*!< Product info setting. + : Use @ref adc_mod2_t. */ + adc_cmpx_t CMPxEN[4]; /*!< adc_cmpx_t. */ +} adc_initial_setting_t; + +/*----------------------------------*/ +/*! @struct adc_channel_setting_t + @brief Channel Setting. \n +*/ +/*----------------------------------*/ +typedef struct { + uint32_t interrupt; /*!< Interrupt Enable/Disable. + : Use @ref adc_dma_int_t. */ + uint32_t type; /*!< Conversion Type. + : Use @ref adc_conversion_t. */ + uint32_t ain; /*!< AIN. */ +} adc_channel_setting_t; + +/*----------------------------------*/ +/*! @struct adc_internal_info_t + @brief Driver internal information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + adc_ch_t ch[ADC_NUM_MAX]; /*!< Channel Instance. */ +} adc_internal_info_t; + +/*----------------------------------*/ +/*! @struct adc_t + @brief ADC handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_AD_TypeDef *p_instance; /*!< Registers base address. */ + adc_initial_setting_t init; /*!< Initial setting. */ + adc_internal_info_t info; /*!< Driver internal information. */ + struct { + void (*single)(uint32_t id, TXZ_Result result); /*!< Notify Single Conversion Done. */ + void (*continuity)(uint32_t id, TXZ_Result result); /*!< Notify Continuity Conversion Done. */ + void (*trigger)(uint32_t id, TXZ_Result result); /*!< Notify Trigger Conversion Done. */ + void (*highpriority)(uint32_t id, TXZ_Result result); /*!< Notify HighPriority Conversion Done. */ + } handler; /*!< Handler structure. */ +} adc_t; + +/** + * @} + */ /* End of group ADC_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_functions ADC Exported Functions + * @{ + */ +TXZ_Result adc_init(adc_t *p_obj); +TXZ_Result adc_deinit(adc_t *p_obj); +TXZ_Result adc_mode1_setting(void); +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting); +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch); +TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); +TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t); +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value); +TXZ_Result adc_start(adc_t *p_obj); +TXZ_Result adc_stop(adc_t *p_obj); +TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status); +TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout); +void adc_compa_irq_handler(void); +void adc_compb_irq_handler(void); +void adc_single_irq_handler(void); +void adc_continuity_irq_handler(void); +void adc_trigger_irq_handler(void); +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc_ch.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc_ch.h new file mode 100644 index 0000000..78baec1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc_ch.h @@ -0,0 +1,145 @@ +/** + ******************************************************************************* + * @file txz_adc_ch.h + * @brief This file provides all the functions prototypes for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_CH_H +#define __ADC_CH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_define ADC Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_typedef ADC Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/*! @struct adc_ch_initial_setting_t + * @brief Initialize Setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t interrupt; /*!< Interrupt Enable/Disable. + : Use @ref adc_dma_int_t. */ + uint32_t type; /*!< Conversion Type. + : Use @ref adc_conversion_t. */ + uint32_t ain; /*!< AIN. */ +} adc_ch_initial_setting_t; + +/*----------------------------------*/ +/*! @struct adc_ch_t + * @brief ADC handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + __IO uint32_t *p_tset; /*!< ADxTSETn Address. */ + __I uint32_t *p_reg; /*!< ADxREGx Address. */ + adc_ch_initial_setting_t init; /*!< Initial setting. */ +} adc_ch_t; + +/** + * @} + */ /* End of group ADC_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Exported_functions ADC Exported Functions + * @{ + */ +uint32_t get_conversion_data(uint32_t reg); +TXZ_Result adc_ch_init(adc_ch_t *p_obj); +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj); +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj); +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj); +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value); +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_CH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc_include.h new file mode 100644 index 0000000..64a288f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_adc_include.h @@ -0,0 +1,361 @@ +/** + ******************************************************************************* + * @file txz_adc_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __ADC_INCLUDE_H +#define __ADC_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_hal.h" + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @defgroup ADC ADC + * @brief ADC Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/** + * @defgroup NULL_Pointer NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define ADC_NULL ((void *)0) /*!< NULL Pointer. */ +/** + * @} + */ /* End of group NULL_Pointer */ + +/** + * @defgroup Parameter_Result Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define ADC_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define ADC_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group Parameter_Result */ + +/** + * @defgroup ADxCR0 ADxCR0 + * @brief ADxCR0 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ADEN | + * | 6-3 | - | + * | 2 | HPSGL | + * | 1 | SGL | + * | 0 | CNT | + * @{ + */ +/* ADEN */ +#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000) /*!< ADEN :Disable */ +#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080) /*!< ADEN :Enable */ +/* HPSGL */ +#define ADxCR0_HPSGL_ENABLE ((uint32_t)0x00000004) /*!< HPSGL :Enable */ +/* SGL */ +#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002) /*!< SGL :Enable */ +/* CNT */ +#define ADxCR0_CNT_MASK ((uint32_t)0x00000001) /*!< CNT :Mask */ +#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000) /*!< CNT :Disable */ +#define ADxCR0_CNT_ENABLE ((uint32_t)0x00000001) /*!< CNT :Enable */ +/** + * @} + */ /* End of group ADxCR0 */ + +/** + * @defgroup ADxCR1 ADxCR1 + * @brief ADxCR1 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | HPDMEN | + * | 6 | CNTDMEN | + * | 5 | SGLDMEN | + * | 4 | TRGDMEN | + * | 3:2 | - | + * | 1 | HPTRGEN | + * | 0 | TRGEN | + * @{ + */ +/* HPDMEN */ +#define ADxCR1_HPDMEN_DISABLE ((uint32_t)0x00000000) /*!< HPDMEN :Disable */ +#define ADxCR1_HPDMEN_ENABLE ((uint32_t)0x00000080) /*!< HPDMEN :Enable */ +/* CNTDMEN */ +#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000) /*!< CNTDMEN :Disable */ +#define ADxCR1_CNTDMEN_ENABLE ((uint32_t)0x00000040) /*!< CNTDMEN :Enable */ +/* SGLDMEN */ +#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000) /*!< SGLDMEN :Disable */ +#define ADxCR1_SGLDMEN_ENABLE ((uint32_t)0x00000020) /*!< SGLDMEN :Enable */ +/* TRGDMEN */ +#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000) /*!< TRGDMEN :Disable */ +#define ADxCR1_TRGDMEN_ENABLE ((uint32_t)0x00000010) /*!< TRGDMEN :Enable */ +/* HPTRGEN */ +#define ADxCR1_HPTRGEN_DISABLE ((uint32_t)0x00000000) /*!< HPTRGEN :Disable */ +#define ADxCR1_HPTRGEN_ENABLE ((uint32_t)0x00000002) /*!< HPTRGEN :Enable */ +/* TRGEN */ +#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< TRGEN :Disable */ +#define ADxCR1_TRGEN_ENABLE ((uint32_t)0x00000001) /*!< TRGEN :Enable */ +/** + * @} + */ /* End of group ADxCR1 */ + +/** + * @defgroup ADxST ADxST + * @brief ADxST Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ADBF | + * | 6-4 | - | + * | 3 | CNTF | + * | 2 | SNGF | + * | 1 | TRGF | + * | 0 | HPF | + * @{ + */ +/* ADBF */ +#define ADxST_ADBF_MASK ((uint32_t)0x00000080) /*!< ADBF :Mask. */ +#define ADxST_ADBF_IDLE ((uint32_t)0x00000000) /*!< ADBF :Idle. Can stop ADCLK. */ +#define ADxST_ADBF_RUN ((uint32_t)0x00000080) /*!< ADBF :Running. Can't stop ADCLK. */ +/* CNTF */ +#define ADxST_CNTF_MASK ((uint32_t)0x00000008) /*!< CNTF :Mask. */ +#define ADxST_CNTF_IDLE ((uint32_t)0x00000000) /*!< CNTF :Idle. */ +#define ADxST_CNTF_RUN ((uint32_t)0x00000008) /*!< CNTF :Running. */ +/* SNGF */ +#define ADxST_SNGF_MASK ((uint32_t)0x00000004) /*!< SNGF :Mask. */ +#define ADxST_SNGF_IDLE ((uint32_t)0x00000000) /*!< SNGF :Idle. */ +#define ADxST_SNGF_RUN ((uint32_t)0x00000004) /*!< SNGF :Running. */ +/* TRGF */ +#define ADxST_TRGF_MASK ((uint32_t)0x00000002) /*!< TRGF :Mask. */ +#define ADxST_TRGF_IDLE ((uint32_t)0x00000000) /*!< TRGF :Idle. */ +#define ADxST_TRGF_RUN ((uint32_t)0x00000002) /*!< TRGF :Running. */ +/* PMDF */ +#define ADxST_HPF_MASK ((uint32_t)0x00000001) /*!< HPF :Mask. */ +#define ADxST_HPF_IDLE ((uint32_t)0x00000000) /*!< HPF :Idle. */ +#define ADxST_HPF_RUN ((uint32_t)0x00000001) /*!< HPF :Running. */ +/** + * @} + */ /* End of group ADxST */ + +/** + * @defgroup ADxMOD0 ADxMOD0. + * @brief ADxMOD0 Register. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | RCUT | + * | 0 | DACON | + * @{ + */ +/* RCUT */ +#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000) /*!< RCUT :Normal */ +#define ADxMOD0_RCUT_IREF_CUT ((uint32_t)0x00000002) /*!< RCUT :Iref cut */ +/* DACON */ +#define ADxMOD0_DACON_OFF ((uint32_t)0x00000000) /*!< DACON :DAC off */ +#define ADxMOD0_DACON_ON ((uint32_t)0x00000001) /*!< DACON :DAC on */ +/** + * @} + */ /* End of group ADxMOD0 */ + +/** + * @name ADxCMPEN Macro Definition. + * @brief ADxCMPEN Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | CMP3EN | + * | 2 | CMP2EN | + * | 1 | CMP1EN | + * | 0 | CMP0EN | + * @{ + */ +/* CMP3EN */ +#define ADxCMPEN_CMP3EN_DISABLE ((uint32_t)0x00000000) /*!< CMP3EN :Disable */ +#define ADxCMPEN_CMP3EN_ENABLE ((uint32_t)0x00000008) /*!< CMP3EN :Enable */ +/* CMP2EN */ +#define ADxCMPEN_CMP2EN_DISABLE ((uint32_t)0x00000000) /*!< CMP2EN :Disable */ +#define ADxCMPEN_CMP2EN_ENABLE ((uint32_t)0x00000004) /*!< CMP2EN :Enable */ +/* CMP1EN */ +#define ADxCMPEN_CMP1EN_DISABLE ((uint32_t)0x00000000) /*!< CMP1EN :Disable */ +#define ADxCMPEN_CMP1EN_ENABLE ((uint32_t)0x00000002) /*!< CMP1EN :Enable */ +/* CMP0EN */ +#define ADxCMPEN_CMP0EN_DISABLE ((uint32_t)0x00000000) /*!< CMP0EN :Disable */ +#define ADxCMPEN_CMP0EN_ENABLE ((uint32_t)0x00000001) /*!< CMP0EN :Enable */ +/** + * @} + */ /* End of name ADxCMPEN Macro Definition */ + +/** + * @name ADxTSETn Macro Definition. + * @brief ADxTSETn Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | ENINT0 | + * | 6-5 | TRGS0[1:0] | + * | 4-0 | AINST0[4:0]| + * @{ + */ +/* ENINT0 */ +#define ADxTSETn_ENINT_MASK ((uint32_t)0x00000080) /*!< ENINT :Mask */ +#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000) /*!< ENINT :Disable */ +#define ADxTSETn_ENINT_ENABLE ((uint32_t)0x00000080) /*!< ENINT :Enable */ +/* TRGS0[1:0] */ +#define ADxTSETn_TRGS_DISABLE ((uint32_t)0x00000000) /*!< TRGS :Disable */ +#define ADxTSETn_TRGS_CNT ((uint32_t)0x00000100) /*!< TRGS :Continuation */ +#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000200) /*!< TRGS :Single */ +#define ADxTSETn_TRGS_TRG ((uint32_t)0x00000300) /*!< TRGS :Universal Trigger */ +#define ADxTSETn_TRGS_PRI ((uint32_t)0x00000400) /*!< TRGS :Priority Trigger */ +/** + * @} + */ /* End of name ADxTSETn Macro Definition */ + +/** + * @name ADxREGn Macro Definition. + * @brief ADxREGn Register Macro Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-30 | - | + * | 29 | ADOVRF_Mn | + * | 28 | ADRF_Mn | + * | 27-16 | ADR_Mn[11:0] | + * | 15-4 | ADRn[11:0] | + * | 3-2 | - | + * | 1 | ADOVRFn | + * | 0 | ADRFn | + * @{ + */ +/* ADOVRF_Mn */ +#define ADxREGn_ADOVRF_Mn_MASK ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Mask */ +#define ADxREGn_ADOVRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ +#define ADxREGn_ADOVRF_Mn_ON ((uint32_t)0x20000000) /*!< ADOVRF_Mn :Flag on */ +/* ADRF_Mn */ +#define ADxREGn_ADRF_Mn_MASK ((uint32_t)0x10000000) /*!< ADRF_Mn :Mask */ +#define ADxREGn_ADRF_Mn_OFF ((uint32_t)0x00000000) /*!< ADRF_Mn :Flag off. */ +#define ADxREGn_ADRF_Mn_ON ((uint32_t)0x10000000) /*!< ADRF_Mn :Flag on */ +/* ADR_Mn */ +#define ADxREGn_ADR_Mn_MASK ((uint32_t)0x0FFF0000) /*!< ADR_Mn :Mask */ +/* ADRn */ +#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0) /*!< ADRn :Mask */ +/* ADOVRFn */ +#define ADxREGn_ADOVRFn_MASK ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Mask */ +#define ADxREGn_ADOVRFn_OFF ((uint32_t)0x00000000) /*!< ADOVRF_Mn :Flag off. */ +#define ADxREGn_ADOVRFn_ON ((uint32_t)0x00000002) /*!< ADOVRF_Mn :Flag on */ +/* ADRFn */ +#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001) /*!< ADRFn :Mask */ +#define ADxREGn_ADRFn_OFF ((uint32_t)0x00000000) /*!< ADRFn :Flag off. */ +#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001) /*!< ADRFn :Flag on */ +/** + * @} + */ /* End of name ADxREGn Macro Definition */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_functions ADC Private Functions + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group ADC_Private_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_INCLUDE_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_cg.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_cg.h new file mode 100644 index 0000000..cf9e30c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_cg.h @@ -0,0 +1,124 @@ +/** + ******************************************************************************* + * @file txz_cg.h + * @brief This file provides all the functions prototypes for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __CG_H +#define __CG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup CG CG + * @brief CG Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_typedef CG Exported Typedef + * @{ + */ +/** + * @brief CG member. +*/ +/*----------------------------------*/ +typedef struct { + TSB_CG_TypeDef *p_instance; /*!< Registers base address. */ +} cg_t; + +/** + * @} + */ /* End of group CG_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ +uint32_t cg_get_fsysm(cg_t *p_obj); +uint32_t cg_get_phyt0(cg_t *p_obj); +uint32_t cg_get_mphyt0(cg_t *p_obj); +TXZ_Result cg_ihosc_enable(cg_t *p_obj); +TXZ_Result cg_ihosc_disable(cg_t *p_obj); +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __CG_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_driver_def.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_driver_def.h new file mode 100644 index 0000000..ff6376d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_driver_def.h @@ -0,0 +1,112 @@ +/** + ******************************************************************************* + * @file txz_driver_def.h + * @brief All common macro and definition for TXZ peripheral drivers + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TXZ_DRIVER_DEF_H +#define __TXZ_DRIVER_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF + * @brief All common macro and definition for TXZ peripheral drivers + * @{ + */ + +/** @defgroup Device_Header_Included Device Header Included + * @brief Include the Device header file of a Target. + * @{ + */ +#if (defined(TMPM4NR) || defined(TMPM4NQ) || defined(TMPM4NN)) +#include "TMPM4Nx.h" /*!< TMPM4Nx Group Header file. */ +#else +#error "target device is non-select." +#endif +/** + * @} + */ /* End of group Device_Header */ + + +/** @defgroup TXZ_Exported_typedef TXZ Exported typedef + * @{ + */ +typedef enum { + TXZ_SUCCESS = 0U, + TXZ_ERROR = 1U +} TXZ_Result; + +typedef enum { + TXZ_BUSY = 0U, + TXZ_DONE = 1U +} TXZ_WorkState; + +typedef enum { + TXZ_DISABLE = 0U, + TXZ_ENABLE = 1U +} TXZ_FunctionalState; +/** + * @} + */ /* End of group TXZ_Exported_typedef */ + +/** @defgroup TXZ_Exported_macro TXZ Exported macro + * @{ + */ +#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) + +/** + * @brief To report the name of the source file and source line number where the + * assert_param error has occurred, "__DEBUG__" must be defined. And detailed + * definition of assert_failed() is needed to be implemented, which can be + * done, for example, in the main.c file. + */ +#ifdef __DEBUG__ +void assert_failed(char *file, int32_t line); +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) +#else +#define assert_param(expr) +#endif /* __DEBUG__ */ +/** + * @} + */ /* End of group TXZ_Exported_macro */ + +/** + * @} + */ /* End of group Periph_Driver */ + +/** + * @} + */ /* End of group TXZ_DRIVER_DEF */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fc.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fc.h new file mode 100644 index 0000000..d9d67df --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fc.h @@ -0,0 +1,149 @@ +/** + ******************************************************************************* + * @file txz_fc.h + * @brief This file provides all the functions prototypes for FLASH. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FC_H +#define __FC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +#if defined(__FC_H) +/** @addtogroup Periph driver + * @{ + */ + +/** @defgroup fc + * @brief fc + * @{ + */ + + +/** @defgroup FlashApi_Exported_Types + * @{ + */ + +/** + * @enum fc_sr0_t + * @brief Enumerated type definition of the FCSR0 register. + */ +typedef enum { + FC_SR0_RDYBSY = (0x00000001UL) /*!< 0:Busy, 1:Ready all flash */ +} fc_sr0_t; + +/*----------------------------------*/ +/** + * @enum fc_erase_kind_t + * @brief FC Erase Flash Kind structure definenition. +*/ +/*----------------------------------*/ +typedef enum { + FC_ERASE_KIND_PAGE = (0x00000040UL), /*!< Page Erase */ + FC_ERASE_KIND_BLOCK = (0x00000030UL) /*!< Block Erase */ +} fc_erase_kind_t; + +typedef enum { + FC_CODE_FLASH_PAGE0 = 0, /*!< (0x5E000000UL), CODE FLASH Page0 */ + FC_CODE_FLASH_PAGE1, /*!< (0x5E001000UL), CODE FLASH Page1 */ + FC_CODE_FLASH_PAGE2, /*!< (0x5E002000UL), CODE FLASH Page2 */ + FC_CODE_FLASH_PAGE3, /*!< (0x5E003000UL), CODE FLASH Page3 */ + FC_CODE_FLASH_PAGE4, /*!< (0x5E004000UL), CODE FLASH Page4 */ + FC_CODE_FLASH_PAGE5, /*!< (0x5E005000UL), CODE FLASH Page5 */ + FC_CODE_FLASH_PAGE6, /*!< (0x5E006000UL), CODE FLASH Page6 */ + FC_CODE_FLASH_PAGE7, /*!< (0x5E007000UL), CODE FLASH Page7 */ + FC_CODE_FLASH_PAGE8, /*!< (0x5E008000UL), CODE FLASH Page8 */ + FC_CODE_FLASH_PAGE9, /*!< (0x5E009000UL), CODE FLASH Page9 */ + FC_CODE_FLASH_PAGE10, /*!< (0x5E00A000UL), CODE FLASH Page10 */ + FC_CODE_FLASH_PAGE11, /*!< (0x5E00B000UL), CODE FLASH Page11 */ + FC_CODE_FLASH_PAGE12, /*!< (0x5E00C000UL), CODE FLASH Page12 */ + FC_CODE_FLASH_PAGE13, /*!< (0x5E00D000UL), CODE FLASH Page13 */ + FC_CODE_FLASH_PAGE14, /*!< (0x5E00E000UL), CODE FLASH Page14 */ + FC_CODE_FLASH_PAGE15, /*!< (0x5E00F000UL), CODE FLASH Page15 */ + FC_CODE_FLASH_PAGE16, /*!< (0x5E010000UL), CODE FLASH Page16 */ + FC_CODE_FLASH_PAGE17, /*!< (0x5E011000UL), CODE FLASH Page17 */ + FC_CODE_FLASH_PAGE18, /*!< (0x5E012000UL), CODE FLASH Page18 */ + FC_CODE_FLASH_PAGE19, /*!< (0x5E013000UL), CODE FLASH Page19 */ + FC_CODE_FLASH_PAGE20, /*!< (0x5E014000UL), CODE FLASH Page20 */ + FC_CODE_FLASH_PAGE21, /*!< (0x5E015000UL), CODE FLASH Page21 */ + FC_CODE_FLASH_PAGE22, /*!< (0x5E016000UL), CODE FLASH Page22 */ + FC_CODE_FLASH_PAGE23, /*!< (0x5E017000UL), CODE FLASH Page23 */ + FC_CODE_FLASH_PAGE24, /*!< (0x5E018000UL), CODE FLASH Page24 */ + FC_CODE_FLASH_PAGE25, /*!< (0x5E019000UL), CODE FLASH Page25 */ + FC_CODE_FLASH_PAGE26, /*!< (0x5E01A000UL), CODE FLASH Page26 */ + FC_CODE_FLASH_PAGE27, /*!< (0x5E01B000UL), CODE FLASH Page27 */ + FC_CODE_FLASH_PAGE28, /*!< (0x5E01C000UL), CODE FLASH Page28 */ + FC_CODE_FLASH_PAGE29, /*!< (0x5E01D000UL), CODE FLASH Page29 */ + FC_CODE_FLASH_PAGE30, /*!< (0x5E01E000UL), CODE FLASH Page30 */ + FC_CODE_FLASH_PAGE31 /*!< (0x5E01F000UL), CODE FLASH Page31 */ +} fc_code_flash_page_number_t; + +/** @} */ +/* End of group FlashApi_Exported_Types */ + +/** @defgroup FlashApi_Exported_Constants + * @{ + */ + +//#define FC_RAMADDRESSTOP (0x20000000UL) /*!< RAM Address Top */ +//#define FC_RAMADDRESSEND (0x20003fffUL) /*!< RAM Address End */ +#define FC_CODE_FLASH_ADDRESS_TOP (0x5E000000UL) /*!< CODE FLASH Address Top */ +//#define FC_CODEFLASHADDRESSEND (0x5E01FFFFUL) /*!< CODE FLASH Address End */ +#define FC_PAGE_SIZE (0x1000) /*!< The number of bytes in a page. */ +//#define FC_CODEFLASHPAGESIZE (0x1000) /*!< CODE FLASH PAGE SIZE */ +#define FC_CODE_FLASH_WRITE_SIZE (sizeof(uint32_t)*4) /*!< CODE FLASH WRITE SIZE */ + +/** @} */ +/* End of group FlashApi_Exported_Constants */ + + + +/** @weakgroup FlashApi_Exported_FunctionPrototypes + * @{ + */ +TXZ_WorkState fc_get_status(fc_sr0_t status); +TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages); +TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t lasr_page); +TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr); + +/** @} */ +/* End of group FlashApi_Exported_FunctionPrototypes */ + + +/** @} */ +/* End of group fc */ + +/** @} */ +/* End of group Periph_driver */ + +#endif /* defined(__FC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FC_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_flash.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_flash.h new file mode 100644 index 0000000..2d3a934 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_flash.h @@ -0,0 +1,135 @@ +/** + ******************************************************************************* + * @file txz_flash.h + * @brief This file provides all the functions prototypes for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FLASH_H +#define __FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup FLASH FLASH + * @brief FLASH Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_macro FLASH Exported Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_define FLASH Exported Define + * @{ + */ +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_define FLASH Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_typedef FLASH Exported Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Exported_functions FLASH Exported Functions + * @{ + */ + +void fc_read_clock_set(uint32_t sysclock); + +/** + * @} + */ /* End of group FLASH_Exported_functions */ + +/** + * @} + */ /* End of group FLASH */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FLASH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart.h new file mode 100644 index 0000000..4fb0431 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart.h @@ -0,0 +1,555 @@ +/** + ******************************************************************************* + * @file txz_fuart.h + * @brief This file provides all the functions prototypes for FUART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_H +#define __FUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup FUART FUART + * @brief FUART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_define FUART Exported Define + * @{ + */ + +/** + * @defgroup FUART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define FUART_TX_FIFO_MAX ((uint32_t)0x00000020) /*!< TX FIFO Max. */ +#define FUART_RX_FIFO_MAX ((uint32_t)0x00000020) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup FUART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definition. + * @{ + */ +#define FUART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_CTS_ENABLE ((uint32_t)0x00008000) /*!< Available. */ +/** + * @} + */ /* End of group FUART_CTSHandshake */ + + +/** + * @defgroup FUART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definition. + * @{ + */ +#define FUART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_RTS_ENABLE ((uint32_t)0x00004000) /*!< Available. */ +/** + * @} + */ /* End of group FUART_RTSHandshake */ + +/** + * @defgroup FUART_FIFO FIFO Enable + * @brief FIFO Enable Bit Macro Definition. + * @{ + */ +#define FUART_FIFO_DISABLE ((uint32_t)0x00000000) /*!< Disable. */ +#define FUART_FIFO_ENABLE ((uint32_t)0x00000010) /*!< Enable. */ +/** + * @} + */ /* End of group FUART_FIFO */ + + +/** + * @defgroup FUART_StopBit Stop Bit + * @brief Stop Bit Macro Definition. + * @{ + */ +#define FUART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define FUART_STOP_BIT_2 ((uint32_t)0x00000008) /*!< 2 bit */ +/** + * @} + */ /* End of group FUART_StopBit */ + + +/** + * @defgroup FUART_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define FUART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define FUART_PARITY_BIT_EVEN ((uint32_t)0x00000004) /*!< Even Parity */ +/** + * @} + */ /* End of group FUART_ParityBit */ + + +/** + * @defgroup FUART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define FUART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group FUART_ParityEnable */ + +/** + * @defgroup FUART_StaticParityEnable Static Parity Enable + * @brief Enable/Disable Static Parity Macro Definition. + * @{ + */ +#define FUART_STATIC_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_STATIC_PARITY_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group FUART_ParityEnable */ + +/** + * @defgroup FUART_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define FUART_DATA_LENGTH_5 ((uint32_t)0x00000000) /*!< 5 bit */ +#define FUART_DATA_LENGTH_6 ((uint32_t)0x00000020) /*!< 6 bit */ +#define FUART_DATA_LENGTH_7 ((uint32_t)0x00000040) /*!< 7 bit */ +#define FUART_DATA_LENGTH_8 ((uint32_t)0x00000060) /*!< 8 bit */ +/** + * @} + */ /* End of group FUART_DataLength */ + +/** + * @defgroup FUART_FIFO_Level FIFO Level + * @brief FIFO Level Macro Definition. + * @{ + */ +#define FUART_FIFO_LEVEL_4 ((uint32_t)0x00000000) /*!< 4 level */ +#define FUART_FIFO_LEVEL_8 ((uint32_t)0x00000001) /*!< 8 level */ +#define FUART_FIFO_LEVEL_16 ((uint32_t)0x00000002) /*!< 16 level */ +#define FUART_FIFO_LEVEL_24 ((uint32_t)0x00000003) /*!< 24 level */ +#define FUART_FIFO_LEVEL_28 ((uint32_t)0x00000004) /*!< 28 level */ + +/** + * @} + */ /* End of group FUART_DataLength */ + +/** + * @defgroup FUART_TxInterrupt Tx Interrupt + * @brief Available Transmit Interrupt Macro Definition. + * @{ + */ +#define FUART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_TX_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group FUART_TxInterrupt */ + + +/** + * @defgroup FUART_RxInterrupt Rx Interrupt + * @brief Available Receive Interrupt Macro Definition. + * @{ + */ +#define FUART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define FUART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group FUART_RxInterrupt */ + + +/** + * @defgroup FUART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +/** + * @defgroup FUART_OVER_RUN_ErrorInterrupt Over Run Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_OV_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_OV_ERR_INT_ENABLE ((uint32_t)0x00000400) /*!< Enable */ +/** + * @} + */ /* End of group FUART_OVER_RUN_ErrorInterrupt */ + +/** + * @defgroup FUART_BREAK_ErrorInterrupt Break Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_BK_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_BK_ERR_INT_ENABLE ((uint32_t)0x00000200) /*!< Enable */ +/** + * @} + */ /* End of group FUART_BREAK_ErrorInterrupt */ + +/** + * @defgroup FUART_PARITY_ErrorInterrupt Parity Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_PA_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_PA_ERR_INT_ENABLE ((uint32_t)0x00000100) /*!< Enable */ +/** + * @} + */ /* End of group FUART_PARITY_ErrorInterrupt */ + +/** + * @defgroup FUART_FRAMING_ErrorInterrupt Framing Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_FR_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_FR_ERR_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group FUART_FRAMING_ErrorInterrupt */ + +/** + * @defgroup FUART_RX_TIMEOUT_ErrorInterrupt Rx Timeout Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define FUART_TO_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define FUART_TO_ERR_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group FUART_RX_TIMEOUT_RUN_ErrorInterrupt */ +/** + * @} + */ /* End of group FUART_ErrorInterrupt */ + + +/** + * @defgroup FUART_RangeK Range K + * @brief Range of K Macro Definition. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= FUART_RANGE_K_MAX)". + * @{ + */ +#define FUART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define FUART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group FUART_RangeK */ + + +/** + * @defgroup FUART_RangeN Range N + * @brief Range of N Macro Definition. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= FUART_RANGE_N_MAX)". + * @{ + */ +#define FUART_RANGE_N_MIN ((uint32_t)0x00000002) /*!< Minimum Value :N=2 */ +#define FUART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group FUART_RangeN */ + + +/** + * @defgroup FUART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define FUART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group FUART_OverrunErr */ + + +/** + * @defgroup FUART_BreakErr Break Error + * @brief Break Error Macro Definition. + * @{ + */ +#define FUART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_BREAK_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group FUART_BreakErr */ + + +/** + * @defgroup FUART_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define FUART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_PARITY_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group FUART_ParityErr */ + + +/** + * @defgroup FUART_FramingErr Framing Error + * @brief Framing Error Macro Definition. + * @{ + */ +#define FUART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define FUART_FRAMING_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group FUART_FramingErr */ + +/** + * @defgroup FUARTxFR FUARTxFR Register + * @brief FUARTxFR Register Definition. + * @{ + */ +/* FR */ +#define FUARTxFR_TXFE_MASK ((uint32_t)0x00000080) /*!< TXFE :Mask */ +#define FUARTxFR_RXFF_MASK ((uint32_t)0x00000040) /*!< RXFF :Mask */ +#define FUARTxFR_TXFF_MASK ((uint32_t)0x00000020) /*!< TXFF :Mask */ +#define FUARTxFR_RXFE_MASK ((uint32_t)0x00000010) /*!< RXFE :Mask */ +#define FUARTxFR_BUSY_MASK ((uint32_t)0x00000008) /*!< BUSY :Mask */ +#define FUARTxFR_CTS_MASK ((uint32_t)0x00000001) /*!< CTS :Mask */ + +#define FUARTxFR_TXFE_FLAG_SET ((uint32_t)0x00000080) /*!< TXFE :Flag Set */ +#define FUARTxFR_RXFF_FLAG_SET ((uint32_t)0x00000040) /*!< RXFF :Flag Set */ +#define FUARTxFR_TXFF_FLAG_SET ((uint32_t)0x00000020) /*!< TXFF :Flag Set */ +#define FUARTxFR_RXFE_FLAG_SET ((uint32_t)0x00000010) /*!< RXFE :Flag Set */ +#define FUARTxFR_BUSY_FLAG_SET ((uint32_t)0x00000008) /*!< BUSY :Flag Set */ +#define FUARTxFR_CTS_FLAG_SET ((uint32_t)0x00000001) /*!< CTS :Flag Set */ + +#define FUARTxFR_TXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFE :Flag Clear */ +#define FUARTxFR_RXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFF :Flag Clear */ +#define FUARTxFR_TXFF_FLAG_CLR ((uint32_t)0x00000000) /*!< TXFF :Flag Clear */ +#define FUARTxFR_RXFE_FLAG_CLR ((uint32_t)0x00000000) /*!< RXFE :Flag Clear */ +#define FUARTxFR_BUSY_FLAG_CLR ((uint32_t)0x00000000) /*!< BUSY :Flag Clear */ +#define FUARTxFR_CTS_FLAG_CLR ((uint32_t)0x00000000) /*!< CTS :Flag Clear */ +/** + * @} + */ /* End of group FUARTxFR */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_define FUART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_typedef FUART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} fuart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} fuart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brk; /*!< Division Value K. + : K Range ( FUART_RANGE_K_MIN <= K =< FUART_RANGE_K_MAX ) @ref FUART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( FUART_RANGE_N_MIN <= N =< FUART_RANGE_N_MAX ) @ref FUART_RangeN */ +} fuart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref FUART_TxInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Use @ref FUART_FIFO_Level */ +} fuart_tx_int_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref FUART_RxInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Use @ref FUART_FIFO_Level */ +} fuart_rx_int_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + fuart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref fuart_boudrate_t */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref FUART_ErrorInterrupt */ + fuart_tx_int_t tx_int; /*!< Transmit Interrupt setting. + : Use @ref fuart_tx_int_t */ + fuart_rx_int_t rx_int; /*!< Receive Interrupt setting. + : Use @ref fuart_rx_int_t */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref FUART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref FUART_RTSHandshake */ + uint32_t stpa; /*!< Enable/Disable Static Parity. + : Use @ref FUART_StaticParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref FUART_DataLength */ + uint32_t fifo; /*!< Available FIFO. + : Use @ref FUART_FIFO */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref FUART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref FUART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref FUART_ParityEnable */ +} fuart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief FUART handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_FURT_TypeDef *p_instance; /*!< Registers base address. */ + fuart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + fuart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + uint32_t wp; /*!< Num of received data. */ + fuart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, fuart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} fuart_t; + +/** + * @} + */ /* End of group FUART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Exported_functions FUART Exported Functions + * @{ + */ +TXZ_Result fuart_init(fuart_t *p_obj); +TXZ_Result fuart_deinit(fuart_t *p_obj); +TXZ_Result fuart_discard_transmit(fuart_t *p_obj); +TXZ_Result fuart_discard_receive(fuart_t *p_obj); +TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info); +TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info); +void fuart_transmit_irq_handler(fuart_t *p_obj); +void fuart_receive_irq_handler(fuart_t *p_obj); +void fuart_error_irq_handler(fuart_t *p_obj); +void fuart_irq_handler(fuart_t *p_obj); +TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status); +TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error); +TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_setting); +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart_ex.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart_ex.h new file mode 100644 index 0000000..038eb33 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart_ex.h @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * @file txz_fuart_ex.h + * @brief This file provides all the functions prototypes for FUART driver. + * @brief Extended functionality. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_EX_H +#define __FUART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +#include "txz_fuart.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +TXZ_Result fuart_send_break(fuart_t *p_obj); +TXZ_Result fuart_stop_break(fuart_t *p_obj); +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __FUART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart_include.h new file mode 100644 index 0000000..a20a88c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_fuart_include.h @@ -0,0 +1,398 @@ +/** + ******************************************************************************* + * @file txz_fuart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FUART_INCLUDE_H +#define __FUART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/** + * @defgroup FUART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define FUART_NULL ((void *)0) /*!< Null Pointer. */ +/** + * @} + */ /* End of group FUART_NullPointer */ + +/** + * @defgroup FUART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define FUART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define FUART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group FUART_ParameterResult */ + +/** + * @defgroup FUARTxDR FUARTxDR Register + * @brief FUARTxDR Register Definition. + * @{ + */ +/* DR */ +#define FUARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of group FUARTxDR */ + +/** + * @defgroup FUARTxCR FUARTxCR Register + * @brief FUARTxCR Register Definition. + * @{ + */ +#define FUARTxCR_CTSEN_MASK ((uint32_t)0x00008000) /*!< CTSEN :MASK. */ +#define FUARTxCR_RTSEN_MASK ((uint32_t)0x00004000) /*!< RTSEN :MASK. */ +#define FUARTxCR_RXE_MASK ((uint32_t)0x00000200) /*!< RXE :MASK. */ +#define FUARTxCR_TXE_MASK ((uint32_t)0x00000100) /*!< TXE :MASK. */ +#define FUARTxCR_UARTEN_MSK ((uint32_t)0x00000001) /*!< UARTEN :MASK. */ + +#define FUARTxCR_CTSEN_DISABLE ((uint32_t)0x00000000) /*!< CTSEN :Not Available. */ +#define FUARTxCR_RTSEN_DISABLE ((uint32_t)0x00000000) /*!< RTSEN :Not Available. */ +#define FUARTxCR_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable. */ +#define FUARTxCR_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable. */ +#define FUARTxCR_UARTEN_DISABLE ((uint32_t)0x00000000) /*!< UARTEN :Disable. */ + +#define FUARTxCR_CTSEN_ENABLE ((uint32_t)0x00008000) /*!< CTSEN :Available. */ +#define FUARTxCR_RTSEN_ENABLE ((uint32_t)0x00004000) /*!< RTSEN :Available. */ +#define FUARTxCR_RXE_ENABLE ((uint32_t)0x00000200) /*!< RXE :Enable. */ +#define FUARTxCR_TXE_ENABLE ((uint32_t)0x00000100) /*!< TXE :Enable. */ +#define FUARTxCR_UARTEN_ENABLE ((uint32_t)0x00000001) /*!< UARTEN :Enable. */ +/** + * @} + */ /* End of group FUARTxRSR */ + +/** + * @defgroup FUARTxRSR FUARTxRSR Register + * @brief FUARTxRSR Register Definition. + * @{ + */ +#define FUARTxRSR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ +#define FUARTxRSR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ +#define FUARTxRSR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ +#define FUARTxRSR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ + +#define FUARTxRSR_OE_ERR ((uint32_t)0x00000008) /*!< OE :Error */ +#define FUARTxRSR_BE_ERR ((uint32_t)0x00000004) /*!< BE :Error */ +#define FUARTxRSR_PE_ERR ((uint32_t)0x00000002) /*!< PE :Error */ +#define FUARTxRSR_FE_ERR ((uint32_t)0x00000001) /*!< FE :Error */ +/** + * @} + */ /* End of group FUARTxRSR */ + +/** + * @defgroup FUARTxECR FUARTxECR Register + * @brief FUARTxECR Register Definition. + * @{ + */ +/* ECR */ +#define FUARTxECR_OE_MASK ((uint32_t)0x00000008) /*!< OE :Mask */ +#define FUARTxECR_BE_MASK ((uint32_t)0x00000004) /*!< BE :Mask */ +#define FUARTxECR_PE_MASK ((uint32_t)0x00000002) /*!< PE :Mask */ +#define FUARTxECR_FE_MASK ((uint32_t)0x00000001) /*!< FE :Mask */ + +#define FUARTxECR_OE_CLR ((uint32_t)0x00000008) /*!< OE :Clear */ +#define FUARTxECR_BE_CLR ((uint32_t)0x00000004) /*!< BE :Clear */ +#define FUARTxECR_PE_CLR ((uint32_t)0x00000002) /*!< PE :Clear */ +#define FUARTxECR_FE_CLR ((uint32_t)0x00000001) /*!< FE :Clear */ + +/** + * @} + */ /* End of group FUARTxECR */ + +/** + * @defgroup FUARTxLCR_H FUARTxRSR Register + * @brief FUARTxLCR_H Register Definition. + * @{ + */ +#define FUARTxLCR_H_BRK_MASK ((uint32_t)0x00000001) /*!< BRK :Mask */ + +#define FUARTxLCR_H_BRK_SEND ((uint32_t)0x00000001) /*!< BRK :Send */ +#define FUARTxLCR_H_BRK_STOP ((uint32_t)0x00000000) /*!< BRK :Stop */ +/** + * @} + */ /* End of group FUARTxLCR_H */ + +/** + * @defgroup FUARTxRIS FUARTxRIS Register + * @brief FUARTxRIS Register Definition. + * @{ + */ +#define FUARTxRIS_OERIS_MASK ((uint32_t)0x00000400) /*!< OERIS :Mask */ +#define FUARTxRIS_BERIS_MASK ((uint32_t)0x00000200) /*!< BERIS :Mask */ +#define FUARTxRIS_PERIS_MASK ((uint32_t)0x00000100) /*!< PRRIS :Mask */ +#define FUARTxRIS_FERIS_MASK ((uint32_t)0x00000080) /*!< FERIS :Mask */ +#define FUARTxRIS_RTRIS_MASK ((uint32_t)0x00000040) /*!< RTRIS :Mask */ +#define FUARTxRIS_TXRIS_MASK ((uint32_t)0x00000020) /*!< TXRIS :Mask */ +#define FUARTxRIS_RXRIS_MASK ((uint32_t)0x00000010) /*!< RXRIS :Mask */ + +#define FUARTxRIS_OERIS_REQ ((uint32_t)0x00000400) /*!< OERIS :Request */ +#define FUARTxRIS_BERIS_REQ ((uint32_t)0x00000200) /*!< BERIS :Request */ +#define FUARTxRIS_PERIS_REQ ((uint32_t)0x00000100) /*!< PRRIS :Request */ +#define FUARTxRIS_FERIS_REQ ((uint32_t)0x00000080) /*!< FERIS :Request */ +#define FUARTxRIS_RTRIS_REQ ((uint32_t)0x00000040) /*!< RTRIS :Request */ +#define FUARTxRIS_TXRIS_REQ ((uint32_t)0x00000020) /*!< TXRIS :Request */ +#define FUARTxRIS_RXRIS_REQ ((uint32_t)0x00000010) /*!< RXRIS :Request */ + +/** + * @} + */ /* End of group FUARTxRIS */ + +/** + * @defgroup FUARTxMIS FUARTxMIS Register + * @brief FUARTxMIS Register Definition. + * @{ + */ +#define FUARTxMIS_OEMIS_MASK ((uint32_t)0x00000400) /*!< OEMIS :Mask */ +#define FUARTxMIS_BEMIS_MASK ((uint32_t)0x00000200) /*!< BEMIS :Mask */ +#define FUARTxMIS_PEMIS_MASK ((uint32_t)0x00000100) /*!< PRMIS :Mask */ +#define FUARTxMIS_FEMIS_MASK ((uint32_t)0x00000080) /*!< FEMIS :Mask */ +#define FUARTxMIS_RTMIS_MASK ((uint32_t)0x00000040) /*!< RTMIS :Mask */ +#define FUARTxMIS_TXMIS_MASK ((uint32_t)0x00000020) /*!< TXMIS :Mask */ +#define FUARTxMIS_RXMIS_MASK ((uint32_t)0x00000010) /*!< RXMIS :Mask */ + +#define FUARTxMIS_OEMIS_REQ ((uint32_t)0x00000400) /*!< OEMIS :Request */ +#define FUARTxMIS_BEMIS_REQ ((uint32_t)0x00000200) /*!< BEMIS :Request */ +#define FUARTxMIS_PEMIS_REQ ((uint32_t)0x00000100) /*!< PRMIS :Request */ +#define FUARTxMIS_FEMIS_REQ ((uint32_t)0x00000080) /*!< FEMIS :Request */ +#define FUARTxMIS_RTMIS_REQ ((uint32_t)0x00000040) /*!< RTMIS :Request */ +#define FUARTxMIS_TXMIS_REQ ((uint32_t)0x00000020) /*!< TXMIS :Request */ +#define FUARTxMIS_RXMIS_REQ ((uint32_t)0x00000010) /*!< RXMIS :Request */ + +/** + * @} + */ /* End of group FUARTxMIS */ + +/** + * @defgroup FUARTxICR FUARTxICR Register + * @brief FUARTxICR Register Definition. + * @{ + */ +#define FUARTxICR_OEIC_MASK ((uint32_t)0x00000400) /*!< OEIC :Mask */ +#define FUARTxICR_BEIC_MASK ((uint32_t)0x00000200) /*!< BEIC :Mask */ +#define FUARTxICR_PEIC_MASK ((uint32_t)0x00000100) /*!< PRIC :Mask */ +#define FUARTxICR_FEIC_MASK ((uint32_t)0x00000080) /*!< FEIC :Mask */ +#define FUARTxICR_RTIC_MASK ((uint32_t)0x00000040) /*!< RTIC :Mask */ +#define FUARTxICR_TXIC_MASK ((uint32_t)0x00000020) /*!< TXIC :Mask */ +#define FUARTxICR_RXIC_MASK ((uint32_t)0x00000010) /*!< RXIC :Mask */ + +#define FUARTxICR_OEIC_CLR ((uint32_t)0x00000400) /*!< OEIC :Request */ +#define FUARTxICR_BEIC_CLR ((uint32_t)0x00000200) /*!< BEIC :Request */ +#define FUARTxICR_PEIC_CLR ((uint32_t)0x00000100) /*!< PRIC :Request */ +#define FUARTxICR_FEIC_CLR ((uint32_t)0x00000080) /*!< FEIC :Request */ +#define FUARTxICR_RTIC_CLR ((uint32_t)0x00000040) /*!< RTIC :Request */ +#define FUARTxICR_TXIC_CLR ((uint32_t)0x00000020) /*!< TXIC :Request */ +#define FUARTxICR_RXIC_CLR ((uint32_t)0x00000010) /*!< RXIC :Request */ + +/** + * @} + */ /* End of group FUARTxICR */ + +/** + * @defgroup FUARTxDMACR FUARTxDMACR Register + * @brief FUARTxDMACR Register Definition. + * @{ + */ +#define FUARTxDMACR_RXDMAE_MASK ((uint32_t)0x00000001) /*!< RXDMAE :Mask */ +#define FUARTxDMACR_TXDMAE_MASK ((uint32_t)0x00000002) /*!< TXDMAE :Mask */ + +#define FUARTxDMACR_RXDMAE_ENABLE ((uint32_t)0x00000001) /*!< RXDMAE :Enable */ +#define FUARTxDMACR_TXDMAE_ENABLE ((uint32_t)0x00000002) /*!< TXDMAE :Enable */ + +#define FUARTxDMACR_RXDMAE_DISABLE ((uint32_t)0x00000000) /*!< RXDMAE :Disable */ +#define FUARTxDMACR_TXDMAE_DISABLE ((uint32_t)0x00000000) /*!< TXDMAE :Disable */ +/** + * @} + */ /* End of group FUARTxDMACR */ + + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_functions + * @{ + */ +__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); +__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable FUARTxCR TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable FUARTxCR TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_FUARTxCR_TXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 8))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable FUARTxCR RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable FUARTxCR RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_FUARTxCR_RXE(TSB_FURT_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->CR, 9))) = 1; +#endif +} + + +/** + * @} + */ /* End of group FUART_Private_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_gpio.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_gpio.h new file mode 100644 index 0000000..4f75420 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_gpio.h @@ -0,0 +1,199 @@ +/** + ******************************************************************************* + * @file txz_gpio.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_H +#define __GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +/** @defgroup Device_Included Device Included + * @{ + */ +#if defined(TMPM4NR) +#include "txz_gpio_M4NR.h" +#elif defined(TMPM4NQ) +#include "txz_gpio_M4NQ.h" +#elif defined(TMPM4NN) +#include "txz_gpio_M4NN.h" +#else +#error "target device is non-select." +#endif + +/** + * @} + */ /* End of group Device_Included */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ +#define CHECK_MASK(mode, mask) ((1 << ((mode)/4)) & (mask)) +#define WRITE_PORT(mode, addr, val, mask) \ + do { \ + if(CHECK_MASK(mode, mask)) *((uint32_t*)(addr) + (mode)/4) = (val); \ + }while(0) +#define READ_PORT(mode, addr, val, mask) \ + do { \ + if(CHECK_MASK(mode, mask)) (*(val)) = (*((uint32_t*)(addr) + (mode)/4)); \ + }while(0) + +/** + * @defgroup GPIO_Result Result + * @brief GPIO Result Macro Definition. + * @{ + */ +#define GPIO_RESULT_SUCCESS (0) /*!< Success */ +#define GPIO_RESULT_FAILURE (-1) /*!< Failure */ +#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group GPIO_Result */ + +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_pinstate_t + * @brief Pin State Reset/Set Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_RESET = 0, /*!< 0: Clear */ + GPIO_PIN_SET, /*!< 1: Set */ +} gpio_pinstate_t; + +/** + * @enum gpio_pininout_t + * @brief Pin Input/Output Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_INPUT = 0, /*!< 0: Input */ + GPIO_PIN_OUTPUT, /*!< 1: Output */ + GPIO_PIN_INOUT, /*!< 2: Input/Output */ + GPIO_PIN_NOTINOUT, /*!< 3: Not Input/Output */ +} gpio_pininout_t; + +/** + * @enum gpio_mode_t + * @brief Port Mode Enumerated Type Definition. + */ +typedef enum { + GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */ + GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */ + GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */ + GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */ + GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */ + GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */ + GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */ + GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */ + GPIO_Mode_FR7 = 0x20, /*!< 0x20: PxFR7 */ + GPIO_Mode_FR8 = 0x24, /*!< 0x24: PxFR8 */ + GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */ + GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */ + GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */ + GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */ +} gpio_mode_t; + +/** + * @enum gpio_mode_num + * @brief Port Mode Enumerated Num(bit num). + */ +typedef enum { + GPIO_ModeNum_DATA = 0, /*!< 0: PxDATA */ + GPIO_ModeNum_CR, /*!< 1: PxCR */ + GPIO_ModeNum_FR1, /*!< 2: PxFR1 */ + GPIO_ModeNum_FR2, /*!< 3: PxFR2 */ + GPIO_ModeNum_FR3, /*!< 4: PxFR3 */ + GPIO_ModeNum_FR4, /*!< 5: PxFR4 */ + GPIO_ModeNum_FR5, /*!< 6: PxFR5 */ + GPIO_ModeNum_FR6, /*!< 7: PxFR6 */ + GPIO_ModeNum_FR7, /*!< 8: PxFR7 */ + GPIO_ModeNum_FR8, /*!< 9: PxFR8 */ + GPIO_ModeNum_OD, /*!< 10: PxOD */ + GPIO_ModeNum_PUP, /*!< 11: PxPUP */ + GPIO_ModeNum_PDN, /*!< 12: PxPDN */ + GPIO_ModeNum_IE, /*!< 13: PxIE */ + GPIO_ModeNum_Max, /*!< 14: Max */ +} gpio_mode_num; +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_functions GPIO Exported Functions + * @{ + */ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val); +TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout); +TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val); +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate); + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +#ifdef __cplusplus +} +#endif +#endif /* __GPIO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_gpio_M4NR.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_gpio_M4NR.h new file mode 100644 index 0000000..b09f52d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_gpio_M4NR.h @@ -0,0 +1,2673 @@ +/** + ******************************************************************************* + * @file txz_gpio_M4NR.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_M4NR_H +#define __GPIO_M4NR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup GPIO GPIO + * @brief GPIO Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ +/*PinExist define*/ +/* PortA */ +#define GPIO_PORT_A_0 (0x3DDF) +#define GPIO_PORT_A_1 (0x3D57) +#define GPIO_PORT_A_2 (0x3F17) +#define GPIO_PORT_A_3 (0x3DDF) +#define GPIO_PORT_A_4 (0x3DDF) +#define GPIO_PORT_A_5 (0x3DD7) +#define GPIO_PORT_A_6 (0x3F97) +#define GPIO_PORT_A_7 (0x3DDF) +/* PortB */ +#define GPIO_PORT_B_0 (0x3CFF) +#define GPIO_PORT_B_1 (0x3CDF) +#define GPIO_PORT_B_2 (0x3CD7) +#define GPIO_PORT_B_3 (0x3C97) +#define GPIO_PORT_B_4 (0x0000) +#define GPIO_PORT_B_5 (0x0000) +#define GPIO_PORT_B_6 (0x0000) +#define GPIO_PORT_B_7 (0x0000) +/* PortC */ +#define GPIO_PORT_C_0 (0x0000) +#define GPIO_PORT_C_1 (0x0000) +#define GPIO_PORT_C_2 (0x0000) +#define GPIO_PORT_C_3 (0x0000) +#define GPIO_PORT_C_4 (0x3C57) +#define GPIO_PORT_C_5 (0x3C17) +#define GPIO_PORT_C_6 (0x3C07) +#define GPIO_PORT_C_7 (0x3C07) +/* PortD */ +#define GPIO_PORT_D_0 (0x3DFF) +#define GPIO_PORT_D_1 (0x3D7F) +#define GPIO_PORT_D_2 (0x3F77) +#define GPIO_PORT_D_3 (0x3F37) +#define GPIO_PORT_D_4 (0x3FD7) +#define GPIO_PORT_D_5 (0x3F97) +#define GPIO_PORT_D_6 (0x3FDF) +#define GPIO_PORT_D_7 (0x3FDF) +/* PortE */ +#define GPIO_PORT_E_0 (0x3FFF) +#define GPIO_PORT_E_1 (0x3FF7) +#define GPIO_PORT_E_2 (0x3FF7) +#define GPIO_PORT_E_3 (0x3FF7) +#define GPIO_PORT_E_4 (0x3EF7) +#define GPIO_PORT_E_5 (0x3EF7) +#define GPIO_PORT_E_6 (0x3EF7) +#define GPIO_PORT_E_7 (0x3EFF) +/* PortF */ +#define GPIO_PORT_F_0 (0x3C07) +#define GPIO_PORT_F_1 (0x3C07) +#define GPIO_PORT_F_2 (0x3D83) +#define GPIO_PORT_F_3 (0x3D83) +#define GPIO_PORT_F_4 (0x3C07) +#define GPIO_PORT_F_5 (0x3C87) +#define GPIO_PORT_F_6 (0x3C87) +#define GPIO_PORT_F_7 (0x3CE7) +/* PortG */ +#define GPIO_PORT_G_0 (0x3E57) +#define GPIO_PORT_G_1 (0x3E57) +#define GPIO_PORT_G_2 (0x3FF3) +#define GPIO_PORT_G_3 (0x3FF3) +#define GPIO_PORT_G_4 (0x3FEB) +#define GPIO_PORT_G_5 (0x3FFB) +#define GPIO_PORT_G_6 (0x3CE7) +#define GPIO_PORT_G_7 (0x3E67) +/* PortH */ +#define GPIO_PORT_H_0 (0x3E77) +#define GPIO_PORT_H_1 (0x3C77) +#define GPIO_PORT_H_2 (0x3C77) +#define GPIO_PORT_H_3 (0x3C77) +#define GPIO_PORT_H_4 (0x3C57) +#define GPIO_PORT_H_5 (0x3C57) +#define GPIO_PORT_H_6 (0x3C57) +#define GPIO_PORT_H_7 (0x3C57) +/* PortJ */ +#define GPIO_PORT_J_0 (0x3C53) +#define GPIO_PORT_J_1 (0x3C53) +#define GPIO_PORT_J_2 (0x3DD3) +#define GPIO_PORT_J_3 (0x3DD3) +#define GPIO_PORT_J_4 (0x3C5B) +#define GPIO_PORT_J_5 (0x3C5B) +#define GPIO_PORT_J_6 (0x3DC3) +#define GPIO_PORT_J_7 (0x3DC3) +/* PortK */ +#define GPIO_PORT_K_0 (0x3E9F) +#define GPIO_PORT_K_1 (0x3CFF) +#define GPIO_PORT_K_2 (0x3E87) +#define GPIO_PORT_K_3 (0x3E87) +#define GPIO_PORT_K_4 (0x3EA7) +#define GPIO_PORT_K_5 (0x3EA7) +#define GPIO_PORT_K_6 (0x3EBF) +#define GPIO_PORT_K_7 (0x3FBB) +/* PortL */ +#define GPIO_PORT_L_0 (0x3FDB) +#define GPIO_PORT_L_1 (0x3F43) +#define GPIO_PORT_L_2 (0x3F43) +#define GPIO_PORT_L_3 (0x3FDB) +#define GPIO_PORT_L_4 (0x3C1B) +#define GPIO_PORT_L_5 (0x3C0B) +#define GPIO_PORT_L_6 (0x3C1B) +#define GPIO_PORT_L_7 (0x3C0F) +/* PortM */ +#define GPIO_PORT_M_0 (0x3FE7) +#define GPIO_PORT_M_1 (0x3FF7) +#define GPIO_PORT_M_2 (0x3FDB) +#define GPIO_PORT_M_3 (0x3FEB) +#define GPIO_PORT_M_4 (0x3DAB) +#define GPIO_PORT_M_5 (0x3D9B) +#define GPIO_PORT_M_6 (0x3DFF) +#define GPIO_PORT_M_7 (0x3DEF) +/* PortN */ +#define GPIO_PORT_N_0 (0x3C03) +#define GPIO_PORT_N_1 (0x3C03) +#define GPIO_PORT_N_2 (0x3C03) +#define GPIO_PORT_N_3 (0x3C03) +#define GPIO_PORT_N_4 (0x3C03) +#define GPIO_PORT_N_5 (0x3C03) +#define GPIO_PORT_N_6 (0x3C03) +#define GPIO_PORT_N_7 (0x3C03) +/* PortP */ +#define GPIO_PORT_P_0 (0x3C5B) +#define GPIO_PORT_P_1 (0x3C5B) +#define GPIO_PORT_P_2 (0x3C5B) +#define GPIO_PORT_P_3 (0x3C5B) +#define GPIO_PORT_P_4 (0x3C5B) +#define GPIO_PORT_P_5 (0x3C5B) +#define GPIO_PORT_P_6 (0x3C5B) +#define GPIO_PORT_P_7 (0x3C5B) +/* PortR */ +#define GPIO_PORT_R_0 (0x3C1B) +#define GPIO_PORT_R_1 (0x3C1B) +#define GPIO_PORT_R_2 (0x3C1B) +#define GPIO_PORT_R_3 (0x3C1B) +#define GPIO_PORT_R_4 (0x3C1B) +#define GPIO_PORT_R_5 (0x3C1B) +#define GPIO_PORT_R_6 (0x3C1B) +#define GPIO_PORT_R_7 (0x3C1B) +/* PortT */ +#define GPIO_PORT_T_0 (0x3C03) +#define GPIO_PORT_T_1 (0x3C03) +#define GPIO_PORT_T_2 (0x3D03) +#define GPIO_PORT_T_3 (0x3C9F) +#define GPIO_PORT_T_4 (0x3E03) +#define GPIO_PORT_T_5 (0x3C0B) +#define GPIO_PORT_T_6 (0x0000) +#define GPIO_PORT_T_7 (0x0000) +/* PortU */ +#define GPIO_PORT_U_0 (0x3D5B) +#define GPIO_PORT_U_1 (0x0000) +#define GPIO_PORT_U_2 (0x3D9B) +#define GPIO_PORT_U_3 (0x3DDB) +#define GPIO_PORT_U_4 (0x3D9B) +#define GPIO_PORT_U_5 (0x3D9B) +#define GPIO_PORT_U_6 (0x3F9B) +#define GPIO_PORT_U_7 (0x3F8B) +/* PortV */ +#define GPIO_PORT_V_0 (0x3FDB) +#define GPIO_PORT_V_1 (0x3FDB) +#define GPIO_PORT_V_2 (0x3FDB) +#define GPIO_PORT_V_3 (0x3FCB) +#define GPIO_PORT_V_4 (0x3FEF) +#define GPIO_PORT_V_5 (0x3FFF) +#define GPIO_PORT_V_6 (0x3D7B) +#define GPIO_PORT_V_7 (0x3DEB) +/* PortW */ +#define GPIO_PORT_W_0 (0x3CE3) +#define GPIO_PORT_W_1 (0x3D63) +#define GPIO_PORT_W_2 (0x3D63) +#define GPIO_PORT_W_3 (0x3C63) +#define GPIO_PORT_W_4 (0x3D53) +#define GPIO_PORT_W_5 (0x3D43) +#define GPIO_PORT_W_6 (0x3D43) +#define GPIO_PORT_W_7 (0x3D53) +/* PortY */ +#define GPIO_PORT_Y_0 (0x3801) +#define GPIO_PORT_Y_1 (0x3801) +#define GPIO_PORT_Y_2 (0x3801) +#define GPIO_PORT_Y_3 (0x3801) +#define GPIO_PORT_Y_4 (0x1CA7) +#define GPIO_PORT_Y_5 (0x0000) +#define GPIO_PORT_Y_6 (0x0000) +#define GPIO_PORT_Y_7 (0x0000) + +/* Port Register setting */ +#define PORT_CLOCK_DISABLE_PORTA(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTB(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTC(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTD(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTE(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTF(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTG(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTH(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTJ(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTK(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTL(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTM(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTN(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTP(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTR(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTT(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTU(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTV(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTW(var) ((var) = 0U) +#define PORT_CLOCK_DISABLE_PORTY(var) ((var) = 0U) + +#define PORT_CLOCK_ENABLE_PORTA(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTB(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTC(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTD(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTE(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTF(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTG(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTH(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTJ(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTK(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTL(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTM(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTN(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTP(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTR(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTT(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTU(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTV(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTW(var) ((var) = 1U) +#define PORT_CLOCK_ENABLE_PORTY(var) ((var) = 1U) + +/* PortA */ +#define INIT_GPIO_PORT_A_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR4(var) +#define INIT_GPIO_PORT_A_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_A_IE(var) ((var) = 0x00) +/* PortB */ +#define INIT_GPIO_PORT_B_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_FR7(var) +#define INIT_GPIO_PORT_B_FR8(var) +#define INIT_GPIO_PORT_B_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_B_IE(var) ((var) = 0x00) +/* PortC */ +#define INIT_GPIO_PORT_C_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR2(var) +#define INIT_GPIO_PORT_C_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR4(var) +#define INIT_GPIO_PORT_C_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_FR6(var) +#define INIT_GPIO_PORT_C_FR7(var) +#define INIT_GPIO_PORT_C_FR8(var) +#define INIT_GPIO_PORT_C_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_C_IE(var) ((var) = 0x00) +/* PortD */ +#define INIT_GPIO_PORT_D_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_D_IE(var) ((var) = 0x00) +/* PortE */ +#define INIT_GPIO_PORT_E_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_E_IE(var) ((var) = 0x00) +/* PortF */ +#define INIT_GPIO_PORT_F_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR2(var) +#define INIT_GPIO_PORT_F_FR3(var) +#define INIT_GPIO_PORT_F_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_FR8(var) +#define INIT_GPIO_PORT_F_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_F_IE(var) ((var) = 0x00) +/* PortG */ +#define INIT_GPIO_PORT_G_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_G_IE(var) ((var) = 0x00) +/* PortH */ +#define INIT_GPIO_PORT_H_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_CR(var) ((var) = 0x50) +#define INIT_GPIO_PORT_H_FR1(var) ((var) = 0xF8) +#define INIT_GPIO_PORT_H_FR2(var) +#define INIT_GPIO_PORT_H_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_FR6(var) +#define INIT_GPIO_PORT_H_FR7(var) +#define INIT_GPIO_PORT_H_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_H_PUP(var) ((var) = 0x98) +#define INIT_GPIO_PORT_H_PDN(var) ((var) = 0x20) +#define INIT_GPIO_PORT_H_IE(var) ((var) = 0xB8) +/* PortJ */ +#define INIT_GPIO_PORT_J_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR1(var) +#define INIT_GPIO_PORT_J_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR4(var) +#define INIT_GPIO_PORT_J_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_FR8(var) +#define INIT_GPIO_PORT_J_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_J_IE(var) ((var) = 0x00) +/* PortK */ +#define INIT_GPIO_PORT_K_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_K_IE(var) ((var) = 0x00) +/* PortL */ +#define INIT_GPIO_PORT_L_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR4(var) +#define INIT_GPIO_PORT_L_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_L_IE(var) ((var) = 0x00) +/* PortM */ +#define INIT_GPIO_PORT_M_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_M_IE(var) ((var) = 0x00) +/* PortN */ +#define INIT_GPIO_PORT_N_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_FR1(var) +#define INIT_GPIO_PORT_N_FR2(var) +#define INIT_GPIO_PORT_N_FR3(var) +#define INIT_GPIO_PORT_N_FR4(var) +#define INIT_GPIO_PORT_N_FR5(var) +#define INIT_GPIO_PORT_N_FR6(var) +#define INIT_GPIO_PORT_N_FR7(var) +#define INIT_GPIO_PORT_N_FR8(var) +#define INIT_GPIO_PORT_N_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_N_IE(var) ((var) = 0x00) +/* PortP */ +#define INIT_GPIO_PORT_P_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR1(var) +#define INIT_GPIO_PORT_P_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR4(var) +#define INIT_GPIO_PORT_P_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_FR6(var) +#define INIT_GPIO_PORT_P_FR7(var) +#define INIT_GPIO_PORT_P_FR8(var) +#define INIT_GPIO_PORT_P_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_P_IE(var) ((var) = 0x00) +/* PortR */ +#define INIT_GPIO_PORT_R_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR1(var) +#define INIT_GPIO_PORT_R_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_FR4(var) +#define INIT_GPIO_PORT_R_FR5(var) +#define INIT_GPIO_PORT_R_FR6(var) +#define INIT_GPIO_PORT_R_FR7(var) +#define INIT_GPIO_PORT_R_FR8(var) +#define INIT_GPIO_PORT_R_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_R_IE(var) ((var) = 0x00) +/* PortT */ +#define INIT_GPIO_PORT_T_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR4(var) +#define INIT_GPIO_PORT_T_FR5(var) +#define INIT_GPIO_PORT_T_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_T_IE(var) ((var) = 0x00) +/* PortU */ +#define INIT_GPIO_PORT_U_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR1(var) +#define INIT_GPIO_PORT_U_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR4(var) +#define INIT_GPIO_PORT_U_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_U_IE(var) ((var) = 0x00) +/* PortV */ +#define INIT_GPIO_PORT_V_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR2(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_FR8(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_V_IE(var) ((var) = 0x00) +/* PortW */ +#define INIT_GPIO_PORT_W_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR1(var) +#define INIT_GPIO_PORT_W_FR2(var) +#define INIT_GPIO_PORT_W_FR3(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR5(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR7(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_FR8(var) +#define INIT_GPIO_PORT_W_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_W_IE(var) ((var) = 0x00) +/* PortY */ +#define INIT_GPIO_PORT_Y_DATA(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_CR(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR1(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR2(var) +#define INIT_GPIO_PORT_Y_FR3(var) +#define INIT_GPIO_PORT_Y_FR4(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR5(var) +#define INIT_GPIO_PORT_Y_FR6(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_FR7(var) +#define INIT_GPIO_PORT_Y_FR8(var) +#define INIT_GPIO_PORT_Y_OD(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_PUP(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_PDN(var) ((var) = 0x00) +#define INIT_GPIO_PORT_Y_IE(var) ((var) = 0x00) +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_gr_t + * @brief Port Group Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_A = 0x0, /*!< 0: PA */ + GPIO_PORT_B, /*!< 1: PB */ + GPIO_PORT_C, /*!< 2: PC */ + GPIO_PORT_D, /*!< 3: PD */ + GPIO_PORT_E, /*!< 4: PE */ + GPIO_PORT_F, /*!< 5: PF */ + GPIO_PORT_G, /*!< 6: PG */ + GPIO_PORT_H, /*!< 7: PH */ + GPIO_PORT_J, /*!< 8: PJ */ + GPIO_PORT_K, /*!< 9: PK */ + GPIO_PORT_L, /*!< 10:PL */ + GPIO_PORT_M, /*!< 11: PM */ + GPIO_PORT_N, /*!< 12: PN */ + GPIO_PORT_P, /*!< 13: PP */ + GPIO_PORT_R, /*!< 14: PR */ + GPIO_PORT_T, /*!< 15: PT */ + GPIO_PORT_U, /*!< 16: PU */ + GPIO_PORT_V, /*!< 17: PV */ + GPIO_PORT_W, /*!< 18: PW */ + GPIO_PORT_Y, /*!< 19: PY */ + GPIO_GROUP_Max /*!< Max Number */ +} gpio_gr_t; + +/** + * @enum gpio_num_t + * @brief Port Number Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_0 = 0x0, /*!< 0: Port0 */ + GPIO_PORT_1, /*!< 1: Port1 */ + GPIO_PORT_2, /*!< 2: Port2 */ + GPIO_PORT_3, /*!< 3: Port3 */ + GPIO_PORT_4, /*!< 4: Port4 */ + GPIO_PORT_5, /*!< 5: Port5 */ + GPIO_PORT_6, /*!< 6: Port6 */ + GPIO_PORT_7, /*!< 7: Port7 */ + GPIO_PORT_Max /*!< Max Number */ +} gpio_num_t; + +/** + * @enum gpio_fr_t + * @brief Port Function Number Enumerated Type Definition. + */ +typedef enum { + GPIO_FR_1 = 1, /*!< 1: PxFR1 */ + GPIO_FR_2, /*!< 2: PxFR2 */ + GPIO_FR_3, /*!< 3: PxFR3 */ + GPIO_FR_4, /*!< 4: PxFR4 */ + GPIO_FR_5, /*!< 5: PxFR5 */ + GPIO_FR_6, /*!< 6: PxFR6 */ + GPIO_FR_7, /*!< 7: PxFR7 */ + GPIO_FR_8, /*!< 8: PxFR8 */ + GPIO_FR_NA, /*!< 9: N/A */ + GPIO_FR_Max, /*!< Max Number */ +} gpio_fr_t; + +/** + * @enum gpio_pa0_func_t + * @brief PortA0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA0_INT02a = 0, /*!< 0: INT02a */ + GPIO_PA0_EA00 = GPIO_FR_1, /*!< PAFR1: EA00 */ + GPIO_PA0_T32A00INB1 = GPIO_FR_2, /*!< PAFR2: T32A00INB1 */ + GPIO_PA0_T32A00INA0 = GPIO_FR_3, /*!< PAFR3: T32A00INA0 */ + GPIO_PA0_T32A00INC0 = GPIO_FR_5, /*!< PAFR5: T32A00INC0 */ + GPIO_PA0_TSPI0CSIN = GPIO_FR_6, /*!< PAFR6: TSPI0CSIN */ + GPIO_PA0_TSPI0CS0 = GPIO_FR_7, /*!< PAFR7: TSPI0CS0 */ +} gpio_pa0_func_t; + +/** + * @enum gpio_pa1_func_t + * @brief PortA1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA1_EA01 = GPIO_FR_1, /*!< PAFR1: EA01 */ + GPIO_PA1_T32A00OUTA = GPIO_FR_3, /*!< PAFR3: T32A00OUTA */ + GPIO_PA1_T32A00OUTC = GPIO_FR_5, /*!< PAFR5: T32A00OUTC */ + GPIO_PA1_TSPI0SCK = GPIO_FR_7, /*!< PAFR7: TSPI0SCK */ +} gpio_pa1_func_t; + +/** + * @enum gpio_pa2_func_t + * @brief PortA2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA2_EA02 = GPIO_FR_1, /*!< PAFR1: EA02 */ + GPIO_PA2_T32A00OUTB = GPIO_FR_3, /*!< PAFR3: T32A00OUTB */ + GPIO_PA2_TSPI0RXD = GPIO_FR_7, /*!< PAFR7: TSPI0RXD */ + GPIO_PA2_EMAPPSOUT0 = GPIO_FR_8, /*!< PAFR8: EMAPPSOUT0 */ +} gpio_pa2_func_t; + +/** +* @enum gpio_pa3_func_t +* @brief PortA3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PA3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA3_EA03 = GPIO_FR_1, /*!< PAFR1: EA03 */ + GPIO_PA3_T32A00INA1 = GPIO_FR_2, /*!< PAFR2: T32A00INA1 */ + GPIO_PA3_T32A00INB0 = GPIO_FR_3, /*!< PAFR3: T32A00INB0 */ + GPIO_PA3_T32A00INC1 = GPIO_FR_5, /*!< PAFR5: T32A00INC1 */ + GPIO_PA3_TSPI2CS1 = GPIO_FR_6, /*!< PAFR6: TSPI2CS1 */ + GPIO_PA3_TSPI0TXD = GPIO_FR_7, /*!< PAFR7: TSPI0TXD */ +} gpio_pa3_func_t; + +/** +* @enum gpio_pa4_func_t +* @brief PortA4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PA4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA4_EA04 = GPIO_FR_1, /*!< PAFR1: EA04 */ + GPIO_PA4_T32A01INB1 = GPIO_FR_2, /*!< PAFR2: T32A01INB1 */ + GPIO_PA4_T32A01INA0 = GPIO_FR_3, /*!< PAFR3: T32A01INA0 */ + GPIO_PA4_T32A01INC0 = GPIO_FR_5, /*!< PAFR5: T32A01INC0 */ + GPIO_PA4_TSPI0CS1 = GPIO_FR_6, /*!< PAFR6: TSPI0CS1 */ + GPIO_PA4_TSPI2TXD = GPIO_FR_7, /*!< PAFR7: TSPI2TXD */ +} gpio_pa4_func_t; + +/** + * @enum gpio_pa5_func_t + * @brief PortA5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA5_EA05 = GPIO_FR_1, /*!< PAFR1: EA05 */ + GPIO_PA5_T32A01OUTA = GPIO_FR_3, /*!< PAFR3: T32A01OUTA */ + GPIO_PA5_T32A01OUTC = GPIO_FR_5, /*!< PAFR5: T32A01OUTC */ + GPIO_PA5_TSPI0CS2 = GPIO_FR_6, /*!< PAFR6: TSPI0CS2 */ + GPIO_PA5_TSPI2RXD = GPIO_FR_7, /*!< PAFR7: TSPI2RXD */ +} gpio_pa5_func_t; + +/** + * @enum gpio_pa6_func_t + * @brief PortA6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA6_EA06 = GPIO_FR_1, /*!< PAFR1: EA06 */ + GPIO_PA6_T32A01OUTB = GPIO_FR_3, /*!< PAFR3: T32A01OUTB */ + GPIO_PA6_TSPI0CS3 = GPIO_FR_6, /*!< PAFR6: TSPI0CS3 */ + GPIO_PA6_TSPI2SCK = GPIO_FR_7, /*!< PAFR7: TSPI2SCK */ + GPIO_PA6_EMAPPSOUT1 = GPIO_FR_8, /*!< PAFR8: EMAPPSOUT1 */ +} gpio_pa6_func_t; + + +/** + * @enum gpio_pa7_func_t + * @brief PortA6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PA7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PA7_INT03a = 0, /*!< 0: INT03a */ + GPIO_PA7_EA07 = GPIO_FR_1, /*!< PAFR1: EA07 */ + GPIO_PA7_T32A01INA1 = GPIO_FR_2, /*!< PAFR2: T32A01INA1 */ + GPIO_PA7_T32A01INB0 = GPIO_FR_3, /*!< PAFR3: T32A01INB0 */ + GPIO_PA7_T32A01INC1 = GPIO_FR_5, /*!< PAFR5: T32A01INC1 */ + GPIO_PA7_TSPI2CSIN = GPIO_FR_6, /*!< PAFR6: TSPI2CSIN */ + GPIO_PA7_TSPI2CS0 = GPIO_FR_7, /*!< PAFR7: TSPI2CS0 */ +} gpio_pa7_func_t; + + + +/** + * @enum gpio_pb0_func_t + * @brief PortB0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB0_INT04a = 0, /*!< 0: INT04a */ + GPIO_PB0_EA08 = GPIO_FR_1, /*!< PBFR1: EA08 */ + GPIO_PB0_T32A02INB1 = GPIO_FR_2, /*!< PBFR2: T32A02INB1 */ + GPIO_PB0_T32A02INA0 = GPIO_FR_3, /*!< PBFR3: T32A02INA0 */ + GPIO_PB0_I2S0MCKIO = GPIO_FR_4, /*!< PBFR4: I2S0MCKI/O */ + GPIO_PB0_T32A02INC0 = GPIO_FR_5, /*!< PBFR5: T32A02INC0 */ + GPIO_PB0_USB_ECLK = GPIO_FR_6, /*!< PBFR6: USB_ECLK */ +} gpio_pb0_func_t; + +/** + * @enum gpio_pb1_func_t + * @brief PortB1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB1_INT05a = 0, /*!< 0: INT05a */ + GPIO_PB1_EA09 = GPIO_FR_1, /*!< PBFR1: EA09 */ + GPIO_PB1_T32A02INA1 = GPIO_FR_2, /*!< PBFR2: T32A02INA1 */ + GPIO_PB1_T32A02INB0 = GPIO_FR_3, /*!< PBFR3: T32A02INB0 */ + GPIO_PB1_T32A02INC1 = GPIO_FR_5, /*!< PBFR5: T32A02INC1 */ + GPIO_PB1_HDMAREQA = GPIO_FR_6, /*!< PBFR6: HDMAREQA */ +} gpio_pb1_func_t; + +/** + * @enum gpio_pb2_func_t + * @brief PortB2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB2_EA10 = GPIO_FR_1, /*!< PBFR1: EA10 */ + GPIO_PB2_T32A02OUTA = GPIO_FR_3, /*!< PBFR3: T32A02OUTA */ + GPIO_PB2_T32A02OUTC = GPIO_FR_5, /*!< PBFR5: T32A02OUTC */ + GPIO_PB2_USBA_VBUSEN = GPIO_FR_6,/*!< PBFR6: USBA_VBUSEN */ +} gpio_pb2_func_t; + +/** +* @enum gpio_pb3_func_t +* @brief PortB3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PB3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PB3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PB3_EA11 = GPIO_FR_1, /*!< PBFR1: EA11 */ + GPIO_PB3_T32A02OUTB = GPIO_FR_3, /*!< PBFR3: T32A02OUTB */ + GPIO_PB3_USBA_ID = GPIO_FR_6, /*!< PBFR6: USBA_ID */ +} gpio_pb3_func_t; + +/** +* @enum gpio_pc4_func_t +* @brief PortC4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PC4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC4_EA20 = GPIO_FR_1, /*!< PCFR1: EA20 */ + GPIO_PC4_T32A10OUTA = GPIO_FR_3, /*!< PCFR3: T32A10OUTA */ + GPIO_PC4_T32A10OUTC = GPIO_FR_5, /*!< PCFR5: T32A10OUTC */ +} gpio_pc4_func_t; + +/** + * @enum gpio_pc5_func_t + * @brief PortC5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC5_EA21 = GPIO_FR_1, /*!< PCFR1: EA21 */ + GPIO_PC5_T32A10OUTB = GPIO_FR_3, /*!< PCFR3: T32A10OUTB */ +} gpio_pc5_func_t; + +/** + * @enum gpio_pc6_func_t + * @brief PortC6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC6_INT14a = 0, /*!< 0: INT14a */ + GPIO_PC6_EA22 = GPIO_FR_1, /*!< PCFR1: EA22 */ +} gpio_pc6_func_t; + +/** + * @enum gpio_pc7_func_t + * @brief PortC7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PC7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PC7_INT15a = 0, /*!< 0: INT15a */ + GPIO_PC7_EA23 = GPIO_FR_1, /*!< PCFR1: EA23 */ +} gpio_pc7_func_t; + +/** + * @enum gpio_pd0_func_t + * @brief PortD0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD0_ED00 = GPIO_FR_1, /*!< PCFR1: ED00 */ + GPIO_PD0_T32A04INB1 = GPIO_FR_2, /*!< PCFR2: T32A04INB1 */ + GPIO_PD0_T32A04INA0 = GPIO_FR_3, /*!< PCFR3: T32A04INA0 */ + GPIO_PD0_TSPI4CS0 = GPIO_FR_4, /*!< PCFR4: TSPI4CS0 */ + GPIO_PD0_T32A04INC0 = GPIO_FR_5, /*!< PCFR5: T32A04INC0 */ + GPIO_PD0_TSPI4CSIN = GPIO_FR_6, /*!< PCFR6: TSPI4CSIN */ + GPIO_PD0_UO0 = GPIO_FR_7, /*!< PCFR7: UO0 */ +} gpio_pd0_func_t; + +/** + * @enum gpio_pd1_func_t + * @brief PortD1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD1_ED01 = GPIO_FR_1, /*!< PCFR1: ED01 */ + GPIO_PD1_T32A04INA1 = GPIO_FR_2, /*!< PCFR2: T32A04INA1 */ + GPIO_PD1_T32A04INB0 = GPIO_FR_3, /*!< PCFR3: T32A04INB0 */ + GPIO_PD1_TSPI4SCK = GPIO_FR_4, /*!< PCFR4: TSPI4SCK */ + GPIO_PD1_T32A04INC1 = GPIO_FR_5, /*!< PCFR5: T32A04INC1 */ + GPIO_PD1_XO0 = GPIO_FR_7, /*!< PCFR7: XO0 */ +} gpio_pd1_func_t; + +/** + * @enum gpio_pd2_func_t + * @brief PortD2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD2_ED02 = GPIO_FR_1, /*!< PCFR1: ED02 */ + GPIO_PD2_T32A04OUTA = GPIO_FR_3, /*!< PCFR3: T32A04OUTA */ + GPIO_PD2_TSPI4RXD = GPIO_FR_4, /*!< PCFR4: TSPI4RXD */ + GPIO_PD2_T32A04OUTC = GPIO_FR_5, /*!< PCFR5: T32A04OUTC */ + GPIO_PD2_VO0 = GPIO_FR_7, /*!< PCFR7: VO0 */ + GPIO_PD2_TSSI0TCK = GPIO_FR_8, /*!< PCFR8: TSSI0TCK */ +} gpio_pd2_func_t; + +/** +* @enum gpio_pd3_func_t +* @brief PortD3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PD3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD3_ED03 = GPIO_FR_1, /*!< PCFR1: ED03 */ + GPIO_PD3_T32A04OUTB = GPIO_FR_3, /*!< PCFR3: T32A04OUTB */ + GPIO_PD3_TSPI4TXD = GPIO_FR_4, /*!< PCFR4: TSPI4TXD */ + GPIO_PD3_YO0 = GPIO_FR_7, /*!< PCFR7: YO0 */ + GPIO_PD3_TSSI0TFS = GPIO_FR_8, /*!< PCFR8: TSSI0TFS */ +} gpio_pd3_func_t; + +/** + * @enum gpio_pd4_func_t + * @brief PortD4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD4_ED04 = GPIO_FR_1, /*!< PCFR1: ED04 */ + GPIO_PD4_T32A05OUTA = GPIO_FR_3, /*!< PCFR3: T32A05OUTA */ + GPIO_PD4_T32A05OUTC = GPIO_FR_5, /*!< PCFR5: T32A05OUTC */ + GPIO_PD4_I2S0LRCK = GPIO_FR_6, /*!< PCFR6: I2S0LRCK */ + GPIO_PD4_WO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ + GPIO_PD4_TSSI0TXD = GPIO_FR_8, /*!< PCFR8: TSSI0TXD */ +} gpio_pd4_func_t; + +/** + * @enum gpio_pd5_func_t + * @brief PortD5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD5_ED05 = GPIO_FR_1, /*!< PCFR1: ED05 */ + GPIO_PD5_T32A05OUTB = GPIO_FR_3, /*!< PCFR3: T32A05OUTB */ + GPIO_PD5_I2S0BCK = GPIO_FR_6, /*!< PCFR6: I2S0BCK */ + GPIO_PD5_ZO0 = GPIO_FR_7, /*!< PCFR7: WO0 */ + GPIO_PD5_TSSI0RXD = GPIO_FR_8, /*!< PCFR8: TSSI0RXD */ +} gpio_pd5_func_t; + +/** + * @enum gpio_pd6_func_t + * @brief PortD6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD6_ED06 = GPIO_FR_1, /*!< PCFR1: ED06 */ + GPIO_PD6_T32A05INB1 = GPIO_FR_2, /*!< PCFR2: T32A05INB1 */ + GPIO_PD6_T32A05INA0 = GPIO_FR_3, /*!< PCFR3: T32A05INA0 */ + GPIO_PD6_T32A05INC0 = GPIO_FR_5, /*!< PCFR5: T32A05INC0 */ + GPIO_PD6_I2S0DI = GPIO_FR_6, /*!< PCFR6: I2S0DI */ + GPIO_PD6_EMG0 = GPIO_FR_7, /*!< PCFR7: EMG0 */ + GPIO_PD6_TSSI0RFS = GPIO_FR_8, /*!< PCFR8: TSSI0RFS */ +} gpio_pd6_func_t; + +/** + * @enum gpio_pd7_func_t + * @brief PortD7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PD7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PD7_ED07 = GPIO_FR_1, /*!< PCFR1: ED07 */ + GPIO_PD7_T32A05INA1 = GPIO_FR_2, /*!< PCFR2: T32A05INA1 */ + GPIO_PD7_T32A05INB0 = GPIO_FR_3, /*!< PCFR3: T32A05INB0 */ + GPIO_PD7_T32A05INC1 = GPIO_FR_5, /*!< PCFR5: T32A05INC1 */ + GPIO_PD7_I2S0DO = GPIO_FR_6, /*!< PCFR6: I2S0DO */ + GPIO_PD7_OVV0 = GPIO_FR_7, /*!< PCFR7: OVV0 */ + GPIO_PD7_TSSI0RCK = GPIO_FR_8, /*!< PCFR8: TSSI0RCK */ +} gpio_pd7_func_t; + +/** + * @enum gpio_pe0_func_t + * @brief PortE0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE0_ED08 = GPIO_FR_1, /*!< PCFR1: ED08 */ + GPIO_PE0_T32A06INB1 = GPIO_FR_2, /*!< PCFR2: T32A06INB1 */ + GPIO_PE0_T32A06OUTB = GPIO_FR_3, /*!< PCFR3: T32A06OUTB */ + GPIO_PE0_EA23 = GPIO_FR_4, /*!< PCFR4: EA23 */ + GPIO_PE0_T32A06INA1 = GPIO_FR_5, /*!< PCFR5: T32A06INA1 */ + GPIO_PE0_CANBTX = GPIO_FR_6, /*!< PCFR6: CANBTX */ + GPIO_PE0_UT0RTS_N = GPIO_FR_7, /*!< PCFR7: UT0RTS_N */ + GPIO_PE0_EA15 = GPIO_FR_8, /*!< PCFR8: EA15 */ +} gpio_pe0_func_t; + +/** + * @enum gpio_pe1_func_t + * @brief PortE1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE1_ED09 = GPIO_FR_1, /*!< PCFR1: ED09 */ + GPIO_PE1_T32A06OUTA = GPIO_FR_3, /*!< PCFR3: T32A06OUTA */ + GPIO_PE1_EA22 = GPIO_FR_4, /*!< PCFR4: EA22 */ + GPIO_PE1_T32A06OUTC = GPIO_FR_5, /*!< PCFR5: T32A06OUTC */ + GPIO_PE1_CANBRX = GPIO_FR_6, /*!< PCFR6: CANBRX */ + GPIO_PE1_UT0CTS_N = GPIO_FR_7, /*!< PCFR7: UT0CTS_N */ + GPIO_PE1_EA14 = GPIO_FR_8, /*!< PCFR8: EA14 */ +} gpio_pe1_func_t; + +/** + * @enum gpio_pe2_func_t + * @brief PortE2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE2_ED10 = GPIO_FR_1, /*!< PCFR1: ED10 */ + GPIO_PE2_T32A06INA0 = GPIO_FR_3, /*!< PCFR3: T32A06INA0 */ + GPIO_PE2_EA21 = GPIO_FR_4, /*!< PCFR4: EA21 */ + GPIO_PE2_T32A06INC0 = GPIO_FR_5, /*!< PCFR5: T32A06INC0 */ + GPIO_PE2_EMAPPSOUT0 = GPIO_FR_6, /*!< PCFR6: EMAPPSOUT0 */ + GPIO_PE2_UT0RXD = GPIO_FR_7, /*!< PCFR7: UT0RXD */ + GPIO_PE2_EA13 = GPIO_FR_8, /*!< PCFR8: EA13 */ +} gpio_pe2_func_t; + +/** +* @enum gpio_pe3_func_t +* @brief PortE3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE3_ED11 = GPIO_FR_1, /*!< PCFR1: ED11 */ + GPIO_PE3_T32A06INB0 = GPIO_FR_3, /*!< PCFR3: T32A06INB0 */ + GPIO_PE3_EA20 = GPIO_FR_4, /*!< PCFR4: EA20 */ + GPIO_PE3_T32A06INC1 = GPIO_FR_5, /*!< PCFR5: T32A06INC1 */ + GPIO_PE3_EMAPPSOUT1 = GPIO_FR_6, /*!< PCFR5: EMAPPSOUT1 */ + GPIO_PE3_UT0TXDA = GPIO_FR_7, /*!< PCFR7: UT0TXDA */ + GPIO_PE3_EA12 = GPIO_FR_8, /*!< PCFR8: EA12 */ +} gpio_pe3_func_t; + +/** +* @enum gpio_pe4_func_t +* @brief PortE4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE4_ED12 = GPIO_FR_1, /*!< PCFR1: ED12 */ + GPIO_PE4_T32A07INA0 = GPIO_FR_3, /*!< PCFR3: T32A07INA0 */ + GPIO_PE4_EA19 = GPIO_FR_4, /*!< PCFR4: EA19 */ + GPIO_PE4_T32A07INC0 = GPIO_FR_5, /*!< PCFR5: T32A07INC0 */ + GPIO_PE4_I2S1DO = GPIO_FR_6, /*!< PCFR6: I2S1DO */ + GPIO_PE4_ISDAIN0 = 0, /*!< 0: ISDAIN0 */ + GPIO_PE4_EA11 = GPIO_FR_8, /*!< PCFR8: EA11 */ +} gpio_pe4_func_t; + +/** + * @enum gpio_pe5_func_t + * @brief PortE5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE5_ED13 = GPIO_FR_1, /*!< PCFR1: ED13 */ + GPIO_PE5_T32A07INB0 = GPIO_FR_3, /*!< PCFR3: T32A07INB0 */ + GPIO_PE5_EA18 = GPIO_FR_4, /*!< PCFR4: EA18 */ + GPIO_PE5_T32A07INC1 = GPIO_FR_5, /*!< PCFR5: T32A07INC1 */ + GPIO_PE5_I2S1DI = GPIO_FR_6, /*!< PCFR6: I2S1DI */ + GPIO_PE5_ISDAIN1 = 0, /*!< 0: ISDAIN1 */ + GPIO_PE5_EA10 = GPIO_FR_8, /*!< PCFR8: EA10 */ +} gpio_pe5_func_t; + +/** + * @enum gpio_pe6_func_t + * @brief PortE6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE6_ED14 = GPIO_FR_1, /*!< PCFR1: ED14 */ + GPIO_PE6_T32A07OUTA = GPIO_FR_3, /*!< PCFR3: T32A07OUTA */ + GPIO_PE6_EA17 = GPIO_FR_4, /*!< PCFR4: EA17 */ + GPIO_PE6_T32A07OUTC = GPIO_FR_5, /*!< PCFR5: T32A07OUTC */ + GPIO_PE6_I2S1BCK = GPIO_FR_6, /*!< PCFR6: I2S1BCK */ + GPIO_PE6_ISDAIN2 = 0, /*!< 0: ISDAIN2 */ + GPIO_PE6_EA09 = GPIO_FR_8, /*!< PCFR8: EA09 */ +} gpio_pe6_func_t; + +/** + * @enum gpio_pe7_func_t + * @brief PortE7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PE7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PE7_ED15 = GPIO_FR_1, /*!< PCFR1: ED15 */ + GPIO_PE7_T32A07INB1 = GPIO_FR_2, /*!< PCFR2: T32A07INB1 */ + GPIO_PE7_T32A07OUTB = GPIO_FR_3, /*!< PCFR3: T32A07OUTB */ + GPIO_PE7_EA16 = GPIO_FR_4, /*!< PCFR4: EA16 */ + GPIO_PE7_T32A07INA1 = GPIO_FR_5, /*!< PCFR5: T32A07INA1 */ + GPIO_PE7_I2S1LRCK = GPIO_FR_6, /*!< PCFR6: I2S1LRCK */ + GPIO_PE7_ISDAIN3 = 0, /*!< 0: ISDAIN3 */ + GPIO_PE7_EA08 = GPIO_FR_8, /*!< PCFR8: EA08 */ +} gpio_pe7_func_t; + +/** + * @enum gpio_pf0_func_t + * @brief PortF0 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF0_INT04b = 0, /*!< 0: INT04b */ + GPIO_PF0_ERD_N = GPIO_FR_1, /*!< PCFR1: ERD_N */ +} gpio_pf0_func_t; + +/** + * @enum gpio_pf1_func_t + * @brief PortF1 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF1_EWR_N = GPIO_FR_1, /*!< PCFR1: EWR_N */ +} gpio_pf1_func_t; + +/** + * @enum gpio_pf2_func_t + * @brief PortF2 Function Enumerated TyPF Definition. + */ +typedef enum { + GPIO_PF2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF2_EI2C1SDA = GPIO_FR_6, /*!< PCFR6: EI2C1SDA */ + GPIO_PF2_I2C1SDA = GPIO_FR_7, /*!< PCFR7: I2C1SDA */ +} gpio_pf2_func_t; + +/** +* @enum gpio_pf3_func_t +* @brief PortF3 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF3_EI2C1SCL = GPIO_FR_6, /*!< PCFR6: EI2C1SCL */ + GPIO_PF3_I2C1SCL = GPIO_FR_7, /*!< PCFR7: I2C1SCL */ +} gpio_pf3_func_t; + +/** +* @enum gpio_pf4_func_t +* @brief PortF4 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF4_ECS2_N = GPIO_FR_1, /*!< PCFR1: ECS2_N */ +} gpio_pf4_func_t; + +/** +* @enum gpio_pf5_func_t +* @brief PortF5 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF5_ECS3_N = GPIO_FR_1, /*!< PCFR1: ECS3_N */ + GPIO_PF5_USBB_SOF_TGL = GPIO_FR_6, /*!< PCFR6: USBB_SOF_TGL */ +} gpio_pf5_func_t; + +/** +* @enum gpio_pf6_func_t +* @brief PortF6 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF6_EBELL_N = GPIO_FR_1, /*!< PCFR1: EBELL_N */ + GPIO_PF6_CANATX = GPIO_FR_6, /*!< PCFR6: CANATX */ +} gpio_pf6_func_t; + +/** +* @enum gpio_pf7_func_t +* @brief PortF7 Function Enumerated TyPF Definition. +*/ +typedef enum { + GPIO_PF7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PF7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PF7_INT05b = 0, /*!< 0: INT05b */ + GPIO_PF7_EBELH_N = GPIO_FR_1, /*!< PCFR1: EBELH_N */ + GPIO_PF7_TSPI2CSIN = GPIO_FR_4, /*!< PCFR4: TSPI2CSIN */ + GPIO_PF7_TSPI2CS0 = GPIO_FR_5, /*!< PCFR5: TSPI2CS0 */ + GPIO_PF7_CANARX = GPIO_FR_6, /*!< PCFR6: CANARX */ +} gpio_pf7_func_t; + +/** + * @enum gpio_pg0_func_t + * @brief PortG0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG0_INT08a = 0, /*!< 0: INT08a */ + GPIO_PG0_EALE = GPIO_FR_1, /*!< PCFR1: EALE */ + GPIO_PG0_UT2RXD = GPIO_FR_3, /*!< PCFR3: UT2RXD */ + GPIO_PG0_UT2TXDA = GPIO_FR_5, /*!< PCFR5: UT2TXDA */ + GPIO_PG0_EMARXDV = GPIO_FR_8, /*!< PCFR8: EMARXDV */ +} gpio_pg0_func_t; + +/** + * @enum gpio_pg1_func_t + * @brief PortG1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG1_INT09a = 0, /*!< 0: INT09a */ + GPIO_PG1_EWAIT_N = GPIO_FR_1, /*!< PCFR1: EWAIT_N */ + GPIO_PG1_UT2TXDA = GPIO_FR_3, /*!< PCFR3: UT2TXDA */ + GPIO_PG1_UT2RXD = GPIO_FR_5, /*!< PCFR5: UT2RXD */ + GPIO_PG1_EMARXER = GPIO_FR_8, /*!< PCFR8: EMARXER */ +} gpio_pg1_func_t; + +/** + * @enum gpio_pg2_func_t + * @brief PortG2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG2_UT2RTS_N = GPIO_FR_3, /*!< PCFR3: UT2RTS_N */ + GPIO_PG2_ALARM_N = GPIO_FR_4, /*!< PCFR4: ALARM_N */ + GPIO_PG2_UT2CTS_N = GPIO_FR_5, /*!< PCFR5: UT2CTS_N */ + GPIO_PG2_EI2C0SDA = GPIO_FR_6, /*!< PCFR6: EI2C0SDA */ + GPIO_PG2_I2C0SDA = GPIO_FR_7, /*!< PCFR7: I2C0SDA */ + GPIO_PG2_EMACRS = GPIO_FR_8, /*!< PCFR8: EMACRS */ +} gpio_pg2_func_t; + +/** + * @enum gpio_pg3_func_t + * @brief PortG3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG3_UT2CTS_N = GPIO_FR_3, /*!< PCFR3: UT2CTS_N */ + GPIO_PG3_TRGIN0 = GPIO_FR_4, /*!< PCFR4: TRGIN0 */ + GPIO_PG3_UT2RTS_N = GPIO_FR_5, /*!< PCFR5: UT2RTS_N */ + GPIO_PG3_EI2C0SCL = GPIO_FR_6, /*!< PCFR6: EI2C0SCL */ + GPIO_PG3_I2C0SCL = GPIO_FR_7, /*!< PCFR7: I2C0SCL */ + GPIO_PG3_EMACOL = GPIO_FR_8, /*!< PCFR8: EMACOL */ +} gpio_pg3_func_t; + +/** + * @enum gpio_pg4_func_t + * @brief PortG4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG4_T32A02OUTB = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ + GPIO_PG4_FUT0IROUT = GPIO_FR_4, /*!< PCF41: FUT0IROUT */ + GPIO_PG4_FUT0TXD = GPIO_FR_5, /*!< PCFR5: FUT0TXD */ + GPIO_PG4_EI2C2SDA = GPIO_FR_6, /*!< PCFR6: EI2C2SDA */ + GPIO_PG4_I2C2SDA = GPIO_FR_7, /*!< PCFR7: I2C2SDA */ + GPIO_PG4_EMARXD2 = GPIO_FR_8, /*!< PCFR8: EMARXD2 */ +} gpio_pg4_func_t; + +/** + * @enum gpio_pg5_func_t + * @brief PortG5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG5_T32A02OUTA = GPIO_FR_2, /*!< PCFR2: T32A02OUTB */ + GPIO_PG5_T32A02OUTC = GPIO_FR_3, /*!< PCFR3: T32A02OUTC */ + GPIO_PG5_FUT0IRIN = GPIO_FR_4, /*!< PCFR4: FUT0IRIN */ + GPIO_PG5_FUT0RXD = GPIO_FR_5, /*!< PCFR5: FUT0RXD */ + GPIO_PG5_EI2C2SCL = GPIO_FR_6, /*!< PCFR6: EI2C2SCL */ + GPIO_PG5_I2C2SCL = GPIO_FR_7, /*!< PCFR7: I2C2SCL */ + GPIO_PG5_EMARXD3 = GPIO_FR_8, /*!< PCFR8: EMARXD3 */ +} gpio_pg5_func_t; + +/** + * @enum gpio_pg6_func_t + * @brief PortG6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG6_TRACECLK = GPIO_FR_1, /*!< PCFR1: TRACECLK */ + GPIO_PG6_NBDCLK = GPIO_FR_4, /*!< PCFR4: NBDCLK */ + GPIO_PG6_FUT0RTS_N = GPIO_FR_5, /*!< PCFR5: FUT0RTS_N */ + GPIO_PG6_I2S1MCKIO = GPIO_FR_6, /*!< PCFR6: I2S1MCKIO */ +} gpio_pg6_func_t; + +/** + * @enum gpio_pg7_func_t + * @brief PortG7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PG7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PG7_TRACEDATA0 = GPIO_FR_1, /*!< PCFR1: TRACEDATA0 */ + GPIO_PG7_NBDDATA0 = GPIO_FR_4, /*!< PCFR4: NBDDATA0 */ + GPIO_PG7_FUT0CTS_N = GPIO_FR_5, /*!< PCFR5: FUT0CTS_N */ + GPIO_PG7_EMAMDC = GPIO_FR_8, /*!< PCFR8: EMAMDC */ +} gpio_pg7_func_t; + +/** + * @enum gpio_ph0_func_t + * @brief PortH0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH0_TRACEDATA1 = GPIO_FR_1, /*!< PCFR1: TRACEDATA1 */ + GPIO_PH0_UT1RXD = GPIO_FR_3, /*!< PCFR3: UT1RXD */ + GPIO_PH0_NBDDATA1 = GPIO_FR_4, /*!< PCFR4: NBDDATA1 */ + GPIO_PH0_UT1TXDA = GPIO_FR_5, /*!< PCFR5: UT1TXDA */ + GPIO_PH0_EMAMDIO = GPIO_FR_8, /*!< PCFR8: EMAMDIO */ +} gpio_ph0_func_t; + +/** + * @enum gpio_ph1_func_t + * @brief PortH1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH1_TRACEDATA2 = GPIO_FR_1, /*!< PCFR1: TRACEDATA2 */ + GPIO_PH1_UT1TXDA = GPIO_FR_3, /*!< PCFR3: UT1TXDA */ + GPIO_PH1_NBDDATA2 = GPIO_FR_4, /*!< PCFR4: NBDDATA2 */ + GPIO_PH1_UT1RXD = GPIO_FR_5, /*!< PCFR5: UT1RXD */ +} gpio_ph1_func_t; + +/** + * @enum gpio_ph2_func_t + * @brief PortH2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH2_TRACEDATA3 = GPIO_FR_1, /*!< PCFR1: TRACEDATA3 */ + GPIO_PH2_UT1RTS_N = GPIO_FR_3, /*!< PCFR3: UT1RTS_N */ + GPIO_PH2_NBDDATA3 = GPIO_FR_4, /*!< PCFR4: NBDDATA3 */ + GPIO_PH2_UT1CTS_N = GPIO_FR_5, /*!< PCFR5: UT1CTS_N */ +} gpio_ph2_func_t; + +/** +* @enum gpio_ph3_func_t +* @brief PortH3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH3_TDI = GPIO_FR_1, /*!< PCFR1: TDI */ + GPIO_PH3_UT1CTS_N = GPIO_FR_3, /*!< PCFR3: UT1CTS_N */ + GPIO_PH3_NBDSYNC = GPIO_FR_4, /*!< PCFR4: NBDSYNC */ + GPIO_PH3_UT1RTS_N = GPIO_FR_5, /*!< PCFR5: UT1RTS_N */ +} gpio_ph3_func_t; + +/** +* @enum gpio_ph4_func_t +* @brief PortH4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH4_SWDIO = GPIO_FR_1, /*!< PCFR1: SWDIO */ + GPIO_PH4_UT0RXD = GPIO_FR_3, /*!< PCFR3: UT0RXD */ + GPIO_PH4_UT0TXDA = GPIO_FR_5, /*!< PCFR5: UT0TXDA */ +} gpio_ph4_func_t; + +/** +* @enum gpio_ph5_func_t +* @brief PortH5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH5_TCK = GPIO_FR_1, /*!< PCFR1: TCK */ + GPIO_PH5_UT0TXDA = GPIO_FR_3, /*!< PCFR3: UT0TXDA */ + GPIO_PH5_UT0RXD = GPIO_FR_5, /*!< PCFR5: UT0RXD */ +} gpio_ph5_func_t; + +/** +* @enum gpio_ph6_func_t +* @brief PortH6 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH6_TDO = GPIO_FR_1, /*!< PCFR1: TDO */ + GPIO_PH6_UT0RTS_N = GPIO_FR_3, /*!< PCFR3: UT0RTS_N */ + GPIO_PH6_UT0CTS_N = GPIO_FR_5, /*!< PCFR5: UT0CTS_N */ +} gpio_ph6_func_t; + +/** +* @enum gpio_ph7_func_t +* @brief PortH7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PH7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PH7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PH7_TRST_N = GPIO_FR_1, /*!< PCFR1: TRST_N */ + GPIO_PH7_UT0CTS_N = GPIO_FR_3, /*!< PCFR3: UT0CTS_N */ + GPIO_PH7_UT0RTS_N = GPIO_FR_5, /*!< PCFR5: UT0RTS_N */ +} gpio_ph7_func_t; + +/** + * @enum gpio_pj0_func_t + * @brief PortJ0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ0_UT5RXD = GPIO_FR_3, /*!< PJFR3: UT5RXD */ + GPIO_PJ0_UT5TXDA = GPIO_FR_5, /*!< PJFR5: UT5TXDA */ +} gpio_pj0_func_t; + +/** + * @enum gpio_pj1_func_t + * @brief PortJ1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ1_UT5TXDA = GPIO_FR_3, /*!< PJFR3: UT5TXDA */ + GPIO_PJ1_UT5RXD = GPIO_FR_5, /*!< PJFR5: UT5RXD */ +} gpio_pj1_func_t; + +/** + * @enum gpio_pj2_func_t + * @brief PortJ2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ2_UT5RTS_N = GPIO_FR_3, /*!< PJFR3: UT5RTS_N */ + GPIO_PJ2_UT5CTS_N = GPIO_FR_5, /*!< PJFR5: UT5CTS_N */ + GPIO_PJ2_EI2C4SCL = GPIO_FR_6, /*!< PJFR6: EI2C4SCL */ + GPIO_PJ2_I2C4SCL = GPIO_FR_7, /*!< PJFR7: I2C4SCL */ +} gpio_pj2_func_t; + +/** +* @enum gpio_pj3_func_t +* @brief PortJ3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ3_UT5CTS_N = GPIO_FR_3, /*!< PJFR3: UT5CTS_N */ + GPIO_PJ3_UT5RTS_N = GPIO_FR_5, /*!< PJFR5: UT5RTS_N */ + GPIO_PJ3_EI2C4SDA = GPIO_FR_6, /*!< PJFR6: EI2C4SDA */ + GPIO_PJ3_I2C4SDA = GPIO_FR_7, /*!< PJFR7: I2C4SDA */ +} gpio_pj3_func_t; + +/** +* @enum gpio_pj4_func_t +* @brief PortJ4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ4_T32A03INA0 = GPIO_FR_2, /*!< PJFR2: T32A03INA0 */ + GPIO_PJ4_T32A03INC0 = GPIO_FR_3, /*!< PJFR3: T32A03INC0 */ + GPIO_PJ4_FUT0TXD = GPIO_FR_5, /*!< PJFR5: FUT0TXD */ +} gpio_pj4_func_t; + +/** + * @enum gpio_pj5_func_t + * @brief PortJ5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ5_T32A03INB0 = GPIO_FR_2, /*!< PJFR2: T32A03INB0 */ + GPIO_PJ5_T32A03INC1 = GPIO_FR_3, /*!< PJFR3: T32A03INC1 */ + GPIO_PJ5_FUT0RXD = GPIO_FR_5, /*!< PJFR5: FUT0RXD */ +} gpio_pj5_func_t; + +/** + * @enum gpio_pj6_func_t + * @brief PortJ6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ6_FUT1TXD = GPIO_FR_5, /*!< PJFR5: FUT1TXD */ + GPIO_PJ6_EI2C3SDA = GPIO_FR_6, /*!< PJFR6: EI2C3SDA */ + GPIO_PJ6_I2C3SDA = GPIO_FR_7, /*!< PJFR7: I2C3SDA */ +} gpio_pj6_func_t; + +/** + * @enum gpio_pj7_func_t + * @brief PortJ7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PJ7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PJ7_FUT1RXD = GPIO_FR_5, /*!< PJFR5: FUT1RXD */ + GPIO_PJ7_EI2C3SCL = GPIO_FR_6, /*!< PJFR6: EI2C3SCL */ + GPIO_PJ7_I2C3SCL = GPIO_FR_7, /*!< PJFR7: I2C3SCL */ +} gpio_pj7_func_t; + +/** + * @enum gpio_pk0_func_t + * @brief PortK0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK0_INT10a = 0, /*!< 0: INT10a */ + GPIO_PK0_ISDAOUT = GPIO_FR_1, /*!< PKFR1: ISDAOUT */ + GPIO_PK0_T32A00INA0 = GPIO_FR_2, /*!< PKFR2: T32A00INA0 */ + GPIO_PK0_T32A00INC0 = GPIO_FR_3, /*!< PKFR3: T32A00INC0 */ + GPIO_PK0_SMI0CS1_N = GPIO_FR_6, /*!< PKFR6: ISDAOUT */ + GPIO_PK0_EMATXEN = GPIO_FR_8, /*!< PKFR8: EMATXEN */ +} gpio_pk0_func_t; + +/** + * @enum gpio_pk1_func_t + * @brief PortK1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK1_INT11a = 0, /*!< 0: INT11a */ + GPIO_PK1_ISDBOUT = GPIO_FR_1, /*!< PKFR1: ISDBOUT */ + GPIO_PK1_T32A00INB0 = GPIO_FR_2, /*!< PKFR2: T32A00INB0 */ + GPIO_PK1_T32A00INC1 = GPIO_FR_3, /*!< PKFR3: T32A00INC1 */ + GPIO_PK1_HDMAREQB = GPIO_FR_4, /*!< PKFR4: HDMAREQB */ + GPIO_PK1_TSPI3CS0 = GPIO_FR_5, /*!< PKFR5: TSPI3CS0 */ + GPIO_PK1_TSPI3CSIN = GPIO_FR_6, /*!< PKFR6: TSPI3CSIN */ +} gpio_pk1_func_t; + +/** + * @enum gpio_pk2_func_t + * @brief PortK2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK2_ECS0_N = GPIO_FR_1, /*!< PKFR1: ECS0_N */ + GPIO_PK2_SMI0D0 = GPIO_FR_6, /*!< PKFR6: SMI0D0 */ + GPIO_PK2_EMAMDC = GPIO_FR_8, /*!< PKFR8: EMAMDC */ +} gpio_pk2_func_t; + +/** +* @enum gpio_pk3_func_t +* @brief PortK3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK3_ECS1_N = GPIO_FR_1, /*!< PKFR1: ECS1_N */ + GPIO_PK3_SMI0D1 = GPIO_FR_6, /*!< PKFR6: SMI0D1 */ + GPIO_PK3_EMAMDIO = GPIO_FR_8, /*!< PKFR8: EMAMDIO */ +} gpio_pk3_func_t; + +/** +* @enum gpio_pk4_func_t +* @brief PortK4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK4_TSPI1CS1 = GPIO_FR_1, /*!< PKFR1: TSPI1CS1 */ + GPIO_PK4_TSPI3TXD = GPIO_FR_4, /*!< PKFR4: TSPI3TXD */ + GPIO_PK4_SMI0D2 = GPIO_FR_6, /*!< PKFR6: SMI0D2 */ + GPIO_PK4_EMATXCLK = GPIO_FR_8, /*!< PKFR8: EMATXCLK */ +} gpio_pk4_func_t; + +/** + * @enum gpio_pk5_func_t + * @brief PortK5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK5_TSPI1CS2 = GPIO_FR_1, /*!< PKFR1: TSPI1CS2 */ + GPIO_PK5_TSPI3RXD = GPIO_FR_4, /*!< PKFR4: TSPI3RXD */ + GPIO_PK5_SMI0D3 = GPIO_FR_6, /*!< PKFR6: SMI0D3 */ + GPIO_PK5_EMATXD3 = GPIO_FR_8, /*!< PKFR8: EMATXD3 */ +} gpio_pk5_func_t; + +/** + * @enum gpio_pk6_func_t + * @brief PortK6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK6_TSPI1CS3 = GPIO_FR_1, /*!< PKFR1: TSPI1CS3 */ + GPIO_PK6_T32A01INA0 = GPIO_FR_2, /*!< PKFR2: T32A01INA0 */ + GPIO_PK6_T32A01INC0 = GPIO_FR_3, /*!< PKFR3: T32A01INC0 */ + GPIO_PK6_TSPI3SCK = GPIO_FR_4, /*!< PKFR4: TSPI3SCK */ + GPIO_PK6_SMI0CLK = GPIO_FR_6, /*!< PKFR6: SMI0CLK */ + GPIO_PK6_EMATXD2 = GPIO_FR_8, /*!< PKFR8: EMATXD2 */ +} gpio_pk6_func_t; + +/** + * @enum gpio_pk7_func_t + * @brief PortK7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PK7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PK7_INT00a = 0, /*!< 0: INT00a */ + GPIO_PK7_T32A01INB0 = GPIO_FR_2, /*!< PKFR2: T32A01INB0 */ + GPIO_PK7_T32A01INC1 = GPIO_FR_3, /*!< PKFR3: T32A01INC1 */ + GPIO_PK7_TSPI3CS0 = GPIO_FR_4, /*!< PKFR4: TSPI3CS0 */ + GPIO_PK7_SMI0CS0_N = GPIO_FR_6, /*!< PKFR6: SMI0CS0_N */ + GPIO_PK7_TSPI3CSIN = GPIO_FR_7, /*!< PKFR7: TSPI3CSIN */ + GPIO_PK7_EMATXD1 = GPIO_FR_8, /*!< PKFR8: EMATXD1 */ +} gpio_pk7_func_t; + +/** + * @enum gpio_pl0_func_t + * @brief PortL0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL0_INT01a = 0, /*!< 0: INT01a */ + GPIO_PL0_T32A02INA0 = GPIO_FR_2, /*!< PLFR2: T32A02INA0 */ + GPIO_PL0_T32A02INC0 = GPIO_FR_3, /*!< PLFR3: T32A02INC0 */ + GPIO_PL0_SMI0D4 = GPIO_FR_5, /*!< PLFR5: SMI0D4 */ + GPIO_PL0_TSPI1CSIN = GPIO_FR_6, /*!< PLFR6: TSPI1CSIN */ + GPIO_PL0_TSPI1CS0 = GPIO_FR_7, /*!< PLFR7: TSPI1CS0 */ + GPIO_PL0_EMATXD0 = GPIO_FR_8, /*!< PKFR8: EMATXD0 */ +} gpio_pl0_func_t; + +/** + * @enum gpio_pl1_func_t + * @brief PortL1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL1_SMI0D5 = GPIO_FR_5, /*!< PLFR5: SMI0D5 */ + GPIO_PL1_TSPI1SCK = GPIO_FR_7, /*!< PLFR7: TSPI1SCK */ + GPIO_PL1_EMARXCLK = GPIO_FR_8, /*!< PLFR8: EMARXCLK */ +} gpio_pl1_func_t; + +/** + * @enum gpio_pl2_func_t + * @brief PortL2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL2_SMI0D6 = GPIO_FR_5, /*!< PLFR5: SMI0D6 */ + GPIO_PL2_TSPI1RXD = GPIO_FR_7, /*!< PLFR7: TSPI1RXD */ + GPIO_PL2_EMARXD0 = GPIO_FR_8, /*!< PLFR8: EMARXD0 */ +} gpio_pl2_func_t; + +/** +* @enum gpio_pl3_func_t +* @brief PortL3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL3_T32A02INB0 = GPIO_FR_2, /*!< PLFR2: T32A02INB0 */ + GPIO_PL3_T32A02INC1 = GPIO_FR_3, /*!< PLFR3: T32A02INC1 */ + GPIO_PL3_SMI0D7 = GPIO_FR_5, /*!< PLFR5: SMI0D7 */ + GPIO_PL3_TSPI3CS1 = GPIO_FR_6, /*!< PLFR6: TSPI3CS1 */ + GPIO_PL3_TSPI1TXD = GPIO_FR_7, /*!< PLFR7: TSPI1TXD */ + GPIO_PL3_EMARXD1 = GPIO_FR_8, /*!< PLFR8: EMARXD1 */ +} gpio_pl3_func_t; + +/** +* @enum gpio_pl4_func_t +* @brief PortL4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL4_INT12b = 0, /*!< 0: IN112b */ + GPIO_PL4_T32A08OUTA = GPIO_FR_2, /*!< PLFR2: T32A08OUTA */ + GPIO_PL4_T32A08OUTC = GPIO_FR_3, /*!< PLFR3: T32A08OUTC */ +} gpio_pl4_func_t; + +/** + * @enum gpio_pl5_func_t + * @brief PortL5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL5_INT13b = 0, /*!< 0: INT13b */ + GPIO_PL5_T32A08OUTB = GPIO_FR_2, /*!< PLFR2: T32A08OUTB */ +} gpio_pl5_func_t; + +/** + * @enum gpio_pl6_func_t + * @brief PortL6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL6_INT03b = 0, /*!< 0: INT03b */ + GPIO_PL6_T32A09OUTA = GPIO_FR_2, /*!< PLFR2: T32A09OUTA */ + GPIO_PL6_T32A09OUTC = GPIO_FR_3, /*!< PLFR3: T32A09OUTC */ +} gpio_pl6_func_t; + +/** + * @enum gpio_pl7_func_t + * @brief PortL7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PL7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PL7_TRGIN1 = GPIO_FR_1, /*!< PLFR1: TRGIN1 */ + GPIO_PL7_T32A09OUTB = GPIO_FR_2, /*!< PLFR2: T32A09OUTB */ +} gpio_pl7_func_t; + +/** + * @enum gpio_pm0_func_t + * @brief PortM0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM0_EI2C3SDA = GPIO_FR_1, /*!< PMFR1: EI2C3SDA */ + GPIO_PM0_I2C3SDA = GPIO_FR_4, /*!< PMFR4: I2C3SDA */ + GPIO_PM0_UT4RXD = GPIO_FR_5, /*!< PMFR5: UT4RXD */ + GPIO_PM0_TSPI6TXD = GPIO_FR_6, /*!< PMFR6: TSPI6TXD */ + GPIO_PM0_UT4TXDA = GPIO_FR_7, /*!< PMFR7: UT4TXDA */ + GPIO_PM0_EMATXD3 = GPIO_FR_8, /*!< PMFR8: EMATXD3 */ +} gpio_pm0_func_t; + +/** + * @enum gpio_pm1_func_t + * @brief PortM1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM1_EI2C3SCL = GPIO_FR_1, /*!< PMFR1: EI2C3SCL */ + GPIO_PM1_USBB_SOF_TQL = GPIO_FR_3, /*!< PMFR3: USBB_SOF_TQL */ + GPIO_PM1_I2C3SCL = GPIO_FR_4, /*!< PMFR4: I2C3SCL */ + GPIO_PM1_UT4TXDA = GPIO_FR_5, /*!< PMFR5: UT4TXDA */ + GPIO_PM1_TSPI6RXD = GPIO_FR_6, /*!< PMFR6: TSPI6RXD */ + GPIO_PM1_UT4RXD = GPIO_FR_7, /*!< PMFR7: UT4RXD */ + GPIO_PM1_EMATXD2 = GPIO_FR_8, /*!< PMFR8: EMATXD2 */ +} gpio_pm1_func_t; + +/** + * @enum gpio_pm2_func_t + * @brief PortM2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM2_T32A11OUTA = GPIO_FR_2, /*!< PMFR2: T32A11OUTA */ + GPIO_PM2_T32A11OUTC = GPIO_FR_3, /*!< PMFR3: T32A11OUTC */ + GPIO_PM2_UT4RTS_N = GPIO_FR_5, /*!< PMFR5: UT4RTS_N */ + GPIO_PM2_TSPI6SCK = GPIO_FR_6, /*!< PMFR6: TSPI6SCK */ + GPIO_PM2_UT4CTS_N = GPIO_FR_7, /*!< PMFR7: UT4CTS_N */ + GPIO_PM2_EMATXD1 = GPIO_FR_8, /*!< PMFR8: EMATXD1 */ +} gpio_pm2_func_t; + +/** +* @enum gpio_pm3_func_t +* @brief PortM3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM3_INT14b = 0, /*!< 0: INT14b */ + GPIO_PM3_T32A11OUTB = GPIO_FR_2, /*!< PMFR2: T32A11OUTB */ + GPIO_PM3_TSPI6CSIN = GPIO_FR_4, /*!< PMFR4: TSPI6CSIN */ + GPIO_PM3_UT4CTS_N = GPIO_FR_5, /*!< PMFR5: UT4CTS_N */ + GPIO_PM3_TSPI6CS0 = GPIO_FR_6, /*!< PMFR6: TSPI6CS0 */ + GPIO_PM3_UT4RTS_N = GPIO_FR_7, /*!< PMFR7: UT4RTS_N */ + GPIO_PM3_EMATXD0 = GPIO_FR_8, /*!< PMFR8: EMATXD0 */ +} gpio_pm3_func_t; + +/** +* @enum gpio_pm4_func_t +* @brief PortM4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM4_INT15b = 0, /*!< 0: INT15b */ + GPIO_PM4_T32A06OUTB = GPIO_FR_2, /*!< PMFR2: T32A06OUTB */ + GPIO_PM4_TSPI7CSIN = GPIO_FR_4, /*!< PMFR4: TSPI7CSIN */ + GPIO_PM4_TSPI7CS0 = GPIO_FR_6, /*!< PMFR6: TSPI7CS0 */ + GPIO_PM4_FUT1CTS_N = GPIO_FR_7, /*!< PMFR7: FUT1CTS_N */ +} gpio_pm4_func_t; + +/** + * @enum gpio_pm5_func_t + * @brief PortM5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM5_T32A06OUTA = GPIO_FR_2, /*!< PMFR2: T32A06OUTA */ + GPIO_PM5_T32A06OUTC = GPIO_FR_3, /*!< PMFR3: T32A06OUTC */ + GPIO_PM5_TSPI7SCK = GPIO_FR_6, /*!< PMFR6: TSPI7SCK */ + GPIO_PM5_FUT1RTS_N = GPIO_FR_7, /*!< PMFR7: FUT1RTS_N */ +} gpio_pm5_func_t; + +/** + * @enum gpio_pm6_func_t + * @brief PortM6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM6_EI2C4SDA = GPIO_FR_1, /*!< PMFR1: EI2C4SDA */ + GPIO_PM6_T32A07OUTA = GPIO_FR_2, /*!< PMFR2: T32A07OUTA */ + GPIO_PM6_T32A07OUTC = GPIO_FR_3, /*!< PMFR3: T32A07OUTC */ + GPIO_PM6_I2C4SDA = GPIO_FR_4, /*!< PMFR4: I2C4SDA */ + GPIO_PM6_FUT1IRIN = GPIO_FR_5, /*!< PMFR5: FUT1IRIN */ + GPIO_PM6_TSPI7RXD = GPIO_FR_6, /*!< PMFR6: TSPI7RXD */ + GPIO_PM6_FUT1RXD = GPIO_FR_7, /*!< PMFR7: FUT1RXD */ +} gpio_pm6_func_t; + +/** + * @enum gpio_pm7_func_t + * @brief PortM7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PM7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PM7_EI2C4SCL = GPIO_FR_1, /*!< PMFR1: EI2C4SCL */ + GPIO_PM7_T32A07OUTB = GPIO_FR_2, /*!< PMFR2: T32A07OUTB */ + GPIO_PM7_I2C4SCL = GPIO_FR_4, /*!< PMFR4: I2C4SCL */ + GPIO_PM7_FUT1IROUT = GPIO_FR_5, /*!< PMFR5: FUT1IROUT */ + GPIO_PM7_TSPI7TXD = GPIO_FR_6, /*!< PMFR6: TSPI7TXD */ + GPIO_PM7_FUT1TXD = GPIO_FR_7, /*!< PMFR7: FUT1TXD */ +} gpio_pm7_func_t; + +/** + * @enum gpio_pn0_func_t + * @brief PortN0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN0_AINA00 = GPIO_FR_NA, /*!< N/A: AINA00 */ +} gpio_pn0_func_t; + +/** + * @enum gpio_pn1_func_t + * @brief PortN1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN1_AINA01 = GPIO_FR_NA, /*!< N/A: AINA01 */ +} gpio_pn1_func_t; + +/** + * @enum gpio_pn2_func_t + * @brief PortN2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN2_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN2_AINA02 = GPIO_FR_NA, /*!< N/A: AINA02 */ +} gpio_pn2_func_t; + +/** + * @enum gpio_pn3_func_t + * @brief PortN3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN3_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN3_AINA03 = GPIO_FR_NA, /*!< N/A: AINA03 */ +} gpio_pn3_func_t; + +/** +* @enum gpio_pn4_func_t +* @brief PortN4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PN4_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN4_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN4_AINA04 = GPIO_FR_NA, /*!< N/A: AINA04 */ +} gpio_pn4_func_t; + +/** + * @enum gpio_pn5_func_t + * @brief PortN5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN5_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN5_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN5_AINA05 = GPIO_FR_NA, /*!< N/A: AINA05 */ +} gpio_pn5_func_t; + +/** + * @enum gpio_pn6_func_t + * @brief PortN6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN6_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN6_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN6_AINA06 = GPIO_FR_NA, /*!< N/A: AINA06 */ +} gpio_pn6_func_t; + +/** + * @enum gpio_pn7_func_t + * @brief PortN7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN7_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PN7_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PN7_AINA07 = GPIO_FR_NA, /*!< N/A: AINA07 */ +} gpio_pn7_func_t; + +/** + * @enum gpio_pp0_func_t + * @brief PortP0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP0_AINA08 = 0, /*!< 0: AINA08 */ + GPIO_PP0_T32A04INA0 = GPIO_FR_2, /*!< PPFR2: T32A04INA0 */ + GPIO_PP0_T32A04INC0 = GPIO_FR_3, /*!< PPFR3: T32A04INC0 */ + GPIO_PP0_T32A04INB1 = GPIO_FR_5, /*!< PPFR5: T32A04INB1 */ +} gpio_pp0_func_t; + +/** + * @enum gpio_pp1_func_t + * @brief PortP1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP1_AINA09 = 0, /*!< 0: AINA09 */ + GPIO_PP1_T32A04INB0 = GPIO_FR_2, /*!< PPFR2: T32A04INB0 */ + GPIO_PP1_T32A04INC1 = GPIO_FR_3, /*!< PPFR3: T32A04INC1 */ + GPIO_PP1_T32A04INA1 = GPIO_FR_5, /*!< PPFR5: T32A04INA1 */ +} gpio_pp1_func_t; + +/** + * @enum gpio_pp2_func_t + * @brief PortP2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP2_AINA10 = 0, /*!< 0: AINA10 */ + GPIO_PP2_T32A05INA0 = GPIO_FR_2, /*!< PPFR2: T32A05INA0 */ + GPIO_PP2_T32A05INC0 = GPIO_FR_3, /*!< PPFR3: T32A05INC0 */ + GPIO_PP2_T32A05INB1 = GPIO_FR_5, /*!< PPFR5: T32A05INB1 */ +} gpio_pp2_func_t; + +/** +* @enum gpio_pp3_func_t +* @brief PortP3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP3_AINA11 = 0, /*!< 0: AINA11 */ + GPIO_PP3_T32A05INB0 = GPIO_FR_2, /*!< PPFR2: T32A05INB0 */ + GPIO_PP3_T32A05INC1 = GPIO_FR_3, /*!< PPFR3: T32A05INC1 */ + GPIO_PP3_T32A05INA1 = GPIO_FR_5, /*!< PPFR5: T32A05INA1 */ +} gpio_pp3_func_t; + +/** +* @enum gpio_pp4_func_t +* @brief PortP4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP4_AINA12 = 0, /*!< 0: AINA12 */ + GPIO_PP4_T32A06INA0 = GPIO_FR_2, /*!< PPFR2: T32A06INA0 */ + GPIO_PP4_T32A06INC0 = GPIO_FR_3, /*!< PPFR3: T32A06INC0 */ + GPIO_PP4_T32A06INB1 = GPIO_FR_5, /*!< PPFR5: T32A06INB1 */ +} gpio_pp4_func_t; + +/** +* @enum gpio_pp5_func_t +* @brief PortP5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP5_AINA13 = 0, /*!< 0: AINA13 */ + GPIO_PP5_T32A06INB0 = GPIO_FR_2, /*!< PPFR2: T32A06INB0 */ + GPIO_PP5_T32A06INC1 = GPIO_FR_3, /*!< PPFR3: T32A06INC1 */ + GPIO_PP5_T32A06INA1 = GPIO_FR_5, /*!< PPFR5: T32A06INA1 */ +} gpio_pp5_func_t; + +/** + * @enum gpio_pp6_func_t + * @brief PortP6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PP6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP6_AINA14 = 0, /*!< 0: AINA14 */ + GPIO_PP6_INT10b = 0, /*!< 0: INT10b */ + GPIO_PP6_T32A07INA0 = GPIO_FR_2, /*!< PPFR2: T32A07INA0 */ + GPIO_PP6_T32A07INC0 = GPIO_FR_3, /*!< PPFR3: T32A07INC0 */ + GPIO_PP6_T32A07INB1 = GPIO_FR_5, /*!< PPFR5: T32A07INB1 */ +} gpio_pp6_func_t; + +/** +* @enum gpio_pp7_func_t +* @brief PortP7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PP7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PP7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PP7_AINA15 = 0, /*!< 0: AINA15 */ + GPIO_PP7_INT11b = 0, /*!< 0: INT11b */ + GPIO_PP7_T32A07INB0 = GPIO_FR_2, /*!< PPFR2: T32A07INB0 */ + GPIO_PP7_T32A07INC1 = GPIO_FR_3, /*!< PPFR3: T32A07INC1 */ + GPIO_PP7_T32A07INA1 = GPIO_FR_5, /*!< PPFR5: T32A07INA1 */ +} gpio_pp7_func_t; + +/** + * @enum gpio_pr0_func_t + * @brief PortR0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR0_AINA16 = 0, /*!< 0: AINA16 */ + GPIO_PR0_T32A08INA0 = GPIO_FR_2, /*!< PRFR2: T32A08INA0 */ + GPIO_PR0_T32A08INC0 = GPIO_FR_3, /*!< PRFR3: T32A08INC0 */ +} gpio_pr0_func_t; + +/** + * @enum gpio_pr1_func_t + * @brief PortR1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR1_AINA17 = 0, /*!< 0: AINA17 */ + GPIO_PR1_T32A08INB0 = GPIO_FR_2, /*!< PRFR2: T32A08INB0 */ + GPIO_PR1_T32A08INC1 = GPIO_FR_3, /*!< PRFR3: T32A08INC1 */ +} gpio_pr1_func_t; + +/** + * @enum gpio_pr2_func_t + * @brief PortR2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR2_AINA18 = 0, /*!< 0: AINA18 */ + GPIO_PR2_T32A09INA0 = GPIO_FR_2, /*!< PRFR2: T32A09INA0 */ + GPIO_PR2_T32A09INC0 = GPIO_FR_3, /*!< PRFR3: T32A09INC0 */ +} gpio_pr2_func_t; + +/** + * @enum gpio_pr3_func_t + * @brief PortR3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR3_AINA19 = 0, /*!< 0: AINA19 */ + GPIO_PR3_T32A09INB0 = GPIO_FR_2, /*!< PRFR2: T32A09INB0 */ + GPIO_PR3_T32A09INC1 = GPIO_FR_3, /*!< PRFR3: T32A09INC1 */ +} gpio_pr3_func_t; + +/** + * @enum gpio_pr4_func_t + * @brief PortR4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR4_AINA20 = 0, /*!< 0: AINA20 */ + GPIO_PR4_T32A10INA0 = GPIO_FR_2, /*!< PRFR2: T32A10INA0 */ + GPIO_PR4_T32A10INC0 = GPIO_FR_3, /*!< PRFR3: T32A10INC0 */ +} gpio_pr4_func_t; + +/** + * @enum gpio_pr5_func_t + * @brief PortR5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR5_AINA21 = 0, /*!< 0: AINA21 */ + GPIO_PR5_T32A10INB0 = GPIO_FR_2, /*!< PRFR2: T32A10INB0 */ + GPIO_PR5_T32A10INC1 = GPIO_FR_3, /*!< PRFR3: T32A10INC1 */ +} gpio_pr5_func_t; + +/** + * @enum gpio_pr6_func_t + * @brief PortR6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR6_AINA22 = 0, /*!< 0: AINA22 */ + GPIO_PR6_T32A11INA0 = GPIO_FR_2, /*!< PRFR2: T32A11INA0 */ + GPIO_PR6_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC0 */ +} gpio_pr6_func_t; + +/** + * @enum gpio_pr7_func_t + * @brief PortR7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PR7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PR7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PR7_AINA23 = 0, /*!< 0: AINA23 */ + GPIO_PR7_T32A11INB0 = GPIO_FR_2, /*!< PRFR2: T32A11INB0 */ + GPIO_PR7_T32A11INC0 = GPIO_FR_3, /*!< PRFR3: T32A11INC1 */ +} gpio_pr7_func_t; + + +/** + * @enum gpio_pt0_func_t + * @brief PortT0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PT0_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PT0_DAC0 = GPIO_FR_NA, /*!< N/A: DAC0 */ +} gpio_pt0_func_t; + +/** + * @enum gpio_pt1_func_t + * @brief PortT1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PT1_OUTPUT = GPIO_FR_NA, /*!< N/A: Output Port */ + GPIO_PT1_DAC1 = GPIO_FR_NA, /*!< N/A: DAC1 */ +} gpio_pt1_func_t; + +/** + * @enum gpio_pt2_func_t + * @brief PortT2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT2_CEC0 = GPIO_FR_7, /*!< PTFR1: CEC0 Input/Output */ +} gpio_pt2_func_t; + +/** + * @enum gpio_pt3_func_t + * @brief PortT3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT3_INT00b = 0, /*!< 0: INT00b */ + GPIO_PT3_RTCOUT = GPIO_FR_1, /*!< PTFR1: RTCOUT */ + GPIO_PT3_T32A03OUTA = GPIO_FR_2, /*!< PTFR2: T32A03OUTA */ + GPIO_PT3_T32A03OUTC = GPIO_FR_3, /*!< PTFR3: T32A03OUTC */ + GPIO_PT3_RXIN0 = 0, /*!< 0: RXIN0 */ + GPIO_PT3_TRGIN2 = GPIO_FR_6, /*!< PTFR6: TRGIN2 */ +} gpio_pt3_func_t; + +/** + * @enum gpio_pt4_func_t + * @brief PortT4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT4_INT01b = 0, /*!< 0: INT01b */ + GPIO_PT4_RXIN1 = 0, /*!< 0: RXIN1 */ + GPIO_PT4_EMATXCLK = GPIO_FR_8, /*!< PTFR8: EMATXCLK */ +} gpio_pt4_func_t; + +/** + * @enum gpio_pt5_func_t + * @brief PortT5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PT5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PT5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PT5_INT02b = 0, /*!< 0: INT02b */ + GPIO_PT5_T32A03OUTB = GPIO_FR_2, /*!< PTFR2: T32A03OUTB */ +} gpio_pt5_func_t; + +/** + * @enum gpio_pu0_func_t + * @brief PortU0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU0_T32A12OUTA = GPIO_FR_2, /*!< PUFR2: T32A12OUTA */ + GPIO_PU0_T32A12OUTC = GPIO_FR_3, /*!< PUFR3: T32A12OUTC */ + GPIO_PU0_USBB_ID = GPIO_FR_5, /*!< PUFR5: USBB_ID */ + GPIO_PU0_UT4TXDA = GPIO_FR_7, /*!< PUFR7: UT4TXDA */ +} gpio_pu0_func_t; + +/** + * @enum gpio_pu2_func_t + * @brief PortU2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU2_INT06b = 0, /*!< 0: INT06b */ + GPIO_PU2_T32A12INA0 = GPIO_FR_2, /*!< PUFR2: T32A12INA0 */ + GPIO_PU2_T32A12INC0 = GPIO_FR_3, /*!< PUFR3: T32A12INC0 */ + GPIO_PU2_TSSI1TCK = GPIO_FR_6, /*!< PUFR6: TSSI1TCK */ + GPIO_PU2_UT4CTS_N = GPIO_FR_7, /*!< PUFR7: UT4CTS_N */ +} gpio_pu2_func_t; + +/** + * @enum gpio_pu3_func_t + * @brief PortU3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU3_INT07b = 0, /*!< 0: INT07b */ + GPIO_PU3_T32A12INB0 = GPIO_FR_2, /*!< PUFR2: T32A12INB0 */ + GPIO_PU3_T32A12INC1 = GPIO_FR_3, /*!< PUFR3: T32A12INC1 */ + GPIO_PU3_USBB_VBUSEN = GPIO_FR_5,/*!< PUFR5: USBB_VBUSEN */ + GPIO_PU3_TSSI1TFS = GPIO_FR_6, /*!< PUFR6: TSSI1TFS */ + GPIO_PU3_UT4RTS_N = GPIO_FR_7, /*!< PUFR7: UT4RTS_N */ +} gpio_pu3_func_t; + +/** + * @enum gpio_pu4_func_t + * @brief PortU4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU4_INT08b = 0, /*!< 0: INT08b */ + GPIO_PU4_T32A13INB0 = GPIO_FR_2, /*!< PUFR2: T32A13INB0 */ + GPIO_PU4_T32A13INC1 = GPIO_FR_3, /*!< PUFR3: T32A13INC1 */ + GPIO_PU4_TSSI1TXD = GPIO_FR_6, /*!< PUFR6: TSSI1TXD */ + GPIO_PU4_UT3RTS_N = GPIO_FR_7, /*!< PUFR7: UT3RTS_N */ +} gpio_pu4_func_t; + +/** + * @enum gpio_pu5_func_t + * @brief PortU5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU5_INT09b = 0, /*!< 0: INT09b */ + GPIO_PU5_T32A13INA0 = GPIO_FR_2, /*!< PUFR2: T32A13INA0 */ + GPIO_PU5_T32A13INC0 = GPIO_FR_3, /*!< PUFR3: T32A13INC0 */ + GPIO_PU5_TSSI1RXD = GPIO_FR_6, /*!< PUFR6: TSSI1RXD */ + GPIO_PU5_UT3CTS_N = GPIO_FR_7, /*!< PUFR7: UT3CTS_N */ +} gpio_pu5_func_t; + +/** + * @enum gpio_pu6_func_t + * @brief PortU6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU6_T32A13OUTA = GPIO_FR_2, /*!< PUFR2: T32A13OUTA */ + GPIO_PU6_T32A13OUTC = GPIO_FR_3, /*!< PUFR3: T32A13OUTC */ + GPIO_PU6_TSSI1RFS = GPIO_FR_6, /*!< PUFR6: TSSI1RFS */ + GPIO_PU6_UT3RXD = GPIO_FR_7, /*!< PUFR7: UT3RXD */ + GPIO_PU6_CANBRX = GPIO_FR_8, /*!< PUFR8: CANBRX */ +} gpio_pu6_func_t; + +/** + * @enum gpio_pu7_func_t + * @brief PortU7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PU7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PU7_T32A13OUTB = GPIO_FR_2, /*!< PUFR2: T32A13OUTB */ + GPIO_PU7_TSSI1RCK = GPIO_FR_6, /*!< PUFR6: TSSI1RCK */ + GPIO_PU7_UT3TXDA = GPIO_FR_7, /*!< PUFR7: UT3TXDA */ + GPIO_PU7_CANBTX = GPIO_FR_8, /*!< PUFR8: CANBTX */ +} gpio_pu7_func_t; + +/** + * @enum gpio_pv0_func_t + * @brief PortV0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV0_T32A09INA0 = GPIO_FR_2, /*!< PVFR2: T32A09INA0 */ + GPIO_PV0_T32A09INC0 = GPIO_FR_3, /*!< PVFR3: T32A09INC0 */ + GPIO_PV0_ISDBIN0 = 0, /*!< 0: ISDBIN0 */ + GPIO_PV0_UO0 = GPIO_FR_5, /*!< PVFR5: UO0 */ + GPIO_PV0_UT3RXD = GPIO_FR_6, /*!< PVFR6: UT3RXD */ + GPIO_PV0_UT3TXDA = GPIO_FR_7, /*!< PVFR7: UT3TXDA */ + GPIO_PV0_EMARXD0 = GPIO_FR_8, /*!< PVFR8: EMARXD0 */ +} gpio_pv0_func_t; + +/** + * @enum gpio_pv1_func_t + * @brief PortV1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV1_T32A09INB0 = GPIO_FR_2, /*!< PVFR2: T32A09INB0 */ + GPIO_PV1_T32A09INC1 = GPIO_FR_3, /*!< PVFR3: T32A09INC1 */ + GPIO_PV1_ISDBIN1 = 0, /*!< 0: ISDBIN1 */ + GPIO_PV1_XO0 = GPIO_FR_5, /*!< PVFR5: XO0 */ + GPIO_PV1_UT3TXDA = GPIO_FR_6, /*!< PVFR6: UT3TXDA */ + GPIO_PV1_UT3RXD = GPIO_FR_7, /*!< PVFR7: UT3RXD */ + GPIO_PV1_EMARXD1 = GPIO_FR_8, /*!< PVFR8: EMARXD1 */ +} gpio_pv1_func_t; + +/** + * @enum gpio_pv2_func_t + * @brief PortV2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV2_T32A09OUTA = GPIO_FR_2, /*!< PVFR2: T32A09OUTA */ + GPIO_PV2_T32A09OUTC = GPIO_FR_3, /*!< PVFR3: T32A09OUTC */ + GPIO_PV2_ISDBIN2 = 0, /*!< 0: ISDBIN2 */ + GPIO_PV2_VO0 = GPIO_FR_5, /*!< PVFR5: VO0 */ + GPIO_PV2_UT3RTS_N = GPIO_FR_6, /*!< PVFR6: UT3RTS_N */ + GPIO_PV2_UT3CTS_N = GPIO_FR_7, /*!< PVFR7: UT3CTS_N */ + GPIO_PV2_EMARXD2 = GPIO_FR_8, /*!< PVFR8: EMARXD2 */ +} gpio_pv2_func_t; + +/** + * @enum gpio_pv3_func_t + * @brief PortV3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV3_T32A09OUTB = GPIO_FR_2, /*!< PVFR2: T32A09OUTB */ + GPIO_PV3_ISDBIN3 = 0, /*!< 0: ISDBIN3 */ + GPIO_PV3_YO0 = GPIO_FR_5, /*!< PVFR5: YO0 */ + GPIO_PV3_UT3CTS_N = GPIO_FR_6, /*!< PVFR6: UT3CTS_N */ + GPIO_PV3_UT3RTS_N = GPIO_FR_7, /*!< PVFR7: UT3RTS_N */ + GPIO_PV3_EMARXD3 = GPIO_FR_8, /*!< PVFR8: EMARXD3 */ +} gpio_pv3_func_t; + +/** + * @enum gpio_pv4_func_t + * @brief PortV4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV4_EI2C2SCL = GPIO_FR_1, /*!< PVFR1: EI2C2SCL */ + GPIO_PV4_T32A04OUTB = GPIO_FR_2, /*!< PVFR2: T32A04OUTB */ + GPIO_PV4_TSPI5RXD = GPIO_FR_4, /*!< PVFR4: TSPI5RXD */ + GPIO_PV4_WO0 = GPIO_FR_5, /*!< PVFR5: WO0 */ + GPIO_PV4_I2C2SCL = GPIO_FR_6, /*!< PVFR6: I2C2SCL */ + GPIO_PV4_UT1RXD = GPIO_FR_7, /*!< PVFR7: UT1RXD */ + GPIO_PV4_CANATX = GPIO_FR_8, /*!< PVFR8: CANATX */ +} gpio_pv4_func_t; + +/** + * @enum gpio_pv5_func_t + * @brief PortV5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV5_EI2CSDA = GPIO_FR_1, /*!< PVFR1: EI2CSDA */ + GPIO_PV5_T32A04OUTA = GPIO_FR_2, /*!< PVFR2: T32A04OUTA */ + GPIO_PV5_T32A04OUTC = GPIO_FR_3, /*!< PVFR3: T32A04OUTC */ + GPIO_PV5_TSPI5TXD = GPIO_FR_4, /*!< PVFR4: TSPI5TXD */ + GPIO_PV5_ZO0 = GPIO_FR_5, /*!< PVFR5: ZO0 */ + GPIO_PV5_I2C2SDA = GPIO_FR_6, /*!< PVFR6: I2C2SDA */ + GPIO_PV5_UT1TXDA = GPIO_FR_7, /*!< PVFR7: UT1TXDA */ + GPIO_PV5_CANARX = GPIO_FR_8, /*!< PVFR8: CANARX */ +} gpio_pv5_func_t; + +/** + * @enum gpio_pv6_func_t + * @brief PortV6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV6_T32A05OUTA = GPIO_FR_2, /*!< PVFR2: T32A05OUTA */ + GPIO_PV6_T32A05OUTC = GPIO_FR_3, /*!< PVFR3: T32A05OUTC */ + GPIO_PV6_TSPI5SCK = GPIO_FR_4, /*!< PVFR4: TSPI5SCK */ + GPIO_PV6_EMG0 = GPIO_FR_5, /*!< PVFR5: EMG0 */ + GPIO_PV6_UT1CTS_N = GPIO_FR_7, /*!< PVFR7: UT1CTS_N */ +} gpio_pv6_func_t; + +/** + * @enum gpio_pv7_func_t + * @brief PortV7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PV7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PV7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PV7_T32A05OUTB = GPIO_FR_2, /*!< PVFR2: T32A05OUTB */ + GPIO_PV7_TSPI5CS0 = GPIO_FR_4, /*!< PVFR4: TSPI5CS0 */ + GPIO_PV7_OVV0 = GPIO_FR_5, /*!< PVFR5: OVV0 */ + GPIO_PV7_TSPI5CSIN = GPIO_FR_6, /*!< PVFR6: TSPI5CSIN */ + GPIO_PV7_UT1RTS_N = GPIO_FR_7, /*!< PVFR7: UT1RTS_N */ +} gpio_pv7_func_t; + +/** + * @enum gpio_pw0_func_t + * @brief PortW0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW0_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW0_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW0_TSPI8CS0 = GPIO_FR_4, /*!< PWFR4: TSPI8CS0 */ + GPIO_PW0_T32A00OUTB = GPIO_FR_5, /*!< PWFR5: T32A00OUTB */ + GPIO_PW0_TSPI8CSIN = GPIO_FR_6, /*!< PWFR6: TSPI8CSIN */ +} gpio_pw0_func_t; + +/** + * @enum gpio_pw1_func_t + * @brief PortW1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW1_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW1_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW1_TSPI8SCK = GPIO_FR_4, /*!< PWFR4: TSPI8SCK */ + GPIO_PW1_T32A00OUTA = GPIO_FR_5, /*!< PWFR5: T32A00OUTA */ + GPIO_PW1_T32A00OUTC = GPIO_FR_7, /*!< PWFR7: T32A00OUTC */ +} gpio_pw1_func_t; + +/** + * @enum gpio_pw2_func_t + * @brief PortW2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW2_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW2_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW2_TSPI8RXD = GPIO_FR_4, /*!< PWFR4: TSPI8RXD */ + GPIO_PW2_T32A01OUTA = GPIO_FR_5, /*!< PWFR5: T32A01OUTA */ + GPIO_PW2_T32A01OUTC = GPIO_FR_7, /*!< PWFR7: T32A01OUTC */ +} gpio_pw2_func_t; + +/** + * @enum gpio_pw3_func_t + * @brief PortW3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW3_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW3_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW3_TSPI8TXD = GPIO_FR_4, /*!< PWFR4: TSPI8TXD */ + GPIO_PW3_T32A01OUTB = GPIO_FR_5, /*!< PWFR5: T32A01OUTB */ +} gpio_pw3_func_t; + +/** + * @enum gpio_pw4_func_t + * @brief PortW4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW4_T32A11INA1 = GPIO_FR_3, /*!< PWFR3: T32A11INA1 */ + GPIO_PW4_T32A10OUTB = GPIO_FR_5, /*!< PWFR5: T32A10OUTB */ + GPIO_PW4_ISDCIN0 = 0, /*!< 0: ISDCIN0 */ + GPIO_PW4_T32A10INA0 = GPIO_FR_7, /*!< PWFR7: T32A10INA0 */ +} gpio_pw4_func_t; + +/** + * @enum gpio_pw5_func_t + * @brief PortW5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW5_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW5_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW5_T32A10OUTA = GPIO_FR_5, /*!< PWFR5: T32A10OUTA */ + GPIO_PW5_ISDCIN1 = 0, /*!< 0: ISDCIN1 */ + GPIO_PW5_T32A10OUTC = GPIO_FR_7, /*!< PWFR7: T32A10OUTC */ +} gpio_pw5_func_t; + +/** + * @enum gpio_pw6_func_t + * @brief PortW6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW6_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW6_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW6_T32A11OUTA = GPIO_FR_5, /*!< PWFR5: T32A11OUTA */ + GPIO_PW6_ISDCIN2 = 0, /*!< 0: ISDCIN2 */ + GPIO_PW6_T32A11OUTC = GPIO_FR_7, /*!< PWFR7: T32A11OUTC */ +} gpio_pw6_func_t; + +/** + * @enum gpio_pw7_func_t + * @brief PortW7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PW7_INPUT = 0, /*!< 0: Input Port */ + GPIO_PW7_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PW7_T32A10INA1 = GPIO_FR_3, /*!< PWFR3: T32A10INA1 */ + GPIO_PW7_T32A11OUTB = GPIO_FR_5, /*!< PWFR5: T32A11OUTB */ + GPIO_PW7_ISDCIN3 = 0, /*!< 0: ISDCIN3 */ + GPIO_PW7_T32A11INA0 = GPIO_FR_7, /*!< PWFR7: T32A11INA0 */ +} gpio_pw7_func_t; + +/** + * @enum gpio_py0_func_t + * @brief PortY0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY0_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY0_X1 = GPIO_FR_NA, /*!< N/A: X1 */ +} gpio_py0_func_t; + +/** + * @enum gpio_py1_func_t + * @brief PortY1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY1_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY1_X2 = GPIO_FR_NA, /*!< N/A: X2 */ +} gpio_py1_func_t; + +/** + * @enum gpio_py2_func_t + * @brief PortY2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY2_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY2_XT1 = GPIO_FR_NA, /*!< N/A: XT1 */ +} gpio_py2_func_t; + +/** + * @enum gpio_py3_func_t + * @brief PortY3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY3_INPUT = GPIO_FR_NA, /*!< N/A: Input Port */ + GPIO_PY3_XT2 = GPIO_FR_NA, /*!< N/A: XT2 */ +} gpio_py3_func_t; + +/** + * @enum gpio_py4_func_t + * @brief PortY4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PY4_INPUT = 0, /*!< 0: Input Port */ + GPIO_PY4_OUTPUT = 0, /*!< 0: Output Port */ + GPIO_PY4_ISDCOUT = GPIO_FR_1, /*!< PYFR1: ISDCOUT */ + GPIO_PY4_EEXBCLK = GPIO_FR_4, /*!< PYFR4: EEXBCLK */ + GPIO_PY4_USBA_SOF_TGL = GPIO_FR_6, /*!< PYFR6: USBA_SOF_TGL */ +} gpio_py4_func_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ +/*! + * @brief Pin Exist Table + * @details Bit0 :GPIO_Mode_DATA + * @details Bit1 :GPIO_Mode_CR + * @details Bit2 :GPIO_Mode_FR1 + * @details Bit3 :GPIO_Mode_FR2 + * @details Bit4 :GPIO_Mode_FR3 + * @details Bit5 :GPIO_Mode_FR4 + * @details Bit6 :GPIO_Mode_FR5 + * @details Bit7 :GPIO_Mode_FR6 + * @details Bit8 :GPIO_Mode_FR7 + * @details Bit9 :GPIO_Mode_FR8 + * @details Bit10 :GPIO_Mode_OD + * @details Bit11 :GPIO_Mode_PUP + * @details Bit12 :GPIO_Mode_PDN + * @details Bit13 :GPIO_Mode_IE + */ +static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = { + /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ + { GPIO_PORT_A_0, GPIO_PORT_A_1, GPIO_PORT_A_2, GPIO_PORT_A_3, GPIO_PORT_A_4, GPIO_PORT_A_5, GPIO_PORT_A_6, GPIO_PORT_A_7 }, /** GPIO_PORT_A */ + { GPIO_PORT_B_0, GPIO_PORT_B_1, GPIO_PORT_B_2, GPIO_PORT_B_3, GPIO_PORT_B_4, GPIO_PORT_B_5, GPIO_PORT_B_6, GPIO_PORT_B_7 }, /** GPIO_PORT_B */ + { GPIO_PORT_C_0, GPIO_PORT_C_1, GPIO_PORT_C_2, GPIO_PORT_C_3, GPIO_PORT_C_4, GPIO_PORT_C_5, GPIO_PORT_C_6, GPIO_PORT_C_7 }, /** GPIO_PORT_C */ + { GPIO_PORT_D_0, GPIO_PORT_D_1, GPIO_PORT_D_2, GPIO_PORT_D_3, GPIO_PORT_D_4, GPIO_PORT_D_5, GPIO_PORT_D_6, GPIO_PORT_D_7 }, /** GPIO_PORT_D */ + { GPIO_PORT_E_0, GPIO_PORT_E_1, GPIO_PORT_E_2, GPIO_PORT_E_3, GPIO_PORT_E_4, GPIO_PORT_E_5, GPIO_PORT_E_6, GPIO_PORT_E_7 }, /** GPIO_PORT_E */ + { GPIO_PORT_F_0, GPIO_PORT_F_1, GPIO_PORT_F_2, GPIO_PORT_F_3, GPIO_PORT_F_4, GPIO_PORT_F_5, GPIO_PORT_F_6, GPIO_PORT_F_7 }, /** GPIO_PORT_F */ + { GPIO_PORT_G_0, GPIO_PORT_G_1, GPIO_PORT_G_2, GPIO_PORT_G_3, GPIO_PORT_G_4, GPIO_PORT_G_5, GPIO_PORT_G_6, GPIO_PORT_G_7 }, /** GPIO_PORT_G */ + { GPIO_PORT_H_0, GPIO_PORT_H_1, GPIO_PORT_H_2, GPIO_PORT_H_3, GPIO_PORT_H_4, GPIO_PORT_H_5, GPIO_PORT_H_6, GPIO_PORT_H_7 }, /** GPIO_PORT_H */ + { GPIO_PORT_J_0, GPIO_PORT_J_1, GPIO_PORT_J_2, GPIO_PORT_J_3, GPIO_PORT_J_4, GPIO_PORT_J_5, GPIO_PORT_J_6, GPIO_PORT_J_7 }, /** GPIO_PORT_J */ + { GPIO_PORT_K_0, GPIO_PORT_K_1, GPIO_PORT_K_2, GPIO_PORT_K_3, GPIO_PORT_K_4, GPIO_PORT_K_5, GPIO_PORT_K_6, GPIO_PORT_K_7 }, /** GPIO_PORT_K */ + { GPIO_PORT_L_0, GPIO_PORT_L_1, GPIO_PORT_L_2, GPIO_PORT_L_3, GPIO_PORT_L_4, GPIO_PORT_L_5, GPIO_PORT_L_6, GPIO_PORT_L_7 }, /** GPIO_PORT_L */ + { GPIO_PORT_M_0, GPIO_PORT_M_1, GPIO_PORT_M_2, GPIO_PORT_M_3, GPIO_PORT_M_4, GPIO_PORT_M_5, GPIO_PORT_M_6, GPIO_PORT_M_7 }, /** GPIO_PORT_M */ + { GPIO_PORT_N_0, GPIO_PORT_N_1, GPIO_PORT_N_2, GPIO_PORT_N_3, GPIO_PORT_N_4, GPIO_PORT_N_5, GPIO_PORT_N_6, GPIO_PORT_N_7 }, /** GPIO_PORT_N */ + { GPIO_PORT_P_0, GPIO_PORT_P_1, GPIO_PORT_P_2, GPIO_PORT_P_3, GPIO_PORT_P_4, GPIO_PORT_P_5, GPIO_PORT_P_6, GPIO_PORT_P_7 }, /** GPIO_PORT_P */ + { GPIO_PORT_R_0, GPIO_PORT_R_1, GPIO_PORT_R_2, GPIO_PORT_R_3, GPIO_PORT_R_4, GPIO_PORT_R_5, GPIO_PORT_R_6, GPIO_PORT_R_7 }, /** GPIO_PORT_R */ + { GPIO_PORT_T_0, GPIO_PORT_T_1, GPIO_PORT_T_2, GPIO_PORT_T_3, GPIO_PORT_T_4, GPIO_PORT_T_5, GPIO_PORT_T_6, GPIO_PORT_T_7 }, /** GPIO_PORT_T */ + { GPIO_PORT_U_0, GPIO_PORT_U_1, GPIO_PORT_U_2, GPIO_PORT_U_3, GPIO_PORT_U_4, GPIO_PORT_U_5, GPIO_PORT_U_6, GPIO_PORT_U_7 }, /** GPIO_PORT_U */ + { GPIO_PORT_V_0, GPIO_PORT_V_1, GPIO_PORT_V_2, GPIO_PORT_V_3, GPIO_PORT_V_4, GPIO_PORT_V_5, GPIO_PORT_V_6, GPIO_PORT_V_7 }, /** GPIO_PORT_V */ + { GPIO_PORT_W_0, GPIO_PORT_W_1, GPIO_PORT_W_2, GPIO_PORT_W_3, GPIO_PORT_W_4, GPIO_PORT_W_5, GPIO_PORT_W_6, GPIO_PORT_W_7 }, /** GPIO_PORT_W */ + { GPIO_PORT_Y_0, GPIO_PORT_Y_1, GPIO_PORT_Y_2, GPIO_PORT_Y_3, GPIO_PORT_Y_4, GPIO_PORT_Y_5, GPIO_PORT_Y_6, GPIO_PORT_Y_7 }, /** GPIO_PORT_Y */ +}; +/** + * @} + */ /* End of group GPIO_Private_typedef */ +/*----------------------------------*/ +/** + * @brief GPIO handle structure definition. +*/ +/*----------------------------------*/ +typedef struct gpio_pa_handle { + TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ + TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ + TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ + TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ + TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ + TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ + TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ + TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ + TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */ + TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ + TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ + TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ + TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ + TSB_PP_TypeDef *p_pp_instance; /*!< Registers base address. */ + TSB_PR_TypeDef *p_pr_instance; /*!< Registers base address. */ + TSB_PT_TypeDef *p_pt_instance; /*!< Registers base address. */ + TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */ + TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ + TSB_PW_TypeDef *p_pw_instance; /*!< Registers base address. */ + TSB_PY_TypeDef *p_py_instance; /*!< Registers base address. */ +} _gpio_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __GPIO_M4NR_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_hal.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_hal.h new file mode 100644 index 0000000..1204fa6 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_hal.h @@ -0,0 +1,160 @@ +/** + ******************************************************************************* + * @file txz_hal.h + * @brief This file provides all the functions prototypes for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __HAL_H +#define __HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup HAL HAL + * @brief HAL Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_macro HAL Exported Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_define HAL Exported Define + * @{ + */ +#if defined ( __CC_ARM ) /* RealView Compiler */ +extern uint32_t Load$$FLASH_CODE_RAM$$Base; +extern uint32_t Image$$FLASH_CODE_RAM$$Base; +extern uint32_t Load$$FLASH_CODE_RAM$$Length; + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma section = "FLASH_CODE_RAM" +#pragma section = "FLASH_CODE_ROM" +#endif + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base +#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base +#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM")) +#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM")) +#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM")) +#endif + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_define HAL Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_typedef HAL Exported Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Exported_functions HAL Exported Functions + * @{ + */ + +void hal_inc_tick(void); +uint32_t hal_get_tick(void); +void wait(uint32_t count); +void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size); +void fc_ram_con_reg_set(uint32_t sysclock); + +/** + * @} + */ /* End of group HAL_Exported_functions */ + +/** + * @} + */ /* End of group HAL */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __HAL_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_i2c.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_i2c.h new file mode 100644 index 0000000..d0f9d90 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_i2c.h @@ -0,0 +1,818 @@ +/** + ******************************************************************************* + * @file txz_i2c.h + * @brief This file provides all the functions prototypes for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __I2C_H +#define __I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +#ifdef __DEBUG__ +/** + * @name I2C_NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of name I2C_NULL Pointer */ +#endif + +/** + * @name I2CxST Macro Definition. + * @brief I2CxST Register Macro Definition. + * @{ + */ +#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */ +#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */ +#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */ +#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */ +#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */ +/** + * @} + */ /* End of name I2CxST Macro Definition */ + +/** + * @name I2CxCR1 Macro Definition. + * @brief I2CxCR1 Register Macro Definition. + * @{ + */ +#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */ +#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */ +#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */ + +/** + * @} + */ /* End of name I2CxCR1 Macro Definition */ + +/** + * @name I2CxDBR Macro Definition. + * @brief I2CxDBR Register Macro Definition. + * @{ + */ +#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ +/** + * @} + */ /* End of name I2CxDBR Macro Definition */ + + +/** + * @name I2CxCR2 Macro Definition. + * @brief I2CxCR2 Register Macro Definition. + * @{ + */ +#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */ +#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */ +#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */ +#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */ +#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */ +#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */ +#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */ +#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */ + +/** + * @} + */ /* End of name I2CxCR2 Macro Definition */ + +/** + * @name I2CxSR Macro Definition. + * @brief I2CxSR Register Macro Definition. + * @{ + */ +#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */ +#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */ +#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */ +#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */ +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */ +#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */ +#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */ +/** + * @} + */ /* End of name I2CxSR Macro Definition */ + +/** + * @name I2CxPRS Macro Definition. + * @brief I2CxPRS Register Macro Definition. + * @{ + */ +#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */ +/** + * @} + */ /* End of name I2CxPRS Macro Definition */ + +/** + * @name I2CxIE Macro Definition. + * @brief I2CxIE Register Macro Definition. + * @{ + */ +#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */ +#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */ +#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */ +#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */ +#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */ + +/** + * @} + */ /* End of name I2CxIE Macro Definition */ + + +/** + * @name I2CxOP Macro Definition. + * @brief I2CxOP Register Macro Definition. + * @{ + */ +#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */ +#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */ +#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */ +#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */ +#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */ +#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */ +#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */ +#ifndef I2C_MULTI_MASTER +#define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */ +#else +#define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */ +#endif +#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */ +/** + * @} + */ /* End of name I2CxOP Macro Definition */ + +/** + * @name I2CxAR Macro Definition. + * @brief I2CxAR Register Macro Definition. + * @{ + */ +#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */ +#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ +#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ + +/** + * @} + */ /* End of name I2CxAR Macro Definition */ + + +/** + * @name I2CxPM Macro Definition. + * @brief I2CxPM Register Macro Definition. + * @{ + */ +#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ +/** + * @} + */ /* End of name I2CxPM Macro Definition */ + +/** + * @name I2CxWUPCR_INT Macro Definition. + * @brief I2CxWUPCR_INT Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ +#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ +/** + * @} + */ /* End of name I2CxWUPCR_INT Macro Definition */ + +/** + * @name I2CxWUPCR_RST Macro Definition. + * @brief I2CxWUPCR_RST Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ +#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ + + +/** + * @name I2CxWUPCR_ACK Macro Definition. + * @brief I2CxWUPCR_ACK Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ +#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sck; /*!< Select internal SCL output clock frequency. */ + uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */ +} I2C_clock_setting_t; + +/*----------------------------------*/ +/** + * @brief Wakeup Control setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sgcdi; /*!< Select general call detect ON/OFF. */ + uint32_t ack; /*!< Select ACK output. */ + uint32_t reset; /*!< I2C BUS Rest. */ + uint32_t intend; /*!< Interrupt release. */ +} I2CS_wup_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_clock_setting_t clock; /*!< Serial clock setting. */ +} I2C_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */ +} I2CS_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */ + I2C_initial_setting_t init; /*!< Initial setting. */ +} I2C_t; +#if defined(I2CSxWUP_EN) +/*----------------------------------*/ +/** + * @brief I2CS handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */ + I2CS_initial_setting_t init; /*!< Initial setting. */ +} I2CS_t; +#endif +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj); +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj); +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj); +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data); +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack); +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx); +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr); +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj); + +/*--------------------------------------------------*/ +/** + * @brief I2C software reset. + * @param p_obj :I2C object. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief I2C bus port high + * @param p_obj :I2C object. + * @retval true :SDA and SCL Port High. + * @retval false :Bus Error. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); + } + return (0); +#else + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Generate stop condition. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Read from Data buffer + * @param p_obj :I2C object. + * @retval result :Read data. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); + } + return (0); +#else + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Write to Data buffer. + * @param p_obj :I2C object. + * @param data :Write data. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + } +#else + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return restart condition + * @param p_obj :I2C object. + * @retval true :Restart Detected. + * @retval false :Restart Non-Detected. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); + } + return (0); +#else + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set Ack condition + * @param p_obj :I2C object. + * @param nack :1 NACK, 0 ACK. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } + } +#else + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return received Ack condition + * @param p_obj :I2C object. + * @retval true :NACK Received. + * @retval false :ACK Received. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return Busy condition + * @param p_obj :I2C object. + * @retval true :I2C bus busy. + * @retval false :I2C bus free. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Master status + * @param p_obj :I2C object. + * @retval true :Master mode. + * @retval false :Slave mode. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Transmitter + * @param p_obj :I2C object. + * @retval true :Transmitter. + * @retval false :Receiver. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status + * @param p_obj :I2C object. + * @retval true :Interrupt Occurred. + * @retval false :No Interrupt Occurred. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); + } + return (0); +#else + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status Clear + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->ST = I2CxST_CLEAR; + } +#else + p_obj->p_instance->ST = I2CxST_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_I2C; + } +#else + p_obj->p_instance->IE = I2CxIE_I2C; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @param tx :Direction of transfer(1=tx 0=rx). + * @retval - + * @note For DMA transfer. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } + } +#else + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_CLEAR; + } +#else + p_obj->p_instance->IE = I2CxIE_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set slave address. + * @param p_obj :I2C object. + * @param addr :slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; + } +#else + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Detecting Slave Address + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj) +{ +#ifdef __DEBUG__ + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); + } + return (0); +#else + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); +#endif +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +void I2C_init(I2C_t *p_obj); +void I2C_start_condition(I2C_t *p_obj, uint32_t data); +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting); +void I2C_slave_init(I2C_t *p_obj); +#if defined(I2CSxWUP_EN) +void I2CS_init(I2CS_t *p_obj); +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_i2c_api.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_i2c_api.h new file mode 100644 index 0000000..2a8dcdb --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_i2c_api.h @@ -0,0 +1,321 @@ +/** + ******************************************************************************* + * @file i2c_api.h + * @brief This file provides all the functions prototypes for I2C Driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __BSP_I2C_H +#define __BSP_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ +/** + * @defgroup I2C_NullPointer Null Pointer + * @brief I2C NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of group I2C_NullPointer */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/** + * @defgroup I2C_ACK I2C ACK Macros + * @brief I2C Type of Acknowledge. + * @{ + */ +#define I2C_NACK (0) /*!< NACK Received. */ +#define I2C_ACK (1) /*!< ACK Received. */ +/** + * @} + */ /* End of group I2C_ACK */ + + +/** + * @defgroup I2C_ERROR I2C ERROR Macros + * @brief I2C Error definitions. + * @{ + */ +#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */ +#if 0 +#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */ +#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */ +#endif +#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */ +#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */ +#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */ +/** + * @} + */ /* End of group I2C_ERROR */ + + +/** + * @defgroup I2C_Events I2C Events Macros + * @brief I2C Asynch Events. + * @{ + */ +#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */ +#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */ +#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */ +#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */ +#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) +/** + * @} + */ /* End of group I2C_Events */ + +/** + * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros + * @brief I2C Received Contents of Slave. + * @{ + */ +#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */ +#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */ +#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */ +#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */ +/** + * @} + */ /* End of group I2C_SlaveReceive */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/*----------------------------------*/ +/** + * @brief i2c Port Enumerated Type Definition. +*/ +/*----------------------------------*/ +typedef enum { + I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */ + I2C_PORT_PG3, /*!< 1: PG3 I2C0 */ + I2C_PORT_PF2, /*!< 2: PF2 I2C1 */ + I2C_PORT_PF3, /*!< 3: PF3 I2C1 */ + I2C_PORT_PG4, /*!< 4: PG4 I2C2 */ + I2C_PORT_PG5, /*!< 5: PG5 I2C2 */ + I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */ + I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */ + I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */ + I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */ +} +i2c_port_t; + +/*----------------------*/ +/* I2C Setting */ +/*----------------------*/ +/* #define I2C_CHANNEL0 */ +#define I2C_CHANNEL3 +/* #define I2C_CHANNEL2 */ +/* #define I2C_CHANNEL3 */ +/* #define I2C_CHANNEL4 */ +#if defined(I2C_CHANNEL0) +#define I2Cx_TEXT "I2C0" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL1) +#define I2Cx_TEXT "I2C1" +#define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL2) +#define I2Cx_TEXT "I2C2" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL3) +#define I2Cx_TEXT "I2C3" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL4) +#define I2Cx_TEXT "I2C4" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */ +#else +#error "target channel is non-select." +#endif + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief I2C internal information structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t bus_free; /*!< Bus free information. */ + uint8_t start; /*!< Start condition information. */ + uint32_t irqn; /*!< IRQ number table pointer. */ + struct { + uint32_t address; /*!< Slave address. */ + uint32_t stop; /*!< Stop control */ + uint32_t event; /*!< I2C Event information. */ + uint32_t state; /*!< Transfer State. */ + } asynch; +} i2c_internal_info_t; + +/*----------------------------------*/ +/** + * @brief I2C buffer structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_buffer; /*!< Buffer address. */ + uint32_t length; /*!< Buffer length. */ + uint32_t pos; /*!< Buffer pointer. */ +} i2c_buffer_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_t i2c; /*!< I2C class structure. */ + i2c_internal_info_t info; /*!< Internal Information. */ + i2c_buffer_t tx_buff; /*!< Tx buffer structure. */ + i2c_buffer_t rx_buff; /*!< Rx buffer structure. */ +} _i2c_t; + +/** + * @} + */ /* End of group UTILITIES_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl); +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz); +void i2c_reset_t(_i2c_t *p_obj); +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj); +TXZ_Result i2c_start_t(_i2c_t *p_obj); +TXZ_Result i2c_stop_t(_i2c_t *p_obj); +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last); +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data); +uint8_t i2c_active_t(_i2c_t *p_obj); +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop); +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_abort_asynch_t(_i2c_t *p_obj); +uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn); + +/* For slave */ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave); +int32_t i2c_slave_receive_t(_i2c_t *p_obj); +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address); +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length); +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_slave_abort_asynch_t(_i2c_t *p_obj); + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __BSP_I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_t32a.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_t32a.h new file mode 100644 index 0000000..d8ebb41 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_t32a.h @@ -0,0 +1,1013 @@ +/** + ******************************************************************************* + * @file txz_t32a.h + * @brief This file provides all the functions prototypes for T32A driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __T32A_H +#define __T32A_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup T32A T32A + * @brief T32A Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_define T32A Exported Define + * @{ + */ + +/** + * @defgroup T32A_Result Result + * @brief T32A Result Macro Definition. + * @{ + */ +#define T32A_RESULT_SUCCESS (0) /*!< Success */ +#define T32A_RESULT_FAILURE (-1) /*!< Failure */ +#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group T32A_Result */ + +/** + * @defgroup T32A_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */ +/** + * @} + */ /* End of group T32A_NullPointer */ + +/** +* @defgroup T32A_HALT T32A Debug HALT Control +* @brief Debug HALT Control Run/Stop HALT Macro Definition. +* @{ +*/ +#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */ +#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */ +/** + * @} + */ /* End of group T32A_HALT */ + +/** +* @defgroup T32A_MODE32 T32A 16bit/32bit MODE +* @brief T32A 16bit/32bit MODE MODE32 Macro Definition. +* @{ +*/ +#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */ +#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */ +/** + * @} + */ /* End of group T32A_MODE32 */ + +/** +* @defgroup T32A_RUNFLGx T32A RUNFLG Control +* @brief Run/Stop RUNFLGx Macro Definition. +* @{ +*/ +#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */ +#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */ +/** + * @} + */ /* End of group T32A_RUNFLGx */ + +/** + * @defgroup T32A_SFTSTPx T32A SW STOP Control + * @brief T32A SW STOPx SFTSTPx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */ +/** + * @} + */ /* End of group T32A_SFTSTPx */ + +/** + * @defgroup T32A_SFTSTAx T32A SW START Control + * @brief T32A SW STARTx SFTSTAx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */ +/** + * @} + */ /* End of group T32A_SFTSTAx */ + +/** + * @defgroup T32A_RUNx T32A RUN Disable/Enable Control + * @brief RUN Disable/Enable RUNx Macro Definition. + * @{ + */ +#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group T32A_RUNx */ + + +/** + * @defgroup T32A_PRSCLx T32A PRESCALER Control + * @brief PRESCALER Control PRSCLx Macro Definition. + * @{ + */ +#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */ +#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */ +#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */ +#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */ +#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */ +#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */ +#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */ +/** + * @} + */ /* End of group T32A_PRSCLx */ + +/** + * @defgroup T32A_CLKx T32A COLCK Control + * @brief CLOCK Control CLKA Macro Definition. + * @{ + */ +#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */ +#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */ +#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */ +#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */ +#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */ +#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */ +/** + * @} + */ /* End of group T32A_CLKx */ + +/** + * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control + * @brief Double Buffer Disable/Enable WBFx Macro Definition. + * @{ + */ +#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */ +/** + * @} + */ /* End of group T32A_WBFx */ + +/** +* @defgroup T32A_UPDNx T32A Counter Up/Down Control +* @brief Counter Up/Down Control UPDNx Macro Definition. +* @{ +*/ +#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */ +#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */ +#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */ +#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */ +/** + * @} + */ /* End of group T32A_UPDNx */ + +/** +* @defgroup T32A_RELDx T32A Counter Reload Control +* @brief Counter Reload Control RELDx Macro Definition. +* @{ +*/ +#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */ +#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */ +#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */ +#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */ +#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */ +#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */ +#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */ +#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */ +/** + * @} + */ /* End of group T32A_RELDx */ + +/** +* @defgroup T32A_STOPx T32A Counter Stop Control +* @brief Counter Stop Control STOPx Macro Definition. +* @{ +*/ +#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */ +#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */ +#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */ +#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */ +#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */ +#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */ +/** + * @} + */ /* End of group T32A_STOPx */ + + +/** +* @defgroup T32A_STARTx T32A Counter Start Control +* @brief Counter Start Control STARTx Macro Definition. +* @{ +*/ +#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */ +#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */ +#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */ +#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */ +#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */ +#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */ +/** + * @} + */ /* End of group T32A_STARTx */ + +/** + * @defgroup T32A_OCRx T32AxOUTA Control + * @brief T32AxOUTA Control OCRx Macro Definition. + * @{ + */ +#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRx */ + +/** + * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 + * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */ +#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */ +#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx1 */ + +/** + * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value + * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */ +#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */ +#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx0 */ + +/** + * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value + * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */ +#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */ +#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx1 */ + +/** + * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value + * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx0 */ + +/** + * @defgroup T32A_RGx0 T32A Timer Register x0 MASK + * @brief T32A Timer Register A0 MASK RGx0 Macro Definition. + * @{ + */ +#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_RGx1 T32A Timer Register x1 MASK + * @brief T32A Timer Register A1 MASK RGx1 Macro Definition. + * @{ + */ +#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_TMRx T32A Counter Capture Register x MASK + * @brief T32A Counter Capture Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_TMRx */ + +/** + * @defgroup T32A_RELD T32A Counter Reload Register x MASK + * @brief T32A Counter Reload Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RELD */ + +/** +* @defgroup T32A_CAPMx1 T32A Capture Control Register x1 +* @brief Capture Control Register A1 CAPMx1 Macro Definition. +* @{ +*/ +#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */ +#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */ +#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */ +#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */ +#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */ +#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx1 */ + +/** +* @defgroup T32A_CAPMx0 T32A Capture Control Register x0 +* @brief Capture Control Register x0 CAPMx0 Macro Definition. +* @{ +*/ +#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */ +#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */ +#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */ +#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */ +#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */ +#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx0 */ + +/** + * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK + * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition. + * @{ + */ +#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx0 */ + +/** + * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK + * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition. + * @{ + */ +#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx1 */ + +/** + * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK + * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition. + * @{ + */ +#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) +#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_IMSTERR */ + +/** + * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK + * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition. + * @{ + */ +#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */ +/** + * @} + */ /* End of group T32A_IMUFx */ + +/** + * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK + * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition. + * @{ + */ +#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */ +/** + * @} + */ /* End of group T32A_IMOFx */ + +/** + * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition. + * @{ + */ +#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx1 */ + +/** + * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition. + * @{ + */ +#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx0 */ + +/** + * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status + * @brief T32A Statuserr Flag Status INTSTERR Macro Definition. + * @{ + */ +#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) +#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_INTSTERR */ + +/** + * @defgroup T32A_INTUFA T32A Underflow Flag Status + * @brief T32A Underflow Flag Status INTUFA Macro Definition. + * @{ + */ +#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */ +#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTUFA */ + +/** + * @defgroup T32A_INTOFA T32A Overflow Flag Status + * @brief T32A Overflow Flag Status INTOFA Macro Definition. + * @{ + */ +#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */ +#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTOFA */ + +/** + * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status + * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition. + * @{ + */ +#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */ +#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA1 */ + +/** + * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status + * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition. + * @{ + */ +#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */ +#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA0 */ + +/** + * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control + * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition. + * @{ + */ +#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx2 */ + +/** + * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control + * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition. + * @{ + */ +#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx1 */ + +/** + * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control + * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition. + * @{ + */ +#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx0 */ + +/** +* @defgroup T32A_PDN T32A Pulse Mode Count Down Control +* @brief Pulse Mode Count Down Control PDN Macro Definition. +* @{ +*/ +#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */ +#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */ +#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */ +#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */ +#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */ +#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */ +#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PDN */ + +/** +* @defgroup T32A_PUP T32A Pulse Mode Count UP Control +* @brief Pulse Mode Count UP Control PUP Macro Definition. +* @{ +*/ +#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */ +#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */ +#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */ +#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */ +#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */ +#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */ +#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PUP */ + +/** +* @defgroup T32A_NF T32A Noise Filter control +* @brief Noise Filter control NF Macro Definition. +* @{ +*/ +#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/phiT0 */ +#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/phiT0 */ +#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/phiT0 */ +/** + * @} + */ /* End of group T32A_NF */ + +/** + * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control + * @brief Phase 2 Pulse Direction control PDIR Macro Definition. + * @{ + */ +#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */ +#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */ +/** + * @} + */ /* End of group T32A_PDIR */ + +/** + * @defgroup T32A_PMODE T32A Pulse Count Mode control + * @brief Pulse Count Mode control PDIR Macro Definition. + * @{ + */ +#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */ +#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */ +/** + * @} + */ /* End of group T32A_PMODE */ + +/** + * @} + */ /* End of group T32A_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ + +/** + * @enum t32_type_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_TIMERA = 0, /*!< 0: Timer A */ + T32A_TIMERB, /*!< 1: Timer B */ + T32A_TIMERC, /*!< 2: Timer C */ + T32A_TIMERMAX, +} t32_type_t; + +/** + * @enum t32_regnum_t + * @brief Use of Timer register number. + */ +typedef enum { + T32A_REG0 = 0, /*!< 0: Register 0 */ + T32A_REG1, /*!< 1: Register 1 */ + T32A_RELOAD, /*!< 2: Reload Register */ +} t32_regnum_t; +/** + * @enum t32_mode_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_MATCH = 0, /*!< 0: compare match detection 0 */ + T32A_OVERFLOW, /*!< 1: Overfloe detection */ + T32A_UNDERFLOW, /*!< 2: Underflow detection */ + T32A_CAPTURE0, /*!< 3: Capture 0 */ + T32A_CAPTURE1, /*!< 4: Capture 0 */ +} t32_mode_t; + +/** + * @enum t32_triger_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_INTRG = 0, /*!< 0: internal triger */ + T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */ + T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */ + T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */ + T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */ +} t32_triger_t; +/** + * @} + */ /* End of group T32A_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct t32a_mode_t + * @brief TimerA Mode Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t halt; /*!< T32A Debug HALT Control. + : Use @ref T32A_HALT */ + uint32_t mode; /*!< T32A 16bit/32bit MODE . + : Use @ref T32A_MODE32 */ +} t32a_mode_t; + +/*----------------------------------*/ +/** + * @struct t32a_runx_t + * @brief TimerA Run Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t runflg; /*!< TimerA Run Control Flag. + : Use @ref T32A_RUNFLGx */ + uint32_t sftstp; /*!< SW Counter STOP Control. + : Use @ref T32A_SFTSTPx */ + uint32_t sftsta; /*!< SW Counter START Control. + : Use @ref T32A_SFTSTAx */ + uint32_t run; /*!< TimerA Run Control. + : Use @ref T32A_RUNx */ +} t32a_runx_t; + +/*----------------------------------*/ +/** + * @struct t32a_crx_t + * @brief Counter Register Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prscl; /*!< T32A PRESCALER Control. + : Use @ref T32A_PRSCLx */ + uint32_t clk; /*!< T32A COLCK Control. + : Use @ref T32A_CLKx */ + uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control. + : Use @ref T32A_WBFx */ + uint32_t updn; /*!< T32A Counter Up/Down Control. + : Use @ref T32A_UPDNx */ + uint32_t reld; /*!< T32A Counter Reload Control. + : Use @ref T32A_RELDx */ + uint32_t stop; /*!< T32A Counter Stop Control. + : Use @ref T32A_STOPx */ + uint32_t start; /*!< T32A Counter Start Controlc. + : Use @ref T32A_STARTx */ +} t32a_crx_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx0_t + * @brief TimerA Output Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocr; /*!< T32AxOUTA Control. + : Use @ref T32A_OCRx */ +} t32a_outcrx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx1_t + * @brief T32AxOUTA Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1. + : Use @ref T32A_OCRCAPx1 */ + uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1. + : Use @ref T32A_OCRCAPx0 */ + uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value + : Use @ref T32A_OCRCMPx1 */ + uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value + : Use @ref T32A_OCRCMPx0 */ +} t32a_outcrx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_capcrx_t + * @brief Capture Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capmx1; /*!< T32A Capture Control Register x1. + : Use @ref T32A_CAPMx1 */ + uint32_t capmx0; /*!< T32A Capture Control Register A0. + : Use @ref T32A_CAPMx0 */ +} t32a_capcrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx0_t + * @brief T32A Timer Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx0; /*!< T32A Timer Register x0. + : Use @ref T32A_RGx0 */ +} t32a_rgx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx1_t + * @brief T32A Timer Register x1 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx1; /*!< T32A Timer Register x1. + : Use @ref T32A_RGx1 */ +} t32a_rgx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_tmrx_t + * @brief T32A Counter Capture Register A Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tmrx; /*!< T32A Counter Capture Register x. + : Use @ref T32A_TMRx */ +} t32a_tmrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_reldx_t + * @brief T32A Counter Reload Register Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reld; /*!< T32A Counter Reload Register. + : Use @ref T32A_RELD */ +} t32a_reldx_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx0_t + * @brief T32A Capture Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx0; /*!< T32A Capture Register x0. + : Use @ref T32A_CAPx0 */ +} t32a_capx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx1_t + * @brief T32A Capture Register x0 Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx1; /*!< T32A Capture Register x1. + : Use @ref T32A_CAPx1 */ +} t32a_capx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_imx_t + * @brief Interrupt mask register Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C). + : Use @ref T32A_IMSTERR */ + uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMUFx */ + uint32_t imof; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMOFx */ + uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK. + : Use @ref T32A_IMx1 */ + uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK. + : Use @ref T32A_IMx0 */ +} t32a_imx_t; + +/*----------------------------------*/ +/** + * @struct t32a_stx_t + * @brief Status register structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C). + : Use @ref T32A_INTSTERR */ + uint32_t intuf; /*!< T32A Underflow Flag Status. + : Use @ref T32A_INTUFA */ + uint32_t intof; /*!< T32A Overflow Flag Status. + : Use @ref T32A_INTOFA */ + uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status. + : Use @ref T32A_INTA1 */ + uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status. + : Use @ref T32A_INTA0 */ +} t32a_stx_t; + +/*----------------------------------*/ +/** + * @struct t32a_dma_req_t + * @brief DMA Request register setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control. + : Use @ref T32A_DMAENx2 */ + uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control. + : Use @ref T32A_DMAENx1 */ + uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control. + : Use @ref T32A_DMAENx0 */ +} t32a_dma_req_t; + +/*----------------------------------*/ +/** + * @struct t32a_pulse_cr_t + * @brief Pulse Count Control register setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t pdn; /*!< Pulse Mode Count Down Control. + : Use @ref T32A_PDN */ + uint32_t pup; /*!< Pulse Mode Count UP Control. + : Use @ref T32A_PUP */ + uint32_t nf; /*!< Noise Filter control. + : Use @ref T32A_NF */ + uint32_t pdir; /*!< Phase 2 Pulse Direction control. + : Use @ref T32A_PDIR */ + uint32_t pmode; /*!< Pulse Count Mode control. + : Use @ref T32A_PMODE */ +} t32a_pulse_cr_t; + +/** + * @struct t32a_initial_setting_t + * @brief Initial Timer setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + t32a_runx_t runx; /*!< Timer Run Control Setting */ + t32a_crx_t crx; /*!< Counter Register Control Setting */ + t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */ + t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */ + t32a_capcrx_t capcrx; /*!< Capture Control Setting */ + t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */ + t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */ + t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */ + t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */ + t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */ + t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */ + t32a_imx_t imx; /*!< Interrupt mask register Setting */ + t32a_dma_req_t dma_req; /*!< DMA Request register Setting */ + t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */ + void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */ + void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */ + void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */ +} t32a_initial_setting_t; + +/** + * @struct t32a_initial_mode_t + * @brief Initial Mode setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + t32a_mode_t mode; /*!< Timer Mode Setting */ +} t32a_initial_mode_t; + + +/*----------------------------------*/ +/** + * @brief T32A handle structure definition. +*/ +/*----------------------------------*/ +typedef struct t32a_handle { + TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */ + t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */ + t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */ +} t32a_t; + +/** @} */ +/* End of group T32A_Exported_Types */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_functions T32A Exported Functions + * @{ + */ +TXZ_Result t32a_mode_init(t32a_t *p_obj); +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value); +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val); +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type); +void t32a_timer_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj); +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __T32A_H */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_tspi.h new file mode 100644 index 0000000..64ac70d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_tspi.h @@ -0,0 +1,1391 @@ +/** + ******************************************************************************* + * @file txz_tspi.h + * @brief This file provides all the functions prototypes for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __TSPI_H +#define __TSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup TSPI TSPI + * @brief TSPI Driver. + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_define TSPI Exported Define + * @{ + */ +/** + * @defgroup TSPI_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define TSPI_NULL ((void *)0) +/** + * @} + */ /* End of group TSPI_NullPointer */ + +/** + * @defgroup TSPI_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group TSPI_ParameterResult */ + + +/** + * @defgroup TSPI_Result Result + * @brief TSPI Result Macro Definition. + * @{ + */ +#define TSPI_RESULT_SUCCESS (0) /*!< Success */ +#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ +/** + * @} + */ /* End of group TSPI_Result */ + +/** + * @defgroup TSPI_SW_Reset SW Reset + * @brief Software Rest Macro Definition. + * @{ + */ +#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattern 10 */ +#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattern 01 */ +/** + * @} + */ /* End of group TSPI_SW_Reset */ + + +/** + * @defgroup TSPI_Enable TSPI Enable/Disable Control + * @brief Enable/Disable TSPIE Macro Definition. + * @{ + */ +#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Enable */ + +/** + * @defgroup TSPI_Infinity_Control Frame infinity Control + * @brief Frame infinity Enable/Disable Macro Definition. + * @{ + */ +#define TSPI_INF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_INF_ENABLE ((uint32_t)0x00010000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Infinity_Control */ + +/** + * @defgroup TSPI_Trigger_Control Trigger Control + * @brief Enable/Disable TRGEN Macro Definition. + * @{ + */ +#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Control Transmission Control + * @brief Enable/Disable TRXE Macro Definition. + * @{ + */ +#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ +#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Mode Transmission Mode + * @brief TSPIIMS Mode Macro Definition. + * @{ + */ +#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ +#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ +/** + * @} + */ /* End of group TSPI_Transmission_Mode */ + + +/** + * @defgroup TSPI_Operation_Select Operation Select + * @brief Master/Slave MSTR Operation Macro Definition. + * @{ + */ +#define TSPI_MASTER_OPERATION ((uint32_t)0x00001000) /*!< MASTER MODE */ +#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ +/** + * @} + */ /* End of group TSPI_Operation_Select */ + + +/** + * @defgroup TSPI_Transfer_Mode Transfer Mode + * @brief Transfer Mode TMMD Macro Definition. + * @{ + */ +#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ +#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ +#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ +#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ +/** + * @} + */ /* End of group TSPI_Transfer_Mode */ + + +/** + * @defgroup TSPI_CSSEL_Select CSSEL Select + * @brief TSPIIxCS0/1/2/3 Select Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ +#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ +#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ +#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ +/** + * @} + */ /* End of group TSPI_CSSEL_Select */ + +/** + * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range + * @brief Transfer Frame Range Macro Definition. + * @{ + */ +#define TSPI_TRANS_RANGE_CONTINUE ((uint32_t)0x00000000) /*!< Continue Transfer Frame :0 */ +#define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000001) /*!< Single Transfer Frame :1 */ +#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ +/** + * @} + */ /* End of group TSPI_Transfer_Frame_Range */ +/** + * @defgroup TSPI_IDLE_Output_value IDLE Output Value + * @brief IDLE time Output Value TIDLE Macro Definition. + * @{ + */ +#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ +#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ +#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ +#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_IDLE_Output_value */ + +/** + * @defgroup TSPI_RXDLY_value RXDLY Value + * @brief IDLE time Output Value TIDLE Macro Definition. + * @{ + */ +#define TSPI_RXDLY_1CLK ((uint32_t)0x00000000) /*!< RXDLY 1CLK */ +#define TSPI_RXDLY_2CLK ((uint32_t)0x00010000) /*!< RXDLY 2CLK */ +#define TSPI_RXDLY_3CLK ((uint32_t)0x00020000) /*!< RXDLY 3CLK */ +#define TSPI_RXDLY_4CLK ((uint32_t)0x00030000) /*!< RXDLY 4CLK */ +#define TSPI_RXDLY_5CLK ((uint32_t)0x00040000) /*!< RXDLY 5CLK */ +#define TSPI_RXDLY_6CLK ((uint32_t)0x00050000) /*!< RXDLY 6CLK */ +#define TSPI_RXDLY_7CLK ((uint32_t)0x00060000) /*!< RXDLY 7CLK */ +#define TSPI_RXDLY_8CLK ((uint32_t)0x00070000) /*!< RXDLY 8CLK */ +/** + * @} + */ /* End of group TSPI_RXDLY_value*/ + + +/** +* @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value +* @brief In case of Under Run Output Value TXDEMP Macro Definition. +* @{ +*/ +#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ +#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_Underrun_Output_value */ + + +/** + * @defgroup TSPI_TxFillLevel Tx Fill Level + * @brief Transmit Fill Level Macro Definition. + * @{ + */ +#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ +#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ +#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ +#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ +#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ +#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ +#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ +#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ +/*! + * @} + */ /* End of group TSPI_TxFillLevel */ + + +/** + * @defgroup TSPI_RxFillLevel Rx Fill Level + * @brief Receive Fill Level Macro Definition. + * @{ + */ +#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ +#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ +#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ +#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ +#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ +#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ +#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ +#define TSPI_RX_FILL_LEVEL_8 ((uint32_t)0x00000800) /*!< 8 */ +#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000F00) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RxFillLevel */ + + +/** + * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrupt + * @brief Enable/Disable Transmit FIFO Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterrupt */ + + +/** + * @defgroup TSPI_TxInterrupt Tx Interrupt + * @brief Enable/Disable Transmit Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxInterrupt */ + + +/** + * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrupt + * @brief Enable/Disable Receive FIFO Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterrupt */ + + +/** + * @defgroup TSPI_RxInterrupt Rx Interrupt + * @brief Enable/Disable Receive Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxInterrupt */ + + +/** + * @defgroup TSPI_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ErrorInterrupt */ + + +/** + * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt + * @brief Enable/Disable Transmit DMA Interrupt Macro Definition. + * @{ + */ +#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ +#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxDMAInterrupt */ + + +/** + * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt + * @brief Enable/Disable Receive DMA Interrupt Macro Definition. + * @{ + */ +#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ +#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxDMAInterrupt */ + + +/** + * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear + * @brief Tx Buffer Clear Macro Definition. + * @{ + */ +#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Tx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear + * @brief Rx Buffer Clear Macro Definition. + * @{ + */ +#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Rx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock + * @brief Baudrate Input Clock Macro Definition. + * @{ + */ +#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ +#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ +#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ +#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ +#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ +#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ +#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ +#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ +#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ +#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Clock */ + + +/** + * @defgroup TSPI_Baudrate_Divider Baudrate Divider + * @brief Baudrate IDivider Macro Definition. + * @{ + */ +#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ +#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ +#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ +#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ +#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ +#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ +#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ +#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ +#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ +#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ +#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ +#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ +#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ +#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ +#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ +#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Divider */ + + +/** + * @defgroup TSPI_DataDirection Data Direction + * @brief Data Direction Macro Definition. + * @{ + */ +#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ +/*! + * @} + */ /* End of group TSPI_DataDirection */ + + +/** + * @defgroup TSPI_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ +#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ +#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ +#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ +#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ +#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ +#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ +#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ +#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ +#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ +#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ +#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ +#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ +#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ +#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ +#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ +#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ +#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ +#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ +#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ +#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ +#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ +#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ +#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ +#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ +#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ +/** + * @} + */ /* End of group TSPI_DataLength */ + + +/** + * @defgroup TSPI_Frame_Interval_Time Frame Interval time + * @brief Frame Interval time Macro Definition. + * @{ + */ +#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Frame_Interval_Time */ + + +/** + * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity + * @brief TSPIxCS3 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS3_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity + * @brief TSPIxCS2 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS2_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity + * @brief TSPIxCS1 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS1_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity + * @brief TSPIxCS0 Polarity Macro Definition. + * @{ + */ +#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS0_Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity + * @brief Serial Clock Polarity Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ +#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ +/** + * @} + */ /* End of group Serial Clock Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity + * @brief Serial Clock IDLE Polarity Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ +#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ + + +/** + * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time + * @brief Minimum IDLE Time Macro Definition. + * @{ + */ +#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Minimum_IDLE_Time */ + + +/** + * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay + * @brief Serial Clock Delay Macro Definition. + * @{ + */ +#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_Delay */ + + +/** + * @defgroup TSPI_Negate_Delay Negate Delay + * @brief Negate Delay Macro Definition. + * @{ + */ +#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ +#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ +#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ +#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ +#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ +#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ +#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ +#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ +#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ +#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ +#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ +#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ +#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ +#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ +#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Negate_Delay */ + + +/** + * @defgroup TSPI_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ParityEnable */ + + +/** + * @defgroup TSPI_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ +/** + * @} + */ /* End of group TSPI_ParityBit */ + + +/** + * @defgroup TSPI_SECT_MODE Sect mode setting + * @brief Sect mode Macro Definition. + * @{ + */ +#define TSPI_SECT_MODE_FRAME ((uint32_t)0x00000000) /*!< Frame Mode */ +#define TSPI_SECT_MODE_SECT ((uint32_t)0x00000001) /*!< Sect Mode */ +/** + * @} + */ /* End of group TSPI_SECT_MODE */ + + +/** + * @defgroup TSPI_SECT_VALUE Sect bit length setting + * @brief Sect bit length Macro Definition. + * @{ + */ +#define TSPI_SECT_VALUE_0 ((uint32_t)0x00000000) /*!< length:0 */ +#define TSPI_SECT_VALUE_1 ((uint32_t)0x00000001) /*!< length:1 */ +#define TSPI_SECT_VALUE_MAX ((uint32_t)0x00000020) /*!< MAX:32 */ +/** + * @} + */ /* End of group TSPI_SECT_VALUE */ + +/** + * @defgroup TSPI_Status_Setting_flag Status Setting Flag + * @brief Enable/Disable Status Setting Flag Macro Definition. + * @{ + */ +#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group TSPI_Status_Setting_flag */ + + +/** + * @defgroup TSPI_TxState Transmitting State Flag + * @brief Transmitting State Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ +#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_TxState */ + + +/** + * @defgroup TSPI_TxDone Transmitting Complete Flag + * @brief Transmitting Complete Flag Macro Definition. + * @{ + */ +#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ +#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ +#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxDone */ + + +/** + * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrupt Flag + * @brief Transmitting FIFO Interrupt Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ +#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag + * @brief Transmitting FIFO Empty Flag Macro Definition. + * @{ + */ +#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_TxFIFOEmptyFlag */ + +/** + * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level + * @brief Current Transmitting FIFO Level Macro Definition. + * @{ + */ +#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ +#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ +#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ +#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ +#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ +#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ +#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ +#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_TxReachFillLevel */ + + +/** + * @defgroup TSPI_RxState Receive State Flag + * @brief Receive State Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ +#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_RxState */ + + +/** + * @defgroup TSPI_RxDone Receive Complete Flag + * @brief Receive Complete Flag Macro Definition. + * @{ + */ +#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ +#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ +#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxDone */ + + +/** + * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrupt Flag + * @brief Rx FIFO Interrupt Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ +#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag + * @brief Receiving FIFO Full Flag Macro Definition. + * @{ + */ +#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_RxFIFOFullFlag */ + + +/** + * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level + * @brief Current Receive FIFO Level Macro Definition. + * @{ + */ +#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ +#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ +#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ +#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ +#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ +#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ +#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ +#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_RxReachFillLevel */ + + +/** + * @defgroup TSPI_TRGErr Trigger Error + * @brief Trigger Error Macro Definition. + * @{ + */ +#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ +#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_TRGErr */ + +/** + * @defgroup TSPI_UnderrunErr Underrun Error + * @brief Underrun Error Macro Definition. + * @{ + */ +#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ +#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_UnderrunErr */ + +/** + * @defgroup TSPI_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ +#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_OverrunErr */ + + +/** + * @defgroup TSPI_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ +#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_ParityErr */ + +/** +* @defgroup TSPI_Data_allign Data allign +* @brief Data allign Macro Definition. +* @{ +*/ +#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ +#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ +#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ +/** + * @} + */ /* End of group TSPI_Data_allign */ + +/** +* @defgroup TSPI_FifoMax FIFO MAX +* @brief FIFO MAX LEVEL +* @{ +*/ +#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ +/** + * @} + */ /* End of group TSPI_FifoMax */ + +/** +* @defgroup TSPI_ErrCode Error Code +* @brief Error Code Macro Definition. +* @{ +*/ +#define NOERROR ((uint32_t)0x00000000) /*!< no error */ +#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ +#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ +#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ +#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ +#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ +#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ +#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ +#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ +#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ +#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ +/** +* @} + */ /* End of group TSPI_ErrCode */ + +/** +* @defgroup TSPI_Buffer_Size Receive Buffer size +* @brief Error Code Macro Definition. +* @{ +*/ +#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ +/** +* @} + */ /* End of group TSPI_Buffer_Size */ +/** + * @} + */ /* End of group TSPI_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/* No define */ +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct tspi_receive8_t + * @brief Receive event information structure definition. + * @brief When data length definition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive8_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive16_t + * @brief Receive event information structure definition. + * @brief When data length definition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive16_t; + +/** + * @struct tspi_receive32_t + * @brief Receive event information structure definition. + * @brief When data length definition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive32_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive_t + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef union { + tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ + tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ + tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ +} tspi_receive_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit8_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit8_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit16_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit16_t; +/*----------------------------------*/ +/** + * @struct tspi_transmit32_t + * @brief Transmit data information structure definition. + * @brief When data length definition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit32_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit_t + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef union { + tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ + tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ + tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ +} tspi_transmit_t; + +/*----------------------------------*/ +/** + * @struct tspi_control1_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inf; /*!< INF Transmission Infinity Control. + : Use @ref TSPI_Infinity_Control */ + uint32_t trgen; /*!< TRGEN Transmission Trigger Control. + : Use @ref TSPI_Trigger_Control */ + uint32_t trxe; /*!< TRXE Transmission Control. + : Use @ref TSPI_Transmission_Control */ + uint32_t tspims; /*!< TSPI/SIO Transmission Mode. + : Use @ref TSPI_Transmission_Mode */ + uint32_t mstr; /*!< Master/Slave Operation Select. + : Use @ref TSPI_Operation_Select */ + uint32_t tmmd; /*!< Transfer Mode Select. + : Use @ref TSPI_Transfer_Mode */ + uint32_t cssel; /*!< CSSEL Select. + : Use @ref TSPI_CSSEL_Select */ + uint32_t fc; /*!< Transfer Frame Value. + : Range ( TSPI_TRANS_RANGE_CONTINUE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ +} tspi_control1_t; + +/*----------------------------------*/ +/** + * @struct tspi_control2_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tidle; /*!< IDLE Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t txdemp; /*!< Under Run Occur Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t rxdly; /*!< Fsys Select. + : Use @ref TSPI_RXDLY_value */ + uint32_t til; /*!< Transmit Fill Level. + : Use @ref TSPI_TxFillLevel */ + uint32_t ril; /*!< Receive Fill Level. + : Use @ref TSPI_RxFillLevel */ + uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. + : Use @ref TSPI_TxFIFOInterrupt */ + uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. + : Use @ref TSPI_TxInterrupt */ + uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. + : Use @ref TSPI_RxFIFOInterrupt */ + uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. + : Use @ref TSPI_RxInterrupt */ + uint32_t interr; /*!< Enable/Disable Error Interrupt. + : Use @ref TSPI_ErrorInterrupt */ + uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. + : Use @ref TSPI_TxDMAInterrupt */ + uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. + : Use @ref TSPI_RxDMAInterrupt */ +} tspi_control2_t; + +/*----------------------------------*/ +/** + * @struct tspi_control3_t + * @brief Control Setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tfempclr; /*!< Transmit Buffer Clear. + : Use @ref TSPI_Tx_Buffer_Clear */ + uint32_t rffllclr; /*!< Receive Buffer Clear. + : Use @ref TSPI_Rx_Buffer_Clear */ +} tspi_control3_t; + +/*----------------------------------*/ +/** + * @struct tspi_baudrate_t + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brck; /*!< Baudrate Input Clock. + : Use @ref TSPI_Baudrate_Clock */ + uint32_t brs; /*!< Baudrate Divider. + : Use @ref TSPI_Baudrate_Divider */ +} tspi_baudrate_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr0_t + * @brief Format control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dir; /*!< Data Direction. + : Use @ref TSPI_DataDirection */ + uint32_t fl; /*!< Data Length. + : Use @ref TSPI_DataLength */ + uint32_t fint; /*!< Frame Interval time. + : Use @ref TSPI_Frame_Interval_Time */ + uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS3_Polarity */ + uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS2_Polarity */ + uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS1_Polarity */ + uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS0_Polarity */ + uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. + : Use @ref TSPI_Serial_Clock_Polarity */ + uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. + : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ + uint32_t csint; /*!< Minimum IDLE Time. + : Use @ref TSPI_Minimum_IDLE_Time */ + uint32_t cssckdl; /*!< Serial Clock Delay. + : Use @ref TSPI_Serial_Clock_Delay */ + uint32_t sckcsdl; /*!< Negate Delay. + : Use @ref TSPI_Negate_Delay */ +} tspi_fmtr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr1_t + * @brief Format control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reserved; /*!< SIO Slave Mode. + : */ + uint32_t vpe; /*!< Enable/Disable Parity Function. + : Use @ref TSPI_ParityEnable */ + uint32_t vpm; /*!< Odd/Even Parity Bit. + : Use @ref TSPI_ParityBit */ +} tspi_fmtr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr0_t + * @brief Sect control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sect; /*!< Sect mode settings. + : Use @ref TSPI_SECT_MODE */ +} tspi_sectcr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr1_t + * @brief Sect control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sectl3; /*!< SECTL3 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl2; /*!< SECTL2 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl1; /*!< SECTL1 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ + uint32_t sectl0; /*!< SECTL0 Bit length setting. + : Use @ref TSPI_SECT_VALUE */ +} tspi_sectcr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_status_t + * @brief Status register. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. + : Use @ref TSPI_Status_Setting_flag */ + uint32_t txrun; /*!< Stop/Active Tx Active Flag. + : Use @ref TSPI_TxState */ + uint32_t txend; /*!< Tx Data Send Complete Flag. + : Use @ref TSPI_TxDone */ + uint32_t inttxwf; /*!< Tx FIFO Interrupt Flag. + : Use @ref TSPI_TxFIFOInterruptFlag */ + uint32_t tfemp; /*!< Tx FIFO Empty Flag. + : Use @ref TSPI_TxFIFOEmptyFlag */ + uint32_t tlvll; /*!< Tx Reach Fill Level + : Use @ref TSPI_TxReachFillLevel */ + uint32_t rxrun; /*!< Stop/Active Rx Active Flag. + : Use @ref TSPI_RxState */ + uint32_t rxend; /*!< Rx Data Receive Complete Flag. + : Use @ref TSPI_RxDone */ + uint32_t intrxff; /*!< Rx FIFO Interrupt Flag + : Use @ref TSPI_RxFIFOInterruptFlag */ + uint32_t rffll; /*!< Rx FIFO Full Flag + : Use @ref TSPI_RxFIFOFullFlag */ + uint32_t rlvl; /*!< Rx Reach Fill Level + : Use @ref TSPI_RxReachFillLevel */ +} tspi_status_t; + +/*----------------------------------*/ +/** + * @struct tspi_error_t + * @brief Error flag. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t udrerr; /*!< Underrun Error. + : Use @ref TSPI_UnderrunErr */ + uint32_t ovrerr; /*!< Overrun Error. + : Use @ref TSPI_OverrunErr */ + uint32_t perr; /*!< Parity Error. + : Use @ref TSPI_ParityErr */ +} tspi_error_t; + + +/*----------------------------------*/ +/** + * @struct tspi_initial_setting_t + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + tspi_control1_t cnt1; /*!< Control1 setting. + : Use @ref tspi_control1_t */ + tspi_control2_t cnt2; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_control3_t cnt3; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_baudrate_t brd; /*!< Baudrate setting. + : Use @ref tspi_baudrate_t */ + tspi_fmtr0_t fmr0; /*!< Format control0 setting. + : Use @ref tspi_fmtr0_t */ + tspi_fmtr1_t fmr1; /*!< Format control1 setting. + : Use @ref tspi_fmtr1_t */ + tspi_sectcr0_t scr0; /*!< Sect control0 setting. + : Use @ref tspi_sectcr0_t */ + tspi_sectcr1_t scr1; /*!< Sect control1 setting. + : Use @ref tspi_sectcr1_t */ +} tspi_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief TSPI handle structure definition. +*/ +/*----------------------------------*/ +typedef struct tspi_handle { + TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ + tspi_initial_setting_t init; /*!< Initial setting. */ + uint32_t errcode; /*!< ErrorCode */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + tspi_transmit_t info; /*!< Transmit Data Information. */ + uint8_t tx_allign; /*!< Transmit Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + tspi_receive_t info; /*!< Receive Data Information. */ + uint8_t rx_allign; /*!< Receive Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} tspi_t; +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_functions TSPI Exported Functions + * @{ + */ +TXZ_Result tspi_init(tspi_t *p_obj); +TXZ_Result tspi_deinit(tspi_t *p_obj); +TXZ_Result tspi_format(tspi_t *p_obj); +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); +TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info); +void tspi_irq_handler_transmit(tspi_t *p_obj); +void tspi_irq_handler_receive(tspi_t *p_obj); +void tspi_error_irq_handler(tspi_t *p_obj); +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); +TXZ_Result tspi_error_clear(tspi_t *p_obj); +TXZ_Result tspi_discard_transmit(tspi_t *p_obj); +TXZ_Result tspi_discard_receive(tspi_t *p_obj); +/** + * @} + */ /* End of group TSPI_Exported_functions */ +/** + * @} + */ /* End of group TSPI */ +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TSPI_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_uart.h new file mode 100644 index 0000000..fc4ca0d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_uart.h @@ -0,0 +1,810 @@ +/** + ******************************************************************************* + * @file txz_uart.h + * @brief This file provides all the functions prototypes for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_H +#define __UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup UART UART + * @brief UART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/** + * @defgroup UART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */ +#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup UART_HalfClockSelect Half Clock Select + * @brief Output Terminal Select + * @{ + */ +#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */ +#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */ +/** + * @} + */ /* End of group UART_HalfClockSelect */ + +/** + * @defgroup UART_HalfClockMode Half Clock Mode + * @brief Half Clock Mode Setting. + * @{ + */ +#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */ +#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */ +/** + * @} + */ /* End of group UART_HalfClockMode */ + +/** + * @defgroup UART_HalfClockCTR Half Clock Mode Control + * @brief Half Clock Control. + * @{ + */ +#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */ +#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */ +/** + * @} + */ /* End of group UART_HalfClockCTR */ + +/** + * @defgroup UART_LoopBack Loop Back Function + * @brief Half Clock Control. + * @{ + */ +#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */ +#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */ +/** + * @} + */ /* End of group UART_LoopBack */ + + +/** + * @defgroup UART_NoiseFilter Noise Filter + * @brief Noise Filter Setting. + * @{ + */ +#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */ +#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */ +/** + * @} + */ /* End of group UART_NoiseFilter */ + + +/** + * @defgroup UART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definition. + * @{ + */ +#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */ +/** + * @} + */ /* End of group UART_CTSHandshake */ + + +/** + * @defgroup UART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definition. + * @{ + */ +#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */ +/** + * @} + */ /* End of group UART_RTSHandshake */ + + +/** + * @defgroup UART_DataComplementation Data Complementation + * @brief Enable/Disable Data Signal Complementation Macro Definition. + * @{ + */ +#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group UART_DataComplementation */ + + +/** + * @defgroup UART_DataDirection Data Direction + * @brief Data Direction Macro Definition. + * @{ + */ +#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */ +/*! + * @} + */ /* End of group UART_DataDirection */ + + +/** + * @defgroup UART_StopBit Stop Bit + * @brief Stop Bit Macro Definition. + * @{ + */ +#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */ +/** + * @} + */ /* End of group UART_StopBit */ + + +/** + * @defgroup UART_ParityBit Parity Bit + * @brief Parity Bit Macro Definition. + * @{ + */ +#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */ +/** + * @} + */ /* End of group UART_ParityBit */ + + +/** + * @defgroup UART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definition. + * @{ + */ +#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ParityEnable */ + + +/** + * @defgroup UART_DataLength Data Length + * @brief Data Length Macro Definition. + * @{ + */ +#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */ +#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */ +#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */ +/** + * @} + */ /* End of group UART_DataLength */ + + +/** + * @defgroup UART_TxFillLevelRange Tx Fill Level Range + * @brief Transmit Fill Level Range Macro Definition. + * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */ +#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */ +/*! + * @} + */ /* End of group UART_TxFillLevelRange */ + + +/** + * @defgroup UART_RxFillLevelRange Rx Fill Level Range + * @brief Receive Fill Level Range Macro Definition. + * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */ +#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */ +/** + * @} + */ /* End of group UART_RxFillLevelRange */ + + +/** + * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrupt + * @brief Available Transmit FIFO Interrupt Macro Definition. + * @{ + */ +#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxFIFOInterrupt */ + + +/** + * @defgroup UART_TxInterrupt Tx Interrupt + * @brief Available Transmit Interrupt Macro Definition. + * @{ + */ +#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxInterrupt */ + + +/** + * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrupt + * @brief Available Receive FIFO Interrupt Macro Definition. + * @{ + */ +#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxFIFOInterrupt */ + + +/** + * @defgroup UART_RxInterrupt Rx Interrupt + * @brief Available Receive Interrupt Macro Definition. + * @{ + */ +#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxInterrupt */ + + +/** + * @defgroup UART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definition. + * @{ + */ +#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ErrorInterrupt */ + + +/** + * @defgroup UART_Prescaler Prescaler + * @brief Prescaler Macro Definition. + * @{ + */ +#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */ +#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */ +#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */ +#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */ +#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */ +#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */ +#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */ +#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */ +#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */ +/** + * @} + */ /* End of group UART_Prescaler */ + + +/** + * @defgroup UART_Clock_Mask Clock Mask + * @brief Clock Mask Macro Definition. + * @{ + */ +#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */ +/** + * @} + */ /* End of group UART_Clock_Mask */ + + +/** + * @defgroup UART_Division Division + * @brief Enable/Disable Division Macro Definition. + * @{ + */ +#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */ +/** + * @} + */ /* End of group UART_Division */ + + +/** + * @defgroup UART_RangeK Range K + * @brief Range of K Macro Definition. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)". + * @{ + */ +#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group UART_RangeK */ + + +/** + * @defgroup UART_RangeN Range N + * @brief Range of N Macro Definition. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)". + * @{ + */ +#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */ +#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group UART_RangeN */ + + +/** + * @defgroup UART_SettingEnable Setting Enable + * @brief Enable/Disable Setting Macro Definition. + * @{ + */ +#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */ +#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group UART_SettingEnable */ + + +/** + * @defgroup UART_TxState Tx State + * @brief Transmitting State Macro Definition. + * @{ + */ +#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */ +#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */ +/** + * @} + */ /* End of group UART_TxState */ + + +/** + * @defgroup UART_TxDone Transmitting Done + * @brief Transmitting Done Macro Definition. + * @{ + */ +#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */ +#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */ +/** + * @} + */ /* End of group UART_TxDone */ + + +/** + * @defgroup UART_TxReachFillLevel Tx Reach Fill Level + * @brief Reach Transmitting Fill Level Macro Definition. + * @{ + */ +#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */ +#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */ +/** + * @} + */ /* End of group UART_TxReachFillLevel */ + + +/** + * @defgroup UART_TxFifoLevel Tx FIFO Fill Level + * @brief Transmitting FIFO Fill Level Macro Definition. + * @{ + */ +#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */ +/** + * @} + */ /* End of group UART_TxFifoLevel */ + + +/** + * @defgroup UART_RxState Rx State + * @brief Receive State Macro Definition. + * @{ + */ +#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */ +#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */ +/** + * @} + */ /* End of group UART_RxState */ + + +/** + * @defgroup UART_RxDone Rx Done + * @brief Receive Done Macro Definition. + * @{ + */ +#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */ +#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */ +/** + * @} + */ /* End of group UART_RxDone */ + + +/** + * @defgroup UART_RxReachFillLevel Rx Reach Fill Level + * @brief Reach Receive Fill Level Macro Definition. + * @{ + */ +#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */ +#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */ +/** + * @} + */ /* End of group UART_RxReachFillLevel */ + + +/** + * @defgroup UART_RxFifoLevel Rx FIFO Fill Level + * @brief Receive FIFO Fill Level Macro Definition. + * @{ + */ +#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */ +/** + * @} + */ /* End of group UART_RxFifoLevel */ + + +/** + * @defgroup UART_TriggerErr Trigger Error + * @brief Trigger Error Macro Definition. + * @{ + */ +#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */ +/** + * @} + */ /* End of group UART_TxTriggerErr */ + + +/** + * @defgroup UART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definition. + * @{ + */ +#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group UART_OverrunErr */ + + +/** + * @defgroup UART_ParityErr Parity Error + * @brief Parity Error Macro Definition. + * @{ + */ +#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group UART_ParityErr */ + + +/** + * @defgroup UART_FramingErr Framing Error + * @brief Framing Error Macro Definition. + * @{ + */ +#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group UART_FramingErr */ + + +/** + * @defgroup UART_BreakErr Break Error + * @brief Break Error Macro Definition. + * @{ + */ +#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group UART_BreakErr */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_typedef UART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. + * @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this. + * @attention "num" must be over FIFO max num. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive8_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. + * @brief When data length definition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive16_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definition. +*/ +/*----------------------------------*/ +typedef union { + uart_receive8_t rx8; /*!< @ref uart_receive8_t */ + uart_receive16_t rx16; /*!< @ref uart_receive16_t */ +} uart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. + * @brief When data length definition is "7 or 8bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit8_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. + * @brief When data length definition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. + Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit16_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definition. +*/ +/*----------------------------------*/ +typedef union { + uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */ + uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */ +} uart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Clock setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prsel; /*!< Prescaler. + : Use @ref UART_Prescaler */ +} uart_clock_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ken; /*!< Enable/Disable Division Definition. + : Use @ref UART_Division */ + uint32_t brk; /*!< Division Value K. + : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */ +} uart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit FIFO Interrupt. + : Use @ref UART_TxFIFOInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */ +} uart_tx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive FIFO Interrupt. + : Use @ref UART_RxFIFOInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */ +} uart_rx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + uart_clock_t clock; /*!< Clock setting. + : Use @ref uart_clock_t */ + uart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref uart_boudrate_t */ + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref UART_TxInterrupt */ + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref UART_RxInterrupt */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref UART_ErrorInterrupt */ + uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting. + : Use @ref uart_tx_fifo_t */ + uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting. + : Use @ref uart_rx_fifo_t */ + uint32_t hct; /*!< Half Clock Terminal Select. + : Use @ref UART_HalfClockSelect */ + uint32_t hcm; /*!< Half Clock Mode Select. + : Use @ref UART_HalfClockMode */ + uint32_t hcc; /*!< Half Clock Control. + : Use @ref UART_HalfClockCTR */ + uint32_t lbc; /*!< Loop Back Control. + : Use @ref UART_LoopBack */ + uint32_t nf; /*!< UTxRXD Noise Filter. + : Use @ref UART_NoiseFilter */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref UART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref UART_RTSHandshake */ + uint32_t iv; /*!< Data Signal Complementation. + : Use @ref UART_DataComplementation */ + uint32_t dir; /*!< Data Direction. + : Use @ref UART_DataDirection */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref UART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref UART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref UART_ParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref UART_DataLength */ +} uart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief UART handle structure definition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_UART_TypeDef *p_instance; /*!< Registers base address. */ + uart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Information. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmitted data. */ + uart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Information. + */ + /*------------------------------------------*/ + struct { + uart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} uart_t; + +/** + * @} + */ /* End of group UART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_functions UART Exported Functions + * @{ + */ +TXZ_Result uart_init(uart_t *p_obj); +TXZ_Result uart_deinit(uart_t *p_obj); +TXZ_Result uart_discard_transmit(uart_t *p_obj); +TXZ_Result uart_discard_receive(uart_t *p_obj); +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info); +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info); +void uart_transmit_irq_handler(uart_t *p_obj); +void uart_receive_irq_handler(uart_t *p_obj); +void uart_error_irq_handler(uart_t *p_obj); +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status); +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error); +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting); +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_uart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_uart_include.h new file mode 100644 index 0000000..226b283 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/inc/txz_uart_include.h @@ -0,0 +1,484 @@ +/** + ******************************************************************************* + * @file txz_uart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_INCLUDE_H +#define __UART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/** + * @defgroup UART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define UART_NULL ((void *)0) +/** + * @} + */ /* End of group UART_NullPointer */ + +/** + * @defgroup UART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group UART_ParameterResult */ + +/** + * @defgroup UARTxSWRST UARTxSWRST Register + * @brief UARTxSWRST Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | SWRSTF | + * | 6:2 | - | + * | 1:0 | SWRST | + * @{ + */ +/* SWRSTF */ +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */ +#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */ +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */ +/* SWRST */ +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */ +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */ +/** + * @} + */ /* End of group UARTxSWRST */ + +/** + * @defgroup UARTxCR0 UARTxCR0 Register + * @brief UARTxCR0 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | HBSST | + * | 17 | HBSMD | + * | 16 | HBSEN | + * | 15 | LPB | + * | 14-12 | NF[2:0] | + * | 11 | - | + * | 10 | CTSE | + * | 9 | RTSE | + * | 8 | WU | + * | 7 | - | + * | 6 | IV | + * | 5 | DIR | + * | 4 | SBLEN | + * | 3 | EVEN | + * | 2 | PE | + * | 1-0 | SM[1:0] | + * @{ + */ +/* HBSST */ +#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */ +/* HBSMD */ +#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */ +/* HBSEN */ +#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */ +#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */ +#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */ +/* LPB */ +#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */ +#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */ +#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */ +/* WU */ +#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */ +#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */ +#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */ +/** + * @} + */ /* End of group UARTxCR0 */ + +/** + * @defgroup UARTxCR1 UARTxCR1 Register + * @brief UARTxCR1 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-15 | - | + * | 14-12 | TIL[2:0] | + * | 11 | - | + * | 10-8 | RIL[2:0] | + * | 7 | INTTXFE | + * | 6 | INTTXWE | + * | 5 | INTRXFE | + * | 4 | INTRXWE | + * | 3 | - | + * | 2 | INTERR | + * | 1 | DMATE | + * | 0 | DMARE | + * @{ + */ +/* RIL */ +#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */ +/* DMATE */ +#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */ +#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */ +#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */ +/* DMARE */ +#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */ +#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */ +#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */ +/** + * @} + */ /* End of group UARTxCR1 */ + +/** + * @defgroup UARTxTRANS UARTxTRANS Register + * @brief UARTxTRANS Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | BK | + * | 2 | TXTRG | + * | 1 | TXE | + * | 0 | RXE | + * @{ + */ +/* BK */ +#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */ +#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */ +#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */ +/* TXTRG */ +#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */ +#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */ +#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */ +/* TXE */ +#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */ +#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */ +#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */ +/* RXE */ +#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */ +#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */ +#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */ +/* TXE,RXE */ +#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */ +/** + * @} + */ /* End of group UARTxTRANS */ + +/** + * @defgroup UARTxDR UARTxDR Register + * @brief UARTxDR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | PERR | + * | 17 | FERR | + * | 16 | BERR | + * | 15:9 | - | + * | 8:0 | DR | + * @{ + */ +/* DR */ +#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */ +#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */ +/** + * @} + */ /* End of group UARTxDR */ + +/** + * @defgroup UARTxSR UARTxSR Register + * @brief UARTxSR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31 | SUE | + * | 30:16 | - | + * | 15 | TXRUN | + * | 14 | TXEND | + * | 13 | TXFF | + * | 12 | - | + * | 11:8 | TLVL | + * | 7 | RXRUN | + * | 6 | RXEND | + * | 5 | RXFF | + * | 4 | - | + * | 3:0 | RLVL | + * @{ + */ +/* SUE */ +#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */ +/* TXEND */ +#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */ +#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */ +#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */ +/* TXFF */ +#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */ +#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */ +#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */ +/* TLVL */ +#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */ +/* RXEND */ +#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */ +#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */ +#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */ +/* RXFF */ +#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */ +#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */ +#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */ +/* RLVL */ +#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */ +/** + * @} + */ /* End of group UARTxSR */ + +/** + * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register + * @brief UARTxFIFOCLR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | TFCLR | + * | 0 | RFCLR | + * @{ + */ +/* TFCLR */ +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */ +/* RFCLR */ +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */ +/** + * @} + */ /* End of group UARTxFIFOCLR */ + +/** + * @defgroup UARTxERR UARTxERR Register + * @brief UARTxERR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-5 | - | + * | 4 | TRGERR | + * | 3 | OVRERR | + * | 2 | PERR | + * | 1 | FERR | + * | 0 | BERR | + * @{ + */ +/* TRGERR */ +#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */ +#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */ +#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */ +#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */ +/* OVRERR */ +#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */ +#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */ +#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */ +#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */ +/* PERR */ +#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */ +#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */ +#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */ +#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */ +/* FERR */ +#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */ +#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */ +#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */ +#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */ +/* BERR */ +#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */ +#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */ +#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */ +#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */ +/** + * @} + */ /* End of group UARTxERR */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_functions + * @{ + */ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef __DEBUG__ + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; +#endif +} + + +/** + * @} + */ /* End of group UART_Private_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_adc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_adc.c new file mode 100644 index 0000000..af40828 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_adc.c @@ -0,0 +1,1067 @@ +/** + ******************************************************************************* + * @file txz_adc.c + * @brief This file provides API functions for ADC driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_adc_include.h" +#include "txz_adc_ch.h" +#include "txz_adc.h" + +#if defined(__ADC_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_macro ADC Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_Enumeration ADC Private Enumeration + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_Enumeration */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Variable Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_variable ADC Private Variable Definition + * @{ + */ +static adc_t *p_AdcObj; +/** + * @} + */ /* End of group ADC_Private_variable */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +static int32_t check_param_sampling_period0(adc_sampling_period0_t param); +static int32_t check_param_sampling_period1(adc_sampling_period1_t param); +static int32_t check_param_prescaler_output(adc_sclk_t param); +static int32_t check_param_interrupt(adc_int_t param); +static int32_t check_param_type(adc_conversion_t param); +static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max); +static void clear_ch_instance_info(adc_ch_t *p_ch); + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_sampling_period0(adc_sampling_period0_t param) + * @brief Check the Sampling Period's parameter. + * @param[in] param :Sampling Period's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_sampling_period0(adc_sampling_period0_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SAMPLING_PERIOD0_XN: + case ADC_SAMPLING_PERIOD0_X2N: + case ADC_SAMPLING_PERIOD0_X3N: + case ADC_SAMPLING_PERIOD0_X4N: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_sampling_period1(adc_sampling_period1_t param) + * @brief Check the Sampling Period's parameter. + * @param[in] param :Sampling Period's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SamplingPeriod"ADC_SAMPLING_PERIOD_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_sampling_period1(adc_sampling_period1_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SAMPLING_PERIOD1_XN: + case ADC_SAMPLING_PERIOD1_X2N: + case ADC_SAMPLING_PERIOD1_X3N: + case ADC_SAMPLING_PERIOD1_X4N: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_prescaler_output(adc_sclk_t param) + * @brief Check the AD Prescaler Output's parameter. + * @param[in] param :AD Prescaler Output's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_SCLK"ADC_SCLK_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_prescaler_output(adc_sclk_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_SCLK_2: + case ADC_SCLK_4: + case ADC_SCLK_8: + case ADC_SCLK_16: + case ADC_SCLK_3: + case ADC_SCLK_5: + case ADC_SCLK_6: + case ADC_SCLK_10: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_interrupt(adc_int_t param) + * @brief Check the Interrupt's parameter. + * @param[in] param :Interrupt's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_IntEnable"ADC_INT_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_interrupt(adc_int_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_INT_DISABLE: + case ADC_INT_ENABLE: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_type(adc_conversion_t param) + * @brief Check the Conversion Type's parameter. + * @param[in] param :Conversion Type's parameter + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note Macro definition is ADC_Conversion"ADC_CONVERSION_xxxx". + */ +/*--------------------------------------------------*/ +static int32_t check_param_type(adc_conversion_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_CONVERSION_DISABLE: + case ADC_CONVERSION_CNT: + case ADC_CONVERSION_SGL: + case ADC_CONVERSION_TRG: + case ADC_CONVERSION_HPTG: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) + * @brief Check the AIN Range's parameter. + * @param[in] ain :AIN Range's parameter + * @param[in] min :Range Min. + * @param[in] max :Range Max. + * @retval ADC_PARAM_OK :Success. + * @retval ADC_PARAM_NG :Failure. + * @note - + */ +/*--------------------------------------------------*/ +static int32_t check_param_ain(adc_ain_range_t ain, adc_ain_range_t min, adc_ain_range_t max) +{ + int32_t result = ADC_PARAM_NG; + + if (min == 0) { + if (ain <= max) { + result = ADC_PARAM_OK; + } + } else { + if ((min <= ain) && (ain <= max)) { + result = ADC_PARAM_OK; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn static void clear_ch_instance_info(adc_ch_t *p_ch) + * @brief Channel Instance Information Clear. + * @param[in] p_ch :Channel Instance Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +static void clear_ch_instance_info(adc_ch_t *p_ch) +{ + p_ch->p_tset = ADC_NULL; + p_ch->p_reg = ADC_NULL; + p_ch->init.type = ADC_CONVERSION_DISABLE; +} +/*--------------------------------------------------*/ +/*! + * @fn static void adc_compa_irq_handler( void ) + * @brief IRQ Handler for Compare_A done. + * @param - + * @retval - + * @note Call by Compare_A Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_compa_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->init.CMPxEN[0].handle != ADC_NULL)) { + p_AdcObj->init.CMPxEN[0].handle(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_compb_irq_handler( void ) + * @brief IRQ Handler for Compare_B done. + * @param - + * @retval - + * @note Call by Compare_B Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_compb_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->init.CMPxEN[1].handle != ADC_NULL)) { + p_AdcObj->init.CMPxEN[1].handle(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_single_irq_handler( void ) + * @brief IRQ Handler for single conversion done. + * @param - + * @retval - + * @note Call by Single Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_single_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.single != ADC_NULL)) { + p_AdcObj->handler.single(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_continuity_irq_handler( void ) + * @brief IRQ Handler for continuity conversion done. + * @param - + * @retval - + * @note Call by Continuity Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_continuity_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.continuity != ADC_NULL)) { + p_AdcObj->handler.continuity(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_trigger_irq_handler( void ) + * @brief IRQ Handler for trigger conversion done. + * @param - + * @retval - + * @note Call by Trigger Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_trigger_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.trigger != ADC_NULL)) { + p_AdcObj->handler.trigger(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/*--------------------------------------------------*/ +/*! + * @fn static void adc_highpriority_irq_handler( void ) + * @brief IRQ Handler for highpriority conversion done. + * @param - + * @retval - + * @note Call by HigPriority Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_highpriority_irq_handler(void) +{ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if ((p_AdcObj != ADC_NULL) && + (p_AdcObj->handler.highpriority != ADC_NULL)) { + p_AdcObj->handler.highpriority(p_AdcObj->init.id, TXZ_SUCCESS); + } +} + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_init(adc_t *p_obj) + * @brief Initialize the ADC object. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_init(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + /* Check the parameter. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if ((void *)(p_obj->p_instance) == (void *)0) { + result = TXZ_ERROR; + } + if (check_param_sampling_period0(p_obj->init.clk.exaz0) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_sampling_period1(p_obj->init.clk.exaz1) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (p_obj->init.clk.sampling_select > 0x0100000) { + result = TXZ_ERROR; + } + if (check_param_prescaler_output(p_obj->init.clk.vadcld) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (result == TXZ_SUCCESS) { + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + uint32_t i; + + for (i = 0; i < ADC_NUM_MAX; i++) { + clear_ch_instance_info(&p_obj->info.ch[i]); + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCLK ---*/ + p_obj->p_instance->CLK = ((uint32_t)p_obj->init.clk.exaz0 | (uint32_t)p_obj->init.clk.exaz1 | (uint32_t)p_obj->init.clk.vadcld); + /*--- ADxEXAZSEL ---*/ + p_obj->p_instance->EXAZSEL = (uint32_t)p_obj->init.clk.sampling_select; + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON); + /* wait 3us after set the MOD0 to 1 */ + wait(3); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->MOD1 = p_obj->init.mod1; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = p_obj->init.mod2; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_deinit(adc_t *p_obj) + * @brief Release the ADC object. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_deinit(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t i; + adc_ch_t *p_ch; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) { + clear_ch_instance_info(p_ch); + } + } + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCMPEN ---*/ + p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE); + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->MOD1 = ADC_MOD1_SCLK_3; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADC_MOD2_CLEAR; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) + * @brief ADC Channel Setting + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @param[in] p_setting :Channel Setting Source Address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_setting) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } + if (check_param_interrupt((adc_int_t)p_setting->interrupt) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_type((adc_conversion_t)p_setting->type) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (check_param_ain((adc_ain_range_t)p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX) == ADC_PARAM_NG) { + result = TXZ_ERROR; + } + if (result == TXZ_SUCCESS) { + /*------------------------------*/ + /* Channel Class Construct */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch); + p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch); + p_ch->init.interrupt = p_setting->interrupt; + p_ch->init.type = p_setting->type; + p_ch->init.ain = p_setting->ain; + result = adc_ch_init(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) + * @brief ADC Channel Clear + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_deinit(p_ch); + /* Init Variable */ + clear_ch_instance_info(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) + * @brief Initialize the ADC Compare register + * @param[in] p_obj :ADC object. + * @param[in] p_cmpx_t :Clock information structure. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_cmp_init(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_cmpx_t) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) { + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; + } + if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) { + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_ENABLE) { + p_obj->init.CMPxEN[0].CMPEN = p_cmpx_t->CMPEN; + p_obj->init.CMPxEN[0].CMPCNT = p_cmpx_t->CMPCNT; + p_obj->init.CMPxEN[0].CMPCond = p_cmpx_t->CMPCond; + p_obj->init.CMPxEN[0].CMPBigSml = p_cmpx_t->CMPBigSml; + p_obj->init.CMPxEN[0].StrReg = p_cmpx_t->StrReg; + p_obj->init.CMPxEN[0].ADComp = p_cmpx_t->ADComp; + p_obj->init.CMPxEN[0].handle = p_cmpx_t->handle; + p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; + p_obj->p_instance->CMPCR0 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; + p_obj->p_instance->CMP0 = p_cmpx_t->ADComp; + } else if (p_cmpx_t->CMPEN == ADCMP1EN_ENABLE) { + p_obj->init.CMPxEN[1].CMPEN = p_cmpx_t->CMPEN; + p_obj->init.CMPxEN[1].CMPCNT = p_cmpx_t->CMPCNT; + p_obj->init.CMPxEN[1].CMPCond = p_cmpx_t->CMPCond; + p_obj->init.CMPxEN[1].CMPBigSml = p_cmpx_t->CMPBigSml; + p_obj->init.CMPxEN[1].StrReg = p_cmpx_t->StrReg; + p_obj->init.CMPxEN[1].ADComp = p_cmpx_t->ADComp; + p_obj->init.CMPxEN[1].handle = p_cmpx_t->handle; + p_obj->p_instance->CMPEN |= p_cmpx_t->CMPEN; + p_obj->p_instance->CMPCR1 = p_cmpx_t->CMPCNT | p_cmpx_t->CMPCond | p_cmpx_t->CMPBigSml | p_cmpx_t->StrReg; + p_obj->p_instance->CMP1 = p_cmpx_t->ADComp; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) + * @brief Release the ADC Compare register + * @param[in] p_obj :ADC object. + * @param[in] p_cmpx_t :Clock information structure. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_cmp_deinit(adc_t *p_obj, adc_cmpx_t *p_cmpx_t) +{ + TXZ_Result result = TXZ_SUCCESS; + p_AdcObj = p_obj; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_cmpx_t) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + if (p_cmpx_t->CMPEN == ADCMP0EN_DISABLE) { + p_obj->init.CMPxEN[0].CMPEN = 0; + p_obj->init.CMPxEN[0].CMPCNT = 0; + p_obj->init.CMPxEN[0].CMPCond = 0; + p_obj->init.CMPxEN[0].CMPBigSml = 0; + p_obj->init.CMPxEN[0].StrReg = 0; + p_obj->init.CMPxEN[0].ADComp = 0; + p_obj->init.CMPxEN[0].handle = (void *)0; + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP0EN_ENABLE; + p_obj->p_instance->CMPCR0 = 0; + p_obj->p_instance->CMP0 = 0; + } else if (p_cmpx_t->CMPEN == ADCMP1EN_DISABLE) { + p_obj->init.CMPxEN[1].CMPEN = 0; + p_obj->init.CMPxEN[1].CMPCNT = 0; + p_obj->init.CMPxEN[1].CMPCond = 0; + p_obj->init.CMPxEN[1].CMPBigSml = 0; + p_obj->init.CMPxEN[1].StrReg = 0; + p_obj->init.CMPxEN[1].ADComp = 0; + p_obj->init.CMPxEN[1].handle = (void *)0; + p_obj->p_instance->CMPEN &= ~(uint32_t)ADCMP1EN_ENABLE; + p_obj->p_instance->CMPCR1 = 0; + p_obj->p_instance->CMP1 = 0; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) + * @brief Get AD value + * @param[in] p_obj :ADC object. + * @param[in] ch :Channel. Range is (value < ADC_NUM_MAX). + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_value) == (void *)0) || + (ch >= ADC_NUM_MAX)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Get Value */ + /*------------------------------*/ + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_get_value(p_ch, p_value); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_start(adc_t *p_obj) + * @brief Start Conversion. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_start(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Enable Conversion */ + /*------------------------------*/ + uint32_t i; + adc_ch_t *p_ch; + uint32_t cr0 = (ADxCR0_ADEN_ENABLE | ADxCR0_CNT_DISABLE); + uint32_t cr1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + switch (p_ch->init.type) { + case ADC_CONVERSION_CNT: + cr0 |= ADxCR0_CNT_ENABLE; + break; + case ADC_CONVERSION_SGL: + cr0 |= ADxCR0_SGL_ENABLE; + break; + case ADC_CONVERSION_TRG: + cr1 |= ADxCR1_TRGEN_ENABLE; + break; + case ADC_CONVERSION_HPTG: + cr1 |= ADxCR1_HPTRGEN_ENABLE; + break; + default: + /* no processing */ + break; + } + } + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = cr1; + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = cr0; + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_stop(adc_t *p_obj) + * @brief Stop Conversion. + * @param[in] p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_stop(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t i; + adc_ch_t *p_ch; + uint32_t value; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Disable Conversion */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Dummy Read */ + /*------------------------------*/ + /* Read is needed before the next convertion. */ + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) { + /* no processing */ + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) + * @brief Wait for single conversion to be completed + * @param[in] p_obj :ADC object. + * @param[in] timeout :Timeout(tick). + * @retval TXZ_DONE :Success. + * @retval TXZ_BUSY :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_WorkState adc_poll_conversion(adc_t *p_obj, uint32_t timeout) +{ + TXZ_WorkState result = TXZ_BUSY; + TXZ_WorkState loopBreak = TXZ_BUSY; + uint32_t base = hal_get_tick(); + uint32_t current = 0; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0)) { + result = TXZ_DONE; + } else { + /*------------------------------*/ + /* Check Status */ + /*------------------------------*/ + while (loopBreak == TXZ_BUSY) { + /*--- Check Status ---*/ + /* Read status. */ + status = p_obj->p_instance->ST; + /* Check status. */ + if ((status & ADxST_SNGF_MASK) == ADxST_SNGF_IDLE) { + result = TXZ_DONE; + loopBreak = TXZ_DONE; + } else { + /*--- Check Timeout ---*/ + if (timeout == 0) { + loopBreak = TXZ_DONE; + } else { + current = hal_get_tick(); + if (current > base) { + if ((current - base) >= timeout) { + loopBreak = TXZ_DONE; + } + } else { + base = current; + } + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @fn TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) + * @brief Get Conversion Status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-8 | - | - | + * | 7 | ADBF | AD Running Flag. Use @ref adc_status_t. | + * | 6-4 | - | - | + * | 3 | CNTF | Continuity Conversion Running Flag. Use @ref adc_cnt_status_t. | + * | 2 | SNGF | Single Conversion Running Flag. Use @ref adc_sgl_status_t. | + * | 1 | TRGF | Trigger Conversion Running Flag. Use @ref adc_trg_status_t. | + * | 0 | - | - | + * + * @param[in] p_obj :ADC object. + * @param[out] p_status :Conversion Status. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_get_status(adc_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((void *)(p_obj->p_instance) == (void *)0) || + ((void *)(p_status) == (void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Read Register */ + /*------------------------------*/ + *p_status = p_obj->p_instance->ST; + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_adc_ch.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_adc_ch.c new file mode 100644 index 0000000..34dbeb3 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_adc_ch.c @@ -0,0 +1,347 @@ +/** + ******************************************************************************* + * @file txz_adc_ch.c + * @brief This file provides API functions for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_adc_include.h" +#include "txz_adc_ch.h" + +#if defined(__ADC_CH_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +/* no define */ +#endif + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn static uint32_t get_conversion_data(uint32_t reg) + * @brief Get convertion data from ADxREGn. + * @param[in] reg :ADxREGn data. + * @retval Convertion data. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t get_conversion_data(uint32_t reg) +{ + uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4); + + return (result); +} +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_init(adc_ch_t *p_obj) + * @brief Initialize the ADC Channel object. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_init(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + /*--- ADxTSET ---*/ + *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain); + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) + * @brief Release the ADC Channel object. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0); + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) + * @brief Enable Interrupt. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) + * @brief Disable Interrupt. + * @param[in][out] p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if (((void *)(p_obj) == (void *)0) || + ((volatile void *)(p_obj->p_tset) == (volatile void *)0) || + ((const volatile void *)(p_obj->p_reg) == (const volatile void *)0)) { + result = TXZ_ERROR; + } else { + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) + * @brief Get conversion value. + * @param p_obj :ADC Channel object. + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has done. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + reg = *p_obj->p_reg; + /*------------------------------*/ + /* Check Result */ + /*------------------------------*/ + if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { + *p_value = get_conversion_data(reg); + result = TXZ_SUCCESS; + } + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_cg.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_cg.c new file mode 100644 index 0000000..1ee77bd --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_cg.c @@ -0,0 +1,498 @@ +/** + ******************************************************************************* + * @file txz_cg.c + * @brief This file provides API functions for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_cg.h" + +#if defined(__CG_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup CG + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */ + +#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */ +#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */ +#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */ +#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */ +#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */ + +#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */ +#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */ +#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */ +#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */ +#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */ + +#define CG_PRCK_MASK ((uint32_t)0x00000F00) /*!< CG PRCK mask */ + +#define CG_PRCK_1 ((uint32_t)0x00000000) /*!< CG phiT0 fc register value */ +#define CG_PRCK_2 ((uint32_t)0x00000100) /*!< CG phiT0 fc/2 register value */ +#define CG_PRCK_4 ((uint32_t)0x00000200) /*!< CG phiT0 fc/4 register value */ +#define CG_PRCK_8 ((uint32_t)0x00000300) /*!< CG phiT0 fc/8 register value */ +#define CG_PRCK_16 ((uint32_t)0x00000400) /*!< CG phiT0 fc/16 register value */ +#define CG_PRCK_32 ((uint32_t)0x00000500) /*!< CG phiT0 fc/32 register value */ +#define CG_PRCK_64 ((uint32_t)0x00000600) /*!< CG phiT0 fc/64 register value */ +#define CG_PRCK_128 ((uint32_t)0x00000700) /*!< CG phiT0 fc/128 register value */ +#define CG_PRCK_256 ((uint32_t)0x00000800) /*!< CG phiT0 fc/256 register value */ +#define CG_PRCK_512 ((uint32_t)0x00000900) /*!< CG phiT0 fc/512 register value */ + +#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */ + +#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG phiT0 fc register status */ +#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG phiT0 fc/2 register status */ +#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG phiT0 fc/4 register status */ +#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG phiT0 fc/8 register status */ +#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG phiT0 fc/16 register status */ +#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG phiT0 fc/32 register status */ +#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG phiT0 fc/64 register status */ +#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG phiT0 fc/128 register status */ +#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG phiT0 fc/256 register status */ +#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG phiT0 fc/512 register status */ + +#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG phiT0 fc division value */ +#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG phiT0 fc/2 division value */ +#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG phiT0 fc/4 division value */ +#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG phiT0 fc/8 division value */ +#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG phiT0 fc/16 division value */ +#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG phiT0 fc/32 division value */ +#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG phiT0 fc/64 division value */ +#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG phiT0 fc/128 division value */ +#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG phiT0 fc/256 division value */ +#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG phiT0 fc/512 division value */ + + +#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */ + +#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG phiT0 fc/PRCK value */ +#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG phiT0 fc/PRCK/2 value */ +#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG phiT0 fc/PRCK/4 value */ + +#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm phiT0 division value */ +#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm phiT0/2 division value */ +#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm phiT0/4 division value */ + +#define CG_IHOSC_DISABLE ((uint32_t)0x00000000) /*!< Internal high-speed oscillator disable */ +#define CG_IHOSC_ENABLE ((uint32_t)0x00000001) /*!< Internal high-speed oscillator enable */ + +#define CG_IHOSC1EN ((uint32_t)0x00000000) /*!< CG OSCCR bit0 */ + +#define CG_MCKSELGST_MASK ((uint32_t)0x00C00000) /*!< CG MCKSELGST mask */ +#define CG_MCKSELGST_1 ((uint32_t)0x00000000) /*!< CG fsysm fc/PRCK value */ +#define CG_MCKSELGST_2 ((uint32_t)0x00400000) /*!< CG fsysm fc/PRCK/2 value */ +#define CG_MCKSELGST_4 ((uint32_t)0x00800000) /*!< CG fsysm fc/PRCK/4 value */ + + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_typedef CG Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_fuctions CG Private Fuctions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_fsysm(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + switch (p_obj->p_instance->SYSCR & CG_MCKSELGST_MASK) { + case CG_MCKSELGST_1: /* fsysm -> fc/PRCK */ + result = SystemCoreClock / CG_FSYSM_1_DIV; + break; + case CG_MCKSELGST_2: /* fsysm -> fc/PRCK/2 */ + result = SystemCoreClock / CG_FSYSM_2_DIV; + break; + case CG_MCKSELGST_4: /* fsysm -> fc/PRCK/4 */ + result = SystemCoreClock / CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); + +} + +/*--------------------------------------------------*/ +/** + * @brief Update PrescalerClock according register values. + * @param p_obj :CG object. + * @retval PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_phyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* phiT0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* phiT0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* phiT0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* phiT0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* phiT0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* phiT0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* phiT0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* phiT0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* phiT0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* phiT0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_mphyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* phiT0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* phiT0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* phiT0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* phiT0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* phiT0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* phiT0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* phiT0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* phiT0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* phiT0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* phiT0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) { + case CG_MCKSELPST_1: /* phiT0 -> fc/PRCK */ + result /= CG_FSYSM_1_DIV; + break; + case CG_MCKSELPST_2: /* phiT0 -> fc/PRCK/2 */ + result /= CG_FSYSM_2_DIV; + break; + case CG_MCKSELPST_4: /* phiT0 -> fc/PRCK/4 */ + result /= CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Internal high-speed oscillator enable. + * @param p_obj :CG object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result cg_ihosc_enable(cg_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* Internal high-speed oscillator is enable. */ + (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Internal high-speed oscillator disable. + * @param p_obj :CG object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result cg_ihosc_disable(cg_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /* Internal high-speed oscillator is disable. */ + (*((__IO uint32_t *)BITBAND_PERI(&p_obj->p_instance->OSCCR, CG_IHOSC1EN))) = CG_IHOSC_DISABLE; + + return (result); +} +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__CG_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fc.c new file mode 100644 index 0000000..7c8302c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fc.c @@ -0,0 +1,695 @@ +/** + ******************************************************************************* + * @file flash512ud32_b.c + * @brief This file provides API functions for FLASH. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include +#include "txz_fc.h" +//#include "txz_sample_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @defgroup Flash_Userboot Flash_Userboot Sample Appli + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_macro Flash_Userboot Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ +#define FC_MAX_PAGES (uint8_t)(0x20) /*!< Maxmum pages */ +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ +#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */ +#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ +#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ +#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ + +/****************** Changed by TSIP *************************************/ +///* Area Selection All */ +#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) +#define FC_AREASEL_EXPECT_AREA1 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area1 */ +#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) //select Area 0 +#define FC_AREASEL_AREA1 (uint32_t)(0x00000070UL) /*!< RW, Selects area1 */ +#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0FF8UL) //mask Area 0 +#define FC_AREASEL_MASK_AREA1 (uint32_t)(0xFF8F0F8FUL) /*!< RW, Selects area1 */ +#define FC_AREASEL_WRITEA0_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode(area0) */ +#define FC_AREASEL_WRITEA1_MODE (uint32_t)(0x08000000UL) /*!< R, Write Mode(area1) */ +static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { + (0x5E000000UL), /*!< CODE FLASH Page0 */ + (0x5E001000UL), /*!< CODE FLASH Page1 */ + (0x5E002000UL), /*!< CODE FLASH Page2 */ + (0x5E003000UL), /*!< CODE FLASH Page3 */ + (0x5E004000UL), /*!< CODE FLASH Page4 */ + (0x5E005000UL), /*!< CODE FLASH Page5 */ + (0x5E006000UL), /*!< CODE FLASH Page6 */ + (0x5E007000UL), /*!< CODE FLASH Page7 */ + (0x5E008000UL), /*!< CODE FLASH Page8 */ + (0x5E009000UL), /*!< CODE FLASH Page9 */ + (0x5E00A000UL), /*!< CODE FLASH Page10 */ + (0x5E00B000UL), /*!< CODE FLASH Page11 */ + (0x5E00C000UL), /*!< CODE FLASH Page12 */ + (0x5E00D000UL), /*!< CODE FLASH Page13 */ + (0x5E00E000UL), /*!< CODE FLASH Page14 */ + (0x5E00F000UL), /*!< CODE FLASH Page15 */ + (0x5E010000UL), /*!< CODE FLASH Page16 */ + (0x5E011000UL), /*!< CODE FLASH Page17 */ + (0x5E012000UL), /*!< CODE FLASH Page18 */ + (0x5E013000UL), /*!< CODE FLASH Page19 */ + (0x5E014000UL), /*!< CODE FLASH Page20 */ + (0x5E015000UL), /*!< CODE FLASH Page21 */ + (0x5E016000UL), /*!< CODE FLASH Page22 */ + (0x5E017000UL), /*!< CODE FLASH Page23 */ + (0x5E018000UL), /*!< CODE FLASH Page24 */ + (0x5E019000UL), /*!< CODE FLASH Page25 */ + (0x5E01A000UL), /*!< CODE FLASH Page26 */ + (0x5E01B000UL), /*!< CODE FLASH Page27 */ + (0x5E01C000UL), /*!< CODE FLASH Page28 */ + (0x5E01D000UL), /*!< CODE FLASH Page29 */ + (0x5E01E000UL), /*!< CODE FLASH Page30 */ + (0x5E01F000UL) /*!< CODE FLASH Page31 */ +}; + +/** + * @} + */ /* End of group Flash_Userboot_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_define Flash_Userboot Private Define + * @{ + */ +/** + * @defgroup Flash_Userboot_Private_typedef Flash_Userboot Private Typedef + * @{ + */ + +/** + * @} + */ /* End of group Flash_Userboot_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_variables Flash_Userboot Private Variables + * @{ + */ +/** + * @} + */ /* End of group Flash_Userboot_Private_variables */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Private_fuctions Flash_Userboot Private Fuctions + * @{ + */ +__STATIC_INLINE TXZ_Result fc_enable_areasel0(void); +__STATIC_INLINE TXZ_Result fc_disable_areasel0(void); +__STATIC_INLINE TXZ_Result fc_enable_areasel1(void); +__STATIC_INLINE TXZ_Result fc_disable_areasel1(void); +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind); +static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size); + +/*--------------------------------------------------*/ +/** + * @brief Enables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_enable_areasel0(void) +{ + TXZ_Result retval = TXZ_ERROR; + + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + reg |= FC_AREASEL_AREA0; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the FCAREASEL register the SSF0 was set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA0_MODE) == FC_AREASEL_WRITEA0_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Disables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_disable_areasel0(void) +{ + TXZ_Result retval = TXZ_ERROR; + + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + reg |= FC_AREASEL_EXPECT_AREA0; + + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the SSF0 of the FCAREASEL register is not set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA0_MODE) != FC_AREASEL_WRITEA0_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + return (retval); +} +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_enable_areasel1(void) +{ + TXZ_Result retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1; + reg |= FC_AREASEL_AREA1; + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->AREASEL = reg; + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA1_MODE) == FC_AREASEL_WRITEA1_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + return (retval); +} +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +__STATIC_INLINE TXZ_Result fc_disable_areasel1(void) +{ + TXZ_Result retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA1; + reg |= FC_AREASEL_EXPECT_AREA1; + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->AREASEL = reg; + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITEA1_MODE) != FC_AREASEL_WRITEA1_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Writes data of the Flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval1; + uint32_t retval0; + volatile uint32_t *addr1; + volatile uint32_t *addr2; + volatile uint32_t *addr3; + uint32_t *source = (uint32_t *) src_address; + + addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + addr3 = (uint32_t *)((uint32_t)dst_address + FC_CODE_FLASH_ADDRESS_TOP); + /* Enables the AREA0. Write Mode. */ + retval0 = fc_enable_areasel0(); + retval1 = fc_enable_areasel1(); + + if ((retval0 == TXZ_SUCCESS) + && (retval1 == TXZ_SUCCESS)) { + uint32_t i; + + *addr1 = (0x000000AAUL); /* bus cycle 1 */ + *addr2 = (0x00000055UL); /* bus cycle 2 */ + *addr1 = (0x000000A0UL); /* bus cycle 3 */ + for (i = (0UL); i < size; i += (0x4UL)) { + *addr3 = *source; + source++; + } + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + }; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { + }; + } + + /* Disables the AREA0. Read Mode. */ + retval0 = fc_disable_areasel0(); + retval1 = fc_disable_areasel1(); +} + +/*--------------------------------------------------*/ +/** + * @brief Verifies data of the Flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + TXZ_Result retval = TXZ_ERROR; + int res = memcmp(src_address, dst_address, size); + if (res == 0) { + retval = TXZ_SUCCESS; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the flash ROM. + * @param uint32_t* flash_top_address : flash top address + * @param uint32_t* erase_top_address : erase top address + * @param fc_erase_kind_t kind : Chip, Area, Block, Page, etc. + * @return - + * @note This function erases specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +//TXZ_Result fc_erase_pages_flash(uint32_t* top_address, uint32_t* erase_top_address) +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind) +{ + TXZ_Result retval0; + + TXZ_Result retval1; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC2_ADDR); + + volatile uint32_t *addr3 = (uint32_t *) erase_top_address; + + /* Enables the AREA0. Write Mode. */ + retval0 = fc_enable_areasel0(); + retval1 = fc_enable_areasel1(); + + if ((retval0 == TXZ_SUCCESS) + && (retval1 == TXZ_SUCCESS)) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x00000080UL); + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr3 = kind; + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + }; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { + }; + } + + /* Disables the AREA0. Read Mode. */ + retval0 = fc_disable_areasel0(); + retval1 = fc_disable_areasel1(); +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the Flash ROM every 4bytes. + * @param uint32_t* : addrress + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +static TXZ_Result fc_blank_check(uint32_t *address, uint32_t size) +{ + TXZ_Result retval = TXZ_SUCCESS; + + uint32_t i; + + for (i = 0; i < (size / sizeof(uint32_t)); i++) { + uint32_t *addr = &address[i]; + if (*addr != FC_BRANK_VALUE) { + retval = TXZ_ERROR; + break; + } + } + + return (retval); +} + +/** + * @} + */ /* End of group Flash_Userboot_Private_fuctions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Userboot_Exported_functions Flash_Userboot Exported Functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Get the status of the flash auto operation. + * @param fc_sr0_t : status + * @return Result. + * @retval TXZ_BUSY : Busy. + * @retval TXZ_DONE : Done. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_WorkState fc_get_status(fc_sr0_t status) +{ + TXZ_WorkState retval = TXZ_BUSY; + uint32_t work32; + + /* Reads the FCSR0. Masks the other specfic status */ + work32 = TSB_FC->SR0 & (uint32_t)status; + + /* Confirms the specific status of the flash ROM */ + if (work32 == (uint32_t)status) { + retval = TXZ_DONE; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the code flash ROM. + * @param uint32_t* : src_address + * @param uint32_t* : dst_address + * @param uint32_t : size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the code Flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + TXZ_Result retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + + uint32_t i; + /* Checks the code Flash ROM status */ + for (i = 0; i < size; i += (uint32_t)(0x10UL)) { + /* Writes 16bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), (uint32_t *)((uint32_t)dst_address + i), (uint32_t)(0x10UL)); + } + + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, dst_address, size); + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the code flash ROM. + * @param first_page : The first page to erase + * @param num_of_pages : The number of pages to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +TXZ_Result fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages) +{ + TXZ_Result retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum pages. */ + if ((first_page + num_of_pages) <= FC_MAX_PAGES) { + uint8_t i; + for (i = 0; i < num_of_pages ; i++) { + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_code_flash_address[first_page + i], + FC_ERASE_KIND_PAGE); + } + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)fc_const_code_flash_address[first_page], FC_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the code Flash ROM of specified pages. + * @param first_page : The first page which checks a blank. + * @param last_page : The last page which checks a blank.. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_blank_check_page_code_flash(fc_code_flash_page_number_t first_page, fc_code_flash_page_number_t last_page) +{ + TXZ_Result retval; + + uint32_t *address = (uint32_t *)fc_const_code_flash_address[first_page]; + uint32_t size = ((uint32_t)(last_page - first_page + 1) * (uint32_t)FC_PAGE_SIZE); + + retval = fc_blank_check(address, size); + + return (retval); +} + +/*--------------------------------------------------*/ +/*************** written by TSIP ******************/ +/** + * @brief Erases the entire block of code Flash ROM of specified address. + * @param uint32_t *top_addr : top address of Flash ROM. + * @param uint32_t *blk_addr : start address of block to be erased. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +#if defined ( __ICCARM__ ) // IAR Compiler +__ramfunc +#endif +TXZ_Result fc_erase_block_code_flash(uint32_t *top_addr, uint32_t *blk_addr) +{ + TXZ_Result retval = TXZ_SUCCESS; + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, blk_addr, FC_ERASE_KIND_BLOCK); + /* Checks a blank of the specific block. */ + if (fc_blank_check(blk_addr, (uint32_t)0x8000) == TXZ_ERROR) { + retval = TXZ_ERROR; + } else { + // do nothing + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + + +/** + * @} + */ /* End of group Flash_Userboot_Exported_functions */ + +/** + * @} + */ /* End of group Flash_Userboot */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_flash.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_flash.c new file mode 100644 index 0000000..fe6b07c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_flash.c @@ -0,0 +1,230 @@ +/** + ******************************************************************************* + * @file txz_flash.c + * @brief This file provides API functions for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_flash.h" + +#if defined(__FLASH_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FLASH + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_macro FLASH Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ +/** + * @defgroup wait Configuration + * @brief wait Configuration. + * @{ + */ +/* FC ACCR setting configration */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_ACCR_CODE_7CLK (0x00000006UL) /*!< 7clock(less than 200MHZ). */ +#define FC_ACCR_CODE_6CLK (0x00000005UL) /*!< 6clock(less than 160MHZ). */ +#define FC_ACCR_CODE_5CLK (0x00000004UL) /*!< 5clock(less than 120MHZ). */ +#define FC_ACCR_CODE_4CLK (0x00000003UL) /*!< 4clock(less than 100MHZ). */ +#define FC_ACCR_CODE_3CLK (0x00000002UL) /*!< 3clock(less than 80MHZ). */ +#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */ +#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */ +#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */ +#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */ +#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */ + +#define FC_ACCR_DATA (FC_ACCR_DATA_7CLK) +#define FC_ACCR_DATA_7CLK (0x00000600UL) /*!< 7clock(Must). */ + +/** + * @} + */ /* End of group waitConfiguration */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_define FLASH Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_typedef FLASH Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FLASH_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FLASH_Private_fuctions FLASH Private Fuctions + * @{ + */ + +/** + * @} + */ /* End of group FLASH_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FLASH_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Raed clock set. + * @param none. + * @retval none. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +void fc_read_clock_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock <= FC_ACCR_80MHZ) { /* less than 80MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->ACCR = regval; + while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_3CLK | FC_ACCR_DATA)) { + } + } else if (sysclock <= FC_ACCR_100MHZ) { /* less than 100MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->ACCR = regval; + while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_4CLK | FC_ACCR_DATA)) { + } + } else if (sysclock <= FC_ACCR_120MHZ) { /* less than 120MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->ACCR = regval; + while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_5CLK | FC_ACCR_DATA)) { + } + } else if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->ACCR = regval; + while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_6CLK | FC_ACCR_DATA)) { + } + } else if (sysclock <= FC_ACCR_200MHZ) { /* less than 200MHZ */ + regval = (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA); + + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->ACCR = regval; + while (TSB_FC->ACCR != (uint32_t)(FC_ACCR_CODE_7CLK | FC_ACCR_DATA)) { + /* no processing */ + } + } else { + /* no processing */ + } +} + +/** + * @} + */ /* End of group FLASH_Exported_functions */ + +/** + * @} + */ /* End of group FLASH */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__FLASH_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fuart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fuart.c new file mode 100644 index 0000000..02b2f43 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fuart.c @@ -0,0 +1,1384 @@ +/** + ******************************************************************************* + * @file txz_fuart.c + * @brief This file provides API functions for FUART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_fuart_include.h" +#include "txz_fuart.h" + +#if defined(__FUART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup FUART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/** + * @defgroup FUART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define FUART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define FUART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define FUART_CFG_GET_BOUDRATE FUART_CFG_GET_BOUDRATE_ENABLE /*!< Disable/Enable Get Bourate Setting */ + +#define FUART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define FUART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define FUART_CFG_GET_BOUDRATE_TYPE FUART_CFG_GET_BOUDRATE_TYPE_ALL /*!< Get Bourate Type Setting */ + +#define FUART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)1) /*!< Error Margin(%). */ +#define FUART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group FUART_BourateConfig */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_define FUART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_typedef FUART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup FUART_Private_fuctions FUART Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef __DEBUG__ */ +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_CTS_DISABLE: + case FUART_CTS_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_RTS_DISABLE: + case FUART_RTS_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_STOP_BIT_1: + case FUART_STOP_BIT_2: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_PARITY_BIT_ODD: + case FUART_PARITY_BIT_EVEN: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_PARITY_DISABLE: + case FUART_PARITY_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_DATA_LENGTH_5: + case FUART_DATA_LENGTH_6: + case FUART_DATA_LENGTH_7: + case FUART_DATA_LENGTH_8: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_FIFO_LEVEL_4: + case FUART_FIFO_LEVEL_8: + case FUART_FIFO_LEVEL_16: + case FUART_FIFO_LEVEL_24: + case FUART_FIFO_LEVEL_28: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_FIFO_LEVEL_4: + case FUART_FIFO_LEVEL_8: + case FUART_FIFO_LEVEL_16: + case FUART_FIFO_LEVEL_24: + case FUART_FIFO_LEVEL_28: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_TX_INT_DISABLE: + case FUART_TX_INT_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + switch (param) { + case FUART_RX_INT_DISABLE: + case FUART_RX_INT_ENABLE: + result = FUART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrpt's parameter. + * @param param :Error Interrpt's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + param &= ~(FUART_OV_ERR_INT_ENABLE | FUART_BK_ERR_INT_ENABLE | FUART_PA_ERR_INT_ENABLE | FUART_FR_ERR_INT_ENABLE | FUART_TO_ERR_INT_ENABLE); + + if (param == 0) { + result = FUART_PARAM_OK; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + /*--- Now, FUART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((FUART_RANGE_K_MIN <= param) && (param <= FUART_RANGE_K_MAX)) +#else + if (param <= FUART_RANGE_K_MAX) +#endif + { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note Macro definition is @ref FUART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if ((FUART_RANGE_N_MIN <= param) && (param <= FUART_RANGE_N_MAX)) { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if (param != 0) { + result = FUART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval FUART_PARAM_OK :Valid + * @retval FUART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = FUART_PARAM_NG; + + if (param != 0) { + result = FUART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef __DEBUG__ */ + +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi T0 */ + tx64 = (uint64_t)((uint64_t)clock << (FUART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * FUART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (uint64_t)k); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group FUART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the FUART object. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_init(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.tx_int.inttx)); + assert_param(check_param_rx_int(p_obj->init.rx_int.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fill_level_range(p_obj->init.tx_int.level)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rx_int.level)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable FUART */ + /*------------------------------*/ + p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | + FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); + /*------------------------------*/ + /* Interrupt Disable */ + /*------------------------------*/ + p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | + FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | + FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | + FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | + FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); + + /*------------------------------*/ + /* FIFO Disable */ + /*------------------------------*/ + p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + p_obj->p_instance->BRD = p_obj->init.boudrate.brn; + p_obj->p_instance->FBRD = p_obj->init.boudrate.brk; + p_obj->p_instance->LCR_H = (p_obj->init.stpa | p_obj->init.sm | + p_obj->init.fifo | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe); + p_obj->p_instance->IFLS = ((p_obj->init.rx_int.level << 3) | p_obj->init.tx_int.level); + p_obj->p_instance->IMSC = (p_obj->init.interr | p_obj->init.tx_int.inttx | p_obj->init.rx_int.intrx); + p_obj->p_instance->CR = (p_obj->init.ctse | p_obj->init.rtse | FUARTxCR_UARTEN_ENABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the FUART object. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_deinit(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable FUART */ + /*------------------------------*/ + p_obj->p_instance->CR = (FUARTxCR_CTSEN_DISABLE | FUARTxCR_RTSEN_DISABLE | + FUARTxCR_RXE_DISABLE | FUARTxCR_TXE_DISABLE | FUARTxCR_UARTEN_DISABLE); + /*------------------------------*/ + /* Interrupt Disable */ + /*------------------------------*/ + p_obj->p_instance->IMSC = (FUART_OV_ERR_INT_DISABLE | FUART_BK_ERR_INT_DISABLE | + FUART_PA_ERR_INT_DISABLE | FUART_FR_ERR_INT_DISABLE | + FUART_TO_ERR_INT_DISABLE | FUART_TX_INT_DISABLE | FUART_RX_INT_DISABLE); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = (FUARTxICR_OEIC_CLR | FUARTxICR_BEIC_CLR | + FUARTxICR_PEIC_CLR | FUARTxICR_FEIC_CLR | + FUARTxICR_RTIC_CLR | FUARTxICR_TXIC_CLR | FUARTxICR_RXIC_CLR); + /*------------------------------*/ + /* FIFO Disable */ + /*------------------------------*/ + p_obj->p_instance->LCR_H = (FUART_STATIC_PARITY_DISABLE | FUART_DATA_LENGTH_8 | FUART_FIFO_DISABLE | FUART_STOP_BIT_1 | FUART_PARITY_BIT_ODD | FUART_PARITY_DISABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_discard_transmit(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + disable_FUARTxCR_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = FUARTxICR_TXIC_CLR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :FUART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_discard_receive(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + disable_FUARTxCR_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Interrupt Clear */ + /*------------------------------*/ + p_obj->p_instance->ICR = FUARTxICR_RXIC_CLR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :FUART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_transmitIt(fuart_t *p_obj, fuart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); + assert_param(check_param_tx_buff_num(p_info->num)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + p_obj->transmit.info.p_data = p_info->p_data; + p_obj->transmit.info.num = p_info->num; + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + volatile uint32_t fr_reg; + + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- FUARTxDR ---*/ + if (p_obj->transmit.info.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_FUARTxCR_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :FUART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref FUART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_receiveIt(fuart_t *p_obj, fuart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + volatile uint8_t dummy; + volatile uint32_t fr_reg; + uint32_t rx_count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + assert_param(IS_POINTER_NOT_NULL(p_info->p_data)); + assert_param(check_param_rx_buff_num(p_info->num)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_RXE(p_obj->p_instance); + /* FIFO CLR */ + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) { + dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + if (p_obj->init.fifo == 1) { + if (++rx_count > FUART_RX_FIFO_MAX) { + break; + } + } else { + if (++rx_count > 1) { + break; + } + } + fr_reg = p_obj->p_instance->FR; + } + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->receive.wp = 0; + p_obj->receive.info.p_data = p_info->p_data; + p_obj->receive.info.num = p_info->num; + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_FUARTxCR_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_transmit_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + volatile uint32_t fr_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_TXE_MASK) == FUARTxCR_TXE_ENABLE) { + if (p_obj->transmit.info.num <= p_obj->transmit.rp) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + /* disable_FUARTxCR_TXE(p_obj->p_instance); */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != FUART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_TXFF_MASK) != FUARTxFR_TXFF_FLAG_SET) { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- FUARTxDR ---*/ + if (p_obj->transmit.info.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.p_data + p_obj->transmit.rp) & FUARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_receive_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + volatile uint32_t fr_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) { + uint32_t rx_count = 0; + + fr_reg = p_obj->p_instance->FR; + while ((fr_reg & FUARTxFR_RXFE_MASK) == FUARTxFR_RXFE_FLAG_CLR) { + *(p_obj->receive.info.p_data + p_obj->receive.wp) = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + p_obj->receive.wp += 1; + if (p_obj->receive.wp >= p_obj->receive.info.num) { + break; + } + if (p_obj->init.fifo == 1) { + if (++rx_count >= FUART_RX_FIFO_MAX) { + break; + } + } else { + break; + } + fr_reg = p_obj->p_instance->FR; + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.wp >= p_obj->receive.info.num) { + if (p_obj->receive.handler != FUART_NULL) { + fuart_receive_t param; + param.p_data = p_obj->receive.info.p_data; + param.num = p_obj->receive.wp; + p_obj->receive.wp = 0; + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_error_irq_handler(fuart_t *p_obj) +{ + uint32_t cr_reg; + uint32_t error; + uint32_t ecr_reg = 0x00; + uint32_t icr_reg = 0x00; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current FUARTxCR */ + cr_reg = p_obj->p_instance->CR; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current FUARTxRSR. */ + error = p_obj->p_instance->RSR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- FUARTxRSR ---*/ + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVER RUN */ + if ((error & FUARTxRSR_OE_MASK) == FUARTxRSR_OE_ERR) { + volatile uint8_t dummy; + + icr_reg |= FUARTxICR_OEIC_CLR; + ecr_reg |= FUARTxECR_OE_CLR; + dummy = (uint8_t)(p_obj->p_instance->DR & FUARTxDR_DR_8BIT_MASK); + err = TXZ_ERROR; + } + /* BREAK */ + if ((error & FUARTxRSR_BE_MASK) == FUARTxRSR_BE_ERR) { + icr_reg |= FUARTxICR_BEIC_CLR; + ecr_reg |= FUARTxECR_BE_CLR; + err = TXZ_ERROR; + } + /* PARITY */ + if ((error & FUARTxRSR_PE_MASK) == FUARTxRSR_PE_ERR) { + icr_reg |= FUARTxICR_PEIC_CLR; + ecr_reg |= FUARTxECR_PE_CLR; + err = TXZ_ERROR; + } + /* FRAMING */ + if ((error & FUARTxRSR_FE_MASK) == FUARTxRSR_FE_ERR) { + icr_reg |= FUARTxICR_FEIC_CLR; + ecr_reg |= FUARTxECR_FE_CLR; + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + p_obj->p_instance->ICR = icr_reg; + p_obj->p_instance->ECR = ecr_reg; + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((cr_reg & FUARTxCR_RXE_MASK) == FUARTxCR_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- FUARTxCR ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_FUARTxCR_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != FUART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for timeout error. + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_timeout_error_irq_handler(fuart_t *p_obj) +{ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != FUART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, FUART_NULL); + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler . + * @param p_obj :FUART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void fuart_irq_handler(fuart_t *p_obj) +{ + uint32_t interrupt_status = p_obj->p_instance->MIS; + if ((interrupt_status & FUARTxMIS_RXMIS_MASK) == FUARTxMIS_RXMIS_REQ) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RXMIS_MASK; + fuart_receive_irq_handler(p_obj); + } + if ((interrupt_status & FUARTxMIS_TXMIS_MASK) == FUARTxMIS_TXMIS_REQ) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_TXMIS_MASK; + fuart_transmit_irq_handler(p_obj); + } + if ((interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK)) != 0) { + p_obj->p_instance->ICR = interrupt_status & (FUARTxMIS_RTMIS_MASK | FUARTxMIS_FEMIS_MASK | FUARTxMIS_PEMIS_MASK | FUARTxMIS_BEMIS_MASK | FUARTxMIS_OEMIS_MASK); + fuart_error_irq_handler(p_obj); + } + if ((interrupt_status & FUARTxMIS_RTMIS_MASK) != 0) { + p_obj->p_instance->ICR = interrupt_status & FUARTxMIS_RTMIS_MASK; + fuart_timeout_error_irq_handler(p_obj); + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | 31-8 | - | - | + * | 7 | TXFE | Transmit FIFO Empty Flag. | + * | 6 | RXFF | Reach Receive Fill Level Flag. | + * | 5 | TXFF | Reach Transmit Fill Level Flag. | | + * | 4 | RXFE | Receive FIFO Empty Flag. | + * | 3 | BUSY | Transmit BUSY Flag. | + * | 2-1 | - | - | + * | 0 | CTS | FUTxCTS Flag. | + * + * @param p_obj :FUART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_status(fuart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- FUARTxFR ---*/ + /* Read current FUARTxFR. */ + *p_status = p_obj->p_instance->FR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | OVRERR | Overrun Error. Use @ref FUART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref FUART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref FUART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref FUART_BreakErr. | + * + * @param p_obj :FUART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_error(fuart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- FUARTxRSR ---*/ + /* Read current FUARTxRSR. */ + *p_error = p_obj->p_instance->RSR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_get_boudrate_setting(uint32_t clock, uint32_t boudrate, fuart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of FUARTxCLK. */ +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi T0 ---*/ + tx = (uint64_t)((uint64_t)clock << FUART_CFG_BOUDRATE_FIXED_POINT_BIT); + + /*--- N+(K/64) division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = FUART_RANGE_K_MIN; (k <= FUART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx - (uint64_t)k; + work >>= FUART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((FUART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= FUART_RANGE_N_MAX)) { + uint64_t workRange = 0; + /* Verification */ + if (verification_boudrate64(clock, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (FUART_CFG_GET_BOUDRATE_TYPE == FUART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } +#endif /* (FUART_CFG_GET_BOUDRATE == FUART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fuart_ex.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fuart_ex.c new file mode 100644 index 0000000..f7bb84b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_fuart_ex.c @@ -0,0 +1,218 @@ +/** + ******************************************************************************* + * @file txz_fuart_ex.c + * @brief This file provides API functions for FUART driver. + * @brief Extended functionality. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_fuart_include.h" +#include "txz_fuart_ex.h" + +#if defined(__FUART_EX_H) + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group FUART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Private_fuctions + * @{ + */ + +/** + * @} + */ /* End of group FUART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup FUART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Send Break. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_send_break(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Set Break */ + /*------------------------------*/ + { + uint32_t trans = p_obj->p_instance->LCR_H; + + trans &= ~FUARTxLCR_H_BRK_MASK; + trans |= FUARTxLCR_H_BRK_SEND; + p_obj->p_instance->LCR_H = trans; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Stop Break. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result fuart_stop_break(fuart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the FUART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Set Break */ + /*------------------------------*/ + { + uint32_t trans = p_obj->p_instance->LCR_H; + + trans &= ~FUARTxLCR_H_BRK_MASK; + trans |= FUARTxLCR_H_BRK_STOP; + p_obj->p_instance->LCR_H = trans; + } + + return (result); +} + + +/** + * @} + */ /* End of group FUART_Exported_functions */ + +/** + * @} + */ /* End of group FUART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_EX_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_gpio.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_gpio.c new file mode 100644 index 0000000..7553b1c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_gpio.c @@ -0,0 +1,1831 @@ +/** + ******************************************************************************* + * @file txz_gpio.c + * @brief This file provides API functions for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_gpio.h" + +#if defined(__GPIO_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup GPIO + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name Bit Operation Macro + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */ +#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */ +#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (uint32_t)(gr)) ) /*!< Operational target Port Adress */ +#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */ +#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)(base)) |= (uint32_t)(0x0000001UL<< (bitnum))) /*!< Target Pin Bit set */ +#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)(base)) &= ~((uint32_t)(0x0000001UL<< (bitnum)))) /*!< Target Pin Bit clear */ +#define BITBAND_PORT_READ(val, base, bitnum) ((val) = ((*((__IO uint32_t *)(base)) & (uint32_t)(0x0000001UL<< (bitnum))) >> (bitnum))) /*!< Target Pin Bit read */ +/** + * @} + */ /* End of Bit Operation Macro */ +/** + * @} + */ /* End of group GPIO_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group GPIO_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group GPIO_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_fuctions GPIO Private Fuctions + * @{ + */ + +static uint8_t change_mode_to_num(uint32_t mode); +static uint8_t change_func_to_num(uint32_t func); +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func); + +static uint8_t change_mode_to_num(uint32_t mode) +{ + uint8_t retVal = 0; + + if (mode == GPIO_Mode_DATA) { + retVal = GPIO_ModeNum_DATA; + } else if (mode == GPIO_Mode_CR) { + retVal = GPIO_ModeNum_CR; + } else if (mode == GPIO_Mode_FR1) { + retVal = GPIO_ModeNum_FR1; + } else if (mode == GPIO_Mode_FR2) { + retVal = GPIO_ModeNum_FR2; + } else if (mode == GPIO_Mode_FR3) { + retVal = GPIO_ModeNum_FR3; + } else if (mode == GPIO_Mode_FR4) { + retVal = GPIO_ModeNum_FR4; + } else if (mode == GPIO_Mode_FR5) { + retVal = GPIO_ModeNum_FR5; + } else if (mode == GPIO_Mode_FR6) { + retVal = GPIO_ModeNum_FR6; + } else if (mode == GPIO_Mode_FR7) { + retVal = GPIO_ModeNum_FR7; + } else if (mode == GPIO_Mode_FR8) { + retVal = GPIO_ModeNum_FR8; + } else if (mode == GPIO_Mode_OD) { + retVal = GPIO_ModeNum_OD; + } else if (mode == GPIO_Mode_PUP) { + retVal = GPIO_ModeNum_PUP; + } else if (mode == GPIO_Mode_PDN) { + retVal = GPIO_ModeNum_PDN; + } else if (mode == GPIO_Mode_IE) { + retVal = GPIO_ModeNum_IE; + } else { + retVal = GPIO_ModeNum_Max; + } + + return retVal; +} + +static uint8_t change_func_to_num(uint32_t func) +{ + uint8_t retVal = 0; + + if (func == GPIO_FR_1) { + retVal = GPIO_ModeNum_FR1; + } else if (func == GPIO_FR_2) { + retVal = GPIO_ModeNum_FR2; + } else if (func == GPIO_FR_3) { + retVal = GPIO_ModeNum_FR3; + } else if (func == GPIO_FR_4) { + retVal = GPIO_ModeNum_FR4; + } else if (func == GPIO_FR_5) { + retVal = GPIO_ModeNum_FR5; + } else if (func == GPIO_FR_6) { + retVal = GPIO_ModeNum_FR6; + } else if (func == GPIO_FR_7) { + retVal = GPIO_ModeNum_FR7; + } else if (func == GPIO_FR_8) { + retVal = GPIO_ModeNum_FR8; + } else if (func == GPIO_FR_NA) { + retVal = GPIO_ModeNum_CR; + } else if (func == 0) { + retVal = GPIO_ModeNum_CR; + } else { + retVal = GPIO_ModeNum_Max; + } + + return retVal; +} + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_pin_exist(gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) + * @brief Check the Pin Exist. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + */ +/*--------------------------------------------------*/ +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) +{ + int32_t result = PARAM_NG; + uint8_t chgmode; + uint16_t tmp; + + chgmode = change_mode_to_num(mode); + if ((chgmode < GPIO_ModeNum_Max) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgmode) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func) +{ + int32_t result = PARAM_NG; + uint8_t chgfunc; + uint16_t tmp; + + chgfunc = change_func_to_num(func); + /* param check skip if func is INPUT or OUTPUT */ + if (chgfunc == GPIO_ModeNum_CR) { + return (PARAM_OK); + } + if ((chgfunc < GPIO_ModeNum_Max) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +/** + * @} + */ /* End of group GPIO_Private_functions */ + + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_init(gpio_t *p_obj, uint32_t group) + * @brief Initialize the GPIO object. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; + + /* Check the NULL of address. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + /* PA Clock Enable */ + PORT_CLOCK_ENABLE_PORTA(TSB_CG_FSYSMENB_IPMENB02); + INIT_GPIO_PORT_A_DATA(p_obj->p_pa_instance->DATA); + INIT_GPIO_PORT_A_CR(p_obj->p_pa_instance->CR); + INIT_GPIO_PORT_A_FR1(p_obj->p_pa_instance->FR1); + INIT_GPIO_PORT_A_FR2(p_obj->p_pa_instance->FR2); + INIT_GPIO_PORT_A_FR3(p_obj->p_pa_instance->FR3); + INIT_GPIO_PORT_A_FR4(p_obj->p_pa_instance->FR4); + INIT_GPIO_PORT_A_FR5(p_obj->p_pa_instance->FR5); + INIT_GPIO_PORT_A_FR6(p_obj->p_pa_instance->FR6); + INIT_GPIO_PORT_A_FR7(p_obj->p_pa_instance->FR7); + INIT_GPIO_PORT_A_FR8(p_obj->p_pa_instance->FR8); + INIT_GPIO_PORT_A_OD(p_obj->p_pa_instance->OD); + INIT_GPIO_PORT_A_PUP(p_obj->p_pa_instance->PUP); + INIT_GPIO_PORT_A_PDN(p_obj->p_pa_instance->PDN); + INIT_GPIO_PORT_A_IE(p_obj->p_pa_instance->IE); + break; + case GPIO_PORT_B: + /* PB Clock Enable */ + PORT_CLOCK_ENABLE_PORTB(TSB_CG_FSYSMENB_IPMENB03); + INIT_GPIO_PORT_B_DATA(p_obj->p_pb_instance->DATA); + INIT_GPIO_PORT_B_CR(p_obj->p_pb_instance->CR); + INIT_GPIO_PORT_B_FR1(p_obj->p_pb_instance->FR1); + INIT_GPIO_PORT_B_FR2(p_obj->p_pb_instance->FR2); + INIT_GPIO_PORT_B_FR3(p_obj->p_pb_instance->FR3); + INIT_GPIO_PORT_B_FR4(p_obj->p_pb_instance->FR4); + INIT_GPIO_PORT_B_FR5(p_obj->p_pb_instance->FR5); + INIT_GPIO_PORT_B_FR6(p_obj->p_pb_instance->FR6); + INIT_GPIO_PORT_B_FR7(p_obj->p_pb_instance->FR7); + INIT_GPIO_PORT_B_FR8(p_obj->p_pb_instance->FR8); + INIT_GPIO_PORT_B_OD(p_obj->p_pb_instance->OD); + INIT_GPIO_PORT_B_PUP(p_obj->p_pb_instance->PUP); + INIT_GPIO_PORT_B_PDN(p_obj->p_pb_instance->PDN); + INIT_GPIO_PORT_B_IE(p_obj->p_pb_instance->IE); + break; + case GPIO_PORT_C: + /* PC Clock Enable */ + PORT_CLOCK_ENABLE_PORTC(TSB_CG_FSYSMENB_IPMENB04); + INIT_GPIO_PORT_C_DATA(p_obj->p_pc_instance->DATA); + INIT_GPIO_PORT_C_CR(p_obj->p_pc_instance->CR); + INIT_GPIO_PORT_C_FR1(p_obj->p_pc_instance->FR1); + INIT_GPIO_PORT_C_FR2(p_obj->p_pc_instance->FR2); + INIT_GPIO_PORT_C_FR3(p_obj->p_pc_instance->FR3); + INIT_GPIO_PORT_C_FR4(p_obj->p_pc_instance->FR4); + INIT_GPIO_PORT_C_FR5(p_obj->p_pc_instance->FR5); + INIT_GPIO_PORT_C_FR6(p_obj->p_pc_instance->FR6); + INIT_GPIO_PORT_C_FR7(p_obj->p_pc_instance->FR7); + INIT_GPIO_PORT_C_FR8(p_obj->p_pc_instance->FR8); + INIT_GPIO_PORT_C_OD(p_obj->p_pc_instance->OD); + INIT_GPIO_PORT_C_PUP(p_obj->p_pc_instance->PUP); + INIT_GPIO_PORT_C_PDN(p_obj->p_pc_instance->PDN); + INIT_GPIO_PORT_C_IE(p_obj->p_pc_instance->IE); + break; + case GPIO_PORT_D: + /* PD Clock Enable */ + PORT_CLOCK_ENABLE_PORTD(TSB_CG_FSYSMENB_IPMENB05); + INIT_GPIO_PORT_D_DATA(p_obj->p_pd_instance->DATA); + INIT_GPIO_PORT_D_CR(p_obj->p_pd_instance->CR); + INIT_GPIO_PORT_D_FR1(p_obj->p_pd_instance->FR1); + INIT_GPIO_PORT_D_FR2(p_obj->p_pd_instance->FR2); + INIT_GPIO_PORT_D_FR3(p_obj->p_pd_instance->FR3); + INIT_GPIO_PORT_D_FR4(p_obj->p_pd_instance->FR4); + INIT_GPIO_PORT_D_FR5(p_obj->p_pd_instance->FR5); + INIT_GPIO_PORT_D_FR6(p_obj->p_pd_instance->FR6); + INIT_GPIO_PORT_D_FR7(p_obj->p_pd_instance->FR7); + INIT_GPIO_PORT_D_FR8(p_obj->p_pd_instance->FR8); + INIT_GPIO_PORT_D_OD(p_obj->p_pd_instance->OD); + INIT_GPIO_PORT_D_PUP(p_obj->p_pd_instance->PUP); + INIT_GPIO_PORT_D_PDN(p_obj->p_pd_instance->PDN); + INIT_GPIO_PORT_D_IE(p_obj->p_pd_instance->IE); + break; + case GPIO_PORT_E: + /* PE Clock Enable */ + PORT_CLOCK_ENABLE_PORTE(TSB_CG_FSYSMENB_IPMENB06); + INIT_GPIO_PORT_E_DATA(p_obj->p_pe_instance->DATA); + INIT_GPIO_PORT_E_CR(p_obj->p_pe_instance->CR); + INIT_GPIO_PORT_E_FR1(p_obj->p_pe_instance->FR1); + INIT_GPIO_PORT_E_FR2(p_obj->p_pe_instance->FR2); + INIT_GPIO_PORT_E_FR3(p_obj->p_pe_instance->FR3); + INIT_GPIO_PORT_E_FR4(p_obj->p_pe_instance->FR4); + INIT_GPIO_PORT_E_FR5(p_obj->p_pe_instance->FR5); + INIT_GPIO_PORT_E_FR6(p_obj->p_pe_instance->FR6); + INIT_GPIO_PORT_E_FR7(p_obj->p_pe_instance->FR7); + INIT_GPIO_PORT_E_FR8(p_obj->p_pe_instance->FR8); + INIT_GPIO_PORT_E_OD(p_obj->p_pe_instance->OD); + INIT_GPIO_PORT_E_PUP(p_obj->p_pe_instance->PUP); + INIT_GPIO_PORT_E_PDN(p_obj->p_pe_instance->PDN); + INIT_GPIO_PORT_E_IE(p_obj->p_pe_instance->IE); + break; + case GPIO_PORT_F: + /* PF Clock Enable */ + PORT_CLOCK_ENABLE_PORTF(TSB_CG_FSYSMENB_IPMENB07); + INIT_GPIO_PORT_F_DATA(p_obj->p_pf_instance->DATA); + INIT_GPIO_PORT_F_CR(p_obj->p_pf_instance->CR); + INIT_GPIO_PORT_F_FR1(p_obj->p_pf_instance->FR1); + INIT_GPIO_PORT_F_FR2(p_obj->p_pf_instance->FR2); + INIT_GPIO_PORT_F_FR3(p_obj->p_pf_instance->FR3); + INIT_GPIO_PORT_F_FR4(p_obj->p_pf_instance->FR4); + INIT_GPIO_PORT_F_FR5(p_obj->p_pf_instance->FR5); + INIT_GPIO_PORT_F_FR6(p_obj->p_pf_instance->FR6); + INIT_GPIO_PORT_F_FR7(p_obj->p_pf_instance->FR7); + INIT_GPIO_PORT_F_FR8(p_obj->p_pf_instance->FR8); + INIT_GPIO_PORT_F_OD(p_obj->p_pf_instance->OD); + INIT_GPIO_PORT_F_PUP(p_obj->p_pf_instance->PUP); + INIT_GPIO_PORT_F_PDN(p_obj->p_pf_instance->PDN); + INIT_GPIO_PORT_F_IE(p_obj->p_pf_instance->IE); + break; + case GPIO_PORT_G: + /* PG Clock Enable */ + PORT_CLOCK_ENABLE_PORTG(TSB_CG_FSYSMENB_IPMENB08); + INIT_GPIO_PORT_G_DATA(p_obj->p_pg_instance->DATA); + INIT_GPIO_PORT_G_CR(p_obj->p_pg_instance->CR); + INIT_GPIO_PORT_G_FR1(p_obj->p_pg_instance->FR1); + INIT_GPIO_PORT_G_FR2(p_obj->p_pg_instance->FR2); + INIT_GPIO_PORT_G_FR3(p_obj->p_pg_instance->FR3); + INIT_GPIO_PORT_G_FR4(p_obj->p_pg_instance->FR4); + INIT_GPIO_PORT_G_FR6(p_obj->p_pg_instance->FR6); + INIT_GPIO_PORT_G_FR5(p_obj->p_pg_instance->FR5); + INIT_GPIO_PORT_G_FR7(p_obj->p_pg_instance->FR7); + INIT_GPIO_PORT_G_FR8(p_obj->p_pg_instance->FR8); + INIT_GPIO_PORT_G_OD(p_obj->p_pg_instance->OD); + INIT_GPIO_PORT_G_PUP(p_obj->p_pg_instance->PUP); + INIT_GPIO_PORT_G_PDN(p_obj->p_pg_instance->PDN); + INIT_GPIO_PORT_G_IE(p_obj->p_pg_instance->IE); + break; + case GPIO_PORT_H: + /* PH Clock Enable */ + PORT_CLOCK_ENABLE_PORTH(TSB_CG_FSYSMENB_IPMENB09); + INIT_GPIO_PORT_H_DATA(p_obj->p_ph_instance->DATA); + INIT_GPIO_PORT_H_CR(p_obj->p_ph_instance->CR); + INIT_GPIO_PORT_H_FR1(p_obj->p_ph_instance->FR1); + INIT_GPIO_PORT_H_FR2(p_obj->p_ph_instance->FR2); + INIT_GPIO_PORT_H_FR3(p_obj->p_ph_instance->FR3); + INIT_GPIO_PORT_H_FR4(p_obj->p_ph_instance->FR4); + INIT_GPIO_PORT_H_FR5(p_obj->p_ph_instance->FR5); + INIT_GPIO_PORT_H_FR6(p_obj->p_ph_instance->FR6); + INIT_GPIO_PORT_H_FR7(p_obj->p_ph_instance->FR7); + INIT_GPIO_PORT_H_FR8(p_obj->p_ph_instance->FR8); + INIT_GPIO_PORT_H_OD(p_obj->p_ph_instance->OD); + INIT_GPIO_PORT_H_PUP(p_obj->p_ph_instance->PUP); + INIT_GPIO_PORT_H_PDN(p_obj->p_ph_instance->PDN); + INIT_GPIO_PORT_H_IE(p_obj->p_ph_instance->IE); + break; + case GPIO_PORT_J: + /* PJ Clock Enable */ + PORT_CLOCK_ENABLE_PORTJ(TSB_CG_FSYSMENB_IPMENB10); + INIT_GPIO_PORT_J_DATA(p_obj->p_pj_instance->DATA); + INIT_GPIO_PORT_J_CR(p_obj->p_pj_instance->CR); + INIT_GPIO_PORT_J_FR1(p_obj->p_pj_instance->FR1); + INIT_GPIO_PORT_J_FR2(p_obj->p_pj_instance->FR2); + INIT_GPIO_PORT_J_FR3(p_obj->p_pj_instance->FR3); + INIT_GPIO_PORT_J_FR4(p_obj->p_pj_instance->FR4); + INIT_GPIO_PORT_J_FR5(p_obj->p_pj_instance->FR5); + INIT_GPIO_PORT_J_FR6(p_obj->p_pj_instance->FR6); + INIT_GPIO_PORT_J_FR7(p_obj->p_pj_instance->FR7); + INIT_GPIO_PORT_J_FR8(p_obj->p_pj_instance->FR8); + INIT_GPIO_PORT_J_OD(p_obj->p_pj_instance->OD); + INIT_GPIO_PORT_J_PUP(p_obj->p_pj_instance->PUP); + INIT_GPIO_PORT_J_PDN(p_obj->p_pj_instance->PDN); + INIT_GPIO_PORT_J_IE(p_obj->p_pj_instance->IE); + break; + case GPIO_PORT_K: + /* PK Clock Enable */ + PORT_CLOCK_ENABLE_PORTK(TSB_CG_FSYSMENB_IPMENB11); + INIT_GPIO_PORT_K_DATA(p_obj->p_pk_instance->DATA); + INIT_GPIO_PORT_K_CR(p_obj->p_pk_instance->CR); + INIT_GPIO_PORT_K_FR1(p_obj->p_pk_instance->FR1); + INIT_GPIO_PORT_K_FR2(p_obj->p_pk_instance->FR2); + INIT_GPIO_PORT_K_FR3(p_obj->p_pk_instance->FR3); + INIT_GPIO_PORT_K_FR4(p_obj->p_pk_instance->FR4); + INIT_GPIO_PORT_K_FR5(p_obj->p_pk_instance->FR5); + INIT_GPIO_PORT_K_FR6(p_obj->p_pk_instance->FR6); + INIT_GPIO_PORT_K_FR7(p_obj->p_pk_instance->FR7); + INIT_GPIO_PORT_K_FR8(p_obj->p_pk_instance->FR8); + INIT_GPIO_PORT_K_OD(p_obj->p_pk_instance->OD); + INIT_GPIO_PORT_K_PUP(p_obj->p_pk_instance->PUP); + INIT_GPIO_PORT_K_PDN(p_obj->p_pk_instance->PDN); + INIT_GPIO_PORT_K_IE(p_obj->p_pk_instance->IE); + break; + case GPIO_PORT_L: + /* PL Clock Enable */ + PORT_CLOCK_ENABLE_PORTL(TSB_CG_FSYSMENB_IPMENB12); + INIT_GPIO_PORT_L_DATA(p_obj->p_pl_instance->DATA); + INIT_GPIO_PORT_L_CR(p_obj->p_pl_instance->CR); + INIT_GPIO_PORT_L_FR1(p_obj->p_pl_instance->FR1); + INIT_GPIO_PORT_L_FR2(p_obj->p_pl_instance->FR2); + INIT_GPIO_PORT_L_FR3(p_obj->p_pl_instance->FR3); + INIT_GPIO_PORT_L_FR4(p_obj->p_pl_instance->FR4); + INIT_GPIO_PORT_L_FR5(p_obj->p_pl_instance->FR5); + INIT_GPIO_PORT_L_FR6(p_obj->p_pl_instance->FR6); + INIT_GPIO_PORT_L_FR7(p_obj->p_pl_instance->FR7); + INIT_GPIO_PORT_L_FR8(p_obj->p_pl_instance->FR8); + INIT_GPIO_PORT_L_OD(p_obj->p_pl_instance->OD); + INIT_GPIO_PORT_L_PUP(p_obj->p_pl_instance->PUP); + INIT_GPIO_PORT_L_PDN(p_obj->p_pl_instance->PDN); + INIT_GPIO_PORT_L_IE(p_obj->p_pl_instance->IE); + break; + case GPIO_PORT_M: + /* PM Clock Enable */ + PORT_CLOCK_ENABLE_PORTM(TSB_CG_FSYSMENB_IPMENB13); + INIT_GPIO_PORT_M_DATA(p_obj->p_pm_instance->DATA); + INIT_GPIO_PORT_M_CR(p_obj->p_pm_instance->CR); + INIT_GPIO_PORT_M_FR1(p_obj->p_pm_instance->FR1); + INIT_GPIO_PORT_M_FR2(p_obj->p_pm_instance->FR2); + INIT_GPIO_PORT_M_FR3(p_obj->p_pm_instance->FR3); + INIT_GPIO_PORT_M_FR4(p_obj->p_pm_instance->FR4); + INIT_GPIO_PORT_M_FR5(p_obj->p_pm_instance->FR5); + INIT_GPIO_PORT_M_FR6(p_obj->p_pm_instance->FR6); + INIT_GPIO_PORT_M_FR7(p_obj->p_pm_instance->FR7); + INIT_GPIO_PORT_M_FR8(p_obj->p_pm_instance->FR8); + INIT_GPIO_PORT_M_OD(p_obj->p_pm_instance->OD); + INIT_GPIO_PORT_M_PUP(p_obj->p_pm_instance->PUP); + INIT_GPIO_PORT_M_PDN(p_obj->p_pm_instance->PDN); + INIT_GPIO_PORT_M_IE(p_obj->p_pm_instance->IE); + break; + case GPIO_PORT_N: + /* PN Clock Enable */ + PORT_CLOCK_ENABLE_PORTN(TSB_CG_FSYSMENB_IPMENB14); + INIT_GPIO_PORT_N_DATA(p_obj->p_pn_instance->DATA); + INIT_GPIO_PORT_N_CR(p_obj->p_pn_instance->CR); + INIT_GPIO_PORT_N_FR1(p_obj->p_pn_instance->FR1); + INIT_GPIO_PORT_N_FR2(p_obj->p_pn_instance->FR2); + INIT_GPIO_PORT_N_FR3(p_obj->p_pn_instance->FR3); + INIT_GPIO_PORT_N_FR4(p_obj->p_pn_instance->FR4); + INIT_GPIO_PORT_N_FR5(p_obj->p_pn_instance->FR5); + INIT_GPIO_PORT_N_FR6(p_obj->p_pn_instance->FR6); + INIT_GPIO_PORT_N_FR7(p_obj->p_pn_instance->FR7); + INIT_GPIO_PORT_N_FR8(p_obj->p_pn_instance->FR8); + INIT_GPIO_PORT_N_OD(p_obj->p_pn_instance->OD); + INIT_GPIO_PORT_N_PUP(p_obj->p_pn_instance->PUP); + INIT_GPIO_PORT_N_PDN(p_obj->p_pn_instance->PDN); + INIT_GPIO_PORT_N_IE(p_obj->p_pn_instance->IE); + break; + case GPIO_PORT_P: + /* PP Clock Enable */ + PORT_CLOCK_ENABLE_PORTP(TSB_CG_FSYSMENB_IPMENB15); + INIT_GPIO_PORT_P_DATA(p_obj->p_pp_instance->DATA); + INIT_GPIO_PORT_P_CR(p_obj->p_pp_instance->CR); + INIT_GPIO_PORT_P_FR1(p_obj->p_pp_instance->FR1); + INIT_GPIO_PORT_P_FR2(p_obj->p_pp_instance->FR2); + INIT_GPIO_PORT_P_FR3(p_obj->p_pp_instance->FR3); + INIT_GPIO_PORT_P_FR4(p_obj->p_pp_instance->FR4); + INIT_GPIO_PORT_P_FR5(p_obj->p_pp_instance->FR5); + INIT_GPIO_PORT_P_FR6(p_obj->p_pp_instance->FR6); + INIT_GPIO_PORT_P_FR7(p_obj->p_pp_instance->FR7); + INIT_GPIO_PORT_P_FR8(p_obj->p_pp_instance->FR8); + INIT_GPIO_PORT_P_OD(p_obj->p_pp_instance->OD); + INIT_GPIO_PORT_P_PUP(p_obj->p_pp_instance->PUP); + INIT_GPIO_PORT_P_PDN(p_obj->p_pp_instance->PDN); + INIT_GPIO_PORT_P_IE(p_obj->p_pp_instance->IE); + break; + case GPIO_PORT_R: + /* PR Clock Enable */ + PORT_CLOCK_ENABLE_PORTR(TSB_CG_FSYSMENB_IPMENB16); + INIT_GPIO_PORT_R_DATA(p_obj->p_pr_instance->DATA); + INIT_GPIO_PORT_R_CR(p_obj->p_pr_instance->CR); + INIT_GPIO_PORT_R_FR1(p_obj->p_pr_instance->FR1); + INIT_GPIO_PORT_R_FR2(p_obj->p_pr_instance->FR2); + INIT_GPIO_PORT_R_FR3(p_obj->p_pr_instance->FR3); + INIT_GPIO_PORT_R_FR4(p_obj->p_pr_instance->FR4); + INIT_GPIO_PORT_R_FR5(p_obj->p_pr_instance->FR5); + INIT_GPIO_PORT_R_FR6(p_obj->p_pr_instance->FR6); + INIT_GPIO_PORT_R_FR7(p_obj->p_pr_instance->FR7); + INIT_GPIO_PORT_R_FR8(p_obj->p_pr_instance->FR8); + INIT_GPIO_PORT_R_OD(p_obj->p_pr_instance->OD); + INIT_GPIO_PORT_R_PUP(p_obj->p_pr_instance->PUP); + INIT_GPIO_PORT_R_PDN(p_obj->p_pr_instance->PDN); + INIT_GPIO_PORT_R_IE(p_obj->p_pr_instance->IE); + break; + case GPIO_PORT_T: + /* PT Clock Enable */ + PORT_CLOCK_ENABLE_PORTT(TSB_CG_FSYSMENB_IPMENB17); + INIT_GPIO_PORT_T_DATA(p_obj->p_pt_instance->DATA); + INIT_GPIO_PORT_T_CR(p_obj->p_pt_instance->CR); + INIT_GPIO_PORT_T_FR1(p_obj->p_pt_instance->FR1); + INIT_GPIO_PORT_T_FR2(p_obj->p_pt_instance->FR2); + INIT_GPIO_PORT_T_FR3(p_obj->p_pt_instance->FR3); + INIT_GPIO_PORT_T_FR4(p_obj->p_pt_instance->FR4); + INIT_GPIO_PORT_T_FR5(p_obj->p_pt_instance->FR5); + INIT_GPIO_PORT_T_FR6(p_obj->p_pt_instance->FR6); + INIT_GPIO_PORT_T_FR7(p_obj->p_pt_instance->FR7); + INIT_GPIO_PORT_T_FR8(p_obj->p_pt_instance->FR8); + INIT_GPIO_PORT_T_OD(p_obj->p_pt_instance->OD); + INIT_GPIO_PORT_T_PUP(p_obj->p_pt_instance->PUP); + INIT_GPIO_PORT_T_PDN(p_obj->p_pt_instance->PDN); + INIT_GPIO_PORT_T_IE(p_obj->p_pt_instance->IE); + break; + case GPIO_PORT_U: + /* PU Clock Enable */ + PORT_CLOCK_ENABLE_PORTU(TSB_CG_FSYSMENB_IPMENB18); + INIT_GPIO_PORT_U_DATA(p_obj->p_pu_instance->DATA); + INIT_GPIO_PORT_U_CR(p_obj->p_pu_instance->CR); + INIT_GPIO_PORT_U_FR1(p_obj->p_pu_instance->FR1); + INIT_GPIO_PORT_U_FR2(p_obj->p_pu_instance->FR2); + INIT_GPIO_PORT_U_FR3(p_obj->p_pu_instance->FR3); + INIT_GPIO_PORT_U_FR4(p_obj->p_pu_instance->FR4); + INIT_GPIO_PORT_U_FR5(p_obj->p_pu_instance->FR5); + INIT_GPIO_PORT_U_FR6(p_obj->p_pu_instance->FR6); + INIT_GPIO_PORT_U_FR7(p_obj->p_pu_instance->FR7); + INIT_GPIO_PORT_U_FR8(p_obj->p_pu_instance->FR8); + INIT_GPIO_PORT_U_OD(p_obj->p_pu_instance->OD); + INIT_GPIO_PORT_U_PUP(p_obj->p_pu_instance->PUP); + INIT_GPIO_PORT_U_PDN(p_obj->p_pu_instance->PDN); + INIT_GPIO_PORT_U_IE(p_obj->p_pu_instance->IE); + break; + case GPIO_PORT_V: + /* PV Clock Enable */ + PORT_CLOCK_ENABLE_PORTV(TSB_CG_FSYSMENB_IPMENB19); + INIT_GPIO_PORT_V_DATA(p_obj->p_pv_instance->DATA); + INIT_GPIO_PORT_V_CR(p_obj->p_pv_instance->CR); + INIT_GPIO_PORT_V_FR1(p_obj->p_pv_instance->FR1); + INIT_GPIO_PORT_V_FR2(p_obj->p_pv_instance->FR2); + INIT_GPIO_PORT_V_FR3(p_obj->p_pv_instance->FR3); + INIT_GPIO_PORT_V_FR4(p_obj->p_pv_instance->FR4); + INIT_GPIO_PORT_V_FR5(p_obj->p_pv_instance->FR5); + INIT_GPIO_PORT_V_FR6(p_obj->p_pv_instance->FR6); + INIT_GPIO_PORT_V_FR7(p_obj->p_pv_instance->FR7); + INIT_GPIO_PORT_V_FR8(p_obj->p_pv_instance->FR8); + INIT_GPIO_PORT_V_OD(p_obj->p_pv_instance->OD); + INIT_GPIO_PORT_V_PUP(p_obj->p_pv_instance->PUP); + INIT_GPIO_PORT_V_PDN(p_obj->p_pv_instance->PDN); + INIT_GPIO_PORT_V_IE(p_obj->p_pv_instance->IE); + break; + case GPIO_PORT_W: + /* PW Clock Enable */ + PORT_CLOCK_ENABLE_PORTW(TSB_CG_FSYSMENB_IPMENB20); + INIT_GPIO_PORT_W_DATA(p_obj->p_pw_instance->DATA); + INIT_GPIO_PORT_W_CR(p_obj->p_pw_instance->CR); + INIT_GPIO_PORT_W_FR1(p_obj->p_pw_instance->FR1); + INIT_GPIO_PORT_W_FR2(p_obj->p_pw_instance->FR2); + INIT_GPIO_PORT_W_FR3(p_obj->p_pw_instance->FR3); + INIT_GPIO_PORT_W_FR4(p_obj->p_pw_instance->FR4); + INIT_GPIO_PORT_W_FR5(p_obj->p_pw_instance->FR5); + INIT_GPIO_PORT_W_FR6(p_obj->p_pw_instance->FR6); + INIT_GPIO_PORT_W_FR7(p_obj->p_pw_instance->FR7); + INIT_GPIO_PORT_W_FR8(p_obj->p_pw_instance->FR8); + INIT_GPIO_PORT_W_OD(p_obj->p_pw_instance->OD); + INIT_GPIO_PORT_W_PUP(p_obj->p_pw_instance->PUP); + INIT_GPIO_PORT_W_PDN(p_obj->p_pw_instance->PDN); + INIT_GPIO_PORT_W_IE(p_obj->p_pw_instance->IE); + break; + case GPIO_PORT_Y: + /* PY Clock Enable */ + PORT_CLOCK_ENABLE_PORTY(TSB_CG_FSYSMENB_IPMENB21); + INIT_GPIO_PORT_Y_DATA(p_obj->p_py_instance->DATA); + INIT_GPIO_PORT_Y_CR(p_obj->p_py_instance->CR); + INIT_GPIO_PORT_Y_FR1(p_obj->p_py_instance->FR1); + INIT_GPIO_PORT_Y_FR2(p_obj->p_py_instance->FR2); + INIT_GPIO_PORT_Y_FR3(p_obj->p_py_instance->FR3); + INIT_GPIO_PORT_Y_FR4(p_obj->p_py_instance->FR4); + INIT_GPIO_PORT_Y_FR5(p_obj->p_py_instance->FR5); + INIT_GPIO_PORT_Y_FR6(p_obj->p_py_instance->FR6); + INIT_GPIO_PORT_Y_FR7(p_obj->p_py_instance->FR7); + INIT_GPIO_PORT_Y_FR8(p_obj->p_py_instance->FR8); + INIT_GPIO_PORT_Y_OD(p_obj->p_py_instance->OD); + INIT_GPIO_PORT_Y_PUP(p_obj->p_py_instance->PUP); + INIT_GPIO_PORT_Y_PDN(p_obj->p_py_instance->PDN); + INIT_GPIO_PORT_Y_IE(p_obj->p_py_instance->IE); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_deinit(gpio_t *p_obj, uint32_t group) + * @brief Release the GPIO object. + * @param p_obj :GPIO object. + * @param group :GPIO Port Group.: Use @ref gpio_gr_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; + + /* Check the NULL of address. */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else { + /* Disable the selected GPIO peripheral */ + switch (group) { + case GPIO_PORT_A: + INIT_GPIO_PORT_A_DATA(p_obj->p_pa_instance->DATA); + INIT_GPIO_PORT_A_CR(p_obj->p_pa_instance->CR); + INIT_GPIO_PORT_A_FR1(p_obj->p_pa_instance->FR1); + INIT_GPIO_PORT_A_FR2(p_obj->p_pa_instance->FR2); + INIT_GPIO_PORT_A_FR3(p_obj->p_pa_instance->FR3); + INIT_GPIO_PORT_A_FR4(p_obj->p_pa_instance->FR4); + INIT_GPIO_PORT_A_FR5(p_obj->p_pa_instance->FR5); + INIT_GPIO_PORT_A_FR6(p_obj->p_pa_instance->FR6); + INIT_GPIO_PORT_A_FR7(p_obj->p_pa_instance->FR7); + INIT_GPIO_PORT_A_FR8(p_obj->p_pa_instance->FR8); + INIT_GPIO_PORT_A_OD(p_obj->p_pa_instance->OD); + INIT_GPIO_PORT_A_PUP(p_obj->p_pa_instance->PUP); + INIT_GPIO_PORT_A_PDN(p_obj->p_pa_instance->PDN); + INIT_GPIO_PORT_A_IE(p_obj->p_pa_instance->IE); + /* PA Clock Disable */ + PORT_CLOCK_DISABLE_PORTA(TSB_CG_FSYSMENB_IPMENB02); + break; + case GPIO_PORT_B: + INIT_GPIO_PORT_B_DATA(p_obj->p_pb_instance->DATA); + INIT_GPIO_PORT_B_CR(p_obj->p_pb_instance->CR); + INIT_GPIO_PORT_B_FR1(p_obj->p_pb_instance->FR1); + INIT_GPIO_PORT_B_FR2(p_obj->p_pb_instance->FR2); + INIT_GPIO_PORT_B_FR3(p_obj->p_pb_instance->FR3); + INIT_GPIO_PORT_B_FR4(p_obj->p_pb_instance->FR4); + INIT_GPIO_PORT_B_FR5(p_obj->p_pb_instance->FR5); + INIT_GPIO_PORT_B_FR6(p_obj->p_pb_instance->FR6); + INIT_GPIO_PORT_B_FR7(p_obj->p_pb_instance->FR7); + INIT_GPIO_PORT_B_FR8(p_obj->p_pb_instance->FR8); + INIT_GPIO_PORT_B_OD(p_obj->p_pb_instance->OD); + INIT_GPIO_PORT_B_PUP(p_obj->p_pb_instance->PUP); + INIT_GPIO_PORT_B_PDN(p_obj->p_pb_instance->PDN); + INIT_GPIO_PORT_B_IE(p_obj->p_pb_instance->IE); + /* PB Clock Disable */ + PORT_CLOCK_DISABLE_PORTB(TSB_CG_FSYSMENB_IPMENB03); + break; + case GPIO_PORT_C: + INIT_GPIO_PORT_C_DATA(p_obj->p_pc_instance->DATA); + INIT_GPIO_PORT_C_CR(p_obj->p_pc_instance->CR); + INIT_GPIO_PORT_C_FR1(p_obj->p_pc_instance->FR1); + INIT_GPIO_PORT_C_FR2(p_obj->p_pc_instance->FR2); + INIT_GPIO_PORT_C_FR3(p_obj->p_pc_instance->FR3); + INIT_GPIO_PORT_C_FR4(p_obj->p_pc_instance->FR4); + INIT_GPIO_PORT_C_FR5(p_obj->p_pc_instance->FR5); + INIT_GPIO_PORT_C_FR6(p_obj->p_pc_instance->FR6); + INIT_GPIO_PORT_C_FR7(p_obj->p_pc_instance->FR7); + INIT_GPIO_PORT_C_FR8(p_obj->p_pc_instance->FR8); + INIT_GPIO_PORT_C_OD(p_obj->p_pc_instance->OD); + INIT_GPIO_PORT_C_PUP(p_obj->p_pc_instance->PUP); + INIT_GPIO_PORT_C_PDN(p_obj->p_pc_instance->PDN); + INIT_GPIO_PORT_C_IE(p_obj->p_pc_instance->IE); + /* PC Clock Disable */ + PORT_CLOCK_DISABLE_PORTC(TSB_CG_FSYSMENB_IPMENB04); + break; + case GPIO_PORT_D: + INIT_GPIO_PORT_D_DATA(p_obj->p_pd_instance->DATA); + INIT_GPIO_PORT_D_CR(p_obj->p_pd_instance->CR); + INIT_GPIO_PORT_D_FR1(p_obj->p_pd_instance->FR1); + INIT_GPIO_PORT_D_FR2(p_obj->p_pd_instance->FR2); + INIT_GPIO_PORT_D_FR3(p_obj->p_pd_instance->FR3); + INIT_GPIO_PORT_D_FR4(p_obj->p_pd_instance->FR4); + INIT_GPIO_PORT_D_FR5(p_obj->p_pd_instance->FR5); + INIT_GPIO_PORT_D_FR6(p_obj->p_pd_instance->FR6); + INIT_GPIO_PORT_D_FR7(p_obj->p_pd_instance->FR7); + INIT_GPIO_PORT_D_FR8(p_obj->p_pd_instance->FR8); + INIT_GPIO_PORT_D_OD(p_obj->p_pd_instance->OD); + INIT_GPIO_PORT_D_PUP(p_obj->p_pd_instance->PUP); + INIT_GPIO_PORT_D_PDN(p_obj->p_pd_instance->PDN); + INIT_GPIO_PORT_D_IE(p_obj->p_pd_instance->IE); + /* PD Clock Disable */ + PORT_CLOCK_DISABLE_PORTD(TSB_CG_FSYSMENB_IPMENB05); + break; + case GPIO_PORT_E: + INIT_GPIO_PORT_E_DATA(p_obj->p_pe_instance->DATA); + INIT_GPIO_PORT_E_CR(p_obj->p_pe_instance->CR); + INIT_GPIO_PORT_E_FR1(p_obj->p_pe_instance->FR1); + INIT_GPIO_PORT_E_FR2(p_obj->p_pe_instance->FR2); + INIT_GPIO_PORT_E_FR3(p_obj->p_pe_instance->FR3); + INIT_GPIO_PORT_E_FR4(p_obj->p_pe_instance->FR4); + INIT_GPIO_PORT_E_FR5(p_obj->p_pe_instance->FR5); + INIT_GPIO_PORT_E_FR6(p_obj->p_pe_instance->FR6); + INIT_GPIO_PORT_E_FR7(p_obj->p_pe_instance->FR7); + INIT_GPIO_PORT_E_FR8(p_obj->p_pe_instance->FR8); + INIT_GPIO_PORT_E_OD(p_obj->p_pe_instance->OD); + INIT_GPIO_PORT_E_PUP(p_obj->p_pe_instance->PUP); + INIT_GPIO_PORT_E_PDN(p_obj->p_pe_instance->PDN); + INIT_GPIO_PORT_E_IE(p_obj->p_pe_instance->IE); + /* PE Clock Disable */ + PORT_CLOCK_DISABLE_PORTE(TSB_CG_FSYSMENB_IPMENB06); + break; + case GPIO_PORT_F: + INIT_GPIO_PORT_F_DATA(p_obj->p_pf_instance->DATA); + INIT_GPIO_PORT_F_CR(p_obj->p_pf_instance->CR); + INIT_GPIO_PORT_F_FR1(p_obj->p_pf_instance->FR1); + INIT_GPIO_PORT_F_FR2(p_obj->p_pf_instance->FR2); + INIT_GPIO_PORT_F_FR3(p_obj->p_pf_instance->FR3); + INIT_GPIO_PORT_F_FR4(p_obj->p_pf_instance->FR4); + INIT_GPIO_PORT_F_FR5(p_obj->p_pf_instance->FR5); + INIT_GPIO_PORT_F_FR6(p_obj->p_pf_instance->FR6); + INIT_GPIO_PORT_F_FR7(p_obj->p_pf_instance->FR7); + INIT_GPIO_PORT_F_FR8(p_obj->p_pf_instance->FR8); + INIT_GPIO_PORT_F_OD(p_obj->p_pf_instance->OD); + INIT_GPIO_PORT_F_PUP(p_obj->p_pf_instance->PUP); + INIT_GPIO_PORT_F_PDN(p_obj->p_pf_instance->PDN); + INIT_GPIO_PORT_F_IE(p_obj->p_pf_instance->IE); + /* PF Clock Disable */ + PORT_CLOCK_DISABLE_PORTF(TSB_CG_FSYSMENB_IPMENB07); + break; + case GPIO_PORT_G: + INIT_GPIO_PORT_G_DATA(p_obj->p_pg_instance->DATA); + INIT_GPIO_PORT_G_CR(p_obj->p_pg_instance->CR); + INIT_GPIO_PORT_G_FR1(p_obj->p_pg_instance->FR1); + INIT_GPIO_PORT_G_FR2(p_obj->p_pg_instance->FR2); + INIT_GPIO_PORT_G_FR3(p_obj->p_pg_instance->FR3); + INIT_GPIO_PORT_G_FR4(p_obj->p_pg_instance->FR4); + INIT_GPIO_PORT_G_FR5(p_obj->p_pg_instance->FR5); + INIT_GPIO_PORT_G_FR6(p_obj->p_pg_instance->FR6); + INIT_GPIO_PORT_G_FR7(p_obj->p_pg_instance->FR7); + INIT_GPIO_PORT_G_FR8(p_obj->p_pg_instance->FR8); + INIT_GPIO_PORT_G_OD(p_obj->p_pg_instance->OD); + INIT_GPIO_PORT_G_PUP(p_obj->p_pg_instance->PUP); + INIT_GPIO_PORT_G_PDN(p_obj->p_pg_instance->PDN); + INIT_GPIO_PORT_G_IE(p_obj->p_pg_instance->IE); + /* PG Clock Disable */ + PORT_CLOCK_DISABLE_PORTG(TSB_CG_FSYSMENB_IPMENB08); + break; + case GPIO_PORT_H: + INIT_GPIO_PORT_H_DATA(p_obj->p_ph_instance->DATA); + INIT_GPIO_PORT_H_CR(p_obj->p_ph_instance->CR); + INIT_GPIO_PORT_H_FR1(p_obj->p_ph_instance->FR1); + INIT_GPIO_PORT_H_FR2(p_obj->p_ph_instance->FR2); + INIT_GPIO_PORT_H_FR3(p_obj->p_ph_instance->FR3); + INIT_GPIO_PORT_H_FR4(p_obj->p_ph_instance->FR4); + INIT_GPIO_PORT_H_FR5(p_obj->p_ph_instance->FR5); + INIT_GPIO_PORT_H_FR6(p_obj->p_ph_instance->FR6); + INIT_GPIO_PORT_H_FR7(p_obj->p_ph_instance->FR7); + INIT_GPIO_PORT_H_FR8(p_obj->p_ph_instance->FR8); + INIT_GPIO_PORT_H_OD(p_obj->p_ph_instance->OD); + INIT_GPIO_PORT_H_PUP(p_obj->p_ph_instance->PUP); + INIT_GPIO_PORT_H_PDN(p_obj->p_ph_instance->PDN); + INIT_GPIO_PORT_H_IE(p_obj->p_ph_instance->IE); + /* PH Clock Disable */ + PORT_CLOCK_DISABLE_PORTH(TSB_CG_FSYSMENB_IPMENB09); + break; + case GPIO_PORT_J: + INIT_GPIO_PORT_J_DATA(p_obj->p_pj_instance->DATA); + INIT_GPIO_PORT_J_CR(p_obj->p_pj_instance->CR); + INIT_GPIO_PORT_J_FR1(p_obj->p_pj_instance->FR1); + INIT_GPIO_PORT_J_FR2(p_obj->p_pj_instance->FR2); + INIT_GPIO_PORT_J_FR3(p_obj->p_pj_instance->FR3); + INIT_GPIO_PORT_J_FR4(p_obj->p_pj_instance->FR4); + INIT_GPIO_PORT_J_FR5(p_obj->p_pj_instance->FR5); + INIT_GPIO_PORT_J_FR6(p_obj->p_pj_instance->FR6); + INIT_GPIO_PORT_J_FR7(p_obj->p_pj_instance->FR7); + INIT_GPIO_PORT_J_FR8(p_obj->p_pj_instance->FR8); + INIT_GPIO_PORT_J_OD(p_obj->p_pj_instance->OD); + INIT_GPIO_PORT_J_PUP(p_obj->p_pj_instance->PUP); + INIT_GPIO_PORT_J_PDN(p_obj->p_pj_instance->PDN); + INIT_GPIO_PORT_J_IE(p_obj->p_pj_instance->IE); + /* PJ Clock Disable */ + PORT_CLOCK_DISABLE_PORTJ(TSB_CG_FSYSMENB_IPMENB10); + break; + case GPIO_PORT_K: + INIT_GPIO_PORT_K_DATA(p_obj->p_pk_instance->DATA); + INIT_GPIO_PORT_K_CR(p_obj->p_pk_instance->CR); + INIT_GPIO_PORT_K_FR1(p_obj->p_pk_instance->FR1); + INIT_GPIO_PORT_K_FR2(p_obj->p_pk_instance->FR2); + INIT_GPIO_PORT_K_FR3(p_obj->p_pk_instance->FR3); + INIT_GPIO_PORT_K_FR4(p_obj->p_pk_instance->FR4); + INIT_GPIO_PORT_K_FR5(p_obj->p_pk_instance->FR5); + INIT_GPIO_PORT_K_FR6(p_obj->p_pk_instance->FR6); + INIT_GPIO_PORT_K_FR7(p_obj->p_pk_instance->FR7); + INIT_GPIO_PORT_K_FR8(p_obj->p_pk_instance->FR8); + INIT_GPIO_PORT_K_OD(p_obj->p_pk_instance->OD); + INIT_GPIO_PORT_K_PUP(p_obj->p_pk_instance->PUP); + INIT_GPIO_PORT_K_PDN(p_obj->p_pk_instance->PDN); + INIT_GPIO_PORT_K_IE(p_obj->p_pk_instance->IE); + /* PK Clock Disable */ + PORT_CLOCK_DISABLE_PORTK(TSB_CG_FSYSMENB_IPMENB11); + break; + case GPIO_PORT_L: + INIT_GPIO_PORT_L_DATA(p_obj->p_pl_instance->DATA); + INIT_GPIO_PORT_L_CR(p_obj->p_pl_instance->CR); + INIT_GPIO_PORT_L_FR1(p_obj->p_pl_instance->FR1); + INIT_GPIO_PORT_L_FR2(p_obj->p_pl_instance->FR2); + INIT_GPIO_PORT_L_FR3(p_obj->p_pl_instance->FR3); + INIT_GPIO_PORT_L_FR4(p_obj->p_pl_instance->FR4); + INIT_GPIO_PORT_L_FR5(p_obj->p_pl_instance->FR5); + INIT_GPIO_PORT_L_FR6(p_obj->p_pl_instance->FR6); + INIT_GPIO_PORT_L_FR7(p_obj->p_pl_instance->FR7); + INIT_GPIO_PORT_L_FR8(p_obj->p_pl_instance->FR8); + INIT_GPIO_PORT_L_OD(p_obj->p_pl_instance->OD); + INIT_GPIO_PORT_L_PUP(p_obj->p_pl_instance->PUP); + INIT_GPIO_PORT_L_PDN(p_obj->p_pl_instance->PDN); + INIT_GPIO_PORT_L_IE(p_obj->p_pl_instance->IE); + /* PL Clock Disable */ + PORT_CLOCK_DISABLE_PORTL(TSB_CG_FSYSMENB_IPMENB12); + break; + case GPIO_PORT_M: + INIT_GPIO_PORT_M_DATA(p_obj->p_pm_instance->DATA); + INIT_GPIO_PORT_M_CR(p_obj->p_pm_instance->CR); + INIT_GPIO_PORT_M_FR1(p_obj->p_pm_instance->FR1); + INIT_GPIO_PORT_M_FR2(p_obj->p_pm_instance->FR2); + INIT_GPIO_PORT_M_FR3(p_obj->p_pm_instance->FR3); + INIT_GPIO_PORT_M_FR4(p_obj->p_pm_instance->FR4); + INIT_GPIO_PORT_M_FR5(p_obj->p_pm_instance->FR5); + INIT_GPIO_PORT_M_FR6(p_obj->p_pm_instance->FR6); + INIT_GPIO_PORT_M_FR7(p_obj->p_pm_instance->FR7); + INIT_GPIO_PORT_M_FR8(p_obj->p_pm_instance->FR8); + INIT_GPIO_PORT_M_OD(p_obj->p_pm_instance->OD); + INIT_GPIO_PORT_M_PUP(p_obj->p_pm_instance->PUP); + INIT_GPIO_PORT_M_PDN(p_obj->p_pm_instance->PDN); + INIT_GPIO_PORT_M_IE(p_obj->p_pm_instance->IE); + /* PM Clock Disable */ + PORT_CLOCK_DISABLE_PORTM(TSB_CG_FSYSMENB_IPMENB13); + break; + case GPIO_PORT_N: + INIT_GPIO_PORT_N_DATA(p_obj->p_pn_instance->DATA); + INIT_GPIO_PORT_N_CR(p_obj->p_pn_instance->CR); + INIT_GPIO_PORT_N_FR1(p_obj->p_pn_instance->FR1); + INIT_GPIO_PORT_N_FR2(p_obj->p_pn_instance->FR2); + INIT_GPIO_PORT_N_FR3(p_obj->p_pn_instance->FR3); + INIT_GPIO_PORT_N_FR4(p_obj->p_pn_instance->FR4); + INIT_GPIO_PORT_N_FR5(p_obj->p_pn_instance->FR5); + INIT_GPIO_PORT_N_FR6(p_obj->p_pn_instance->FR6); + INIT_GPIO_PORT_N_FR7(p_obj->p_pn_instance->FR7); + INIT_GPIO_PORT_N_FR8(p_obj->p_pn_instance->FR8); + INIT_GPIO_PORT_N_OD(p_obj->p_pn_instance->OD); + INIT_GPIO_PORT_N_PUP(p_obj->p_pn_instance->PUP); + INIT_GPIO_PORT_N_PDN(p_obj->p_pn_instance->PDN); + INIT_GPIO_PORT_N_IE(p_obj->p_pn_instance->IE); + /* PN Clock Disable */ + PORT_CLOCK_DISABLE_PORTN(TSB_CG_FSYSMENB_IPMENB14); + break; + case GPIO_PORT_P: + INIT_GPIO_PORT_P_DATA(p_obj->p_pp_instance->DATA); + INIT_GPIO_PORT_P_CR(p_obj->p_pp_instance->CR); + INIT_GPIO_PORT_P_FR1(p_obj->p_pp_instance->FR1); + INIT_GPIO_PORT_P_FR2(p_obj->p_pp_instance->FR2); + INIT_GPIO_PORT_P_FR3(p_obj->p_pp_instance->FR3); + INIT_GPIO_PORT_P_FR4(p_obj->p_pp_instance->FR4); + INIT_GPIO_PORT_P_FR5(p_obj->p_pp_instance->FR5); + INIT_GPIO_PORT_P_FR6(p_obj->p_pp_instance->FR6); + INIT_GPIO_PORT_P_FR7(p_obj->p_pp_instance->FR7); + INIT_GPIO_PORT_P_FR8(p_obj->p_pp_instance->FR8); + INIT_GPIO_PORT_P_OD(p_obj->p_pp_instance->OD); + INIT_GPIO_PORT_P_PUP(p_obj->p_pp_instance->PUP); + INIT_GPIO_PORT_P_PDN(p_obj->p_pp_instance->PDN); + INIT_GPIO_PORT_P_IE(p_obj->p_pp_instance->IE); + /* PP Clock Disable */ + PORT_CLOCK_DISABLE_PORTP(TSB_CG_FSYSMENB_IPMENB15); + break; + case GPIO_PORT_R: + INIT_GPIO_PORT_R_DATA(p_obj->p_pr_instance->DATA); + INIT_GPIO_PORT_R_CR(p_obj->p_pr_instance->CR); + INIT_GPIO_PORT_R_FR1(p_obj->p_pr_instance->FR1); + INIT_GPIO_PORT_R_FR2(p_obj->p_pr_instance->FR2); + INIT_GPIO_PORT_R_FR3(p_obj->p_pr_instance->FR3); + INIT_GPIO_PORT_R_FR4(p_obj->p_pr_instance->FR4); + INIT_GPIO_PORT_R_FR5(p_obj->p_pr_instance->FR5); + INIT_GPIO_PORT_R_FR6(p_obj->p_pr_instance->FR6); + INIT_GPIO_PORT_R_FR7(p_obj->p_pr_instance->FR7); + INIT_GPIO_PORT_R_FR8(p_obj->p_pr_instance->FR8); + INIT_GPIO_PORT_R_OD(p_obj->p_pr_instance->OD); + INIT_GPIO_PORT_R_PUP(p_obj->p_pr_instance->PUP); + INIT_GPIO_PORT_R_PDN(p_obj->p_pr_instance->PDN); + INIT_GPIO_PORT_R_IE(p_obj->p_pr_instance->IE); + /* PR Clock Disable */ + PORT_CLOCK_DISABLE_PORTR(TSB_CG_FSYSMENB_IPMENB16); + break; + case GPIO_PORT_T: + INIT_GPIO_PORT_T_DATA(p_obj->p_pt_instance->DATA); + INIT_GPIO_PORT_T_CR(p_obj->p_pt_instance->CR); + INIT_GPIO_PORT_T_FR1(p_obj->p_pt_instance->FR1); + INIT_GPIO_PORT_T_FR2(p_obj->p_pt_instance->FR2); + INIT_GPIO_PORT_T_FR3(p_obj->p_pt_instance->FR3); + INIT_GPIO_PORT_T_FR4(p_obj->p_pt_instance->FR4); + INIT_GPIO_PORT_T_FR5(p_obj->p_pt_instance->FR5); + INIT_GPIO_PORT_T_FR6(p_obj->p_pt_instance->FR6); + INIT_GPIO_PORT_T_FR7(p_obj->p_pt_instance->FR7); + INIT_GPIO_PORT_T_FR8(p_obj->p_pt_instance->FR8); + INIT_GPIO_PORT_T_OD(p_obj->p_pt_instance->OD); + INIT_GPIO_PORT_T_PUP(p_obj->p_pt_instance->PUP); + INIT_GPIO_PORT_T_PDN(p_obj->p_pt_instance->PDN); + INIT_GPIO_PORT_T_IE(p_obj->p_pt_instance->IE); + /* PT Clock Disable */ + PORT_CLOCK_DISABLE_PORTT(TSB_CG_FSYSMENB_IPMENB17); + break; + case GPIO_PORT_U: + INIT_GPIO_PORT_U_DATA(p_obj->p_pu_instance->DATA); + INIT_GPIO_PORT_U_CR(p_obj->p_pu_instance->CR); + INIT_GPIO_PORT_U_FR1(p_obj->p_pu_instance->FR1); + INIT_GPIO_PORT_U_FR2(p_obj->p_pu_instance->FR2); + INIT_GPIO_PORT_U_FR3(p_obj->p_pu_instance->FR3); + INIT_GPIO_PORT_U_FR4(p_obj->p_pu_instance->FR4); + INIT_GPIO_PORT_U_FR5(p_obj->p_pu_instance->FR5); + INIT_GPIO_PORT_U_FR6(p_obj->p_pu_instance->FR6); + INIT_GPIO_PORT_U_FR7(p_obj->p_pu_instance->FR7); + INIT_GPIO_PORT_U_FR8(p_obj->p_pu_instance->FR8); + INIT_GPIO_PORT_U_OD(p_obj->p_pu_instance->OD); + INIT_GPIO_PORT_U_PUP(p_obj->p_pu_instance->PUP); + INIT_GPIO_PORT_U_PDN(p_obj->p_pu_instance->PDN); + INIT_GPIO_PORT_U_IE(p_obj->p_pu_instance->IE); + /* PU Clock Disable */ + PORT_CLOCK_DISABLE_PORTU(TSB_CG_FSYSMENB_IPMENB18); + break; + case GPIO_PORT_V: + INIT_GPIO_PORT_V_DATA(p_obj->p_pv_instance->DATA); + INIT_GPIO_PORT_V_CR(p_obj->p_pv_instance->CR); + INIT_GPIO_PORT_V_FR1(p_obj->p_pv_instance->FR1); + INIT_GPIO_PORT_V_FR2(p_obj->p_pv_instance->FR2); + INIT_GPIO_PORT_V_FR3(p_obj->p_pv_instance->FR3); + INIT_GPIO_PORT_V_FR4(p_obj->p_pv_instance->FR4); + INIT_GPIO_PORT_V_FR5(p_obj->p_pv_instance->FR5); + INIT_GPIO_PORT_V_FR6(p_obj->p_pv_instance->FR6); + INIT_GPIO_PORT_V_FR7(p_obj->p_pv_instance->FR7); + INIT_GPIO_PORT_V_FR8(p_obj->p_pv_instance->FR8); + INIT_GPIO_PORT_V_OD(p_obj->p_pv_instance->OD); + INIT_GPIO_PORT_V_PUP(p_obj->p_pv_instance->PUP); + INIT_GPIO_PORT_V_PDN(p_obj->p_pv_instance->PDN); + INIT_GPIO_PORT_V_IE(p_obj->p_pv_instance->IE); + /* PV Clock Disable */ + PORT_CLOCK_DISABLE_PORTV(TSB_CG_FSYSMENB_IPMENB19); + break; + case GPIO_PORT_W: + INIT_GPIO_PORT_W_DATA(p_obj->p_pw_instance->DATA); + INIT_GPIO_PORT_W_CR(p_obj->p_pw_instance->CR); + INIT_GPIO_PORT_W_FR1(p_obj->p_pw_instance->FR1); + INIT_GPIO_PORT_W_FR2(p_obj->p_pw_instance->FR2); + INIT_GPIO_PORT_W_FR3(p_obj->p_pw_instance->FR3); + INIT_GPIO_PORT_W_FR4(p_obj->p_pw_instance->FR4); + INIT_GPIO_PORT_W_FR5(p_obj->p_pw_instance->FR5); + INIT_GPIO_PORT_W_FR6(p_obj->p_pw_instance->FR6); + INIT_GPIO_PORT_W_FR7(p_obj->p_pw_instance->FR7); + INIT_GPIO_PORT_W_FR8(p_obj->p_pw_instance->FR8); + INIT_GPIO_PORT_W_OD(p_obj->p_pw_instance->OD); + INIT_GPIO_PORT_W_PUP(p_obj->p_pw_instance->PUP); + INIT_GPIO_PORT_W_PDN(p_obj->p_pw_instance->PDN); + INIT_GPIO_PORT_W_IE(p_obj->p_pw_instance->IE); + /* PW Clock Disable */ + PORT_CLOCK_DISABLE_PORTW(TSB_CG_FSYSMENB_IPMENB20); + break; + case GPIO_PORT_Y: + INIT_GPIO_PORT_Y_DATA(p_obj->p_py_instance->DATA); + INIT_GPIO_PORT_Y_CR(p_obj->p_py_instance->CR); + INIT_GPIO_PORT_Y_FR1(p_obj->p_py_instance->FR1); + INIT_GPIO_PORT_Y_FR2(p_obj->p_py_instance->FR2); + INIT_GPIO_PORT_Y_FR3(p_obj->p_py_instance->FR3); + INIT_GPIO_PORT_Y_FR4(p_obj->p_py_instance->FR4); + INIT_GPIO_PORT_Y_FR5(p_obj->p_py_instance->FR5); + INIT_GPIO_PORT_Y_FR6(p_obj->p_py_instance->FR6); + INIT_GPIO_PORT_Y_FR7(p_obj->p_py_instance->FR7); + INIT_GPIO_PORT_Y_FR8(p_obj->p_py_instance->FR8); + INIT_GPIO_PORT_Y_OD(p_obj->p_py_instance->OD); + INIT_GPIO_PORT_Y_PUP(p_obj->p_py_instance->PUP); + INIT_GPIO_PORT_Y_PDN(p_obj->p_py_instance->PDN); + INIT_GPIO_PORT_Y_IE(p_obj->p_py_instance->IE); + /* PY Clock Disable */ + PORT_CLOCK_DISABLE_PORTY(TSB_CG_FSYSMENB_IPMENB21); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_write_mode(gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) + * @brief Port Mode Write + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[in] val :value + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t i; + int32_t param_result = PARAM_NG; + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + WRITE_PORT(mode, p_obj->p_pa_instance, val, PinExistTbl[GPIO_PORT_A][i]); + break; + case GPIO_PORT_B: + WRITE_PORT(mode, p_obj->p_pb_instance, val, PinExistTbl[GPIO_PORT_B][i]); + break; + case GPIO_PORT_C: + WRITE_PORT(mode, p_obj->p_pc_instance, val, PinExistTbl[GPIO_PORT_C][i]); + break; + case GPIO_PORT_D: + WRITE_PORT(mode, p_obj->p_pd_instance, val, PinExistTbl[GPIO_PORT_D][i]); + break; + case GPIO_PORT_E: + WRITE_PORT(mode, p_obj->p_pe_instance, val, PinExistTbl[GPIO_PORT_E][i]); + break; + case GPIO_PORT_F: + WRITE_PORT(mode, p_obj->p_pf_instance, val, PinExistTbl[GPIO_PORT_F][i]); + break; + case GPIO_PORT_G: + WRITE_PORT(mode, p_obj->p_pg_instance, val, PinExistTbl[GPIO_PORT_G][i]); + break; + case GPIO_PORT_H: + WRITE_PORT(mode, p_obj->p_ph_instance, val, PinExistTbl[GPIO_PORT_H][i]); + break; + case GPIO_PORT_J: + WRITE_PORT(mode, p_obj->p_pj_instance, val, PinExistTbl[GPIO_PORT_J][i]); + break; + case GPIO_PORT_K: + WRITE_PORT(mode, p_obj->p_pk_instance, val, PinExistTbl[GPIO_PORT_K][i]); + break; + case GPIO_PORT_L: + WRITE_PORT(mode, p_obj->p_pl_instance, val, PinExistTbl[GPIO_PORT_L][i]); + break; + case GPIO_PORT_M: + WRITE_PORT(mode, p_obj->p_pm_instance, val, PinExistTbl[GPIO_PORT_M][i]); + break; + case GPIO_PORT_N: + WRITE_PORT(mode, p_obj->p_pn_instance, val, PinExistTbl[GPIO_PORT_N][i]); + break; + case GPIO_PORT_P: + WRITE_PORT(mode, p_obj->p_pp_instance, val, PinExistTbl[GPIO_PORT_P][i]); + break; + case GPIO_PORT_R: + WRITE_PORT(mode, p_obj->p_pr_instance, val, PinExistTbl[GPIO_PORT_R][i]); + break; + case GPIO_PORT_T: + WRITE_PORT(mode, p_obj->p_pt_instance, val, PinExistTbl[GPIO_PORT_T][i]); + break; + case GPIO_PORT_U: + WRITE_PORT(mode, p_obj->p_pu_instance, val, PinExistTbl[GPIO_PORT_U][i]); + break; + case GPIO_PORT_V: + WRITE_PORT(mode, p_obj->p_pv_instance, val, PinExistTbl[GPIO_PORT_V][i]); + break; + case GPIO_PORT_W: + WRITE_PORT(mode, p_obj->p_pw_instance, val, PinExistTbl[GPIO_PORT_W][i]); + break; + case GPIO_PORT_Y: + WRITE_PORT(mode, p_obj->p_py_instance, val, PinExistTbl[GPIO_PORT_Y][i]); + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_read_mode(gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) + * @brief Port Mode Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[out] val :Store of value + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t param_result = PARAM_NG; + int32_t i; + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + READ_PORT(mode, p_obj->p_pa_instance, val, PinExistTbl[GPIO_PORT_A][i]); + break; + case GPIO_PORT_B: + READ_PORT(mode, p_obj->p_pb_instance, val, PinExistTbl[GPIO_PORT_B][i]); + break; + case GPIO_PORT_C: + READ_PORT(mode, p_obj->p_pc_instance, val, PinExistTbl[GPIO_PORT_C][i]); + break; + case GPIO_PORT_D: + READ_PORT(mode, p_obj->p_pd_instance, val, PinExistTbl[GPIO_PORT_D][i]); + break; + case GPIO_PORT_E: + READ_PORT(mode, p_obj->p_pe_instance, val, PinExistTbl[GPIO_PORT_E][i]); + break; + case GPIO_PORT_F: + READ_PORT(mode, p_obj->p_pf_instance, val, PinExistTbl[GPIO_PORT_F][i]); + break; + case GPIO_PORT_G: + READ_PORT(mode, p_obj->p_pg_instance, val, PinExistTbl[GPIO_PORT_G][i]); + break; + case GPIO_PORT_H: + READ_PORT(mode, p_obj->p_ph_instance, val, PinExistTbl[GPIO_PORT_H][i]); + break; + case GPIO_PORT_J: + READ_PORT(mode, p_obj->p_pj_instance, val, PinExistTbl[GPIO_PORT_J][i]); + break; + case GPIO_PORT_K: + READ_PORT(mode, p_obj->p_pk_instance, val, PinExistTbl[GPIO_PORT_K][i]); + break; + case GPIO_PORT_L: + READ_PORT(mode, p_obj->p_pl_instance, val, PinExistTbl[GPIO_PORT_L][i]); + break; + case GPIO_PORT_M: + READ_PORT(mode, p_obj->p_pm_instance, val, PinExistTbl[GPIO_PORT_M][i]); + break; + case GPIO_PORT_N: + READ_PORT(mode, p_obj->p_pn_instance, val, PinExistTbl[GPIO_PORT_N][i]); + break; + case GPIO_PORT_P: + READ_PORT(mode, p_obj->p_pp_instance, val, PinExistTbl[GPIO_PORT_P][i]); + break; + case GPIO_PORT_R: + READ_PORT(mode, p_obj->p_pr_instance, val, PinExistTbl[GPIO_PORT_R][i]); + break; + case GPIO_PORT_T: + READ_PORT(mode, p_obj->p_pt_instance, val, PinExistTbl[GPIO_PORT_T][i]); + break; + case GPIO_PORT_U: + READ_PORT(mode, p_obj->p_pu_instance, val, PinExistTbl[GPIO_PORT_U][i]); + break; + case GPIO_PORT_V: + READ_PORT(mode, p_obj->p_pv_instance, val, PinExistTbl[GPIO_PORT_V][i]); + break; + case GPIO_PORT_W: + READ_PORT(mode, p_obj->p_pw_instance, val, PinExistTbl[GPIO_PORT_W][i]); + break; + case GPIO_PORT_Y: + READ_PORT(mode, p_obj->p_py_instance, val, PinExistTbl[GPIO_PORT_Y][i]); + break; + default: + result = TXZ_ERROR; + break; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Port Function switching + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t + * @param inout :GPIO Input/Output.: Use @ref gpio_pininout_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_func(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, uint32_t func, gpio_pininout_t inout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + int32_t param_result = PARAM_NG; + + /* Check the parameters, the NULL of address */ + param_result = check_param_func_pin_exist(p_obj, group, num, func); + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + } else { + switch (group) { + case GPIO_PORT_A: + port_base = (uint32_t)p_obj->p_pa_instance; + break; + case GPIO_PORT_B: + port_base = (uint32_t)p_obj->p_pb_instance; + break; + case GPIO_PORT_C: + port_base = (uint32_t)p_obj->p_pc_instance; + break; + case GPIO_PORT_D: + port_base = (uint32_t)p_obj->p_pd_instance; + break; + case GPIO_PORT_E: + port_base = (uint32_t)p_obj->p_pe_instance; + break; + case GPIO_PORT_F: + port_base = (uint32_t)p_obj->p_pf_instance; + break; + case GPIO_PORT_G: + port_base = (uint32_t)p_obj->p_pg_instance; + break; + case GPIO_PORT_H: + port_base = (uint32_t)p_obj->p_ph_instance; + break; + case GPIO_PORT_J: + port_base = (uint32_t)p_obj->p_pj_instance; + break; + case GPIO_PORT_K: + port_base = (uint32_t)p_obj->p_pk_instance; + break; + case GPIO_PORT_L: + port_base = (uint32_t)p_obj->p_pl_instance; + break; + case GPIO_PORT_M: + port_base = (uint32_t)p_obj->p_pm_instance; + break; + case GPIO_PORT_N: + port_base = (uint32_t)p_obj->p_pn_instance; + break; + case GPIO_PORT_P: + port_base = (uint32_t)p_obj->p_pp_instance; + break; + case GPIO_PORT_R: + port_base = (uint32_t)p_obj->p_pr_instance; + break; + case GPIO_PORT_T: + port_base = (uint32_t)p_obj->p_pt_instance; + break; + case GPIO_PORT_U: + port_base = (uint32_t)p_obj->p_pu_instance; + break; + case GPIO_PORT_V: + port_base = (uint32_t)p_obj->p_pv_instance; + break; + case GPIO_PORT_W: + port_base = (uint32_t)p_obj->p_pw_instance; + break; + case GPIO_PORT_Y: + port_base = (uint32_t)p_obj->p_py_instance; + break; + default: + result = TXZ_ERROR; + break; + } + if (result == TXZ_ERROR) { + return (result); + } + + /* Initialization PxFR OFF */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_CLR(mode_base, num); + + /* Initialize Input/Output */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + + switch (func) { + case 0: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_1: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_2: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_3: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_4: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_5: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case GPIO_FR_6: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_7: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_8: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR8); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + case GPIO_FR_NA: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_NOTINOUT) { + /* No Process */ + } + break; + default: + result = TXZ_ERROR; + return (result); + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Set Pull up mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetPullUp(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PUP) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PUP); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Set Pull down mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetPullDown(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_PDN) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_PDN); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/** + * @brief Set Open drain mode + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_SetOpenDrain(_gpio_t *p_obj, gpio_gr_t group, gpio_num_t num, gpio_pinstate_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t port_base; + uint32_t mode_base; + + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, GPIO_Mode_OD) == PARAM_NG) { + result = TXZ_ERROR; + } else { + port_base = BITBAND_PORT_BASE(group); + + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_OD); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(mode_base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(mode_base, num); + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_write_bit(gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) + * @brief Port Bit Write + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param val :GPIO Pin Reset/Set. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + + /* Check the parameters */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + } else { + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, num); + } else if (val == GPIO_PIN_RESET) { + BITBAND_PORT_CLR(base, num); + } else { + result = TXZ_ERROR; + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/*! + * @fn TXZ_Result gpio_read_bit(gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) + * @brief Port Bit Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + uint32_t val; + + /* Check the parameters */ + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + } else if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + } else { + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + BITBAND_PORT_READ(val, base, num); + if (val == GPIO_PIN_RESET) { + *pinstate = GPIO_PIN_RESET; + } else if (val == GPIO_PIN_SET) { + *pinstate = GPIO_PIN_SET; + } else { + result = TXZ_ERROR; + } + } + + return result; +} + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__GPIO_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_hal.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_hal.c new file mode 100644 index 0000000..6580abc --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_hal.c @@ -0,0 +1,301 @@ +/** + ******************************************************************************* + * @file txz_hal.c + * @brief This file provides API functions for driver common part. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_hal.h" + +#if defined(__HAL_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup HAL + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_macro HAL Private Macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ +/** + * @defgroup wait Configuration + * @brief wait Configuration. + * @{ + */ +#define WAIT_UNIT_1US ((uint32_t)(1000000)) /*!< 1S-1us transfor unit. */ +#define WAIT_FORLOOP_STEPS ((uint32_t)(5)) /*!< for loop steps. */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_ACCR_200MHZ (200000000UL) /*!< 200MHZ */ +#define FC_ACCR_160MHZ (160000000UL) /*!< 160MHZ */ +#define FC_ACCR_120MHZ (120000000UL) /*!< 120MHZ */ +#define FC_ACCR_100MHZ (100000000UL) /*!< 100MHZ */ +#define FC_ACCR_80MHZ ( 80000000UL) /*!< 80MHZ */ +/* FC RACCR setting configration */ +#define FC_RACCR_RAMLC_1CLK (0x00000000UL) /*!< 1clock(less than 160MHZ). */ +#define FC_RACCR_RAMLC_2CLK (0x00000010UL) /*!< 2clock(more than 160MHZ). */ + +/** + * @} + */ /* End of group waitConfiguration */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_define HAL Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_typedef HAL Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group HAL_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup HAL_Private_fuctions HAL Private Fuctions + * @{ + */ + +static uint32_t tick; + +/** + * @} + */ /* End of group HAL_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup HAL_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Increment a tick value. + * @param - + * @retval - + * @note Please call by user. + * @note In the sample, this variable is incremented each 1ms timer interrupt. + */ +/*--------------------------------------------------*/ +void hal_inc_tick(void) +{ + tick++; +} + +/*--------------------------------------------------*/ +/** + * @brief Provides a tick value. + * @param - + * @return Tick value. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +uint32_t hal_get_tick(void) +{ + return (tick); +} + +/*--------------------------------------------------*/ +/** + * @brief wait Function(us) + * @param uint32_t :count(unit:us). + * @return void + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void wait(uint32_t count) +{ + uint32_t i, steps; + + /*-----------------------------------------*/ + /* step : 1000000us = fsys :1 */ + /* step = EOSC_SYS_CLOCK/1000000 */ + /*-----------------------------------------*/ + /* system core clock update */ + SystemCoreClockUpdate(); + steps = count * (SystemCoreClock / WAIT_UNIT_1US) / WAIT_FORLOOP_STEPS; + + for (i = 0; i < steps; ++i) { + __NOP(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief copy 32-bit data from source to dest + * @param the address of source and dast, the data size + * @retval None. + * @note - + */ +/*--------------------------------------------------*/ +void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size) +{ + uint32_t *dest_addr, *source_addr, tmpsize; + uint32_t i, tmps, tmpd, mask; + + dest_addr = dest; + source_addr = source; + + tmpsize = size >> 2U; + for (i = 0U; i < tmpsize; i++) { /* 32bits copy */ + *dest_addr = *source_addr; + dest_addr++; + source_addr++; + } + if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */ + mask = 0xFFFFFF00U; + i = size & 0x00000003U; + tmps = *source_addr; + tmpd = *dest_addr; + while (i - 1U) { + mask = mask << 8U; + i--; + } + tmps = tmps & (~mask); + tmpd = tmpd & (mask); + *dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */ + } else { + /* Do nothing */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief RAM register set. + * @param none. + * @retval none. + * @note - + */ +/*--------------------------------------------------*/ +void fc_ram_con_reg_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock <= FC_ACCR_160MHZ) { /* less than 160MHZ */ + regval = (uint32_t)FC_RACCR_RAMLC_1CLK; + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->RACCR = regval; + while (TSB_FC->RACCR != (uint32_t)FC_RACCR_RAMLC_1CLK) { + } + } else { /* more than 160MHZ */ + regval = (uint32_t)FC_RACCR_RAMLC_2CLK; + + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->RACCR = regval; + while (TSB_FC->RACCR != (uint32_t)FC_RACCR_RAMLC_2CLK) { + /* no processing */ + } + } +} + +/** + * @} + */ /* End of group HAL_Exported_functions */ + +/** + * @} + */ /* End of group HAL */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__HAL_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_i2c.c new file mode 100644 index 0000000..25764be --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_i2c.c @@ -0,0 +1,414 @@ +/** + ******************************************************************************* + * @file txz_i2c.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c.h" + +#if defined(__I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief SCK Divider value table. + * @details SCK = b000 - b111. + * @note NFSEL=0 (Digital Setting) Divider value. +*/ +/*----------------------------------*/ +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528 }; +static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 }; + +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initializing I2C Regester + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE; + p_obj->p_instance->OP = I2CxOP_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->AR = I2CxAR_INIT; + p_obj->p_instance->AR2 = I2CxAR2_INIT; + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); + p_obj->p_instance->IE = I2CxIE_CLEAR; +} + +/*--------------------------------------------------*/ +/** + * @brief Generate start condition + * @param p_obj :I2C object. + * @param data :Slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_start_condition(I2C_t *p_obj, uint32_t data) +{ + __IO uint32_t opreg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + opreg = p_obj->p_instance->OP; + opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); + if (I2C_master(p_obj)) { + if ((p_obj->p_instance->SR & I2CxSR_BB)) { + opreg |= I2CxOP_SREN; + } + } + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->OP = opreg; + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION; +} + +/*--------------------------------------------------*/ +/** + * @brief Return the I2c clock setting + * @param p_obj :I2C object. + * @param frequency :Maximum frequency. + * @param fsys :SystemCoreClock. + * @param p_setting :Clock data pointer. + * @retval Non-zero :Scl frequency. + * @retval 0 :Error. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting) +{ + uint32_t result = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_setting)); +#endif /* #ifdef __DEBUG__ */ + + if (frequency <= 1000000) { + uint64_t sck, tmp_sck; + uint64_t prsck, tmp_prsck; + uint64_t fscl, tmp_fscl; + uint64_t fx; + uint64_t max_fx, min_fx; + uint64_t low_width, low_width_min; + + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + + if (frequency <= 400000) { + max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */ + min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */ + low_width_min = 1600; + } else { + max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */ + min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */ + low_width_min = 675; + } + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)fsys / prsck); + + if ((fx < max_fx) && (fx >= min_fx)) { + for (sck = 0; sck <= 7; sck++) { + low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys; + if (low_width < low_width_min) { + continue; + } + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + + if ((fscl <= frequency) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32) ? prsck : 0; + } + } + } + } + result = (uint32_t)tmp_fscl; + p_setting->sck = (uint32_t)tmp_sck; + p_setting->prsck = (tmp_prsck < 32) ? (uint32_t)tmp_prsck : 0; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Slave mode setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_slave_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->OP = I2CxOP_SLAVE_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck); + p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); +} +#if defined(I2CSxWUP_EN) +/*--------------------------------------------------*/ +/** + * @brief I2C Wakeup Control setting. + * @param p_obj :I2CS object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_init(I2CS_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR1 = (p_obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend); +} + +/*--------------------------------------------------*/ +/** + * @brief Primary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Primary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR2 = (0x0000000E & adr); +} + +/*--------------------------------------------------*/ +/** + * @brief Secondary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Secondary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + p_obj->p_instance->WUPCR3 = (0x0000000E & adr); + p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */ +} +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_i2c_api.c new file mode 100644 index 0000000..33ae60d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_i2c_api.c @@ -0,0 +1,1721 @@ +/** + ******************************************************************************* + * @file i2c_b.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_i2c_api.h" + +#if defined(__BSP_I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name timeout + * @brief This timeouts are not based on accurate values, this just guarantee that + the application will not remain stuck if the I2C communication is corrupted. + * @{ + */ +#define I2C_TIMEOUT (100000) /*>! fail safe. */ + +/** + * @} + */ /* End of name timeout */ + +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +#define I2C_CH0 (0) /*!< I2C Channel 0. */ +#define I2C_CH1 (1) /*!< I2C Channel 1. */ +#define I2C_CH2 (2) /*!< I2C Channel 2. */ +#define I2C_CH3 (3) /*!< I2C Channel 3. */ +#define I2C_CH4 (4) /*!< I2C Channel 3. */ +#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +/*----------------------------------*/ +/** + * @brief Transfer State. +*/ +/*----------------------------------*/ +enum { + I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */ + I2C_TRANSFER_STATE_BUSY /*!< Busy. */ +} TransferState; + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief For IRQn_Type number definition. +*/ +/*----------------------------------*/ +typedef struct { + IRQn_Type i2c; + IRQn_Type al; + IRQn_Type bf; + IRQn_Type na; +} i2c_irq_t; + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief Channel 0 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = { + { INTI2C0NST_IRQn, INTI2C0ATX_IRQn, INTI2C0BRX_IRQn, INTI2C0NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 1 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH1_IRQN_TBL[1] = { + { INTI2C1NST_IRQn, INTI2C1ATX_IRQn, INTI2C1BRX_IRQn, INTI2C1NA_IRQn } +}; + +/*----------------------------------*/ +/** + * @brief Channel 2 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH2_IRQN_TBL[1] = { + { INTI2C2NST_IRQn, INTI2C2ATX_IRQn, INTI2C2BRX_IRQn, INTI2C2NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 3 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH3_IRQN_TBL[1] = { + {INTI2C3NST_IRQn, INTI2C3ATX_IRQn, INTI2C3BRX_IRQn, INTI2C3NA_IRQn} +}; + +/*----------------------------------*/ +/** + * @brief Channel 4 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH4_IRQN_TBL[1] = { + { INTI2C4NST_IRQn, INTI2C4ATX_IRQn, INTI2C4BRX_IRQn, INTI2C4NA_IRQn} +}; +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn); +__STATIC_INLINE int32_t check_param_address(int32_t address); +#endif +__STATIC_INLINE void enable_irq(uint32_t irqn); +__STATIC_INLINE void disable_irq(uint32_t irqn); +__STATIC_INLINE void clear_irq(uint32_t irqn); +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj); +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj); +static void i2c_irq_handler(_i2c_t *p_obj); +static void i2c_slave_irq_handler(_i2c_t *p_obj); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Compare the IRQn's parameter. + * @param irqn :I2C IRQn List. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note -. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn) +{ + int32_t result = I2C_PARAM_NG; + + if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL) { + result = I2C_PARAM_OK; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Compare the Slave address's parameter. + * @param address :Address. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note Here, 10bit address has not supported. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_address(int32_t address) +{ + int32_t result = I2C_PARAM_NG; + + if ((address >= 0) && (address <= 255)) { + result = I2C_PARAM_OK; + } + return (result); +} +#endif + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_EnableIRQ(p_irqn->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_DisableIRQ(p_irqn->i2c); + NVIC_DisableIRQ(p_irqn->al); + NVIC_DisableIRQ(p_irqn->bf); + NVIC_DisableIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief ClearPending I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void clear_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_ClearPendingIRQ(p_irqn->i2c); + NVIC_ClearPendingIRQ(p_irqn->al); + NVIC_ClearPendingIRQ(p_irqn->bf); + NVIC_ClearPendingIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PG2, PG3) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) { + /* Port G */ + + /* SCL */ + TSB_PG_IE_PG3IE = 0; /* Input :Disable */ + TSB_PG_CR_PG3C = 0; /* Output :Disable */ + TSB_PG_OD_PG3OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG3UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG3DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG3 = 0; /* Data :0 */ + TSB_PG_FR7_PG3F7 = 1; /* Function :I2C0SCL */ + TSB_PG_IE_PG3IE = 1; /* Input :Enable */ + TSB_PG_CR_PG3C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PG_IE_PG2IE = 0; /* Input :Disable */ + TSB_PG_CR_PG2C = 0; /* Output :Disable */ + TSB_PG_OD_PG2OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG2UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG2DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG2 = 0; /* Data :0 */ + TSB_PG_FR7_PG2F7 = 1; /* Function :I2C0SDA */ + TSB_PG_IE_PG2IE = 1; /* Input :Enable */ + TSB_PG_CR_PG2C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PF2, PF3) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) { + /* Port F */ + + /* SCL */ + TSB_PF_IE_PF3IE = 0; /* Input :Disable */ + TSB_PF_CR_PF3C = 0; /* Output :Disable */ + TSB_PF_OD_PF3OD = 1; /* OD Control :Open Drain */ + TSB_PF_PUP_PF3UP = 0; /* Pull-up :Disable */ + TSB_PF_PDN_PF3DN = 0; /* Pull-down :Disable */ + TSB_PF_DATA_PF3 = 0; /* Data :0 */ + TSB_PF_FR7_PF3F7 = 1; /* Function :I2C0SCL */ + TSB_PF_IE_PF3IE = 1; /* Input :Enable */ + TSB_PF_CR_PF3C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PF_IE_PF2IE = 0; /* Input :Disable */ + TSB_PF_CR_PF2C = 0; /* Output :Disable */ + TSB_PF_OD_PF2OD = 1; /* OD Control :Open Drain */ + TSB_PF_PUP_PF2UP = 0; /* Pull-up :Disable */ + TSB_PF_PDN_PF2DN = 0; /* Pull-down :Disable */ + TSB_PF_DATA_PF2 = 0; /* Data :0 */ + TSB_PF_FR7_PF2F7 = 1; /* Function :I2C0SDA */ + TSB_PF_IE_PF2IE = 1; /* Input :Enable */ + TSB_PF_CR_PF2C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PG4, PG5) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) { + /* Port G */ + + /* SCL */ + TSB_PG_IE_PG5IE = 0; /* Input :Disable */ + TSB_PG_CR_PG5C = 0; /* Output :Disable */ + TSB_PG_OD_PG5OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG5UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG5DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG5 = 0; /* Data :0 */ + TSB_PG_FR7_PG5F7 = 1; /* Function :I2C0SCL */ + TSB_PG_IE_PG5IE = 1; /* Input :Enable */ + TSB_PG_CR_PG5C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PG_IE_PG4IE = 0; /* Input :Disable */ + TSB_PG_CR_PG4C = 0; /* Output :Disable */ + TSB_PG_OD_PG4OD = 1; /* OD Control :Open Drain */ + TSB_PG_PUP_PG4UP = 0; /* Pull-up :Disable */ + TSB_PG_PDN_PG4DN = 0; /* Pull-down :Disable */ + TSB_PG_DATA_PG4 = 0; /* Data :0 */ + TSB_PG_FR7_PG4F7 = 1; /* Function :I2C0SDA */ + TSB_PG_IE_PG4IE = 1; /* Input :Enable */ + TSB_PG_CR_PG4C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PM0, PM1) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) { + /* Port M */ + + /* SCL */ + TSB_PJ_IE_PJ6IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ6C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ6OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ6UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ6DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ6 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ6F7 = 1; /* Function :I2C3SCL */ + TSB_PJ_IE_PJ6IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ6C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PJ_IE_PJ7IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ7C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ7OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ7UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ7DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ7 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ7F7 = 1; /* Function :I2C3SDA */ + TSB_PJ_IE_PJ7IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ7C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Port Setting (PM6, PM7) + * @param sda :SDA port. + * @param scl :SCL port. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl) +{ + if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) { + /* Port M */ + + /* SCL */ + TSB_PJ_IE_PJ2IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ2C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ2OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ2UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ2DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ2 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ2F7 = 1; /* Function :I2C3SCL */ + TSB_PJ_IE_PJ2IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ2C = 1; /* Output :Enable */ + + /* SDA */ + TSB_PJ_IE_PJ3IE = 0; /* Input :Disable */ + TSB_PJ_CR_PJ3C = 0; /* Output :Disable */ + TSB_PJ_OD_PJ3OD = 1; /* OD Control :Open Drain */ + TSB_PJ_PUP_PJ3UP = 0; /* Pull-up :Disable */ + TSB_PJ_PDN_PJ3DN = 0; /* Pull-down :Disable */ + TSB_PJ_DATA_PJ3 = 0; /* Data :0 */ + TSB_PJ_FR7_PJ3F7 = 1; /* Function :I2C3SDA */ + TSB_PJ_IE_PJ3IE = 1; /* Input :Enable */ + TSB_PJ_CR_PJ3C = 1; /* Output :Enable */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Setting + * @param ch :I2C Channel. + * @param p_irqn :Destination Address of a I2C IRQn List. + * @retval non-zero :Instance Address. + * @retval zero :Channel not supported. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn) +{ + uint32_t instance = 0; + + switch (ch) { + case I2C_CH0: + instance = (uint32_t)TSB_I2C0; + *p_irqn = (uint32_t)&I2C_CH0_IRQN_TBL; + break; + + case I2C_CH1: + instance = (uint32_t)TSB_I2C1; + *p_irqn = (uint32_t)&I2C_CH1_IRQN_TBL; + break; + + case I2C_CH2: + instance = (uint32_t)TSB_I2C2; + *p_irqn = (uint32_t)&I2C_CH2_IRQN_TBL; + break; + + case I2C_CH3: + instance = (uint32_t)TSB_I2C3; + *p_irqn = (uint32_t)&I2C_CH3_IRQN_TBL; + break; + + case I2C_CH4: + instance = (uint32_t)TSB_I2C4; + *p_irqn = (uint32_t)&I2C_CH4_IRQN_TBL; + break; + + default: + break; + } + return (instance); +} + +/*--------------------------------------------------*/ +/** + * @brief Reset Asynch Transfer + * @param p_obj :i2c object + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); + I2C_disable_interrupt(&p_obj->i2c); +} + +__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); +#endif +} +/*--------------------------------------------------*/ +/** + * @brief Waiting i2c status + * @param p_obj :i2c object + * @retval 0 :Success. + * @retval -1 :Failure. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj) +{ + int32_t timeout; + + timeout = I2C_TIMEOUT; + while (!I2C_int_status(&p_obj->i2c)) { + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + (void)dummy; + return (-5); + } + if ((timeout--) == 0) { + return (-1); + } + } + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + (void)dummy; + return (-5); + } + return (0); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + if (I2C_transmitter(&p_obj->i2c)) { + int32_t start = I2C_restart(&p_obj->i2c); + (void)start; + + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if ((p_obj->tx_buff.pos < p_obj->tx_buff.length) || (p_obj->tx_buff.length == 0)) { + if (p_obj->tx_buff.pos == 0) { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } else { + int32_t start = I2C_restart(&p_obj->i2c); + + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_slave_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_slave_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + int32_t start = I2C_slave_detected(&p_obj->i2c); + if (start) { + uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c); + (void)sa; + } + if (I2C_transmitter(&p_obj->i2c)) { + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else { + /* dummy, wait nack */ + I2C_write_data(&p_obj->i2c, 0); + } + } else { + /* error event not be set */ + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_slave_init(&p_obj->i2c); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_enable_irq(_i2c_t *p_obj) +{ + enable_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_disable_irq(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initialize the I2C Driver + * @param p_obj :i2c object. + * @param sda :SDA port. + * @param scl :SCL port. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t instance = 0; + uint32_t irqn = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* ch0 */ + if ((sda == I2C_PORT_PG2) && (scl == I2C_PORT_PG3)) { + set_port_ch0(sda, scl); + instance = set_i2c(I2C_CH0, &irqn); + } + /* ch1 */ + if ((sda == I2C_PORT_PF2) && (scl == I2C_PORT_PF3)) { + set_port_ch1(sda, scl); + instance = set_i2c(I2C_CH1, &irqn); + } + /* ch2 */ + if ((sda == I2C_PORT_PG4) && (scl == I2C_PORT_PG5)) { + set_port_ch2(sda, scl); + instance = set_i2c(I2C_CH2, &irqn); + } + /* ch3 */ + if ((sda == I2C_PORT_PJ6) && (scl == I2C_PORT_PJ7)) { + set_port_ch3(sda, scl); + instance = set_i2c(I2C_CH3, &irqn); + } + /* ch4 */ + if ((sda == I2C_PORT_PJ2) && (scl == I2C_PORT_PJ3)) { + set_port_ch4(sda, scl); + instance = set_i2c(I2C_CH3, &irqn); + } + + if ((instance != 0) && (irqn != 0)) { + disable_irq(irqn); + clear_irq(irqn); + + /* Set irqn table */ + p_obj->info.irqn = irqn; + + /* Set instance */ + p_obj->i2c.p_instance = (TSB_I2C_TypeDef *)instance; + + /* I2C Reset */ + i2c_reset_t(p_obj); + + /* Set Frequency Default at 100KHz */ + if (i2c_frequency_t(p_obj, 100000) == TXZ_SUCCESS) { + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Reset I2C peripheral + * @param p_obj :i2c object. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_reset_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* Software reset */ + I2C_reset(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure the I2C frequency + * @param p_obj :i2c object. + * @param hz :frequency in Hz. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_port_high(&p_obj->i2c)) { + uint32_t fval; + + SystemCoreClockUpdate(); + + fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock); + if (fval != 0) { + //I2C_init(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + p_obj->info.asynch.address = 0; + p_obj->info.asynch.stop = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + p_obj->info.asynch.event = 0; + p_obj->tx_buff.p_buffer = I2C_NULL; + p_obj->tx_buff.length = 0; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = I2C_NULL; + p_obj->rx_buff.length = 0; + p_obj->rx_buff.pos = 0; + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check bus free on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.bus_free = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a start condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure.(now, not use) + * @note Start condition is not generate yet, after this function returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_start_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.start = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a stop condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_stop_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_stop_condition(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + result = TXZ_ERROR; + break; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Address of Read data. + * @param length :Number of the bytes to read. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of read bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (length > 0) { + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U)); + if (result == I2C_ACK) { + /* Read all bytes */ + while (count < length) { + int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1)) ? 0 : 1)); + if (data < 0) { + result = data; + break; + } + p_data[count++] = (uint8_t)data; + } + result = count; + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1) ;//I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Destination address of Write data. + * @param length :Number of the bytes to write. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of write bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, address); + if (result == I2C_ACK) { + /* Write all bytes */ + while (count < length) { + int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]); + if (data < I2C_ACK) { + result = data; + break; + } + } + if (result >= 0) { + result = count; + } + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1); //I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Read one byte + * @param p_obj :i2c object. + * @param last :last acknowledge. + * @retval The read byte (but -1 is timout error). + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last) +{ + int32_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, last); + I2C_write_data(&p_obj->i2c, 0); + result = wait_status(p_obj); + if (result < 0) { + // result = -1; + } else { + result = (int32_t)I2C_read_data(&p_obj->i2c); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Write one byte + * @param p_obj :i2c object. + * @param data :Write data. + * @retval 0 :NACK was received. + * @retval 1 :ACK was received. + * @retval -1 :Timout error. + * @note Macro definition of return values is @ref I2C_ACK. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data) +{ + int32_t result; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + if (p_obj->info.start == 1) { + p_obj->info.start = 0; + if (p_obj->info.bus_free == 1) { + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + p_obj->info.bus_free = 0; + return (-1); + } + } + } + /* Start Condition */ + I2C_start_condition(&p_obj->i2c, (uint32_t)data); + if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c))) { + p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->info.bus_free = 0; + if (I2C_status_arbitration(&p_obj->i2c)) { + return (-5); + } + return (-2); + } + } else { + I2C_write_data(&p_obj->i2c, (uint32_t)data); + } + p_obj->info.bus_free = 0; + result = wait_status(p_obj); + if (result < 0) { + return (result); + } + if (!I2C_get_ack(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Attempts to determine if the I2C bus is already in use + * @param p_obj :i2c object. + * @retval 0 :Non-active. + * @retval 1 :Active. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint8_t i2c_active_t(_i2c_t *p_obj) +{ + uint8_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_status_busy(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @param address :Slave address(7-bit) and last bit is 0. + * @param stop :Stop to be generated after the transfer is done. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and non-blocking function. + * @note Events of this function will be notified on i2c_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = (uint32_t)address; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = (uint32_t)stop; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + if ((tx_length == 0) && (rx_length != 0)) { + I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U)); + } else { + I2C_start_condition(&p_obj->i2c, (uint32_t)address); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note After error event occurred on i2c_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C as slave or master. + * @param p_obj :i2c object. + * @param enable_slave :Enable slave mode. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + disable_irq(p_obj->info.irqn); + + if (enable_slave) { + I2C_slave_init(&p_obj->i2c); + } else { + /* Slave Disable Settings. */ + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + I2C_clear_int_status(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Check to see if the I2C slave has been addressed. + * @param p_obj :i2c object. + * @retval I2C_NO_DATA :The slave has not been addressed. + * @retval I2C_READ_ADDRESSED :Read addresses. + * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support). + * @retval I2C_WRITE_ADDRESSED :Write addressed. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_receive_t(_i2c_t *p_obj) +{ + int32_t result = I2C_NO_DATA; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_slave_detected(&p_obj->i2c)) { + uint32_t sa = I2C_read_data(&p_obj->i2c); + (void)sa; + + if (!I2C_transmitter(&p_obj->i2c)) { + result = I2C_WRITE_ADDRESSED; + } else { + result = I2C_READ_ADDRESSED; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data. + * @param p_obj :i2c object. + * @param p_data :Destination address of read data. + * @param length :Number of bytes to read. + * @retval Number of read bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Read all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, ((count < (length - 1)) ? 0 : 1)); + I2C_write_data(&p_obj->i2c, 0); + if (wait_status(p_obj) < 0) { + break; + } + if (I2C_slave_detected(&p_obj->i2c)) { + return (count); + } + p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data. + * @param p_obj :i2c object. + * @param p_data :Source address of write data. + * @param length :Number of bytes to write. + * @retval Number of written bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Write all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]); + if (wait_status(p_obj) < 0) { + break; + } + if (!I2C_get_ack(&p_obj->i2c)) { + /* continue */ + } else { + break; + } + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C slave address. + * @param p_obj :i2c object. + * @param address :Address to be set. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address((int32_t)address)); +#endif /* #ifdef DEBUG */ + + I2C_set_address(&p_obj->i2c, address); +} + + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Slave and non-blocking function. + * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = 0; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = 0; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_slave_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note For a non-blocking function. + * @note After error event occurred on i2c_slave_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + I2C_slave_init(&p_obj->i2c); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__BSP_I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_t32a.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_t32a.c new file mode 100644 index 0000000..6e2dd55 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_t32a.c @@ -0,0 +1,1998 @@ +/** +******************************************************************************* +* @file txz_t32a.c +* @brief This file provides API functions for T32A driver. +* @version V1.0.0 +* +* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +* +* Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +******************************************************************************* +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_t32a.h" + +#if defined(__T32A_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup T32A + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ +/** + * @} + */ /* End of group T32A_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_typedef T32A Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Private_member T32A Private Member + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_member */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_fuctions TSPI Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__INLINE static int32_t check_param_mode_halt(uint32_t param); +__INLINE static int32_t check_param_mode_mode32(uint32_t param); +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param); +__INLINE static int32_t check_param_runx_sftstax(uint32_t param); +__INLINE static int32_t check_param_runx_runx(uint32_t param); +__INLINE static int32_t check_param_crx_prsclx(uint32_t param); +__INLINE static int32_t check_param_crx_clkx(uint32_t param); +__INLINE static int32_t check_param_crx_wbfx(uint32_t param); +__INLINE static int32_t check_param_crx_updnx(uint32_t param); +__INLINE static int32_t check_param_crx_reldx(uint32_t param); +__INLINE static int32_t check_param_crx_stopx(uint32_t param); +__INLINE static int32_t check_param_crx_startx(uint32_t param); +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param); +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param); +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param); +__INLINE static int32_t check_param_reldx_reld(uint32_t param); +__INLINE static int32_t check_param_imx_imsterr(uint32_t param); +__INLINE static int32_t check_param_imx_imufx(uint32_t param); +__INLINE static int32_t check_param_imx_imofx(uint32_t param); +__INLINE static int32_t check_param_imx_imx1(uint32_t param); +__INLINE static int32_t check_param_imx_imx0(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param); +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param); +#endif + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Mode HALT's parameter. + * @param param :Mode HALT's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_HALT + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_halt(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DBG_HALT_RUN: + case T32A_DBG_HALT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Mode mode32's parameter. + * @param param :Mode mode32's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_MODE32 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_mode32(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_MODE_16: + case T32A_MODE_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW Counter STOP Control's parameter. + * @param param :SW Counter STOP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_STOP: + case T32A_COUNT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW START Control's parameter. + * @param param :SW START Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTAx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstax(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_START: + case T32A_COUNT_START: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A RUN Disable/Enable Control's parameter. + * @param param :T32A RUN Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_runx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RUN_DISABLE: + case T32A_RUN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_prsclx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PRSCLx_1: + case T32A_PRSCLx_2: + case T32A_PRSCLx_8: + case T32A_PRSCLx_32: + case T32A_PRSCLx_128: + case T32A_PRSCLx_256: + case T32A_PRSCLx_512: + case T32A_PRSCLx_1024: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CLKx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_clkx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CLKx_PRSCLx: + case T32A_CLKx_INTRG: + case T32A_CLKx_TIM_RISING_EDGE: + case T32A_CLKx_TIM_TRAILING_EDGE: + case T32A_CLKx_EXTTRG_RISING_EDGE: + case T32A_CLKx_EXTTRG_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Double Buffer Disable/Enable Control's parameter. + * @param param :Double Buffer Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_WBFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_wbfx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_WBF_DISABLE: + case T32A_WBF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Up/Down Control's parameter. + * @param param :T32A Counter Up/Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_UPDNx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_updnx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_UP: + case T32A_COUNT_DOWN: + case T32A_COUNT_UPDOWN: + case T32A_COUNT_PLS: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Control's parameter. + * @param param :T32A Counter Reload Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELDx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_reldx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RELOAD_NON: + case T32A_RELOAD_INTRG: + case T32A_RELOAD_EXTTRG_RISING_EDGE: + case T32A_RELOAD_EXTTRG_TRAILING_EDGE: + case T32A_RELOAD_TIM_RISING_EDGE: + case T32A_RELOAD_TIM_TRAILING_EDGE: + case T32A_RELOAD_SYNC: + case T32A_RELOAD_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Stop Control's parameter. + * @param param :T32A Counter Stop Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STOPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_stopx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_STOP_NON: + case T32A_STOP_INTRG: + case T32A_STOP_EXTTRG_RISING_EDGE: + case T32A_STOP_EXTTRG_TRAILING_EDGE: + case T32A_STOP_TIM_RISING_EDGE: + case T32A_STOP_TIM_TRAILING_EDGE: + case T32A_STOP_SYNC: + case T32A_STOP_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Start Control's parameter. + * @param param :T32A Counter Start Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STARTx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_startx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_START_NON: + case T32A_START_INTRG: + case T32A_START_EXTTRG_RISING_EDGE: + case T32A_START_EXTTRG_TRAILING_EDGE: + case T32A_START_TIM_RISING_EDGE: + case T32A_START_TIM_TRAILING_EDGE: + case T32A_START_SYNC: + result = PARAM_OK; + break; + case T32A_START_Rsvd: + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control's parameter. + * @param param :T32AxOUTA Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCR_DISABLE: + case T32A_OCR_SET: + case T32A_OCR_CLR: + case T32A_OCR_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx1_DISABLE: + case T32A_OCRCAPx1_SET: + case T32A_OCRCAPx1_CLR: + case T32A_OCRCAPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx0_DISABLE: + case T32A_OCRCAPx0_SET: + case T32A_OCRCAPx0_CLR: + case T32A_OCRCAPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx1_DISABLE: + case T32A_OCRCMPx1_SET: + case T32A_OCRCMPx1_CLR: + case T32A_OCRCMPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx0_DISABLE: + case T32A_OCRCMPx0_SET: + case T32A_OCRCMPx0_CLR: + case T32A_OCRCMPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A1's parameter. + * @param param :T32A Capture Control Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx1_DISABLE: + case T32A_CAPMx1_INTRG: + case T32A_CAPMx1_INx0_RISING_EDGE: + case T32A_CAPMx1_INx0_TRAILING_EDGE: + case T32A_CAPMx1_INx1_RISING_EDGE: + case T32A_CAPMx1_INx1_TRAILING_EDGE: + case T32A_CAPMx1_TIM_RISING_EDGE: + case T32A_CAPMx1_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A0's parameter. + * @param param :T32A Capture Control Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx0_DISABLE: + case T32A_CAPMx0_INTRG: + case T32A_CAPMx0_INx0_RISING_EDGE: + case T32A_CAPMx0_INx0_TRAILING_EDGE: + case T32A_CAPMx0_INx1_RISING_EDGE: + case T32A_CAPMx0_INx1_TRAILING_EDGE: + case T32A_CAPMx0_TIM_RISING_EDGE: + case T32A_CAPMx0_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A0's parameter. + * @param param :T32A Timer Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx0_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A1's parameter. + * @param param :T32A Timer Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx1_MASK) { + result = PARAM_OK; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Register A's parameter. + * @param param :T32A Counter Reload Register A's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELD + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_reldx_reld(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RELDx_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Statuserr Interrupt Request MASK's parameter. + * @param param :T32A Statuserr Interrupt Request MASK's parameter. + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMSTEER + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imsterr(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMSTERR_MASK_NOREQ: + case T32A_IMSTERR_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMUFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imufx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMOFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imofx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx1_MASK_NOREQ: + case T32A_IMx1_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx0_MASK_NOREQ: + case T32A_IMx0_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA Converter1 Request control's parameter. + * @param param :T32A DMA Converter1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx2 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx2_DISABLE: + case T32A_DMAENx2_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture1 Request control's parameter. + * @param param :T32A DMA InputCapture1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx1_DISABLE: + case T32A_DMAENx1_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture0 Request control's parameter. + * @param param :T32A DMA InputCapture0 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx0_DISABLE: + case T32A_DMAENx0_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count Down Control's parameter. + * @param param :T32A Pulse Mode Count Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDN + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDN_NON0: + case T32A_PDN_NON1: + case T32A_PDN_INC0_RISING_EDGE: + case T32A_PDN_INC0_TRAILING_EDGE: + case T32A_PDN_INC1_RISING_EDGE: + case T32A_PDN_INC1_TRAILING_EDGE: + case T32A_PDN_INC0_BOTH_EDGE: + case T32A_PDN_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count UP Control's parameter. + * @param param :T32A Pulse Mode Count UP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PUP + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PUP_NON0: + case T32A_PUP_NON1: + case T32A_PUP_INC0_RISING_EDGE: + case T32A_PUP_INC0_TRAILING_EDGE: + case T32A_PUP_INC1_RISING_EDGE: + case T32A_PUP_INC1_TRAILING_EDGE: + case T32A_PUP_INC0_BOTH_EDGE: + case T32A_PUP_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Noise Filter control's parameter. + * @param param :T32A Noise Filter control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_NF + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_NF_NON: + case T32A_NF_2: + case T32A_NF_4: + case T32A_NF_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Phase 2 Pulse Direction control's parameter. + * @param param :T32A Phase 2 Pulse Direction control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDIR + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDIR_FORWARD: + case T32A_PDIR_BACKWARD: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Count Mode control's parameter. + * @param param :T32A Pulse Count Mode control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PMODE + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PMODE_PHASE_2: + case T32A_PMODE_PHASE_1: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + + + +#endif +/** + * @} + */ /* End of group T32A_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_functions + + */ +/*--------------------------------------------------*/ +/** + * @brief Mode Initialize the T32A object. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_mode_init(t32a_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); +#endif /* __DEBUG__ */ + /* Timer Mode Set */ + p_obj->p_instance->MOD = 0; + p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Initialize the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter of TimerA Mode Set */ + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); + /* Check the parameter of TimerA Run Control Set */ + check_param_runx_sftstpx(p_obj->init[type].runx.sftstp); + check_param_runx_sftstax(p_obj->init[type].runx.sftsta); + check_param_runx_runx(p_obj->init[type].runx.run); + /* Check the parameter of Counter Register Control Set */ + check_param_crx_prsclx(p_obj->init[type].crx.prscl); + check_param_crx_clkx(p_obj->init[type].crx.clk); + check_param_crx_wbfx(p_obj->init[type].crx.wbf); + check_param_crx_updnx(p_obj->init[type].crx.updn); + check_param_crx_reldx(p_obj->init[type].crx.reld); + check_param_crx_stopx(p_obj->init[type].crx.stop); + check_param_crx_startx(p_obj->init[type].crx.start); + /* Check the parameter of TimerA Output Control Set */ + check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr); + /* Check the parameter of T32AxOUTA Control Set */ + check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1); + check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0); + check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1); + check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0); + /* Check the parameter of Capture Control Set */ + check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1); + check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0); + /* Check the parameter of T32A Timer Register 0 Set */ + check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0); + /* Check the parameter of T32A Timer Register 1 Set */ + check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1); + /* Check the parameter of T32A Counter Reload Register Set */ + check_param_reldx_reld(p_obj->init[type].reldx.reld); + /* Check the parameter of Interrupt mask register Set */ + check_param_imx_imsterr(p_obj->init[type].imx.imsterr); + check_param_imx_imufx(p_obj->init[type].imx.imuf); + check_param_imx_imofx(p_obj->init[type].imx.imof); + check_param_imx_imx1(p_obj->init[type].imx.imx1); + check_param_imx_imx0(p_obj->init[type].imx.imx0); + /* Check the parameter of DMA Request register Set */ + check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2); + check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1); + check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0); +#endif + + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerA Run Control Disable */ + p_obj->p_instance->RUNA = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRA = 0; + p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerA Output Control Set */ + p_obj->p_instance->OUTCRA0 = 0; + p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTA Control Set */ + p_obj->p_instance->OUTCRA1 = 0; + p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register A0 Set */ + p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register A1 Set */ + p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDA = 0; + p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMA = 0; + p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAA = 0; + p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerA Run Control Set */ + p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERB: + /* Timer B */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerB Run Control Disable */ + p_obj->p_instance->RUNB = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRB = 0; + p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerB Output Control Set */ + p_obj->p_instance->OUTCRB0 = 0; + p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTB Control Set */ + p_obj->p_instance->OUTCRB1 = 0; + p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register B0 Set */ + p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register B1 Set */ + p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDB = 0; + p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMB = 0; + p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAB = 0; + p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerB Run Control Set */ + p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERC: + /* Timer C */ + if (p_obj->init_mode.mode.mode != T32A_MODE_32) { + result = TXZ_ERROR; + return (result); + } + /* TimerC Run Control Disable */ + p_obj->p_instance->RUNC = 0; +#ifdef __DEBUG__ + /* Pulse Count Control register Set */ + check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn); + check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup); + check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf); + check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir); + check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode); +#endif + /* Counter Register Control Set */ + p_obj->p_instance->CRC = 0; + p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerC Output Control Set */ + p_obj->p_instance->OUTCRC0 = 0; + p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTC Control Set */ + p_obj->p_instance->OUTCRC1 = 0; + p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register C0 Set */ + p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register C1 Set */ + p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDC = 0; + p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld; + /* TimerC Capture Control Set */ + p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMC = 0; + p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAC = 0; + p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* Pulse Count Control register Set */ + p_obj->p_instance->PLSCR = 0; + p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \ + p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode); + /* TimerC Run Control Set */ + p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* Timer C */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A RUN */ + p_obj->p_instance->RUNA |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer B RUN */ + p_obj->p_instance->RUNB |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C RUN */ + p_obj->p_instance->RUNC |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A Stop */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B Stop */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* SW Counter Stop & Timer C Stop */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A SW Counter start */ + p_obj->p_instance->RUNA |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer SW Counter start */ + p_obj->p_instance->RUNB |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C SW Counter start */ + p_obj->p_instance->RUNC |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* TimerA SW Counter Stop */ + p_obj->p_instance->RUNA = T32A_COUNT_STOP; + break; + case T32A_TIMERB: + /* Timer B SW Counter Stop */ + p_obj->p_instance->RUNB = T32A_COUNT_STOP; + break; + case T32A_TIMERC: + /* Timer C SW Counter Stop */ + p_obj->p_instance->RUNC = T32A_COUNT_STOP; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Setting + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param num :T32A Register Number. : Use @ref t32_regnum_t + * @param value :Setting Value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (num == T32A_REG0) { + p_obj->p_instance->RGA0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGA1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDA = value; + } + break; + case T32A_TIMERB: + /* Timer B */ + if (num == T32A_REG0) { + p_obj->p_instance->RGB0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGB1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDB = value; + } + break; + case T32A_TIMERC: + /* Timer C */ + if (num == T32A_REG0) { + p_obj->p_instance->RGC0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGC1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDC = value; + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Read + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param p_val :Save area for register value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val) +{ + TXZ_Result result = TXZ_SUCCESS; + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_val = p_obj->p_instance->TMRA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_val = p_obj->p_instance->TMRB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_val = p_obj->p_instance->TMRC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. | + * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. | + * + * @param p_obj :T32A object. + * @param p_status :Save area for status. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_status = p_obj->p_instance->STA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_status = p_obj->p_instance->STB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_status = p_obj->p_instance->STC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for Timer interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Calculate timer value to set timer register. + * @param p_value: time value store pointer. + * @param time: The require period which the uint is us. + * @param prescaler: System Clock Freq + * @param prscl: Select the division for source clock @ref T32A_PRSCLx. + * @retval the value set to Tmrb timer register. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) +{ + TXZ_Result result = TXZ_SUCCESS; + uint64_t denominator; + uint64_t numerator; + uint32_t div; + + /* div */ + switch (prscl) { + case T32A_PRSCLx_1: + div = 1; + break; + case T32A_PRSCLx_2: + div = 2; + break; + case T32A_PRSCLx_8: + div = 8; + break; + case T32A_PRSCLx_32: + div = 32; + break; + case T32A_PRSCLx_128: + div = 128; + break; + case T32A_PRSCLx_256: + div = 256; + break; + case T32A_PRSCLx_512: + div = 512; + break; + case T32A_PRSCLx_1024: + div = 1024; + break; + default: + div = 1; + break; + } + /*-----------------------------------------------*/ + /* "1"counter (s) = 1 / fs */ + /* "1"counter (s) = 1 / (prescaler / div) */ + /* "1"counter (us) = (10^6) / (prescaler / div) */ + /* "1"counter (us) = ((10^6) * div)/prescaler */ + /* "x"counter (us) = time */ + /*-----------------------------------------------*/ + /* x : time = 1 : ((10^6) * div)/prescaler */ + /*-----------------------------------------------*/ + /* x = time / (((10^6) * div)/prescaler) */ + /* = (prescaler * time) / ((10^6) * div) */ + /*-----------------------------------------------*/ + denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time)); + numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div); + denominator = (uint64_t)(denominator / numerator); + /* result */ + if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF))) { + result = TXZ_ERROR; + } else { + *p_value = (uint32_t)denominator; + } + + return (result); +} + +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__T32A_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_tspi.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_tspi.c new file mode 100644 index 0000000..b5c01cf --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_tspi.c @@ -0,0 +1,2895 @@ +/** + ******************************************************************************* + * @file txz_tspi.c + * @brief This file provides API functions for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_tspi.h" + +#if defined(__TSPI_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup TSPI + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ +/** + * @name TSPI NULL Pointer + * @brief Null Pointer for TSPI + * @{ + */ +#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ +/** + * @} + */ /* End of name TSPI NULL Pointer */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name FIFO Max Num. + * @brief Transfer's/Receive's FIFO Max Num. + * @{ + */ +#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ +#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ +/** + * @} + */ /* End of name FIFO Max Num */ + +/** + * @name TSPIxDR_MASK Macro Definition. + * @brief TSPIxDR_MASK Macro Definition. + * @{ + */ +/* DR */ +#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of name TSPIxDR_MASK Macro Definition */ + +/** + * @name TSPI _DATA_LENGTH Macro Definition. + * @brief TSPI DATA LENGTH Macro Definition. + * @{ + */ +#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ +#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ +#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ +#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ +#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ +#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ +#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ +#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ +#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ +#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ +#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ +#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ +#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ +#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ +#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ +#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ +#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ +#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ +#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ +#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ +#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ +#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ +#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ +#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ +#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ +/** + * @} + */ /* End of name TSPI _DATA_LENGTH Macro Definition */ +/** + * @} + */ /* End of group TSPI_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group TSPI_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_typedef TSPI Private Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief TSPI mask array. +*/ +/*----------------------------------*/ +static uint32_t mask[32] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TSPI_DR_8BIT_MASK, + TSPI_DR_9BIT_MASK, + TSPI_DR_10BIT_MASK, + TSPI_DR_11BIT_MASK, + TSPI_DR_12BIT_MASK, + TSPI_DR_13BIT_MASK, + TSPI_DR_14BIT_MASK, + TSPI_DR_15BIT_MASK, + TSPI_DR_16BIT_MASK, + TSPI_DR_17BIT_MASK, + TSPI_DR_18BIT_MASK, + TSPI_DR_19BIT_MASK, + TSPI_DR_20BIT_MASK, + TSPI_DR_21BIT_MASK, + TSPI_DR_22BIT_MASK, + TSPI_DR_23BIT_MASK, + TSPI_DR_24BIT_MASK, + TSPI_DR_25BIT_MASK, + TSPI_DR_26BIT_MASK, + TSPI_DR_27BIT_MASK, + TSPI_DR_28BIT_MASK, + TSPI_DR_29BIT_MASK, + TSPI_DR_30BIT_MASK, + TSPI_DR_31BIT_MASK +}; + +/** + * @} + */ /* End of group TSPI_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_fuctions TSPI Private Fuctions + * @{ + */ + +#ifdef __DEBUG__ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param); +__INLINE static int32_t check_param_trgen_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); +__INLINE static int32_t check_param_transmit_master(uint32_t param); +__INLINE static int32_t check_param_transmit_mode(uint32_t param); +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param); +__INLINE static int32_t check_param_frame_range(uint32_t param); +__INLINE static int32_t check_param_idle_imp(uint32_t param); +__INLINE static int32_t check_param_underrun_imp(uint32_t param); +__INLINE static int32_t check_param_rxdly_value(uint32_t param); +__INLINE static int32_t check_param_tx_fill_level(uint32_t param); +__INLINE static int32_t check_param_rx_fill_level(uint32_t param); +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_err_int(uint32_t param); +__INLINE static int32_t check_param_tx_dma_int(uint32_t param); +__INLINE static int32_t check_param_rx_dma_int(uint32_t param); +__INLINE static int32_t check_param_input_clock(uint32_t param); +__INLINE static int32_t check_param_input_divider(uint32_t param); +__INLINE static int32_t check_param_data_direction(uint32_t param); +__INLINE static int32_t check_param_frame_length(uint32_t param); +__INLINE static int32_t check_param_frame_interval(uint32_t param); +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param); +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param); +__INLINE static int32_t check_param_min_idle_time(uint32_t param); +__INLINE static int32_t check_param_clock_delay(uint32_t param); +__INLINE static int32_t check_param_negate_delay(uint32_t param); +__INLINE static int32_t check_param_parity_enable(uint32_t param); +__INLINE static int32_t check_param_parity_bit(uint32_t param); +__INLINE static int32_t check_param_sect_mode(uint32_t param); +__INLINE static int32_t check_param_sectl0_value(uint32_t param); +__INLINE static int32_t check_param_sectl1_value(uint32_t param); +__INLINE static int32_t check_param_sectl2_value(uint32_t param); +__INLINE static int32_t check_param_sectl3_value(uint32_t param); +#endif + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit frame infinity Enable's parameter. + * @param param :Transmit frame infinity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Infinity_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INF_DISABLE: + case TSPI_INF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Trgen Enable's parameter. + * @param param :Trgen Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Trigger_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_trgen_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRGEN_DISABLE: + case TSPI_TRGEN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Enable's parameter. + * @param param :Transmit Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRXE_DISABLE: + case TSPI_TRXE_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Mode's parameter. + * @param param :Transmit Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SPI_MODE: + case TSPI_SIO_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Master/Slave parameter. + * @param param :Transmit Master/Slave parameter (Only support Master mode) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Operation_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_master(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MASTER_OPERATION: + case TSPI_SLAVE_OPERATION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transfer Mode's parameter. + * @param param :Transfer Mode's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TWO_WAY: + case TSPI_TX_ONLY: + case TSPI_RX_ONLY: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Sel Select's parameter. + * @param param :Transmit Sel Select's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_CSSEL_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_ENABLE: + case TSPI_TSPIxCS1_ENABLE: + case TSPI_TSPIxCS2_ENABLE: + case TSPI_TSPIxCS3_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Frame Range's parameter. + * @param param :TransmitFrame Range's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Frame_Range + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_range(uint32_t param) + +{ + int32_t result = PARAM_NG; + + if ((TSPI_TRANS_RANGE_CONTINUE == param) || (TSPI_TRANS_RANGE_SINGLE == param) || (param <= TSPI_TRANS_RANGE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the IDLE Output Value's parameter. + * @param param :IDLE Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_IDLE_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TIDLE_Hiz: + case TSPI_TIDLE_LAST_DATA: + case TSPI_TIDLE_LOW: + case TSPI_TIDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_underrun_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TXDEMP_LOW: + case TSPI_TXDEMP_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rxdly_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RXDLY_1CLK: + case TSPI_RXDLY_2CLK: + case TSPI_RXDLY_3CLK: + case TSPI_RXDLY_4CLK: + case TSPI_RXDLY_5CLK: + case TSPI_RXDLY_6CLK: + case TSPI_RXDLY_7CLK: + case TSPI_RXDLY_8CLK: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level's parameter. + * @param param :Tx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FILL_LEVEL_0: + case TSPI_TX_FILL_LEVEL_1: + case TSPI_TX_FILL_LEVEL_2: + case TSPI_TX_FILL_LEVEL_3: + case TSPI_TX_FILL_LEVEL_4: + case TSPI_TX_FILL_LEVEL_5: + case TSPI_TX_FILL_LEVEL_6: + case TSPI_TX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FILL_LEVEL_1: + case TSPI_RX_FILL_LEVEL_2: + case TSPI_RX_FILL_LEVEL_3: + case TSPI_RX_FILL_LEVEL_4: + case TSPI_RX_FILL_LEVEL_5: + case TSPI_RX_FILL_LEVEL_6: + case TSPI_RX_FILL_LEVEL_7: + case TSPI_RX_FILL_LEVEL_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FIFO_INT_DISABLE: + case TSPI_TX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_INT_DISABLE: + case TSPI_TX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFIFOInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FIFO_INT_DISABLE: + case TSPI_RX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_INT_DISABLE: + case TSPI_RX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ErrorInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_err_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_ERR_INT_DISABLE: + case TSPI_ERR_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx DMA Interrupt's parameter. + * @param param :Tx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_DMA_INT_DISABLE: + case TSPI_TX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx DMA Interrupt's parameter. + * @param param :Rx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_DMA_INT_DISABLE: + case TSPI_RX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Input Clock's parameter. + * @param param :Input Clock's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_clock(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_CLOCK_0: + case TSPI_BR_CLOCK_1: + case TSPI_BR_CLOCK_2: + case TSPI_BR_CLOCK_4: + case TSPI_BR_CLOCK_8: + case TSPI_BR_CLOCK_16: + case TSPI_BR_CLOCK_32: + case TSPI_BR_CLOCK_64: + case TSPI_BR_CLOCK_128: + case TSPI_BR_CLOCK_256: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Baudrate Divider's parameter. + * @param param :Baudrate Divider's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_divider(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_DIVIDER_16: + case TSPI_BR_DIVIDER_1: + case TSPI_BR_DIVIDER_2: + case TSPI_BR_DIVIDER_3: + case TSPI_BR_DIVIDER_4: + case TSPI_BR_DIVIDER_5: + case TSPI_BR_DIVIDER_6: + case TSPI_BR_DIVIDER_7: + case TSPI_BR_DIVIDER_8: + case TSPI_BR_DIVIDER_9: + case TSPI_BR_DIVIDER_10: + case TSPI_BR_DIVIDER_11: + case TSPI_BR_DIVIDER_12: + case TSPI_BR_DIVIDER_13: + case TSPI_BR_DIVIDER_14: + case TSPI_BR_DIVIDER_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_DIRECTION_LSB: + case TSPI_DATA_DIRECTION_MSB: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter (Only support 8bit DATA) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_length(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_LENGTH_8: + case TSPI_DATA_LENGTH_9: + case TSPI_DATA_LENGTH_10: + case TSPI_DATA_LENGTH_11: + case TSPI_DATA_LENGTH_12: + case TSPI_DATA_LENGTH_13: + case TSPI_DATA_LENGTH_14: + case TSPI_DATA_LENGTH_15: + case TSPI_DATA_LENGTH_16: + case TSPI_DATA_LENGTH_17: + case TSPI_DATA_LENGTH_18: + case TSPI_DATA_LENGTH_19: + case TSPI_DATA_LENGTH_20: + case TSPI_DATA_LENGTH_21: + case TSPI_DATA_LENGTH_22: + case TSPI_DATA_LENGTH_23: + case TSPI_DATA_LENGTH_24: + case TSPI_DATA_LENGTH_25: + case TSPI_DATA_LENGTH_26: + case TSPI_DATA_LENGTH_27: + case TSPI_DATA_LENGTH_28: + case TSPI_DATA_LENGTH_29: + case TSPI_DATA_LENGTH_30: + case TSPI_DATA_LENGTH_31: + case TSPI_DATA_LENGTH_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Frame Interval's parameter. + * @param param :Frame Interval's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Frame_Interval_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_interval(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INTERVAL_TIME_0: + case TSPI_INTERVAL_TIME_1: + case TSPI_INTERVAL_TIME_2: + case TSPI_INTERVAL_TIME_3: + case TSPI_INTERVAL_TIME_4: + case TSPI_INTERVAL_TIME_5: + case TSPI_INTERVAL_TIME_6: + case TSPI_INTERVAL_TIME_7: + case TSPI_INTERVAL_TIME_8: + case TSPI_INTERVAL_TIME_9: + case TSPI_INTERVAL_TIME_10: + case TSPI_INTERVAL_TIME_11: + case TSPI_INTERVAL_TIME_12: + case TSPI_INTERVAL_TIME_13: + case TSPI_INTERVAL_TIME_14: + case TSPI_INTERVAL_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS3 Polarity's parameter. + * @param param :TTSPIxCS3 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS3_NEGATIVE: + case TSPI_TSPIxCS3_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS2 Polarity's parameter. + * @param param :TTSPIxCS2 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS2_NEGATIVE: + case TSPI_TSPIxCS2_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS1 Polarity's parameter. + * @param param :TTSPIxCS1 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS1_NEGATIVE: + case TSPI_TSPIxCS1_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS0 Polarity's parameter. + * @param param :TTSPIxCS0 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_NEGATIVE: + case TSPI_TSPIxCS0_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Polarity's parameter. + * @param param :Serial Clock Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_1ST_EDGE: + case TSPI_SERIAL_CK_2ND_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock IDLE Polarity's parameter. + * @param param :Serial Clock IDLE Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_IDLE_LOW: + case TSPI_SERIAL_CK_IDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Minimum IDLE Time's parameter. + * @param param :Minimum IDLE Time's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Minimum_IDLE_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_min_idle_time(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MIN_IDLE_TIME_1: + case TSPI_MIN_IDLE_TIME_2: + case TSPI_MIN_IDLE_TIME_3: + case TSPI_MIN_IDLE_TIME_4: + case TSPI_MIN_IDLE_TIME_5: + case TSPI_MIN_IDLE_TIME_6: + case TSPI_MIN_IDLE_TIME_7: + case TSPI_MIN_IDLE_TIME_8: + case TSPI_MIN_IDLE_TIME_9: + case TSPI_MIN_IDLE_TIME_10: + case TSPI_MIN_IDLE_TIME_11: + case TSPI_MIN_IDLE_TIME_12: + case TSPI_MIN_IDLE_TIME_13: + case TSPI_MIN_IDLE_TIME_14: + case TSPI_MIN_IDLE_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Delay's parameter. + * @param param :Serial Clock Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_DELAY_1: + case TSPI_SERIAL_CK_DELAY_2: + case TSPI_SERIAL_CK_DELAY_3: + case TSPI_SERIAL_CK_DELAY_4: + case TSPI_SERIAL_CK_DELAY_5: + case TSPI_SERIAL_CK_DELAY_6: + case TSPI_SERIAL_CK_DELAY_7: + case TSPI_SERIAL_CK_DELAY_8: + case TSPI_SERIAL_CK_DELAY_9: + case TSPI_SERIAL_CK_DELAY_10: + case TSPI_SERIAL_CK_DELAY_11: + case TSPI_SERIAL_CK_DELAY_12: + case TSPI_SERIAL_CK_DELAY_13: + case TSPI_SERIAL_CK_DELAY_14: + case TSPI_SERIAL_CK_DELAY_15: + case TSPI_SERIAL_CK_DELAY_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Negate Delay's parameter. + * @param param :Negate Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Negate_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_negate_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_NEGATE_1: + case TSPI_NEGATE_2: + case TSPI_NEGATE_3: + case TSPI_NEGATE_4: + case TSPI_NEGATE_5: + case TSPI_NEGATE_6: + case TSPI_NEGATE_7: + case TSPI_NEGATE_8: + case TSPI_NEGATE_9: + case TSPI_NEGATE_10: + case TSPI_NEGATE_11: + case TSPI_NEGATE_12: + case TSPI_NEGATE_13: + case TSPI_NEGATE_14: + case TSPI_NEGATE_15: + case TSPI_NEGATE_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_DISABLE: + case TSPI_PARITY_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_BIT_ODD: + case TSPI_PARITY_BIT_EVEN: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sect Mode's parameter. + * @param param :Sect Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_MODE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sect_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SECT_MODE_FRAME: + case TSPI_SECT_MODE_SECT: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl0 bit length's parameter. + * @param param :Sectl0 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl0_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + /* 1~32:setting enable */ + if ((param >= TSPI_SECT_VALUE_1) && (param <= TSPI_SECT_VALUE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl1 bit length's parameter. + * @param param :Sectl1 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl1_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl1_value = (param >> 8); + + /* 1~32:setting enable */ + if ((sectl1_value >= TSPI_SECT_VALUE_1) && (sectl1_value <= TSPI_SECT_VALUE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl2 bit length's parameter. + * @param param :Sectl2 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl2_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl2_value = (param >> 16); + + /* 0~32:setting enable */ + if (sectl2_value <= TSPI_SECT_VALUE_MAX) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl3 bit length's parameter. + * @param param :Sectl3 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl3_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl3_value = (param >> 24); + + /* 0~32:setting enable */ + if (sectl3_value <= TSPI_SECT_VALUE_MAX) { + result = PARAM_OK; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group TSPI_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_init(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxCR1. */ + assert_param(check_param_frameinf_enable(p_obj->init.cnt1.inf)); + assert_param(check_param_trgen_enable(p_obj->init.cnt1.trgen)); + assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); + assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); + assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); + assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); + assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); + assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); + /* Check the parameter of TTSPIxCR2 */ + assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); + assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); + assert_param(check_param_rxdly_value(p_obj->init.cnt2.rxdly)); + assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); + assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); + assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); + assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); + assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); + assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); + assert_param(check_param_err_int(p_obj->init.cnt2.interr)); + assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); + assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); + /* Check the parameter of TTSPIxBR */ + assert_param(check_param_input_clock(p_obj->init.brd.brck)); + assert_param(check_param_input_divider(p_obj->init.brd.brs)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); + /* Check the parameter of TSPISECTCR0 */ + assert_param(check_param_sect_mode(p_obj->init.scr0.sect)); + /* Check the parameter of TSPISECTCR1 */ + assert_param(check_param_sectl0_value(p_obj->init.scr1.sectl0)); + assert_param(check_param_sectl1_value(p_obj->init.scr1.sectl1)); + assert_param(check_param_sectl2_value(p_obj->init.scr1.sectl2)); + assert_param(check_param_sectl3_value(p_obj->init.scr1.sectl3)); +#endif + + + /* TSPI Software Reset */ + p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); + p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE);; + + /* Wait for 2 clocks of reset completion */ + __NOP(); + __NOP(); + + /* Enable the selected TSPI peripheral (TSPIE)*/ + p_obj->p_instance->CR0 = TSPI_ENABLE; + + /* Control1 Register1 Set*/ + p_obj->p_instance->CR1 = 0x00001C01U; + p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ + p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims | p_obj->init.cnt1.trgen | p_obj->init.cnt1.inf); + /* Control2 Register Set */ + p_obj->p_instance->CR2 = 0x00E10100U; + p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ + p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe | p_obj->init.cnt2.inttxwe | \ + p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare); + + /* Control3 Register is FIFO clear, do nothing */ + + /* Baudrate Register Set */ + p_obj->p_instance->BR = 0U; + p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); + + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = 0x8800C400U; + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = 0U; + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + + /* Sect control0 Register Set*/ + p_obj->p_instance->SECTCR0 = 0U; + p_obj->p_instance->SECTCR0 = p_obj->init.scr0.sect; + + /* Sect control1 Register Set*/ + p_obj->p_instance->SECTCR1 = 0x00000101U; + p_obj->p_instance->SECTCR1 = (p_obj->init.scr1.sectl3 | p_obj->init.scr1.sectl2 | p_obj->init.scr1.sectl1 | p_obj->init.scr1.sectl0); + + /* not created */ + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_deinit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Disable the selected TSPI peripheral */ + p_obj->p_instance->CR0 = TSPI_DISABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data.. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + + /* Transmit data check*/ + if ((p_info->tx8.p_data == TSPI_NULL) || (p_info->tx8.num == 0)) { + p_obj->errcode = DATABUFEMPERR; + result = TXZ_ERROR; + return (result); + } + + /* FIFO Cear */ + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + /* Transmit Data write to D ata Register */ + while (p_info->tx8.num > 0) { + /* Check the current fill level */ + if (((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { + *((__IO uint8_t *)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); + p_info->tx8.num--; + /* check complete transmit */ + if ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } else { + /* Enable TSPI Transmission Control */ + if (p_info->tx8.num == 0) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + return (result); + } else { + /* Next transmit data sending */ + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + } + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + + } + /* check complete transmit */ + while ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + /* Check Error Flag */ + if ((tspi_get_error(p_obj, &err)) != TXZ_ERROR) { + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + } else { + result = TXZ_ERROR; + return (result); + } + if (p_obj->errcode == NOERROR) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + uint32_t count = 0; + uint32_t index = 0; + + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + /* Transmit data check*/ + if ((p_info->rx8.p_data == TSPI_NULL) || (p_info->rx8.num == 0)) { + result = TXZ_ERROR; + return (result); + } + count = p_info->rx8.num; + + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + while (timeout > 0) { + /* Wait until Receive Complete Flag is set to receive data */ + if ((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { + while (count > 0) { + /* Check the remain data exist */ + if ((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { + p_info->rx8.p_data[index] = (*((__IO uint8_t *)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); + count--; + index++; + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + } + /* Receive Complete Flag is clear */ + p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; + /* FIFO Cear */ + p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + timeout--; + } + } + /* Timeout management */ + p_obj->errcode = TIMEOUTERR; + + /* Check Error Flag set */ + if ((tspi_get_error(p_obj, &err)) != TXZ_ERROR) { + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + } else { + result = TXZ_ERROR; + return (result); + } + + result = TXZ_ERROR; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + + + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data DMA. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Write to DMATE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR2 & TSPI_TX_DMA_INT_ENABLE) != TSPI_TX_DMA_INT_ENABLE) { + p_obj->p_instance->CR2 |= TSPI_TX_DMA_INT_ENABLE; + } + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data DMA. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Write to DMARE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR2 & TSPI_RX_DMA_INT_ENABLE) != TSPI_RX_DMA_INT_ENABLE) { + p_obj->p_instance->CR2 |= TSPI_RX_DMA_INT_ENABLE; + } + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_transmit(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + /* Check the transmit's end flag. */ + if (((status & TSPI_TX_DONE_FLAG) == TSPI_TX_DONE) || + ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Get the empty num in FIFO. */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + if (tlvl == TRANSFER_FIFO_MAX_NUM) { + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.tx_allign = 8; + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.tx_allign = 16; + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else { + /* 17 - 32 bit */ + p_obj->transmit.tx_allign = 32; + if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } +#if 0 + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; +#endif + } + } +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_receive(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.rx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + /* Check the receive's end flag. */ + if (((status & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) || + ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) { + /* Read FIFO fill level. */ + __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); + /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ + if (rlvl > RECEIVE_FIFO_MAX_NUM) { + rlvl = RECEIVE_FIFO_MAX_NUM; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->receive.rx_allign) { + case 8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); + break; + case 16: + *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + case 32: + *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + tspi_receive_t param; + + switch (p_obj->receive.rx_allign) { + case 8: + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + break; + case 16: + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + break; + case 32: + param.rx32.p_data = p_obj->receive.info.rx32.p_data; + param.rx32.num = rlvl; + break; + default: + /* no process */ + break; + } + /* Call the receive handler with SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_error_irq_handler(tspi_t *p_obj) +{ + __IO uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current TSPIxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- TSPIxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with FAILURE. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* UNDERERR */ + if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) { + err = TXZ_ERROR; + } + /* OVRERR */ + if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + /* Call the receive handler with FAILURE. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); + } + } + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Data Format setting + * @param p_obj :TSPI object. + * @retval - + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_format(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); +#endif + + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | + * | 30-24 | - | - | + * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | + * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | + * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | + * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | + * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | + * | 15-8 | - | - | + * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | + * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | + * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | + * + * @param p_obj :TSPI object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_status is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI state */ + *p_status = p_obj->p_instance->SR; + if (p_status != TSPI_NULL) { + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI ERROR */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Error information clear. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_error_clear(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + p_obj->p_instance->ERR = (TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_transmit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_receive(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + + +/** + * @} + */ /* End of group TSPI_Exported_functions */ + +/** + * @} + */ /* End of group TSPI */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__TSPI_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_uart.c new file mode 100644 index 0000000..127b57c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/Periph_driver/src/txz_uart.c @@ -0,0 +1,1805 @@ +/** + ******************************************************************************* + * @file txz_uart.c + * @brief This file provides API functions for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txz_uart_include.h" +#include "txz_uart.h" + +#if defined(__UART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/** + * @defgroup UART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */ + +#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL + +#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */ +#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group UART_BourateConfig */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_typedef UART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_fuctions UART Private Fuctions + * @{ + */ +#ifdef __DEBUG__ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param); +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param); +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param); +__STATIC_INLINE int32_t check_param_division(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef __DEBUG__ */ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level); +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level); +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef __DEBUG__ +/*--------------------------------------------------*/ +/** + * @brief Check the Noize Fileter's parameter. + * @param param :Noize fileter's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_NOISE_FILTER_NON: + case UART_NOISE_FILTER_2_T0: + case UART_NOISE_FILTER_4_T0: + case UART_NOISE_FILTER_8_T0: + case UART_NOISE_FILTER_2_CLOCK: + case UART_NOISE_FILTER_3_CLOCK: + case UART_NOISE_FILTER_4_CLOCK: + case UART_NOISE_FILTER_5_CLOCK: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_CTS_DISABLE: + case UART_CTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RTS_DISABLE: + case UART_RTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Complementation's parameter. + * @param param :Data Complementation's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_COMPLEMENTION_DISABLE: + case UART_DATA_COMPLEMENTION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_DIRECTION_LSB: + case UART_DATA_DIRECTION_MSB: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_STOP_BIT_1: + case UART_STOP_BIT_2: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_BIT_ODD: + case UART_PARITY_BIT_EVEN: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_DISABLE: + case UART_PARITY_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_LENGTH_7: + case UART_DATA_LENGTH_8: + case UART_DATA_LENGTH_9: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/ +#if 0 + if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX)) +#else + if (param <= UART_TX_FILL_RANGE_MAX) +#endif + { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX)) { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_FIFO_INT_DISABLE: + case UART_TX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_INT_DISABLE: + case UART_TX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_FIFO_INT_DISABLE: + case UART_RX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_INT_DISABLE: + case UART_RX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_ERR_INT_DISABLE: + case UART_ERR_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Prescaler's parameter. + * @param param :Prescaler's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PLESCALER_1: + case UART_PLESCALER_2: + case UART_PLESCALER_4: + case UART_PLESCALER_8: + case UART_PLESCALER_16: + case UART_PLESCALER_32: + case UART_PLESCALER_64: + case UART_PLESCALER_128: + case UART_PLESCALER_256: + case UART_PLESCALER_512: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Division's parameter. + * @param param :Division's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_division(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DIVISION_DISABLE: + case UART_DIVISION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX)) +#else + if (param <= UART_RANGE_K_MAX) +#endif + { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX)) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param != 0) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param >= 8) { + result = UART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef __DEBUG__ */ + +/*--------------------------------------------------*/ +/** + * @brief Convert Tx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result = (level << 12); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Convert Rx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result; + + if (level < 8) { + result = (level << 8); + } else { + result = 0; + } + + return (result); +} + +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi Tx */ + uint32_t prescaler = (p_clk->prsel >> 4); + + work64 = (uint64_t)((uint64_t)1 << prescaler); + tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + tx64 /= work64; + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * UART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group UART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_init(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_prescaler(p_obj->init.clock.prsel)); + assert_param(check_param_division(p_obj->init.boudrate.ken)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.inttx)); + assert_param(check_param_rx_int(p_obj->init.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx)); + assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level)); + assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level)); + assert_param(check_param_noize_filter(p_obj->init.nf)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_data_complemention(p_obj->init.iv)); + assert_param(check_param_data_direction(p_obj->init.dir)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* SW Reset */ + /*------------------------------*/ + /*--- UARTxSWRST ---*/ + /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */ + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /* Write to SWRST(=10). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10; + /* Write to SWRST(=01). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01; + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /*------------------------------*/ + /* FIFO Clear */ + /*------------------------------*/ + /*--- UARTxFIFOCLR ---*/ + /* Write to TFCLR(=1), and RFCLR(=1) */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- UARTxCLK ---*/ + /* Reflecting "p_obj->init.clk" */ + p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK); + /*--- UARTxBRD ---*/ + /* Reflecting "p_obj->init.brd" */ + /* Be careful, BRK needs to bit shit. */ + { + uint32_t brk = (p_obj->init.boudrate.brk << 16); + p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn); + } + /*--- UARTxCR0 ---*/ + /* Reflecting "p_obj->init.cnt0" */ + p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm | + p_obj->init.hcc | p_obj->init.lbc | + p_obj->init.nf | p_obj->init.ctse | + p_obj->init.rtse | p_obj->init.iv | + p_obj->init.dir | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe | + p_obj->init.sm); + /*--- UARTxCR1 ---*/ + /* Reflecting "p_obj->init.cnt1" */ + /* Fixed: "DMATE=0", "DMARE=0". */ + /* Be careful, "TIL", "RIL" need to bit shit. */ + p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) | + convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) | + p_obj->init.txfifo.inttx | p_obj->init.inttx | + p_obj->init.rxfifo.intrx | p_obj->init.intrx | + p_obj->init.interr); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_deinit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*--- UARTxCR1 ---*/ + p_obj->p_instance->CR1 = 0; + /*--- UARTxCR0 ---*/ + p_obj->p_instance->CR0 = 0; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_transmit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR); + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR); + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Return RXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_receive(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the receive's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */ + p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR | + UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Return TXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK)); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx8.num)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + } else { + /* 7/8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /*--- UARTxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Empty FIFO Num */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx8.num)); + } +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + } else { + /* 7/8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_transmit_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*---- UARTxSR ---*/ + /* Check the transmit's end flag. */ + if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) || + ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + uint32_t tlvl = (status & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Get the empty num in FIFO. */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + if (tlvl == UART_TX_FIFO_MAX) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + default: + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_receive_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /* Check the receive's end flag. */ + if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) || + ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED)) { + /* Read FIFO fill level. */ + uint32_t rlvl = (status & UARTxSR_RLVL_MASK); + /* FIFO Max = UART_RX_FIFO_MAX */ + if (rlvl > UART_RX_FIFO_MAX) { + rlvl = UART_RX_FIFO_MAX; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK); + break; + case UART_DATA_LENGTH_8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK); + break; + case UART_DATA_LENGTH_7: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + uart_receive_t param; + + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + } else { + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + } + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_error_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current UARTxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR) { + /*------------------------------*/ + /* Transmit Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_ERROR. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVRERR */ + if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR) { + err = TXZ_ERROR; + } + /* FERR */ + if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR) { + err = TXZ_ERROR; + } + /* BERR */ + if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. | + * | 30-16 | - | - | + * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. | + * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. | + * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. | + * | 12 | - | - | + * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel | + * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. | + * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel | + * | 4 | - | - | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel | + * + * @param p_obj :UART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Read current UARTxSR. */ + *p_status = p_obj->p_instance->SR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-5 | - | - | + * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. | + * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. | + * + * @param p_obj :UART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Read current UARTxERR. */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef __DEBUG__ + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_clk)); + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of UARTxCLK. */ +#endif /* #ifdef __DEBUG__ */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi Tx ---*/ + uint32_t prescaler = (p_clk->prsel >> 4); + + work = (uint64_t)((uint64_t)1 << prescaler); + tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + tx /= work; + + /*--- N+(64-K)/64 division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx + (uint64_t)k; + if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT)) { + work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { + uint64_t workRange = 0; + + /* Verification */ + if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } + } +#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PeripheralNames.h new file mode 100644 index 0000000..b9c8fe7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PeripheralNames.h @@ -0,0 +1,174 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + SERIAL_2, + SERIAL_3, + SERIAL_4, + SERIAL_5, + INVALID_SERIAL = (int)NC +} UARTName; + +typedef enum { + DAC_0 = 0, + DAC_1, + INVALID_DAC = (int)NC +} DACName; + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + PWM_5, + PWM_6, + PWM_7, + PWM_8, + PWM_9, + PWM_10, + PWM_11, + PWM_12, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + ADC_A0 = 0, + ADC_A1, + ADC_A2, + ADC_A3, + ADC_A4, + ADC_A5, + ADC_A6, + ADC_A7, + ADC_A9 = 9, + ADC_A14 = 14, + ADC_A17 = 17, + ADC_A18, + ADC_A19, + ADC_A20, + ADC_A21, + ADC_A22, + ADC_A23, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + SPI_0 = 0, + SPI_1, + INVALID_SPI = (int)NC +} SPIName; + +typedef enum { + GPIO_IRQ_0 = 0, + GPIO_IRQ_1, + GPIO_IRQ_2, + GPIO_IRQ_3, + GPIO_IRQ_4, + GPIO_IRQ_5, + GPIO_IRQ_6, + GPIO_IRQ_7, + GPIO_IRQ_8, + GPIO_IRQ_9, + GPIO_IRQ_A, + GPIO_IRQ_B, + GPIO_IRQ_C, + GPIO_IRQ_D, + GPIO_IRQ_E, + GPIO_IRQ_F, + INVALID_GPIO_IRQ = (int)NC +} GPIO_IRQName; + +// DAP UART +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) +#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX +#else +#define STDIO_UART_TX CONSOLE_TX +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) +#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX +#else +#define STDIO_UART_RX CONSOLE_RX +#endif + +#define SERIAL_TX PV1 +#define SERIAL_RX PV0 + +#define STDIO_UART SERIAL_2 + +// TxD RxD +#define MBED_UART0 PE3, PE2 +#define MBED_UART1 PV5, PV4 +#define MBED_UART2 PV1, PV0 +#define MBED_UART3 PJ1, PJ0 +#define MBED_UART4 PJ4, PJ5 +#define MBED_UART5 PJ6, PJ7 +#define MBED_UARTUSB CONSOLE_TX, CONSOLE_RX + +// SDA SCK +#define MBED_I2C0 PF2, PF3 +#define MBED_I2C1 PV5, PV4 +#define MBED_I2C2 PJ6, PJ7 +#define MBED_I2C3 PJ3, PJ2 + +// MOSI, MISO, SCLK SS +#define MBED_SPI0 PA3, PA2, PA1, PA0 +#define MBED_SPI1 PA4, PA5, PA6, PA7 + +#define MBED_ANALOGIN0 A0 +#define MBED_ANALOGIN1 A1 +#define MBED_ANALOGIN2 A2 +#define MBED_ANALOGIN3 A3 +#define MBED_ANALOGIN4 A4 +#define MBED_ANALOGIN5 A5 + +#define MBED_PWMOUT0 PW1 +#define MBED_PWMOUT1 PW2 +#define MBED_PWMOUT2 PT3 +#define MBED_PWMOUT3 PD2 +#define MBED_PWMOUT4 PD4 +#define MBED_PWMOUT5 PE1 +#define MBED_PWMOUT6 PE6 +#define MBED_PWMOUT7 PL4 +#define MBED_PWMOUT8 PL6 +#define MBED_PWMOUT9 PC4 +#define MBED_PWMOUT10 PW6 +#define MBED_PWMOUT11 PU0 +#define MBED_PWMOUT12 PU6 + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PinNames.h new file mode 100644 index 0000000..535e650 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PinNames.h @@ -0,0 +1,138 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) + +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) +#define PIN_DIR(X) ((X) & 0xffff) + +// Other mbed Pin Names +#define LED1 PW4 +#define LED2 PW5 +#define LED3 PW6 +#define LED4 PW7 +#define I2C_SDA SDA +#define I2C_SCL SCL + + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM4NR Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7, + PB0 = 1 << 3, PB1, PB2, PB3, + PC4 = (2 << 3) | 4, PC5, PC6, PC7, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, PD6, PD7, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7, + PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, + PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7, + PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, + PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7, + PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5, PN6, PN7, + PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7, + PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7, + PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, + PU0 = 16 << 3, + PU2 = (16 << 3) | 2, PU3, PU4, PU5, PU6, PU7, + PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7, + PW0 = 18 << 3, PW1, PW2, PW3, PW4, PW5, PW6, PW7, + PY0 = 19 << 3, PY1, PY2, PY3, PY4, + + // External data bus Pin Names + D0 = PJ1, + D1 = PJ0, + D2 = PM7, + D3 = PT5, + D4 = PM6, + D5 = PW3, + D6 = PW2, + D7 = PM5, + D8 = PM4, + D9 = PW1, + D10 = PA7, + D11 = PA4, + D12 = PA5, + D13 = PA6, + D14 = PF2, + D15 = PF3, + + // Analogue in pins + A0 = PN0, + A1 = PN1, + A2 = PN2, + A3 = PN3, + A4 = PN4, + A5 = PN5, + + // USB2_UART + CONSOLE_TX = PV1, + CONSOLE_RX = PV0, + MBEDIF_TXD = CONSOLE_TX, + MBEDIF_RXD = CONSOLE_RX, + + MBED_CONF_APP_UART0_TX = PE3, + MBED_CONF_APP_UART0_RX = PE2, + + // Switches + SW1 = PL5, + SW2 = PV2, + //SW3 = PV0, + //SW4 = PV1, + + // I2C pins + SDA = PF2, + SCL = PF3, + + // Analogue out + DAC0 = PT0, + DAC1 = PT1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PortNames.h new file mode 100644 index 0000000..417523a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/PortNames.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ, + PortK, + PortL, + PortM, + PortN, + PortP, + PortR, + PortT, + PortU, + PortV, + PortW, + PortY +} PortName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/analogin_api.c new file mode 100644 index 0000000..908f4a2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/analogin_api.c @@ -0,0 +1,139 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "txz_adc_include.h" + +#define ADC_12BIT_RANGE 0xFFF +#define CONVERSION_FLAG 0x4 + +static const PinMap PinMap_ADC[] = { + {PN0, ADC_A0, PIN_DATA(0, 0)}, + {PN1, ADC_A1, PIN_DATA(0, 0)}, + {PN2, ADC_A2, PIN_DATA(0, 0)}, + {PN3, ADC_A3, PIN_DATA(0, 0)}, + {PN4, ADC_A4, PIN_DATA(0, 0)}, + {PN5, ADC_A5, PIN_DATA(0, 0)}, + {PN6, ADC_A6, PIN_DATA(0, 0)}, + {PN7, ADC_A7, PIN_DATA(0, 0)}, + {PP1, ADC_A9, PIN_DATA(0, 0)}, + {PP6, ADC_A14, PIN_DATA(0, 0)}, + {PR1, ADC_A17, PIN_DATA(0, 0)}, + {PR2, ADC_A18, PIN_DATA(0, 0)}, + {PR3, ADC_A19, PIN_DATA(0, 0)}, + {PR4, ADC_A20, PIN_DATA(0, 0)}, + {PR5, ADC_A21, PIN_DATA(0, 0)}, + {PR6, ADC_A22, PIN_DATA(0, 0)}, + {PR7, ADC_A23, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Enable ADC clock supply + TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; + TSB_CG_SPCLKEN_ADCKEN = TXZ_ENABLE; + TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE; + + // Enable clock for GPIO + if (obj->adc <= ADC_A7) { + TSB_CG_FSYSMENB_IPMENB14 = TXZ_ENABLE; + } else if (obj->adc <= ADC_A14) { + TSB_CG_FSYSMENB_IPMENB15 = TXZ_ENABLE; + } else { + TSB_CG_FSYSMENB_IPMENB16 = TXZ_ENABLE; + } + + // Set pin function as ADC + pinmap_pinout(pin, PinMap_ADC); + + // Initialize + obj->p_adc.p_instance = TSB_ADA; + obj->p_adc.init.clk.exaz0 = ADC_SAMPLING_PERIOD0_XN; + obj->p_adc.init.clk.exaz1 = ADC_SAMPLING_PERIOD1_XN; + obj->p_adc.init.clk.vadcld = ADC_SCLK_5; /*less than 40MHz*/ + obj->p_adc.init.clk.sampling_select = 0; + obj->p_adc.init.mod1 = ADC_MOD1_SCLK_4; + obj->p_adc.init.mod2 = ADC_MOD2_SET; + obj->p_adc.handler.single = NULL; + obj->p_adc.handler.continuity = NULL; + obj->p_adc.handler.trigger = NULL; + obj->p_adc.handler.highpriority = NULL; + + if (adc_init(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : ADC Initialization"); + } + + // ADC channel setting + obj->param.interrupt = ADC_INT_DISABLE; + obj->param.type = ADC_CONVERSION_SGL; + obj->param.ain = obj->adc; + + if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) { + error("Failed : ADC channel setting"); + } +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint32_t adc_result = 0; + + // Assert that ADC channel is valid + MBED_ASSERT(obj->adc != (ADCName)NC); + + wait_us(7000); // Wait at least 7ms to ensure the voltage is stable + if (adc_start(&obj->p_adc) == TXZ_SUCCESS) { + // adc started + } + + // Wait for Continuous conversion program flag clear. + while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) { + // Do nothing + } + + if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) { + error("Failed : To read ADC converted result"); + } + + if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : To Stop ADC Conversion"); + } + + return (uint16_t)adc_result; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = 0; + + value = analogin_read_u16(obj); + + return (float)(value * (1.0f / (float)ADC_12BIT_RANGE)); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/analogout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/analogout_api.c new file mode 100644 index 0000000..d98aad7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/analogout_api.c @@ -0,0 +1,129 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "cmsis.h" +#include "analogout_api.h" +#include "pinmap.h" + +#define REG_DAC_DAxCR_REN_DISABLE ((uint32_t)0x00000000) // DAC Control Disable. +#define REG_DAC_DAxCR_REN_ENABLE ((uint32_t)0x00000001) // DAC Control Enable. +#define DAC0_CLR_IN_CLR_OUT (1) // As per TRM DAC pin inout mode should be neither in nor out +#define DAC1_CLR_IN_CLR_OUT (2) +#define MAX_ANALOG_VAL (1.0f) +#define MIN_ANALOG_VAL (0.0f) + + +static const PinMap PinMap_DAC[] = { + {PT0, DAC_0, PIN_DATA(0, 1)}, + {PT1, DAC_1, PIN_DATA(0, 1)}, + {NC, NC, 0} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + DACName dac_name = (DACName)pinmap_peripheral(pin, PinMap_DAC); + + MBED_ASSERT(dac_name != (DACName)NC); + + obj->dac = dac_name; + + switch (dac_name) { + case DAC_0: + obj->DACx = TSB_DA0; + // Enable clock for DAC0 and Port T + TSB_CG_FSYSMENA_IPMENA04 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; + break; + case DAC_1: + obj->DACx = TSB_DA1; + // Enable clock for DAC1 and Port T + TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB17 = TXZ_ENABLE; + break; + default: + break; + } + + + pinmap_pinout(pin, PinMap_DAC); + + // DAC pins as neither input and nor output + if (dac_name == DAC_0) { + TSB_PT->CR &= ~(DAC0_CLR_IN_CLR_OUT); + TSB_PT->IE &= ~(DAC0_CLR_IN_CLR_OUT); + } else if (dac_name == DAC_1) { + TSB_PT->CR &= ~(DAC1_CLR_IN_CLR_OUT); + TSB_PT->IE &= ~(DAC1_CLR_IN_CLR_OUT); + } else { + return; + } + + obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; +} + +void analogout_free(dac_t *obj) +{ + obj->DACx->CR = REG_DAC_DAxCR_REN_DISABLE; + obj->dac = (DACName)NC; +} + +void analogout_write(dac_t *obj, float value) +{ + uint8_t outputcode = 0; + obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; + if (value < 0.0f) { + value = 0.0f; + } else { + if (value >= 1.0f) { + value = 1.0f; + } + } + outputcode = (uint8_t)(value * 255.0f); + obj->DACx->REG = outputcode; +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + // Writing higher 8-bits to Data Register + obj->DACx->CR = REG_DAC_DAxCR_REN_ENABLE; + obj->DACx->REG = (uint8_t)(value & 0xFF); +} + +float analogout_read(dac_t *obj) +{ + float result = 0.0; + uint32_t value = 0; + + value = ((obj->DACx->REG) & (0xFF)); + result = ((float)value / 255.0f); + + return result; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + uint16_t value = 0; + + value = (uint16_t)((obj->DACx->REG) & (0xFF)); + return value; + // Upper and lower byte stored with read value +} + +const PinMap *analogout_pinmap() +{ + return PinMap_DAC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device.h new file mode 100644 index 0000000..1fb6792 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device.h @@ -0,0 +1,26 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define TRANSACTION_QUEUE_SIZE_SPI 4 +#define DEVICE_ID_LENGTH 32 + +#include +#include "objects.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4NR.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4NR.h new file mode 100644 index 0000000..02fd883 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4NR.h @@ -0,0 +1,9339 @@ +/** + ******************************************************************************* + * @file TMPM4NR.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4NR' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM4NR + * @{ + */ + +#ifndef __TMPM4NR_H__ +#define __TMPM4NR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** TMPM4NR Specific Interrupt Numbers *******************************************************************/ + INT00_IRQn = 0, /*!< Interrupt pin 00a/00b */ + INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */ + INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */ + INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */ + INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */ + INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */ + INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */ + INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */ + INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */ + INT09_IRQn = 9, /*!< Interrupt pin 09a/09b */ + INT10_IRQn = 10, /*!< Interrupt pin 10a/10b */ + INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */ + INT12_IRQn = 12, /*!< Interrupt pin 12a/12b */ + INT13_IRQn = 13, /*!< Interrupt pin 13a/13b */ + INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */ + INT15_IRQn = 15, /*!< Interrupt pin 15a/15b */ + INTRTC_IRQn = 16, /*!< Real time clock(XHz) interrupt */ + INTCEC0RX_IRQn = 17, /*!< CEC reception interrupt (channel 0) */ + INTCEC0TX_IRQn = 18, /*!< CEC transmission interrupt (channel 0) */ + INTISDA_IRQn = 19, /*!< Interval Sensing Detector interrupt (Unit A) */ + INTISDB_IRQn = 20, /*!< Interval Sensing Detector interrupt (Unit B) */ + INTISDC_IRQn = 21, /*!< Interval Sensing Detector interrupt (Unit C) */ + INTRMC0_IRQn = 22, /*!< Remote control reception interrupt 0 */ + INTRMC1_IRQn = 23, /*!< Remote control reception interrupt 1 */ + INTLTTMR0_IRQn = 24, /*!< Long Term Timer Interrupt(channel 0) */ + INTHDMAATC_IRQn = 25, /*!< HDMA complete of transfer(Unit A) */ + INTHDMAAERR_IRQn = 26, /*!< HDMA transfer error(Unit A) */ + INTHDMABTC_IRQn = 27, /*!< HDMA end of transfer(Unit B) */ + INTHDMABERR_IRQn = 28, /*!< HDMA transfer error(Unit B) */ + INTMDMAATC_IRQn = 29, /*!< MDMA complete of transfer(Unit A) */ + INTT32A00_A_CT_IRQn = 30, /*!< T32A00 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A00_B_C01_CPC_IRQn = 31, /*!< T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A01_A_CT_IRQn = 32, /*!< T32A01 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A01_B_C01_CPC_IRQn = 33, /*!< T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A02_A_CT_IRQn = 34, /*!< T32A02 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A02_B_C01_CPC_IRQn = 35, /*!< T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A03_A_CT_IRQn = 36, /*!< T32A03 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A03_B_C01_CPC_IRQn = 37, /*!< T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A04_A_CT_IRQn = 38, /*!< T32A04 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A04_B_C01_CPC_IRQn = 39, /*!< T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A05_A_CT_IRQn = 40, /*!< T32A05 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A05_B_C01_CPC_IRQn = 41, /*!< T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A06_A_CT_IRQn = 42, /*!< T32A06 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A06_B_C01_CPC_IRQn = 43, /*!< T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A07_A_CT_IRQn = 44, /*!< T32A07 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A07_B_C01_CPC_IRQn = 45, /*!< T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A08_A_CT_IRQn = 46, /*!< T32A08 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A08_B_C01_CPC_IRQn = 47, /*!< T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A09_A_CT_IRQn = 48, /*!< T32A09 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A09_B_C01_CPC_IRQn = 49, /*!< T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A10_A_CT_IRQn = 50, /*!< T32A10 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A10_B_C01_CPC_IRQn = 51, /*!< T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A11_A_CT_IRQn = 52, /*!< T32A11 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A11_B_C01_CPC_IRQn = 53, /*!< T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A12_A_CT_IRQn = 54, /*!< T32A12 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A12_B_C01_CPC_IRQn = 55, /*!< T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTT32A13_A_CT_IRQn = 56, /*!< T32A13 TimerA all interrupt /TimerC match, overflow, and underflow*/ + INTT32A13_B_C01_CPC_IRQn = 57, /*!< T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt*/ + INTEMG0_IRQn = 58, /*!< PMD0 EMG interrupt */ + INTOVV0_IRQn = 59, /*!< PMD0 OVV interrupt */ + INTPWM0_IRQn = 60, /*!< PMD0 interrupt */ + INTT0RX_IRQn = 61, /*!< TSPI/SIO reception (channel 0) interrupt */ + INTT0TX_IRQn = 62, /*!< TSPI/SIO transmit (channel 0) interrupt */ + INTT0ERR_IRQn = 63, /*!< TSPI/SIO error (channel 0) interrupt */ + INTT1RX_IRQn = 64, /*!< TSPI/SIO reception (channel 1) interrupt */ + INTT1TX_IRQn = 65, /*!< TSPI/SIO transmit (channel 1) interrupt */ + INTT1ERR_IRQn = 66, /*!< TSPI/SIO error (channel 1) interrupt */ + INTT2RX_IRQn = 67, /*!< TSPI/SIO reception (channel 2) interrupt */ + INTT2TX_IRQn = 68, /*!< TSPI/SIO transmit (channel 2) interrupt */ + INTT2ERR_IRQn = 69, /*!< TSPI/SIO error (channel 2) interrupt */ + INTT3RX_IRQn = 70, /*!< TSPI/SIO reception (channel 3) interrupt */ + INTT3TX_IRQn = 71, /*!< TSPI/SIO transmit (channel 3) interrupt */ + INTT3ERR_IRQn = 72, /*!< TSPI/SIO error (channel 3) interrupt */ + INTT4RX_IRQn = 73, /*!< TSPI/SIO reception (channel 4) interrupt */ + INTT4TX_IRQn = 74, /*!< TSPI/SIO transmit (channel 4) interrupt */ + INTT4ERR_IRQn = 75, /*!< TSPI/SIO error (channel 4) interrupt */ + INTT5RX_IRQn = 76, /*!< TSPI/SIO reception (channel 5) interrupt */ + INTT5TX_IRQn = 77, /*!< TSPI/SIO transmit (channel 5) interrupt */ + INTT5ERR_IRQn = 78, /*!< TSPI/SIO error (channel 5) interrupt */ + INTT6RX_IRQn = 79, /*!< TSPI/SIO reception (channel 6) interrupt */ + INTT6TX_IRQn = 80, /*!< TSPI/SIO transmit (channel 6) interrupt */ + INTT6ERR_IRQn = 81, /*!< TSPI/SIO error (channel 6) interrupt */ + INTT7RX_IRQn = 82, /*!< TSPI/SIO reception (channel 7) interrupt */ + INTT7TX_IRQn = 83, /*!< TSPI/SIO transmit (channel 7) interrupt */ + INTT7ERR_IRQn = 84, /*!< TSPI/SIO error (channel 7) interrupt */ + INTT8RX_IRQn = 85, /*!< TSPI/SIO reception (channel 8) interrupt */ + INTT8TX_IRQn = 86, /*!< TSPI/SIO transmit (channel 8) interrupt */ + INTT8ERR_IRQn = 87, /*!< TSPI/SIO error (channel 8) interrupt */ + INTSMI0_IRQn = 88, /*!< Serial Memory Interface interrupt */ + INTUART0RX_IRQn = 89, /*!< UART reception (channel 0) interrupt */ + INTUART0TX_IRQn = 90, /*!< UART transmit (channel 0) interrupt */ + INTUART0ERR_IRQn = 91, /*!< UART error (channel 0) interrupt */ + INTUART1RX_IRQn = 92, /*!< UART reception (channel 1) interrupt */ + INTUART1TX_IRQn = 93, /*!< UART transmit (channel 1) interrupt */ + INTUART1ERR_IRQn = 94, /*!< UART error (channel 1) interrupt */ + INTUART2RX_IRQn = 95, /*!< UART reception (channel 2) interrupt */ + INTUART2TX_IRQn = 96, /*!< UART transmit (channel 2) interrupt */ + INTUART2ERR_IRQn = 97, /*!< UART error (channel 2) interrupt */ + INTUART3RX_IRQn = 98, /*!< UART reception (channel 3) interrupt */ + INTUART3TX_IRQn = 99, /*!< UART transmit (channel 3) interrupt */ + INTUART3ERR_IRQn = 100, /*!< UART error (channel 3) interrupt */ + INTUART4RX_IRQn = 101, /*!< UART reception (channel 4) interrupt */ + INTUART4TX_IRQn = 102, /*!< UART transmit (channel 4) interrupt */ + INTUART4ERR_IRQn = 103, /*!< UART error (channel 4) interrupt */ + INTUART5RX_IRQn = 104, /*!< UART reception (channel 5) interrupt */ + INTUART5TX_IRQn = 105, /*!< UART transmit (channel 5) interrupt */ + INTUART5ERR_IRQn = 106, /*!< UART error (channel 5) interrupt */ + INTFUART0_IRQn = 107, /*!< FUART interrupt(channel 0) */ + INTFUART1_IRQn = 108, /*!< FUART interrupt(channel 1) */ + INTI2C0NST_IRQn = 109, /*!< I2C0 interrupt / EI2C0 status interrupt */ + INTI2C0ATX_IRQn = 110, /*!< I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C0BRX_IRQn = 111, /*!< I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C0NA_IRQn = 112, /*!< I2C0 NACK detection interrupt */ + INTI2C1NST_IRQn = 113, /*!< I2C1 interrupt / EI2C0 status interrupt */ + INTI2C1ATX_IRQn = 114, /*!< I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C1BRX_IRQn = 115, /*!< I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C1NA_IRQn = 116, /*!< I2C1 NACK detection interrupt */ + INTI2C2NST_IRQn = 117, /*!< I2C2 interrupt / EI2C0 status interrupt */ + INTI2C2ATX_IRQn = 118, /*!< I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C2BRX_IRQn = 119, /*!< I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C2NA_IRQn = 120, /*!< I2C2 NACK detection interrupt */ + INTI2C3NST_IRQn = 121, /*!< I2C3 interrupt / EI2C0 status interrupt */ + INTI2C3ATX_IRQn = 122, /*!< I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C3BRX_IRQn = 123, /*!< I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C3NA_IRQn = 124, /*!< I2C3 NACK detection interrupt */ + INTI2C4NST_IRQn = 125, /*!< I2C4 interrupt / EI2C0 status interrupt */ + INTI2C4ATX_IRQn = 126, /*!< I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt*/ + INTI2C4BRX_IRQn = 127, /*!< I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt*/ + INTI2C4NA_IRQn = 128, /*!< I2C4 NACK detection interrupt */ + INTADACP0_IRQn = 129, /*!< ADC conversion monitoring function interrupt 0 */ + INTADACP1_IRQn = 130, /*!< ADC conversion monitoring function interrupt 1 */ + INTADATRG_IRQn = 131, /*!< ADC conversion triggered by General purpose is finished */ + INTADASGL_IRQn = 132, /*!< ADC conversion triggered by Single program is finished */ + INTADACNT_IRQn = 133, /*!< ADC conversion triggered by Continuity program is finished */ + INTADAHP_IRQn = 134, /*!< ADC high priority AD conversion interrupt */ + INTFLDRDY_IRQn = 135, /*!< Data FLASH Ready interrupt */ + INTFLCRDY_IRQn = 136, /*!< Code FLASH Area0/1 Ready interrupt */ + INTMDMAABERR_IRQn = 139, /*!< MDMA bus error(Unit A) interrupt */ + INTMDMAADERR_IRQn = 140, /*!< MDMA descriptor error(Unit A) interrupt */ + INTI2S0SI_IRQn = 141, /*!< I2S ch0 SI transfer end interrupt */ + INTI2S0SIERR_IRQn = 142, /*!< I2S ch0 SI error interrupt */ + INTI2S0SO_IRQn = 143, /*!< I2S ch0 SO transfer end interrupt */ + INTI2S0SOERR_IRQn = 144, /*!< I2S ch0 SO error interrupt */ + INTI2S1SI_IRQn = 145, /*!< I2S ch1 SI transfer end interrupt */ + INTI2S1SIERR_IRQn = 146, /*!< I2S ch1 SI error interrupt */ + INTI2S1SO_IRQn = 147, /*!< I2S ch1 SO transfer end interrupt */ + INTI2S1SOERR_IRQn = 148, /*!< I2S ch1 SO error interrupt */ + INTFIR0_IRQn = 149, /*!< FIR ch0 interrupt */ + INTTSSI0RX_IRQn = 150, /*!< TSSI ch0 receive interrupt */ + INTTSSI0TX_IRQn = 151, /*!< TSSI ch0 transmission interrupt */ + INTTSSI0ERR_IRQn = 152, /*!< TSSI ch0 error interrupt */ + INTTSSI1RX_IRQn = 153, /*!< TSSI ch1 receive interrupt */ + INTTSSI1TX_IRQn = 154, /*!< TSSI ch1 transmission interrupt */ + INTTSSI1ERR_IRQn = 155, /*!< TSSI ch1 error interrupt */ + INTEMA_IRQn = 156, /*!< ETHM unit A interrupt */ + INTEMAMP_IRQn = 157, /*!< ETHM unit A magic packet detection interrupt */ + INTCANARXD_IRQn = 158, /*!< CAN unit A receive interrupt */ + INTCANATXD_IRQn = 159, /*!< CAN unit A transmission interrupt */ + INTCANAGLB_IRQn = 160, /*!< CAN unit A Global interrupt */ + INTCANBRXD_IRQn = 161, /*!< CAN unit B receive interrupt */ + INTCANBTXD_IRQn = 162, /*!< CAN unit B transmission interrupt */ + INTCANBGLB_IRQn = 163, /*!< CAN unit B Global interrupt */ + INTUSBOTGA_IRQn = 164, /*!< USB OTG unit A interrupt */ + INTUSBOTGAWK_IRQn = 165, /*!< USB OTG unit A Wakeup interrupt */ + INTUSBOTGB_IRQn = 166, /*!< USB OTG unit B interrupt */ + INTUSBOTGBWK_IRQn = 167, /*!< USB OTG unit B Wakeup interrupt */ + INTT32A14_A_IRQn = 168, /*!< T32A14 TimerA all interrupt */ + INTT32A14_B_IRQn = 169, /*!< T32A14 TimerB all interrupt */ + INTT32A14_CT_IRQn = 170, /*!< T32A14 TimerC match, overflow, and underflow Interrupt */ + INTT32A15_A_IRQn = 171, /*!< T32A15 TimerA all interrupt */ + INTT32A15_B_IRQn = 172, /*!< T32A15 TimerB all interrupt */ + INTT32A15_C_IRQn = 173, /*!< T32A15 TimerC all interrupt */ + INTMDMAADISR_IRQn = 174 /*!< MDMAC unit A Descriptor interrupt */ +} IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_TMPM4Nx.h" /* TMPM4Nx System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief DMA Controller + */ +typedef struct { + __I uint32_t INTSTATUS; /*!< DMAC Interrupt Status Register */ + __I uint32_t INTTCSTATUS; /*!< DMAC Transfer Completion Interrupt Status Register*/ + __O uint32_t INTTCCLEAR; /*!< DMAC Transfer Completion Interrupt Clear Register*/ + __I uint32_t INTERRORSTATUS; /*!< DMAC Error Interrupt Status Register */ + __O uint32_t INTERRCLR; /*!< DMAC Error Interrupt Clear Register */ + __I uint32_t RAWINTTCSTATUS; /*!< DMAC Raw Transfer Completion Interrupt Status Register*/ + __I uint32_t RAWINTERRORSTATUS; /*!< DMAC Raw Error Interrupt Status Register */ + __I uint32_t ENBLDCHNS; /*!< DMAC Channel Enable Register */ + __IO uint32_t SOFTBREQ; /*!< DMAC Software Burst Transfer Request Register*/ + __IO uint32_t SOFTSREQ; /*!< DMAC Software Single Transfer Request Register*/ + uint32_t RESERVED0[2]; + __IO uint32_t CONFIGURATION; /*!< DMAC Configuration Register */ + uint32_t RESERVED1[51]; + __IO uint32_t C0SRCADDR; /*!< DMAC Channel 0 Transfer Source Address Register*/ + __IO uint32_t C0DESTADDR; /*!< DMAC Channel 0 Transfer Destination Address Register*/ + __IO uint32_t C0LLI; /*!< DMAC Channel 0 Linked List Item Register */ + __IO uint32_t C0CONTROL; /*!< DMAC Channel 0 Control Register */ + __IO uint32_t C0CONFIGURATION; /*!< DMAC Channel 0 Configuration Register */ + uint32_t RESERVED2[3]; + __IO uint32_t C1SRCADDR; /*!< DMAC Channel 1 Transfer Source Address Register*/ + __IO uint32_t C1DESTADDR; /*!< DMAC Channel 1 Transfer Destination Address Register*/ + __IO uint32_t C1LLI; /*!< DMAC Channel 1 Linked List Item Register */ + __IO uint32_t C1CONTROL; /*!< DMAC Channel 1 Control Register */ + __IO uint32_t C1CONFIGURATION; /*!< DMAC Channel 1 Configuration Register */ +} TSB_DMAC_TypeDef; + +/** + * @brief CAN Controller Mailbox RAM (CANMB) + */ +typedef struct { + __IO uint32_t ID; /*!< CAN Message ID Field Register */ + uint32_t RESERVED0; + __IO uint32_t TSVMCF; /*!< CAN Time Stamp Values/ Message Control Filed Register*/ + uint32_t RESERVED1; + __IO uint32_t DL; /*!< CAN Data Filed Register (DL) */ + uint32_t RESERVED2; + __IO uint32_t DH; /*!< CAN Data Filed Register (DH) */ +} TSB_CANAMB_TypeDef; + +/** + * @brief CAN Controller Mailbox RAM (CANMB) + */ +typedef struct { + __IO uint32_t ID; /*!< CAN Message ID Field Register */ + uint32_t RESERVED0; + __IO uint32_t TSVMCF; /*!< CAN Time Stamp Values/ Message Control Filed Register*/ + uint32_t RESERVED1; + __IO uint32_t DL; /*!< CAN Data Filed Register (DL) */ + uint32_t RESERVED2; + __IO uint32_t DH; /*!< CAN Data Filed Register (DH) */ +} TSB_CANBMB_TypeDef; + +/** + * @brief CAN Controller (CAN) + */ +typedef struct { + __IO uint32_t MC; /*!< CAN Mailbox Configuration Register */ + uint32_t RESERVED0; + __IO uint32_t MD; /*!< CAN Mailbox Direction Register */ + uint32_t RESERVED1; + __IO uint32_t TRS; /*!< CAN Transmission Request Set Register */ + uint32_t RESERVED2; + __IO uint32_t TRR; /*!< CAN Transmission Request Reset Register */ + uint32_t RESERVED3; + __IO uint32_t TA; /*!< CAN Transmission Acknowledge Register */ + uint32_t RESERVED4; + __IO uint32_t AA; /*!< CAN Abort Acknowledge Register */ + uint32_t RESERVED5; + __IO uint32_t RMP; /*!< CAN Receive Message Pending Register */ + uint32_t RESERVED6; + __IO uint32_t RML; /*!< CAN Receive Message Lost Register */ + uint32_t RESERVED7; + __IO uint32_t LAM; /*!< CAN Local Acceptance Mask Register */ + uint32_t RESERVED8; + __IO uint32_t GAM; /*!< CAN Global Acceptance Mask Register */ + uint32_t RESERVED9; + __IO uint32_t MCR; /*!< CAN Master Control Register */ + uint32_t RESERVED10; + __I uint32_t GSR; /*!< CAN Global Status Register */ + uint32_t RESERVED11; + __IO uint32_t BCR1; /*!< CAN Bit Configuration Register 1 */ + uint32_t RESERVED12; + __IO uint32_t BCR2; /*!< CAN Bit Configuration Register 2 */ + uint32_t RESERVED13; + __IO uint32_t GIF; /*!< CAN Global Interrupt Flag Register */ + uint32_t RESERVED14; + __IO uint32_t GIM; /*!< CAN Global Interrupt Mask Register */ + uint32_t RESERVED15; + __IO uint32_t MBTIF; /*!< CAN Mailbox Transmit Interrupt Flag Register */ + uint32_t RESERVED16; + __IO uint32_t MBRIF; /*!< CAN Mailbox Receive Interrupt Flag Register */ + uint32_t RESERVED17; + __IO uint32_t MBIM; /*!< CAN Mailbox Interrupt Mask Register */ + uint32_t RESERVED18; + __IO uint32_t CDR; /*!< CAN Change Data Request Register */ + uint32_t RESERVED19; + __IO uint32_t RFP; /*!< CAN Remote Frame Pending Register */ + uint32_t RESERVED20; + __IO uint32_t CEC; /*!< CAN Error Counter Register */ + uint32_t RESERVED21; + __IO uint32_t TSP; /*!< CAN Time Stamp Counter Prescaler Register */ + uint32_t RESERVED22; + __I uint32_t TSC; /*!< CAN Time Stamp Counter Register */ +} TSB_CAN_TypeDef; + +/** + * @brief Ether Mac + */ +typedef struct { + __IO uint32_t TMAC_CONFIGURATION;/*!< TMAC Configuration Register */ + __IO uint32_t TMAC_FRAME_FILTER; /*!< TMAC Frame Filter Register */ + __IO uint32_t HASH_TABLE_HIGH; /*!< Hash Table High Register */ + __IO uint32_t HASH_TABLE_LOW; /*!< Hash Table Low Register */ + __IO uint32_t MII_ADDRESS; /*!< MII Address Register */ + __IO uint32_t MII_DATA; /*!< MII Data Register */ + __IO uint32_t FLOW_CONTROL; /*!< Flow Control Register */ + __IO uint32_t VLAN_TAG; /*!< VLAN Tag Register */ + uint32_t RESERVED0; + __I uint32_t DEBUG; /*!< Debug Register */ + __IO uint32_t REMOTE_WAKE_UP_FRAME_FILTER;/*!< Remote Wake-Up Frame Filter Register */ + __IO uint32_t PMT_CONTROL_STATUS;/*!< PMT Control and Status Register */ + uint32_t RESERVED1[2]; + __I uint32_t INTERRUPT_STATUS; /*!< Interrupt Status Register */ + __IO uint32_t INTERRUPT_MASK; /*!< Interrupt Mask Register */ + __IO uint32_t MAC_ADDRESS0_HIGH; /*!< MAC Address0 High Register */ + __IO uint32_t MAC_ADDRESS0_LOW; /*!< MAC Address0 Low Register */ + __IO uint32_t MAC_ADDRESS1_HIGH; /*!< MAC Address1 High Register */ + __IO uint32_t MAC_ADDRESS1_LOW; /*!< MAC Address1 Low Register */ + __IO uint32_t MAC_ADDRESS2_HIGH; /*!< MAC Address2 High Register */ + __IO uint32_t MAC_ADDRESS2_LOW; /*!< MAC Address2 Low Register */ + __IO uint32_t MAC_ADDRESS3_HIGH; /*!< MAC Address3 High Register */ + __IO uint32_t MAC_ADDRESS3_LOW; /*!< MAC Address3 Low Register */ + uint32_t RESERVED2[31]; + __IO uint32_t WDOG_TIMEOUT; /*!< Watchdog Timeout Register */ + uint32_t RESERVED3[8]; + __IO uint32_t MMC_CONTROL; /*!< MMC Control Register */ + __I uint32_t MMC_RECEIVE_INTERRUPT;/*!< MMC Receive Interrupt Register */ + __I uint32_t MMC_TRANSMIT_INTERRUPT;/*!< MMC Transmit Interrupt Register */ + __IO uint32_t MMC_RECEIVE_INTERRUPT_MASK;/*!< MMC Receive Interrupt Mask Register */ + __IO uint32_t MMC_TRANSMIT_INTERRUPT_MASK;/*!< MMC Transmit Interrupt Mask Register */ + uint32_t RESERVED4; + __I uint32_t TX_FRAME_COUNT_GOOD_BAD;/*!< Transmit Frame Count for Good and Bad Frames Register*/ + uint32_t RESERVED5[11]; + __I uint32_t TX_UNDERFLOW_ERROR_FRAMES;/*!< Transmit Frame Count for Underflow Error Frames Register*/ + __I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES;/*!< Transmit Frame Count for Frames Transmitted after Single Collision Register*/ + __I uint32_t TX_MULTIPLE_COLLISION_GOOD_FRAMES;/*!< Transmit Frame Count for Frames Transmitted after Multiple Collision Register*/ + uint32_t RESERVED6[5]; + __I uint32_t TX_FRAME_COUNT_GOOD;/*!< Transmit Frame Count for Good Frames Register*/ + uint32_t RESERVED7[5]; + __I uint32_t RX_FRAMES_COUNT_GOOD_BAD;/*!< Receive Frame Count for Good and Bad Frames Register*/ + uint32_t RESERVED8[4]; + __I uint32_t RX_CRC_ERROR_FRAMES;/*!< Receive Frame Count for CRC Error Frames Register*/ + __I uint32_t RX_ALIGNMENT_ERROR_FRAMES;/*!< Receive Frame Count for Alignment Error Frames Register*/ + uint32_t RESERVED9[10]; + __I uint32_t RX_UNICAST_FRAMES_GOOD;/*!< Receive Frame Count for Good Unicast Frames Register*/ + uint32_t RESERVED10[3]; + __I uint32_t RX_FIFO_OVERFLOW_FRAMES;/*!< Receive Frame Count for FIFO Overflow Frames Register*/ + uint32_t RESERVED11[10]; + __IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK;/*!< MMC Receive Checksum Offload Interrupt Mask Register*/ + uint32_t RESERVED12; + __I uint32_t MMC_IPC_RECEIVE_INTERRUPT;/*!< MMC Receive Checksum Offload Interrupt Register*/ + uint32_t RESERVED13[13]; + __I uint32_t RXICMP_GOOD_FRAMES;/*!< Receive ICMP Good Frame Counter Register */ + __I uint32_t RXICMP_ERROR_FRAMES;/*!< Receive ICMP Error Frame Counter Register */ + uint32_t RESERVED14[207]; + __IO uint32_t VLAN_INCL_REG; /*!< VLAN Tag Inclusion or Replacement Register */ + __IO uint32_t VLAN_HASH_TABLE_REG;/*!< VLAN Hash Table Register */ + uint32_t RESERVED15[93]; + __IO uint32_t TIMESTAMP_CONTROL; /*!< Timestamp Control Register */ + __IO uint32_t SUB_SECOND_INCREMENT;/*!< Sub-Second Increment Register */ + __I uint32_t SYSTEM_TIME_SECONDS;/*!< System Time - Seconds Register */ + __I uint32_t SYSTEM_TIME_NANOSECONDS;/*!< System Time - Nanoseconds Register */ + __IO uint32_t SYSTEM_TIME_SECONDS_UPDATE;/*!< System Time - Seconds Update Register */ + __IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE;/*!< System Time - Nanoseconds Update Register */ + __IO uint32_t TIMESTAMP_ADDEND; /*!< Timestamp Addend Register */ + __IO uint32_t TARGET_TIME_SECONDS;/*!< Target Time Seconds Register */ + __IO uint32_t TARGET_TIME_NANOSECONDS;/*!< Target Time Nanoseconds Register */ + __IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS;/*!< System Time - Higher Word Seconds Register */ + __I uint32_t TIMESTAMP_STATUS; /*!< Timestamp Status Register */ + __IO uint32_t PPS_CONTROL; /*!< PPS Control Register */ + uint32_t RESERVED16[12]; + __IO uint32_t PPS0_INTERVAL; /*!< PPS0 Interval Register */ + __IO uint32_t PPS0_WIDTH; /*!< PPS0 Width Register */ + uint32_t RESERVED17[6]; + __IO uint32_t PPS1_TARGET_TIME_SECONDS;/*!< PPS1 Target Time Seconds Register */ + __IO uint32_t PPS1_TARGET_TIME_NANOSECONDS;/*!< PPS1 Target Time NanoSeconds Register */ + __IO uint32_t PPS1_INTERVAL; /*!< PPS1 Interval Register */ + __IO uint32_t PPS1_WIDTH; /*!< PPS1 Width Register */ + uint32_t RESERVED18[540]; + __IO uint32_t BUS_MODE; /*!< Bus Mode Register */ + __IO uint32_t TRANSMIT_POLL_DEMAND;/*!< Transmit Poll Demand Register */ + __IO uint32_t RECEIVE_POLL_DEMAND;/*!< Receive Poll Demand Register */ + __IO uint32_t RECEIVE_DESCRIPTOR_LIST_ADDRESS;/*!< Receive Descriptor List Address Register */ + __IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS;/*!< Transmit Descriptor List Address Register */ + __IO uint32_t STATUS; /*!< Status Register */ + __IO uint32_t OPERATION_MODE; /*!< Operation Mode Register */ + __IO uint32_t INTERRUPT_ENABLE; /*!< Interrupt Enable Register */ + __I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;/*!< Missed Frame and Buffer Overflow Counter Register*/ + __IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER;/*!< Receive Interrupt Watchdog Timer Register */ + uint32_t RESERVED19; + __I uint32_t AHB_STATUS; /*!< AHB Status Register */ + uint32_t RESERVED20[6]; + __I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR;/*!< Current Host Transmit Descriptor Register */ + __I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR;/*!< Current Host Receive Descriptor Register */ + __I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;/*!< Current Host Transmit Buffer Address Register*/ + __I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;/*!< Current Host Receive Buffer Address Register */ + uint32_t RESERVED21[490]; + __IO uint32_t MAC_CTRL0; /*!< Ether Mac Control Register 0 */ + __IO uint32_t MAC_CTRL1; /*!< Ether Mac Control Register 1 */ + __IO uint32_t MAC_CTRL2; /*!< Ether Mac Control Register 2 */ +} TSB_EM_TypeDef; + +/** + * @brief SMIF + */ +typedef struct { + __IO uint32_t MAP0; /*!< SMIF Address Map Control Register 0 */ + __IO uint32_t MAP1; /*!< SMIF Address Map Control Register 1 */ + __IO uint32_t DACR0; /*!< SMIF Direct Access Control Register 0 */ + __IO uint32_t DACR1; /*!< SMIF Direct Access Control Register 1 */ + __IO uint32_t DRCR0; /*!< SMIF Direct Read Control Register 0 */ + __IO uint32_t DRCR1; /*!< SMIF Direct Read Control Register 1 */ + __IO uint32_t DWCR0; /*!< SMIF Direct Write Control Register 0 */ + __IO uint32_t DWCR1; /*!< SMIF Direct Write Control Register 1 */ + uint32_t RESERVED0[248]; + __IO uint32_t RACR0; /*!< SMIF Indirect Access Control Register 0 */ + __IO uint32_t RACR1; /*!< SMIF Indirect Access Control Register 1 */ + __IO uint32_t IOCR; /*!< SMIF Indirect Access I/O Control Register */ + __IO uint32_t OECR; /*!< SMIF Indirect Access Output Enable Register */ + uint32_t RESERVED1[12]; + __IO uint32_t INT; /*!< SMIF Interrupt Control Register */ + __IO uint32_t STAT; /*!< SMIF Status Register */ + uint32_t RESERVED2[14]; + __IO uint32_t SWR; /*!< SMIF Software Reset Register */ + __IO uint32_t ACKR; /*!< SMIF Additional Clock Control Register */ + __IO uint32_t CCOR; /*!< SMIF Serial Clock, CS pin Direction Control Register*/ + __IO uint32_t STPR; /*!< SMIF Forced Stop Control Register */ + uint32_t RESERVED3[28]; + __IO uint32_t PBUF0; /*!< SMIF Indirect Access Primary Buffer Register 0*/ + __IO uint32_t PBUF1; /*!< SMIF Indirect Access Primary Buffer Register 1*/ + __IO uint32_t PBUF2; /*!< SMIF Indirect Access Primary Buffer Register 2*/ + __IO uint32_t PBUF3; /*!< SMIF Indirect Access Primary Buffer Register 3*/ + __IO uint32_t PBUF4; /*!< SMIF Indirect Access Primary Buffer Register 4*/ + __IO uint32_t PBUF5; /*!< SMIF Indirect Access Primary Buffer Register 5*/ + __IO uint32_t PBUF6; /*!< SMIF Indirect Access Primary Buffer Register 6*/ + __IO uint32_t PBUF7; /*!< SMIF Indirect Access Primary Buffer Register 7*/ + uint32_t RESERVED4[56]; + __IO uint32_t SBUF00; /*!< SMIF Indirect Access Secondary Buffer Register 00*/ + __IO uint32_t SBUF01; /*!< SMIF Indirect Access Secondary Buffer Register 01*/ + __IO uint32_t SBUF02; /*!< SMIF Indirect Access Secondary Buffer Register 02*/ + __IO uint32_t SBUF03; /*!< SMIF Indirect Access Secondary Buffer Register 03*/ + __IO uint32_t SBUF04; /*!< SMIF Indirect Access Secondary Buffer Register 04*/ + __IO uint32_t SBUF05; /*!< SMIF Indirect Access Secondary Buffer Register 05*/ + __IO uint32_t SBUF06; /*!< SMIF Indirect Access Secondary Buffer Register 06*/ + __IO uint32_t SBUF07; /*!< SMIF Indirect Access Secondary Buffer Register 07*/ + __IO uint32_t SBUF08; /*!< SMIF Indirect Access Secondary Buffer Register 08*/ + __IO uint32_t SBUF09; /*!< SMIF Indirect Access Secondary Buffer Register 09*/ + __IO uint32_t SBUF10; /*!< SMIF Indirect Access Secondary Buffer Register 10*/ + __IO uint32_t SBUF11; /*!< SMIF Indirect Access Secondary Buffer Register 11*/ + __IO uint32_t SBUF12; /*!< SMIF Indirect Access Secondary Buffer Register 12*/ + __IO uint32_t SBUF13; /*!< SMIF Indirect Access Secondary Buffer Register 13*/ + __IO uint32_t SBUF14; /*!< SMIF Indirect Access Secondary Buffer Register 14*/ + __IO uint32_t SBUF15; /*!< SMIF Indirect Access Secondary Buffer Register 15*/ + __IO uint32_t SBUF16; /*!< SMIF Indirect Access Secondary Buffer Register 16*/ + __IO uint32_t SBUF17; /*!< SMIF Indirect Access Secondary Buffer Register 17*/ + __IO uint32_t SBUF18; /*!< SMIF Indirect Access Secondary Buffer Register 18*/ + __IO uint32_t SBUF19; /*!< SMIF Indirect Access Secondary Buffer Register 19*/ + __IO uint32_t SBUF20; /*!< SMIF Indirect Access Secondary Buffer Register 20*/ + __IO uint32_t SBUF21; /*!< SMIF Indirect Access Secondary Buffer Register 21*/ + __IO uint32_t SBUF22; /*!< SMIF Indirect Access Secondary Buffer Register 22*/ + __IO uint32_t SBUF23; /*!< SMIF Indirect Access Secondary Buffer Register 23*/ + __IO uint32_t SBUF24; /*!< SMIF Indirect Access Secondary Buffer Register 24*/ + __IO uint32_t SBUF25; /*!< SMIF Indirect Access Secondary Buffer Register 25*/ + __IO uint32_t SBUF26; /*!< SMIF Indirect Access Secondary Buffer Register 26*/ + __IO uint32_t SBUF27; /*!< SMIF Indirect Access Secondary Buffer Register 27*/ + __IO uint32_t SBUF28; /*!< SMIF Indirect Access Secondary Buffer Register 28*/ + __IO uint32_t SBUF29; /*!< SMIF Indirect Access Secondary Buffer Register 29*/ + __IO uint32_t SBUF30; /*!< SMIF Indirect Access Secondary Buffer Register 30*/ + __IO uint32_t SBUF31; /*!< SMIF Indirect Access Secondary Buffer Register 31*/ + __IO uint32_t SBUF32; /*!< SMIF Indirect Access Secondary Buffer Register 32*/ + __IO uint32_t SBUF33; /*!< SMIF Indirect Access Secondary Buffer Register 33*/ + __IO uint32_t SBUF34; /*!< SMIF Indirect Access Secondary Buffer Register 34*/ + __IO uint32_t SBUF35; /*!< SMIF Indirect Access Secondary Buffer Register 35*/ + __IO uint32_t SBUF36; /*!< SMIF Indirect Access Secondary Buffer Register 36*/ + __IO uint32_t SBUF37; /*!< SMIF Indirect Access Secondary Buffer Register 37*/ + __IO uint32_t SBUF38; /*!< SMIF Indirect Access Secondary Buffer Register 38*/ + __IO uint32_t SBUF39; /*!< SMIF Indirect Access Secondary Buffer Register 39*/ + __IO uint32_t SBUF40; /*!< SMIF Indirect Access Secondary Buffer Register 40*/ + __IO uint32_t SBUF41; /*!< SMIF Indirect Access Secondary Buffer Register 41*/ + __IO uint32_t SBUF42; /*!< SMIF Indirect Access Secondary Buffer Register 42*/ + __IO uint32_t SBUF43; /*!< SMIF Indirect Access Secondary Buffer Register 43*/ + __IO uint32_t SBUF44; /*!< SMIF Indirect Access Secondary Buffer Register 44*/ + __IO uint32_t SBUF45; /*!< SMIF Indirect Access Secondary Buffer Register 45*/ + __IO uint32_t SBUF46; /*!< SMIF Indirect Access Secondary Buffer Register 46*/ + __IO uint32_t SBUF47; /*!< SMIF Indirect Access Secondary Buffer Register 47*/ + __IO uint32_t SBUF48; /*!< SMIF Indirect Access Secondary Buffer Register 48*/ + __IO uint32_t SBUF49; /*!< SMIF Indirect Access Secondary Buffer Register 49*/ + __IO uint32_t SBUF50; /*!< SMIF Indirect Access Secondary Buffer Register 50*/ + __IO uint32_t SBUF51; /*!< SMIF Indirect Access Secondary Buffer Register 51*/ + __IO uint32_t SBUF52; /*!< SMIF Indirect Access Secondary Buffer Register 52*/ + __IO uint32_t SBUF53; /*!< SMIF Indirect Access Secondary Buffer Register 53*/ + __IO uint32_t SBUF54; /*!< SMIF Indirect Access Secondary Buffer Register 54*/ + __IO uint32_t SBUF55; /*!< SMIF Indirect Access Secondary Buffer Register 55*/ + __IO uint32_t SBUF56; /*!< SMIF Indirect Access Secondary Buffer Register 56*/ + __IO uint32_t SBUF57; /*!< SMIF Indirect Access Secondary Buffer Register 57*/ + __IO uint32_t SBUF58; /*!< SMIF Indirect Access Secondary Buffer Register 58*/ + __IO uint32_t SBUF59; /*!< SMIF Indirect Access Secondary Buffer Register 59*/ + __IO uint32_t SBUF60; /*!< SMIF Indirect Access Secondary Buffer Register 60*/ + __IO uint32_t SBUF61; /*!< SMIF Indirect Access Secondary Buffer Register 61*/ + __IO uint32_t SBUF62; /*!< SMIF Indirect Access Secondary Buffer Register 62*/ + __IO uint32_t SBUF63; /*!< SMIF Indirect Access Secondary Buffer Register 63*/ +} TSB_SMI_TypeDef; + +/** + * @brief Interrupt Control Registers A + */ +typedef struct { + __IO uint8_t NIC00; /*!< Non-maskable Interrupt A Control Register 00 */ + uint8_t RESERVED0[31]; + __IO uint8_t IMC00; /*!< Interrupt A Mode Control Register 00 */ + __IO uint8_t IMC01; /*!< Interrupt A Mode Control Register 01 */ + __IO uint8_t IMC02; /*!< Interrupt A Mode Control Register 02 */ + __IO uint8_t IMC03; /*!< Interrupt A Mode Control Register 03 */ + __IO uint8_t IMC04; /*!< Interrupt A Mode Control Register 04 */ + __IO uint8_t IMC05; /*!< Interrupt A Mode Control Register 05 */ + __IO uint8_t IMC06; /*!< Interrupt A Mode Control Register 06 */ + __IO uint8_t IMC07; /*!< Interrupt A Mode Control Register 07 */ + __IO uint8_t IMC08; /*!< Interrupt A Mode Control Register 08 */ + __IO uint8_t IMC09; /*!< Interrupt A Mode Control Register 09 */ + __IO uint8_t IMC10; /*!< Interrupt A Mode Control Register 10 */ + __IO uint8_t IMC11; /*!< Interrupt A Mode Control Register 11 */ + uint8_t RESERVED1; + __IO uint8_t IMC13; /*!< Interrupt A Mode Control Register 13 */ + uint8_t RESERVED2; + __IO uint8_t IMC15; /*!< Interrupt A Mode Control Register 15 */ + __IO uint8_t IMC16; /*!< Interrupt A Mode Control Register 16 */ + __IO uint8_t IMC17; /*!< Interrupt A Mode Control Register 17 */ + __IO uint8_t IMC18; /*!< Interrupt A Mode Control Register 18 */ + __IO uint8_t IMC19; /*!< Interrupt A Mode Control Register 19 */ + __IO uint8_t IMC20; /*!< Interrupt A Mode Control Register 20 */ + __IO uint8_t IMC21; /*!< Interrupt A Mode Control Register 21 */ + __IO uint8_t IMC22; /*!< Interrupt A Mode Control Register 22 */ + __IO uint8_t IMC23; /*!< Interrupt A Mode Control Register 23 */ + uint8_t RESERVED3; + __IO uint8_t IMC25; /*!< Interrupt A Mode Control Register 25 */ + uint8_t RESERVED4; + __IO uint8_t IMC27; /*!< Interrupt A Mode Control Register 27 */ + __IO uint8_t IMC28; /*!< Interrupt A Mode Control Register 28 */ + __IO uint8_t IMC29; /*!< Interrupt A Mode Control Register 29 */ + __IO uint8_t IMC30; /*!< Interrupt A Mode Control Register 30 */ + __IO uint8_t IMC31; /*!< Interrupt A Mode Control Register 31 */ + uint8_t RESERVED5[17]; + __IO uint8_t IMC49; /*!< Interrupt A Mode Control Register 49 */ + __IO uint8_t IMC50; /*!< Interrupt A Mode Control Register 50 */ + __IO uint8_t IMC51; /*!< Interrupt A Mode Control Register 51 */ + __IO uint8_t IMC52; /*!< Interrupt A Mode Control Register 52 */ + __IO uint8_t IMC53; /*!< Interrupt A Mode Control Register 53 */ + __IO uint8_t IMC54; /*!< Interrupt A Mode Control Register 54 */ + __IO uint8_t IMC55; /*!< Interrupt A Mode Control Register 55 */ + __IO uint8_t IMC56; /*!< Interrupt A Mode Control Register 56 */ + __IO uint8_t IMC57; /*!< Interrupt A Mode Control Register 57 */ +} TSB_IA_TypeDef; + +/** + * @brief Low speed oscillation/power control/reset + */ +typedef struct { + __IO uint8_t LOSCCR; /*!< Low speed oscillation and Internal High speed oscillation 2 clock control register*/ + __IO uint8_t SHTDNOP; /*!< Power supply cut off control register */ + __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ + __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ + uint8_t RESERVED0[11]; + __IO uint8_t PROTECT; /*!< RLM write protection register */ +} TSB_RLM_TypeDef; + +/** + * @brief LVD0 + */ +typedef struct { + __IO uint8_t CR1; /*!< LVD Control Register1 */ + __IO uint8_t CR2; /*!< LVD Control Register2 */ + __IO uint8_t LVL1; /*!< LVD Detection Voltage Select Register 1 */ + uint8_t RESERVED0; + __I uint8_t SR; /*!< LVD Status Register */ +} TSB_LVD_TypeDef; + +/** + * @brief TRGSEL + */ +typedef struct { + __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ + __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ + __IO uint32_t CR2; /*!< TSEL Control register 2 */ + __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ + __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ + __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ + __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ + __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ + __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ + __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ + __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ + __IO uint32_t CR11; /*!< TRGSEL Control register 11 */ + __IO uint32_t CR12; /*!< TRGSEL Control register 12 */ + __IO uint32_t CR13; /*!< TRGSEL Control register 13 */ + __IO uint32_t CR14; /*!< TRGSEL Control register 14 */ +} TSB_TSEL_TypeDef; + +/** + * @brief Long Term Timer(LTTMR) + */ +typedef struct { + __IO uint8_t CR0; /*!< LTTMR Control Register */ + __IO uint8_t VALL; /*!< LTTMR Data Register (Lower) */ + __IO uint8_t VALH; /*!< LTTMR Data Register (Upper) */ +} TSB_LTT_TypeDef; + +/** + * @brief Serial Interface (TSPI) + */ +typedef struct { + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + __IO uint32_t SECTCR0; /*!< TSPI Sector mode Control Register 0 */ + __IO uint32_t SECTCR1; /*!< TSPI Sector mode Control Register 1 */ + uint32_t RESERVED0[55]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Error Flag Register */ +} TSB_TSPI_TypeDef; + +/** + * @brief External Bus Interface(EXB) + */ +typedef struct { + __IO uint32_t MOD; /*!< EBIF Mode Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t AS0; /*!< EBIF Area and Start Address Configuration Register 0*/ + __IO uint32_t AS1; /*!< EBIF Area and Start Address Configuration Register 1*/ + __IO uint32_t AS2; /*!< EBIF Area and Start Address Configuration Register 2*/ + __IO uint32_t AS3; /*!< EBIF Area and Start Address Configuration Register 3*/ + uint32_t RESERVED1[8]; + __IO uint32_t CS0; /*!< EBIF Chip Select Control Register 0 */ + __IO uint32_t CS1; /*!< EBIF Chip Select Control Register 1 */ + __IO uint32_t CS2; /*!< EBIF Chip Select Control Register 2 */ + __IO uint32_t CS3; /*!< EBIF Chip Select Control Register 3 */ + uint32_t RESERVED2[4]; + __IO uint32_t CLKCTL; /*!< EBIF Clock Output Control Register */ +} TSB_EXB_TypeDef; + +/** + * @brief Clock Generator (CG) + */ +typedef struct { + __IO uint32_t PROTECT; /*!< CG write protection register */ + __IO uint32_t OSCCR; /*!< CG Oscillation control register */ + __IO uint32_t SYSCR; /*!< CG System clock control register */ + __IO uint32_t STBYCR; /*!< CG Standby control register */ + uint32_t RESERVED0[4]; + __IO uint32_t PLL0SEL; /*!< CG PLL selection register for fsys */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< CG High speed oscillation warming up register*/ + __IO uint32_t WUPLCR; /*!< CG Low speed oscillation warming up register */ + uint32_t RESERVED2[3]; + __IO uint32_t FSYSMENC; /*!< CG Middle speed clock supply and stop register C for fsys*/ + __IO uint32_t FSYSMENA; /*!< CG Middle speed clock supply and stop register A for fsys*/ + __IO uint32_t FSYSMENB; /*!< CG Middle speed clock supply and stop register B for fsys*/ + __IO uint32_t FSYSENA; /*!< CG High speed clock supply and stop register A for fsys*/ + uint32_t RESERVED3; + __IO uint32_t FCEN; /*!< CG Clock supply and stop register for fc */ + __IO uint32_t SPCLKEN; /*!< CG Clock supply for ADC and Trace Register */ + uint32_t RESERVED4[2]; + __IO uint32_t EXTEND2; /*!< CG Function extension register 2 */ +} TSB_CG_TypeDef; + +/** + * @brief Interrupt Control Register B + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint8_t NIC00; /*!< Non-maskable Interrupt B Control Register 00 */ + uint8_t RESERVED1[79]; + __IO uint8_t IMC000; /*!< Interrupt B Mode Control Register 000 */ + __IO uint8_t IMC001; /*!< Interrupt B Mode Control Register 001 */ + __IO uint8_t IMC002; /*!< Interrupt B Mode Control Register 002 */ + __IO uint8_t IMC003; /*!< Interrupt B Mode Control Register 003 */ + __IO uint8_t IMC004; /*!< Interrupt B Mode Control Register 004 */ + __IO uint8_t IMC005; /*!< Interrupt B Mode Control Register 005 */ + __IO uint8_t IMC006; /*!< Interrupt B Mode Control Register 006 */ + __IO uint8_t IMC007; /*!< Interrupt B Mode Control Register 007 */ + __IO uint8_t IMC008; /*!< Interrupt B Mode Control Register 008 */ + __IO uint8_t IMC009; /*!< Interrupt B Mode Control Register 009 */ + __IO uint8_t IMC010; /*!< Interrupt B Mode Control Register 010 */ + __IO uint8_t IMC011; /*!< Interrupt B Mode Control Register 011 */ + __IO uint8_t IMC012; /*!< Interrupt B Mode Control Register 012 */ + __IO uint8_t IMC013; /*!< Interrupt B Mode Control Register 013 */ + __IO uint8_t IMC014; /*!< Interrupt B Mode Control Register 014 */ + __IO uint8_t IMC015; /*!< Interrupt B Mode Control Register 015 */ + __IO uint8_t IMC016; /*!< Interrupt B Mode Control Register 016 */ + __IO uint8_t IMC017; /*!< Interrupt B Mode Control Register 017 */ + __IO uint8_t IMC018; /*!< Interrupt B Mode Control Register 018 */ + __IO uint8_t IMC019; /*!< Interrupt B Mode Control Register 019 */ + __IO uint8_t IMC020; /*!< Interrupt B Mode Control Register 020 */ + __IO uint8_t IMC021; /*!< Interrupt B Mode Control Register 021 */ + __IO uint8_t IMC022; /*!< Interrupt B Mode Control Register 022 */ + __IO uint8_t IMC023; /*!< Interrupt B Mode Control Register 023 */ + __IO uint8_t IMC024; /*!< Interrupt B Mode Control Register 024 */ + __IO uint8_t IMC025; /*!< Interrupt B Mode Control Register 025 */ + __IO uint8_t IMC026; /*!< Interrupt B Mode Control Register 026 */ + __IO uint8_t IMC027; /*!< Interrupt B Mode Control Register 027 */ + __IO uint8_t IMC028; /*!< Interrupt B Mode Control Register 028 */ + __IO uint8_t IMC029; /*!< Interrupt B Mode Control Register 029 */ + __IO uint8_t IMC030; /*!< Interrupt B Mode Control Register 030 */ + __IO uint8_t IMC031; /*!< Interrupt B Mode Control Register 031 */ + __IO uint8_t IMC032; /*!< Interrupt B Mode Control Register 032 */ + __IO uint8_t IMC033; /*!< Interrupt B Mode Control Register 033 */ + __IO uint8_t IMC034; /*!< Interrupt B Mode Control Register 034 */ + __IO uint8_t IMC035; /*!< Interrupt B Mode Control Register 035 */ + __IO uint8_t IMC036; /*!< Interrupt B Mode Control Register 036 */ + __IO uint8_t IMC037; /*!< Interrupt B Mode Control Register 037 */ + __IO uint8_t IMC038; /*!< Interrupt B Mode Control Register 038 */ + __IO uint8_t IMC039; /*!< Interrupt B Mode Control Register 039 */ + __IO uint8_t IMC040; /*!< Interrupt B Mode Control Register 040 */ + __IO uint8_t IMC041; /*!< Interrupt B Mode Control Register 041 */ + __IO uint8_t IMC042; /*!< Interrupt B Mode Control Register 042 */ + __IO uint8_t IMC043; /*!< Interrupt B Mode Control Register 043 */ + __IO uint8_t IMC044; /*!< Interrupt B Mode Control Register 044 */ + __IO uint8_t IMC045; /*!< Interrupt B Mode Control Register 045 */ + __IO uint8_t IMC046; /*!< Interrupt B Mode Control Register 046 */ + __IO uint8_t IMC047; /*!< Interrupt B Mode Control Register 047 */ + __IO uint8_t IMC048; /*!< Interrupt B Mode Control Register 048 */ + __IO uint8_t IMC049; /*!< Interrupt B Mode Control Register 049 */ + __IO uint8_t IMC050; /*!< Interrupt B Mode Control Register 050 */ + __IO uint8_t IMC051; /*!< Interrupt B Mode Control Register 051 */ + __IO uint8_t IMC052; /*!< Interrupt B Mode Control Register 052 */ + __IO uint8_t IMC053; /*!< Interrupt B Mode Control Register 053 */ + __IO uint8_t IMC054; /*!< Interrupt B Mode Control Register 054 */ + __IO uint8_t IMC055; /*!< Interrupt B Mode Control Register 055 */ + __IO uint8_t IMC056; /*!< Interrupt B Mode Control Register 056 */ + __IO uint8_t IMC057; /*!< Interrupt B Mode Control Register 057 */ + __IO uint8_t IMC058; /*!< Interrupt B Mode Control Register 058 */ + __IO uint8_t IMC059; /*!< Interrupt B Mode Control Register 059 */ + __IO uint8_t IMC060; /*!< Interrupt B Mode Control Register 060 */ + __IO uint8_t IMC061; /*!< Interrupt B Mode Control Register 061 */ + __IO uint8_t IMC062; /*!< Interrupt B Mode Control Register 062 */ + __IO uint8_t IMC063; /*!< Interrupt B Mode Control Register 063 */ + __IO uint8_t IMC064; /*!< Interrupt B Mode Control Register 064 */ + __IO uint8_t IMC065; /*!< Interrupt B Mode Control Register 065 */ + __IO uint8_t IMC066; /*!< Interrupt B Mode Control Register 066 */ + __IO uint8_t IMC067; /*!< Interrupt B Mode Control Register 067 */ + __IO uint8_t IMC068; /*!< Interrupt B Mode Control Register 068 */ + __IO uint8_t IMC069; /*!< Interrupt B Mode Control Register 069 */ + __IO uint8_t IMC070; /*!< Interrupt B Mode Control Register 070 */ + __IO uint8_t IMC071; /*!< Interrupt B Mode Control Register 071 */ + __IO uint8_t IMC072; /*!< Interrupt B Mode Control Register 072 */ + __IO uint8_t IMC073; /*!< Interrupt B Mode Control Register 073 */ + __IO uint8_t IMC074; /*!< Interrupt B Mode Control Register 074 */ + __IO uint8_t IMC075; /*!< Interrupt B Mode Control Register 075 */ + __IO uint8_t IMC076; /*!< Interrupt B Mode Control Register 076 */ + __IO uint8_t IMC077; /*!< Interrupt B Mode Control Register 077 */ + __IO uint8_t IMC078; /*!< Interrupt B Mode Control Register 078 */ + __IO uint8_t IMC079; /*!< Interrupt B Mode Control Register 079 */ + __IO uint8_t IMC080; /*!< Interrupt B Mode Control Register 080 */ + __IO uint8_t IMC081; /*!< Interrupt B Mode Control Register 081 */ + __IO uint8_t IMC082; /*!< Interrupt B Mode Control Register 082 */ + __IO uint8_t IMC083; /*!< Interrupt B Mode Control Register 083 */ + __IO uint8_t IMC084; /*!< Interrupt B Mode Control Register 084 */ + __IO uint8_t IMC085; /*!< Interrupt B Mode Control Register 085 */ + __IO uint8_t IMC086; /*!< Interrupt B Mode Control Register 086 */ + __IO uint8_t IMC087; /*!< Interrupt B Mode Control Register 087 */ + __IO uint8_t IMC088; /*!< Interrupt B Mode Control Register 088 */ + __IO uint8_t IMC089; /*!< Interrupt B Mode Control Register 089 */ + __IO uint8_t IMC090; /*!< Interrupt B Mode Control Register 090 */ + __IO uint8_t IMC091; /*!< Interrupt B Mode Control Register 091 */ + __IO uint8_t IMC092; /*!< Interrupt B Mode Control Register 092 */ + __IO uint8_t IMC093; /*!< Interrupt B Mode Control Register 093 */ + __IO uint8_t IMC094; /*!< Interrupt B Mode Control Register 094 */ + __IO uint8_t IMC095; /*!< Interrupt B Mode Control Register 095 */ + __IO uint8_t IMC096; /*!< Interrupt B Mode Control Register 096 */ + __IO uint8_t IMC097; /*!< Interrupt B Mode Control Register 097 */ + __IO uint8_t IMC098; /*!< Interrupt B Mode Control Register 098 */ + __IO uint8_t IMC099; /*!< Interrupt B Mode Control Register 099 */ + __IO uint8_t IMC100; /*!< Interrupt B Mode Control Register 100 */ + __IO uint8_t IMC101; /*!< Interrupt B Mode Control Register 101 */ + __IO uint8_t IMC102; /*!< Interrupt B Mode Control Register 102 */ + __IO uint8_t IMC103; /*!< Interrupt B Mode Control Register 103 */ + __IO uint8_t IMC104; /*!< Interrupt B Mode Control Register 104 */ + __IO uint8_t IMC105; /*!< Interrupt B Mode Control Register 105 */ + __IO uint8_t IMC106; /*!< Interrupt B Mode Control Register 106 */ + __IO uint8_t IMC107; /*!< Interrupt B Mode Control Register 107 */ + __IO uint8_t IMC108; /*!< Interrupt B Mode Control Register 108 */ + __IO uint8_t IMC109; /*!< Interrupt B Mode Control Register 109 */ + __IO uint8_t IMC110; /*!< Interrupt B Mode Control Register 110 */ + __IO uint8_t IMC111; /*!< Interrupt B Mode Control Register 111 */ + __IO uint8_t IMC112; /*!< Interrupt B Mode Control Register 112 */ + __IO uint8_t IMC113; /*!< Interrupt B Mode Control Register 113 */ + __IO uint8_t IMC114; /*!< Interrupt B Mode Control Register 114 */ + __IO uint8_t IMC115; /*!< Interrupt B Mode Control Register 115 */ + __IO uint8_t IMC116; /*!< Interrupt B Mode Control Register 116 */ + __IO uint8_t IMC117; /*!< Interrupt B Mode Control Register 117 */ + __IO uint8_t IMC118; /*!< Interrupt B Mode Control Register 118 */ + __IO uint8_t IMC119; /*!< Interrupt B Mode Control Register 119 */ + __IO uint8_t IMC120; /*!< Interrupt B Mode Control Register 120 */ + __IO uint8_t IMC121; /*!< Interrupt B Mode Control Register 121 */ + __IO uint8_t IMC122; /*!< Interrupt B Mode Control Register 122 */ + __IO uint8_t IMC123; /*!< Interrupt B Mode Control Register 123 */ + __IO uint8_t IMC124; /*!< Interrupt B Mode Control Register 124 */ + __IO uint8_t IMC125; /*!< Interrupt B Mode Control Register 125 */ + __IO uint8_t IMC126; /*!< Interrupt B Mode Control Register 126 */ + __IO uint8_t IMC127; /*!< Interrupt B Mode Control Register 127 */ + __IO uint8_t IMC128; /*!< Interrupt B Mode Control Register 128 */ + __IO uint8_t IMC129; /*!< Interrupt B Mode Control Register 129 */ + __IO uint8_t IMC130; /*!< Interrupt B Mode Control Register 130 */ + __IO uint8_t IMC131; /*!< Interrupt B Mode Control Register 131 */ + __IO uint8_t IMC132; /*!< Interrupt B Mode Control Register 132 */ + __IO uint8_t IMC133; /*!< Interrupt B Mode Control Register 133 */ + __IO uint8_t IMC134; /*!< Interrupt B Mode Control Register 134 */ + __IO uint8_t IMC135; /*!< Interrupt B Mode Control Register 135 */ + __IO uint8_t IMC136; /*!< Interrupt B Mode Control Register 136 */ + __IO uint8_t IMC137; /*!< Interrupt B Mode Control Register 137 */ + __IO uint8_t IMC138; /*!< Interrupt B Mode Control Register 138 */ + __IO uint8_t IMC139; /*!< Interrupt B Mode Control Register 139 */ + __IO uint8_t IMC140; /*!< Interrupt B Mode Control Register 140 */ + __IO uint8_t IMC141; /*!< Interrupt B Mode Control Register 141 */ + __IO uint8_t IMC142; /*!< Interrupt B Mode Control Register 142 */ + __IO uint8_t IMC143; /*!< Interrupt B Mode Control Register 143 */ + __IO uint8_t IMC144; /*!< Interrupt B Mode Control Register 144 */ + __IO uint8_t IMC145; /*!< Interrupt B Mode Control Register 145 */ + __IO uint8_t IMC146; /*!< Interrupt B Mode Control Register 146 */ + __IO uint8_t IMC147; /*!< Interrupt B Mode Control Register 147 */ + __IO uint8_t IMC148; /*!< Interrupt B Mode Control Register 148 */ + __IO uint8_t IMC149; /*!< Interrupt B Mode Control Register 149 */ + __IO uint8_t IMC150; /*!< Interrupt B Mode Control Register 150 */ + __IO uint8_t IMC151; /*!< Interrupt B Mode Control Register 151 */ + __IO uint8_t IMC152; /*!< Interrupt B Mode Control Register 152 */ + __IO uint8_t IMC153; /*!< Interrupt B Mode Control Register 153 */ + __IO uint8_t IMC154; /*!< Interrupt B Mode Control Register 154 */ + __IO uint8_t IMC155; /*!< Interrupt B Mode Control Register 155 */ + __IO uint8_t IMC156; /*!< Interrupt B Mode Control Register 156 */ + __IO uint8_t IMC157; /*!< Interrupt B Mode Control Register 157 */ + __IO uint8_t IMC158; /*!< Interrupt B Mode Control Register 158 */ + __IO uint8_t IMC159; /*!< Interrupt B Mode Control Register 159 */ +} TSB_IB_TypeDef; + +/** + * @brief Interrupt Monitor Register + */ +typedef struct { + __I uint32_t FLGNMI; /*!< Non-maskable Interrupt Monitor Flag Register Register*/ + __I uint32_t FLG1; /*!< Interrupt Monitor Flag Register 1 (032 - 063)*/ + __I uint32_t FLG2; /*!< Interrupt Monitor Flag Register 2 (064 - 095)*/ + __I uint32_t FLG3; /*!< Interrupt Monitor Flag Register 3 (096 - 127)*/ + __I uint32_t FLG4; /*!< Interrupt Monitor Flag Register 4 (128 - 159)*/ + __I uint32_t FLG5; /*!< Interrupt Monitor Flag Register 5 (160 - 191)*/ + __I uint32_t FLG6; /*!< Interrupt Monitor Flag Register 6 (192 - 223)*/ + __I uint32_t FLG7; /*!< Interrupt Monitor Flag Register 7 (224 - 255)*/ +} TSB_IMN_TypeDef; + +/** + * @brief DNF + */ +typedef struct { + __IO uint32_t CKCR; /*!< DNF Unit A Noise Filter Control Register */ + __IO uint32_t ENCR; /*!< DNF Unit A Noise Filter Enable Register */ +} TSB_DNF_TypeDef; + +/** + * @brief Watchdog Timer (SIWDT) + */ +typedef struct { + __IO uint32_t PRO; /*!< SIWDT Protect Register */ + __IO uint32_t EN; /*!< SIWDT Enable Register */ + __O uint32_t CR; /*!< SIWDT Control Register */ + __IO uint32_t MOD; /*!< SIWDT Mode Register */ + __I uint32_t MONI; /*!< SIWDT Count Monitor Register */ +} TSB_SIWD_TypeDef; + +/** + * @brief NBDIF + */ +typedef struct { + __IO uint32_t CR0; /*!< NBDIF control register 0 */ + __IO uint32_t CR1; /*!< NBDIF control register 1 */ +} TSB_NBD_TypeDef; + +/** + * @brief Malti Porpose Direct Memory Accsess(MDMA) + */ +typedef struct { + uint32_t RESERVED0; + __IO uint32_t CEN; /*!< MDMA Transfer Channel Enable Register */ + __IO uint32_t REQ; /*!< MDMA Transfer Request Register */ + __IO uint32_t SUS; /*!< MDMA Transfer Suspension Register */ + __IO uint32_t ACT; /*!< MDMA Transfer Active Register */ + __IO uint32_t END; /*!< MDMA Transfer End Register */ + __IO uint32_t PRI; /*!< MDMA Transfer Priority Setting Register */ + __IO uint32_t ENE; /*!< MDMA Transfer Completion Interrupt Enable Register*/ + __IO uint32_t DTAB; /*!< MDMA Transfer Descriptor Table Start Address Register*/ + uint32_t RESERVED1; + __I uint32_t CHN; /*!< MDMA Transfer Execution Channel Number Register*/ + __I uint32_t XFTYP; /*!< MDMA Transfer Type Register */ + __I uint32_t XFSAD; /*!< MDMA Transfer Source Address Register */ + __I uint32_t XFDAD; /*!< MDMA Transfer Destination Address Register */ + __I uint32_t XFSIZ; /*!< MDMA Transfer Size Register */ + __I uint32_t DSADS; /*!< MDMA Transfer Descriptor Storage Address Register*/ + __I uint32_t DSNUM; /*!< MDMA Transfer Descriptor Count Register */ + uint32_t RESERVED2; + __IO uint32_t DEND; /*!< MDMA Descriptor End Register */ + __IO uint32_t DENE; /*!< MDMA Descriptor Completion Interrupt Enable Register*/ + __I uint32_t C00XFTYP; /*!< MDMA ch 00 Transfer Type Saving Register */ + __I uint32_t C00XFSAD; /*!< MDMA ch 00 Transfer Source Address Saving Register*/ + __I uint32_t C00XFDAD; /*!< MDMA ch 00 Transfer Destination Address Saving Register*/ + __I uint32_t C00XFSIZ; /*!< MDMA ch 00 Transfer Size Saving Register */ + __I uint32_t C00DSADS; /*!< MDMA ch 00 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C00DSNUM; /*!< MDMA ch 00 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED3[2]; + __I uint32_t C01XFTYP; /*!< MDMA ch 01 Transfer Type Saving Register */ + __I uint32_t C01XFSAD; /*!< MDMA ch 01 Transfer Source Address Saving Register*/ + __I uint32_t C01XFDAD; /*!< MDMA ch 01 Transfer Destination Address Saving Register*/ + __I uint32_t C01XFSIZ; /*!< MDMA ch 01 Transfer Size Saving Register */ + __I uint32_t C01DSADS; /*!< MDMA ch 01 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C01DSNUM; /*!< MDMA ch 01 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED4[2]; + __I uint32_t C02XFTYP; /*!< MDMA ch 02 Transfer Type Saving Register */ + __I uint32_t C02XFSAD; /*!< MDMA ch 02 Transfer Source Address Saving Register*/ + __I uint32_t C02XFDAD; /*!< MDMA ch 02 Transfer Destination Address Saving Register*/ + __I uint32_t C02XFSIZ; /*!< MDMA ch 02 Transfer Size Saving Register */ + __I uint32_t C02DSADS; /*!< MDMA ch 02 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C02DSNUM; /*!< MDMA ch 02 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED5[2]; + __I uint32_t C03XFTYP; /*!< MDMA ch 03 Transfer Type Saving Register */ + __I uint32_t C03XFSAD; /*!< MDMA ch 03 Transfer Source Address Saving Register*/ + __I uint32_t C03XFDAD; /*!< MDMA ch 03 Transfer Destination Address Saving Register*/ + __I uint32_t C03XFSIZ; /*!< MDMA ch 03 Transfer Size Saving Register */ + __I uint32_t C03DSADS; /*!< MDMA ch 03 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C03DSNUM; /*!< MDMA ch 03 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED6[2]; + __I uint32_t C04XFTYP; /*!< MDMA ch 04 Transfer Type Saving Register */ + __I uint32_t C04XFSAD; /*!< MDMA ch 04 Transfer Source Address Saving Register*/ + __I uint32_t C04XFDAD; /*!< MDMA ch 04 Transfer Destination Address Saving Register*/ + __I uint32_t C04XFSIZ; /*!< MDMA ch 04 Transfer Size Saving Register */ + __I uint32_t C04DSADS; /*!< MDMA ch 04 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C04DSNUM; /*!< MDMA ch 04 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED7[2]; + __I uint32_t C05XFTYP; /*!< MDMA ch 05 Transfer Type Saving Register */ + __I uint32_t C05XFSAD; /*!< MDMA ch 05 Transfer Source Address Saving Register*/ + __I uint32_t C05XFDAD; /*!< MDMA ch 05 Transfer Destination Address Saving Register*/ + __I uint32_t C05XFSIZ; /*!< MDMA ch 05 Transfer Size Saving Register */ + __I uint32_t C05DSADS; /*!< MDMA ch 05 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C05DSNUM; /*!< MDMA ch 05 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED8[2]; + __I uint32_t C06XFTYP; /*!< MDMA ch 06 Transfer Type Saving Register */ + __I uint32_t C06XFSAD; /*!< MDMA ch 06 Transfer Source Address Saving Register*/ + __I uint32_t C06XFDAD; /*!< MDMA ch 06 Transfer Destination Address Saving Register*/ + __I uint32_t C06XFSIZ; /*!< MDMA ch 06 Transfer Size Saving Register */ + __I uint32_t C06DSADS; /*!< MDMA ch 06 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C06DSNUM; /*!< MDMA ch 06 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED9[2]; + __I uint32_t C07XFTYP; /*!< MDMA ch 07 Transfer Type Saving Register */ + __I uint32_t C07XFSAD; /*!< MDMA ch 07 Transfer Source Address Saving Register*/ + __I uint32_t C07XFDAD; /*!< MDMA ch 07 Transfer Destination Address Saving Register*/ + __I uint32_t C07XFSIZ; /*!< MDMA ch 07 Transfer Size Saving Register */ + __I uint32_t C07DSADS; /*!< MDMA ch 07 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C07DSNUM; /*!< MDMA ch 07 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED10[2]; + __I uint32_t C08XFTYP; /*!< MDMA ch 08 Transfer Type Saving Register */ + __I uint32_t C08XFSAD; /*!< MDMA ch 08 Transfer Source Address Saving Register*/ + __I uint32_t C08XFDAD; /*!< MDMA ch 08 Transfer Destination Address Saving Register*/ + __I uint32_t C08XFSIZ; /*!< MDMA ch 08 Transfer Size Saving Register */ + __I uint32_t C08DSADS; /*!< MDMA ch 08 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C08DSNUM; /*!< MDMA ch 08 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED11[2]; + __I uint32_t C09XFTYP; /*!< MDMA ch n Transfer Type Saving Register */ + __I uint32_t C09XFSAD; /*!< MDMA ch n Transfer Source Address Saving Register*/ + __I uint32_t C09XFDAD; /*!< MDMA ch n Transfer Destination Address Saving Register*/ + __I uint32_t C09XFSIZ; /*!< MDMA ch n Transfer Size Saving Register */ + __I uint32_t C09DSADS; /*!< MDMA ch n Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C09DSNUM; /*!< MDMA ch n Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED12[2]; + __I uint32_t C10XFTYP; /*!< MDMA ch 10 Transfer Type Saving Register */ + __I uint32_t C10XFSAD; /*!< MDMA ch 10 Transfer Source Address Saving Register*/ + __I uint32_t C10XFDAD; /*!< MDMA ch 10 Transfer Destination Address Saving Register*/ + __I uint32_t C10XFSIZ; /*!< MDMA ch 10 Transfer Size Saving Register */ + __I uint32_t C10DSADS; /*!< MDMA ch 10 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C10DSNUM; /*!< MDMA ch 10 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED13[2]; + __I uint32_t C11XFTYP; /*!< MDMA ch 11 Transfer Type Saving Register */ + __I uint32_t C11XFSAD; /*!< MDMA ch 11 Transfer Source Address Saving Register*/ + __I uint32_t C11XFDAD; /*!< MDMA ch 11 Transfer Destination Address Saving Register*/ + __I uint32_t C11XFSIZ; /*!< MDMA ch 11 Transfer Size Saving Register */ + __I uint32_t C11DSADS; /*!< MDMA ch 11 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C11DSNUM; /*!< MDMA ch 11 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED14[2]; + __I uint32_t C12XFTYP; /*!< MDMA ch 12 Transfer Type Saving Register */ + __I uint32_t C12XFSAD; /*!< MDMA ch 12 Transfer Source Address Saving Register*/ + __I uint32_t C12XFDAD; /*!< MDMA ch 12 Transfer Destination Address Saving Register*/ + __I uint32_t C12XFSIZ; /*!< MDMA ch 12 Transfer Size Saving Register */ + __I uint32_t C12DSADS; /*!< MDMA ch 12 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C12DSNUM; /*!< MDMA ch 12 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED15[2]; + __I uint32_t C13XFTYP; /*!< MDMA ch 13 Transfer Type Saving Register */ + __I uint32_t C13XFSAD; /*!< MDMA ch 13 Transfer Source Address Saving Register*/ + __I uint32_t C13XFDAD; /*!< MDMA ch 13 Transfer Destination Address Saving Register*/ + __I uint32_t C13XFSIZ; /*!< MDMA ch 13 Transfer Size Saving Register */ + __I uint32_t C13DSADS; /*!< MDMA ch 13 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C13DSNUM; /*!< MDMA ch 13 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED16[2]; + __I uint32_t C14XFTYP; /*!< MDMA ch 14 Transfer Type Saving Register */ + __I uint32_t C14XFSAD; /*!< MDMA ch 14 Transfer Source Address Saving Register*/ + __I uint32_t C14XFDAD; /*!< MDMA ch 14 Transfer Destination Address Saving Register*/ + __I uint32_t C14XFSIZ; /*!< MDMA ch 14 Transfer Size Saving Register */ + __I uint32_t C14DSADS; /*!< MDMA ch 14 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C14DSNUM; /*!< MDMA ch 14 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED17[2]; + __I uint32_t C15XFTYP; /*!< MDMA ch 15 Transfer Type Saving Register */ + __I uint32_t C15XFSAD; /*!< MDMA ch 15 Transfer Source Address Saving Register*/ + __I uint32_t C15XFDAD; /*!< MDMA ch 15 Transfer Destination Address Saving Register*/ + __I uint32_t C15XFSIZ; /*!< MDMA ch 15 Transfer Size Saving Register */ + __I uint32_t C15DSADS; /*!< MDMA ch 15 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C15DSNUM; /*!< MDMA ch 15 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED18[2]; + __I uint32_t C16XFTYP; /*!< MDMA ch 16 Transfer Type Saving Register */ + __I uint32_t C16XFSAD; /*!< MDMA ch 16 Transfer Source Address Saving Register*/ + __I uint32_t C16XFDAD; /*!< MDMA ch 16 Transfer Destination Address Saving Register*/ + __I uint32_t C16XFSIZ; /*!< MDMA ch 16 Transfer Size Saving Register */ + __I uint32_t C16DSADS; /*!< MDMA ch 16 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C16DSNUM; /*!< MDMA ch 16 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED19[2]; + __I uint32_t C17XFTYP; /*!< MDMA ch 17 Transfer Type Saving Register */ + __I uint32_t C17XFSAD; /*!< MDMA ch 17 Transfer Source Address Saving Register*/ + __I uint32_t C17XFDAD; /*!< MDMA ch 17 Transfer Destination Address Saving Register*/ + __I uint32_t C17XFSIZ; /*!< MDMA ch 17 Transfer Size Saving Register */ + __I uint32_t C17DSADS; /*!< MDMA ch 17 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C17DSNUM; /*!< MDMA ch 17 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED20[2]; + __I uint32_t C18XFTYP; /*!< MDMA ch 18 Transfer Type Saving Register */ + __I uint32_t C18XFSAD; /*!< MDMA ch 18 Transfer Source Address Saving Register*/ + __I uint32_t C18XFDAD; /*!< MDMA ch 18 Transfer Destination Address Saving Register*/ + __I uint32_t C18XFSIZ; /*!< MDMA ch 18 Transfer Size Saving Register */ + __I uint32_t C18DSADS; /*!< MDMA ch 18 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C18DSNUM; /*!< MDMA ch 18 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED21[2]; + __I uint32_t C19XFTYP; /*!< MDMA ch 19 Transfer Type Saving Register */ + __I uint32_t C19XFSAD; /*!< MDMA ch 19 Transfer Source Address Saving Register*/ + __I uint32_t C19XFDAD; /*!< MDMA ch 19 Transfer Destination Address Saving Register*/ + __I uint32_t C19XFSIZ; /*!< MDMA ch 19 Transfer Size Saving Register */ + __I uint32_t C19DSADS; /*!< MDMA ch 19 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C19DSNUM; /*!< MDMA ch 19 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED22[2]; + __I uint32_t C20XFTYP; /*!< MDMA ch 20 Transfer Type Saving Register */ + __I uint32_t C20XFSAD; /*!< MDMA ch 20 Transfer Source Address Saving Register*/ + __I uint32_t C20XFDAD; /*!< MDMA ch 20 Transfer Destination Address Saving Register*/ + __I uint32_t C20XFSIZ; /*!< MDMA ch 20 Transfer Size Saving Register */ + __I uint32_t C20DSADS; /*!< MDMA ch 20 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C20DSNUM; /*!< MDMA ch 20 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED23[2]; + __I uint32_t C21XFTYP; /*!< MDMA ch 21 Transfer Type Saving Register */ + __I uint32_t C21XFSAD; /*!< MDMA ch 21 Transfer Source Address Saving Register*/ + __I uint32_t C21XFDAD; /*!< MDMA ch 21 Transfer Destination Address Saving Register*/ + __I uint32_t C21XFSIZ; /*!< MDMA ch 21 Transfer Size Saving Register */ + __I uint32_t C21DSADS; /*!< MDMA ch 21 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C21DSNUM; /*!< MDMA ch 21 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED24[2]; + __I uint32_t C22XFTYP; /*!< MDMA ch 22 Transfer Type Saving Register */ + __I uint32_t C22XFSAD; /*!< MDMA ch 22 Transfer Source Address Saving Register*/ + __I uint32_t C22XFDAD; /*!< MDMA ch 22 Transfer Destination Address Saving Register*/ + __I uint32_t C22XFSIZ; /*!< MDMA ch 22 Transfer Size Saving Register */ + __I uint32_t C22DSADS; /*!< MDMA ch 22 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C22DSNUM; /*!< MDMA ch 22 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED25[2]; + __I uint32_t C23XFTYP; /*!< MDMA ch 23 Transfer Type Saving Register */ + __I uint32_t C23XFSAD; /*!< MDMA ch 23 Transfer Source Address Saving Register*/ + __I uint32_t C23XFDAD; /*!< MDMA ch 23 Transfer Destination Address Saving Register*/ + __I uint32_t C23XFSIZ; /*!< MDMA ch 23 Transfer Size Saving Register */ + __I uint32_t C23DSADS; /*!< MDMA ch 23 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C23DSNUM; /*!< MDMA ch 23 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED26[2]; + __I uint32_t C24XFTYP; /*!< MDMA ch 24 Transfer Type Saving Register */ + __I uint32_t C24XFSAD; /*!< MDMA ch 24 Transfer Source Address Saving Register*/ + __I uint32_t C24XFDAD; /*!< MDMA ch 24 Transfer Destination Address Saving Register*/ + __I uint32_t C24XFSIZ; /*!< MDMA ch 24 Transfer Size Saving Register */ + __I uint32_t C24DSADS; /*!< MDMA ch 24 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C24DSNUM; /*!< MDMA ch 24 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED27[2]; + __I uint32_t C25XFTYP; /*!< MDMA ch 25 Transfer Type Saving Register */ + __I uint32_t C25XFSAD; /*!< MDMA ch 25 Transfer Source Address Saving Register*/ + __I uint32_t C25XFDAD; /*!< MDMA ch 25 Transfer Destination Address Saving Register*/ + __I uint32_t C25XFSIZ; /*!< MDMA ch 25 Transfer Size Saving Register */ + __I uint32_t C25DSADS; /*!< MDMA ch 25 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C25DSNUM; /*!< MDMA ch 25 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED28[2]; + __I uint32_t C26XFTYP; /*!< MDMA ch 26 Transfer Type Saving Register */ + __I uint32_t C26XFSAD; /*!< MDMA ch 26 Transfer Source Address Saving Register*/ + __I uint32_t C26XFDAD; /*!< MDMA ch 26 Transfer Destination Address Saving Register*/ + __I uint32_t C26XFSIZ; /*!< MDMA ch 26 Transfer Size Saving Register */ + __I uint32_t C26DSADS; /*!< MDMA ch 26 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C26DSNUM; /*!< MDMA ch 26 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED29[2]; + __I uint32_t C27XFTYP; /*!< MDMA ch 27 Transfer Type Saving Register */ + __I uint32_t C27XFSAD; /*!< MDMA ch 27 Transfer Source Address Saving Register*/ + __I uint32_t C27XFDAD; /*!< MDMA ch 27 Transfer Destination Address Saving Register*/ + __I uint32_t C27XFSIZ; /*!< MDMA ch 27 Transfer Size Saving Register */ + __I uint32_t C27DSADS; /*!< MDMA ch 27 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C27DSNUM; /*!< MDMA ch 27 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED30[2]; + __I uint32_t C28XFTYP; /*!< MDMA ch 28 Transfer Type Saving Register */ + __I uint32_t C28XFSAD; /*!< MDMA ch 28 Transfer Source Address Saving Register*/ + __I uint32_t C28XFDAD; /*!< MDMA ch 28 Transfer Destination Address Saving Register*/ + __I uint32_t C28XFSIZ; /*!< MDMA ch 28 Transfer Size Saving Register */ + __I uint32_t C28DSADS; /*!< MDMA ch 28 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C28DSNUM; /*!< MDMA ch 28 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED31[2]; + __I uint32_t C29XFTYP; /*!< MDMA ch 29 Transfer Type Saving Register */ + __I uint32_t C29XFSAD; /*!< MDMA ch 29 Transfer Source Address Saving Register*/ + __I uint32_t C29XFDAD; /*!< MDMA ch 29 Transfer Destination Address Saving Register*/ + __I uint32_t C29XFSIZ; /*!< MDMA ch 29 Transfer Size Saving Register */ + __I uint32_t C29DSADS; /*!< MDMA ch 29 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C29DSNUM; /*!< MDMA ch 29 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED32[2]; + __I uint32_t C30XFTYP; /*!< MDMA ch 30 Transfer Type Saving Register */ + __I uint32_t C30XFSAD; /*!< MDMA ch 30 Transfer Source Address Saving Register*/ + __I uint32_t C30XFDAD; /*!< MDMA ch 30 Transfer Destination Address Saving Register*/ + __I uint32_t C30XFSIZ; /*!< MDMA ch 30 Transfer Size Saving Register */ + __I uint32_t C30DSADS; /*!< MDMA ch 30 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C30DSNUM; /*!< MDMA ch 30 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED33[2]; + __I uint32_t C31XFTYP; /*!< MDMA ch 31 Transfer Type Saving Register */ + __I uint32_t C31XFSAD; /*!< MDMA ch 31 Transfer Source Address Saving Register*/ + __I uint32_t C31XFDAD; /*!< MDMA ch 31 Transfer Destination Address Saving Register*/ + __I uint32_t C31XFSIZ; /*!< MDMA ch 31 Transfer Size Saving Register */ + __I uint32_t C31DSADS; /*!< MDMA ch 31 Transfer Descriptor Storage Address Saving Register*/ + __I uint32_t C31DSNUM; /*!< MDMA ch 31 Transfer Descriptor Count Saving Register*/ + uint32_t RESERVED34[238]; + __IO uint32_t MSK; /*!< MDMA Transfer Request Mask Register */ +} TSB_MDMA_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief ARM Prime Cell PL011 + */ +typedef struct { + __IO uint32_t DR; /*!< FUART Data Register */ + union { + __I uint32_t RSR; /*!< FUART Receive Status Register */ + __O uint32_t ECR; /*!< FUART Error Clear Register */ + }; + uint32_t RESERVED0[4]; + __I uint32_t FR; /*!< FUART Flag Register */ + uint32_t RESERVED1; + __IO uint32_t ILPR; /*!< FUART IrDA Low-power Counter register */ + __IO uint32_t BRD; /*!< FUART Integer Baud Rate Register */ + __IO uint32_t FBRD; /*!< FUART Fractional Baud Rate Register */ + __IO uint32_t LCR_H; /*!< FUART Line Control Register */ + __IO uint32_t CR; /*!< FUART Cntrol Register */ + __IO uint32_t IFLS; /*!< FUART Interrupt FIFO Level Select Register */ + __IO uint32_t IMSC; /*!< FUART Interrupt Mask Set/Clear Register */ + __I uint32_t RIS; /*!< FUART Raw Interrupt Status Register */ + __I uint32_t MIS; /*!< FUART Masked Interrupt Status Register */ + __O uint32_t ICR; /*!< FUART Interrupt Clear Register */ + __IO uint32_t DMACR; /*!< FUART DMA Control Register */ +} TSB_FURT_TypeDef; + +/** + * @brief ADC + */ +typedef struct { + __IO uint32_t CR0; /*!< AD Control Register 0 */ + __IO uint32_t CR1; /*!< AD Control Register 1 */ + __I uint32_t ST; /*!< AD Status Register */ + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Setting Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Setting Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Setting Register 2 */ + uint32_t RESERVED0; + __IO uint32_t CMPEN; /*!< Monitor function Enable Register */ + __IO uint32_t CMPCR0; /*!< AD Monitor function Setting Register 0 */ + __IO uint32_t CMPCR1; /*!< AD Monitor function Setting Register 1 */ + __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ + __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ + uint32_t RESERVED1[34]; + __IO uint32_t EXAZSEL; /*!< AD External AIN sampling period selection Register*/ + __IO uint32_t TSET0; /*!< AD Start-up Factor Program Register 0 */ + __IO uint32_t TSET1; /*!< AD Start-up Factor Program Register 1 */ + __IO uint32_t TSET2; /*!< AD Start-up Factor Program Register 2 */ + __IO uint32_t TSET3; /*!< AD Start-up Factor Program Register 3 */ + __IO uint32_t TSET4; /*!< AD Start-up Factor Program Register 4 */ + __IO uint32_t TSET5; /*!< AD Start-up Factor Program Register 5 */ + __IO uint32_t TSET6; /*!< AD Start-up Factor Program Register 6 */ + __IO uint32_t TSET7; /*!< AD Start-up Factor Program Register 7 */ + __IO uint32_t TSET8; /*!< AD Start-up Factor Program Register 8 */ + __IO uint32_t TSET9; /*!< AD Start-up Factor Program Register 9 */ + __IO uint32_t TSET10; /*!< AD Start-up Factor Program Register 10 */ + __IO uint32_t TSET11; /*!< AD Start-up Factor Program Register 11 */ + __IO uint32_t TSET12; /*!< AD Start-up Factor Program Register 12 */ + __IO uint32_t TSET13; /*!< AD Start-up Factor Program Register 13 */ + __IO uint32_t TSET14; /*!< AD Start-up Factor Program Register 14 */ + __IO uint32_t TSET15; /*!< AD Start-up Factor Program Register 15 */ + __IO uint32_t TSET16; /*!< AD Start-up Factor Program Register 16 */ + __IO uint32_t TSET17; /*!< AD Start-up Factor Program Register 17 */ + __IO uint32_t TSET18; /*!< AD Start-up Factor Program Register 18 */ + __IO uint32_t TSET19; /*!< AD Start-up Factor Program Register 19 */ + __IO uint32_t TSET20; /*!< AD Start-up Factor Program Register 20 */ + __IO uint32_t TSET21; /*!< AD Start-up Factor Program Register 21 */ + __IO uint32_t TSET22; /*!< AD Start-up Factor Program Register 22 */ + __IO uint32_t TSET23; /*!< AD Start-up Factor Program Register 23 */ + uint32_t RESERVED2[8]; + __I uint32_t REG0; /*!< AD Conversion Result Storage Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Storage Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Storage Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Storage Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Storage Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Storage Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Storage Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Storage Register 7 */ + __I uint32_t REG8; /*!< AD Conversion Result Storage Register 8 */ + __I uint32_t REG9; /*!< AD Conversion Result Storage Register 9 */ + __I uint32_t REG10; /*!< AD Conversion Result Storage Register 10 */ + __I uint32_t REG11; /*!< AD Conversion Result Storage Register 11 */ + __I uint32_t REG12; /*!< AD Conversion Result Storage Register 12 */ + __I uint32_t REG13; /*!< AD Conversion Result Storage Register 13 */ + __I uint32_t REG14; /*!< AD Conversion Result Storage Register 14 */ + __I uint32_t REG15; /*!< AD Conversion Result Storage Register 15 */ + __I uint32_t REG16; /*!< AD Conversion Result Storage Register 16 */ + __I uint32_t REG17; /*!< AD Conversion Result Storage Register 17 */ + __I uint32_t REG18; /*!< AD Conversion Result Storage Register 18 */ + __I uint32_t REG19; /*!< AD Conversion Result Storage Register 19 */ + __I uint32_t REG20; /*!< AD Conversion Result Storage Register 20 */ + __I uint32_t REG21; /*!< AD Conversion Result Storage Register 21 */ + __I uint32_t REG22; /*!< AD Conversion Result Storage Register 22 */ + __I uint32_t REG23; /*!< AD Conversion Result Storage Register 23 */ +} TSB_AD_TypeDef; + +/** + * @brief Digital analog converter (DAC) + */ +typedef struct { + __IO uint32_t CR; /*!< DAC Control Register */ + __IO uint32_t REG; /*!< DAC Converted Value Setting Register */ +} TSB_DA_TypeDef; + +/** + * @brief 16-bit Timer/Event Counter (TB) + */ +typedef struct { + __IO uint32_t MOD; /*!< T32A Mode Register */ + uint32_t RESERVED0[15]; + __IO uint32_t RUNA; /*!< T32A Run Register A */ + __IO uint32_t CRA; /*!< T32A Counter Control Register A */ + __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */ + __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */ + __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */ + __IO uint32_t STA; /*!< T32A Status Register A */ + __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */ + __I uint32_t TMRA; /*!< T32A Counter Capture Register A */ + __IO uint32_t RELDA; /*!< T32A Counter Reload Register A */ + __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ + __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ + __I uint32_t CAPA0; /*!< T32A Timer Capture A0 Register */ + __I uint32_t CAPA1; /*!< T32A Timer Cupture A1 Register */ + __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */ + uint32_t RESERVED1[2]; + __IO uint32_t RUNB; /*!< T32A Run Register B */ + __IO uint32_t CRB; /*!< T32A Counter Control Register B */ + __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */ + __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */ + __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */ + __IO uint32_t STB; /*!< T32A Status Register B */ + __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */ + __I uint32_t TMRB; /*!< T32A Counter Capture Register B */ + __IO uint32_t RELDB; /*!< T32A Counter Reload Register B */ + __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ + __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ + __I uint32_t CAPB0; /*!< T32A Timer Capture B0 Register */ + __I uint32_t CAPB1; /*!< T32A Timer Capture B1 Register */ + __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ + uint32_t RESERVED2[2]; + __IO uint32_t RUNC; /*!< T32A Run Register C */ + __IO uint32_t CRC; /*!< T32A Counter Control Register C */ + __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */ + __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */ + __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */ + __IO uint32_t STC; /*!< T32A Status Register C */ + __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */ + __I uint32_t TMRC; /*!< T32A Counter Capture Register C */ + __IO uint32_t RELDC; /*!< T32A Counter Reload Register C */ + __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ + __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ + __I uint32_t CAPC0; /*!< T32A Timer Capture C0 Register */ + __I uint32_t CAPC1; /*!< T32A Capture Register C1 */ + __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */ + __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */ +} TSB_T32A_TypeDef; + +/** + * @brief TSSI + */ +typedef struct { + __IO uint32_t CR0; /*!< TSSI Control Register 0 */ + __IO uint32_t CR1; /*!< TSSI Control Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t CPR; /*!< TSSI Clock Divider Register */ + uint32_t RESERVED1[11]; + __IO uint32_t RCMR; /*!< TSSI Receive Clock / Mode Control Register */ + __IO uint32_t RFMR; /*!< TSSI Receive Data Frame Control Register */ + __IO uint32_t RCR; /*!< TSSI Receive Data Comparison Register */ + __IO uint32_t RDMACR; /*!< TSSI Receive DMA Control Register */ + uint32_t RESERVED2[4]; + __IO uint32_t RSR; /*!< TSSI Reception Status Register */ + __IO uint32_t RIER; /*!< TSSI Receive Interrupt Enable Register */ + uint32_t RESERVED3[2]; + __IO uint32_t RFTLR; /*!< TSSI Receive FIFO Threshold Register */ + __I uint32_t RFLR; /*!< TSSI Receive FIFO Entry Register */ + uint32_t RESERVED4[2]; + __I uint32_t RDR0; /*!< TSSI Receive Data Register 0 */ + __I uint32_t RDR1; /*!< TSSI Receive Data Register 1 */ + __I uint32_t RDR2; /*!< TSSI Receive Data Register 2 */ + __I uint32_t RDR3; /*!< TSSI Receive Data Register 3 */ + uint32_t RESERVED5[4]; + __IO uint32_t TCMR; /*!< TSSI Transmit Clock / Mode Control Register */ + __IO uint32_t TFMR; /*!< TSSI Transmit Data Frame Control Register */ + uint32_t RESERVED6; + __IO uint32_t TDMACR; /*!< TSSI Transmit DMA Control Register */ + uint32_t RESERVED7[4]; + __IO uint32_t TSR; /*!< TSSI Transmission Status Register */ + __IO uint32_t TIER; /*!< TSSI Transmission Interrupt Enable Register */ + uint32_t RESERVED8[2]; + __IO uint32_t TFTLR; /*!< TSSI Transmit FIFO Threshold Register */ + __I uint32_t TFLR; /*!< TSSI Transmit FIFO Entry Register */ + uint32_t RESERVED9[2]; + __O uint32_t TDR0; /*!< TSSI Transmission Data Register 0 */ + __O uint32_t TDR1; /*!< TSSI Transmission Data Register 1 */ + __O uint32_t TDR2; /*!< TSSI Transmission Data Register 2 */ + __O uint32_t TDR3; /*!< TSSI Transmission Data Register 3 */ +} TSB_TSSI_TypeDef; + +/** + * @brief UART + */ +typedef struct { + __IO uint32_t SWRST; /*!< UART Software Reset Register */ + __IO uint32_t CR0; /*!< UART Control Register 0 */ + __IO uint32_t CR1; /*!< UART Control Register 1 */ + __IO uint32_t CLK; /*!< UART Clock Control Register */ + __IO uint32_t BRD; /*!< UART Baud Rate Register */ + __IO uint32_t TRANS; /*!< UART Transfer Enable Register */ + __IO uint32_t DR; /*!< UART Data Register */ + __IO uint32_t SR; /*!< UART Status Register */ + __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */ + __IO uint32_t ERR; /*!< UART Error Register */ +} TSB_UART_TypeDef; + +/** + * @brief I2S interface + */ +typedef struct { + uint32_t RESERVED0; + __IO uint32_t CSTART; /*!< I2S Clock LRCK Generation Start Register */ + __I uint32_t CBUSY; /*!< I2S Clock LRCK Generation Status Register */ + __IO uint32_t CSTOP; /*!< I2S Clock LRCK Generation Stop Register */ + __IO uint32_t CAUDIOSET; /*!< I2S Clock AUDIOSET Register */ + uint32_t RESERVED1[11]; + __I uint32_t CREGBUSY; /*!< I2S Clock REGBUSY Register */ + uint32_t RESERVED2[45]; + __IO uint32_t CMODESET; /*!< I2S Clock Audio Data Format Setting Register */ + uint32_t RESERVED3[65]; + __IO uint32_t CMS_SEL; /*!< I2S Clock Master/Slave Select Register */ + __IO uint32_t CMCLK_IO_SEL; /*!< I2S Clock MCLK pin input/output Selection Register*/ + uint32_t RESERVED4[3]; + __IO uint32_t CPHT_DIV; /*!< I2S Clock Phi T0 Frequency Division Setting Register*/ + __IO uint32_t CPHT_DIVOUT_EN; /*!< I2S Clock Phi T0 Divided Clock Output Enable Register*/ + uint32_t RESERVED5; + __IO uint32_t CBCK_SRC_SEL; /*!< I2S Clock BCK Source Clock Select Register */ + __IO uint32_t CBCK_DIV; /*!< I2S Clock BCK Frequency Division Setting Register*/ + __IO uint32_t CBCK_DIVOUT_EN; /*!< I2S Clock BCK Output Enable Register */ + uint32_t RESERVED6[118]; + __IO uint32_t ISTART; /*!< I2S Receive Control Start Register */ + __I uint32_t IBUSY; /*!< I2S Receive Operation Status Register */ + __IO uint32_t ISTOP; /*!< I2S Data Receive Stop Register */ + __IO uint32_t IAUDIOSET; /*!< I2S Receive AUDIOSET Register */ + __I uint32_t IINTSTAT; /*!< I2S Receive Control Interrupt Status Register*/ + __IO uint32_t IINTMASK; /*!< I2S Receive Control Interrupt Mask Register */ + __IO uint32_t IINTCLR; /*!< I2S Receive Control Interrupt Clear Register */ + uint32_t RESERVED7; + __IO uint32_t IMUTE; /*!< I2S Receive Mute Setting Register */ + __I uint32_t IEPTR; /*!< I2S Receive Control Error Occurrence Address Storage Register*/ + uint32_t RESERVED8[5]; + __I uint32_t IREGBUSY; /*!< I2S Receive REGBUSY register */ + uint32_t RESERVED9[3]; + __IO uint32_t ITHRESHOLD; /*!< I2S Receive Threshold Setting Register */ + __I uint32_t IFIFO_STS; /*!< I2S Receive FIFO Status Register */ + uint32_t RESERVED10[40]; + __IO uint32_t IMODESET; /*!< I2S Receive Audio Data Format Setting Register*/ + uint32_t RESERVED11; + __I uint32_t ILMEM00; /*!< I2S Receive Data Storage Register 00 */ + __I uint32_t ILMEM01; /*!< I2S Receive Data Storage Register 01 */ + __I uint32_t ILMEM02; /*!< I2S Receive Data Storage Register 02 */ + __I uint32_t ILMEM03; /*!< I2S Receive Data Storage Register 03 */ + __I uint32_t ILMEM04; /*!< I2S Receive Data Storage Register 04 */ + __I uint32_t ILMEM05; /*!< I2S Receive Data Storage Register 05 */ + __I uint32_t ILMEM06; /*!< I2S Receive Data Storage Register 06 */ + __I uint32_t ILMEM07; /*!< I2S Receive Data Storage Register 07 */ + __I uint32_t ILMEM08; /*!< I2S Receive Data Storage Register 08 */ + __I uint32_t ILMEM09; /*!< I2S Receive Data Storage Register 09 */ + __I uint32_t ILMEM10; /*!< I2S Receive Data Storage Register 10 */ + __I uint32_t ILMEM11; /*!< I2S Receive Data Storage Register 11 */ + __I uint32_t ILMEM12; /*!< I2S Receive Data Storage Register 12 */ + __I uint32_t ILMEM13; /*!< I2S Receive Data Storage Register 13 */ + __I uint32_t ILMEM14; /*!< I2S Receive Data Storage Register 14 */ + __I uint32_t ILMEM15; /*!< I2S Receive Data Storage Register 15 */ + __I uint32_t ILMEM16; /*!< I2S Receive Data Storage Register 16 */ + __I uint32_t ILMEM17; /*!< I2S Receive Data Storage Register 17 */ + __I uint32_t ILMEM18; /*!< I2S Receive Data Storage Register 18 */ + __I uint32_t ILMEM19; /*!< I2S Receive Data Storage Register 19 */ + __I uint32_t ILMEM20; /*!< I2S Receive Data Storage Register 20 */ + __I uint32_t ILMEM21; /*!< I2S Receive Data Storage Register 21 */ + __I uint32_t ILMEM22; /*!< I2S Receive Data Storage Register 22 */ + __I uint32_t ILMEM23; /*!< I2S Receive Data Storage Register 23 */ + __I uint32_t ILMEM24; /*!< I2S Receive Data Storage Register 24 */ + __I uint32_t ILMEM25; /*!< I2S Receive Data Storage Register 25 */ + __I uint32_t ILMEM26; /*!< I2S Receive Data Storage Register 26 */ + __I uint32_t ILMEM27; /*!< I2S Receive Data Storage Register 27 */ + __I uint32_t ILMEM28; /*!< I2S Receive Data Storage Register 28 */ + __I uint32_t ILMEM29; /*!< I2S Receive Data Storage Register 29 */ + __I uint32_t ILMEM30; /*!< I2S Receive Data Storage Register 30 */ + __I uint32_t ILMEM31; /*!< I2S Receive Data Storage Register 31 */ + __I uint32_t ILMEM32; /*!< I2S Receive Data Storage Register 32 */ + __I uint32_t ILMEM33; /*!< I2S Receive Data Storage Register 33 */ + __I uint32_t ILMEM34; /*!< I2S Receive Data Storage Register 34 */ + __I uint32_t ILMEM35; /*!< I2S Receive Data Storage Register 35 */ + __I uint32_t ILMEM36; /*!< I2S Receive Data Storage Register 36 */ + __I uint32_t ILMEM37; /*!< I2S Receive Data Storage Register 37 */ + __I uint32_t ILMEM38; /*!< I2S Receive Data Storage Register 38 */ + __I uint32_t ILMEM39; /*!< I2S Receive Data Storage Register 39 */ + __I uint32_t ILMEM40; /*!< I2S Receive Data Storage Register 40 */ + __I uint32_t ILMEM41; /*!< I2S Receive Data Storage Register 41 */ + __I uint32_t ILMEM42; /*!< I2S Receive Data Storage Register 42 */ + __I uint32_t ILMEM43; /*!< I2S Receive Data Storage Register 43 */ + __I uint32_t ILMEM44; /*!< I2S Receive Data Storage Register 44 */ + __I uint32_t ILMEM45; /*!< I2S Receive Data Storage Register 45 */ + __I uint32_t ILMEM46; /*!< I2S Receive Data Storage Register 46 */ + __I uint32_t ILMEM47; /*!< I2S Receive Data Storage Register 47 */ + __I uint32_t ILMEM48; /*!< I2S Receive Data Storage Register 48 */ + __I uint32_t ILMEM49; /*!< I2S Receive Data Storage Register 49 */ + __I uint32_t ILMEM50; /*!< I2S Receive Data Storage Register 50 */ + __I uint32_t ILMEM51; /*!< I2S Receive Data Storage Register 51 */ + __I uint32_t ILMEM52; /*!< I2S Receive Data Storage Register 52 */ + __I uint32_t ILMEM53; /*!< I2S Receive Data Storage Register 53 */ + __I uint32_t ILMEM54; /*!< I2S Receive Data Storage Register 54 */ + __I uint32_t ILMEM55; /*!< I2S Receive Data Storage Register 55 */ + __I uint32_t ILMEM56; /*!< I2S Receive Data Storage Register 56 */ + __I uint32_t ILMEM57; /*!< I2S Receive Data Storage Register 57 */ + __I uint32_t ILMEM58; /*!< I2S Receive Data Storage Register 58 */ + __I uint32_t ILMEM59; /*!< I2S Receive Data Storage Register 59 */ + __I uint32_t ILMEM60; /*!< I2S Receive Data Storage Register 60 */ + __I uint32_t ILMEM61; /*!< I2S Receive Data Storage Register 61 */ + __I uint32_t ILMEM62; /*!< I2S Receive Data Storage Register 62 */ + __I uint32_t ILMEM63; /*!< I2S Receive Data Storage Register 63 */ + uint32_t RESERVED12; + __IO uint32_t OSTART; /*!< I2S Transmit Control Start Register */ + __I uint32_t OBUSY; /*!< I2S Transmit Operation Status Register */ + __IO uint32_t OSTOP; /*!< I2S Data Transmit Stop Register */ + __IO uint32_t OAUDIOSET; /*!< I2S Transmit AUDIOSET Register */ + __I uint32_t OINTSTAT; /*!< I2S Transmit Control Interrupt Status Register*/ + __IO uint32_t OINTMASK; /*!< I2S Transmit Control Interrupt Mask Register */ + __IO uint32_t OINTCLR; /*!< I2S Transmit Control Interrupt Clear Register*/ + uint32_t RESERVED13; + __IO uint32_t OMUTE; /*!< I2S Transmit Mute Setting Register */ + __I uint32_t OEPTR; /*!< I2S Transmit Control Error Occurrence Address Storage Register*/ + uint32_t RESERVED14; + __IO uint32_t OTX_SSIZE; /*!< I2S TX_SSIZE Register */ + uint32_t RESERVED15[3]; + __I uint32_t OREGBUSY; /*!< I2S Transmit REGBUSY Register */ + uint32_t RESERVED16[3]; + __IO uint32_t OTHRESHOLD; /*!< I2S Transmit Threshold Setting Register */ + __I uint32_t OFIFO_STS; /*!< I2S Transmit FIFO Status Register */ + uint32_t RESERVED17[40]; + __IO uint32_t OMODESET; /*!< I2S Transmit Audio Data Format Setting Register*/ + uint32_t RESERVED18; + __O uint32_t OLMEM00; /*!< I2S Transmit Data Storage Register 00 */ + __O uint32_t OLMEM01; /*!< I2S Transmit Data Storage Register 01 */ + __O uint32_t OLMEM02; /*!< I2S Transmit Data Storage Register 02 */ + __O uint32_t OLMEM03; /*!< I2S Transmit Data Storage Register 03 */ + __O uint32_t OLMEM04; /*!< I2S Transmit Data Storage Register 04 */ + __O uint32_t OLMEM05; /*!< I2S Transmit Data Storage Register 05 */ + __O uint32_t OLMEM06; /*!< I2S Transmit Data Storage Register 06 */ + __O uint32_t OLMEM07; /*!< I2S Transmit Data Storage Register 07 */ + __O uint32_t OLMEM08; /*!< I2S Transmit Data Storage Register 08 */ + __O uint32_t OLMEM09; /*!< I2S Transmit Data Storage Register 09 */ + __O uint32_t OLMEM10; /*!< I2S Transmit Data Storage Register 10 */ + __O uint32_t OLMEM11; /*!< I2S Transmit Data Storage Register 11 */ + __O uint32_t OLMEM12; /*!< I2S Transmit Data Storage Register 12 */ + __O uint32_t OLMEM13; /*!< I2S Transmit Data Storage Register 13 */ + __O uint32_t OLMEM14; /*!< I2S Transmit Data Storage Register 14 */ + __O uint32_t OLMEM15; /*!< I2S Transmit Data Storage Register 15 */ + __O uint32_t OLMEM16; /*!< I2S Transmit Data Storage Register 16 */ + __O uint32_t OLMEM17; /*!< I2S Transmit Data Storage Register 17 */ + __O uint32_t OLMEM18; /*!< I2S Transmit Data Storage Register 18 */ + __O uint32_t OLMEM19; /*!< I2S Transmit Data Storage Register 19 */ + __O uint32_t OLMEM20; /*!< I2S Transmit Data Storage Register 20 */ + __O uint32_t OLMEM21; /*!< I2S Transmit Data Storage Register 21 */ + __O uint32_t OLMEM22; /*!< I2S Transmit Data Storage Register 22 */ + __O uint32_t OLMEM23; /*!< I2S Transmit Data Storage Register 23 */ + __O uint32_t OLMEM24; /*!< I2S Transmit Data Storage Register 24 */ + __O uint32_t OLMEM25; /*!< I2S Transmit Data Storage Register 25 */ + __O uint32_t OLMEM26; /*!< I2S Transmit Data Storage Register 26 */ + __O uint32_t OLMEM27; /*!< I2S Transmit Data Storage Register 27 */ + __O uint32_t OLMEM28; /*!< I2S Transmit Data Storage Register 28 */ + __O uint32_t OLMEM29; /*!< I2S Transmit Data Storage Register 29 */ + __O uint32_t OLMEM30; /*!< I2S Transmit Data Storage Register 30 */ + __O uint32_t OLMEM31; /*!< I2S Transmit Data Storage Register 31 */ + __O uint32_t OLMEM32; /*!< I2S Transmit Data Storage Register 32 */ + __O uint32_t OLMEM33; /*!< I2S Transmit Data Storage Register 33 */ + __O uint32_t OLMEM34; /*!< I2S Transmit Data Storage Register 34 */ + __O uint32_t OLMEM35; /*!< I2S Transmit Data Storage Register 35 */ + __O uint32_t OLMEM36; /*!< I2S Transmit Data Storage Register 36 */ + __O uint32_t OLMEM37; /*!< I2S Transmit Data Storage Register 37 */ + __O uint32_t OLMEM38; /*!< I2S Transmit Data Storage Register 38 */ + __O uint32_t OLMEM39; /*!< I2S Transmit Data Storage Register 39 */ + __O uint32_t OLMEM40; /*!< I2S Transmit Data Storage Register 40 */ + __O uint32_t OLMEM41; /*!< I2S Transmit Data Storage Register 41 */ + __O uint32_t OLMEM42; /*!< I2S Transmit Data Storage Register 42 */ + __O uint32_t OLMEM43; /*!< I2S Transmit Data Storage Register 43 */ + __O uint32_t OLMEM44; /*!< I2S Transmit Data Storage Register 44 */ + __O uint32_t OLMEM45; /*!< I2S Transmit Data Storage Register 45 */ + __O uint32_t OLMEM46; /*!< I2S Transmit Data Storage Register 46 */ + __O uint32_t OLMEM47; /*!< I2S Transmit Data Storage Register 47 */ + __O uint32_t OLMEM48; /*!< I2S Transmit Data Storage Register 48 */ + __O uint32_t OLMEM49; /*!< I2S Transmit Data Storage Register 49 */ + __O uint32_t OLMEM50; /*!< I2S Transmit Data Storage Register 50 */ + __O uint32_t OLMEM51; /*!< I2S Transmit Data Storage Register 51 */ + __O uint32_t OLMEM52; /*!< I2S Transmit Data Storage Register 52 */ + __O uint32_t OLMEM53; /*!< I2S Transmit Data Storage Register 53 */ + __O uint32_t OLMEM54; /*!< I2S Transmit Data Storage Register 54 */ + __O uint32_t OLMEM55; /*!< I2S Transmit Data Storage Register 55 */ + __O uint32_t OLMEM56; /*!< I2S Transmit Data Storage Register 56 */ + __O uint32_t OLMEM57; /*!< I2S Transmit Data Storage Register 57 */ + __O uint32_t OLMEM58; /*!< I2S Transmit Data Storage Register 58 */ + __O uint32_t OLMEM59; /*!< I2S Transmit Data Storage Register 59 */ + __O uint32_t OLMEM60; /*!< I2S Transmit Data Storage Register 60 */ + __O uint32_t OLMEM61; /*!< I2S Transmit Data Storage Register 61 */ + __O uint32_t OLMEM62; /*!< I2S Transmit Data Storage Register 62 */ + __O uint32_t OLMEM63; /*!< I2S Transmit Data Storage Register 63 */ +} TSB_I2S_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< I2C Data Buffer Register */ + __IO uint32_t AR; /*!< I2C Bus address Register */ + union { + __O uint32_t CR2; /*!< I2C Control Register 2 */ + __I uint32_t SR; /*!< I2C Status Register */ + }; + __IO uint32_t PRS; /*!< I2C Prescaler clcok setting Register */ + __IO uint32_t IE; /*!< I2C Interrupt Enable Register */ + __IO uint32_t ST; /*!< I2C Interruption Status Register */ + __IO uint32_t OP; /*!< I2C Expanded function setting Register */ + __I uint32_t PM; /*!< I2C Bus pin Monitor Register */ + __IO uint32_t AR2; /*!< I2C 2nd address Register */ +} TSB_I2C_TypeDef; + +/** + * @brief EI2C + */ +typedef struct { + __IO uint32_t ARST; /*!< I2C Reset Register */ + __IO uint32_t AEN; /*!< I2C Bus Enable Register */ + __IO uint32_t ACR0; /*!< I2C Control Register 0 */ + __IO uint32_t ACR1; /*!< I2C Control Register 1 */ + __IO uint32_t ADBRT; /*!< I2C Transmit Data Buffer Register */ + __I uint32_t ADBRR; /*!< I2C Receive Data Buffer Register */ + __I uint32_t ASR0; /*!< I2C Status Register 0 */ + __IO uint32_t ASR1; /*!< I2C Status Register 1 */ + __IO uint32_t APRS; /*!< I2C Prescaler Clock Setting Register */ + __IO uint32_t ASCL; /*!< I2C SCL Wdth Setting Register */ + __IO uint32_t AAR1; /*!< I2C 1st Slave Address Register */ + __IO uint32_t AAR2; /*!< I2C 2nd Slave Address Register */ + __IO uint32_t AIE; /*!< I2C Interrupt DMA Setting Register */ + __I uint32_t APM; /*!< I2C Bus Terminal Monitor Setting Register */ +} TSB_EI2C_TypeDef; + +/** + * @brief Finite Impulse Response + */ +typedef struct { + __IO uint32_t START; /*!< FIR Start Register */ + __IO uint32_t CTRL; /*!< FIR Control Register */ + __IO uint32_t INITIALIZE; /*!< FIR Initialize Register */ + __IO uint32_t INITDATA; /*!< FIR Init data Register */ + __IO uint32_t INTEN; /*!< FIR Interrupt Enable Register */ + __IO uint32_t DMAEN; /*!< FIR DMA Enable Register */ + __IO uint32_t RAWINTSTAT; /*!< FIR Raw Interrupt Status Register */ + __I uint32_t SEQSTAT; /*!< FIR Sequencer Status Register */ + __IO uint32_t DBUFWPTR; /*!< FIR Data Buffer Write Pointer Register */ + __IO uint32_t DBUFRPTR; /*!< FIR Data Buffer Read Pointer Register */ + uint32_t RESERVED0[2]; + __IO uint32_t IDATA; /*!< FIR Input Data Register */ + __I uint32_t ODATA; /*!< FIR Output Data Register */ + uint32_t RESERVED1[2]; + __IO uint32_t COEF0; /*!< FIR Coefficient Register0 */ + __IO uint32_t COEF1; /*!< FIR Coefficient Register1 */ + __IO uint32_t COEF2; /*!< FIR Coefficient Register2 */ + __IO uint32_t COEF3; /*!< FIR Coefficient Register3 */ + __IO uint32_t COEF4; /*!< FIR Coefficient Register4 */ + __IO uint32_t COEF5; /*!< FIR Coefficient Register5 */ + __IO uint32_t COEF6; /*!< FIR Coefficient Register6 */ + __IO uint32_t COEF7; /*!< FIR Coefficient Register7 */ + __IO uint32_t COEF8; /*!< FIR Coefficient Register8 */ + __IO uint32_t COEF9; /*!< FIR Coefficient Register9 */ + __IO uint32_t COEF10; /*!< FIR Coefficient Register10 */ + __IO uint32_t COEF11; /*!< FIR Coefficient Register11 */ + __IO uint32_t COEF12; /*!< FIR Coefficient Register12 */ + __IO uint32_t COEF13; /*!< FIR Coefficient Register13 */ + __IO uint32_t COEF14; /*!< FIR Coefficient Register14 */ + __IO uint32_t COEF15; /*!< FIR Coefficient Register15 */ + __IO uint32_t COEF16; /*!< FIR Coefficient Register16 */ + __IO uint32_t COEF17; /*!< FIR Coefficient Register17 */ + __IO uint32_t COEF18; /*!< FIR Coefficient Register18 */ + __IO uint32_t COEF19; /*!< FIR Coefficient Register19 */ + __IO uint32_t COEF20; /*!< FIR Coefficient Register20 */ + __IO uint32_t COEF21; /*!< FIR Coefficient Register21 */ + __IO uint32_t COEF22; /*!< FIR Coefficient Register22 */ + __IO uint32_t COEF23; /*!< FIR Coefficient Register23 */ + __IO uint32_t COEF24; /*!< FIR Coefficient Register24 */ + __IO uint32_t COEF25; /*!< FIR Coefficient Register25 */ + __IO uint32_t COEF26; /*!< FIR Coefficient Register26 */ + __IO uint32_t COEF27; /*!< FIR Coefficient Register27 */ + __IO uint32_t COEF28; /*!< FIR Coefficient Register28 */ + __IO uint32_t COEF29; /*!< FIR Coefficient Register29 */ + __IO uint32_t COEF30; /*!< FIR Coefficient Register30 */ + __IO uint32_t COEF31; /*!< FIR Coefficient Register31 */ + __IO uint32_t COEF32; /*!< FIR Coefficient Register32 */ + __IO uint32_t COEF33; /*!< FIR Coefficient Register33 */ + __IO uint32_t COEF34; /*!< FIR Coefficient Register34 */ + __IO uint32_t COEF35; /*!< FIR Coefficient Register35 */ + __IO uint32_t COEF36; /*!< FIR Coefficient Register36 */ + __IO uint32_t COEF37; /*!< FIR Coefficient Register37 */ + __IO uint32_t COEF38; /*!< FIR Coefficient Register38 */ + __IO uint32_t COEF39; /*!< FIR Coefficient Register39 */ + __IO uint32_t COEF40; /*!< FIR Coefficient Register40 */ + __IO uint32_t COEF41; /*!< FIR Coefficient Register41 */ + __IO uint32_t COEF42; /*!< FIR Coefficient Register42 */ + __IO uint32_t COEF43; /*!< FIR Coefficient Register43 */ + __IO uint32_t COEF44; /*!< FIR Coefficient Register44 */ + __IO uint32_t COEF45; /*!< FIR Coefficient Register45 */ + __IO uint32_t COEF46; /*!< FIR Coefficient Register46 */ + __IO uint32_t COEF47; /*!< FIR Coefficient Register47 */ + __IO uint32_t COEF48; /*!< FIR Coefficient Register48 */ + __IO uint32_t COEF49; /*!< FIR Coefficient Register49 */ + __IO uint32_t COEF50; /*!< FIR Coefficient Register50 */ + __IO uint32_t COEF51; /*!< FIR Coefficient Register51 */ + __IO uint32_t COEF52; /*!< FIR Coefficient Register52 */ + __IO uint32_t COEF53; /*!< FIR Coefficient Register53 */ + __IO uint32_t COEF54; /*!< FIR Coefficient Register54 */ + __IO uint32_t COEF55; /*!< FIR Coefficient Register55 */ + __IO uint32_t COEF56; /*!< FIR Coefficient Register56 */ + __IO uint32_t COEF57; /*!< FIR Coefficient Register57 */ + __IO uint32_t COEF58; /*!< FIR Coefficient Register58 */ + __IO uint32_t COEF59; /*!< FIR Coefficient Register59 */ + __IO uint32_t COEF60; /*!< FIR Coefficient Register60 */ + __IO uint32_t COEF61; /*!< FIR Coefficient Register61 */ + __IO uint32_t COEF62; /*!< FIR Coefficient Register62 */ + __IO uint32_t COEF63; /*!< FIR Coefficient Register63 */ + __IO uint32_t COEF64; /*!< FIR Coefficient Register64 */ + __IO uint32_t COEF65; /*!< FIR Coefficient Register65 */ + __IO uint32_t COEF66; /*!< FIR Coefficient Register66 */ + __IO uint32_t COEF67; /*!< FIR Coefficient Register67 */ + __IO uint32_t COEF68; /*!< FIR Coefficient Register68 */ + __IO uint32_t COEF69; /*!< FIR Coefficient Register69 */ + __IO uint32_t COEF70; /*!< FIR Coefficient Register70 */ + __IO uint32_t COEF71; /*!< FIR Coefficient Register71 */ + __IO uint32_t COEF72; /*!< FIR Coefficient Register72 */ + __IO uint32_t COEF73; /*!< FIR Coefficient Register73 */ + __IO uint32_t COEF74; /*!< FIR Coefficient Register74 */ + __IO uint32_t COEF75; /*!< FIR Coefficient Register75 */ + __IO uint32_t COEF76; /*!< FIR Coefficient Register76 */ + __IO uint32_t COEF77; /*!< FIR Coefficient Register77 */ + __IO uint32_t COEF78; /*!< FIR Coefficient Register78 */ + __IO uint32_t COEF79; /*!< FIR Coefficient Register79 */ + __IO uint32_t COEF80; /*!< FIR Coefficient Register80 */ + __IO uint32_t COEF81; /*!< FIR Coefficient Register81 */ + __IO uint32_t COEF82; /*!< FIR Coefficient Register82 */ + __IO uint32_t COEF83; /*!< FIR Coefficient Register83 */ + __IO uint32_t COEF84; /*!< FIR Coefficient Register84 */ + __IO uint32_t COEF85; /*!< FIR Coefficient Register85 */ + __IO uint32_t COEF86; /*!< FIR Coefficient Register86 */ + __IO uint32_t COEF87; /*!< FIR Coefficient Register87 */ + __IO uint32_t COEF88; /*!< FIR Coefficient Register88 */ + __IO uint32_t COEF89; /*!< FIR Coefficient Register89 */ + __IO uint32_t COEF90; /*!< FIR Coefficient Register90 */ + __IO uint32_t COEF91; /*!< FIR Coefficient Register91 */ + __IO uint32_t COEF92; /*!< FIR Coefficient Register92 */ + __IO uint32_t COEF93; /*!< FIR Coefficient Register93 */ + __IO uint32_t COEF94; /*!< FIR Coefficient Register94 */ + __IO uint32_t COEF95; /*!< FIR Coefficient Register95 */ + __IO uint32_t COEF96; /*!< FIR Coefficient Register96 */ + __IO uint32_t COEF97; /*!< FIR Coefficient Register97 */ + __IO uint32_t COEF98; /*!< FIR Coefficient Register98 */ + __IO uint32_t COEF99; /*!< FIR Coefficient Register99 */ + __IO uint32_t COEF100; /*!< FIR Coefficient Register100 */ + __IO uint32_t COEF101; /*!< FIR Coefficient Register101 */ + __IO uint32_t COEF102; /*!< FIR Coefficient Register102 */ + __IO uint32_t COEF103; /*!< FIR Coefficient Register103 */ + __IO uint32_t COEF104; /*!< FIR Coefficient Register104 */ + __IO uint32_t COEF105; /*!< FIR Coefficient Register105 */ + __IO uint32_t COEF106; /*!< FIR Coefficient Register106 */ + __IO uint32_t COEF107; /*!< FIR Coefficient Register107 */ + __IO uint32_t COEF108; /*!< FIR Coefficient Register108 */ + __IO uint32_t COEF109; /*!< FIR Coefficient Register109 */ + __IO uint32_t COEF110; /*!< FIR Coefficient Register110 */ + __IO uint32_t COEF111; /*!< FIR Coefficient Register111 */ + __IO uint32_t COEF112; /*!< FIR Coefficient Register112 */ + __IO uint32_t COEF113; /*!< FIR Coefficient Register113 */ + __IO uint32_t COEF114; /*!< FIR Coefficient Register114 */ + __IO uint32_t COEF115; /*!< FIR Coefficient Register115 */ + __IO uint32_t COEF116; /*!< FIR Coefficient Register116 */ + __IO uint32_t COEF117; /*!< FIR Coefficient Register117 */ + __IO uint32_t COEF118; /*!< FIR Coefficient Register118 */ + __IO uint32_t COEF119; /*!< FIR Coefficient Register119 */ + __IO uint32_t COEF120; /*!< FIR Coefficient Register120 */ + __IO uint32_t COEF121; /*!< FIR Coefficient Register121 */ + __IO uint32_t COEF122; /*!< FIR Coefficient Register122 */ + __IO uint32_t COEF123; /*!< FIR Coefficient Register123 */ + __IO uint32_t COEF124; /*!< FIR Coefficient Register124 */ + __IO uint32_t COEF125; /*!< FIR Coefficient Register125 */ + __IO uint32_t COEF126; /*!< FIR Coefficient Register126 */ + __IO uint32_t COEF127; /*!< FIR Coefficient Register127 */ +} TSB_FIR_TypeDef; + +/** + * @brief Port A + */ +typedef struct { + __IO uint32_t DATA; /*!< Port A Data Register */ + __IO uint32_t CR; /*!< Port A Output Control Register */ + __IO uint32_t FR1; /*!< Port A Function Register 1 */ + __IO uint32_t FR2; /*!< Port A Function Register 2 */ + __IO uint32_t FR3; /*!< Port A Function Register 3 */ + uint32_t RESERVED0; + __IO uint32_t FR5; /*!< Port A Function Register 5 */ + __IO uint32_t FR6; /*!< Port A Function Register 6 */ + __IO uint32_t FR7; /*!< Port A Function Register 7 */ + __IO uint32_t FR8; /*!< Port A Function Register 8 */ + __IO uint32_t OD; /*!< Port A Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port A Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port A Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port A Input Control Register */ +} TSB_PA_TypeDef; + +/** + * @brief Port B + */ +typedef struct { + __IO uint32_t DATA; /*!< Port B Data Register */ + __IO uint32_t CR; /*!< Port B Output Control Register */ + __IO uint32_t FR1; /*!< Port B Function Register 1 */ + __IO uint32_t FR2; /*!< Port B Function Register 2 */ + __IO uint32_t FR3; /*!< Port B Function Register 3 */ + __IO uint32_t FR4; /*!< Port B Function Register 4 */ + __IO uint32_t FR5; /*!< Port B Function Register 5 */ + __IO uint32_t FR6; /*!< Port B Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< Port B Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port B Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port B Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port B Input Control Register */ +} TSB_PB_TypeDef; + +/** + * @brief Port C + */ +typedef struct { + __IO uint32_t DATA; /*!< Port C Data Register */ + __IO uint32_t CR; /*!< Port C Output Control Register */ + __IO uint32_t FR1; /*!< Port C Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< Port C Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port C Function Register 5 */ + uint32_t RESERVED2[3]; + __IO uint32_t OD; /*!< Port C Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port C Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port C Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port C Input Control Register */ +} TSB_PC_TypeDef; + +/** + * @brief Port D + */ +typedef struct { + __IO uint32_t DATA; /*!< Port D Data Register */ + __IO uint32_t CR; /*!< Port D Output Control Register */ + __IO uint32_t FR1; /*!< Port D Function Register 1 */ + __IO uint32_t FR2; /*!< Port D Function Register 2 */ + __IO uint32_t FR3; /*!< Port D Function Register 3 */ + __IO uint32_t FR4; /*!< Port D Function Register 4 */ + __IO uint32_t FR5; /*!< Port D Function Register 5 */ + __IO uint32_t FR6; /*!< Port D Function Register 6 */ + __IO uint32_t FR7; /*!< Port D Function Register 7 */ + __IO uint32_t FR8; /*!< Port D Function Register 8 */ + __IO uint32_t OD; /*!< Port D Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port D Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port D Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port D Input Control Register */ +} TSB_PD_TypeDef; + +/** + * @brief Port E + */ +typedef struct { + __IO uint32_t DATA; /*!< Port E Data Register */ + __IO uint32_t CR; /*!< Port E Output Control Register */ + __IO uint32_t FR1; /*!< Port E Function Register 1 */ + __IO uint32_t FR2; /*!< Port E Function Register 2 */ + __IO uint32_t FR3; /*!< Port E Function Register 3 */ + __IO uint32_t FR4; /*!< Port E Function Register 4 */ + __IO uint32_t FR5; /*!< Port E Function Register 5 */ + __IO uint32_t FR6; /*!< Port E Function Register 6 */ + __IO uint32_t FR7; /*!< Port E Function Register 7 */ + __IO uint32_t FR8; /*!< Port E Function Register 8 */ + __IO uint32_t OD; /*!< Port E Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port E Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port E Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port E Input Control Register */ +} TSB_PE_TypeDef; + +/** + * @brief Port F + */ +typedef struct { + __IO uint32_t DATA; /*!< Port F Data Register */ + __IO uint32_t CR; /*!< Port F Output Control Register */ + __IO uint32_t FR1; /*!< Port F Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port F Function Register 4 */ + __IO uint32_t FR5; /*!< Port F Function Register 5 */ + __IO uint32_t FR6; /*!< Port F Function Register 6 */ + __IO uint32_t FR7; /*!< Port F Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port F Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port F Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port F Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port F Input Control Register */ +} TSB_PF_TypeDef; + +/** + * @brief Port G + */ +typedef struct { + __IO uint32_t DATA; /*!< Port G Data Register */ + __IO uint32_t CR; /*!< Port G Output Control Register */ + __IO uint32_t FR1; /*!< Port G Function Register 1 */ + __IO uint32_t FR2; /*!< Port G Function Register 2 */ + __IO uint32_t FR3; /*!< Port G Function Register 3 */ + __IO uint32_t FR4; /*!< Port G Function Register 4 */ + __IO uint32_t FR5; /*!< Port G Function Register 5 */ + __IO uint32_t FR6; /*!< Port G Function Register 6 */ + __IO uint32_t FR7; /*!< Port G Function Register 7 */ + __IO uint32_t FR8; /*!< Port G Function Register 8 */ + __IO uint32_t OD; /*!< Port G Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port G Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port G Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port G Input Control Register */ +} TSB_PG_TypeDef; + +/** + * @brief Port H + */ +typedef struct { + __IO uint32_t DATA; /*!< Port H Data Register */ + __IO uint32_t CR; /*!< Port H Output Control Register */ + __IO uint32_t FR1; /*!< Port H Function Register 1 */ + uint32_t RESERVED0; + __IO uint32_t FR3; /*!< Port H Function Register 3 */ + __IO uint32_t FR4; /*!< Port H Function Register 4 */ + __IO uint32_t FR5; /*!< Port H Function Register 5 */ + uint32_t RESERVED1[2]; + __IO uint32_t FR8; /*!< Port H Function Register 8 */ + __IO uint32_t OD; /*!< Port H Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port H Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port H Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port H Input Control Register */ +} TSB_PH_TypeDef; + +/** + * @brief Port J + */ +typedef struct { + __IO uint32_t DATA; /*!< Port J Data Register */ + __IO uint32_t CR; /*!< Port J Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port J Function Register 2 */ + __IO uint32_t FR3; /*!< Port J Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port J Function Register 5 */ + __IO uint32_t FR6; /*!< Port J Function Register 6 */ + __IO uint32_t FR7; /*!< Port J Function Register 7 */ + uint32_t RESERVED2; + __IO uint32_t OD; /*!< Port J Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port J Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port J Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port J Input Control Register */ +} TSB_PJ_TypeDef; + +/** + * @brief Port K + */ +typedef struct { + __IO uint32_t DATA; /*!< Port K Data Register */ + __IO uint32_t CR; /*!< Port K Output Control Register */ + __IO uint32_t FR1; /*!< Port K Function Register 1 */ + __IO uint32_t FR2; /*!< Port K Function Register 2 */ + __IO uint32_t FR3; /*!< Port K Function Register 3 */ + __IO uint32_t FR4; /*!< Port K Function Register 4 */ + __IO uint32_t FR5; /*!< Port K Function Register 5 */ + __IO uint32_t FR6; /*!< Port K Function Register 6 */ + __IO uint32_t FR7; /*!< Port K Function Register 7 */ + __IO uint32_t FR8; /*!< Port K Function Register 8 */ + __IO uint32_t OD; /*!< Port K Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port K Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port K Pull-up Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port K Input Control Register */ +} TSB_PK_TypeDef; + +/** + * @brief Port L + */ +typedef struct { + __IO uint32_t DATA; /*!< Port L Data Register */ + __IO uint32_t CR; /*!< Port L Output Control Register */ + __IO uint32_t FR1; /*!< Port L Function Register 1 */ + __IO uint32_t FR2; /*!< Port L Function Register 2 */ + __IO uint32_t FR3; /*!< Port L Function Register 3 */ + uint32_t RESERVED0; + __IO uint32_t FR5; /*!< Port L Function Register 5 */ + __IO uint32_t FR6; /*!< Port L Function Register 6 */ + __IO uint32_t FR7; /*!< Port L Function Register 7 */ + __IO uint32_t FR8; /*!< Port L Function Register 8 */ + __IO uint32_t OD; /*!< Port L Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port L Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port L Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port L Input Control Register */ +} TSB_PL_TypeDef; + +/** + * @brief Port M + */ +typedef struct { + __IO uint32_t DATA; /*!< Port M Data Register */ + __IO uint32_t CR; /*!< Port M Output Control Register */ + __IO uint32_t FR1; /*!< Port M Function Register 1 */ + __IO uint32_t FR2; /*!< Port M Function Register 2 */ + __IO uint32_t FR3; /*!< Port M Function Register 3 */ + __IO uint32_t FR4; /*!< Port M Function Register 4 */ + __IO uint32_t FR5; /*!< Port M Function Register 5 */ + __IO uint32_t FR6; /*!< Port M Function Register 6 */ + __IO uint32_t FR7; /*!< Port M Function Register 7 */ + __IO uint32_t FR8; /*!< Port M Function Register 8 */ + __IO uint32_t OD; /*!< Port M Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port M Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port M Pull-up Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port M Input Control Register */ +} TSB_PM_TypeDef; + +/** + * @brief Port N + */ +typedef struct { + __IO uint32_t DATA; /*!< Port N Data Register */ + __IO uint32_t CR; /*!< Port N Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port N Opend Drain Control Register */ + __IO uint32_t PUP; /*!< Port N Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port N Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port N Input Control Register */ +} TSB_PN_TypeDef; + +/** + * @brief Port P + */ +typedef struct { + __IO uint32_t DATA; /*!< Port P Data Register */ + __IO uint32_t CR; /*!< Port P Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port P Function Register 2 */ + __IO uint32_t FR3; /*!< Port P Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port P Function Register 5 */ + uint32_t RESERVED2[3]; + __IO uint32_t OD; /*!< Port P Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port P Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port P Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port P Input Control Register */ +} TSB_PP_TypeDef; + +/** + * @brief Port R + */ +typedef struct { + __IO uint32_t DATA; /*!< Port R Data Register */ + __IO uint32_t CR; /*!< Port R Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port R Function Register 2 */ + __IO uint32_t FR3; /*!< Port R Function Register 3 */ + uint32_t RESERVED1[5]; + __IO uint32_t OD; /*!< Port R Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port R Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port R Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port R Input Control Register */ +} TSB_PR_TypeDef; + +/** + * @brief Port T + */ +typedef struct { + __IO uint32_t DATA; /*!< Port T Data Register */ + __IO uint32_t CR; /*!< Port T Output Control Register */ + __IO uint32_t FR1; /*!< Port T Function Register 1 */ + __IO uint32_t FR2; /*!< Port T Function Register 2 */ + __IO uint32_t FR3; /*!< Port T Function Register 3 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR6; /*!< Port T Function Register 6 */ + __IO uint32_t FR7; /*!< Port T Function Register 7 */ + __IO uint32_t FR8; /*!< Port T Function Register 8 */ + __IO uint32_t OD; /*!< Port T Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port T Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port T Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port T Input Control Register */ +} TSB_PT_TypeDef; + +/** + * @brief Port U + */ +typedef struct { + __IO uint32_t DATA; /*!< Port U Data Register */ + __IO uint32_t CR; /*!< Port U Output Control Register */ + uint32_t RESERVED0; + __IO uint32_t FR2; /*!< Port U Function Register 2 */ + __IO uint32_t FR3; /*!< Port U Function Register 3 */ + uint32_t RESERVED1; + __IO uint32_t FR5; /*!< Port U Function Register 5 */ + __IO uint32_t FR6; /*!< Port U Function Register 6 */ + __IO uint32_t FR7; /*!< Port U Function Register 7 */ + __IO uint32_t FR8; /*!< Port U Function Register 8 */ + __IO uint32_t OD; /*!< Port U Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port U Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port U Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port U Input Control Register */ +} TSB_PU_TypeDef; + +/** + * @brief Port V + */ +typedef struct { + __IO uint32_t DATA; /*!< Port V Data Register */ + __IO uint32_t CR; /*!< Port V OutPut Control Register */ + __IO uint32_t FR1; /*!< Port V Function Register 1 */ + __IO uint32_t FR2; /*!< Port V Function Register 2 */ + __IO uint32_t FR3; /*!< Port V Function Register 3 */ + __IO uint32_t FR4; /*!< Port V Function Register 4 */ + __IO uint32_t FR5; /*!< Port V Function Register 5 */ + __IO uint32_t FR6; /*!< Port V Function Register 6 */ + __IO uint32_t FR7; /*!< Port V Function Register 7 */ + __IO uint32_t FR8; /*!< Port V Function Register 8 */ + __IO uint32_t OD; /*!< Port V Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port V Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port V Pull-down Control Register */ + uint32_t RESERVED0; + __IO uint32_t IE; /*!< Port V InPut Control Register */ +} TSB_PV_TypeDef; + +/** + * @brief Port W + */ +typedef struct { + __IO uint32_t DATA; /*!< Port W Data Register */ + __IO uint32_t CR; /*!< Port W OutPut Control Register */ + uint32_t RESERVED0[2]; + __IO uint32_t FR3; /*!< Port W Function Register 3 */ + __IO uint32_t FR4; /*!< Port W Function Register 4 */ + __IO uint32_t FR5; /*!< Port W Function Register 5 */ + __IO uint32_t FR6; /*!< Port W Function Register 6 */ + __IO uint32_t FR7; /*!< Port W Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port W Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port W Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port W Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port W InPut Control Register */ +} TSB_PW_TypeDef; + +/** + * @brief Port Y + */ +typedef struct { + __IO uint32_t DATA; /*!< Port Y Data Register */ + __IO uint32_t CR; /*!< Port Y OutPut Control Register */ + __IO uint32_t FR1; /*!< Port Y Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port Y Function Register 4 */ + uint32_t RESERVED1; + __IO uint32_t FR6; /*!< Port Y Function Register 6 */ + uint32_t RESERVED2[2]; + __IO uint32_t OD; /*!< Port Y Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port Y Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port Y Pull-down Control Register */ + uint32_t RESERVED3; + __IO uint32_t IE; /*!< Port Y InPut Control Register */ +} TSB_PY_TypeDef; + +/** + * @brief Internal High-speed Oscillation Adjustment + */ +typedef struct { + __IO uint32_t OSCPRO; /*!< TRM Protection Register */ + __IO uint32_t OSCEN; /*!< TRM User Trimming Value Enable Register */ + uint32_t RESERVED0[2]; + __I uint32_t OSCINIT0; /*!< TRM Initial trimming level monitor register0 */ + __I uint32_t OSCINIT1; /*!< TRM Initial trimming level monitor register1 */ + __I uint32_t OSCINIT2; /*!< TRM Initial trimming level monitor register2 */ + uint32_t RESERVED1; + __IO uint32_t OSCSET0; /*!< TRM Trimming level setting register0 for User*/ + __IO uint32_t OSCSET1; /*!< TRM Trimming level setting register1 for User*/ + __IO uint32_t OSCSET2; /*!< TRM Trimming level setting register2 for User*/ +} TSB_TRM_TypeDef; + +/** + * @brief Oscillation Frequency Detector (OFD) + */ +typedef struct { + __IO uint32_t CR1; /*!< OFD Frequency Detection Control Register 1 */ + __IO uint32_t CR2; /*!< OFD Frequency Detection Control Register 2 */ + __IO uint32_t MN0; /*!< OFD Minimum Detection Frequency Setting Register 0 (EHOSC)*/ + __IO uint32_t MN1; /*!< OFD Minimum Detection Frequency Setting Register 1 (fc)*/ + __IO uint32_t MX0; /*!< OFD Maximum Detection Frequency Setting Register 0 (EHOSC)*/ + __IO uint32_t MX1; /*!< OFD Maximum Detection Frequency Setting Register 1 (fc)*/ + __IO uint32_t RST; /*!< OFD Reset Control Register */ + __I uint32_t STAT; /*!< OFD Status Register */ + __IO uint32_t MON; /*!< OFD Detection Target Clock 1 Monitor Setting Register*/ +} TSB_OFD_TypeDef; + +/** + * @brief Real Time Clock (RTC) + */ +typedef struct { + __IO uint8_t SECR; /*!< RTC Second column register (PAGE0) */ + __IO uint8_t MINR; /*!< RTC Minute column register (PAGE0/1) */ + __IO uint8_t HOURR; /*!< RTC Hour column register (PAGE0/1) */ + uint8_t RESERVED0; + __IO uint8_t DAYR; /*!< RTC Day of the week column register (PAGE0/1)*/ + __IO uint8_t DATER; /*!< RTC Day column register (PAGE0/1) */ + __IO uint8_t MONTHR; /*!< RTC Month column register (PAGE0) */ + __IO uint8_t YEARR; /*!< RTC Year column register (PAGE0) */ + __IO uint8_t PAGER; /*!< RTC PAGE register (PAGE0/1) */ + uint8_t RESERVED1[3]; + __IO uint8_t RESTR; /*!< RTC Reset register (PAGE0/1) */ + uint8_t RESERVED2; + __IO uint8_t PROTECT; /*!< RTC Protect register */ + __IO uint8_t ADJCTL; /*!< RTC Correction Function Control Register */ + __IO uint8_t ADJDAT; /*!< RTC Correction Value Register */ + __IO uint8_t ADJSIGN; /*!< RTC Correction Value sign Register */ +} TSB_RTC_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct { + __IO uint32_t EN; /*!< CEC Enable Register */ + __IO uint32_t ADD; /*!< CEC Logical Address Register */ + __O uint32_t RESET; /*!< CEC Software Reset Register */ + __IO uint32_t REN; /*!< CEC Receive Enable Register */ + __I uint32_t RBUF; /*!< CEC Receive Buffer Register */ + __IO uint32_t RCR1; /*!< CEC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< CEC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< CEC Receive Control Register 3 */ + __IO uint32_t TEN; /*!< CEC Transmit Enable Register */ + __IO uint32_t TBUF; /*!< CEC Transmit Buffer Register */ + __IO uint32_t TCR; /*!< CEC Transmit Control Register */ + __I uint32_t RSTAT; /*!< CEC Receive Interrupt Status Register */ + __I uint32_t TSTAT; /*!< CEC Transmit Interrupt Status Register */ + __IO uint32_t FSSEL; /*!< CEC sampling clock select Register */ +} TSB_CEC_TypeDef; + +/** + * @brief Remote Control Signal Preprocessor (RMC) + */ +typedef struct { + __IO uint32_t EN; /*!< RMC Enable Register */ + __IO uint32_t REN; /*!< RMC Receive Enable Register */ + __I uint32_t RBUF1; /*!< RMC Receive Data Buffer Register 1 */ + __I uint32_t RBUF2; /*!< RMC Receive Data Buffer Register 2 */ + __I uint32_t RBUF3; /*!< RMC Receive Data Buffer Register 3 */ + __IO uint32_t RCR1; /*!< RMC Receive Control Register 1 */ + __IO uint32_t RCR2; /*!< RMC Receive Control Register 2 */ + __IO uint32_t RCR3; /*!< RMC Receive Control Register 3 */ + __IO uint32_t RCR4; /*!< RMC Receive Control Register 4 */ + __I uint32_t RSTAT; /*!< RMC Receive Status Register */ + __IO uint32_t END1; /*!< RMC Receive End Bit Number Register 1 */ + __IO uint32_t END2; /*!< RMC Receive End Bit Number Register 2 */ + __IO uint32_t END3; /*!< RMC Receive End Bit Number Register 3 */ + __IO uint32_t FSSEL; /*!< RMC Sampling Clock Selection Register */ +} TSB_RMC_TypeDef; + +/** + * @brief + */ +typedef struct { + __IO uint32_t MDEN; /*!< PMD Enable Register */ + __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ + __IO uint32_t MDCR; /*!< PMD Control Register */ + __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ + __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ + __IO uint32_t RATE; /*!< PWM Frequency Register */ + __IO uint32_t CMPU; /*!< PMD PWM duty comparison U Register */ + __IO uint32_t CMPV; /*!< PMD PWM duty comparison V Register */ + __IO uint32_t CMPW; /*!< PMD PWM duty comparison W Register */ + __IO uint32_t MODESEL; /*!< PMD Mode Select Register */ + __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ + __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ + __O uint32_t EMGREL; /*!< PMD EMG Release Register */ + __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ + __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ + __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ + __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ + __IO uint32_t DTR; /*!< PMD Dead Time Register */ + __IO uint32_t TRGCMP0; /*!< PMD Trigger comparison Register 0 */ + __IO uint32_t TRGCMP1; /*!< PMD Trigger comparison Register 1 */ + __IO uint32_t TRGCMP2; /*!< PMD Trigger comparison Register 2 */ + __IO uint32_t TRGCMP3; /*!< PMD Trigger comparison Register 3 */ + __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ + __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ + __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ + __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ + __IO uint32_t VPWMPH; /*!< PMD V-phase phase difference register */ + __IO uint32_t WPWMPH; /*!< PMD W-phase phase difference register */ + __IO uint32_t MBUFCR; /*!< PMD Intermediate buffer control register */ + __IO uint32_t SYNCCR; /*!< Synchronization control between the PMD channel*/ +} TSB_PMD_TypeDef; + +/** + * @brief + */ +typedef struct { + __IO uint32_t EN; /*!< Interval Sencing Detector(ISD) */ + __IO uint32_t CLKCR; /*!< ISD Clock Control Register */ + __IO uint32_t OCR0; /*!< ISD Output Control Register 0 */ + __IO uint32_t OCR1; /*!< ISD Output Control Register 1 */ + __IO uint32_t ICR; /*!< ISD Input Control Register */ + __IO uint32_t CR; /*!< ISD Control Register */ + __I uint32_t BR; /*!< ISD Buffer Register */ + __I uint32_t SR; /*!< ISD Status Register */ + __IO uint32_t INTCR; /*!< ISD Interrupt Control Register */ +} TSB_ISD_TypeDef; + +/** + * @brief USB interface + */ +typedef struct { + __IO uint32_t GOTGCTL; /*!< OTG Control and Status Register */ + __IO uint32_t GOTGINT; /*!< OTG Interrupt Register */ + __IO uint32_t GAHBCFG; /*!< AHB Configuration Register */ + __IO uint32_t GUSBCFG; /*!< USB Configuration Register */ + __IO uint32_t GRSTCTL; /*!< Reset Register */ + __IO uint32_t GINTSTS; /*!< Interrupt Register */ + __IO uint32_t GINTMSK; /*!< Interrupt Mask Register */ + __I uint32_t GRXSTSR; /*!< Receive Status Debug Read Register */ + __I uint32_t GRXSTSP; /*!< Receive Status Read/Pop Register */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register */ + __IO uint32_t GNPTXFSIZ; /*!< Non-periodic Transmit FIFO Size Register */ + __I uint32_t GNPTXSTS; /*!< Non-periodic Transmit FIFO/Queue Status Register*/ + uint32_t RESERVED0[5]; + __I uint32_t GHWCFG1; /*!< User Hardware Configuration 1 Register */ + __I uint32_t GHWCFG2; /*!< User Hardware Configuration 2 Register */ + __I uint32_t GHWCFG3; /*!< User Hardware Configuration 3 Register */ + __I uint32_t GHWCFG4; /*!< User Hardware Configuration 4 Register */ + uint32_t RESERVED1[2]; + __IO uint32_t GDFIFOCFG; /*!< Global DFIFO Configuration Register */ + uint32_t RESERVED2[40]; + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Transmit FIFO Size Register */ + __IO uint32_t DIEPTXF1; /*!< Device IN Endpoint Transmit FIFO Size Register 1*/ + __IO uint32_t DIEPTXF2; /*!< Device IN Endpoint Transmit FIFO Size Register 2*/ + __IO uint32_t DIEPTXF3; /*!< Device IN Endpoint Transmit FIFO Size Register 3*/ + __IO uint32_t DIEPTXF4; /*!< Device IN Endpoint Transmit FIFO Size Register 4*/ + __IO uint32_t DIEPTXF5; /*!< Device IN Endpoint Transmit FIFO Size Register 5*/ + uint32_t RESERVED3[186]; + __IO uint32_t HCFG; /*!< Host Configuration Register */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register */ + __I uint32_t HFNUM; /*!< Host Frame Number/Frame Time Remaining Register*/ + uint32_t RESERVED4; + __I uint32_t HPTXSTS; /*!< Host Periodic Transmit FIFO/Queue Status Register*/ + __I uint32_t HAINT; /*!< Host All Channels Interrupt Register */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask Register */ + __IO uint32_t HFLBADDR; /*!< Host Frame List Base Address Register */ + uint32_t RESERVED5[8]; + __IO uint32_t HPRT; /*!< Host Port Control and Status Register */ + uint32_t RESERVED6[47]; + __IO uint32_t HCCHAR0; /*!< Host Channel 0 Characteristics Register */ + __IO uint32_t HCSPLT0; /*!< Host Channel 0 Split Control Register */ + __IO uint32_t HCINT0; /*!< Host Channel 0 Interrupt Register */ + __IO uint32_t HCINTMSK0; /*!< Host Channel 0 Interrupt Mask Register */ + __IO uint32_t HCTSIZ0; /*!< Host Channel 0 Transfer Size Register */ + __IO uint32_t HCDMA0; /*!< Host Channel 0 DMA Address Register */ + uint32_t RESERVED7; + __I uint32_t HCDMAB0; /*!< Host Channel 0 DMA Buffer Address Register */ + __IO uint32_t HCCHAR1; /*!< Host Channel 1 Characteristics Register */ + __IO uint32_t HCSPLT1; /*!< Host Channel 1 Split Control Register */ + __IO uint32_t HCINT1; /*!< Host Channel 1 Interrupt Register */ + __IO uint32_t HCINTMSK1; /*!< Host Channel 1 Interrupt Mask Register */ + __IO uint32_t HCTSIZ1; /*!< Host Channel 1 Transfer Size Register */ + __IO uint32_t HCDMA1; /*!< Host Channel 1 DMA Address Register */ + uint32_t RESERVED8; + __I uint32_t HCDMAB1; /*!< Host Channel 1 DMA Buffer Address Register */ + __IO uint32_t HCCHAR2; /*!< Host Channel 2 Characteristics Register */ + __IO uint32_t HCSPLT2; /*!< Host Channel 2 Split Control Register */ + __IO uint32_t HCINT2; /*!< Host Channel 2 Interrupt Register */ + __IO uint32_t HCINTMSK2; /*!< Host Channel 2 Interrupt Mask Register */ + __IO uint32_t HCTSIZ2; /*!< Host Channel 2 Transfer Size Register */ + __IO uint32_t HCDMA2; /*!< Host Channel 2 DMA Address Register */ + uint32_t RESERVED9; + __I uint32_t HCDMAB2; /*!< Host Channel 2 DMA Buffer Address Register */ + __IO uint32_t HCCHAR3; /*!< Host Channel 3 Characteristics Register */ + __IO uint32_t HCSPLT3; /*!< Host Channel 3 Split Control Register */ + __IO uint32_t HCINT3; /*!< Host Channel 3 Interrupt Register */ + __IO uint32_t HCINTMSK3; /*!< Host Channel 3 Interrupt Mask Register */ + __IO uint32_t HCTSIZ3; /*!< Host Channel 3 Transfer Size Register */ + __IO uint32_t HCDMA3; /*!< Host Channel 3 DMA Address Register */ + uint32_t RESERVED10; + __I uint32_t HCDMAB3; /*!< Host Channel 3 DMA Buffer Address Register */ + __IO uint32_t HCCHAR4; /*!< Host Channel 4 Characteristics Register */ + __IO uint32_t HCSPLT4; /*!< Host Channel 4 Split Control Register */ + __IO uint32_t HCINT4; /*!< Host Channel 4 Interrupt Register */ + __IO uint32_t HCINTMSK4; /*!< Host Channel 4 Interrupt Mask Register */ + __IO uint32_t HCTSIZ4; /*!< Host Channel 4 Transfer Size Register */ + __IO uint32_t HCDMA4; /*!< Host Channel 4 DMA Address Register */ + uint32_t RESERVED11; + __I uint32_t HCDMAB4; /*!< Host Channel 4 DMA Buffer Address Register */ + __IO uint32_t HCCHAR5; /*!< Host Channel 5 Characteristics Register */ + __IO uint32_t HCSPLT5; /*!< Host Channel 5 Split Control Register */ + __IO uint32_t HCINT5; /*!< Host Channel 5 Interrupt Register */ + __IO uint32_t HCINTMSK5; /*!< Host Channel 5 Interrupt Mask Register */ + __IO uint32_t HCTSIZ5; /*!< Host Channel 5 Transfer Size Register */ + __IO uint32_t HCDMA5; /*!< Host Channel 5 DMA Address Register */ + uint32_t RESERVED12; + __I uint32_t HCDMAB5; /*!< Host Channel 5 DMA Buffer Address Register */ + __IO uint32_t HCCHAR6; /*!< Host Channel 6 Characteristics Register */ + __IO uint32_t HCSPLT6; /*!< Host Channel 6 Split Control Register */ + __IO uint32_t HCINT6; /*!< Host Channel 6 Interrupt Register */ + __IO uint32_t HCINTMSK6; /*!< Host Channel 6 Interrupt Mask Register */ + __IO uint32_t HCTSIZ6; /*!< Host Channel 6 Transfer Size Register */ + __IO uint32_t HCDMA6; /*!< Host Channel 6 DMA Address Register */ + uint32_t RESERVED13; + __I uint32_t HCDMAB6; /*!< Host Channel 6 DMA Buffer Address Register */ + __IO uint32_t HCCHAR7; /*!< Host Channel 7 Characteristics Register */ + __IO uint32_t HCSPLT7; /*!< Host Channel 7 Split Control Register */ + __IO uint32_t HCINT7; /*!< Host Channel 7 Interrupt Register */ + __IO uint32_t HCINTMSK7; /*!< Host Channel 7 Interrupt Mask Register */ + __IO uint32_t HCTSIZ7; /*!< Host Channel 7 Transfer Size Register */ + __IO uint32_t HCDMA7; /*!< Host Channel 7 DMA Address Register */ + uint32_t RESERVED14; + __I uint32_t HCDMAB7; /*!< Host Channel 7 DMA Buffer Address Register */ + __IO uint32_t HCCHAR8; /*!< Host Channel 8 Characteristics Register */ + __IO uint32_t HCSPLT8; /*!< Host Channel 8 Split Control Register */ + __IO uint32_t HCINT8; /*!< Host Channel 8 Interrupt Register */ + __IO uint32_t HCINTMSK8; /*!< Host Channel 8 Interrupt Mask Register */ + __IO uint32_t HCTSIZ8; /*!< Host Channel 8 Transfer Size Register */ + __IO uint32_t HCDMA8; /*!< Host Channel 8 DMA Address Register */ + uint32_t RESERVED15; + __I uint32_t HCDMAB8; /*!< Host Channel 8 DMA Buffer Address Register */ + __IO uint32_t HCCHAR9; /*!< Host Channel 9 Characteristics Register */ + __IO uint32_t HCSPLT9; /*!< Host Channel 9 Split Control Register */ + __IO uint32_t HCINT9; /*!< Host Channel 9 Interrupt Register */ + __IO uint32_t HCINTMSK9; /*!< Host Channel 9 Interrupt Mask Register */ + __IO uint32_t HCTSIZ9; /*!< Host Channel 9 Transfer Size Register */ + __IO uint32_t HCDMA9; /*!< Host Channel 9 DMA Address Register */ + uint32_t RESERVED16; + __I uint32_t HCDMAB9; /*!< Host Channel 9 DMA Buffer Address Register */ + __IO uint32_t HCCHAR10; /*!< Host Channel 10 Characteristics Register */ + __IO uint32_t HCSPLT10; /*!< Host Channel 10 Split Control Register */ + __IO uint32_t HCINT10; /*!< Host Channel 10 Interrupt Register */ + __IO uint32_t HCINTMSK10; /*!< Host Channel 10 Interrupt Mask Register */ + __IO uint32_t HCTSIZ10; /*!< Host Channel 10 Transfer Size Register */ + __IO uint32_t HCDMA10; /*!< Host Channel 10 DMA Address Register */ + uint32_t RESERVED17; + __I uint32_t HCDMAB10; /*!< Host Channel 10 DMA Buffer Address Register */ + __IO uint32_t HCCHAR11; /*!< Host Channel 11 Characteristics Register */ + __IO uint32_t HCSPLT11; /*!< Host Channel 11 Split Control Register */ + __IO uint32_t HCINT11; /*!< Host Channel 11 Interrupt Register */ + __IO uint32_t HCINTMSK11; /*!< Host Channel 11 Interrupt Mask Register */ + __IO uint32_t HCTSIZ11; /*!< Host Channel 11 Transfer Size Register */ + __IO uint32_t HCDMA11; /*!< Host Channel 11 DMA Address Register */ + uint32_t RESERVED18; + __I uint32_t HCDMAB11; /*!< Host Channel 11 DMA Buffer Address Register */ + uint32_t RESERVED19[96]; + __IO uint32_t DCFG; /*!< Device Configuration Register */ + __IO uint32_t DCTL; /*!< Device Control Register */ + __I uint32_t DSTS; /*!< Device Status Register */ + uint32_t RESERVED20; + __IO uint32_t DIEPMSK; /*!< Device IN Endpoint Common Interrupt Mask Register*/ + __IO uint32_t DOEPMSK; /*!< Device OUT Endpoint Common Interrupt Mask Register*/ + __I uint32_t DAINT; /*!< Device All Endpoints Interrupt Register */ + __IO uint32_t DAINTMSK; /*!< Device All Endpoints Interrupt Mask Register */ + uint32_t RESERVED21[2]; + __IO uint32_t DVBUSDIS; /*!< Device VBUS Discharge Time Register */ + __IO uint32_t DVBUSPULSE; /*!< Device VBUS Pulsing Time Register */ + __IO uint32_t DTHRCTL; /*!< Device Threshold Control Register */ + __IO uint32_t DIEPEMPMSK; /*!< Device IN Endpoint FIFO Empty Interrupt Mask Register*/ + uint32_t RESERVED22[50]; + __IO uint32_t DIEPCTL0; /*!< Device Control IN Endpoint 0 Control Register*/ + uint32_t RESERVED23; + __IO uint32_t DIEPINT0; /*!< Device IN Endpoint 0 Interrupt Register */ + uint32_t RESERVED24; + __IO uint32_t DIEPTSIZ0; /*!< Device IN Endpoint 0 Transfer Size Register */ + __IO uint32_t DIEPDMA0; /*!< Device IN Endpoint 0 DMA Address Register */ + __I uint32_t DTXFSTS0; /*!< Device IN Endpoint Transmit FIFO Status Register 0*/ + __I uint32_t DIEPDMAB0; /*!< Device IN Endpoint 16 Buffer Address Register*/ + __IO uint32_t DIEPCTL1; /*!< Device Control IN Endpoint 1 Control Register*/ + uint32_t RESERVED25; + __IO uint32_t DIEPINT1; /*!< Device IN Endpoint 1 Interrupt Register */ + uint32_t RESERVED26; + __IO uint32_t DIEPTSIZ1; /*!< Device IN Endpoint 1 Transfer Size Register. */ + __IO uint32_t DIEPDMA1; /*!< Device IN Endpoint 1 DMA Address Register */ + __I uint32_t DTXFSTS1; /*!< Device IN Endpoint Transmit FIFO Status Register 1*/ + __I uint32_t DIEPDMAB1; /*!< Device IN Endpoint 1 Buffer Address Register */ + __IO uint32_t DIEPCTL2; /*!< Device Control IN Endpoint 2 Control Register*/ + uint32_t RESERVED27; + __IO uint32_t DIEPINT2; /*!< Device IN Endpoint 2 Interrupt Register */ + uint32_t RESERVED28; + __IO uint32_t DIEPTSIZ2; /*!< Device IN Endpoint 2 Transfer Size Register. */ + __IO uint32_t DIEPDMA2; /*!< Device IN Endpoint 2 DMA Address Register */ + __I uint32_t DTXFSTS2; /*!< Device IN Endpoint Transmit FIFO Status Register 2*/ + __I uint32_t DIEPDMAB2; /*!< Device IN Endpoint 2 Buffer Address Register */ + __IO uint32_t DIEPCTL3; /*!< Device Control IN Endpoint 3 Control Register*/ + uint32_t RESERVED29; + __IO uint32_t DIEPINT3; /*!< Device IN Endpoint 3 Interrupt Register */ + uint32_t RESERVED30; + __IO uint32_t DIEPTSIZ3; /*!< Device IN Endpoint 3 Transfer Size Register. */ + __IO uint32_t DIEPDMA3; /*!< Device IN Endpoint 3 DMA Address Register */ + __I uint32_t DTXFSTS3; /*!< Device IN Endpoint Transmit FIFO Status Register 3*/ + __I uint32_t DIEPDMAB3; /*!< Device IN Endpoint 3 Buffer Address Register */ + __IO uint32_t DIEPCTL4; /*!< Device Control IN Endpoint 4 Control Register*/ + uint32_t RESERVED31; + __IO uint32_t DIEPINT4; /*!< Device IN Endpoint 4 Interrupt Register */ + uint32_t RESERVED32; + __IO uint32_t DIEPTSIZ4; /*!< Device IN Endpoint 4 Transfer Size Register. */ + __IO uint32_t DIEPDMA4; /*!< Device IN Endpoint 4 DMA Address Register */ + __I uint32_t DTXFSTS4; /*!< Device IN Endpoint Transmit FIFO Status Register 4*/ + __I uint32_t DIEPDMAB4; /*!< Device IN Endpoint 4 Buffer Address Register */ + __IO uint32_t DIEPCTL5; /*!< Device Control IN Endpoint 5 Control Register*/ + uint32_t RESERVED33; + __IO uint32_t DIEPINT5; /*!< Device IN Endpoint 5 Interrupt Register */ + uint32_t RESERVED34; + __IO uint32_t DIEPTSIZ5; /*!< Device IN Endpoint 5 Transfer Size Register. */ + __IO uint32_t DIEPDMA5; /*!< Device IN Endpoint 5 DMA Address Register */ + __I uint32_t DTXFSTS5; /*!< Device IN Endpoint Transmit FIFO Status Register 5*/ + __I uint32_t DIEPDMAB5; /*!< Device IN Endpoint 5 Buffer Address Register */ + uint32_t RESERVED35[80]; + __IO uint32_t DOEPCTL0; /*!< Device Control OUT Endpoint 0 Control Register*/ + uint32_t RESERVED36; + __IO uint32_t DOEPINT0; /*!< Device OUT Endpoint 0 Interrupt Register */ + uint32_t RESERVED37; + __IO uint32_t DOEPTSIZ0; /*!< Device OUT Endpoint 0 Transfer Size Register */ + __IO uint32_t DOEPDMA0; /*!< Device OUT Endpoint 0 DMA Address Register */ + uint32_t RESERVED38; + __I uint32_t DOEPDMAB0; /*!< Device OUT Endpoint 16 Buffer Address Register*/ + __IO uint32_t DOEPCTL1; /*!< Device Control OUT Endpoint 1 Control Register*/ + uint32_t RESERVED39; + __IO uint32_t DOEPINT1; /*!< Device OUT Endpoint 1 Interrupt Register */ + uint32_t RESERVED40; + __IO uint32_t DOEPTSIZ1; /*!< Device OUT Endpoint 1 Transfer Size Register */ + __IO uint32_t DOEPDMA1; /*!< Device OUT Endpoint 1 DMA Address Register */ + uint32_t RESERVED41; + __I uint32_t DOEPDMAB1; /*!< Device OUT Endpoint 1 Buffer Address Register*/ + __IO uint32_t DOEPCTL2; /*!< Device Control OUT Endpoint 2 Control Register*/ + uint32_t RESERVED42; + __IO uint32_t DOEPINT2; /*!< Device OUT Endpoint 2 Interrupt Register */ + uint32_t RESERVED43; + __IO uint32_t DOEPTSIZ2; /*!< Device OUT Endpoint 2 Transfer Size Register */ + __IO uint32_t DOEPDMA2; /*!< Device OUT Endpoint 2 DMA Address Register */ + uint32_t RESERVED44; + __I uint32_t DOEPDMAB2; /*!< Device OUT Endpoint 2 Buffer Address Register*/ + __IO uint32_t DOEPCTL3; /*!< Device Control OUT Endpoint 3 Control Register*/ + uint32_t RESERVED45; + __IO uint32_t DOEPINT3; /*!< Device OUT Endpoint 3 Interrupt Register */ + uint32_t RESERVED46; + __IO uint32_t DOEPTSIZ3; /*!< Device OUT Endpoint 3 Transfer Size Register */ + __IO uint32_t DOEPDMA3; /*!< Device OUT Endpoint 3 DMA Address Register */ + uint32_t RESERVED47; + __I uint32_t DOEPDMAB3; /*!< Device OUT Endpoint 3 Buffer Address Register*/ + __IO uint32_t DOEPCTL4; /*!< Device Control OUT Endpoint 4 Control Register*/ + uint32_t RESERVED48; + __IO uint32_t DOEPINT4; /*!< Device OUT Endpoint 4 Interrupt Register */ + uint32_t RESERVED49; + __IO uint32_t DOEPTSIZ4; /*!< Device OUT Endpoint 4 Transfer Size Register */ + __IO uint32_t DOEPDMA4; /*!< Device OUT Endpoint 4 DMA Address Register */ + uint32_t RESERVED50; + __I uint32_t DOEPDMAB4; /*!< Device OUT Endpoint 4 Buffer Address Register*/ + __IO uint32_t DOEPCTL5; /*!< Device Control OUT Endpoint 5 Control Register*/ + uint32_t RESERVED51; + __IO uint32_t DOEPINT5; /*!< Device OUT Endpoint 5 Interrupt Register */ + uint32_t RESERVED52; + __IO uint32_t DOEPTSIZ5; /*!< Device OUT Endpoint 5 Transfer Size Register */ + __IO uint32_t DOEPDMA5; /*!< Device OUT Endpoint 5 DMA Address Register */ + uint32_t RESERVED53; + __I uint32_t DOEPDMAB5; /*!< Device OUT Endpoint 5 Buffer Address Register*/ + uint32_t RESERVED54[144]; + __IO uint32_t PCGCCTL; /*!< Power and Clock Gating Control Register */ + uint32_t RESERVED55[127]; + __IO uint32_t DFIFO_0; /*!< Data FIFO Access Register Map 0 */ + uint32_t RESERVED56[1023]; + __IO uint32_t DFIFO_1; /*!< Data FIFO Access Register Map 1 */ + uint32_t RESERVED57[1023]; + __IO uint32_t DFIFO_2; /*!< Data FIFO Access Register Map 2 */ + uint32_t RESERVED58[1023]; + __IO uint32_t DFIFO_3; /*!< Data FIFO Access Register Map 3 */ + uint32_t RESERVED59[1023]; + __IO uint32_t DFIFO_4; /*!< Data FIFO Access Register Map 4 */ + uint32_t RESERVED60[1023]; + __IO uint32_t DFIFO_5; /*!< Data FIFO Access Register Map 5 */ + uint32_t RESERVED61[11263]; + __IO uint32_t PHY_CTRL; /*!< PHY (USBIO) Control Register */ + __IO uint32_t PHY_CTRL_SET; /*!< PHY (USBIO) Control Register */ + __IO uint32_t PHY_CTRL_CLR; /*!< PHY (USBIO) Control Clear Register */ + uint32_t RESERVED62; + __IO uint32_t MAC_CTRL0; /*!< MAC Control Register 0 */ + __IO uint32_t MAC_CTRL1; /*!< MAC Control Register 1 */ + __IO uint32_t MAC_CTRL2; /*!< MAC Control Register 2 */ + uint32_t RESERVED63; + __IO uint32_t WKUP_CTRL0; /*!< Wakeup Control Register 0 */ + __IO uint32_t WKUP_CTRL1; /*!< Wakeup Control Register 1 */ + __IO uint32_t WKUP_INTEN; /*!< Wakeup Interrupt Enable Register */ + __I uint32_t WKUP_INTFLAG; /*!< Wakeup Interrupt detection Flag Register */ + __I uint32_t WKUP_INTSTS; /*!< Wakeup Interrupt detection Status Register */ + __I uint32_t WKUP_SIGMON; /*!< Wakeup Interrupt factor Signal monitor Register*/ + uint32_t RESERVED64[2]; + __IO uint32_t VBUS_SIGMON_CTRL; /*!< VBUS signal monitor Control Register */ +} TSB_USB_TypeDef; + +/** + * @brief + */ +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ + __IO uint32_t SSR; /*!< Flash Security Status Register */ + __O uint32_t KCR; /*!< Flash Key Code Register */ + uint32_t RESERVED1; + __IO uint32_t SR0; /*!< Flash Status Register 0 */ + uint32_t RESERVED2[3]; + __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ + __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ + __I uint32_t PSR2; /*!< Flash Protect Status Register 2 */ + uint32_t RESERVED3[3]; + __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ + uint32_t RESERVED4; + __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ + __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ + __IO uint32_t PMR2; /*!< Flash Protect Mask Register 2 */ + uint32_t RESERVED5[3]; + __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ + uint32_t RESERVED6[37]; + __I uint32_t SR1; /*!< Flash Status Register 1 */ + __I uint32_t SWPSR; /*!< Flash Memory SWP Status Register */ + uint32_t RESERVED7[14]; + __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ + uint32_t RESERVED8; + __IO uint32_t CR; /*!< Flash Control Register */ + __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ + __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ + __IO uint32_t ACCR; /*!< Flash Access Control Register */ + __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ + uint32_t RESERVED9[1071]; + __IO uint32_t RACCR; /*!< RAM Access Control Register */ +} TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_DMACA_BASE (PERI_BASE + 0x0000000UL) +#define TSB_DMACB_BASE (PERI_BASE + 0x0001000UL) +#define TSB_CANAMB0_BASE (PERI_BASE + 0x0005000UL) +#define TSB_CANAMB1_BASE (PERI_BASE + 0x0005020UL) +#define TSB_CANAMB2_BASE (PERI_BASE + 0x0005040UL) +#define TSB_CANAMB3_BASE (PERI_BASE + 0x0005060UL) +#define TSB_CANAMB4_BASE (PERI_BASE + 0x0005080UL) +#define TSB_CANAMB5_BASE (PERI_BASE + 0x00050A0UL) +#define TSB_CANAMB6_BASE (PERI_BASE + 0x00050C0UL) +#define TSB_CANAMB7_BASE (PERI_BASE + 0x00050E0UL) +#define TSB_CANAMB8_BASE (PERI_BASE + 0x0005100UL) +#define TSB_CANAMB9_BASE (PERI_BASE + 0x0005120UL) +#define TSB_CANAMB10_BASE (PERI_BASE + 0x0005140UL) +#define TSB_CANAMB11_BASE (PERI_BASE + 0x0005160UL) +#define TSB_CANAMB12_BASE (PERI_BASE + 0x0005180UL) +#define TSB_CANAMB13_BASE (PERI_BASE + 0x00051A0UL) +#define TSB_CANAMB14_BASE (PERI_BASE + 0x00051C0UL) +#define TSB_CANAMB15_BASE (PERI_BASE + 0x00051E0UL) +#define TSB_CANAMB16_BASE (PERI_BASE + 0x0005200UL) +#define TSB_CANAMB17_BASE (PERI_BASE + 0x0005220UL) +#define TSB_CANAMB18_BASE (PERI_BASE + 0x0005240UL) +#define TSB_CANAMB19_BASE (PERI_BASE + 0x0005260UL) +#define TSB_CANAMB20_BASE (PERI_BASE + 0x0005280UL) +#define TSB_CANAMB21_BASE (PERI_BASE + 0x00052A0UL) +#define TSB_CANAMB22_BASE (PERI_BASE + 0x00052C0UL) +#define TSB_CANAMB23_BASE (PERI_BASE + 0x00052E0UL) +#define TSB_CANAMB24_BASE (PERI_BASE + 0x0005300UL) +#define TSB_CANAMB25_BASE (PERI_BASE + 0x0005320UL) +#define TSB_CANAMB26_BASE (PERI_BASE + 0x0005340UL) +#define TSB_CANAMB27_BASE (PERI_BASE + 0x0005360UL) +#define TSB_CANAMB28_BASE (PERI_BASE + 0x0005380UL) +#define TSB_CANAMB29_BASE (PERI_BASE + 0x00053A0UL) +#define TSB_CANAMB30_BASE (PERI_BASE + 0x00053C0UL) +#define TSB_CANAMB31_BASE (PERI_BASE + 0x00053E0UL) +#define TSB_CANBMB0_BASE (PERI_BASE + 0x0006000UL) +#define TSB_CANBMB1_BASE (PERI_BASE + 0x0006020UL) +#define TSB_CANBMB2_BASE (PERI_BASE + 0x0006040UL) +#define TSB_CANBMB3_BASE (PERI_BASE + 0x0006060UL) +#define TSB_CANBMB4_BASE (PERI_BASE + 0x0006080UL) +#define TSB_CANBMB5_BASE (PERI_BASE + 0x00060A0UL) +#define TSB_CANBMB6_BASE (PERI_BASE + 0x00060C0UL) +#define TSB_CANBMB7_BASE (PERI_BASE + 0x00060E0UL) +#define TSB_CANBMB8_BASE (PERI_BASE + 0x0006100UL) +#define TSB_CANBMB9_BASE (PERI_BASE + 0x0006120UL) +#define TSB_CANBMB10_BASE (PERI_BASE + 0x0006140UL) +#define TSB_CANBMB11_BASE (PERI_BASE + 0x0006160UL) +#define TSB_CANBMB12_BASE (PERI_BASE + 0x0006180UL) +#define TSB_CANBMB13_BASE (PERI_BASE + 0x00061A0UL) +#define TSB_CANBMB14_BASE (PERI_BASE + 0x00061C0UL) +#define TSB_CANBMB15_BASE (PERI_BASE + 0x00061E0UL) +#define TSB_CANBMB16_BASE (PERI_BASE + 0x0006200UL) +#define TSB_CANBMB17_BASE (PERI_BASE + 0x0006220UL) +#define TSB_CANBMB18_BASE (PERI_BASE + 0x0006240UL) +#define TSB_CANBMB19_BASE (PERI_BASE + 0x0006260UL) +#define TSB_CANBMB20_BASE (PERI_BASE + 0x0006280UL) +#define TSB_CANBMB21_BASE (PERI_BASE + 0x00062A0UL) +#define TSB_CANBMB22_BASE (PERI_BASE + 0x00062C0UL) +#define TSB_CANBMB23_BASE (PERI_BASE + 0x00062E0UL) +#define TSB_CANBMB24_BASE (PERI_BASE + 0x0006300UL) +#define TSB_CANBMB25_BASE (PERI_BASE + 0x0006320UL) +#define TSB_CANBMB26_BASE (PERI_BASE + 0x0006340UL) +#define TSB_CANBMB27_BASE (PERI_BASE + 0x0006360UL) +#define TSB_CANBMB28_BASE (PERI_BASE + 0x0006380UL) +#define TSB_CANBMB29_BASE (PERI_BASE + 0x00063A0UL) +#define TSB_CANBMB30_BASE (PERI_BASE + 0x00063C0UL) +#define TSB_CANBMB31_BASE (PERI_BASE + 0x00063E0UL) +#define TSB_CANA_BASE (PERI_BASE + 0x0005400UL) +#define TSB_CANB_BASE (PERI_BASE + 0x0006400UL) +#define TSB_EMA_BASE (PERI_BASE + 0x000A000UL) +#define TSB_SMI0_BASE (PERI_BASE + 0x000C000UL) +#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) +#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) +#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) +#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL) +#define TSB_LTT0_BASE (PERI_BASE + 0x003FF00UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x006A000UL) +#define TSB_TSPI1_BASE (PERI_BASE + 0x006A400UL) +#define TSB_TSPI2_BASE (PERI_BASE + 0x006A800UL) +#define TSB_TSPI3_BASE (PERI_BASE + 0x006AC00UL) +#define TSB_TSPI4_BASE (PERI_BASE + 0x006B000UL) +#define TSB_TSPI5_BASE (PERI_BASE + 0x006B400UL) +#define TSB_TSPI6_BASE (PERI_BASE + 0x00CB800UL) +#define TSB_TSPI7_BASE (PERI_BASE + 0x00CBC00UL) +#define TSB_TSPI8_BASE (PERI_BASE + 0x00CC000UL) +#define TSB_EXB_BASE (PERI_BASE + 0x0076000UL) +#define TSB_CG_BASE (PERI_BASE + 0x0083000UL) +#define TSB_IB_BASE (PERI_BASE + 0x0083200UL) +#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL) +#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL) +#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL) +#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL) +#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL) +#define TSB_MDMAA_BASE (PERI_BASE + 0x00A4000UL) +#define TSB_FURT0_BASE (PERI_BASE + 0x00A8000UL) +#define TSB_FURT1_BASE (PERI_BASE + 0x00A9000UL) +#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL) +#define TSB_DA0_BASE (PERI_BASE + 0x00BC800UL) +#define TSB_DA1_BASE (PERI_BASE + 0x00BC900UL) +#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL) +#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL) +#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL) +#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL) +#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL) +#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL) +#define TSB_T32A6_BASE (PERI_BASE + 0x00C2800UL) +#define TSB_T32A7_BASE (PERI_BASE + 0x00C2C00UL) +#define TSB_T32A8_BASE (PERI_BASE + 0x00C3000UL) +#define TSB_T32A9_BASE (PERI_BASE + 0x00C3400UL) +#define TSB_T32A10_BASE (PERI_BASE + 0x00C3800UL) +#define TSB_T32A11_BASE (PERI_BASE + 0x00C3C00UL) +#define TSB_T32A12_BASE (PERI_BASE + 0x00C4000UL) +#define TSB_T32A13_BASE (PERI_BASE + 0x00C4400UL) +#define TSB_T32A14_BASE (PERI_BASE + 0x00C4800UL) +#define TSB_T32A15_BASE (PERI_BASE + 0x00C4C00UL) +#define TSB_TSSI0_BASE (PERI_BASE + 0x00CD000UL) +#define TSB_TSSI1_BASE (PERI_BASE + 0x00CD400UL) +#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL) +#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL) +#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL) +#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL) +#define TSB_UART4_BASE (PERI_BASE + 0x00CF000UL) +#define TSB_UART5_BASE (PERI_BASE + 0x00CF400UL) +#define TSB_I2S0_BASE (PERI_BASE + 0x00D0000UL) +#define TSB_I2S1_BASE (PERI_BASE + 0x00D0800UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL) +#define TSB_I2C2_BASE (PERI_BASE + 0x00D3000UL) +#define TSB_I2C3_BASE (PERI_BASE + 0x00D4000UL) +#define TSB_I2C4_BASE (PERI_BASE + 0x00D5000UL) +#define TSB_EI2C0_BASE (PERI_BASE + 0x00D8000UL) +#define TSB_EI2C1_BASE (PERI_BASE + 0x00D9000UL) +#define TSB_EI2C2_BASE (PERI_BASE + 0x00DA000UL) +#define TSB_EI2C3_BASE (PERI_BASE + 0x00DB000UL) +#define TSB_EI2C4_BASE (PERI_BASE + 0x00DC000UL) +#define TSB_FIRnore_BASE (PERI_BASE + 0x00DD000UL) +#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL) +#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL) +#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL) +#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL) +#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL) +#define TSB_PP_BASE (PERI_BASE + 0x00E0D00UL) +#define TSB_PR_BASE (PERI_BASE + 0x00E0E00UL) +#define TSB_PT_BASE (PERI_BASE + 0x00E0F00UL) +#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL) +#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL) +#define TSB_PW_BASE (PERI_BASE + 0x00E1200UL) +#define TSB_PY_BASE (PERI_BASE + 0x00E1300UL) +#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL) +#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL) +#define TSB_RTC_BASE (PERI_BASE + 0x00E4800UL) +#define TSB_CEC0_BASE (PERI_BASE + 0x00E8000UL) +#define TSB_RMC0_BASE (PERI_BASE + 0x00E8100UL) +#define TSB_RMC1_BASE (PERI_BASE + 0x00E8200UL) +#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL) +#define TSB_ISDA_BASE (PERI_BASE + 0x00F0000UL) +#define TSB_ISDB_BASE (PERI_BASE + 0x00F0100UL) +#define TSB_ISDC_BASE (PERI_BASE + 0x00F0200UL) +#define TSB_USBA_BASE (PERI_BASE + 0x0100000UL) +#define TSB_USBB_BASE (PERI_BASE + 0x0140000UL) +#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) + + +/* Peripheral declaration */ +#define TSB_DMACA (( TSB_DMAC_TypeDef *) TSB_DMACA_BASE) +#define TSB_DMACB (( TSB_DMAC_TypeDef *) TSB_DMACB_BASE) +#define TSB_CANAMB0 (( TSB_CANAMB_TypeDef *)TSB_CANAMB0_BASE) +#define TSB_CANAMB1 (( TSB_CANAMB_TypeDef *)TSB_CANAMB1_BASE) +#define TSB_CANAMB2 (( TSB_CANAMB_TypeDef *)TSB_CANAMB2_BASE) +#define TSB_CANAMB3 (( TSB_CANAMB_TypeDef *)TSB_CANAMB3_BASE) +#define TSB_CANAMB4 (( TSB_CANAMB_TypeDef *)TSB_CANAMB4_BASE) +#define TSB_CANAMB5 (( TSB_CANAMB_TypeDef *)TSB_CANAMB5_BASE) +#define TSB_CANAMB6 (( TSB_CANAMB_TypeDef *)TSB_CANAMB6_BASE) +#define TSB_CANAMB7 (( TSB_CANAMB_TypeDef *)TSB_CANAMB7_BASE) +#define TSB_CANAMB8 (( TSB_CANAMB_TypeDef *)TSB_CANAMB8_BASE) +#define TSB_CANAMB9 (( TSB_CANAMB_TypeDef *)TSB_CANAMB9_BASE) +#define TSB_CANAMB10 (( TSB_CANAMB_TypeDef *)TSB_CANAMB10_BASE) +#define TSB_CANAMB11 (( TSB_CANAMB_TypeDef *)TSB_CANAMB11_BASE) +#define TSB_CANAMB12 (( TSB_CANAMB_TypeDef *)TSB_CANAMB12_BASE) +#define TSB_CANAMB13 (( TSB_CANAMB_TypeDef *)TSB_CANAMB13_BASE) +#define TSB_CANAMB14 (( TSB_CANAMB_TypeDef *)TSB_CANAMB14_BASE) +#define TSB_CANAMB15 (( TSB_CANAMB_TypeDef *)TSB_CANAMB15_BASE) +#define TSB_CANAMB16 (( TSB_CANAMB_TypeDef *)TSB_CANAMB16_BASE) +#define TSB_CANAMB17 (( TSB_CANAMB_TypeDef *)TSB_CANAMB17_BASE) +#define TSB_CANAMB18 (( TSB_CANAMB_TypeDef *)TSB_CANAMB18_BASE) +#define TSB_CANAMB19 (( TSB_CANAMB_TypeDef *)TSB_CANAMB19_BASE) +#define TSB_CANAMB20 (( TSB_CANAMB_TypeDef *)TSB_CANAMB20_BASE) +#define TSB_CANAMB21 (( TSB_CANAMB_TypeDef *)TSB_CANAMB21_BASE) +#define TSB_CANAMB22 (( TSB_CANAMB_TypeDef *)TSB_CANAMB22_BASE) +#define TSB_CANAMB23 (( TSB_CANAMB_TypeDef *)TSB_CANAMB23_BASE) +#define TSB_CANAMB24 (( TSB_CANAMB_TypeDef *)TSB_CANAMB24_BASE) +#define TSB_CANAMB25 (( TSB_CANAMB_TypeDef *)TSB_CANAMB25_BASE) +#define TSB_CANAMB26 (( TSB_CANAMB_TypeDef *)TSB_CANAMB26_BASE) +#define TSB_CANAMB27 (( TSB_CANAMB_TypeDef *)TSB_CANAMB27_BASE) +#define TSB_CANAMB28 (( TSB_CANAMB_TypeDef *)TSB_CANAMB28_BASE) +#define TSB_CANAMB29 (( TSB_CANAMB_TypeDef *)TSB_CANAMB29_BASE) +#define TSB_CANAMB30 (( TSB_CANAMB_TypeDef *)TSB_CANAMB30_BASE) +#define TSB_CANAMB31 (( TSB_CANAMB_TypeDef *)TSB_CANAMB31_BASE) +#define TSB_CANBMB0 (( TSB_CANBMB_TypeDef *)TSB_CANBMB0_BASE) +#define TSB_CANBMB1 (( TSB_CANBMB_TypeDef *)TSB_CANBMB1_BASE) +#define TSB_CANBMB2 (( TSB_CANBMB_TypeDef *)TSB_CANBMB2_BASE) +#define TSB_CANBMB3 (( TSB_CANBMB_TypeDef *)TSB_CANBMB3_BASE) +#define TSB_CANBMB4 (( TSB_CANBMB_TypeDef *)TSB_CANBMB4_BASE) +#define TSB_CANBMB5 (( TSB_CANBMB_TypeDef *)TSB_CANBMB5_BASE) +#define TSB_CANBMB6 (( TSB_CANBMB_TypeDef *)TSB_CANBMB6_BASE) +#define TSB_CANBMB7 (( TSB_CANBMB_TypeDef *)TSB_CANBMB7_BASE) +#define TSB_CANBMB8 (( TSB_CANBMB_TypeDef *)TSB_CANBMB8_BASE) +#define TSB_CANBMB9 (( TSB_CANBMB_TypeDef *)TSB_CANBMB9_BASE) +#define TSB_CANBMB10 (( TSB_CANBMB_TypeDef *)TSB_CANBMB10_BASE) +#define TSB_CANBMB11 (( TSB_CANBMB_TypeDef *)TSB_CANBMB11_BASE) +#define TSB_CANBMB12 (( TSB_CANBMB_TypeDef *)TSB_CANBMB12_BASE) +#define TSB_CANBMB13 (( TSB_CANBMB_TypeDef *)TSB_CANBMB13_BASE) +#define TSB_CANBMB14 (( TSB_CANBMB_TypeDef *)TSB_CANBMB14_BASE) +#define TSB_CANBMB15 (( TSB_CANBMB_TypeDef *)TSB_CANBMB15_BASE) +#define TSB_CANBMB16 (( TSB_CANBMB_TypeDef *)TSB_CANBMB16_BASE) +#define TSB_CANBMB17 (( TSB_CANBMB_TypeDef *)TSB_CANBMB17_BASE) +#define TSB_CANBMB18 (( TSB_CANBMB_TypeDef *)TSB_CANBMB18_BASE) +#define TSB_CANBMB19 (( TSB_CANBMB_TypeDef *)TSB_CANBMB19_BASE) +#define TSB_CANBMB20 (( TSB_CANBMB_TypeDef *)TSB_CANBMB20_BASE) +#define TSB_CANBMB21 (( TSB_CANBMB_TypeDef *)TSB_CANBMB21_BASE) +#define TSB_CANBMB22 (( TSB_CANBMB_TypeDef *)TSB_CANBMB22_BASE) +#define TSB_CANBMB23 (( TSB_CANBMB_TypeDef *)TSB_CANBMB23_BASE) +#define TSB_CANBMB24 (( TSB_CANBMB_TypeDef *)TSB_CANBMB24_BASE) +#define TSB_CANBMB25 (( TSB_CANBMB_TypeDef *)TSB_CANBMB25_BASE) +#define TSB_CANBMB26 (( TSB_CANBMB_TypeDef *)TSB_CANBMB26_BASE) +#define TSB_CANBMB27 (( TSB_CANBMB_TypeDef *)TSB_CANBMB27_BASE) +#define TSB_CANBMB28 (( TSB_CANBMB_TypeDef *)TSB_CANBMB28_BASE) +#define TSB_CANBMB29 (( TSB_CANBMB_TypeDef *)TSB_CANBMB29_BASE) +#define TSB_CANBMB30 (( TSB_CANBMB_TypeDef *)TSB_CANBMB30_BASE) +#define TSB_CANBMB31 (( TSB_CANBMB_TypeDef *)TSB_CANBMB31_BASE) +#define TSB_CANA (( TSB_CAN_TypeDef *) TSB_CANA_BASE) +#define TSB_CANB (( TSB_CAN_TypeDef *) TSB_CANB_BASE) +#define TSB_EMA (( TSB_EM_TypeDef *) TSB_EMA_BASE) +#define TSB_SMI0 (( TSB_SMI_TypeDef *) TSB_SMI0_BASE) +#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) +#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) +#define TSB_LTT0 (( TSB_LTT_TypeDef *) TSB_LTT0_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) +#define TSB_TSPI2 (( TSB_TSPI_TypeDef *) TSB_TSPI2_BASE) +#define TSB_TSPI3 (( TSB_TSPI_TypeDef *) TSB_TSPI3_BASE) +#define TSB_TSPI4 (( TSB_TSPI_TypeDef *) TSB_TSPI4_BASE) +#define TSB_TSPI5 (( TSB_TSPI_TypeDef *) TSB_TSPI5_BASE) +#define TSB_TSPI6 (( TSB_TSPI_TypeDef *) TSB_TSPI6_BASE) +#define TSB_TSPI7 (( TSB_TSPI_TypeDef *) TSB_TSPI7_BASE) +#define TSB_TSPI8 (( TSB_TSPI_TypeDef *) TSB_TSPI8_BASE) +#define TSB_EXB (( TSB_EXB_TypeDef *) TSB_EXB_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) +#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) +#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) +#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) +#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) +#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE) +#define TSB_MDMAA (( TSB_MDMA_TypeDef *) TSB_MDMAA_BASE) +#define TSB_FURT0 (( TSB_FURT_TypeDef *) TSB_FURT0_BASE) +#define TSB_FURT1 (( TSB_FURT_TypeDef *) TSB_FURT1_BASE) +#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) +#define TSB_DA0 (( TSB_DA_TypeDef *) TSB_DA0_BASE) +#define TSB_DA1 (( TSB_DA_TypeDef *) TSB_DA1_BASE) +#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) +#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) +#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) +#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) +#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) +#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) +#define TSB_T32A6 (( TSB_T32A_TypeDef *) TSB_T32A6_BASE) +#define TSB_T32A7 (( TSB_T32A_TypeDef *) TSB_T32A7_BASE) +#define TSB_T32A8 (( TSB_T32A_TypeDef *) TSB_T32A8_BASE) +#define TSB_T32A9 (( TSB_T32A_TypeDef *) TSB_T32A9_BASE) +#define TSB_T32A10 (( TSB_T32A_TypeDef *)TSB_T32A10_BASE) +#define TSB_T32A11 (( TSB_T32A_TypeDef *)TSB_T32A11_BASE) +#define TSB_T32A12 (( TSB_T32A_TypeDef *)TSB_T32A12_BASE) +#define TSB_T32A13 (( TSB_T32A_TypeDef *)TSB_T32A13_BASE) +#define TSB_T32A14 (( TSB_T32A_TypeDef *)TSB_T32A14_BASE) +#define TSB_T32A15 (( TSB_T32A_TypeDef *)TSB_T32A15_BASE) +#define TSB_TSSI0 (( TSB_TSSI_TypeDef *) TSB_TSSI0_BASE) +#define TSB_TSSI1 (( TSB_TSSI_TypeDef *) TSB_TSSI1_BASE) +#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) +#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) +#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) +#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) +#define TSB_UART4 (( TSB_UART_TypeDef *) TSB_UART4_BASE) +#define TSB_UART5 (( TSB_UART_TypeDef *) TSB_UART5_BASE) +#define TSB_I2S0 (( TSB_I2S_TypeDef *) TSB_I2S0_BASE) +#define TSB_I2S1 (( TSB_I2S_TypeDef *) TSB_I2S1_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_I2C2 (( TSB_I2C_TypeDef *) TSB_I2C2_BASE) +#define TSB_I2C3 (( TSB_I2C_TypeDef *) TSB_I2C3_BASE) +#define TSB_I2C4 (( TSB_I2C_TypeDef *) TSB_I2C4_BASE) +#define TSB_EI2C0 (( TSB_EI2C_TypeDef *) TSB_EI2C0_BASE) +#define TSB_EI2C1 (( TSB_EI2C_TypeDef *) TSB_EI2C1_BASE) +#define TSB_EI2C2 (( TSB_EI2C_TypeDef *) TSB_EI2C2_BASE) +#define TSB_EI2C3 (( TSB_EI2C_TypeDef *) TSB_EI2C3_BASE) +#define TSB_EI2C4 (( TSB_EI2C_TypeDef *) TSB_EI2C4_BASE) +#define TSB_FIRnore (( TSB_FIR_TypeDef *)TSB_FIRnore_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) +#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) +#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) +#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) +#define TSB_PP (( TSB_PP_TypeDef *) TSB_PP_BASE) +#define TSB_PR (( TSB_PR_TypeDef *) TSB_PR_BASE) +#define TSB_PT (( TSB_PT_TypeDef *) TSB_PT_BASE) +#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) +#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) +#define TSB_PW (( TSB_PW_TypeDef *) TSB_PW_BASE) +#define TSB_PY (( TSB_PY_TypeDef *) TSB_PY_BASE) +#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) +#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) +#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE) +#define TSB_CEC0 (( TSB_CEC_TypeDef *) TSB_CEC0_BASE) +#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE) +#define TSB_RMC1 (( TSB_RMC_TypeDef *) TSB_RMC1_BASE) +#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) +#define TSB_ISDA (( TSB_ISD_TypeDef *) TSB_ISDA_BASE) +#define TSB_ISDB (( TSB_ISD_TypeDef *) TSB_ISDB_BASE) +#define TSB_ISDC (( TSB_ISD_TypeDef *) TSB_ISDC_BASE) +#define TSB_USBA (( TSB_USB_TypeDef *) TSB_USBA_BASE) +#define TSB_USBB (( TSB_USB_TypeDef *) TSB_USBB_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + +/* DMA Controller */ +#define TSB_DMACA_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,0))) +#define TSB_DMACA_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTSTATUS,1))) +#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,0))) +#define TSB_DMACA_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTTCSTATUS,1))) +#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,0))) +#define TSB_DMACA_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->INTERRORSTATUS,1))) +#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,0))) +#define TSB_DMACA_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTTCSTATUS,1))) +#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,0))) +#define TSB_DMACA_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->RAWINTERRORSTATUS,1))) +#define TSB_DMACA_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,0))) +#define TSB_DMACA_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->ENBLDCHNS,1))) +#define TSB_DMACA_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->CONFIGURATION,0))) +#define TSB_DMACA_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,26))) +#define TSB_DMACA_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,27))) +#define TSB_DMACA_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONTROL,31))) +#define TSB_DMACA_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,0))) +#define TSB_DMACA_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,14))) +#define TSB_DMACA_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,15))) +#define TSB_DMACA_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,16))) +#define TSB_DMACA_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,17))) +#define TSB_DMACA_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C0CONFIGURATION,18))) +#define TSB_DMACA_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,26))) +#define TSB_DMACA_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,27))) +#define TSB_DMACA_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONTROL,31))) +#define TSB_DMACA_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,0))) +#define TSB_DMACA_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,14))) +#define TSB_DMACA_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,15))) +#define TSB_DMACA_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,16))) +#define TSB_DMACA_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,17))) +#define TSB_DMACA_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACA->C1CONFIGURATION,18))) + +#define TSB_DMACB_INTSTATUS_INTSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,0))) +#define TSB_DMACB_INTSTATUS_INTSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTSTATUS,1))) +#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,0))) +#define TSB_DMACB_INTTCSTATUS_INTTCSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTTCSTATUS,1))) +#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,0))) +#define TSB_DMACB_INTERRORSTATUS_INTERRSTATUS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->INTERRORSTATUS,1))) +#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,0))) +#define TSB_DMACB_RAWINTTCSTATUS_RAWINTTCS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTTCSTATUS,1))) +#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,0))) +#define TSB_DMACB_RAWINTERRORSTATUS_RAWINTERRS1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->RAWINTERRORSTATUS,1))) +#define TSB_DMACB_ENBLDCHNS_ENABLEDCH0 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,0))) +#define TSB_DMACB_ENBLDCHNS_ENABLEDCH1 (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->ENBLDCHNS,1))) +#define TSB_DMACB_CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->CONFIGURATION,0))) +#define TSB_DMACB_C0CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,26))) +#define TSB_DMACB_C0CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,27))) +#define TSB_DMACB_C0CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONTROL,31))) +#define TSB_DMACB_C0CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,0))) +#define TSB_DMACB_C0CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,14))) +#define TSB_DMACB_C0CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,15))) +#define TSB_DMACB_C0CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,16))) +#define TSB_DMACB_C0CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,17))) +#define TSB_DMACB_C0CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C0CONFIGURATION,18))) +#define TSB_DMACB_C1CONTROL_SI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,26))) +#define TSB_DMACB_C1CONTROL_DI (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,27))) +#define TSB_DMACB_C1CONTROL_I (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONTROL,31))) +#define TSB_DMACB_C1CONFIGURATION_E (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,0))) +#define TSB_DMACB_C1CONFIGURATION_IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,14))) +#define TSB_DMACB_C1CONFIGURATION_ITC (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,15))) +#define TSB_DMACB_C1CONFIGURATION_LOCK (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,16))) +#define TSB_DMACB_C1CONFIGURATION_ACTIVE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,17))) +#define TSB_DMACB_C1CONFIGURATION_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMACB->C1CONFIGURATION,18))) + + +/* CAN Controller Mailbox RAM (CANMB) */ +#define TSB_CANAMB0_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB0->ID,29))) +#define TSB_CANAMB0_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB0->ID,30))) +#define TSB_CANAMB0_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB0->ID,31))) +#define TSB_CANAMB0_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB0->TSVMCF,4))) + +#define TSB_CANAMB1_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB1->ID,29))) +#define TSB_CANAMB1_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB1->ID,30))) +#define TSB_CANAMB1_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB1->ID,31))) +#define TSB_CANAMB1_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB1->TSVMCF,4))) + +#define TSB_CANAMB2_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB2->ID,29))) +#define TSB_CANAMB2_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB2->ID,30))) +#define TSB_CANAMB2_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB2->ID,31))) +#define TSB_CANAMB2_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB2->TSVMCF,4))) + +#define TSB_CANAMB3_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB3->ID,29))) +#define TSB_CANAMB3_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB3->ID,30))) +#define TSB_CANAMB3_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB3->ID,31))) +#define TSB_CANAMB3_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB3->TSVMCF,4))) + +#define TSB_CANAMB4_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB4->ID,29))) +#define TSB_CANAMB4_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB4->ID,30))) +#define TSB_CANAMB4_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB4->ID,31))) +#define TSB_CANAMB4_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB4->TSVMCF,4))) + +#define TSB_CANAMB5_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB5->ID,29))) +#define TSB_CANAMB5_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB5->ID,30))) +#define TSB_CANAMB5_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB5->ID,31))) +#define TSB_CANAMB5_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB5->TSVMCF,4))) + +#define TSB_CANAMB6_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB6->ID,29))) +#define TSB_CANAMB6_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB6->ID,30))) +#define TSB_CANAMB6_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB6->ID,31))) +#define TSB_CANAMB6_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB6->TSVMCF,4))) + +#define TSB_CANAMB7_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB7->ID,29))) +#define TSB_CANAMB7_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB7->ID,30))) +#define TSB_CANAMB7_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB7->ID,31))) +#define TSB_CANAMB7_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB7->TSVMCF,4))) + +#define TSB_CANAMB8_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB8->ID,29))) +#define TSB_CANAMB8_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB8->ID,30))) +#define TSB_CANAMB8_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB8->ID,31))) +#define TSB_CANAMB8_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB8->TSVMCF,4))) + +#define TSB_CANAMB9_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB9->ID,29))) +#define TSB_CANAMB9_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB9->ID,30))) +#define TSB_CANAMB9_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB9->ID,31))) +#define TSB_CANAMB9_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB9->TSVMCF,4))) + +#define TSB_CANAMB10_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB10->ID,29))) +#define TSB_CANAMB10_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB10->ID,30))) +#define TSB_CANAMB10_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB10->ID,31))) +#define TSB_CANAMB10_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB10->TSVMCF,4))) + +#define TSB_CANAMB11_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB11->ID,29))) +#define TSB_CANAMB11_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB11->ID,30))) +#define TSB_CANAMB11_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB11->ID,31))) +#define TSB_CANAMB11_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB11->TSVMCF,4))) + +#define TSB_CANAMB12_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB12->ID,29))) +#define TSB_CANAMB12_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB12->ID,30))) +#define TSB_CANAMB12_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB12->ID,31))) +#define TSB_CANAMB12_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB12->TSVMCF,4))) + +#define TSB_CANAMB13_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB13->ID,29))) +#define TSB_CANAMB13_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB13->ID,30))) +#define TSB_CANAMB13_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB13->ID,31))) +#define TSB_CANAMB13_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB13->TSVMCF,4))) + +#define TSB_CANAMB14_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB14->ID,29))) +#define TSB_CANAMB14_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB14->ID,30))) +#define TSB_CANAMB14_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB14->ID,31))) +#define TSB_CANAMB14_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB14->TSVMCF,4))) + +#define TSB_CANAMB15_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB15->ID,29))) +#define TSB_CANAMB15_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB15->ID,30))) +#define TSB_CANAMB15_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB15->ID,31))) +#define TSB_CANAMB15_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB15->TSVMCF,4))) + +#define TSB_CANAMB16_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB16->ID,29))) +#define TSB_CANAMB16_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB16->ID,30))) +#define TSB_CANAMB16_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB16->ID,31))) +#define TSB_CANAMB16_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB16->TSVMCF,4))) + +#define TSB_CANAMB17_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB17->ID,29))) +#define TSB_CANAMB17_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB17->ID,30))) +#define TSB_CANAMB17_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB17->ID,31))) +#define TSB_CANAMB17_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB17->TSVMCF,4))) + +#define TSB_CANAMB18_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB18->ID,29))) +#define TSB_CANAMB18_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB18->ID,30))) +#define TSB_CANAMB18_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB18->ID,31))) +#define TSB_CANAMB18_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB18->TSVMCF,4))) + +#define TSB_CANAMB19_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB19->ID,29))) +#define TSB_CANAMB19_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB19->ID,30))) +#define TSB_CANAMB19_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB19->ID,31))) +#define TSB_CANAMB19_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB19->TSVMCF,4))) + +#define TSB_CANAMB20_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB20->ID,29))) +#define TSB_CANAMB20_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB20->ID,30))) +#define TSB_CANAMB20_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB20->ID,31))) +#define TSB_CANAMB20_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB20->TSVMCF,4))) + +#define TSB_CANAMB21_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB21->ID,29))) +#define TSB_CANAMB21_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB21->ID,30))) +#define TSB_CANAMB21_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB21->ID,31))) +#define TSB_CANAMB21_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB21->TSVMCF,4))) + +#define TSB_CANAMB22_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB22->ID,29))) +#define TSB_CANAMB22_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB22->ID,30))) +#define TSB_CANAMB22_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB22->ID,31))) +#define TSB_CANAMB22_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB22->TSVMCF,4))) + +#define TSB_CANAMB23_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB23->ID,29))) +#define TSB_CANAMB23_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB23->ID,30))) +#define TSB_CANAMB23_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB23->ID,31))) +#define TSB_CANAMB23_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB23->TSVMCF,4))) + +#define TSB_CANAMB24_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB24->ID,29))) +#define TSB_CANAMB24_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB24->ID,30))) +#define TSB_CANAMB24_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB24->ID,31))) +#define TSB_CANAMB24_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB24->TSVMCF,4))) + +#define TSB_CANAMB25_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB25->ID,29))) +#define TSB_CANAMB25_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB25->ID,30))) +#define TSB_CANAMB25_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB25->ID,31))) +#define TSB_CANAMB25_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB25->TSVMCF,4))) + +#define TSB_CANAMB26_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB26->ID,29))) +#define TSB_CANAMB26_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB26->ID,30))) +#define TSB_CANAMB26_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB26->ID,31))) +#define TSB_CANAMB26_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB26->TSVMCF,4))) + +#define TSB_CANAMB27_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB27->ID,29))) +#define TSB_CANAMB27_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB27->ID,30))) +#define TSB_CANAMB27_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB27->ID,31))) +#define TSB_CANAMB27_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB27->TSVMCF,4))) + +#define TSB_CANAMB28_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB28->ID,29))) +#define TSB_CANAMB28_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB28->ID,30))) +#define TSB_CANAMB28_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB28->ID,31))) +#define TSB_CANAMB28_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB28->TSVMCF,4))) + +#define TSB_CANAMB29_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB29->ID,29))) +#define TSB_CANAMB29_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB29->ID,30))) +#define TSB_CANAMB29_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB29->ID,31))) +#define TSB_CANAMB29_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB29->TSVMCF,4))) + +#define TSB_CANAMB30_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB30->ID,29))) +#define TSB_CANAMB30_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB30->ID,30))) +#define TSB_CANAMB30_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB30->ID,31))) +#define TSB_CANAMB30_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB30->TSVMCF,4))) + +#define TSB_CANAMB31_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB31->ID,29))) +#define TSB_CANAMB31_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB31->ID,30))) +#define TSB_CANAMB31_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB31->ID,31))) +#define TSB_CANAMB31_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANAMB31->TSVMCF,4))) + + +/* CAN Controller Mailbox RAM (CANMB) */ +#define TSB_CANBMB0_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB0->ID,29))) +#define TSB_CANBMB0_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB0->ID,30))) +#define TSB_CANBMB0_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB0->ID,31))) +#define TSB_CANBMB0_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB0->TSVMCF,4))) + +#define TSB_CANBMB1_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB1->ID,29))) +#define TSB_CANBMB1_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB1->ID,30))) +#define TSB_CANBMB1_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB1->ID,31))) +#define TSB_CANBMB1_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB1->TSVMCF,4))) + +#define TSB_CANBMB2_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB2->ID,29))) +#define TSB_CANBMB2_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB2->ID,30))) +#define TSB_CANBMB2_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB2->ID,31))) +#define TSB_CANBMB2_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB2->TSVMCF,4))) + +#define TSB_CANBMB3_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB3->ID,29))) +#define TSB_CANBMB3_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB3->ID,30))) +#define TSB_CANBMB3_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB3->ID,31))) +#define TSB_CANBMB3_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB3->TSVMCF,4))) + +#define TSB_CANBMB4_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB4->ID,29))) +#define TSB_CANBMB4_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB4->ID,30))) +#define TSB_CANBMB4_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB4->ID,31))) +#define TSB_CANBMB4_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB4->TSVMCF,4))) + +#define TSB_CANBMB5_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB5->ID,29))) +#define TSB_CANBMB5_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB5->ID,30))) +#define TSB_CANBMB5_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB5->ID,31))) +#define TSB_CANBMB5_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB5->TSVMCF,4))) + +#define TSB_CANBMB6_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB6->ID,29))) +#define TSB_CANBMB6_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB6->ID,30))) +#define TSB_CANBMB6_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB6->ID,31))) +#define TSB_CANBMB6_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB6->TSVMCF,4))) + +#define TSB_CANBMB7_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB7->ID,29))) +#define TSB_CANBMB7_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB7->ID,30))) +#define TSB_CANBMB7_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB7->ID,31))) +#define TSB_CANBMB7_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB7->TSVMCF,4))) + +#define TSB_CANBMB8_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB8->ID,29))) +#define TSB_CANBMB8_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB8->ID,30))) +#define TSB_CANBMB8_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB8->ID,31))) +#define TSB_CANBMB8_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB8->TSVMCF,4))) + +#define TSB_CANBMB9_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB9->ID,29))) +#define TSB_CANBMB9_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB9->ID,30))) +#define TSB_CANBMB9_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB9->ID,31))) +#define TSB_CANBMB9_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB9->TSVMCF,4))) + +#define TSB_CANBMB10_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB10->ID,29))) +#define TSB_CANBMB10_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB10->ID,30))) +#define TSB_CANBMB10_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB10->ID,31))) +#define TSB_CANBMB10_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB10->TSVMCF,4))) + +#define TSB_CANBMB11_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB11->ID,29))) +#define TSB_CANBMB11_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB11->ID,30))) +#define TSB_CANBMB11_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB11->ID,31))) +#define TSB_CANBMB11_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB11->TSVMCF,4))) + +#define TSB_CANBMB12_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB12->ID,29))) +#define TSB_CANBMB12_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB12->ID,30))) +#define TSB_CANBMB12_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB12->ID,31))) +#define TSB_CANBMB12_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB12->TSVMCF,4))) + +#define TSB_CANBMB13_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB13->ID,29))) +#define TSB_CANBMB13_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB13->ID,30))) +#define TSB_CANBMB13_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB13->ID,31))) +#define TSB_CANBMB13_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB13->TSVMCF,4))) + +#define TSB_CANBMB14_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB14->ID,29))) +#define TSB_CANBMB14_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB14->ID,30))) +#define TSB_CANBMB14_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB14->ID,31))) +#define TSB_CANBMB14_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB14->TSVMCF,4))) + +#define TSB_CANBMB15_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB15->ID,29))) +#define TSB_CANBMB15_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB15->ID,30))) +#define TSB_CANBMB15_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB15->ID,31))) +#define TSB_CANBMB15_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB15->TSVMCF,4))) + +#define TSB_CANBMB16_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB16->ID,29))) +#define TSB_CANBMB16_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB16->ID,30))) +#define TSB_CANBMB16_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB16->ID,31))) +#define TSB_CANBMB16_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB16->TSVMCF,4))) + +#define TSB_CANBMB17_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB17->ID,29))) +#define TSB_CANBMB17_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB17->ID,30))) +#define TSB_CANBMB17_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB17->ID,31))) +#define TSB_CANBMB17_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB17->TSVMCF,4))) + +#define TSB_CANBMB18_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB18->ID,29))) +#define TSB_CANBMB18_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB18->ID,30))) +#define TSB_CANBMB18_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB18->ID,31))) +#define TSB_CANBMB18_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB18->TSVMCF,4))) + +#define TSB_CANBMB19_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB19->ID,29))) +#define TSB_CANBMB19_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB19->ID,30))) +#define TSB_CANBMB19_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB19->ID,31))) +#define TSB_CANBMB19_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB19->TSVMCF,4))) + +#define TSB_CANBMB20_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB20->ID,29))) +#define TSB_CANBMB20_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB20->ID,30))) +#define TSB_CANBMB20_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB20->ID,31))) +#define TSB_CANBMB20_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB20->TSVMCF,4))) + +#define TSB_CANBMB21_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB21->ID,29))) +#define TSB_CANBMB21_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB21->ID,30))) +#define TSB_CANBMB21_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB21->ID,31))) +#define TSB_CANBMB21_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB21->TSVMCF,4))) + +#define TSB_CANBMB22_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB22->ID,29))) +#define TSB_CANBMB22_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB22->ID,30))) +#define TSB_CANBMB22_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB22->ID,31))) +#define TSB_CANBMB22_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB22->TSVMCF,4))) + +#define TSB_CANBMB23_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB23->ID,29))) +#define TSB_CANBMB23_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB23->ID,30))) +#define TSB_CANBMB23_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB23->ID,31))) +#define TSB_CANBMB23_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB23->TSVMCF,4))) + +#define TSB_CANBMB24_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB24->ID,29))) +#define TSB_CANBMB24_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB24->ID,30))) +#define TSB_CANBMB24_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB24->ID,31))) +#define TSB_CANBMB24_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB24->TSVMCF,4))) + +#define TSB_CANBMB25_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB25->ID,29))) +#define TSB_CANBMB25_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB25->ID,30))) +#define TSB_CANBMB25_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB25->ID,31))) +#define TSB_CANBMB25_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB25->TSVMCF,4))) + +#define TSB_CANBMB26_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB26->ID,29))) +#define TSB_CANBMB26_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB26->ID,30))) +#define TSB_CANBMB26_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB26->ID,31))) +#define TSB_CANBMB26_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB26->TSVMCF,4))) + +#define TSB_CANBMB27_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB27->ID,29))) +#define TSB_CANBMB27_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB27->ID,30))) +#define TSB_CANBMB27_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB27->ID,31))) +#define TSB_CANBMB27_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB27->TSVMCF,4))) + +#define TSB_CANBMB28_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB28->ID,29))) +#define TSB_CANBMB28_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB28->ID,30))) +#define TSB_CANBMB28_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB28->ID,31))) +#define TSB_CANBMB28_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB28->TSVMCF,4))) + +#define TSB_CANBMB29_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB29->ID,29))) +#define TSB_CANBMB29_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB29->ID,30))) +#define TSB_CANBMB29_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB29->ID,31))) +#define TSB_CANBMB29_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB29->TSVMCF,4))) + +#define TSB_CANBMB30_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB30->ID,29))) +#define TSB_CANBMB30_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB30->ID,30))) +#define TSB_CANBMB30_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB30->ID,31))) +#define TSB_CANBMB30_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB30->TSVMCF,4))) + +#define TSB_CANBMB31_ID_RFH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB31->ID,29))) +#define TSB_CANBMB31_ID_GAME_LAME (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB31->ID,30))) +#define TSB_CANBMB31_ID_IDE (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB31->ID,31))) +#define TSB_CANBMB31_TSVMCF_RTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANBMB31->TSVMCF,4))) + + +/* CAN Controller (CAN) */ +#define TSB_CANA_MC_MC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,0))) +#define TSB_CANA_MC_MC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,1))) +#define TSB_CANA_MC_MC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,2))) +#define TSB_CANA_MC_MC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,3))) +#define TSB_CANA_MC_MC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,4))) +#define TSB_CANA_MC_MC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,5))) +#define TSB_CANA_MC_MC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,6))) +#define TSB_CANA_MC_MC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,7))) +#define TSB_CANA_MC_MC8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,8))) +#define TSB_CANA_MC_MC9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,9))) +#define TSB_CANA_MC_MC10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,10))) +#define TSB_CANA_MC_MC11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,11))) +#define TSB_CANA_MC_MC12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,12))) +#define TSB_CANA_MC_MC13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,13))) +#define TSB_CANA_MC_MC14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,14))) +#define TSB_CANA_MC_MC15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,15))) +#define TSB_CANA_MC_MC16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,16))) +#define TSB_CANA_MC_MC17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,17))) +#define TSB_CANA_MC_MC18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,18))) +#define TSB_CANA_MC_MC19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,19))) +#define TSB_CANA_MC_MC20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,20))) +#define TSB_CANA_MC_MC21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,21))) +#define TSB_CANA_MC_MC22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,22))) +#define TSB_CANA_MC_MC23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,23))) +#define TSB_CANA_MC_MC24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,24))) +#define TSB_CANA_MC_MC25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,25))) +#define TSB_CANA_MC_MC26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,26))) +#define TSB_CANA_MC_MC27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,27))) +#define TSB_CANA_MC_MC28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,28))) +#define TSB_CANA_MC_MC29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,29))) +#define TSB_CANA_MC_MC30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,30))) +#define TSB_CANA_MC_MC31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MC,31))) +#define TSB_CANA_MD_MD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,0))) +#define TSB_CANA_MD_MD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,1))) +#define TSB_CANA_MD_MD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,2))) +#define TSB_CANA_MD_MD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,3))) +#define TSB_CANA_MD_MD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,4))) +#define TSB_CANA_MD_MD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,5))) +#define TSB_CANA_MD_MD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,6))) +#define TSB_CANA_MD_MD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,7))) +#define TSB_CANA_MD_MD8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,8))) +#define TSB_CANA_MD_MD9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,9))) +#define TSB_CANA_MD_MD10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,10))) +#define TSB_CANA_MD_MD11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,11))) +#define TSB_CANA_MD_MD12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,12))) +#define TSB_CANA_MD_MD13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,13))) +#define TSB_CANA_MD_MD14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,14))) +#define TSB_CANA_MD_MD15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,15))) +#define TSB_CANA_MD_MD16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,16))) +#define TSB_CANA_MD_MD17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,17))) +#define TSB_CANA_MD_MD18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,18))) +#define TSB_CANA_MD_MD19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,19))) +#define TSB_CANA_MD_MD20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,20))) +#define TSB_CANA_MD_MD21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,21))) +#define TSB_CANA_MD_MD22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,22))) +#define TSB_CANA_MD_MD23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,23))) +#define TSB_CANA_MD_MD24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,24))) +#define TSB_CANA_MD_MD25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,25))) +#define TSB_CANA_MD_MD26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,26))) +#define TSB_CANA_MD_MD27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,27))) +#define TSB_CANA_MD_MD28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,28))) +#define TSB_CANA_MD_MD29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,29))) +#define TSB_CANA_MD_MD30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MD,30))) +#define TSB_CANA_MD_MD31 (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->MD,31))) +#define TSB_CANA_TRS_TRS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,0))) +#define TSB_CANA_TRS_TRS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,1))) +#define TSB_CANA_TRS_TRS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,2))) +#define TSB_CANA_TRS_TRS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,3))) +#define TSB_CANA_TRS_TRS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,4))) +#define TSB_CANA_TRS_TRS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,5))) +#define TSB_CANA_TRS_TRS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,6))) +#define TSB_CANA_TRS_TRS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,7))) +#define TSB_CANA_TRS_TRS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,8))) +#define TSB_CANA_TRS_TRS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,9))) +#define TSB_CANA_TRS_TRS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,10))) +#define TSB_CANA_TRS_TRS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,11))) +#define TSB_CANA_TRS_TRS12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,12))) +#define TSB_CANA_TRS_TRS13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,13))) +#define TSB_CANA_TRS_TRS14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,14))) +#define TSB_CANA_TRS_TRS15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,15))) +#define TSB_CANA_TRS_TRS16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,16))) +#define TSB_CANA_TRS_TRS17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,17))) +#define TSB_CANA_TRS_TRS18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,18))) +#define TSB_CANA_TRS_TRS19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,19))) +#define TSB_CANA_TRS_TRS20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,20))) +#define TSB_CANA_TRS_TRS21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,21))) +#define TSB_CANA_TRS_TRS22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,22))) +#define TSB_CANA_TRS_TRS23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,23))) +#define TSB_CANA_TRS_TRS24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,24))) +#define TSB_CANA_TRS_TRS25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,25))) +#define TSB_CANA_TRS_TRS26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,26))) +#define TSB_CANA_TRS_TRS27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,27))) +#define TSB_CANA_TRS_TRS28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,28))) +#define TSB_CANA_TRS_TRS29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,29))) +#define TSB_CANA_TRS_TRS30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRS,30))) +#define TSB_CANA_TRR_TRR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,0))) +#define TSB_CANA_TRR_TRR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,1))) +#define TSB_CANA_TRR_TRR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,2))) +#define TSB_CANA_TRR_TRR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,3))) +#define TSB_CANA_TRR_TRR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,4))) +#define TSB_CANA_TRR_TRR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,5))) +#define TSB_CANA_TRR_TRR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,6))) +#define TSB_CANA_TRR_TRR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,7))) +#define TSB_CANA_TRR_TRR8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,8))) +#define TSB_CANA_TRR_TRR9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,9))) +#define TSB_CANA_TRR_TRR10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,10))) +#define TSB_CANA_TRR_TRR11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,11))) +#define TSB_CANA_TRR_TRR12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,12))) +#define TSB_CANA_TRR_TRR13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,13))) +#define TSB_CANA_TRR_TRR14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,14))) +#define TSB_CANA_TRR_TRR15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,15))) +#define TSB_CANA_TRR_TRR16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,16))) +#define TSB_CANA_TRR_TRR17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,17))) +#define TSB_CANA_TRR_TRR18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,18))) +#define TSB_CANA_TRR_TRR19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,19))) +#define TSB_CANA_TRR_TRR20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,20))) +#define TSB_CANA_TRR_TRR21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,21))) +#define TSB_CANA_TRR_TRR22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,22))) +#define TSB_CANA_TRR_TRR23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,23))) +#define TSB_CANA_TRR_TRR24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,24))) +#define TSB_CANA_TRR_TRR25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,25))) +#define TSB_CANA_TRR_TRR26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,26))) +#define TSB_CANA_TRR_TRR27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,27))) +#define TSB_CANA_TRR_TRR28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,28))) +#define TSB_CANA_TRR_TRR29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,29))) +#define TSB_CANA_TRR_TRR30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TRR,30))) +#define TSB_CANA_TA_TA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,0))) +#define TSB_CANA_TA_TA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,1))) +#define TSB_CANA_TA_TA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,2))) +#define TSB_CANA_TA_TA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,3))) +#define TSB_CANA_TA_TA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,4))) +#define TSB_CANA_TA_TA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,5))) +#define TSB_CANA_TA_TA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,6))) +#define TSB_CANA_TA_TA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,7))) +#define TSB_CANA_TA_TA8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,8))) +#define TSB_CANA_TA_TA9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,9))) +#define TSB_CANA_TA_TA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,10))) +#define TSB_CANA_TA_TA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,11))) +#define TSB_CANA_TA_TA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,12))) +#define TSB_CANA_TA_TA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,13))) +#define TSB_CANA_TA_TA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,14))) +#define TSB_CANA_TA_TA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,15))) +#define TSB_CANA_TA_TA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,16))) +#define TSB_CANA_TA_TA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,17))) +#define TSB_CANA_TA_TA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,18))) +#define TSB_CANA_TA_TA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,19))) +#define TSB_CANA_TA_TA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,20))) +#define TSB_CANA_TA_TA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,21))) +#define TSB_CANA_TA_TA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,22))) +#define TSB_CANA_TA_TA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,23))) +#define TSB_CANA_TA_TA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,24))) +#define TSB_CANA_TA_TA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,25))) +#define TSB_CANA_TA_TA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,26))) +#define TSB_CANA_TA_TA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,27))) +#define TSB_CANA_TA_TA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,28))) +#define TSB_CANA_TA_TA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,29))) +#define TSB_CANA_TA_TA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->TA,30))) +#define TSB_CANA_AA_AA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,0))) +#define TSB_CANA_AA_AA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,1))) +#define TSB_CANA_AA_AA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,2))) +#define TSB_CANA_AA_AA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,3))) +#define TSB_CANA_AA_AA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,4))) +#define TSB_CANA_AA_AA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,5))) +#define TSB_CANA_AA_AA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,6))) +#define TSB_CANA_AA_AA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,7))) +#define TSB_CANA_AA_AA8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,8))) +#define TSB_CANA_AA_AA9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,9))) +#define TSB_CANA_AA_AA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,10))) +#define TSB_CANA_AA_AA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,11))) +#define TSB_CANA_AA_AA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,12))) +#define TSB_CANA_AA_AA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,13))) +#define TSB_CANA_AA_AA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,14))) +#define TSB_CANA_AA_AA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,15))) +#define TSB_CANA_AA_AA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,16))) +#define TSB_CANA_AA_AA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,17))) +#define TSB_CANA_AA_AA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,18))) +#define TSB_CANA_AA_AA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,19))) +#define TSB_CANA_AA_AA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,20))) +#define TSB_CANA_AA_AA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,21))) +#define TSB_CANA_AA_AA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,22))) +#define TSB_CANA_AA_AA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,23))) +#define TSB_CANA_AA_AA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,24))) +#define TSB_CANA_AA_AA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,25))) +#define TSB_CANA_AA_AA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,26))) +#define TSB_CANA_AA_AA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,27))) +#define TSB_CANA_AA_AA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,28))) +#define TSB_CANA_AA_AA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,29))) +#define TSB_CANA_AA_AA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->AA,30))) +#define TSB_CANA_RMP_RMP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,0))) +#define TSB_CANA_RMP_RMP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,1))) +#define TSB_CANA_RMP_RMP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,2))) +#define TSB_CANA_RMP_RMP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,3))) +#define TSB_CANA_RMP_RMP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,4))) +#define TSB_CANA_RMP_RMP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,5))) +#define TSB_CANA_RMP_RMP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,6))) +#define TSB_CANA_RMP_RMP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,7))) +#define TSB_CANA_RMP_RMP8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,8))) +#define TSB_CANA_RMP_RMP9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,9))) +#define TSB_CANA_RMP_RMP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,10))) +#define TSB_CANA_RMP_RMP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,11))) +#define TSB_CANA_RMP_RMP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,12))) +#define TSB_CANA_RMP_RMP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,13))) +#define TSB_CANA_RMP_RMP14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,14))) +#define TSB_CANA_RMP_RMP15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,15))) +#define TSB_CANA_RMP_RMP16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,16))) +#define TSB_CANA_RMP_RMP17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,17))) +#define TSB_CANA_RMP_RMP18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,18))) +#define TSB_CANA_RMP_RMP19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,19))) +#define TSB_CANA_RMP_RMP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,20))) +#define TSB_CANA_RMP_RMP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,21))) +#define TSB_CANA_RMP_RMP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,22))) +#define TSB_CANA_RMP_RMP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,23))) +#define TSB_CANA_RMP_RMP24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,24))) +#define TSB_CANA_RMP_RMP25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,25))) +#define TSB_CANA_RMP_RMP26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,26))) +#define TSB_CANA_RMP_RMP27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,27))) +#define TSB_CANA_RMP_RMP28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,28))) +#define TSB_CANA_RMP_RMP29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,29))) +#define TSB_CANA_RMP_RMP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,30))) +#define TSB_CANA_RMP_RMP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RMP,31))) +#define TSB_CANA_RML_RML0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,0))) +#define TSB_CANA_RML_RML1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,1))) +#define TSB_CANA_RML_RML2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,2))) +#define TSB_CANA_RML_RML3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,3))) +#define TSB_CANA_RML_RML4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,4))) +#define TSB_CANA_RML_RML5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,5))) +#define TSB_CANA_RML_RML6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,6))) +#define TSB_CANA_RML_RML7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,7))) +#define TSB_CANA_RML_RML8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,8))) +#define TSB_CANA_RML_RML9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,9))) +#define TSB_CANA_RML_RML10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,10))) +#define TSB_CANA_RML_RML11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,11))) +#define TSB_CANA_RML_RML12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,12))) +#define TSB_CANA_RML_RML13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,13))) +#define TSB_CANA_RML_RML14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,14))) +#define TSB_CANA_RML_RML15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,15))) +#define TSB_CANA_RML_RML16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,16))) +#define TSB_CANA_RML_RML17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,17))) +#define TSB_CANA_RML_RML18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,18))) +#define TSB_CANA_RML_RML19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,19))) +#define TSB_CANA_RML_RML20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,20))) +#define TSB_CANA_RML_RML21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,21))) +#define TSB_CANA_RML_RML22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,22))) +#define TSB_CANA_RML_RML23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,23))) +#define TSB_CANA_RML_RML24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,24))) +#define TSB_CANA_RML_RML25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,25))) +#define TSB_CANA_RML_RML26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,26))) +#define TSB_CANA_RML_RML27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,27))) +#define TSB_CANA_RML_RML28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,28))) +#define TSB_CANA_RML_RML29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,29))) +#define TSB_CANA_RML_RML30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,30))) +#define TSB_CANA_RML_RML31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RML,31))) +#define TSB_CANA_LAM_LAMI (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->LAM,31))) +#define TSB_CANA_GAM_GAMI (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GAM,31))) +#define TSB_CANA_MCR_SRES (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,0))) +#define TSB_CANA_MCR_TSCC (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,1))) +#define TSB_CANA_MCR_MTOS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,3))) +#define TSB_CANA_MCR_WUBA (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,4))) +#define TSB_CANA_MCR_SMR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,6))) +#define TSB_CANA_MCR_CCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,7))) +#define TSB_CANA_MCR_TSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,8))) +#define TSB_CANA_MCR_TSTLB (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,9))) +#define TSB_CANA_MCR_SUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MCR,11))) +#define TSB_CANA_GSR_EW (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,0))) +#define TSB_CANA_GSR_EP (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,1))) +#define TSB_CANA_GSR_BO (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,2))) +#define TSB_CANA_GSR_TSO (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,3))) +#define TSB_CANA_GSR_SMA (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,6))) +#define TSB_CANA_GSR_CCE (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,7))) +#define TSB_CANA_GSR_SUA (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,8))) +#define TSB_CANA_GSR_TM (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,10))) +#define TSB_CANA_GSR_RM (*((__I uint32_t *)BITBAND_PERI(&TSB_CANA->GSR,11))) +#define TSB_CANA_BCR2_SAM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->BCR2,7))) +#define TSB_CANA_GIF_WLIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,0))) +#define TSB_CANA_GIF_EPIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,1))) +#define TSB_CANA_GIF_BOIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,2))) +#define TSB_CANA_GIF_TSOIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,3))) +#define TSB_CANA_GIF_TRMABF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,4))) +#define TSB_CANA_GIF_RMLIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,5))) +#define TSB_CANA_GIF_WUIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,6))) +#define TSB_CANA_GIF_RFPF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIF,7))) +#define TSB_CANA_GIM_WLIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,0))) +#define TSB_CANA_GIM_EPIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,1))) +#define TSB_CANA_GIM_BOIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,2))) +#define TSB_CANA_GIM_TSOIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,3))) +#define TSB_CANA_GIM_TRMABF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,4))) +#define TSB_CANA_GIM_RMLIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,5))) +#define TSB_CANA_GIM_WUIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,6))) +#define TSB_CANA_GIM_RFPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->GIM,7))) +#define TSB_CANA_MBTIF_MBTIF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,0))) +#define TSB_CANA_MBTIF_MBTIF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,1))) +#define TSB_CANA_MBTIF_MBTIF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,2))) +#define TSB_CANA_MBTIF_MBTIF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,3))) +#define TSB_CANA_MBTIF_MBTIF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,4))) +#define TSB_CANA_MBTIF_MBTIF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,5))) +#define TSB_CANA_MBTIF_MBTIF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,6))) +#define TSB_CANA_MBTIF_MBTIF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,7))) +#define TSB_CANA_MBTIF_MBTIF8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,8))) +#define TSB_CANA_MBTIF_MBTIF9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,9))) +#define TSB_CANA_MBTIF_MBTIF10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,10))) +#define TSB_CANA_MBTIF_MBTIF11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,11))) +#define TSB_CANA_MBTIF_MBTIF12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,12))) +#define TSB_CANA_MBTIF_MBTIF13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,13))) +#define TSB_CANA_MBTIF_MBTIF14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,14))) +#define TSB_CANA_MBTIF_MBTIF15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,15))) +#define TSB_CANA_MBTIF_MBTIF16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,16))) +#define TSB_CANA_MBTIF_MBTIF17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,17))) +#define TSB_CANA_MBTIF_MBTIF18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,18))) +#define TSB_CANA_MBTIF_MBTIF19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,19))) +#define TSB_CANA_MBTIF_MBTIF20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,20))) +#define TSB_CANA_MBTIF_MBTIF21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,21))) +#define TSB_CANA_MBTIF_MBTIF22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,22))) +#define TSB_CANA_MBTIF_MBTIF23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,23))) +#define TSB_CANA_MBTIF_MBTIF24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,24))) +#define TSB_CANA_MBTIF_MBTIF25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,25))) +#define TSB_CANA_MBTIF_MBTIF26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,26))) +#define TSB_CANA_MBTIF_MBTIF27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,27))) +#define TSB_CANA_MBTIF_MBTIF28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,28))) +#define TSB_CANA_MBTIF_MBTIF29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,29))) +#define TSB_CANA_MBTIF_MBTIF30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBTIF,30))) +#define TSB_CANA_MBRIF_MBRIF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,0))) +#define TSB_CANA_MBRIF_MBRIF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,1))) +#define TSB_CANA_MBRIF_MBRIF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,2))) +#define TSB_CANA_MBRIF_MBRIF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,3))) +#define TSB_CANA_MBRIF_MBRIF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,4))) +#define TSB_CANA_MBRIF_MBRIF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,5))) +#define TSB_CANA_MBRIF_MBRIF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,6))) +#define TSB_CANA_MBRIF_MBRIF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,7))) +#define TSB_CANA_MBRIF_MBRIF8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,8))) +#define TSB_CANA_MBRIF_MBRIF9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,9))) +#define TSB_CANA_MBRIF_MBRIF10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,10))) +#define TSB_CANA_MBRIF_MBRIF11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,11))) +#define TSB_CANA_MBRIF_MBRIF12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,12))) +#define TSB_CANA_MBRIF_MBRIF13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,13))) +#define TSB_CANA_MBRIF_MBRIF14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,14))) +#define TSB_CANA_MBRIF_MBRIF15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,15))) +#define TSB_CANA_MBRIF_MBRIF16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,16))) +#define TSB_CANA_MBRIF_MBRIF17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,17))) +#define TSB_CANA_MBRIF_MBRIF18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,18))) +#define TSB_CANA_MBRIF_MBRIF19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,19))) +#define TSB_CANA_MBRIF_MBRIF20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,20))) +#define TSB_CANA_MBRIF_MBRIF21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,21))) +#define TSB_CANA_MBRIF_MBRIF22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,22))) +#define TSB_CANA_MBRIF_MBRIF23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,23))) +#define TSB_CANA_MBRIF_MBRIF24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,24))) +#define TSB_CANA_MBRIF_MBRIF25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,25))) +#define TSB_CANA_MBRIF_MBRIF26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,26))) +#define TSB_CANA_MBRIF_MBRIF27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,27))) +#define TSB_CANA_MBRIF_MBRIF28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,28))) +#define TSB_CANA_MBRIF_MBRIF29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,29))) +#define TSB_CANA_MBRIF_MBRIF30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,30))) +#define TSB_CANA_MBRIF_MBRIF31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBRIF,31))) +#define TSB_CANA_MBIM_MBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,0))) +#define TSB_CANA_MBIM_MBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,1))) +#define TSB_CANA_MBIM_MBIM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,2))) +#define TSB_CANA_MBIM_MBIM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,3))) +#define TSB_CANA_MBIM_MBIM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,4))) +#define TSB_CANA_MBIM_MBIM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,5))) +#define TSB_CANA_MBIM_MBIM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,6))) +#define TSB_CANA_MBIM_MBIM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,7))) +#define TSB_CANA_MBIM_MBIM8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,8))) +#define TSB_CANA_MBIM_MBIM9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,9))) +#define TSB_CANA_MBIM_MBIM10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,10))) +#define TSB_CANA_MBIM_MBIM11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,11))) +#define TSB_CANA_MBIM_MBIM12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,12))) +#define TSB_CANA_MBIM_MBIM13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,13))) +#define TSB_CANA_MBIM_MBIM14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,14))) +#define TSB_CANA_MBIM_MBIM15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,15))) +#define TSB_CANA_MBIM_MBIM16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,16))) +#define TSB_CANA_MBIM_MBIM17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,17))) +#define TSB_CANA_MBIM_MBIM18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,18))) +#define TSB_CANA_MBIM_MBIM19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,19))) +#define TSB_CANA_MBIM_MBIM20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,20))) +#define TSB_CANA_MBIM_MBIM21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,21))) +#define TSB_CANA_MBIM_MBIM22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,22))) +#define TSB_CANA_MBIM_MBIM23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,23))) +#define TSB_CANA_MBIM_MBIM24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,24))) +#define TSB_CANA_MBIM_MBIM25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,25))) +#define TSB_CANA_MBIM_MBIM26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,26))) +#define TSB_CANA_MBIM_MBIM27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,27))) +#define TSB_CANA_MBIM_MBIM28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,28))) +#define TSB_CANA_MBIM_MBIM29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,29))) +#define TSB_CANA_MBIM_MBIM30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,30))) +#define TSB_CANA_MBIM_MBIM31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->MBIM,31))) +#define TSB_CANA_CDR_CDR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,0))) +#define TSB_CANA_CDR_CDR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,1))) +#define TSB_CANA_CDR_CDR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,2))) +#define TSB_CANA_CDR_CDR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,3))) +#define TSB_CANA_CDR_CDR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,4))) +#define TSB_CANA_CDR_CDR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,5))) +#define TSB_CANA_CDR_CDR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,6))) +#define TSB_CANA_CDR_CDR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,7))) +#define TSB_CANA_CDR_CDR8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,8))) +#define TSB_CANA_CDR_CDR9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,9))) +#define TSB_CANA_CDR_CDR10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,10))) +#define TSB_CANA_CDR_CDR11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,11))) +#define TSB_CANA_CDR_CDR12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,12))) +#define TSB_CANA_CDR_CDR13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,13))) +#define TSB_CANA_CDR_CDR14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,14))) +#define TSB_CANA_CDR_CDR15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,15))) +#define TSB_CANA_CDR_CDR16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,16))) +#define TSB_CANA_CDR_CDR17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,17))) +#define TSB_CANA_CDR_CDR18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,18))) +#define TSB_CANA_CDR_CDR19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,19))) +#define TSB_CANA_CDR_CDR20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,20))) +#define TSB_CANA_CDR_CDR21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,21))) +#define TSB_CANA_CDR_CDR22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,22))) +#define TSB_CANA_CDR_CDR23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,23))) +#define TSB_CANA_CDR_CDR24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,24))) +#define TSB_CANA_CDR_CDR25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,25))) +#define TSB_CANA_CDR_CDR26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,26))) +#define TSB_CANA_CDR_CDR27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,27))) +#define TSB_CANA_CDR_CDR28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,28))) +#define TSB_CANA_CDR_CDR29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,29))) +#define TSB_CANA_CDR_CDR30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->CDR,30))) +#define TSB_CANA_RFP_RFP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,0))) +#define TSB_CANA_RFP_RFP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,1))) +#define TSB_CANA_RFP_RFP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,2))) +#define TSB_CANA_RFP_RFP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,3))) +#define TSB_CANA_RFP_RFP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,4))) +#define TSB_CANA_RFP_RFP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,5))) +#define TSB_CANA_RFP_RFP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,6))) +#define TSB_CANA_RFP_RFP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,7))) +#define TSB_CANA_RFP_RFP8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,8))) +#define TSB_CANA_RFP_RFP9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,9))) +#define TSB_CANA_RFP_RFP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,10))) +#define TSB_CANA_RFP_RFP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,11))) +#define TSB_CANA_RFP_RFP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,12))) +#define TSB_CANA_RFP_RFP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,13))) +#define TSB_CANA_RFP_RFP14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,14))) +#define TSB_CANA_RFP_RFP15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,15))) +#define TSB_CANA_RFP_RFP16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,16))) +#define TSB_CANA_RFP_RFP17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,17))) +#define TSB_CANA_RFP_RFP18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,18))) +#define TSB_CANA_RFP_RFP19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,19))) +#define TSB_CANA_RFP_RFP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,20))) +#define TSB_CANA_RFP_RFP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,21))) +#define TSB_CANA_RFP_RFP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,22))) +#define TSB_CANA_RFP_RFP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,23))) +#define TSB_CANA_RFP_RFP24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,24))) +#define TSB_CANA_RFP_RFP25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,25))) +#define TSB_CANA_RFP_RFP26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,26))) +#define TSB_CANA_RFP_RFP27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,27))) +#define TSB_CANA_RFP_RFP28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,28))) +#define TSB_CANA_RFP_RFP29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,29))) +#define TSB_CANA_RFP_RFP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,30))) +#define TSB_CANA_RFP_RFP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANA->RFP,31))) + +#define TSB_CANB_MC_MC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,0))) +#define TSB_CANB_MC_MC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,1))) +#define TSB_CANB_MC_MC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,2))) +#define TSB_CANB_MC_MC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,3))) +#define TSB_CANB_MC_MC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,4))) +#define TSB_CANB_MC_MC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,5))) +#define TSB_CANB_MC_MC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,6))) +#define TSB_CANB_MC_MC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,7))) +#define TSB_CANB_MC_MC8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,8))) +#define TSB_CANB_MC_MC9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,9))) +#define TSB_CANB_MC_MC10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,10))) +#define TSB_CANB_MC_MC11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,11))) +#define TSB_CANB_MC_MC12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,12))) +#define TSB_CANB_MC_MC13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,13))) +#define TSB_CANB_MC_MC14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,14))) +#define TSB_CANB_MC_MC15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,15))) +#define TSB_CANB_MC_MC16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,16))) +#define TSB_CANB_MC_MC17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,17))) +#define TSB_CANB_MC_MC18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,18))) +#define TSB_CANB_MC_MC19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,19))) +#define TSB_CANB_MC_MC20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,20))) +#define TSB_CANB_MC_MC21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,21))) +#define TSB_CANB_MC_MC22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,22))) +#define TSB_CANB_MC_MC23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,23))) +#define TSB_CANB_MC_MC24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,24))) +#define TSB_CANB_MC_MC25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,25))) +#define TSB_CANB_MC_MC26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,26))) +#define TSB_CANB_MC_MC27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,27))) +#define TSB_CANB_MC_MC28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,28))) +#define TSB_CANB_MC_MC29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,29))) +#define TSB_CANB_MC_MC30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,30))) +#define TSB_CANB_MC_MC31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MC,31))) +#define TSB_CANB_MD_MD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,0))) +#define TSB_CANB_MD_MD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,1))) +#define TSB_CANB_MD_MD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,2))) +#define TSB_CANB_MD_MD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,3))) +#define TSB_CANB_MD_MD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,4))) +#define TSB_CANB_MD_MD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,5))) +#define TSB_CANB_MD_MD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,6))) +#define TSB_CANB_MD_MD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,7))) +#define TSB_CANB_MD_MD8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,8))) +#define TSB_CANB_MD_MD9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,9))) +#define TSB_CANB_MD_MD10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,10))) +#define TSB_CANB_MD_MD11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,11))) +#define TSB_CANB_MD_MD12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,12))) +#define TSB_CANB_MD_MD13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,13))) +#define TSB_CANB_MD_MD14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,14))) +#define TSB_CANB_MD_MD15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,15))) +#define TSB_CANB_MD_MD16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,16))) +#define TSB_CANB_MD_MD17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,17))) +#define TSB_CANB_MD_MD18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,18))) +#define TSB_CANB_MD_MD19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,19))) +#define TSB_CANB_MD_MD20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,20))) +#define TSB_CANB_MD_MD21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,21))) +#define TSB_CANB_MD_MD22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,22))) +#define TSB_CANB_MD_MD23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,23))) +#define TSB_CANB_MD_MD24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,24))) +#define TSB_CANB_MD_MD25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,25))) +#define TSB_CANB_MD_MD26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,26))) +#define TSB_CANB_MD_MD27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,27))) +#define TSB_CANB_MD_MD28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,28))) +#define TSB_CANB_MD_MD29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,29))) +#define TSB_CANB_MD_MD30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MD,30))) +#define TSB_CANB_MD_MD31 (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->MD,31))) +#define TSB_CANB_TRS_TRS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,0))) +#define TSB_CANB_TRS_TRS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,1))) +#define TSB_CANB_TRS_TRS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,2))) +#define TSB_CANB_TRS_TRS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,3))) +#define TSB_CANB_TRS_TRS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,4))) +#define TSB_CANB_TRS_TRS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,5))) +#define TSB_CANB_TRS_TRS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,6))) +#define TSB_CANB_TRS_TRS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,7))) +#define TSB_CANB_TRS_TRS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,8))) +#define TSB_CANB_TRS_TRS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,9))) +#define TSB_CANB_TRS_TRS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,10))) +#define TSB_CANB_TRS_TRS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,11))) +#define TSB_CANB_TRS_TRS12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,12))) +#define TSB_CANB_TRS_TRS13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,13))) +#define TSB_CANB_TRS_TRS14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,14))) +#define TSB_CANB_TRS_TRS15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,15))) +#define TSB_CANB_TRS_TRS16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,16))) +#define TSB_CANB_TRS_TRS17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,17))) +#define TSB_CANB_TRS_TRS18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,18))) +#define TSB_CANB_TRS_TRS19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,19))) +#define TSB_CANB_TRS_TRS20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,20))) +#define TSB_CANB_TRS_TRS21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,21))) +#define TSB_CANB_TRS_TRS22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,22))) +#define TSB_CANB_TRS_TRS23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,23))) +#define TSB_CANB_TRS_TRS24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,24))) +#define TSB_CANB_TRS_TRS25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,25))) +#define TSB_CANB_TRS_TRS26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,26))) +#define TSB_CANB_TRS_TRS27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,27))) +#define TSB_CANB_TRS_TRS28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,28))) +#define TSB_CANB_TRS_TRS29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,29))) +#define TSB_CANB_TRS_TRS30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRS,30))) +#define TSB_CANB_TRR_TRR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,0))) +#define TSB_CANB_TRR_TRR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,1))) +#define TSB_CANB_TRR_TRR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,2))) +#define TSB_CANB_TRR_TRR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,3))) +#define TSB_CANB_TRR_TRR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,4))) +#define TSB_CANB_TRR_TRR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,5))) +#define TSB_CANB_TRR_TRR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,6))) +#define TSB_CANB_TRR_TRR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,7))) +#define TSB_CANB_TRR_TRR8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,8))) +#define TSB_CANB_TRR_TRR9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,9))) +#define TSB_CANB_TRR_TRR10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,10))) +#define TSB_CANB_TRR_TRR11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,11))) +#define TSB_CANB_TRR_TRR12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,12))) +#define TSB_CANB_TRR_TRR13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,13))) +#define TSB_CANB_TRR_TRR14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,14))) +#define TSB_CANB_TRR_TRR15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,15))) +#define TSB_CANB_TRR_TRR16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,16))) +#define TSB_CANB_TRR_TRR17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,17))) +#define TSB_CANB_TRR_TRR18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,18))) +#define TSB_CANB_TRR_TRR19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,19))) +#define TSB_CANB_TRR_TRR20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,20))) +#define TSB_CANB_TRR_TRR21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,21))) +#define TSB_CANB_TRR_TRR22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,22))) +#define TSB_CANB_TRR_TRR23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,23))) +#define TSB_CANB_TRR_TRR24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,24))) +#define TSB_CANB_TRR_TRR25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,25))) +#define TSB_CANB_TRR_TRR26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,26))) +#define TSB_CANB_TRR_TRR27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,27))) +#define TSB_CANB_TRR_TRR28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,28))) +#define TSB_CANB_TRR_TRR29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,29))) +#define TSB_CANB_TRR_TRR30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TRR,30))) +#define TSB_CANB_TA_TA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,0))) +#define TSB_CANB_TA_TA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,1))) +#define TSB_CANB_TA_TA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,2))) +#define TSB_CANB_TA_TA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,3))) +#define TSB_CANB_TA_TA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,4))) +#define TSB_CANB_TA_TA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,5))) +#define TSB_CANB_TA_TA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,6))) +#define TSB_CANB_TA_TA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,7))) +#define TSB_CANB_TA_TA8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,8))) +#define TSB_CANB_TA_TA9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,9))) +#define TSB_CANB_TA_TA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,10))) +#define TSB_CANB_TA_TA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,11))) +#define TSB_CANB_TA_TA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,12))) +#define TSB_CANB_TA_TA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,13))) +#define TSB_CANB_TA_TA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,14))) +#define TSB_CANB_TA_TA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,15))) +#define TSB_CANB_TA_TA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,16))) +#define TSB_CANB_TA_TA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,17))) +#define TSB_CANB_TA_TA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,18))) +#define TSB_CANB_TA_TA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,19))) +#define TSB_CANB_TA_TA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,20))) +#define TSB_CANB_TA_TA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,21))) +#define TSB_CANB_TA_TA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,22))) +#define TSB_CANB_TA_TA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,23))) +#define TSB_CANB_TA_TA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,24))) +#define TSB_CANB_TA_TA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,25))) +#define TSB_CANB_TA_TA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,26))) +#define TSB_CANB_TA_TA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,27))) +#define TSB_CANB_TA_TA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,28))) +#define TSB_CANB_TA_TA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,29))) +#define TSB_CANB_TA_TA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->TA,30))) +#define TSB_CANB_AA_AA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,0))) +#define TSB_CANB_AA_AA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,1))) +#define TSB_CANB_AA_AA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,2))) +#define TSB_CANB_AA_AA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,3))) +#define TSB_CANB_AA_AA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,4))) +#define TSB_CANB_AA_AA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,5))) +#define TSB_CANB_AA_AA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,6))) +#define TSB_CANB_AA_AA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,7))) +#define TSB_CANB_AA_AA8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,8))) +#define TSB_CANB_AA_AA9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,9))) +#define TSB_CANB_AA_AA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,10))) +#define TSB_CANB_AA_AA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,11))) +#define TSB_CANB_AA_AA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,12))) +#define TSB_CANB_AA_AA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,13))) +#define TSB_CANB_AA_AA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,14))) +#define TSB_CANB_AA_AA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,15))) +#define TSB_CANB_AA_AA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,16))) +#define TSB_CANB_AA_AA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,17))) +#define TSB_CANB_AA_AA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,18))) +#define TSB_CANB_AA_AA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,19))) +#define TSB_CANB_AA_AA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,20))) +#define TSB_CANB_AA_AA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,21))) +#define TSB_CANB_AA_AA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,22))) +#define TSB_CANB_AA_AA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,23))) +#define TSB_CANB_AA_AA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,24))) +#define TSB_CANB_AA_AA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,25))) +#define TSB_CANB_AA_AA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,26))) +#define TSB_CANB_AA_AA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,27))) +#define TSB_CANB_AA_AA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,28))) +#define TSB_CANB_AA_AA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,29))) +#define TSB_CANB_AA_AA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->AA,30))) +#define TSB_CANB_RMP_RMP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,0))) +#define TSB_CANB_RMP_RMP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,1))) +#define TSB_CANB_RMP_RMP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,2))) +#define TSB_CANB_RMP_RMP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,3))) +#define TSB_CANB_RMP_RMP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,4))) +#define TSB_CANB_RMP_RMP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,5))) +#define TSB_CANB_RMP_RMP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,6))) +#define TSB_CANB_RMP_RMP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,7))) +#define TSB_CANB_RMP_RMP8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,8))) +#define TSB_CANB_RMP_RMP9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,9))) +#define TSB_CANB_RMP_RMP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,10))) +#define TSB_CANB_RMP_RMP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,11))) +#define TSB_CANB_RMP_RMP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,12))) +#define TSB_CANB_RMP_RMP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,13))) +#define TSB_CANB_RMP_RMP14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,14))) +#define TSB_CANB_RMP_RMP15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,15))) +#define TSB_CANB_RMP_RMP16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,16))) +#define TSB_CANB_RMP_RMP17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,17))) +#define TSB_CANB_RMP_RMP18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,18))) +#define TSB_CANB_RMP_RMP19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,19))) +#define TSB_CANB_RMP_RMP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,20))) +#define TSB_CANB_RMP_RMP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,21))) +#define TSB_CANB_RMP_RMP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,22))) +#define TSB_CANB_RMP_RMP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,23))) +#define TSB_CANB_RMP_RMP24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,24))) +#define TSB_CANB_RMP_RMP25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,25))) +#define TSB_CANB_RMP_RMP26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,26))) +#define TSB_CANB_RMP_RMP27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,27))) +#define TSB_CANB_RMP_RMP28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,28))) +#define TSB_CANB_RMP_RMP29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,29))) +#define TSB_CANB_RMP_RMP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,30))) +#define TSB_CANB_RMP_RMP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RMP,31))) +#define TSB_CANB_RML_RML0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,0))) +#define TSB_CANB_RML_RML1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,1))) +#define TSB_CANB_RML_RML2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,2))) +#define TSB_CANB_RML_RML3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,3))) +#define TSB_CANB_RML_RML4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,4))) +#define TSB_CANB_RML_RML5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,5))) +#define TSB_CANB_RML_RML6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,6))) +#define TSB_CANB_RML_RML7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,7))) +#define TSB_CANB_RML_RML8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,8))) +#define TSB_CANB_RML_RML9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,9))) +#define TSB_CANB_RML_RML10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,10))) +#define TSB_CANB_RML_RML11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,11))) +#define TSB_CANB_RML_RML12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,12))) +#define TSB_CANB_RML_RML13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,13))) +#define TSB_CANB_RML_RML14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,14))) +#define TSB_CANB_RML_RML15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,15))) +#define TSB_CANB_RML_RML16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,16))) +#define TSB_CANB_RML_RML17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,17))) +#define TSB_CANB_RML_RML18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,18))) +#define TSB_CANB_RML_RML19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,19))) +#define TSB_CANB_RML_RML20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,20))) +#define TSB_CANB_RML_RML21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,21))) +#define TSB_CANB_RML_RML22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,22))) +#define TSB_CANB_RML_RML23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,23))) +#define TSB_CANB_RML_RML24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,24))) +#define TSB_CANB_RML_RML25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,25))) +#define TSB_CANB_RML_RML26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,26))) +#define TSB_CANB_RML_RML27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,27))) +#define TSB_CANB_RML_RML28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,28))) +#define TSB_CANB_RML_RML29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,29))) +#define TSB_CANB_RML_RML30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,30))) +#define TSB_CANB_RML_RML31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RML,31))) +#define TSB_CANB_LAM_LAMI (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->LAM,31))) +#define TSB_CANB_GAM_GAMI (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GAM,31))) +#define TSB_CANB_MCR_SRES (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,0))) +#define TSB_CANB_MCR_TSCC (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,1))) +#define TSB_CANB_MCR_MTOS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,3))) +#define TSB_CANB_MCR_WUBA (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,4))) +#define TSB_CANB_MCR_SMR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,6))) +#define TSB_CANB_MCR_CCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,7))) +#define TSB_CANB_MCR_TSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,8))) +#define TSB_CANB_MCR_TSTLB (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,9))) +#define TSB_CANB_MCR_SUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MCR,11))) +#define TSB_CANB_GSR_EW (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,0))) +#define TSB_CANB_GSR_EP (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,1))) +#define TSB_CANB_GSR_BO (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,2))) +#define TSB_CANB_GSR_TSO (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,3))) +#define TSB_CANB_GSR_SMA (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,6))) +#define TSB_CANB_GSR_CCE (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,7))) +#define TSB_CANB_GSR_SUA (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,8))) +#define TSB_CANB_GSR_TM (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,10))) +#define TSB_CANB_GSR_RM (*((__I uint32_t *)BITBAND_PERI(&TSB_CANB->GSR,11))) +#define TSB_CANB_BCR2_SAM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->BCR2,7))) +#define TSB_CANB_GIF_WLIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,0))) +#define TSB_CANB_GIF_EPIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,1))) +#define TSB_CANB_GIF_BOIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,2))) +#define TSB_CANB_GIF_TSOIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,3))) +#define TSB_CANB_GIF_TRMABF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,4))) +#define TSB_CANB_GIF_RMLIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,5))) +#define TSB_CANB_GIF_WUIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,6))) +#define TSB_CANB_GIF_RFPF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIF,7))) +#define TSB_CANB_GIM_WLIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,0))) +#define TSB_CANB_GIM_EPIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,1))) +#define TSB_CANB_GIM_BOIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,2))) +#define TSB_CANB_GIM_TSOIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,3))) +#define TSB_CANB_GIM_TRMABF (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,4))) +#define TSB_CANB_GIM_RMLIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,5))) +#define TSB_CANB_GIM_WUIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,6))) +#define TSB_CANB_GIM_RFPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->GIM,7))) +#define TSB_CANB_MBTIF_MBTIF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,0))) +#define TSB_CANB_MBTIF_MBTIF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,1))) +#define TSB_CANB_MBTIF_MBTIF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,2))) +#define TSB_CANB_MBTIF_MBTIF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,3))) +#define TSB_CANB_MBTIF_MBTIF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,4))) +#define TSB_CANB_MBTIF_MBTIF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,5))) +#define TSB_CANB_MBTIF_MBTIF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,6))) +#define TSB_CANB_MBTIF_MBTIF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,7))) +#define TSB_CANB_MBTIF_MBTIF8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,8))) +#define TSB_CANB_MBTIF_MBTIF9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,9))) +#define TSB_CANB_MBTIF_MBTIF10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,10))) +#define TSB_CANB_MBTIF_MBTIF11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,11))) +#define TSB_CANB_MBTIF_MBTIF12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,12))) +#define TSB_CANB_MBTIF_MBTIF13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,13))) +#define TSB_CANB_MBTIF_MBTIF14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,14))) +#define TSB_CANB_MBTIF_MBTIF15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,15))) +#define TSB_CANB_MBTIF_MBTIF16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,16))) +#define TSB_CANB_MBTIF_MBTIF17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,17))) +#define TSB_CANB_MBTIF_MBTIF18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,18))) +#define TSB_CANB_MBTIF_MBTIF19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,19))) +#define TSB_CANB_MBTIF_MBTIF20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,20))) +#define TSB_CANB_MBTIF_MBTIF21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,21))) +#define TSB_CANB_MBTIF_MBTIF22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,22))) +#define TSB_CANB_MBTIF_MBTIF23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,23))) +#define TSB_CANB_MBTIF_MBTIF24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,24))) +#define TSB_CANB_MBTIF_MBTIF25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,25))) +#define TSB_CANB_MBTIF_MBTIF26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,26))) +#define TSB_CANB_MBTIF_MBTIF27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,27))) +#define TSB_CANB_MBTIF_MBTIF28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,28))) +#define TSB_CANB_MBTIF_MBTIF29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,29))) +#define TSB_CANB_MBTIF_MBTIF30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBTIF,30))) +#define TSB_CANB_MBRIF_MBRIF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,0))) +#define TSB_CANB_MBRIF_MBRIF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,1))) +#define TSB_CANB_MBRIF_MBRIF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,2))) +#define TSB_CANB_MBRIF_MBRIF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,3))) +#define TSB_CANB_MBRIF_MBRIF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,4))) +#define TSB_CANB_MBRIF_MBRIF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,5))) +#define TSB_CANB_MBRIF_MBRIF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,6))) +#define TSB_CANB_MBRIF_MBRIF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,7))) +#define TSB_CANB_MBRIF_MBRIF8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,8))) +#define TSB_CANB_MBRIF_MBRIF9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,9))) +#define TSB_CANB_MBRIF_MBRIF10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,10))) +#define TSB_CANB_MBRIF_MBRIF11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,11))) +#define TSB_CANB_MBRIF_MBRIF12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,12))) +#define TSB_CANB_MBRIF_MBRIF13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,13))) +#define TSB_CANB_MBRIF_MBRIF14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,14))) +#define TSB_CANB_MBRIF_MBRIF15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,15))) +#define TSB_CANB_MBRIF_MBRIF16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,16))) +#define TSB_CANB_MBRIF_MBRIF17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,17))) +#define TSB_CANB_MBRIF_MBRIF18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,18))) +#define TSB_CANB_MBRIF_MBRIF19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,19))) +#define TSB_CANB_MBRIF_MBRIF20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,20))) +#define TSB_CANB_MBRIF_MBRIF21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,21))) +#define TSB_CANB_MBRIF_MBRIF22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,22))) +#define TSB_CANB_MBRIF_MBRIF23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,23))) +#define TSB_CANB_MBRIF_MBRIF24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,24))) +#define TSB_CANB_MBRIF_MBRIF25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,25))) +#define TSB_CANB_MBRIF_MBRIF26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,26))) +#define TSB_CANB_MBRIF_MBRIF27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,27))) +#define TSB_CANB_MBRIF_MBRIF28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,28))) +#define TSB_CANB_MBRIF_MBRIF29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,29))) +#define TSB_CANB_MBRIF_MBRIF30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,30))) +#define TSB_CANB_MBRIF_MBRIF31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBRIF,31))) +#define TSB_CANB_MBIM_MBIM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,0))) +#define TSB_CANB_MBIM_MBIM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,1))) +#define TSB_CANB_MBIM_MBIM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,2))) +#define TSB_CANB_MBIM_MBIM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,3))) +#define TSB_CANB_MBIM_MBIM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,4))) +#define TSB_CANB_MBIM_MBIM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,5))) +#define TSB_CANB_MBIM_MBIM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,6))) +#define TSB_CANB_MBIM_MBIM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,7))) +#define TSB_CANB_MBIM_MBIM8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,8))) +#define TSB_CANB_MBIM_MBIM9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,9))) +#define TSB_CANB_MBIM_MBIM10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,10))) +#define TSB_CANB_MBIM_MBIM11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,11))) +#define TSB_CANB_MBIM_MBIM12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,12))) +#define TSB_CANB_MBIM_MBIM13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,13))) +#define TSB_CANB_MBIM_MBIM14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,14))) +#define TSB_CANB_MBIM_MBIM15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,15))) +#define TSB_CANB_MBIM_MBIM16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,16))) +#define TSB_CANB_MBIM_MBIM17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,17))) +#define TSB_CANB_MBIM_MBIM18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,18))) +#define TSB_CANB_MBIM_MBIM19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,19))) +#define TSB_CANB_MBIM_MBIM20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,20))) +#define TSB_CANB_MBIM_MBIM21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,21))) +#define TSB_CANB_MBIM_MBIM22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,22))) +#define TSB_CANB_MBIM_MBIM23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,23))) +#define TSB_CANB_MBIM_MBIM24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,24))) +#define TSB_CANB_MBIM_MBIM25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,25))) +#define TSB_CANB_MBIM_MBIM26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,26))) +#define TSB_CANB_MBIM_MBIM27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,27))) +#define TSB_CANB_MBIM_MBIM28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,28))) +#define TSB_CANB_MBIM_MBIM29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,29))) +#define TSB_CANB_MBIM_MBIM30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,30))) +#define TSB_CANB_MBIM_MBIM31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->MBIM,31))) +#define TSB_CANB_CDR_CDR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,0))) +#define TSB_CANB_CDR_CDR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,1))) +#define TSB_CANB_CDR_CDR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,2))) +#define TSB_CANB_CDR_CDR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,3))) +#define TSB_CANB_CDR_CDR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,4))) +#define TSB_CANB_CDR_CDR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,5))) +#define TSB_CANB_CDR_CDR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,6))) +#define TSB_CANB_CDR_CDR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,7))) +#define TSB_CANB_CDR_CDR8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,8))) +#define TSB_CANB_CDR_CDR9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,9))) +#define TSB_CANB_CDR_CDR10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,10))) +#define TSB_CANB_CDR_CDR11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,11))) +#define TSB_CANB_CDR_CDR12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,12))) +#define TSB_CANB_CDR_CDR13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,13))) +#define TSB_CANB_CDR_CDR14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,14))) +#define TSB_CANB_CDR_CDR15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,15))) +#define TSB_CANB_CDR_CDR16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,16))) +#define TSB_CANB_CDR_CDR17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,17))) +#define TSB_CANB_CDR_CDR18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,18))) +#define TSB_CANB_CDR_CDR19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,19))) +#define TSB_CANB_CDR_CDR20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,20))) +#define TSB_CANB_CDR_CDR21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,21))) +#define TSB_CANB_CDR_CDR22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,22))) +#define TSB_CANB_CDR_CDR23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,23))) +#define TSB_CANB_CDR_CDR24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,24))) +#define TSB_CANB_CDR_CDR25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,25))) +#define TSB_CANB_CDR_CDR26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,26))) +#define TSB_CANB_CDR_CDR27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,27))) +#define TSB_CANB_CDR_CDR28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,28))) +#define TSB_CANB_CDR_CDR29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,29))) +#define TSB_CANB_CDR_CDR30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->CDR,30))) +#define TSB_CANB_RFP_RFP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,0))) +#define TSB_CANB_RFP_RFP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,1))) +#define TSB_CANB_RFP_RFP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,2))) +#define TSB_CANB_RFP_RFP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,3))) +#define TSB_CANB_RFP_RFP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,4))) +#define TSB_CANB_RFP_RFP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,5))) +#define TSB_CANB_RFP_RFP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,6))) +#define TSB_CANB_RFP_RFP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,7))) +#define TSB_CANB_RFP_RFP8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,8))) +#define TSB_CANB_RFP_RFP9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,9))) +#define TSB_CANB_RFP_RFP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,10))) +#define TSB_CANB_RFP_RFP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,11))) +#define TSB_CANB_RFP_RFP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,12))) +#define TSB_CANB_RFP_RFP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,13))) +#define TSB_CANB_RFP_RFP14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,14))) +#define TSB_CANB_RFP_RFP15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,15))) +#define TSB_CANB_RFP_RFP16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,16))) +#define TSB_CANB_RFP_RFP17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,17))) +#define TSB_CANB_RFP_RFP18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,18))) +#define TSB_CANB_RFP_RFP19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,19))) +#define TSB_CANB_RFP_RFP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,20))) +#define TSB_CANB_RFP_RFP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,21))) +#define TSB_CANB_RFP_RFP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,22))) +#define TSB_CANB_RFP_RFP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,23))) +#define TSB_CANB_RFP_RFP24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,24))) +#define TSB_CANB_RFP_RFP25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,25))) +#define TSB_CANB_RFP_RFP26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,26))) +#define TSB_CANB_RFP_RFP27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,27))) +#define TSB_CANB_RFP_RFP28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,28))) +#define TSB_CANB_RFP_RFP29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,29))) +#define TSB_CANB_RFP_RFP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,30))) +#define TSB_CANB_RFP_RFP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CANB->RFP,31))) + + +/* Ether Mac */ +#define TSB_EMA_TMAC_CONFIGURATION_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,2))) +#define TSB_EMA_TMAC_CONFIGURATION_TE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,3))) +#define TSB_EMA_TMAC_CONFIGURATION_DC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,4))) +#define TSB_EMA_TMAC_CONFIGURATION_ACS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,7))) +#define TSB_EMA_TMAC_CONFIGURATION_DR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,9))) +#define TSB_EMA_TMAC_CONFIGURATION_IPC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,10))) +#define TSB_EMA_TMAC_CONFIGURATION_DM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,11))) +#define TSB_EMA_TMAC_CONFIGURATION_LM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,12))) +#define TSB_EMA_TMAC_CONFIGURATION_DO (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,13))) +#define TSB_EMA_TMAC_CONFIGURATION_FES (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,14))) +#define TSB_EMA_TMAC_CONFIGURATION_DCRS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,16))) +#define TSB_EMA_TMAC_CONFIGURATION_JE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,20))) +#define TSB_EMA_TMAC_CONFIGURATION_JD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,22))) +#define TSB_EMA_TMAC_CONFIGURATION_WD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,23))) +#define TSB_EMA_TMAC_CONFIGURATION_CST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,25))) +#define TSB_EMA_TMAC_CONFIGURATION_TWOKPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_CONFIGURATION,27))) +#define TSB_EMA_TMAC_FRAME_FILTER_PR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,0))) +#define TSB_EMA_TMAC_FRAME_FILTER_HUC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,1))) +#define TSB_EMA_TMAC_FRAME_FILTER_HMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,2))) +#define TSB_EMA_TMAC_FRAME_FILTER_DAIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,3))) +#define TSB_EMA_TMAC_FRAME_FILTER_PM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,4))) +#define TSB_EMA_TMAC_FRAME_FILTER_DBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,5))) +#define TSB_EMA_TMAC_FRAME_FILTER_SAIF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,8))) +#define TSB_EMA_TMAC_FRAME_FILTER_SAF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,9))) +#define TSB_EMA_TMAC_FRAME_FILTER_HPF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,10))) +#define TSB_EMA_TMAC_FRAME_FILTER_VTFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,16))) +#define TSB_EMA_TMAC_FRAME_FILTER_RA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TMAC_FRAME_FILTER,31))) +#define TSB_EMA_MII_ADDRESS_GB (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MII_ADDRESS,0))) +#define TSB_EMA_MII_ADDRESS_GW (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MII_ADDRESS,1))) +#define TSB_EMA_FLOW_CONTROL_FCA_BPA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->FLOW_CONTROL,0))) +#define TSB_EMA_FLOW_CONTROL_TFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->FLOW_CONTROL,1))) +#define TSB_EMA_FLOW_CONTROL_RFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->FLOW_CONTROL,2))) +#define TSB_EMA_FLOW_CONTROL_UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->FLOW_CONTROL,3))) +#define TSB_EMA_FLOW_CONTROL_DZPQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->FLOW_CONTROL,7))) +#define TSB_EMA_VLAN_TAG_ETV (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->VLAN_TAG,16))) +#define TSB_EMA_VLAN_TAG_VTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->VLAN_TAG,17))) +#define TSB_EMA_VLAN_TAG_ESVL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->VLAN_TAG,18))) +#define TSB_EMA_VLAN_TAG_VTHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->VLAN_TAG,19))) +#define TSB_EMA_DEBUG_RPESTS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->DEBUG,0))) +#define TSB_EMA_DEBUG_RWCSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->DEBUG,4))) +#define TSB_EMA_DEBUG_TPESTS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->DEBUG,16))) +#define TSB_EMA_DEBUG_TXPAUSED (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->DEBUG,19))) +#define TSB_EMA_DEBUG_TWCSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->DEBUG,22))) +#define TSB_EMA_DEBUG_TXFSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->DEBUG,24))) +#define TSB_EMA_PMT_CONTROL_STATUS_PWRDWN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,0))) +#define TSB_EMA_PMT_CONTROL_STATUS_MGKPKTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,1))) +#define TSB_EMA_PMT_CONTROL_STATUS_RWKPKTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,2))) +#define TSB_EMA_PMT_CONTROL_STATUS_MGKPRCVD (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,5))) +#define TSB_EMA_PMT_CONTROL_STATUS_RWKPRCVD (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,6))) +#define TSB_EMA_PMT_CONTROL_STATUS_GLBLUCAST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,9))) +#define TSB_EMA_PMT_CONTROL_STATUS_RWKPFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,10))) +#define TSB_EMA_PMT_CONTROL_STATUS_RWKFILTRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->PMT_CONTROL_STATUS,31))) +#define TSB_EMA_INTERRUPT_STATUS_PMTIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_STATUS,3))) +#define TSB_EMA_INTERRUPT_STATUS_MMCIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_STATUS,4))) +#define TSB_EMA_INTERRUPT_STATUS_MMCRXIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_STATUS,5))) +#define TSB_EMA_INTERRUPT_STATUS_MMCTXIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_STATUS,6))) +#define TSB_EMA_INTERRUPT_STATUS_MMCRXIPIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_STATUS,7))) +#define TSB_EMA_INTERRUPT_STATUS_TSIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_STATUS,9))) +#define TSB_EMA_INTERRUPT_MASK_PMTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_MASK,3))) +#define TSB_EMA_INTERRUPT_MASK_TSIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_MASK,9))) +#define TSB_EMA_MAC_ADDRESS0_HIGH_AE (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_ADDRESS0_HIGH,31))) +#define TSB_EMA_MAC_ADDRESS1_HIGH_SA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_ADDRESS1_HIGH,30))) +#define TSB_EMA_MAC_ADDRESS1_HIGH_AE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_ADDRESS1_HIGH,31))) +#define TSB_EMA_MAC_ADDRESS2_HIGH_SA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_ADDRESS2_HIGH,30))) +#define TSB_EMA_MAC_ADDRESS2_HIGH_AE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_ADDRESS2_HIGH,31))) +#define TSB_EMA_MAC_ADDRESS3_HIGH_SA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_ADDRESS3_HIGH,30))) +#define TSB_EMA_MAC_ADDRESS3_HIGH_AE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_ADDRESS3_HIGH,31))) +#define TSB_EMA_WDOG_TIMEOUT_PWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->WDOG_TIMEOUT,16))) +#define TSB_EMA_MMC_CONTROL_CNTRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_CONTROL,0))) +#define TSB_EMA_MMC_CONTROL_CNTSTOPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_CONTROL,1))) +#define TSB_EMA_MMC_CONTROL_RSTONRD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_CONTROL,2))) +#define TSB_EMA_MMC_CONTROL_CNTFREEZ (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_CONTROL,3))) +#define TSB_EMA_MMC_CONTROL_CNTPRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_CONTROL,4))) +#define TSB_EMA_MMC_CONTROL_CNTPRSTLVL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_CONTROL,5))) +#define TSB_EMA_MMC_CONTROL_UCDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_CONTROL,8))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_RXGBFRMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT,0))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_RXCRCERFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT,5))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_RXALGNERFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT,6))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_RXUCGFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT,17))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_RXFOVFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT,21))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT,13))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT,14))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT,15))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_TXGFRMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT,21))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT_MASK,0))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT_MASK,5))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT_MASK,6))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT_MASK,17))) +#define TSB_EMA_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_RECEIVE_INTERRUPT_MASK,21))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT_MASK,13))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT_MASK,14))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT_MASK,15))) +#define TSB_EMA_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_TRANSMIT_INTERRUPT_MASK,21))) +#define TSB_EMA_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_IPC_RECEIVE_INTERRUPT_MASK,12))) +#define TSB_EMA_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_IPC_RECEIVE_INTERRUPT_MASK,13))) +#define TSB_EMA_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_IPC_RECEIVE_INTERRUPT,12))) +#define TSB_EMA_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MMC_IPC_RECEIVE_INTERRUPT,13))) +#define TSB_EMA_VLAN_INCL_REG_VLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->VLAN_INCL_REG,18))) +#define TSB_EMA_VLAN_INCL_REG_CSVL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->VLAN_INCL_REG,19))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,0))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSCFUPDT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,1))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSINIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,2))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSUPDT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,3))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSTRIG (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,4))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSADDREG (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,5))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSENALL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,8))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSCTRLSSR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,9))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSVER2ENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,10))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSIPENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,11))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSIPV6ENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,12))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSIPV4ENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,13))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSEVNTENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,14))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSMSTRENA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,15))) +#define TSB_EMA_TIMESTAMP_CONTROL_TSENMACADDR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_CONTROL,18))) +#define TSB_EMA_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->SYSTEM_TIME_NANOSECONDS_UPDATE,31))) +#define TSB_EMA_TARGET_TIME_NANOSECONDS_TRGTBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->TARGET_TIME_NANOSECONDS,31))) +#define TSB_EMA_TIMESTAMP_STATUS_TSSOVF (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_STATUS,0))) +#define TSB_EMA_TIMESTAMP_STATUS_TSTARGT0 (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_STATUS,1))) +#define TSB_EMA_TIMESTAMP_STATUS_TSTRGTERR0 (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_STATUS,3))) +#define TSB_EMA_TIMESTAMP_STATUS_TSTARGT1 (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_STATUS,4))) +#define TSB_EMA_TIMESTAMP_STATUS_TSTRGTERR1 (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->TIMESTAMP_STATUS,5))) +#define TSB_EMA_PPS_CONTROL_PPSEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->PPS_CONTROL,4))) +#define TSB_EMA_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1 (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->PPS1_TARGET_TIME_NANOSECONDS,31))) +#define TSB_EMA_BUS_MODE_SWR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,0))) +#define TSB_EMA_BUS_MODE_DA (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,1))) +#define TSB_EMA_BUS_MODE_ATDS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,7))) +#define TSB_EMA_BUS_MODE_FB (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,16))) +#define TSB_EMA_BUS_MODE_USP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,23))) +#define TSB_EMA_BUS_MODE_PBLX8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,24))) +#define TSB_EMA_BUS_MODE_AAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,25))) +#define TSB_EMA_BUS_MODE_MB (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,26))) +#define TSB_EMA_BUS_MODE_TXPR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->BUS_MODE,27))) +#define TSB_EMA_STATUS_TI (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,0))) +#define TSB_EMA_STATUS_TPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,1))) +#define TSB_EMA_STATUS_TU (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,2))) +#define TSB_EMA_STATUS_TJT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,3))) +#define TSB_EMA_STATUS_OVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,4))) +#define TSB_EMA_STATUS_UNF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,5))) +#define TSB_EMA_STATUS_RI (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,6))) +#define TSB_EMA_STATUS_RU (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,7))) +#define TSB_EMA_STATUS_RPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,8))) +#define TSB_EMA_STATUS_RWT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,9))) +#define TSB_EMA_STATUS_ETI (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,10))) +#define TSB_EMA_STATUS_FBI (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,13))) +#define TSB_EMA_STATUS_ERI (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,14))) +#define TSB_EMA_STATUS_AIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,15))) +#define TSB_EMA_STATUS_NIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,16))) +#define TSB_EMA_STATUS_GMI (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,27))) +#define TSB_EMA_STATUS_GPI (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,28))) +#define TSB_EMA_STATUS_TTI (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->STATUS,29))) +#define TSB_EMA_OPERATION_MODE_SR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,1))) +#define TSB_EMA_OPERATION_MODE_OSF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,2))) +#define TSB_EMA_OPERATION_MODE_DGF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,5))) +#define TSB_EMA_OPERATION_MODE_FUF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,6))) +#define TSB_EMA_OPERATION_MODE_FEF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,7))) +#define TSB_EMA_OPERATION_MODE_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,13))) +#define TSB_EMA_OPERATION_MODE_FTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,20))) +#define TSB_EMA_OPERATION_MODE_TSF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,21))) +#define TSB_EMA_OPERATION_MODE_DFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,24))) +#define TSB_EMA_OPERATION_MODE_RSF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,25))) +#define TSB_EMA_OPERATION_MODE_DT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->OPERATION_MODE,26))) +#define TSB_EMA_INTERRUPT_ENABLE_TIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,0))) +#define TSB_EMA_INTERRUPT_ENABLE_TSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,1))) +#define TSB_EMA_INTERRUPT_ENABLE_TUE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,2))) +#define TSB_EMA_INTERRUPT_ENABLE_TJE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,3))) +#define TSB_EMA_INTERRUPT_ENABLE_OVE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,4))) +#define TSB_EMA_INTERRUPT_ENABLE_UNE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,5))) +#define TSB_EMA_INTERRUPT_ENABLE_RIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,6))) +#define TSB_EMA_INTERRUPT_ENABLE_RUE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,7))) +#define TSB_EMA_INTERRUPT_ENABLE_RSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,8))) +#define TSB_EMA_INTERRUPT_ENABLE_RWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,9))) +#define TSB_EMA_INTERRUPT_ENABLE_ETE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,10))) +#define TSB_EMA_INTERRUPT_ENABLE_FBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,13))) +#define TSB_EMA_INTERRUPT_ENABLE_ERE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,14))) +#define TSB_EMA_INTERRUPT_ENABLE_AIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,15))) +#define TSB_EMA_INTERRUPT_ENABLE_NIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->INTERRUPT_ENABLE,16))) +#define TSB_EMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER,16))) +#define TSB_EMA_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER,28))) +#define TSB_EMA_AHB_STATUS_AHSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_EMA->AHB_STATUS,0))) +#define TSB_EMA_MAC_CTRL0_CLK_LM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_CTRL0,4))) +#define TSB_EMA_MAC_CTRL1_TXCLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_CTRL1,0))) +#define TSB_EMA_MAC_CTRL1_RXCLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_CTRL1,1))) +#define TSB_EMA_MAC_CTRL1_RMIICLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_CTRL1,2))) +#define TSB_EMA_MAC_CTRL2_SRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EMA->MAC_CTRL2,0))) + + +/* SMIF */ +#define TSB_SMI0_MAP0_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,0))) +#define TSB_SMI0_MAP0_WE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP0,1))) +#define TSB_SMI0_MAP1_RE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->MAP1,0))) +#define TSB_SMI0_DACR0_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR0,6))) +#define TSB_SMI0_DACR1_POLLWIP (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DACR1,6))) +#define TSB_SMI0_DRCR0_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DRCR0,8))) +#define TSB_SMI0_DRCR1_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DRCR1,8))) +#define TSB_SMI0_DWCR0_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DWCR0,8))) +#define TSB_SMI0_DWCR1_CMDBC (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->DWCR1,8))) +#define TSB_SMI0_RACR1_CYCGO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,0))) +#define TSB_SMI0_RACR1_CSNUM (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,1))) +#define TSB_SMI0_RACR1_PBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,4))) +#define TSB_SMI0_RACR1_SBUFEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->RACR1,5))) +#define TSB_SMI0_OECR_PBUFOCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->OECR,0))) +#define TSB_SMI0_INT_SCDINTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,0))) +#define TSB_SMI0_INT_SDINTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->INT,4))) +#define TSB_SMI0_STAT_CYCDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,0))) +#define TSB_SMI0_STAT_CYCPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,1))) +#define TSB_SMI0_STAT_STPPROGDONE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,4))) +#define TSB_SMI0_STAT_DIACCINPROG (*((__I uint32_t *)BITBAND_PERI(&TSB_SMI0->STAT,6))) +#define TSB_SMI0_SWR_RSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->SWR,0))) +#define TSB_SMI0_ACKR_FRCCLKOUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->ACKR,0))) +#define TSB_SMI0_ACKR_ADDCLKTGLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->ACKR,8))) +#define TSB_SMI0_CCOR_CLKOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,0))) +#define TSB_SMI0_CCOR_CS0OE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,4))) +#define TSB_SMI0_CCOR_CS1OE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->CCOR,5))) +#define TSB_SMI0_STPR_STOPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_SMI0->STPR,0))) + + + +/* Low speed oscillation/power control/reset */ +#define TSB_RLM_LOSCCR_DRCOSCL (*((__IO uint32_t *)BITBAND_PERI(&TSB_RLM->LOSCCR,2))) + + +/* LVD0 */ +#define TSB_LVD_CR1_LVDNEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0))) +#define TSB_LVD_CR1_LVDSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,4))) +#define TSB_LVD_CR2_LVDOEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR2,0))) +#define TSB_LVD_SR_LVDNS (*((__I uint32_t *)BITBAND_PERI(&TSB_LVD->SR,0))) + + +/* TRGSEL */ +#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) +#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) +#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) +#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) +#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) +#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) +#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) +#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) +#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) +#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) +#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) +#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) +#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) +#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) +#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) +#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) +#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) +#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) +#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) +#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) +#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) +#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) +#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) +#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) +#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) +#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) +#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) +#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) +#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) +#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) +#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) +#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) +#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) +#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) +#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) +#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) +#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) +#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) +#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) +#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) +#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) +#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) +#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) +#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) +#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) +#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) +#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) +#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) +#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) +#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) +#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) +#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) +#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) +#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) +#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) +#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) +#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) +#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) +#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) +#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) +#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) +#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) +#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) +#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) +#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) +#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) +#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) +#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) +#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) +#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) +#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) +#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) +#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) +#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) +#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) +#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) +#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) +#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) +#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) +#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) +#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) +#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) +#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) +#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) +#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) +#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) +#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) +#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) +#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) +#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) +#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) +#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) +#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) +#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) +#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) +#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) +#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) +#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) +#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) +#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) +#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) +#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) +#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) +#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) +#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) +#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) +#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) +#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) +#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) +#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) +#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) +#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) +#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) +#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) +#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) +#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) +#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) +#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) +#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) +#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) +#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) +#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) +#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) +#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) +#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) +#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) +#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) +#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) +#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) +#define TSB_TSEL0_CR10_EN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,24))) +#define TSB_TSEL0_CR10_OUTSEL43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,25))) +#define TSB_TSEL0_CR10_UPDN43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,26))) +#define TSB_TSEL0_CR11_EN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,0))) +#define TSB_TSEL0_CR11_OUTSEL44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,1))) +#define TSB_TSEL0_CR11_UPDN44 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,2))) +#define TSB_TSEL0_CR11_EN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,8))) +#define TSB_TSEL0_CR11_OUTSEL45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,9))) +#define TSB_TSEL0_CR11_UPDN45 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,10))) +#define TSB_TSEL0_CR11_EN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,16))) +#define TSB_TSEL0_CR11_OUTSEL46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,17))) +#define TSB_TSEL0_CR11_UPDN46 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,18))) +#define TSB_TSEL0_CR11_EN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,24))) +#define TSB_TSEL0_CR11_OUTSEL47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,25))) +#define TSB_TSEL0_CR11_UPDN47 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR11,26))) +#define TSB_TSEL0_CR12_EN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,0))) +#define TSB_TSEL0_CR12_OUTSEL48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,1))) +#define TSB_TSEL0_CR12_UPDN48 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,2))) +#define TSB_TSEL0_CR12_EN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,8))) +#define TSB_TSEL0_CR12_OUTSEL49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,9))) +#define TSB_TSEL0_CR12_UPDN49 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,10))) +#define TSB_TSEL0_CR12_EN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,16))) +#define TSB_TSEL0_CR12_OUTSEL50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,17))) +#define TSB_TSEL0_CR12_UPDN50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,18))) +#define TSB_TSEL0_CR12_EN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,24))) +#define TSB_TSEL0_CR12_OUTSEL51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,25))) +#define TSB_TSEL0_CR12_UPDN51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR12,26))) +#define TSB_TSEL0_CR13_EN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,0))) +#define TSB_TSEL0_CR13_OUTSEL52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,1))) +#define TSB_TSEL0_CR13_UPDN52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,2))) +#define TSB_TSEL0_CR13_EN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,8))) +#define TSB_TSEL0_CR13_OUTSEL53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,9))) +#define TSB_TSEL0_CR13_UPDN53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,10))) +#define TSB_TSEL0_CR13_EN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,16))) +#define TSB_TSEL0_CR13_OUTSEL54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,17))) +#define TSB_TSEL0_CR13_UPDN54 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,18))) +#define TSB_TSEL0_CR13_EN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,24))) +#define TSB_TSEL0_CR13_OUTSEL55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,25))) +#define TSB_TSEL0_CR13_UPDN55 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR13,26))) +#define TSB_TSEL0_CR14_EN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,0))) +#define TSB_TSEL0_CR14_OUTSEL56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,1))) +#define TSB_TSEL0_CR14_UPDN56 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR14,2))) + + + +/* Serial Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) +#define TSB_TSPI0_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,16))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) +#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) +#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) +#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SECTCR0,0))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) +#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) + +#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) +#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) +#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) +#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) +#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) +#define TSB_TSPI1_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,16))) +#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) +#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) +#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) +#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) +#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) +#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) +#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) +#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) +#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) +#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) +#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) +#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) +#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) +#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) +#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) +#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) +#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) +#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) +#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) +#define TSB_TSPI1_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SECTCR0,0))) +#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) +#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) +#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) +#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) +#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) +#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) +#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) +#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) +#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) +#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) +#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) +#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) +#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) + +#define TSB_TSPI2_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR0,0))) +#define TSB_TSPI2_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,12))) +#define TSB_TSPI2_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,13))) +#define TSB_TSPI2_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,14))) +#define TSB_TSPI2_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,15))) +#define TSB_TSPI2_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR1,16))) +#define TSB_TSPI2_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,0))) +#define TSB_TSPI2_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,1))) +#define TSB_TSPI2_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,2))) +#define TSB_TSPI2_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,4))) +#define TSB_TSPI2_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,5))) +#define TSB_TSPI2_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,6))) +#define TSB_TSPI2_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,7))) +#define TSB_TSPI2_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR2,21))) +#define TSB_TSPI2_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,0))) +#define TSB_TSPI2_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI2->CR3,1))) +#define TSB_TSPI2_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,14))) +#define TSB_TSPI2_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,15))) +#define TSB_TSPI2_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,16))) +#define TSB_TSPI2_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,17))) +#define TSB_TSPI2_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,18))) +#define TSB_TSPI2_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,19))) +#define TSB_TSPI2_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR0,31))) +#define TSB_TSPI2_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,0))) +#define TSB_TSPI2_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->FMTR1,1))) +#define TSB_TSPI2_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SECTCR0,0))) +#define TSB_TSPI2_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,4))) +#define TSB_TSPI2_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,5))) +#define TSB_TSPI2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,6))) +#define TSB_TSPI2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,7))) +#define TSB_TSPI2_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,20))) +#define TSB_TSPI2_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,21))) +#define TSB_TSPI2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,22))) +#define TSB_TSPI2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,23))) +#define TSB_TSPI2_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI2->SR,31))) +#define TSB_TSPI2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,0))) +#define TSB_TSPI2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,1))) +#define TSB_TSPI2_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,2))) +#define TSB_TSPI2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI2->ERR,3))) + +#define TSB_TSPI3_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR0,0))) +#define TSB_TSPI3_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,12))) +#define TSB_TSPI3_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,13))) +#define TSB_TSPI3_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,14))) +#define TSB_TSPI3_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,15))) +#define TSB_TSPI3_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR1,16))) +#define TSB_TSPI3_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,0))) +#define TSB_TSPI3_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,1))) +#define TSB_TSPI3_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,2))) +#define TSB_TSPI3_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,4))) +#define TSB_TSPI3_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,5))) +#define TSB_TSPI3_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,6))) +#define TSB_TSPI3_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,7))) +#define TSB_TSPI3_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR2,21))) +#define TSB_TSPI3_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,0))) +#define TSB_TSPI3_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI3->CR3,1))) +#define TSB_TSPI3_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,14))) +#define TSB_TSPI3_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,15))) +#define TSB_TSPI3_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,16))) +#define TSB_TSPI3_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,17))) +#define TSB_TSPI3_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,18))) +#define TSB_TSPI3_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,19))) +#define TSB_TSPI3_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR0,31))) +#define TSB_TSPI3_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,0))) +#define TSB_TSPI3_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->FMTR1,1))) +#define TSB_TSPI3_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SECTCR0,0))) +#define TSB_TSPI3_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,4))) +#define TSB_TSPI3_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,5))) +#define TSB_TSPI3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,6))) +#define TSB_TSPI3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,7))) +#define TSB_TSPI3_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,20))) +#define TSB_TSPI3_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,21))) +#define TSB_TSPI3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,22))) +#define TSB_TSPI3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,23))) +#define TSB_TSPI3_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI3->SR,31))) +#define TSB_TSPI3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,0))) +#define TSB_TSPI3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,1))) +#define TSB_TSPI3_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,2))) +#define TSB_TSPI3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI3->ERR,3))) + +#define TSB_TSPI4_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR0,0))) +#define TSB_TSPI4_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,12))) +#define TSB_TSPI4_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,13))) +#define TSB_TSPI4_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,14))) +#define TSB_TSPI4_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,15))) +#define TSB_TSPI4_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR1,16))) +#define TSB_TSPI4_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,0))) +#define TSB_TSPI4_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,1))) +#define TSB_TSPI4_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,2))) +#define TSB_TSPI4_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,4))) +#define TSB_TSPI4_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,5))) +#define TSB_TSPI4_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,6))) +#define TSB_TSPI4_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,7))) +#define TSB_TSPI4_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR2,21))) +#define TSB_TSPI4_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,0))) +#define TSB_TSPI4_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI4->CR3,1))) +#define TSB_TSPI4_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,14))) +#define TSB_TSPI4_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,15))) +#define TSB_TSPI4_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,16))) +#define TSB_TSPI4_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,17))) +#define TSB_TSPI4_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,18))) +#define TSB_TSPI4_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,19))) +#define TSB_TSPI4_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR0,31))) +#define TSB_TSPI4_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,0))) +#define TSB_TSPI4_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->FMTR1,1))) +#define TSB_TSPI4_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SECTCR0,0))) +#define TSB_TSPI4_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,4))) +#define TSB_TSPI4_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,5))) +#define TSB_TSPI4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,6))) +#define TSB_TSPI4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,7))) +#define TSB_TSPI4_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,20))) +#define TSB_TSPI4_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,21))) +#define TSB_TSPI4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,22))) +#define TSB_TSPI4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,23))) +#define TSB_TSPI4_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI4->SR,31))) +#define TSB_TSPI4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,0))) +#define TSB_TSPI4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,1))) +#define TSB_TSPI4_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,2))) +#define TSB_TSPI4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI4->ERR,3))) + +#define TSB_TSPI5_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR0,0))) +#define TSB_TSPI5_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,12))) +#define TSB_TSPI5_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,13))) +#define TSB_TSPI5_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,14))) +#define TSB_TSPI5_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,15))) +#define TSB_TSPI5_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR1,16))) +#define TSB_TSPI5_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,0))) +#define TSB_TSPI5_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,1))) +#define TSB_TSPI5_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,2))) +#define TSB_TSPI5_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,4))) +#define TSB_TSPI5_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,5))) +#define TSB_TSPI5_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,6))) +#define TSB_TSPI5_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,7))) +#define TSB_TSPI5_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR2,21))) +#define TSB_TSPI5_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,0))) +#define TSB_TSPI5_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI5->CR3,1))) +#define TSB_TSPI5_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,14))) +#define TSB_TSPI5_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,15))) +#define TSB_TSPI5_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,16))) +#define TSB_TSPI5_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,17))) +#define TSB_TSPI5_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,18))) +#define TSB_TSPI5_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,19))) +#define TSB_TSPI5_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR0,31))) +#define TSB_TSPI5_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,0))) +#define TSB_TSPI5_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->FMTR1,1))) +#define TSB_TSPI5_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SECTCR0,0))) +#define TSB_TSPI5_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,4))) +#define TSB_TSPI5_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,5))) +#define TSB_TSPI5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,6))) +#define TSB_TSPI5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,7))) +#define TSB_TSPI5_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,20))) +#define TSB_TSPI5_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,21))) +#define TSB_TSPI5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,22))) +#define TSB_TSPI5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,23))) +#define TSB_TSPI5_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI5->SR,31))) +#define TSB_TSPI5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,0))) +#define TSB_TSPI5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,1))) +#define TSB_TSPI5_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,2))) +#define TSB_TSPI5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI5->ERR,3))) + +#define TSB_TSPI6_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR0,0))) +#define TSB_TSPI6_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,12))) +#define TSB_TSPI6_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,13))) +#define TSB_TSPI6_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,14))) +#define TSB_TSPI6_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,15))) +#define TSB_TSPI6_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR1,16))) +#define TSB_TSPI6_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,0))) +#define TSB_TSPI6_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,1))) +#define TSB_TSPI6_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,2))) +#define TSB_TSPI6_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,4))) +#define TSB_TSPI6_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,5))) +#define TSB_TSPI6_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,6))) +#define TSB_TSPI6_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,7))) +#define TSB_TSPI6_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR2,21))) +#define TSB_TSPI6_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,0))) +#define TSB_TSPI6_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI6->CR3,1))) +#define TSB_TSPI6_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,14))) +#define TSB_TSPI6_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,15))) +#define TSB_TSPI6_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,16))) +#define TSB_TSPI6_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,17))) +#define TSB_TSPI6_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,18))) +#define TSB_TSPI6_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,19))) +#define TSB_TSPI6_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR0,31))) +#define TSB_TSPI6_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,0))) +#define TSB_TSPI6_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->FMTR1,1))) +#define TSB_TSPI6_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SECTCR0,0))) +#define TSB_TSPI6_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,4))) +#define TSB_TSPI6_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,5))) +#define TSB_TSPI6_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,6))) +#define TSB_TSPI6_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,7))) +#define TSB_TSPI6_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,20))) +#define TSB_TSPI6_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,21))) +#define TSB_TSPI6_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,22))) +#define TSB_TSPI6_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,23))) +#define TSB_TSPI6_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI6->SR,31))) +#define TSB_TSPI6_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,0))) +#define TSB_TSPI6_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,1))) +#define TSB_TSPI6_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,2))) +#define TSB_TSPI6_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI6->ERR,3))) + +#define TSB_TSPI7_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR0,0))) +#define TSB_TSPI7_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,12))) +#define TSB_TSPI7_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,13))) +#define TSB_TSPI7_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,14))) +#define TSB_TSPI7_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,15))) +#define TSB_TSPI7_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR1,16))) +#define TSB_TSPI7_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,0))) +#define TSB_TSPI7_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,1))) +#define TSB_TSPI7_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,2))) +#define TSB_TSPI7_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,4))) +#define TSB_TSPI7_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,5))) +#define TSB_TSPI7_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,6))) +#define TSB_TSPI7_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,7))) +#define TSB_TSPI7_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR2,21))) +#define TSB_TSPI7_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,0))) +#define TSB_TSPI7_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI7->CR3,1))) +#define TSB_TSPI7_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,14))) +#define TSB_TSPI7_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,15))) +#define TSB_TSPI7_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,16))) +#define TSB_TSPI7_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,17))) +#define TSB_TSPI7_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,18))) +#define TSB_TSPI7_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,19))) +#define TSB_TSPI7_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR0,31))) +#define TSB_TSPI7_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,0))) +#define TSB_TSPI7_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->FMTR1,1))) +#define TSB_TSPI7_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SECTCR0,0))) +#define TSB_TSPI7_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,4))) +#define TSB_TSPI7_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,5))) +#define TSB_TSPI7_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,6))) +#define TSB_TSPI7_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,7))) +#define TSB_TSPI7_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,20))) +#define TSB_TSPI7_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,21))) +#define TSB_TSPI7_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,22))) +#define TSB_TSPI7_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,23))) +#define TSB_TSPI7_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI7->SR,31))) +#define TSB_TSPI7_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,0))) +#define TSB_TSPI7_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,1))) +#define TSB_TSPI7_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,2))) +#define TSB_TSPI7_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI7->ERR,3))) + +#define TSB_TSPI8_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR0,0))) +#define TSB_TSPI8_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,12))) +#define TSB_TSPI8_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,13))) +#define TSB_TSPI8_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,14))) +#define TSB_TSPI8_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,15))) +#define TSB_TSPI8_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR1,16))) +#define TSB_TSPI8_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,0))) +#define TSB_TSPI8_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,1))) +#define TSB_TSPI8_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,2))) +#define TSB_TSPI8_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,4))) +#define TSB_TSPI8_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,5))) +#define TSB_TSPI8_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,6))) +#define TSB_TSPI8_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,7))) +#define TSB_TSPI8_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR2,21))) +#define TSB_TSPI8_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,0))) +#define TSB_TSPI8_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI8->CR3,1))) +#define TSB_TSPI8_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,14))) +#define TSB_TSPI8_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,15))) +#define TSB_TSPI8_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,16))) +#define TSB_TSPI8_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,17))) +#define TSB_TSPI8_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,18))) +#define TSB_TSPI8_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,19))) +#define TSB_TSPI8_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR0,31))) +#define TSB_TSPI8_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,0))) +#define TSB_TSPI8_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->FMTR1,1))) +#define TSB_TSPI8_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SECTCR0,0))) +#define TSB_TSPI8_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,4))) +#define TSB_TSPI8_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,5))) +#define TSB_TSPI8_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,6))) +#define TSB_TSPI8_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,7))) +#define TSB_TSPI8_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,20))) +#define TSB_TSPI8_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,21))) +#define TSB_TSPI8_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,22))) +#define TSB_TSPI8_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,23))) +#define TSB_TSPI8_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI8->SR,31))) +#define TSB_TSPI8_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,0))) +#define TSB_TSPI8_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,1))) +#define TSB_TSPI8_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,2))) +#define TSB_TSPI8_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI8->ERR,3))) + + +/* External Bus Interface(EXB) */ +#define TSB_EXB_MOD_EXBSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->MOD,0))) +#define TSB_EXB_CS0_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,0))) +#define TSB_EXB_CS0_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,12))) +#define TSB_EXB_CS0_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,13))) +#define TSB_EXB_CS1_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,0))) +#define TSB_EXB_CS1_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,12))) +#define TSB_EXB_CS1_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,13))) +#define TSB_EXB_CS2_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,0))) +#define TSB_EXB_CS2_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,12))) +#define TSB_EXB_CS2_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,13))) +#define TSB_EXB_CS3_CSW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,0))) +#define TSB_EXB_CS3_WAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,12))) +#define TSB_EXB_CS3_WSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,13))) +#define TSB_EXB_CLKCTL_CLKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CLKCTL,0))) + + +/* Clock Generator (CG) */ +#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_WUPLCR_WULON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,0))) +#define TSB_CG_WUPLCR_WULEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPLCR,1))) +#define TSB_CG_FSYSMENC_IPMENC00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,0))) +#define TSB_CG_FSYSMENC_IPMENC01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,1))) +#define TSB_CG_FSYSMENC_IPMENC02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,2))) +#define TSB_CG_FSYSMENC_IPMENC03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,3))) +#define TSB_CG_FSYSMENC_IPMENC04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,4))) +#define TSB_CG_FSYSMENC_IPMENC05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,5))) +#define TSB_CG_FSYSMENC_IPMENC06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,6))) +#define TSB_CG_FSYSMENC_IPMENC07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,7))) +#define TSB_CG_FSYSMENC_IPMENC08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,8))) +#define TSB_CG_FSYSMENC_IPMENC09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,9))) +#define TSB_CG_FSYSMENC_IPMENC10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,10))) +#define TSB_CG_FSYSMENC_IPMENC11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,11))) +#define TSB_CG_FSYSMENC_IPMENC12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,12))) +#define TSB_CG_FSYSMENC_IPMENC13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,13))) +#define TSB_CG_FSYSMENC_IPMENC14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,14))) +#define TSB_CG_FSYSMENC_IPMENC15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,15))) +#define TSB_CG_FSYSMENC_IPMENC16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENC,16))) +#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0))) +#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1))) +#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2))) +#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3))) +#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4))) +#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5))) +#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6))) +#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7))) +#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8))) +#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9))) +#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10))) +#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11))) +#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12))) +#define TSB_CG_FSYSMENA_IPMENA13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,13))) +#define TSB_CG_FSYSMENA_IPMENA14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,14))) +#define TSB_CG_FSYSMENA_IPMENA15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,15))) +#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16))) +#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17))) +#define TSB_CG_FSYSMENA_IPMENA18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,18))) +#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19))) +#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20))) +#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21))) +#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22))) +#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23))) +#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24))) +#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25))) +#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26))) +#define TSB_CG_FSYSMENA_IPMENA27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,27))) +#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28))) +#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29))) +#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30))) +#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31))) +#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0))) +#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1))) +#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2))) +#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3))) +#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4))) +#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5))) +#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6))) +#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7))) +#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8))) +#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9))) +#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10))) +#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11))) +#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12))) +#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13))) +#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14))) +#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15))) +#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16))) +#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17))) +#define TSB_CG_FSYSMENB_IPMENB18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,18))) +#define TSB_CG_FSYSMENB_IPMENB19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,19))) +#define TSB_CG_FSYSMENB_IPMENB20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,20))) +#define TSB_CG_FSYSMENB_IPMENB21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,21))) +#define TSB_CG_FSYSMENB_IPMENB22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,22))) +#define TSB_CG_FSYSMENB_IPMENB23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,23))) +#define TSB_CG_FSYSMENB_IPMENB24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,24))) +#define TSB_CG_FSYSMENB_IPMENB28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,28))) +#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29))) +#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30))) +#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31))) +#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) +#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) +#define TSB_CG_FSYSENA_IPENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,2))) +#define TSB_CG_FSYSENA_IPENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,3))) +#define TSB_CG_FSYSENA_IPENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,4))) +#define TSB_CG_FSYSENA_IPENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,5))) +#define TSB_CG_FSYSENA_IPENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,6))) +#define TSB_CG_FSYSENA_IPENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,7))) +#define TSB_CG_FSYSENA_IPENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,8))) +#define TSB_CG_FSYSENA_IPENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,9))) +#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23))) +#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26))) +#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27))) +#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) +#define TSB_CG_SPCLKEN_ADCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) +#define TSB_CG_EXTEND2_RSV20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,0))) +#define TSB_CG_EXTEND2_RSV21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,1))) +#define TSB_CG_EXTEND2_RSV22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->EXTEND2,2))) + + + +/* Interrupt Monitor Register */ +#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) +#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) +#define TSB_IMN_FLG1_INT032FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,0))) +#define TSB_IMN_FLG1_INT033FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,1))) +#define TSB_IMN_FLG1_INT034FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,2))) +#define TSB_IMN_FLG1_INT035FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,3))) +#define TSB_IMN_FLG1_INT036FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,4))) +#define TSB_IMN_FLG1_INT037FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,5))) +#define TSB_IMN_FLG1_INT038FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,6))) +#define TSB_IMN_FLG1_INT039FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,7))) +#define TSB_IMN_FLG1_INT040FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,8))) +#define TSB_IMN_FLG1_INT041FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,9))) +#define TSB_IMN_FLG1_INT042FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,10))) +#define TSB_IMN_FLG1_INT043FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,11))) +#define TSB_IMN_FLG1_INT045FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,13))) +#define TSB_IMN_FLG1_INT047FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,15))) +#define TSB_IMN_FLG1_INT048FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,16))) +#define TSB_IMN_FLG1_INT049FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,17))) +#define TSB_IMN_FLG1_INT050FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,18))) +#define TSB_IMN_FLG1_INT051FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,19))) +#define TSB_IMN_FLG1_INT052FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,20))) +#define TSB_IMN_FLG1_INT053FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,21))) +#define TSB_IMN_FLG1_INT054FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,22))) +#define TSB_IMN_FLG1_INT055FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,23))) +#define TSB_IMN_FLG1_INT057FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,25))) +#define TSB_IMN_FLG1_INT059FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,27))) +#define TSB_IMN_FLG1_INT060FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,28))) +#define TSB_IMN_FLG1_INT061FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,29))) +#define TSB_IMN_FLG1_INT062FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,30))) +#define TSB_IMN_FLG1_INT063FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG1,31))) +#define TSB_IMN_FLG2_INT081FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,17))) +#define TSB_IMN_FLG2_INT082FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,18))) +#define TSB_IMN_FLG2_INT083FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,19))) +#define TSB_IMN_FLG2_INT084FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,20))) +#define TSB_IMN_FLG2_INT085FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,21))) +#define TSB_IMN_FLG2_INT086FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,22))) +#define TSB_IMN_FLG2_INT087FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,23))) +#define TSB_IMN_FLG2_INT088FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,24))) +#define TSB_IMN_FLG2_INT089FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG2,25))) +#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) +#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) +#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) +#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) +#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) +#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) +#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) +#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) +#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) +#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) +#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) +#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) +#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) +#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) +#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) +#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) +#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) +#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) +#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) +#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) +#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) +#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) +#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) +#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) +#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) +#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) +#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) +#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) +#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) +#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) +#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) +#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) +#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) +#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) +#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) +#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) +#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) +#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) +#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) +#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) +#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) +#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) +#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) +#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) +#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) +#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) +#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) +#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) +#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) +#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) +#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) +#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) +#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) +#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) +#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) +#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) +#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) +#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) +#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) +#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) +#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) +#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) +#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) +#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) +#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) +#define TSB_IMN_FLG5_INT161FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,1))) +#define TSB_IMN_FLG5_INT162FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,2))) +#define TSB_IMN_FLG5_INT163FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,3))) +#define TSB_IMN_FLG5_INT164FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,4))) +#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) +#define TSB_IMN_FLG5_INT166FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,6))) +#define TSB_IMN_FLG5_INT167FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,7))) +#define TSB_IMN_FLG5_INT168FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,8))) +#define TSB_IMN_FLG5_INT169FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,9))) +#define TSB_IMN_FLG5_INT170FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,10))) +#define TSB_IMN_FLG5_INT171FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,11))) +#define TSB_IMN_FLG5_INT172FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,12))) +#define TSB_IMN_FLG5_INT173FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,13))) +#define TSB_IMN_FLG5_INT174FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,14))) +#define TSB_IMN_FLG5_INT175FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,15))) +#define TSB_IMN_FLG5_INT176FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,16))) +#define TSB_IMN_FLG5_INT177FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,17))) +#define TSB_IMN_FLG5_INT178FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,18))) +#define TSB_IMN_FLG5_INT179FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,19))) +#define TSB_IMN_FLG5_INT180FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,20))) +#define TSB_IMN_FLG5_INT181FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,21))) +#define TSB_IMN_FLG5_INT182FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,22))) +#define TSB_IMN_FLG5_INT183FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,23))) +#define TSB_IMN_FLG5_INT184FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,24))) +#define TSB_IMN_FLG5_INT185FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,25))) +#define TSB_IMN_FLG5_INT186FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,26))) +#define TSB_IMN_FLG5_INT187FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,27))) +#define TSB_IMN_FLG5_INT188FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,28))) +#define TSB_IMN_FLG5_INT189FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,29))) +#define TSB_IMN_FLG5_INT190FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,30))) +#define TSB_IMN_FLG5_INT191FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,31))) +#define TSB_IMN_FLG6_INT192FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,0))) +#define TSB_IMN_FLG6_INT193FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,1))) +#define TSB_IMN_FLG6_INT194FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,2))) +#define TSB_IMN_FLG6_INT195FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,3))) +#define TSB_IMN_FLG6_INT196FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,4))) +#define TSB_IMN_FLG6_INT197FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,5))) +#define TSB_IMN_FLG6_INT198FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,6))) +#define TSB_IMN_FLG6_INT199FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,7))) +#define TSB_IMN_FLG6_INT200FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,8))) +#define TSB_IMN_FLG6_INT201FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,9))) +#define TSB_IMN_FLG6_INT202FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,10))) +#define TSB_IMN_FLG6_INT203FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,11))) +#define TSB_IMN_FLG6_INT204FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,12))) +#define TSB_IMN_FLG6_INT205FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,13))) +#define TSB_IMN_FLG6_INT206FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,14))) +#define TSB_IMN_FLG6_INT207FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,15))) +#define TSB_IMN_FLG6_INT208FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,16))) +#define TSB_IMN_FLG6_INT209FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,17))) +#define TSB_IMN_FLG6_INT210FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,18))) +#define TSB_IMN_FLG6_INT211FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,19))) +#define TSB_IMN_FLG6_INT212FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,20))) +#define TSB_IMN_FLG6_INT213FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,21))) +#define TSB_IMN_FLG6_INT214FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,22))) +#define TSB_IMN_FLG6_INT215FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,23))) +#define TSB_IMN_FLG6_INT216FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,24))) +#define TSB_IMN_FLG6_INT217FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,25))) +#define TSB_IMN_FLG6_INT218FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,26))) +#define TSB_IMN_FLG6_INT219FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,27))) +#define TSB_IMN_FLG6_INT220FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,28))) +#define TSB_IMN_FLG6_INT221FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,29))) +#define TSB_IMN_FLG6_INT222FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,30))) +#define TSB_IMN_FLG6_INT223FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG6,31))) +#define TSB_IMN_FLG7_INT224FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,0))) +#define TSB_IMN_FLG7_INT225FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,1))) +#define TSB_IMN_FLG7_INT226FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,2))) +#define TSB_IMN_FLG7_INT227FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,3))) +#define TSB_IMN_FLG7_INT228FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,4))) +#define TSB_IMN_FLG7_INT229FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,5))) +#define TSB_IMN_FLG7_INT230FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,6))) +#define TSB_IMN_FLG7_INT231FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,7))) +#define TSB_IMN_FLG7_INT232FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,8))) +#define TSB_IMN_FLG7_INT233FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,9))) +#define TSB_IMN_FLG7_INT234FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,10))) +#define TSB_IMN_FLG7_INT235FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,11))) +#define TSB_IMN_FLG7_INT236FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,12))) +#define TSB_IMN_FLG7_INT237FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,13))) +#define TSB_IMN_FLG7_INT238FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,14))) +#define TSB_IMN_FLG7_INT239FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,15))) +#define TSB_IMN_FLG7_INT240FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,16))) +#define TSB_IMN_FLG7_INT241FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,17))) +#define TSB_IMN_FLG7_INT242FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,18))) +#define TSB_IMN_FLG7_INT243FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,19))) +#define TSB_IMN_FLG7_INT244FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,20))) +#define TSB_IMN_FLG7_INT245FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,21))) +#define TSB_IMN_FLG7_INT246FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,22))) +#define TSB_IMN_FLG7_INT247FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,23))) +#define TSB_IMN_FLG7_INT248FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,24))) +#define TSB_IMN_FLG7_INT249FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,25))) +#define TSB_IMN_FLG7_INT250FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,26))) +#define TSB_IMN_FLG7_INT251FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,27))) +#define TSB_IMN_FLG7_INT252FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,28))) +#define TSB_IMN_FLG7_INT253FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,29))) +#define TSB_IMN_FLG7_INT254FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,30))) +#define TSB_IMN_FLG7_INT255FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG7,31))) + + +/* DNF */ +#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) +#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) +#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) +#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) +#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) +#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) +#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) +#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) +#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) +#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) +#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) +#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) + +#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) +#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) +#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) +#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) +#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) +#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) +#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) +#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) +#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) +#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) +#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) +#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) +#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) +#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) +#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) +#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) + + +/* Watchdog Timer (SIWDT) */ +#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) +#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) +#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) +#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) + + +/* NBDIF */ +#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0))) + + +/* Malti Porpose Direct Memory Accsess(MDMA) */ +#define TSB_MDMAA_XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,16))) +#define TSB_MDMAA_XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->XFTYP,24))) +#define TSB_MDMAA_DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->DSNUM,8))) +#define TSB_MDMAA_C00XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,16))) +#define TSB_MDMAA_C00XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00XFTYP,24))) +#define TSB_MDMAA_C00DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C00DSNUM,8))) +#define TSB_MDMAA_C01XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,16))) +#define TSB_MDMAA_C01XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01XFTYP,24))) +#define TSB_MDMAA_C01DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C01DSNUM,8))) +#define TSB_MDMAA_C02XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,16))) +#define TSB_MDMAA_C02XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02XFTYP,24))) +#define TSB_MDMAA_C02DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C02DSNUM,8))) +#define TSB_MDMAA_C03XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,16))) +#define TSB_MDMAA_C03XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03XFTYP,24))) +#define TSB_MDMAA_C03DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C03DSNUM,8))) +#define TSB_MDMAA_C04XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,16))) +#define TSB_MDMAA_C04XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04XFTYP,24))) +#define TSB_MDMAA_C04DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C04DSNUM,8))) +#define TSB_MDMAA_C05XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,16))) +#define TSB_MDMAA_C05XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05XFTYP,24))) +#define TSB_MDMAA_C05DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C05DSNUM,8))) +#define TSB_MDMAA_C06XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,16))) +#define TSB_MDMAA_C06XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06XFTYP,24))) +#define TSB_MDMAA_C06DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C06DSNUM,8))) +#define TSB_MDMAA_C07XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,16))) +#define TSB_MDMAA_C07XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07XFTYP,24))) +#define TSB_MDMAA_C07DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C07DSNUM,8))) +#define TSB_MDMAA_C08XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,16))) +#define TSB_MDMAA_C08XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08XFTYP,24))) +#define TSB_MDMAA_C08DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C08DSNUM,8))) +#define TSB_MDMAA_C09XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,16))) +#define TSB_MDMAA_C09XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09XFTYP,24))) +#define TSB_MDMAA_C09DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C09DSNUM,8))) +#define TSB_MDMAA_C10XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,16))) +#define TSB_MDMAA_C10XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10XFTYP,24))) +#define TSB_MDMAA_C10DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C10DSNUM,8))) +#define TSB_MDMAA_C11XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,16))) +#define TSB_MDMAA_C11XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11XFTYP,24))) +#define TSB_MDMAA_C11DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C11DSNUM,8))) +#define TSB_MDMAA_C12XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,16))) +#define TSB_MDMAA_C12XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12XFTYP,24))) +#define TSB_MDMAA_C12DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C12DSNUM,8))) +#define TSB_MDMAA_C13XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,16))) +#define TSB_MDMAA_C13XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13XFTYP,24))) +#define TSB_MDMAA_C13DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C13DSNUM,8))) +#define TSB_MDMAA_C14XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,16))) +#define TSB_MDMAA_C14XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14XFTYP,24))) +#define TSB_MDMAA_C14DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C14DSNUM,8))) +#define TSB_MDMAA_C15XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,16))) +#define TSB_MDMAA_C15XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15XFTYP,24))) +#define TSB_MDMAA_C15DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C15DSNUM,8))) +#define TSB_MDMAA_C16XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,16))) +#define TSB_MDMAA_C16XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16XFTYP,24))) +#define TSB_MDMAA_C16DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C16DSNUM,8))) +#define TSB_MDMAA_C17XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,16))) +#define TSB_MDMAA_C17XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17XFTYP,24))) +#define TSB_MDMAA_C17DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C17DSNUM,8))) +#define TSB_MDMAA_C18XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,16))) +#define TSB_MDMAA_C18XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18XFTYP,24))) +#define TSB_MDMAA_C18DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C18DSNUM,8))) +#define TSB_MDMAA_C19XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,16))) +#define TSB_MDMAA_C19XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19XFTYP,24))) +#define TSB_MDMAA_C19DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C19DSNUM,8))) +#define TSB_MDMAA_C20XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,16))) +#define TSB_MDMAA_C20XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20XFTYP,24))) +#define TSB_MDMAA_C20DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C20DSNUM,8))) +#define TSB_MDMAA_C21XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,16))) +#define TSB_MDMAA_C21XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21XFTYP,24))) +#define TSB_MDMAA_C21DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C21DSNUM,8))) +#define TSB_MDMAA_C22XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,16))) +#define TSB_MDMAA_C22XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22XFTYP,24))) +#define TSB_MDMAA_C22DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C22DSNUM,8))) +#define TSB_MDMAA_C23XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,16))) +#define TSB_MDMAA_C23XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23XFTYP,24))) +#define TSB_MDMAA_C23DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C23DSNUM,8))) +#define TSB_MDMAA_C24XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,16))) +#define TSB_MDMAA_C24XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24XFTYP,24))) +#define TSB_MDMAA_C24DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C24DSNUM,8))) +#define TSB_MDMAA_C25XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,16))) +#define TSB_MDMAA_C25XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25XFTYP,24))) +#define TSB_MDMAA_C25DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C25DSNUM,8))) +#define TSB_MDMAA_C26XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,16))) +#define TSB_MDMAA_C26XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26XFTYP,24))) +#define TSB_MDMAA_C26DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C26DSNUM,8))) +#define TSB_MDMAA_C27XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,16))) +#define TSB_MDMAA_C27XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27XFTYP,24))) +#define TSB_MDMAA_C27DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C27DSNUM,8))) +#define TSB_MDMAA_C28XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,16))) +#define TSB_MDMAA_C28XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28XFTYP,24))) +#define TSB_MDMAA_C28DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C28DSNUM,8))) +#define TSB_MDMAA_C29XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,16))) +#define TSB_MDMAA_C29XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29XFTYP,24))) +#define TSB_MDMAA_C29DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C29DSNUM,8))) +#define TSB_MDMAA_C30XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,16))) +#define TSB_MDMAA_C30XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30XFTYP,24))) +#define TSB_MDMAA_C30DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C30DSNUM,8))) +#define TSB_MDMAA_C31XFTYP_UMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,16))) +#define TSB_MDMAA_C31XFTYP_DMODE (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31XFTYP,24))) +#define TSB_MDMAA_C31DSNUM_DSINF (*((__I uint32_t *)BITBAND_PERI(&TSB_MDMAA->C31DSNUM,8))) +#define TSB_MDMAA_MSK_MSK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,0))) +#define TSB_MDMAA_MSK_MSK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,1))) +#define TSB_MDMAA_MSK_MSK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,2))) +#define TSB_MDMAA_MSK_MSK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,3))) +#define TSB_MDMAA_MSK_MSK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,4))) +#define TSB_MDMAA_MSK_MSK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,5))) +#define TSB_MDMAA_MSK_MSK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,6))) +#define TSB_MDMAA_MSK_MSK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,7))) +#define TSB_MDMAA_MSK_MSK8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,8))) +#define TSB_MDMAA_MSK_MSK9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,9))) +#define TSB_MDMAA_MSK_MSK10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,10))) +#define TSB_MDMAA_MSK_MSK11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,11))) +#define TSB_MDMAA_MSK_MSK12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,12))) +#define TSB_MDMAA_MSK_MSK13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,13))) +#define TSB_MDMAA_MSK_MSK14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,14))) +#define TSB_MDMAA_MSK_MSK15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,15))) +#define TSB_MDMAA_MSK_MSK16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,16))) +#define TSB_MDMAA_MSK_MSK17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,17))) +#define TSB_MDMAA_MSK_MSK18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,18))) +#define TSB_MDMAA_MSK_MSK19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,19))) +#define TSB_MDMAA_MSK_MSK20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,20))) +#define TSB_MDMAA_MSK_MSK21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,21))) +#define TSB_MDMAA_MSK_MSK22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,22))) +#define TSB_MDMAA_MSK_MSK23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,23))) +#define TSB_MDMAA_MSK_MSK24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,24))) +#define TSB_MDMAA_MSK_MSK25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,25))) +#define TSB_MDMAA_MSK_MSK26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,26))) +#define TSB_MDMAA_MSK_MSK27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,27))) +#define TSB_MDMAA_MSK_MSK28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,28))) +#define TSB_MDMAA_MSK_MSK29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,29))) +#define TSB_MDMAA_MSK_MSK30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,30))) +#define TSB_MDMAA_MSK_MSK31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_MDMAA->MSK,31))) + + +/* ARM Prime Cell PL011 */ +#define TSB_FURT0_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,8))) +#define TSB_FURT0_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,9))) +#define TSB_FURT0_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,10))) +#define TSB_FURT0_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->DR,11))) +#define TSB_FURT0_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,0))) +#define TSB_FURT0_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,1))) +#define TSB_FURT0_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,2))) +#define TSB_FURT0_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RSR,3))) +#define TSB_FURT0_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,0))) +#define TSB_FURT0_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,3))) +#define TSB_FURT0_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,4))) +#define TSB_FURT0_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,5))) +#define TSB_FURT0_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,6))) +#define TSB_FURT0_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->FR,7))) +#define TSB_FURT0_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,0))) +#define TSB_FURT0_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,1))) +#define TSB_FURT0_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,2))) +#define TSB_FURT0_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,3))) +#define TSB_FURT0_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,4))) +#define TSB_FURT0_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->LCR_H,7))) +#define TSB_FURT0_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,0))) +#define TSB_FURT0_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,1))) +#define TSB_FURT0_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,2))) +#define TSB_FURT0_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,8))) +#define TSB_FURT0_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,9))) +#define TSB_FURT0_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,14))) +#define TSB_FURT0_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->CR,15))) +#define TSB_FURT0_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,4))) +#define TSB_FURT0_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,5))) +#define TSB_FURT0_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,6))) +#define TSB_FURT0_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,7))) +#define TSB_FURT0_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,8))) +#define TSB_FURT0_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,9))) +#define TSB_FURT0_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->IMSC,10))) +#define TSB_FURT0_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,4))) +#define TSB_FURT0_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,5))) +#define TSB_FURT0_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,6))) +#define TSB_FURT0_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,7))) +#define TSB_FURT0_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,8))) +#define TSB_FURT0_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,9))) +#define TSB_FURT0_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->RIS,10))) +#define TSB_FURT0_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,4))) +#define TSB_FURT0_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,5))) +#define TSB_FURT0_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,6))) +#define TSB_FURT0_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,7))) +#define TSB_FURT0_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,8))) +#define TSB_FURT0_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,9))) +#define TSB_FURT0_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT0->MIS,10))) +#define TSB_FURT0_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,4))) +#define TSB_FURT0_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,5))) +#define TSB_FURT0_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,6))) +#define TSB_FURT0_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,7))) +#define TSB_FURT0_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,8))) +#define TSB_FURT0_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,9))) +#define TSB_FURT0_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT0->ICR,10))) +#define TSB_FURT0_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,0))) +#define TSB_FURT0_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,1))) +#define TSB_FURT0_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT0->DMACR,2))) + +#define TSB_FURT1_DR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,8))) +#define TSB_FURT1_DR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,9))) +#define TSB_FURT1_DR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,10))) +#define TSB_FURT1_DR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->DR,11))) +#define TSB_FURT1_RSR_FE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,0))) +#define TSB_FURT1_RSR_PE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,1))) +#define TSB_FURT1_RSR_BE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,2))) +#define TSB_FURT1_RSR_OE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RSR,3))) +#define TSB_FURT1_FR_CTS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,0))) +#define TSB_FURT1_FR_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,3))) +#define TSB_FURT1_FR_RXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,4))) +#define TSB_FURT1_FR_TXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,5))) +#define TSB_FURT1_FR_RXFF (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,6))) +#define TSB_FURT1_FR_TXFE (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->FR,7))) +#define TSB_FURT1_LCR_H_BRK (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,0))) +#define TSB_FURT1_LCR_H_PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,1))) +#define TSB_FURT1_LCR_H_EPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,2))) +#define TSB_FURT1_LCR_H_STP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,3))) +#define TSB_FURT1_LCR_H_FEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,4))) +#define TSB_FURT1_LCR_H_SPS (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->LCR_H,7))) +#define TSB_FURT1_CR_UARTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,0))) +#define TSB_FURT1_CR_SIREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,1))) +#define TSB_FURT1_CR_SIRLP (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,2))) +#define TSB_FURT1_CR_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,8))) +#define TSB_FURT1_CR_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,9))) +#define TSB_FURT1_CR_RTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,14))) +#define TSB_FURT1_CR_CTSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->CR,15))) +#define TSB_FURT1_IMSC_RXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,4))) +#define TSB_FURT1_IMSC_TXIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,5))) +#define TSB_FURT1_IMSC_RTIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,6))) +#define TSB_FURT1_IMSC_FEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,7))) +#define TSB_FURT1_IMSC_PEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,8))) +#define TSB_FURT1_IMSC_BEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,9))) +#define TSB_FURT1_IMSC_OEIM (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->IMSC,10))) +#define TSB_FURT1_RIS_RXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,4))) +#define TSB_FURT1_RIS_TXRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,5))) +#define TSB_FURT1_RIS_RTRIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,6))) +#define TSB_FURT1_RIS_FERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,7))) +#define TSB_FURT1_RIS_PERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,8))) +#define TSB_FURT1_RIS_BERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,9))) +#define TSB_FURT1_RIS_OERIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->RIS,10))) +#define TSB_FURT1_MIS_RXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,4))) +#define TSB_FURT1_MIS_TXMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,5))) +#define TSB_FURT1_MIS_RTMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,6))) +#define TSB_FURT1_MIS_FEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,7))) +#define TSB_FURT1_MIS_PEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,8))) +#define TSB_FURT1_MIS_BEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,9))) +#define TSB_FURT1_MIS_OEMIS (*((__I uint32_t *)BITBAND_PERI(&TSB_FURT1->MIS,10))) +#define TSB_FURT1_ICR_RXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,4))) +#define TSB_FURT1_ICR_TXIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,5))) +#define TSB_FURT1_ICR_RTIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,6))) +#define TSB_FURT1_ICR_FEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,7))) +#define TSB_FURT1_ICR_PEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,8))) +#define TSB_FURT1_ICR_BEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,9))) +#define TSB_FURT1_ICR_OEIC (*((__O uint32_t *)BITBAND_PERI(&TSB_FURT1->ICR,10))) +#define TSB_FURT1_DMACR_RXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,0))) +#define TSB_FURT1_DMACR_TXDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,1))) +#define TSB_FURT1_DMACR_DMAONERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_FURT1->DMACR,2))) + + +/* ADC */ +#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) +#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) +#define TSB_ADA_CR0_HPSGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,2))) +#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) +#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) +#define TSB_ADA_CR1_HPTRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,1))) +#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) +#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) +#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) +#define TSB_ADA_CR1_HPDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,7))) +#define TSB_ADA_ST_HPF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) +#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) +#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) +#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) +#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) +#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) +#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) +#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) +#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) +#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) +#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) +#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) +#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) +#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) +#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) +#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) +#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) +#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) +#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) +#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) +#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) +#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) +#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) +#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) +#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) +#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) +#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) +#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) +#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) +#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) +#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) +#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) +#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) +#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) +#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) +#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) +#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) +#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) +#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) +#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) +#define TSB_ADA_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) +#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) +#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) +#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) +#define TSB_ADA_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) +#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) +#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) +#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) +#define TSB_ADA_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) +#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) +#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) +#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) +#define TSB_ADA_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) +#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) +#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) +#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) +#define TSB_ADA_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) +#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) +#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) +#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) +#define TSB_ADA_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) +#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) +#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) +#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) +#define TSB_ADA_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) +#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) +#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) +#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) +#define TSB_ADA_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) +#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) +#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) +#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) +#define TSB_ADA_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) +#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) +#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) +#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) +#define TSB_ADA_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) +#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) +#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) +#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) +#define TSB_ADA_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) +#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) +#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) +#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) +#define TSB_ADA_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) +#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) +#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) +#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) +#define TSB_ADA_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) +#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) +#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) +#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) +#define TSB_ADA_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) +#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) +#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) +#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) +#define TSB_ADA_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) +#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) +#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) +#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) +#define TSB_ADA_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) +#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) +#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) +#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) +#define TSB_ADA_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) +#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) +#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) +#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) +#define TSB_ADA_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) +#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) +#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) +#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) +#define TSB_ADA_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) +#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) +#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) +#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) +#define TSB_ADA_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) +#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) +#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) +#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) +#define TSB_ADA_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) +#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) +#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) +#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) +#define TSB_ADA_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) +#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) +#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) +#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) +#define TSB_ADA_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) +#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) +#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) +#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) +#define TSB_ADA_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) + + +/* Digital analog converter (DAC) */ +#define TSB_DA0_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA0->CR,0))) + +#define TSB_DA1_CR_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_DA1->CR,0))) + + +/* 16-bit Timer/Event Counter (TB) */ +#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) +#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) +#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) +#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) +#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) +#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) +#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) +#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) +#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) +#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) +#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) +#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) +#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) +#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) +#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) +#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) +#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) +#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) +#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) +#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) +#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) +#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) +#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) +#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) +#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) +#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) +#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) +#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) +#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) +#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) +#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) +#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) +#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) +#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) +#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) +#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) +#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) +#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) +#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) +#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) +#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) +#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) +#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) +#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) +#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) +#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) +#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) +#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) +#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) +#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) +#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) +#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) +#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) +#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) + +#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) +#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) +#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) +#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) +#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) +#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) +#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) +#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) +#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) +#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) +#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) +#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) +#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) +#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) +#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) +#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) +#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) +#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) +#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) +#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) +#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) +#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) +#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) +#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) +#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) +#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) +#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) +#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) +#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) +#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) +#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) +#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) +#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) +#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) +#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) +#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) +#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) +#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) +#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) +#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) +#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) +#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) +#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) +#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) +#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) +#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) +#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) +#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) +#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) +#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) +#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) +#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) +#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) +#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) + +#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) +#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) +#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) +#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) +#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) +#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) +#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) +#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) +#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) +#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) +#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) +#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) +#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) +#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) +#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) +#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) +#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) +#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) +#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) +#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) +#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) +#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) +#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) +#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) +#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) +#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) +#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) +#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) +#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) +#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) +#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) +#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) +#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) +#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) +#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) +#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) +#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) +#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) +#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) +#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) +#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) +#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) +#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) +#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) +#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) +#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) +#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) +#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) +#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) +#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) +#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) +#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) +#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) +#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) + +#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) +#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) +#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) +#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) +#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) +#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) +#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) +#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) +#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) +#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) +#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) +#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) +#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) +#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) +#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) +#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) +#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) +#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) +#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) +#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) +#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) +#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) +#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) +#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) +#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) +#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) +#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) +#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) +#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) +#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) +#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) +#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) +#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) +#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) +#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) +#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) +#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) +#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) +#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) +#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) +#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) +#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) +#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) +#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) +#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) +#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) +#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) +#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) +#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) +#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) +#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) +#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) +#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) +#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) + +#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) +#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) +#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) +#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) +#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) +#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) +#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) +#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) +#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) +#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) +#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) +#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) +#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) +#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) +#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) +#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) +#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) +#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) +#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) +#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) +#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) +#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) +#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) +#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) +#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) +#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) +#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) +#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) +#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) +#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) +#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) +#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) +#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) +#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) +#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) +#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) +#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) +#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) +#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) +#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) +#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) +#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) +#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) +#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) +#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) +#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) +#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) +#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) +#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) +#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) +#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) +#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) +#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) +#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) + +#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) +#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) +#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) +#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) +#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) +#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) +#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) +#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) +#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) +#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) +#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) +#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) +#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) +#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) +#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) +#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) +#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) +#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) +#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) +#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) +#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) +#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) +#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) +#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) +#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) +#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) +#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) +#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) +#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) +#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) +#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) +#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) +#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) +#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) +#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) +#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) +#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) +#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) +#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) +#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) +#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) +#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) +#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) +#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) +#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) +#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) +#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) +#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) +#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) +#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) +#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) +#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) +#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) +#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) + +#define TSB_T32A6_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,0))) +#define TSB_T32A6_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->MOD,1))) +#define TSB_T32A6_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,0))) +#define TSB_T32A6_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,1))) +#define TSB_T32A6_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,2))) +#define TSB_T32A6_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNA,4))) +#define TSB_T32A6_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRA,20))) +#define TSB_T32A6_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,0))) +#define TSB_T32A6_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,1))) +#define TSB_T32A6_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,2))) +#define TSB_T32A6_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STA,3))) +#define TSB_T32A6_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,0))) +#define TSB_T32A6_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,1))) +#define TSB_T32A6_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,2))) +#define TSB_T32A6_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMA,3))) +#define TSB_T32A6_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,0))) +#define TSB_T32A6_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,1))) +#define TSB_T32A6_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAA,2))) +#define TSB_T32A6_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,0))) +#define TSB_T32A6_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,1))) +#define TSB_T32A6_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,2))) +#define TSB_T32A6_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNB,4))) +#define TSB_T32A6_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRB,20))) +#define TSB_T32A6_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,0))) +#define TSB_T32A6_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,1))) +#define TSB_T32A6_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,2))) +#define TSB_T32A6_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STB,3))) +#define TSB_T32A6_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,0))) +#define TSB_T32A6_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,1))) +#define TSB_T32A6_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,2))) +#define TSB_T32A6_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMB,3))) +#define TSB_T32A6_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,0))) +#define TSB_T32A6_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,1))) +#define TSB_T32A6_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAB,2))) +#define TSB_T32A6_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,0))) +#define TSB_T32A6_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,1))) +#define TSB_T32A6_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,2))) +#define TSB_T32A6_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A6->RUNC,4))) +#define TSB_T32A6_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->CRC,20))) +#define TSB_T32A6_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,0))) +#define TSB_T32A6_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,1))) +#define TSB_T32A6_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,2))) +#define TSB_T32A6_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,3))) +#define TSB_T32A6_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->STC,4))) +#define TSB_T32A6_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,0))) +#define TSB_T32A6_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,1))) +#define TSB_T32A6_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,2))) +#define TSB_T32A6_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,3))) +#define TSB_T32A6_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->IMC,4))) +#define TSB_T32A6_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,0))) +#define TSB_T32A6_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,1))) +#define TSB_T32A6_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->DMAC,2))) +#define TSB_T32A6_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,0))) +#define TSB_T32A6_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A6->PLSCR,1))) + +#define TSB_T32A7_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,0))) +#define TSB_T32A7_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->MOD,1))) +#define TSB_T32A7_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,0))) +#define TSB_T32A7_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,1))) +#define TSB_T32A7_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,2))) +#define TSB_T32A7_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNA,4))) +#define TSB_T32A7_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRA,20))) +#define TSB_T32A7_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,0))) +#define TSB_T32A7_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,1))) +#define TSB_T32A7_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,2))) +#define TSB_T32A7_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STA,3))) +#define TSB_T32A7_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,0))) +#define TSB_T32A7_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,1))) +#define TSB_T32A7_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,2))) +#define TSB_T32A7_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMA,3))) +#define TSB_T32A7_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,0))) +#define TSB_T32A7_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,1))) +#define TSB_T32A7_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAA,2))) +#define TSB_T32A7_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,0))) +#define TSB_T32A7_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,1))) +#define TSB_T32A7_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,2))) +#define TSB_T32A7_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNB,4))) +#define TSB_T32A7_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRB,20))) +#define TSB_T32A7_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,0))) +#define TSB_T32A7_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,1))) +#define TSB_T32A7_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,2))) +#define TSB_T32A7_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STB,3))) +#define TSB_T32A7_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,0))) +#define TSB_T32A7_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,1))) +#define TSB_T32A7_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,2))) +#define TSB_T32A7_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMB,3))) +#define TSB_T32A7_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,0))) +#define TSB_T32A7_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,1))) +#define TSB_T32A7_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAB,2))) +#define TSB_T32A7_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,0))) +#define TSB_T32A7_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,1))) +#define TSB_T32A7_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,2))) +#define TSB_T32A7_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A7->RUNC,4))) +#define TSB_T32A7_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->CRC,20))) +#define TSB_T32A7_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,0))) +#define TSB_T32A7_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,1))) +#define TSB_T32A7_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,2))) +#define TSB_T32A7_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,3))) +#define TSB_T32A7_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->STC,4))) +#define TSB_T32A7_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,0))) +#define TSB_T32A7_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,1))) +#define TSB_T32A7_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,2))) +#define TSB_T32A7_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,3))) +#define TSB_T32A7_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->IMC,4))) +#define TSB_T32A7_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,0))) +#define TSB_T32A7_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,1))) +#define TSB_T32A7_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->DMAC,2))) +#define TSB_T32A7_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,0))) +#define TSB_T32A7_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A7->PLSCR,1))) + +#define TSB_T32A8_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,0))) +#define TSB_T32A8_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->MOD,1))) +#define TSB_T32A8_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,0))) +#define TSB_T32A8_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,1))) +#define TSB_T32A8_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,2))) +#define TSB_T32A8_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNA,4))) +#define TSB_T32A8_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRA,20))) +#define TSB_T32A8_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,0))) +#define TSB_T32A8_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,1))) +#define TSB_T32A8_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,2))) +#define TSB_T32A8_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STA,3))) +#define TSB_T32A8_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,0))) +#define TSB_T32A8_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,1))) +#define TSB_T32A8_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,2))) +#define TSB_T32A8_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMA,3))) +#define TSB_T32A8_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,0))) +#define TSB_T32A8_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,1))) +#define TSB_T32A8_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAA,2))) +#define TSB_T32A8_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,0))) +#define TSB_T32A8_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,1))) +#define TSB_T32A8_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,2))) +#define TSB_T32A8_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNB,4))) +#define TSB_T32A8_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRB,20))) +#define TSB_T32A8_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,0))) +#define TSB_T32A8_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,1))) +#define TSB_T32A8_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,2))) +#define TSB_T32A8_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STB,3))) +#define TSB_T32A8_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,0))) +#define TSB_T32A8_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,1))) +#define TSB_T32A8_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,2))) +#define TSB_T32A8_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMB,3))) +#define TSB_T32A8_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,0))) +#define TSB_T32A8_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,1))) +#define TSB_T32A8_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAB,2))) +#define TSB_T32A8_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,0))) +#define TSB_T32A8_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,1))) +#define TSB_T32A8_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,2))) +#define TSB_T32A8_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A8->RUNC,4))) +#define TSB_T32A8_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->CRC,20))) +#define TSB_T32A8_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,0))) +#define TSB_T32A8_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,1))) +#define TSB_T32A8_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,2))) +#define TSB_T32A8_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,3))) +#define TSB_T32A8_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->STC,4))) +#define TSB_T32A8_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,0))) +#define TSB_T32A8_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,1))) +#define TSB_T32A8_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,2))) +#define TSB_T32A8_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,3))) +#define TSB_T32A8_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->IMC,4))) +#define TSB_T32A8_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,0))) +#define TSB_T32A8_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,1))) +#define TSB_T32A8_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->DMAC,2))) +#define TSB_T32A8_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,0))) +#define TSB_T32A8_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A8->PLSCR,1))) + +#define TSB_T32A9_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,0))) +#define TSB_T32A9_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->MOD,1))) +#define TSB_T32A9_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,0))) +#define TSB_T32A9_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,1))) +#define TSB_T32A9_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,2))) +#define TSB_T32A9_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNA,4))) +#define TSB_T32A9_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRA,20))) +#define TSB_T32A9_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,0))) +#define TSB_T32A9_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,1))) +#define TSB_T32A9_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,2))) +#define TSB_T32A9_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STA,3))) +#define TSB_T32A9_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,0))) +#define TSB_T32A9_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,1))) +#define TSB_T32A9_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,2))) +#define TSB_T32A9_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMA,3))) +#define TSB_T32A9_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,0))) +#define TSB_T32A9_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,1))) +#define TSB_T32A9_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAA,2))) +#define TSB_T32A9_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,0))) +#define TSB_T32A9_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,1))) +#define TSB_T32A9_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,2))) +#define TSB_T32A9_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNB,4))) +#define TSB_T32A9_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRB,20))) +#define TSB_T32A9_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,0))) +#define TSB_T32A9_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,1))) +#define TSB_T32A9_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,2))) +#define TSB_T32A9_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STB,3))) +#define TSB_T32A9_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,0))) +#define TSB_T32A9_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,1))) +#define TSB_T32A9_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,2))) +#define TSB_T32A9_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMB,3))) +#define TSB_T32A9_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,0))) +#define TSB_T32A9_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,1))) +#define TSB_T32A9_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAB,2))) +#define TSB_T32A9_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,0))) +#define TSB_T32A9_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,1))) +#define TSB_T32A9_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,2))) +#define TSB_T32A9_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A9->RUNC,4))) +#define TSB_T32A9_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->CRC,20))) +#define TSB_T32A9_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,0))) +#define TSB_T32A9_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,1))) +#define TSB_T32A9_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,2))) +#define TSB_T32A9_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,3))) +#define TSB_T32A9_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->STC,4))) +#define TSB_T32A9_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,0))) +#define TSB_T32A9_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,1))) +#define TSB_T32A9_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,2))) +#define TSB_T32A9_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,3))) +#define TSB_T32A9_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->IMC,4))) +#define TSB_T32A9_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,0))) +#define TSB_T32A9_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,1))) +#define TSB_T32A9_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->DMAC,2))) +#define TSB_T32A9_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,0))) +#define TSB_T32A9_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A9->PLSCR,1))) + +#define TSB_T32A10_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,0))) +#define TSB_T32A10_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->MOD,1))) +#define TSB_T32A10_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,0))) +#define TSB_T32A10_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,1))) +#define TSB_T32A10_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,2))) +#define TSB_T32A10_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNA,4))) +#define TSB_T32A10_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRA,20))) +#define TSB_T32A10_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,0))) +#define TSB_T32A10_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,1))) +#define TSB_T32A10_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,2))) +#define TSB_T32A10_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STA,3))) +#define TSB_T32A10_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,0))) +#define TSB_T32A10_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,1))) +#define TSB_T32A10_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,2))) +#define TSB_T32A10_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMA,3))) +#define TSB_T32A10_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,0))) +#define TSB_T32A10_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,1))) +#define TSB_T32A10_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAA,2))) +#define TSB_T32A10_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,0))) +#define TSB_T32A10_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,1))) +#define TSB_T32A10_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,2))) +#define TSB_T32A10_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNB,4))) +#define TSB_T32A10_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRB,20))) +#define TSB_T32A10_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,0))) +#define TSB_T32A10_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,1))) +#define TSB_T32A10_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,2))) +#define TSB_T32A10_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STB,3))) +#define TSB_T32A10_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,0))) +#define TSB_T32A10_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,1))) +#define TSB_T32A10_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,2))) +#define TSB_T32A10_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMB,3))) +#define TSB_T32A10_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,0))) +#define TSB_T32A10_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,1))) +#define TSB_T32A10_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAB,2))) +#define TSB_T32A10_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,0))) +#define TSB_T32A10_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,1))) +#define TSB_T32A10_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,2))) +#define TSB_T32A10_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A10->RUNC,4))) +#define TSB_T32A10_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->CRC,20))) +#define TSB_T32A10_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,0))) +#define TSB_T32A10_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,1))) +#define TSB_T32A10_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,2))) +#define TSB_T32A10_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,3))) +#define TSB_T32A10_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->STC,4))) +#define TSB_T32A10_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,0))) +#define TSB_T32A10_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,1))) +#define TSB_T32A10_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,2))) +#define TSB_T32A10_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,3))) +#define TSB_T32A10_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->IMC,4))) +#define TSB_T32A10_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,0))) +#define TSB_T32A10_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,1))) +#define TSB_T32A10_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->DMAC,2))) +#define TSB_T32A10_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,0))) +#define TSB_T32A10_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A10->PLSCR,1))) + +#define TSB_T32A11_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,0))) +#define TSB_T32A11_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->MOD,1))) +#define TSB_T32A11_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,0))) +#define TSB_T32A11_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,1))) +#define TSB_T32A11_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,2))) +#define TSB_T32A11_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNA,4))) +#define TSB_T32A11_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRA,20))) +#define TSB_T32A11_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,0))) +#define TSB_T32A11_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,1))) +#define TSB_T32A11_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,2))) +#define TSB_T32A11_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STA,3))) +#define TSB_T32A11_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,0))) +#define TSB_T32A11_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,1))) +#define TSB_T32A11_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,2))) +#define TSB_T32A11_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMA,3))) +#define TSB_T32A11_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,0))) +#define TSB_T32A11_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,1))) +#define TSB_T32A11_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAA,2))) +#define TSB_T32A11_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,0))) +#define TSB_T32A11_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,1))) +#define TSB_T32A11_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,2))) +#define TSB_T32A11_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNB,4))) +#define TSB_T32A11_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRB,20))) +#define TSB_T32A11_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,0))) +#define TSB_T32A11_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,1))) +#define TSB_T32A11_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,2))) +#define TSB_T32A11_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STB,3))) +#define TSB_T32A11_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,0))) +#define TSB_T32A11_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,1))) +#define TSB_T32A11_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,2))) +#define TSB_T32A11_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMB,3))) +#define TSB_T32A11_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,0))) +#define TSB_T32A11_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,1))) +#define TSB_T32A11_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAB,2))) +#define TSB_T32A11_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,0))) +#define TSB_T32A11_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,1))) +#define TSB_T32A11_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,2))) +#define TSB_T32A11_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A11->RUNC,4))) +#define TSB_T32A11_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->CRC,20))) +#define TSB_T32A11_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,0))) +#define TSB_T32A11_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,1))) +#define TSB_T32A11_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,2))) +#define TSB_T32A11_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,3))) +#define TSB_T32A11_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->STC,4))) +#define TSB_T32A11_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,0))) +#define TSB_T32A11_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,1))) +#define TSB_T32A11_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,2))) +#define TSB_T32A11_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,3))) +#define TSB_T32A11_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->IMC,4))) +#define TSB_T32A11_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,0))) +#define TSB_T32A11_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,1))) +#define TSB_T32A11_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->DMAC,2))) +#define TSB_T32A11_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,0))) +#define TSB_T32A11_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A11->PLSCR,1))) + +#define TSB_T32A12_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,0))) +#define TSB_T32A12_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->MOD,1))) +#define TSB_T32A12_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,0))) +#define TSB_T32A12_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,1))) +#define TSB_T32A12_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,2))) +#define TSB_T32A12_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNA,4))) +#define TSB_T32A12_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRA,20))) +#define TSB_T32A12_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,0))) +#define TSB_T32A12_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,1))) +#define TSB_T32A12_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,2))) +#define TSB_T32A12_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STA,3))) +#define TSB_T32A12_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,0))) +#define TSB_T32A12_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,1))) +#define TSB_T32A12_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,2))) +#define TSB_T32A12_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMA,3))) +#define TSB_T32A12_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,0))) +#define TSB_T32A12_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,1))) +#define TSB_T32A12_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAA,2))) +#define TSB_T32A12_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,0))) +#define TSB_T32A12_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,1))) +#define TSB_T32A12_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,2))) +#define TSB_T32A12_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNB,4))) +#define TSB_T32A12_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRB,20))) +#define TSB_T32A12_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,0))) +#define TSB_T32A12_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,1))) +#define TSB_T32A12_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,2))) +#define TSB_T32A12_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STB,3))) +#define TSB_T32A12_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,0))) +#define TSB_T32A12_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,1))) +#define TSB_T32A12_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,2))) +#define TSB_T32A12_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMB,3))) +#define TSB_T32A12_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,0))) +#define TSB_T32A12_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,1))) +#define TSB_T32A12_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAB,2))) +#define TSB_T32A12_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,0))) +#define TSB_T32A12_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,1))) +#define TSB_T32A12_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,2))) +#define TSB_T32A12_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A12->RUNC,4))) +#define TSB_T32A12_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->CRC,20))) +#define TSB_T32A12_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,0))) +#define TSB_T32A12_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,1))) +#define TSB_T32A12_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,2))) +#define TSB_T32A12_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,3))) +#define TSB_T32A12_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->STC,4))) +#define TSB_T32A12_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,0))) +#define TSB_T32A12_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,1))) +#define TSB_T32A12_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,2))) +#define TSB_T32A12_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,3))) +#define TSB_T32A12_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->IMC,4))) +#define TSB_T32A12_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,0))) +#define TSB_T32A12_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,1))) +#define TSB_T32A12_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->DMAC,2))) +#define TSB_T32A12_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,0))) +#define TSB_T32A12_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A12->PLSCR,1))) + +#define TSB_T32A13_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,0))) +#define TSB_T32A13_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->MOD,1))) +#define TSB_T32A13_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,0))) +#define TSB_T32A13_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,1))) +#define TSB_T32A13_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,2))) +#define TSB_T32A13_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNA,4))) +#define TSB_T32A13_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRA,20))) +#define TSB_T32A13_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,0))) +#define TSB_T32A13_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,1))) +#define TSB_T32A13_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,2))) +#define TSB_T32A13_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STA,3))) +#define TSB_T32A13_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,0))) +#define TSB_T32A13_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,1))) +#define TSB_T32A13_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,2))) +#define TSB_T32A13_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMA,3))) +#define TSB_T32A13_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,0))) +#define TSB_T32A13_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,1))) +#define TSB_T32A13_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAA,2))) +#define TSB_T32A13_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,0))) +#define TSB_T32A13_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,1))) +#define TSB_T32A13_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,2))) +#define TSB_T32A13_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNB,4))) +#define TSB_T32A13_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRB,20))) +#define TSB_T32A13_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,0))) +#define TSB_T32A13_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,1))) +#define TSB_T32A13_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,2))) +#define TSB_T32A13_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STB,3))) +#define TSB_T32A13_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,0))) +#define TSB_T32A13_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,1))) +#define TSB_T32A13_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,2))) +#define TSB_T32A13_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMB,3))) +#define TSB_T32A13_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,0))) +#define TSB_T32A13_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,1))) +#define TSB_T32A13_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAB,2))) +#define TSB_T32A13_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,0))) +#define TSB_T32A13_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,1))) +#define TSB_T32A13_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,2))) +#define TSB_T32A13_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A13->RUNC,4))) +#define TSB_T32A13_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->CRC,20))) +#define TSB_T32A13_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,0))) +#define TSB_T32A13_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,1))) +#define TSB_T32A13_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,2))) +#define TSB_T32A13_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,3))) +#define TSB_T32A13_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->STC,4))) +#define TSB_T32A13_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,0))) +#define TSB_T32A13_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,1))) +#define TSB_T32A13_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,2))) +#define TSB_T32A13_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,3))) +#define TSB_T32A13_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->IMC,4))) +#define TSB_T32A13_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,0))) +#define TSB_T32A13_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,1))) +#define TSB_T32A13_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->DMAC,2))) +#define TSB_T32A13_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,0))) +#define TSB_T32A13_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A13->PLSCR,1))) + +#define TSB_T32A14_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->MOD,0))) +#define TSB_T32A14_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->MOD,1))) +#define TSB_T32A14_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,0))) +#define TSB_T32A14_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,1))) +#define TSB_T32A14_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,2))) +#define TSB_T32A14_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNA,4))) +#define TSB_T32A14_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRA,20))) +#define TSB_T32A14_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,0))) +#define TSB_T32A14_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,1))) +#define TSB_T32A14_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,2))) +#define TSB_T32A14_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STA,3))) +#define TSB_T32A14_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,0))) +#define TSB_T32A14_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,1))) +#define TSB_T32A14_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,2))) +#define TSB_T32A14_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMA,3))) +#define TSB_T32A14_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,0))) +#define TSB_T32A14_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,1))) +#define TSB_T32A14_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAA,2))) +#define TSB_T32A14_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,0))) +#define TSB_T32A14_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,1))) +#define TSB_T32A14_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,2))) +#define TSB_T32A14_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNB,4))) +#define TSB_T32A14_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRB,20))) +#define TSB_T32A14_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,0))) +#define TSB_T32A14_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,1))) +#define TSB_T32A14_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,2))) +#define TSB_T32A14_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STB,3))) +#define TSB_T32A14_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,0))) +#define TSB_T32A14_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,1))) +#define TSB_T32A14_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,2))) +#define TSB_T32A14_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMB,3))) +#define TSB_T32A14_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,0))) +#define TSB_T32A14_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,1))) +#define TSB_T32A14_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAB,2))) +#define TSB_T32A14_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,0))) +#define TSB_T32A14_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,1))) +#define TSB_T32A14_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,2))) +#define TSB_T32A14_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A14->RUNC,4))) +#define TSB_T32A14_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->CRC,20))) +#define TSB_T32A14_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,0))) +#define TSB_T32A14_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,1))) +#define TSB_T32A14_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,2))) +#define TSB_T32A14_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,3))) +#define TSB_T32A14_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->STC,4))) +#define TSB_T32A14_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,0))) +#define TSB_T32A14_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,1))) +#define TSB_T32A14_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,2))) +#define TSB_T32A14_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,3))) +#define TSB_T32A14_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->IMC,4))) +#define TSB_T32A14_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,0))) +#define TSB_T32A14_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,1))) +#define TSB_T32A14_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->DMAC,2))) +#define TSB_T32A14_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->PLSCR,0))) +#define TSB_T32A14_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A14->PLSCR,1))) + +#define TSB_T32A15_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->MOD,0))) +#define TSB_T32A15_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->MOD,1))) +#define TSB_T32A15_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,0))) +#define TSB_T32A15_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,1))) +#define TSB_T32A15_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,2))) +#define TSB_T32A15_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNA,4))) +#define TSB_T32A15_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRA,20))) +#define TSB_T32A15_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,0))) +#define TSB_T32A15_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,1))) +#define TSB_T32A15_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,2))) +#define TSB_T32A15_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STA,3))) +#define TSB_T32A15_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,0))) +#define TSB_T32A15_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,1))) +#define TSB_T32A15_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,2))) +#define TSB_T32A15_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMA,3))) +#define TSB_T32A15_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,0))) +#define TSB_T32A15_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,1))) +#define TSB_T32A15_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAA,2))) +#define TSB_T32A15_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,0))) +#define TSB_T32A15_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,1))) +#define TSB_T32A15_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,2))) +#define TSB_T32A15_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNB,4))) +#define TSB_T32A15_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRB,20))) +#define TSB_T32A15_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,0))) +#define TSB_T32A15_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,1))) +#define TSB_T32A15_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,2))) +#define TSB_T32A15_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STB,3))) +#define TSB_T32A15_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,0))) +#define TSB_T32A15_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,1))) +#define TSB_T32A15_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,2))) +#define TSB_T32A15_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMB,3))) +#define TSB_T32A15_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,0))) +#define TSB_T32A15_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,1))) +#define TSB_T32A15_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAB,2))) +#define TSB_T32A15_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,0))) +#define TSB_T32A15_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,1))) +#define TSB_T32A15_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,2))) +#define TSB_T32A15_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A15->RUNC,4))) +#define TSB_T32A15_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->CRC,20))) +#define TSB_T32A15_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,0))) +#define TSB_T32A15_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,1))) +#define TSB_T32A15_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,2))) +#define TSB_T32A15_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,3))) +#define TSB_T32A15_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->STC,4))) +#define TSB_T32A15_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,0))) +#define TSB_T32A15_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,1))) +#define TSB_T32A15_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,2))) +#define TSB_T32A15_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,3))) +#define TSB_T32A15_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->IMC,4))) +#define TSB_T32A15_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,0))) +#define TSB_T32A15_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,1))) +#define TSB_T32A15_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->DMAC,2))) +#define TSB_T32A15_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->PLSCR,0))) +#define TSB_T32A15_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A15->PLSCR,1))) + + +/* TSSI */ +#define TSB_TSSI0_CR0_RXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,6))) +#define TSB_TSSI0_CR0_RXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,7))) +#define TSB_TSSI0_CR0_TXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,14))) +#define TSB_TSSI0_CR0_TXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,15))) +#define TSB_TSSI0_CR0_SWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR0,31))) +#define TSB_TSSI0_CR1_RXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR1,2))) +#define TSB_TSSI0_CR1_TXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->CR1,10))) +#define TSB_TSSI0_RDMACR_RDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RDMACR,0))) +#define TSB_TSSI0_RSR_RBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,0))) +#define TSB_TSSI0_RSR_RFNE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,1))) +#define TSB_TSSI0_RSR_RFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,2))) +#define TSB_TSSI0_RSR_RFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,4))) +#define TSB_TSSI0_RSR_RFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RSR,5))) +#define TSB_TSSI0_RIER_RFNEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,1))) +#define TSB_TSSI0_RIER_RFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,2))) +#define TSB_TSSI0_RIER_RCMIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,3))) +#define TSB_TSSI0_RIER_RFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,4))) +#define TSB_TSSI0_RIER_RFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,5))) +#define TSB_TSSI0_RIER_RFTEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->RIER,7))) +#define TSB_TSSI0_TDMACR_TDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TDMACR,0))) +#define TSB_TSSI0_TSR_TBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,0))) +#define TSB_TSSI0_TSR_TFNF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,1))) +#define TSB_TSSI0_TSR_TFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,2))) +#define TSB_TSSI0_TSR_TFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,4))) +#define TSB_TSSI0_TSR_TFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TSR,5))) +#define TSB_TSSI0_TIER_TFNFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,1))) +#define TSB_TSSI0_TIER_TFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,2))) +#define TSB_TSSI0_TIER_TFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,4))) +#define TSB_TSSI0_TIER_TFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI0->TIER,5))) + +#define TSB_TSSI1_CR0_RXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,6))) +#define TSB_TSSI1_CR0_RXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,7))) +#define TSB_TSSI1_CR0_TXFCLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,14))) +#define TSB_TSSI1_CR0_TXSWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,15))) +#define TSB_TSSI1_CR0_SWRST (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR0,31))) +#define TSB_TSSI1_CR1_RXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR1,2))) +#define TSB_TSSI1_CR1_TXSTS (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->CR1,10))) +#define TSB_TSSI1_RDMACR_RDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RDMACR,0))) +#define TSB_TSSI1_RSR_RBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,0))) +#define TSB_TSSI1_RSR_RFNE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,1))) +#define TSB_TSSI1_RSR_RFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,2))) +#define TSB_TSSI1_RSR_RFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,4))) +#define TSB_TSSI1_RSR_RFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RSR,5))) +#define TSB_TSSI1_RIER_RFNEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,1))) +#define TSB_TSSI1_RIER_RFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,2))) +#define TSB_TSSI1_RIER_RCMIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,3))) +#define TSB_TSSI1_RIER_RFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,4))) +#define TSB_TSSI1_RIER_RFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,5))) +#define TSB_TSSI1_RIER_RFTEIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->RIER,7))) +#define TSB_TSSI1_TDMACR_TDMAE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TDMACR,0))) +#define TSB_TSSI1_TSR_TBSY (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,0))) +#define TSB_TSSI1_TSR_TFNF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,1))) +#define TSB_TSSI1_TSR_TFTF (*((__I uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,2))) +#define TSB_TSSI1_TSR_TFOR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,4))) +#define TSB_TSSI1_TSR_TFUR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TSR,5))) +#define TSB_TSSI1_TIER_TFNFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,1))) +#define TSB_TSSI1_TIER_TFTFIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,2))) +#define TSB_TSSI1_TIER_TFORIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,4))) +#define TSB_TSSI1_TIER_TFURIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSSI1->TIER,5))) + + +/* UART */ +#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) +#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) +#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) +#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) +#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) +#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) +#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) +#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) +#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) +#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) +#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) +#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) +#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) +#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) +#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) +#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) +#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) +#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) +#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) +#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) +#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) +#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) +#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) +#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) +#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) +#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) +#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) +#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) +#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) +#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) +#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) +#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) +#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) +#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) +#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) +#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) +#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) +#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) +#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) +#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) +#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) +#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) + +#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) +#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) +#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) +#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) +#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) +#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) +#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) +#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) +#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) +#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) +#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) +#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) +#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) +#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) +#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) +#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) +#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) +#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) +#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) +#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) +#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) +#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) +#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) +#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) +#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) +#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) +#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) +#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) +#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) +#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) +#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) +#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) +#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) +#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) +#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) +#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) +#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) +#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) +#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) +#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) +#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) +#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) + +#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) +#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) +#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) +#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) +#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) +#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) +#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) +#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) +#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) +#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) +#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) +#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) +#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) +#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) +#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) +#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) +#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) +#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) +#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) +#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) +#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) +#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) +#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) +#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) +#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) +#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) +#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) +#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) +#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) +#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) +#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) +#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) +#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) +#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) +#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) +#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) +#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) +#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) +#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) +#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) +#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) +#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) + +#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) +#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) +#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) +#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) +#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) +#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) +#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) +#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) +#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) +#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) +#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) +#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) +#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) +#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) +#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) +#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) +#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) +#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) +#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) +#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) +#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) +#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) +#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) +#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) +#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) +#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) +#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) +#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) +#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) +#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) +#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) +#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) +#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) +#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) +#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) +#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) +#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) +#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) +#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) +#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) +#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) +#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) + +#define TSB_UART4_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SWRST,7))) +#define TSB_UART4_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,2))) +#define TSB_UART4_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,3))) +#define TSB_UART4_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,4))) +#define TSB_UART4_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,5))) +#define TSB_UART4_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,6))) +#define TSB_UART4_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,8))) +#define TSB_UART4_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,9))) +#define TSB_UART4_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,10))) +#define TSB_UART4_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,15))) +#define TSB_UART4_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,16))) +#define TSB_UART4_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,17))) +#define TSB_UART4_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR0,18))) +#define TSB_UART4_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,0))) +#define TSB_UART4_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,1))) +#define TSB_UART4_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,2))) +#define TSB_UART4_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,4))) +#define TSB_UART4_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,5))) +#define TSB_UART4_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,6))) +#define TSB_UART4_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->CR1,7))) +#define TSB_UART4_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->BRD,23))) +#define TSB_UART4_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,0))) +#define TSB_UART4_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,1))) +#define TSB_UART4_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,2))) +#define TSB_UART4_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->TRANS,3))) +#define TSB_UART4_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,16))) +#define TSB_UART4_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,17))) +#define TSB_UART4_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->DR,18))) +#define TSB_UART4_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,5))) +#define TSB_UART4_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,6))) +#define TSB_UART4_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,7))) +#define TSB_UART4_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,13))) +#define TSB_UART4_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->SR,14))) +#define TSB_UART4_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,15))) +#define TSB_UART4_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART4->SR,31))) +#define TSB_UART4_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,0))) +#define TSB_UART4_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART4->FIFOCLR,1))) +#define TSB_UART4_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,0))) +#define TSB_UART4_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,1))) +#define TSB_UART4_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,2))) +#define TSB_UART4_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,3))) +#define TSB_UART4_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART4->ERR,4))) + +#define TSB_UART5_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SWRST,7))) +#define TSB_UART5_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,2))) +#define TSB_UART5_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,3))) +#define TSB_UART5_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,4))) +#define TSB_UART5_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,5))) +#define TSB_UART5_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,6))) +#define TSB_UART5_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,8))) +#define TSB_UART5_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,9))) +#define TSB_UART5_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,10))) +#define TSB_UART5_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,15))) +#define TSB_UART5_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,16))) +#define TSB_UART5_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,17))) +#define TSB_UART5_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR0,18))) +#define TSB_UART5_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,0))) +#define TSB_UART5_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,1))) +#define TSB_UART5_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,2))) +#define TSB_UART5_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,4))) +#define TSB_UART5_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,5))) +#define TSB_UART5_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,6))) +#define TSB_UART5_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->CR1,7))) +#define TSB_UART5_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->BRD,23))) +#define TSB_UART5_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,0))) +#define TSB_UART5_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,1))) +#define TSB_UART5_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,2))) +#define TSB_UART5_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->TRANS,3))) +#define TSB_UART5_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,16))) +#define TSB_UART5_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,17))) +#define TSB_UART5_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->DR,18))) +#define TSB_UART5_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,5))) +#define TSB_UART5_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,6))) +#define TSB_UART5_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,7))) +#define TSB_UART5_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,13))) +#define TSB_UART5_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->SR,14))) +#define TSB_UART5_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,15))) +#define TSB_UART5_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART5->SR,31))) +#define TSB_UART5_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,0))) +#define TSB_UART5_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART5->FIFOCLR,1))) +#define TSB_UART5_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,0))) +#define TSB_UART5_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,1))) +#define TSB_UART5_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,2))) +#define TSB_UART5_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,3))) +#define TSB_UART5_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART5->ERR,4))) + + +/* I2S interface */ +#define TSB_I2S0_CSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CSTART,8))) +#define TSB_I2S0_CBUSY_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CBUSY,8))) +#define TSB_I2S0_CSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CSTOP,0))) +#define TSB_I2S0_CAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CAUDIOSET,8))) +#define TSB_I2S0_CAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CAUDIOSET,11))) +#define TSB_I2S0_CREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,0))) +#define TSB_I2S0_CREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,3))) +#define TSB_I2S0_CREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,16))) +#define TSB_I2S0_CREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->CREGBUSY,19))) +#define TSB_I2S0_CMS_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CMS_SEL,0))) +#define TSB_I2S0_CMCLK_IO_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CMCLK_IO_SEL,0))) +#define TSB_I2S0_CPHT_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CPHT_DIVOUT_EN,0))) +#define TSB_I2S0_CBCK_SRC_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CBCK_SRC_SEL,0))) +#define TSB_I2S0_CBCK_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->CBCK_DIVOUT_EN,0))) +#define TSB_I2S0_ISTART_MICSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTART,0))) +#define TSB_I2S0_ISTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTART,8))) +#define TSB_I2S0_IBUSY_MICBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,0))) +#define TSB_I2S0_IBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,1))) +#define TSB_I2S0_IBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,16))) +#define TSB_I2S0_IBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IBUSY,17))) +#define TSB_I2S0_ISTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->ISTOP,0))) +#define TSB_I2S0_IAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,8))) +#define TSB_I2S0_IAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,11))) +#define TSB_I2S0_IAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,12))) +#define TSB_I2S0_IAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IAUDIOSET,16))) +#define TSB_I2S0_IINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,0))) +#define TSB_I2S0_IINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,1))) +#define TSB_I2S0_IINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,2))) +#define TSB_I2S0_IINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTSTAT,3))) +#define TSB_I2S0_IINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,0))) +#define TSB_I2S0_IINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,1))) +#define TSB_I2S0_IINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,2))) +#define TSB_I2S0_IINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,3))) +#define TSB_I2S0_IINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTMASK,16))) +#define TSB_I2S0_IINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,0))) +#define TSB_I2S0_IINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,1))) +#define TSB_I2S0_IINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,2))) +#define TSB_I2S0_IINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->IINTCLR,3))) +#define TSB_I2S0_IMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->IMUTE,0))) +#define TSB_I2S0_IREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,0))) +#define TSB_I2S0_IREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,1))) +#define TSB_I2S0_IREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,3))) +#define TSB_I2S0_IREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,16))) +#define TSB_I2S0_IREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,17))) +#define TSB_I2S0_IREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->IREGBUSY,19))) +#define TSB_I2S0_OSTART_SPKSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTART,0))) +#define TSB_I2S0_OSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTART,8))) +#define TSB_I2S0_OBUSY_SPKBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,0))) +#define TSB_I2S0_OBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,1))) +#define TSB_I2S0_OBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,16))) +#define TSB_I2S0_OBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OBUSY,17))) +#define TSB_I2S0_OSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OSTOP,0))) +#define TSB_I2S0_OAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,8))) +#define TSB_I2S0_OAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,11))) +#define TSB_I2S0_OAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,12))) +#define TSB_I2S0_OAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OAUDIOSET,16))) +#define TSB_I2S0_OINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,0))) +#define TSB_I2S0_OINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,1))) +#define TSB_I2S0_OINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,2))) +#define TSB_I2S0_OINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTSTAT,3))) +#define TSB_I2S0_OINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,0))) +#define TSB_I2S0_OINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,1))) +#define TSB_I2S0_OINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,2))) +#define TSB_I2S0_OINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,3))) +#define TSB_I2S0_OINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTMASK,16))) +#define TSB_I2S0_OINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,0))) +#define TSB_I2S0_OINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,1))) +#define TSB_I2S0_OINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,2))) +#define TSB_I2S0_OINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S0->OINTCLR,3))) +#define TSB_I2S0_OMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S0->OMUTE,0))) +#define TSB_I2S0_OREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,0))) +#define TSB_I2S0_OREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,1))) +#define TSB_I2S0_OREGBUSY_TXSSIZEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,2))) +#define TSB_I2S0_OREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,3))) +#define TSB_I2S0_OREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,16))) +#define TSB_I2S0_OREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,17))) +#define TSB_I2S0_OREGBUSY_TXSSIZEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,18))) +#define TSB_I2S0_OREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S0->OREGBUSY,19))) + +#define TSB_I2S1_CSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CSTART,8))) +#define TSB_I2S1_CBUSY_BUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CBUSY,8))) +#define TSB_I2S1_CSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CSTOP,0))) +#define TSB_I2S1_CAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CAUDIOSET,8))) +#define TSB_I2S1_CAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CAUDIOSET,11))) +#define TSB_I2S1_CREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,0))) +#define TSB_I2S1_CREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,3))) +#define TSB_I2S1_CREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,16))) +#define TSB_I2S1_CREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->CREGBUSY,19))) +#define TSB_I2S1_CMS_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CMS_SEL,0))) +#define TSB_I2S1_CMCLK_IO_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CMCLK_IO_SEL,0))) +#define TSB_I2S1_CPHT_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CPHT_DIVOUT_EN,0))) +#define TSB_I2S1_CBCK_SRC_SEL_SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CBCK_SRC_SEL,0))) +#define TSB_I2S1_CBCK_DIVOUT_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->CBCK_DIVOUT_EN,0))) +#define TSB_I2S1_ISTART_MICSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTART,0))) +#define TSB_I2S1_ISTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTART,8))) +#define TSB_I2S1_IBUSY_MICBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,0))) +#define TSB_I2S1_IBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,1))) +#define TSB_I2S1_IBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,16))) +#define TSB_I2S1_IBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IBUSY,17))) +#define TSB_I2S1_ISTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->ISTOP,0))) +#define TSB_I2S1_IAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,8))) +#define TSB_I2S1_IAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,11))) +#define TSB_I2S1_IAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,12))) +#define TSB_I2S1_IAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IAUDIOSET,16))) +#define TSB_I2S1_IINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,0))) +#define TSB_I2S1_IINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,1))) +#define TSB_I2S1_IINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,2))) +#define TSB_I2S1_IINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTSTAT,3))) +#define TSB_I2S1_IINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,0))) +#define TSB_I2S1_IINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,1))) +#define TSB_I2S1_IINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,2))) +#define TSB_I2S1_IINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,3))) +#define TSB_I2S1_IINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTMASK,16))) +#define TSB_I2S1_IINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,0))) +#define TSB_I2S1_IINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,1))) +#define TSB_I2S1_IINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,2))) +#define TSB_I2S1_IINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->IINTCLR,3))) +#define TSB_I2S1_IMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->IMUTE,0))) +#define TSB_I2S1_IREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,0))) +#define TSB_I2S1_IREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,1))) +#define TSB_I2S1_IREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,3))) +#define TSB_I2S1_IREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,16))) +#define TSB_I2S1_IREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,17))) +#define TSB_I2S1_IREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->IREGBUSY,19))) +#define TSB_I2S1_OSTART_SPKSTART (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTART,0))) +#define TSB_I2S1_OSTART_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTART,8))) +#define TSB_I2S1_OBUSY_SPKBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,0))) +#define TSB_I2S1_OBUSY_SERIBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,1))) +#define TSB_I2S1_OBUSY_ERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,16))) +#define TSB_I2S1_OBUSY_LRERRBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OBUSY,17))) +#define TSB_I2S1_OSTOP_I2S_STOP (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OSTOP,0))) +#define TSB_I2S1_OAUDIOSET_SCLKTOWS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,8))) +#define TSB_I2S1_OAUDIOSET_EDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,11))) +#define TSB_I2S1_OAUDIOSET_SDEDGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,12))) +#define TSB_I2S1_OAUDIOSET_DTFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OAUDIOSET,16))) +#define TSB_I2S1_OINTSTAT_INT (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,0))) +#define TSB_I2S1_OINTSTAT_ORERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,1))) +#define TSB_I2S1_OINTSTAT_URERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,2))) +#define TSB_I2S1_OINTSTAT_LRCKERR (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTSTAT,3))) +#define TSB_I2S1_OINTMASK_MASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,0))) +#define TSB_I2S1_OINTMASK_ORMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,1))) +#define TSB_I2S1_OINTMASK_URMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,2))) +#define TSB_I2S1_OINTMASK_LRERRMASK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,3))) +#define TSB_I2S1_OINTMASK_DMACMSK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTMASK,16))) +#define TSB_I2S1_OINTCLR_INTCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,0))) +#define TSB_I2S1_OINTCLR_ORCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,1))) +#define TSB_I2S1_OINTCLR_URCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,2))) +#define TSB_I2S1_OINTCLR_LRERRCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_I2S1->OINTCLR,3))) +#define TSB_I2S1_OMUTE_MUTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2S1->OMUTE,0))) +#define TSB_I2S1_OREGBUSY_AUDIOSETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,0))) +#define TSB_I2S1_OREGBUSY_MUTEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,1))) +#define TSB_I2S1_OREGBUSY_TXSSIZEBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,2))) +#define TSB_I2S1_OREGBUSY_MODESETBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,3))) +#define TSB_I2S1_OREGBUSY_AUDIOSETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,16))) +#define TSB_I2S1_OREGBUSY_MUTEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,17))) +#define TSB_I2S1_OREGBUSY_TXSSIZEPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,18))) +#define TSB_I2S1_OREGBUSY_MODESETPEND (*((__I uint32_t *)BITBAND_PERI(&TSB_I2S1->OREGBUSY,19))) + + +/* I2C */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + +#define TSB_I2C2_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3))) +#define TSB_I2C2_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4))) +#define TSB_I2C2_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0))) +#define TSB_I2C2_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3))) +#define TSB_I2C2_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4))) +#define TSB_I2C2_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5))) +#define TSB_I2C2_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6))) +#define TSB_I2C2_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7))) +#define TSB_I2C2_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0))) +#define TSB_I2C2_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1))) +#define TSB_I2C2_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2))) +#define TSB_I2C2_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3))) +#define TSB_I2C2_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4))) +#define TSB_I2C2_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5))) +#define TSB_I2C2_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6))) +#define TSB_I2C2_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7))) +#define TSB_I2C2_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0))) +#define TSB_I2C2_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,1))) +#define TSB_I2C2_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,2))) +#define TSB_I2C2_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,3))) +#define TSB_I2C2_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,4))) +#define TSB_I2C2_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,5))) +#define TSB_I2C2_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,6))) +#define TSB_I2C2_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,0))) +#define TSB_I2C2_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,1))) +#define TSB_I2C2_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,2))) +#define TSB_I2C2_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->ST,3))) +#define TSB_I2C2_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,0))) +#define TSB_I2C2_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,1))) +#define TSB_I2C2_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,2))) +#define TSB_I2C2_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,3))) +#define TSB_I2C2_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,4))) +#define TSB_I2C2_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,5))) +#define TSB_I2C2_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,6))) +#define TSB_I2C2_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->OP,7))) +#define TSB_I2C2_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,0))) +#define TSB_I2C2_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C2->PM,1))) +#define TSB_I2C2_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR2,0))) + +#define TSB_I2C3_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,3))) +#define TSB_I2C3_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->CR1,4))) +#define TSB_I2C3_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR,0))) +#define TSB_I2C3_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,3))) +#define TSB_I2C3_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,4))) +#define TSB_I2C3_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,5))) +#define TSB_I2C3_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,6))) +#define TSB_I2C3_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C3->CR2,7))) +#define TSB_I2C3_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,0))) +#define TSB_I2C3_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,1))) +#define TSB_I2C3_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,2))) +#define TSB_I2C3_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,3))) +#define TSB_I2C3_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,4))) +#define TSB_I2C3_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,5))) +#define TSB_I2C3_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,6))) +#define TSB_I2C3_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->SR,7))) +#define TSB_I2C3_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,0))) +#define TSB_I2C3_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,1))) +#define TSB_I2C3_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,2))) +#define TSB_I2C3_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,3))) +#define TSB_I2C3_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,4))) +#define TSB_I2C3_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,5))) +#define TSB_I2C3_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->IE,6))) +#define TSB_I2C3_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,0))) +#define TSB_I2C3_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,1))) +#define TSB_I2C3_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,2))) +#define TSB_I2C3_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->ST,3))) +#define TSB_I2C3_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,0))) +#define TSB_I2C3_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,1))) +#define TSB_I2C3_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,2))) +#define TSB_I2C3_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,3))) +#define TSB_I2C3_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,4))) +#define TSB_I2C3_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,5))) +#define TSB_I2C3_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,6))) +#define TSB_I2C3_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->OP,7))) +#define TSB_I2C3_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,0))) +#define TSB_I2C3_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C3->PM,1))) +#define TSB_I2C3_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C3->AR2,0))) + +#define TSB_I2C4_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,3))) +#define TSB_I2C4_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->CR1,4))) +#define TSB_I2C4_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR,0))) +#define TSB_I2C4_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,3))) +#define TSB_I2C4_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,4))) +#define TSB_I2C4_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,5))) +#define TSB_I2C4_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,6))) +#define TSB_I2C4_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C4->CR2,7))) +#define TSB_I2C4_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,0))) +#define TSB_I2C4_SR_ADO (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,1))) +#define TSB_I2C4_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,2))) +#define TSB_I2C4_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,3))) +#define TSB_I2C4_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,4))) +#define TSB_I2C4_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,5))) +#define TSB_I2C4_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,6))) +#define TSB_I2C4_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->SR,7))) +#define TSB_I2C4_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,0))) +#define TSB_I2C4_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,1))) +#define TSB_I2C4_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,2))) +#define TSB_I2C4_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,3))) +#define TSB_I2C4_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,4))) +#define TSB_I2C4_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,5))) +#define TSB_I2C4_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->IE,6))) +#define TSB_I2C4_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,0))) +#define TSB_I2C4_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,1))) +#define TSB_I2C4_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,2))) +#define TSB_I2C4_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->ST,3))) +#define TSB_I2C4_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,0))) +#define TSB_I2C4_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,1))) +#define TSB_I2C4_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,2))) +#define TSB_I2C4_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,3))) +#define TSB_I2C4_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,4))) +#define TSB_I2C4_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,5))) +#define TSB_I2C4_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,6))) +#define TSB_I2C4_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->OP,7))) +#define TSB_I2C4_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,0))) +#define TSB_I2C4_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C4->PM,1))) +#define TSB_I2C4_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C4->AR2,0))) + + +/* EI2C */ +#define TSB_EI2C0_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AEN,0))) +#define TSB_EI2C0_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,0))) +#define TSB_EI2C0_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,1))) +#define TSB_EI2C0_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,2))) +#define TSB_EI2C0_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,3))) +#define TSB_EI2C0_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,4))) +#define TSB_EI2C0_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,8))) +#define TSB_EI2C0_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,11))) +#define TSB_EI2C0_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,0))) +#define TSB_EI2C0_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,1))) +#define TSB_EI2C0_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,2))) +#define TSB_EI2C0_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,3))) +#define TSB_EI2C0_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,4))) +#define TSB_EI2C0_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,10))) +#define TSB_EI2C0_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,0))) +#define TSB_EI2C0_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,1))) +#define TSB_EI2C0_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,2))) +#define TSB_EI2C0_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,3))) +#define TSB_EI2C0_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,0))) +#define TSB_EI2C0_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,1))) +#define TSB_EI2C0_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,2))) +#define TSB_EI2C0_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,3))) +#define TSB_EI2C0_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,4))) +#define TSB_EI2C0_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,5))) +#define TSB_EI2C0_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,6))) +#define TSB_EI2C0_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,7))) +#define TSB_EI2C0_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,8))) +#define TSB_EI2C0_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,9))) +#define TSB_EI2C0_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,10))) +#define TSB_EI2C0_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,11))) +#define TSB_EI2C0_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,12))) +#define TSB_EI2C0_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,13))) +#define TSB_EI2C0_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,0))) +#define TSB_EI2C0_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,15))) +#define TSB_EI2C0_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,0))) +#define TSB_EI2C0_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,15))) +#define TSB_EI2C0_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,0))) +#define TSB_EI2C0_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,1))) +#define TSB_EI2C0_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,2))) +#define TSB_EI2C0_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,6))) +#define TSB_EI2C0_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,7))) +#define TSB_EI2C0_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,8))) +#define TSB_EI2C0_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,9))) +#define TSB_EI2C0_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,11))) +#define TSB_EI2C0_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,12))) +#define TSB_EI2C0_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,13))) +#define TSB_EI2C0_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,14))) +#define TSB_EI2C0_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,15))) +#define TSB_EI2C0_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,0))) +#define TSB_EI2C0_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,1))) +#define TSB_EI2C0_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,2))) +#define TSB_EI2C0_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,3))) + +#define TSB_EI2C1_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AEN,0))) +#define TSB_EI2C1_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,0))) +#define TSB_EI2C1_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,1))) +#define TSB_EI2C1_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,2))) +#define TSB_EI2C1_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,3))) +#define TSB_EI2C1_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,4))) +#define TSB_EI2C1_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,8))) +#define TSB_EI2C1_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,11))) +#define TSB_EI2C1_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,0))) +#define TSB_EI2C1_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,1))) +#define TSB_EI2C1_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,2))) +#define TSB_EI2C1_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,3))) +#define TSB_EI2C1_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,4))) +#define TSB_EI2C1_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,10))) +#define TSB_EI2C1_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,0))) +#define TSB_EI2C1_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,1))) +#define TSB_EI2C1_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,2))) +#define TSB_EI2C1_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,3))) +#define TSB_EI2C1_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,0))) +#define TSB_EI2C1_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,1))) +#define TSB_EI2C1_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,2))) +#define TSB_EI2C1_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,3))) +#define TSB_EI2C1_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,4))) +#define TSB_EI2C1_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,5))) +#define TSB_EI2C1_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,6))) +#define TSB_EI2C1_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,7))) +#define TSB_EI2C1_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,8))) +#define TSB_EI2C1_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,9))) +#define TSB_EI2C1_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,10))) +#define TSB_EI2C1_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,11))) +#define TSB_EI2C1_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,12))) +#define TSB_EI2C1_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,13))) +#define TSB_EI2C1_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,0))) +#define TSB_EI2C1_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,15))) +#define TSB_EI2C1_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,0))) +#define TSB_EI2C1_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,15))) +#define TSB_EI2C1_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,0))) +#define TSB_EI2C1_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,1))) +#define TSB_EI2C1_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,2))) +#define TSB_EI2C1_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,6))) +#define TSB_EI2C1_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,7))) +#define TSB_EI2C1_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,8))) +#define TSB_EI2C1_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,9))) +#define TSB_EI2C1_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,11))) +#define TSB_EI2C1_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,12))) +#define TSB_EI2C1_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,13))) +#define TSB_EI2C1_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,14))) +#define TSB_EI2C1_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,15))) +#define TSB_EI2C1_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,0))) +#define TSB_EI2C1_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,1))) +#define TSB_EI2C1_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,2))) +#define TSB_EI2C1_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,3))) + +#define TSB_EI2C2_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AEN,0))) +#define TSB_EI2C2_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,0))) +#define TSB_EI2C2_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,1))) +#define TSB_EI2C2_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,2))) +#define TSB_EI2C2_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,3))) +#define TSB_EI2C2_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,4))) +#define TSB_EI2C2_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,8))) +#define TSB_EI2C2_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR0,11))) +#define TSB_EI2C2_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,0))) +#define TSB_EI2C2_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,1))) +#define TSB_EI2C2_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,2))) +#define TSB_EI2C2_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,3))) +#define TSB_EI2C2_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,4))) +#define TSB_EI2C2_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ACR1,10))) +#define TSB_EI2C2_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,0))) +#define TSB_EI2C2_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,1))) +#define TSB_EI2C2_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,2))) +#define TSB_EI2C2_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR0,3))) +#define TSB_EI2C2_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,0))) +#define TSB_EI2C2_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,1))) +#define TSB_EI2C2_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,2))) +#define TSB_EI2C2_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,3))) +#define TSB_EI2C2_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,4))) +#define TSB_EI2C2_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,5))) +#define TSB_EI2C2_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,6))) +#define TSB_EI2C2_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,7))) +#define TSB_EI2C2_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,8))) +#define TSB_EI2C2_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,9))) +#define TSB_EI2C2_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,10))) +#define TSB_EI2C2_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,11))) +#define TSB_EI2C2_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,12))) +#define TSB_EI2C2_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->ASR1,13))) +#define TSB_EI2C2_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR1,0))) +#define TSB_EI2C2_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR1,15))) +#define TSB_EI2C2_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR2,0))) +#define TSB_EI2C2_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AAR2,15))) +#define TSB_EI2C2_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,0))) +#define TSB_EI2C2_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,1))) +#define TSB_EI2C2_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,2))) +#define TSB_EI2C2_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,6))) +#define TSB_EI2C2_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,7))) +#define TSB_EI2C2_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,8))) +#define TSB_EI2C2_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,9))) +#define TSB_EI2C2_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,11))) +#define TSB_EI2C2_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,12))) +#define TSB_EI2C2_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,13))) +#define TSB_EI2C2_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,14))) +#define TSB_EI2C2_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C2->AIE,15))) +#define TSB_EI2C2_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,0))) +#define TSB_EI2C2_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,1))) +#define TSB_EI2C2_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,2))) +#define TSB_EI2C2_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C2->APM,3))) + +#define TSB_EI2C3_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AEN,0))) +#define TSB_EI2C3_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,0))) +#define TSB_EI2C3_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,1))) +#define TSB_EI2C3_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,2))) +#define TSB_EI2C3_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,3))) +#define TSB_EI2C3_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,4))) +#define TSB_EI2C3_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,8))) +#define TSB_EI2C3_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR0,11))) +#define TSB_EI2C3_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,0))) +#define TSB_EI2C3_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,1))) +#define TSB_EI2C3_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,2))) +#define TSB_EI2C3_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,3))) +#define TSB_EI2C3_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,4))) +#define TSB_EI2C3_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ACR1,10))) +#define TSB_EI2C3_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,0))) +#define TSB_EI2C3_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,1))) +#define TSB_EI2C3_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,2))) +#define TSB_EI2C3_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR0,3))) +#define TSB_EI2C3_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,0))) +#define TSB_EI2C3_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,1))) +#define TSB_EI2C3_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,2))) +#define TSB_EI2C3_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,3))) +#define TSB_EI2C3_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,4))) +#define TSB_EI2C3_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,5))) +#define TSB_EI2C3_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,6))) +#define TSB_EI2C3_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,7))) +#define TSB_EI2C3_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,8))) +#define TSB_EI2C3_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,9))) +#define TSB_EI2C3_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,10))) +#define TSB_EI2C3_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,11))) +#define TSB_EI2C3_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,12))) +#define TSB_EI2C3_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->ASR1,13))) +#define TSB_EI2C3_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR1,0))) +#define TSB_EI2C3_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR1,15))) +#define TSB_EI2C3_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR2,0))) +#define TSB_EI2C3_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AAR2,15))) +#define TSB_EI2C3_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,0))) +#define TSB_EI2C3_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,1))) +#define TSB_EI2C3_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,2))) +#define TSB_EI2C3_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,6))) +#define TSB_EI2C3_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,7))) +#define TSB_EI2C3_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,8))) +#define TSB_EI2C3_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,9))) +#define TSB_EI2C3_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,11))) +#define TSB_EI2C3_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,12))) +#define TSB_EI2C3_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,13))) +#define TSB_EI2C3_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,14))) +#define TSB_EI2C3_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C3->AIE,15))) +#define TSB_EI2C3_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,0))) +#define TSB_EI2C3_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,1))) +#define TSB_EI2C3_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,2))) +#define TSB_EI2C3_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C3->APM,3))) + +#define TSB_EI2C4_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AEN,0))) +#define TSB_EI2C4_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,0))) +#define TSB_EI2C4_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,1))) +#define TSB_EI2C4_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,2))) +#define TSB_EI2C4_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,3))) +#define TSB_EI2C4_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,4))) +#define TSB_EI2C4_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,8))) +#define TSB_EI2C4_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR0,11))) +#define TSB_EI2C4_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,0))) +#define TSB_EI2C4_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,1))) +#define TSB_EI2C4_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,2))) +#define TSB_EI2C4_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,3))) +#define TSB_EI2C4_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,4))) +#define TSB_EI2C4_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ACR1,10))) +#define TSB_EI2C4_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,0))) +#define TSB_EI2C4_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,1))) +#define TSB_EI2C4_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,2))) +#define TSB_EI2C4_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR0,3))) +#define TSB_EI2C4_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,0))) +#define TSB_EI2C4_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,1))) +#define TSB_EI2C4_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,2))) +#define TSB_EI2C4_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,3))) +#define TSB_EI2C4_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,4))) +#define TSB_EI2C4_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,5))) +#define TSB_EI2C4_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,6))) +#define TSB_EI2C4_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,7))) +#define TSB_EI2C4_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,8))) +#define TSB_EI2C4_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,9))) +#define TSB_EI2C4_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,10))) +#define TSB_EI2C4_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,11))) +#define TSB_EI2C4_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,12))) +#define TSB_EI2C4_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->ASR1,13))) +#define TSB_EI2C4_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR1,0))) +#define TSB_EI2C4_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR1,15))) +#define TSB_EI2C4_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR2,0))) +#define TSB_EI2C4_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AAR2,15))) +#define TSB_EI2C4_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,0))) +#define TSB_EI2C4_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,1))) +#define TSB_EI2C4_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,2))) +#define TSB_EI2C4_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,6))) +#define TSB_EI2C4_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,7))) +#define TSB_EI2C4_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,8))) +#define TSB_EI2C4_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,9))) +#define TSB_EI2C4_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,11))) +#define TSB_EI2C4_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,12))) +#define TSB_EI2C4_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,13))) +#define TSB_EI2C4_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,14))) +#define TSB_EI2C4_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C4->AIE,15))) +#define TSB_EI2C4_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,0))) +#define TSB_EI2C4_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,1))) +#define TSB_EI2C4_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,2))) +#define TSB_EI2C4_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C4->APM,3))) + + +/* Finite Impulse Response */ +#define TSB_FIRnore_START_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->START,0))) +#define TSB_FIRnore_CTRL_ODATAFMT (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->CTRL,28))) +#define TSB_FIRnore_INITIALIZE_INITIALIZE (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INITIALIZE,0))) +#define TSB_FIRnore_INTEN_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,0))) +#define TSB_FIRnore_INTEN_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,1))) +#define TSB_FIRnore_INTEN_OVERFLOW (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->INTEN,2))) +#define TSB_FIRnore_DMAEN_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->DMAEN,0))) +#define TSB_FIRnore_DMAEN_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->DMAEN,1))) +#define TSB_FIRnore_RAWINTSTAT_IDATAWREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,0))) +#define TSB_FIRnore_RAWINTSTAT_ODATARREQ (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,1))) +#define TSB_FIRnore_RAWINTSTAT_OVERFLOW (*((__IO uint32_t *)BITBAND_PERI(&TSB_FIRnore->RAWINTSTAT,2))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_DATA_PA5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5))) +#define TSB_PA_DATA_PA6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6))) +#define TSB_PA_DATA_PA7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_CR_PA5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5))) +#define TSB_PA_CR_PA6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6))) +#define TSB_PA_CR_PA7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7))) +#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) +#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) +#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) +#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3))) +#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) +#define TSB_PA_FR1_PA5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5))) +#define TSB_PA_FR1_PA6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6))) +#define TSB_PA_FR1_PA7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7))) +#define TSB_PA_FR2_PA0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,0))) +#define TSB_PA_FR2_PA3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3))) +#define TSB_PA_FR2_PA4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,4))) +#define TSB_PA_FR2_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7))) +#define TSB_PA_FR3_PA0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,0))) +#define TSB_PA_FR3_PA1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,1))) +#define TSB_PA_FR3_PA2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,2))) +#define TSB_PA_FR3_PA3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,3))) +#define TSB_PA_FR3_PA4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,4))) +#define TSB_PA_FR3_PA5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,5))) +#define TSB_PA_FR3_PA6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,6))) +#define TSB_PA_FR3_PA7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,7))) +#define TSB_PA_FR5_PA0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,0))) +#define TSB_PA_FR5_PA1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,1))) +#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3))) +#define TSB_PA_FR5_PA4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,4))) +#define TSB_PA_FR5_PA5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,5))) +#define TSB_PA_FR5_PA7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,7))) +#define TSB_PA_FR6_PA0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,0))) +#define TSB_PA_FR6_PA3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,3))) +#define TSB_PA_FR6_PA4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,4))) +#define TSB_PA_FR6_PA5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,5))) +#define TSB_PA_FR6_PA6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,6))) +#define TSB_PA_FR6_PA7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,7))) +#define TSB_PA_FR7_PA0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,0))) +#define TSB_PA_FR7_PA1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,1))) +#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2))) +#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3))) +#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4))) +#define TSB_PA_FR7_PA5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,5))) +#define TSB_PA_FR7_PA6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,6))) +#define TSB_PA_FR7_PA7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,7))) +#define TSB_PA_FR8_PA2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR8,2))) +#define TSB_PA_FR8_PA6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR8,6))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_OD_PA5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5))) +#define TSB_PA_OD_PA6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6))) +#define TSB_PA_OD_PA7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PUP_PA5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5))) +#define TSB_PA_PUP_PA6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6))) +#define TSB_PA_PUP_PA7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_PDN_PA5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,5))) +#define TSB_PA_PDN_PA6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,6))) +#define TSB_PA_PDN_PA7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,7))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) +#define TSB_PA_IE_PA5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5))) +#define TSB_PA_IE_PA6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6))) +#define TSB_PA_IE_PA7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_FR1_PB0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,0))) +#define TSB_PB_FR1_PB1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1))) +#define TSB_PB_FR1_PB2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2))) +#define TSB_PB_FR1_PB3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3))) +#define TSB_PB_FR2_PB0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,0))) +#define TSB_PB_FR2_PB1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,1))) +#define TSB_PB_FR3_PB0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,0))) +#define TSB_PB_FR3_PB1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,1))) +#define TSB_PB_FR3_PB2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2))) +#define TSB_PB_FR3_PB3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3))) +#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) +#define TSB_PB_FR5_PB0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,0))) +#define TSB_PB_FR5_PB1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,1))) +#define TSB_PB_FR5_PB2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2))) +#define TSB_PB_FR6_PB0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,0))) +#define TSB_PB_FR6_PB1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,1))) +#define TSB_PB_FR6_PB2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,2))) +#define TSB_PB_FR6_PB3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR6,3))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) + + +/* Port C */ +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) +#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) +#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7))) +#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) +#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) +#define TSB_PC_FR1_PC6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,6))) +#define TSB_PC_FR1_PC7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,7))) +#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) +#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) +#define TSB_PC_FR5_PC4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,4))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) +#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) +#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) +#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) +#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) +#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) +#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) +#define TSB_PD_DATA_PD6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,6))) +#define TSB_PD_DATA_PD7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,7))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) +#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) +#define TSB_PD_CR_PD6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,6))) +#define TSB_PD_CR_PD7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,7))) +#define TSB_PD_FR1_PD0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0))) +#define TSB_PD_FR1_PD1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1))) +#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) +#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) +#define TSB_PD_FR1_PD4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4))) +#define TSB_PD_FR1_PD5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,5))) +#define TSB_PD_FR1_PD6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,6))) +#define TSB_PD_FR1_PD7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,7))) +#define TSB_PD_FR2_PD0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,0))) +#define TSB_PD_FR2_PD1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,1))) +#define TSB_PD_FR2_PD6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,6))) +#define TSB_PD_FR2_PD7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,7))) +#define TSB_PD_FR3_PD0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,0))) +#define TSB_PD_FR3_PD1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,1))) +#define TSB_PD_FR3_PD2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,2))) +#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3))) +#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4))) +#define TSB_PD_FR3_PD5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,5))) +#define TSB_PD_FR3_PD6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,6))) +#define TSB_PD_FR3_PD7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,7))) +#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0))) +#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1))) +#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2))) +#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3))) +#define TSB_PD_FR5_PD0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,0))) +#define TSB_PD_FR5_PD1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,1))) +#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2))) +#define TSB_PD_FR5_PD4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,4))) +#define TSB_PD_FR5_PD6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,6))) +#define TSB_PD_FR5_PD7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,7))) +#define TSB_PD_FR6_PD0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,0))) +#define TSB_PD_FR6_PD4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,4))) +#define TSB_PD_FR6_PD5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,5))) +#define TSB_PD_FR6_PD6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,6))) +#define TSB_PD_FR6_PD7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,7))) +#define TSB_PD_FR7_PD0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,0))) +#define TSB_PD_FR7_PD1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,1))) +#define TSB_PD_FR7_PD2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,2))) +#define TSB_PD_FR7_PD3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,3))) +#define TSB_PD_FR7_PD4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,4))) +#define TSB_PD_FR7_PD5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,5))) +#define TSB_PD_FR7_PD6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,6))) +#define TSB_PD_FR7_PD7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR7,7))) +#define TSB_PD_FR8_PD2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,2))) +#define TSB_PD_FR8_PD3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,3))) +#define TSB_PD_FR8_PD4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,4))) +#define TSB_PD_FR8_PD5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,5))) +#define TSB_PD_FR8_PD6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,6))) +#define TSB_PD_FR8_PD7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR8,7))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) +#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) +#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) +#define TSB_PD_OD_PD6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,6))) +#define TSB_PD_OD_PD7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,7))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) +#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) +#define TSB_PD_PUP_PD6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,6))) +#define TSB_PD_PUP_PD7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,7))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) +#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) +#define TSB_PD_PDN_PD6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,6))) +#define TSB_PD_PDN_PD7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,7))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) +#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) +#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) +#define TSB_PD_IE_PD6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,6))) +#define TSB_PD_IE_PD7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,7))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) +#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) +#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7))) +#define TSB_PE_FR1_PE0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,0))) +#define TSB_PE_FR1_PE1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1))) +#define TSB_PE_FR1_PE2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2))) +#define TSB_PE_FR1_PE3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3))) +#define TSB_PE_FR1_PE4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4))) +#define TSB_PE_FR1_PE5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5))) +#define TSB_PE_FR1_PE6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,6))) +#define TSB_PE_FR1_PE7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,7))) +#define TSB_PE_FR2_PE0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,0))) +#define TSB_PE_FR2_PE7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR2,7))) +#define TSB_PE_FR3_PE0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,0))) +#define TSB_PE_FR3_PE1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,1))) +#define TSB_PE_FR3_PE2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,2))) +#define TSB_PE_FR3_PE3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,3))) +#define TSB_PE_FR3_PE4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,4))) +#define TSB_PE_FR3_PE5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,5))) +#define TSB_PE_FR3_PE6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,6))) +#define TSB_PE_FR3_PE7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,7))) +#define TSB_PE_FR4_PE0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,0))) +#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1))) +#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2))) +#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3))) +#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4))) +#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5))) +#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6))) +#define TSB_PE_FR4_PE7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,7))) +#define TSB_PE_FR5_PE0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,0))) +#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1))) +#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2))) +#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3))) +#define TSB_PE_FR5_PE4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,4))) +#define TSB_PE_FR5_PE5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,5))) +#define TSB_PE_FR5_PE6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,6))) +#define TSB_PE_FR5_PE7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,7))) +#define TSB_PE_FR6_PE0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,0))) +#define TSB_PE_FR6_PE1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,1))) +#define TSB_PE_FR6_PE2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,2))) +#define TSB_PE_FR6_PE3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,3))) +#define TSB_PE_FR6_PE4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,4))) +#define TSB_PE_FR6_PE5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,5))) +#define TSB_PE_FR6_PE6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,6))) +#define TSB_PE_FR6_PE7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,7))) +#define TSB_PE_FR7_PE0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,0))) +#define TSB_PE_FR7_PE1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,1))) +#define TSB_PE_FR7_PE2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,2))) +#define TSB_PE_FR7_PE3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,3))) +#define TSB_PE_FR8_PE0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,0))) +#define TSB_PE_FR8_PE1F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,1))) +#define TSB_PE_FR8_PE2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,2))) +#define TSB_PE_FR8_PE3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,3))) +#define TSB_PE_FR8_PE4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,4))) +#define TSB_PE_FR8_PE5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,5))) +#define TSB_PE_FR8_PE6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,6))) +#define TSB_PE_FR8_PE7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR8,7))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) +#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) +#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) +#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) +#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) +#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7))) + + +/* Port F */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) +#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) +#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) +#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) +#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) +#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) +#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) +#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) +#define TSB_PF_FR1_PF5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5))) +#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6))) +#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7))) +#define TSB_PF_FR4_PF7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,7))) +#define TSB_PF_FR5_PF7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,7))) +#define TSB_PF_FR6_PF2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,2))) +#define TSB_PF_FR6_PF3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,3))) +#define TSB_PF_FR6_PF5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,5))) +#define TSB_PF_FR6_PF6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,6))) +#define TSB_PF_FR6_PF7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,7))) +#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2))) +#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) +#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) +#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) +#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) +#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) +#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) +#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) +#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) +#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) +#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) + + +/* Port G */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) +#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) +#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) +#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) +#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) +#define TSB_PG_DATA_PG7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) +#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) +#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) +#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) +#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) +#define TSB_PG_CR_PG7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7))) +#define TSB_PG_FR1_PG0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0))) +#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) +#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6))) +#define TSB_PG_FR1_PG7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,7))) +#define TSB_PG_FR2_PG4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,4))) +#define TSB_PG_FR2_PG5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR2,5))) +#define TSB_PG_FR3_PG0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,0))) +#define TSB_PG_FR3_PG1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,1))) +#define TSB_PG_FR3_PG2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2))) +#define TSB_PG_FR3_PG3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3))) +#define TSB_PG_FR3_PG5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,5))) +#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) +#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) +#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) +#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5))) +#define TSB_PG_FR4_PG6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,6))) +#define TSB_PG_FR4_PG7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,7))) +#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0))) +#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1))) +#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2))) +#define TSB_PG_FR5_PG3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,3))) +#define TSB_PG_FR5_PG4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,4))) +#define TSB_PG_FR5_PG5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,5))) +#define TSB_PG_FR5_PG6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,6))) +#define TSB_PG_FR5_PG7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,7))) +#define TSB_PG_FR6_PG2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,2))) +#define TSB_PG_FR6_PG3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,3))) +#define TSB_PG_FR6_PG4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,4))) +#define TSB_PG_FR6_PG5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,5))) +#define TSB_PG_FR6_PG6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR6,6))) +#define TSB_PG_FR7_PG2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,2))) +#define TSB_PG_FR7_PG3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,3))) +#define TSB_PG_FR7_PG4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,4))) +#define TSB_PG_FR7_PG5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR7,5))) +#define TSB_PG_FR8_PG0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR8,0))) +#define TSB_PG_FR8_PG1F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR8,1))) +#define TSB_PG_FR8_PG2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR8,2))) +#define TSB_PG_FR8_PG3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR8,3))) +#define TSB_PG_FR8_PG4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR8,4))) +#define TSB_PG_FR8_PG5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR8,5))) +#define TSB_PG_FR8_PG7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR8,7))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) +#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) +#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) +#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) +#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) +#define TSB_PG_OD_PG7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) +#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) +#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) +#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) +#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) +#define TSB_PG_PUP_PG7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) +#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) +#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) +#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) +#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) +#define TSB_PG_PDN_PG7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,7))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) +#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) +#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) +#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) +#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) +#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) +#define TSB_PG_IE_PG7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7))) + + +/* Port H */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_DATA_PH2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2))) +#define TSB_PH_DATA_PH3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3))) +#define TSB_PH_DATA_PH4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,4))) +#define TSB_PH_DATA_PH5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,5))) +#define TSB_PH_DATA_PH6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,6))) +#define TSB_PH_DATA_PH7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,7))) +#define TSB_PH_CR_PH0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0))) +#define TSB_PH_CR_PH1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1))) +#define TSB_PH_CR_PH2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2))) +#define TSB_PH_CR_PH3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3))) +#define TSB_PH_CR_PH4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,4))) +#define TSB_PH_CR_PH5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,5))) +#define TSB_PH_CR_PH6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,6))) +#define TSB_PH_CR_PH7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,7))) +#define TSB_PH_FR1_PH0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0))) +#define TSB_PH_FR1_PH1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1))) +#define TSB_PH_FR1_PH2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2))) +#define TSB_PH_FR1_PH3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3))) +#define TSB_PH_FR1_PH4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,4))) +#define TSB_PH_FR1_PH5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,5))) +#define TSB_PH_FR1_PH6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,6))) +#define TSB_PH_FR1_PH7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,7))) +#define TSB_PH_FR3_PH0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,0))) +#define TSB_PH_FR3_PH1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,1))) +#define TSB_PH_FR3_PH2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,2))) +#define TSB_PH_FR3_PH3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,3))) +#define TSB_PH_FR3_PH4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,4))) +#define TSB_PH_FR3_PH5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,5))) +#define TSB_PH_FR3_PH6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,6))) +#define TSB_PH_FR3_PH7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,7))) +#define TSB_PH_FR4_PH0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,0))) +#define TSB_PH_FR4_PH1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,1))) +#define TSB_PH_FR4_PH2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,2))) +#define TSB_PH_FR4_PH3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,3))) +#define TSB_PH_FR5_PH0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,0))) +#define TSB_PH_FR5_PH1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,1))) +#define TSB_PH_FR5_PH2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,2))) +#define TSB_PH_FR5_PH3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,3))) +#define TSB_PH_FR5_PH4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,4))) +#define TSB_PH_FR5_PH5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,5))) +#define TSB_PH_FR5_PH6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,6))) +#define TSB_PH_FR5_PH7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR5,7))) +#define TSB_PH_FR8_PH0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR8,0))) +#define TSB_PH_OD_PH0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0))) +#define TSB_PH_OD_PH1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1))) +#define TSB_PH_OD_PH2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2))) +#define TSB_PH_OD_PH3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3))) +#define TSB_PH_OD_PH4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,4))) +#define TSB_PH_OD_PH5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,5))) +#define TSB_PH_OD_PH6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,6))) +#define TSB_PH_OD_PH7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,7))) +#define TSB_PH_PUP_PH0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0))) +#define TSB_PH_PUP_PH1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1))) +#define TSB_PH_PUP_PH2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2))) +#define TSB_PH_PUP_PH3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3))) +#define TSB_PH_PUP_PH4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,4))) +#define TSB_PH_PUP_PH5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,5))) +#define TSB_PH_PUP_PH6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,6))) +#define TSB_PH_PUP_PH7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,7))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_PDN_PH2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,2))) +#define TSB_PH_PDN_PH3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,3))) +#define TSB_PH_PDN_PH4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,4))) +#define TSB_PH_PDN_PH5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,5))) +#define TSB_PH_PDN_PH6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,6))) +#define TSB_PH_PDN_PH7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,7))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) +#define TSB_PH_IE_PH2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2))) +#define TSB_PH_IE_PH3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3))) +#define TSB_PH_IE_PH4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,4))) +#define TSB_PH_IE_PH5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,5))) +#define TSB_PH_IE_PH6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,6))) +#define TSB_PH_IE_PH7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,7))) + + +/* Port J */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) +#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) +#define TSB_PJ_DATA_PJ6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,6))) +#define TSB_PJ_DATA_PJ7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,7))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) +#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) +#define TSB_PJ_CR_PJ6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,6))) +#define TSB_PJ_CR_PJ7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,7))) +#define TSB_PJ_FR2_PJ4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,4))) +#define TSB_PJ_FR2_PJ5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,5))) +#define TSB_PJ_FR3_PJ0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,0))) +#define TSB_PJ_FR3_PJ1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,1))) +#define TSB_PJ_FR3_PJ2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,2))) +#define TSB_PJ_FR3_PJ3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,3))) +#define TSB_PJ_FR3_PJ4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,4))) +#define TSB_PJ_FR3_PJ5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,5))) +#define TSB_PJ_FR5_PJ0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,0))) +#define TSB_PJ_FR5_PJ1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,1))) +#define TSB_PJ_FR5_PJ2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,2))) +#define TSB_PJ_FR5_PJ3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,3))) +#define TSB_PJ_FR5_PJ4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,4))) +#define TSB_PJ_FR5_PJ5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,5))) +#define TSB_PJ_FR5_PJ6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,6))) +#define TSB_PJ_FR5_PJ7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR5,7))) +#define TSB_PJ_FR6_PJ2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,2))) +#define TSB_PJ_FR6_PJ3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,3))) +#define TSB_PJ_FR6_PJ6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,6))) +#define TSB_PJ_FR6_PJ7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR6,7))) +#define TSB_PJ_FR7_PJ2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,2))) +#define TSB_PJ_FR7_PJ3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,3))) +#define TSB_PJ_FR7_PJ6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,6))) +#define TSB_PJ_FR7_PJ7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR7,7))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) +#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) +#define TSB_PJ_OD_PJ6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,6))) +#define TSB_PJ_OD_PJ7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,7))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) +#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) +#define TSB_PJ_PUP_PJ6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,6))) +#define TSB_PJ_PUP_PJ7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,7))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) +#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) +#define TSB_PJ_PDN_PJ6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,6))) +#define TSB_PJ_PDN_PJ7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,7))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) +#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) +#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) +#define TSB_PJ_IE_PJ6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,6))) +#define TSB_PJ_IE_PJ7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,7))) + + +/* Port K */ +#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) +#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) +#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) +#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) +#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) +#define TSB_PK_DATA_PK5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,5))) +#define TSB_PK_DATA_PK6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,6))) +#define TSB_PK_DATA_PK7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,7))) +#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) +#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) +#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) +#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) +#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) +#define TSB_PK_CR_PK5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,5))) +#define TSB_PK_CR_PK6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,6))) +#define TSB_PK_CR_PK7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,7))) +#define TSB_PK_FR1_PK0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,0))) +#define TSB_PK_FR1_PK1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,1))) +#define TSB_PK_FR1_PK2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,2))) +#define TSB_PK_FR1_PK3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,3))) +#define TSB_PK_FR1_PK4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,4))) +#define TSB_PK_FR1_PK5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,5))) +#define TSB_PK_FR1_PK6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR1,6))) +#define TSB_PK_FR2_PK0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,0))) +#define TSB_PK_FR2_PK1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1))) +#define TSB_PK_FR2_PK6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,6))) +#define TSB_PK_FR2_PK7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,7))) +#define TSB_PK_FR3_PK0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,0))) +#define TSB_PK_FR3_PK1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,1))) +#define TSB_PK_FR3_PK6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,6))) +#define TSB_PK_FR3_PK7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,7))) +#define TSB_PK_FR4_PK1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,1))) +#define TSB_PK_FR4_PK4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,4))) +#define TSB_PK_FR4_PK5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,5))) +#define TSB_PK_FR4_PK6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,6))) +#define TSB_PK_FR4_PK7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,7))) +#define TSB_PK_FR5_PK1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR5,1))) +#define TSB_PK_FR6_PK0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,0))) +#define TSB_PK_FR6_PK1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,1))) +#define TSB_PK_FR6_PK2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,2))) +#define TSB_PK_FR6_PK3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,3))) +#define TSB_PK_FR6_PK4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,4))) +#define TSB_PK_FR6_PK5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,5))) +#define TSB_PK_FR6_PK6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,6))) +#define TSB_PK_FR6_PK7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR6,7))) +#define TSB_PK_FR7_PK7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR7,7))) +#define TSB_PK_FR8_PK0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR8,0))) +#define TSB_PK_FR8_PK2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR8,2))) +#define TSB_PK_FR8_PK3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR8,3))) +#define TSB_PK_FR8_PK4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR8,4))) +#define TSB_PK_FR8_PK5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR8,5))) +#define TSB_PK_FR8_PK6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR8,6))) +#define TSB_PK_FR8_PK7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR8,7))) +#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) +#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) +#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) +#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) +#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) +#define TSB_PK_OD_PK5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,5))) +#define TSB_PK_OD_PK6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,6))) +#define TSB_PK_OD_PK7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,7))) +#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) +#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) +#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) +#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) +#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) +#define TSB_PK_PUP_PK5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,5))) +#define TSB_PK_PUP_PK6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,6))) +#define TSB_PK_PUP_PK7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,7))) +#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) +#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) +#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) +#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) +#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) +#define TSB_PK_PDN_PK5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,5))) +#define TSB_PK_PDN_PK6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,6))) +#define TSB_PK_PDN_PK7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,7))) +#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) +#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) +#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) +#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) +#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) +#define TSB_PK_IE_PK5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,5))) +#define TSB_PK_IE_PK6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,6))) +#define TSB_PK_IE_PK7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,7))) + + +/* Port L */ +#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) +#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) +#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) +#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) +#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) +#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) +#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) +#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) +#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) +#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) +#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) +#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) +#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) +#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) +#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) +#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) +#define TSB_PL_FR1_PL7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR1,7))) +#define TSB_PL_FR2_PL0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,0))) +#define TSB_PL_FR2_PL3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,3))) +#define TSB_PL_FR2_PL4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,4))) +#define TSB_PL_FR2_PL5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,5))) +#define TSB_PL_FR2_PL6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,6))) +#define TSB_PL_FR2_PL7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR2,7))) +#define TSB_PL_FR3_PL0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0))) +#define TSB_PL_FR3_PL3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3))) +#define TSB_PL_FR3_PL4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,4))) +#define TSB_PL_FR3_PL6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,6))) +#define TSB_PL_FR5_PL0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,0))) +#define TSB_PL_FR5_PL1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1))) +#define TSB_PL_FR5_PL2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2))) +#define TSB_PL_FR5_PL3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3))) +#define TSB_PL_FR6_PL0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,0))) +#define TSB_PL_FR6_PL3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,3))) +#define TSB_PL_FR7_PL0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,0))) +#define TSB_PL_FR7_PL1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,1))) +#define TSB_PL_FR7_PL2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,2))) +#define TSB_PL_FR7_PL3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR7,3))) +#define TSB_PL_FR8_PL0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR8,0))) +#define TSB_PL_FR8_PL1F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR8,1))) +#define TSB_PL_FR8_PL2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR8,2))) +#define TSB_PL_FR8_PL3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR8,3))) +#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) +#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) +#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) +#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) +#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) +#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) +#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) +#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) +#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) +#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) +#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) +#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) +#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) +#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) +#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) +#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) +#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) +#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) +#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) +#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) +#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) +#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) +#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) +#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) +#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) +#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) +#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) +#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) +#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) +#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) +#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) +#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) + + +/* Port M */ +#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) +#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) +#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) +#define TSB_PM_DATA_PM3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,3))) +#define TSB_PM_DATA_PM4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,4))) +#define TSB_PM_DATA_PM5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,5))) +#define TSB_PM_DATA_PM6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,6))) +#define TSB_PM_DATA_PM7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,7))) +#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) +#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) +#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) +#define TSB_PM_CR_PM3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,3))) +#define TSB_PM_CR_PM4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,4))) +#define TSB_PM_CR_PM5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,5))) +#define TSB_PM_CR_PM6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,6))) +#define TSB_PM_CR_PM7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,7))) +#define TSB_PM_FR1_PM0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,0))) +#define TSB_PM_FR1_PM1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,1))) +#define TSB_PM_FR1_PM6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,6))) +#define TSB_PM_FR1_PM7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR1,7))) +#define TSB_PM_FR2_PM2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,2))) +#define TSB_PM_FR2_PM3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,3))) +#define TSB_PM_FR2_PM4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,4))) +#define TSB_PM_FR2_PM5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,5))) +#define TSB_PM_FR2_PM6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,6))) +#define TSB_PM_FR2_PM7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR2,7))) +#define TSB_PM_FR3_PM1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,1))) +#define TSB_PM_FR3_PM2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,2))) +#define TSB_PM_FR3_PM5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,5))) +#define TSB_PM_FR3_PM6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR3,6))) +#define TSB_PM_FR4_PM0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,0))) +#define TSB_PM_FR4_PM1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,1))) +#define TSB_PM_FR4_PM3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,3))) +#define TSB_PM_FR4_PM4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,4))) +#define TSB_PM_FR4_PM6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,6))) +#define TSB_PM_FR4_PM7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR4,7))) +#define TSB_PM_FR5_PM0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,0))) +#define TSB_PM_FR5_PM1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,1))) +#define TSB_PM_FR5_PM2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,2))) +#define TSB_PM_FR5_PM3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,3))) +#define TSB_PM_FR5_PM6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,6))) +#define TSB_PM_FR5_PM7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR5,7))) +#define TSB_PM_FR6_PM0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,0))) +#define TSB_PM_FR6_PM1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,1))) +#define TSB_PM_FR6_PM2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,2))) +#define TSB_PM_FR6_PM3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,3))) +#define TSB_PM_FR6_PM4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,4))) +#define TSB_PM_FR6_PM5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,5))) +#define TSB_PM_FR6_PM6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,6))) +#define TSB_PM_FR6_PM7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR6,7))) +#define TSB_PM_FR7_PM0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,0))) +#define TSB_PM_FR7_PM1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,1))) +#define TSB_PM_FR7_PM2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,2))) +#define TSB_PM_FR7_PM3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,3))) +#define TSB_PM_FR7_PM4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,4))) +#define TSB_PM_FR7_PM5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,5))) +#define TSB_PM_FR7_PM6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,6))) +#define TSB_PM_FR7_PM7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR7,7))) +#define TSB_PM_FR8_PM0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR8,0))) +#define TSB_PM_FR8_PM1F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR8,1))) +#define TSB_PM_FR8_PM2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR8,2))) +#define TSB_PM_FR8_PM3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->FR8,3))) +#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) +#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) +#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) +#define TSB_PM_OD_PM3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,3))) +#define TSB_PM_OD_PM4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,4))) +#define TSB_PM_OD_PM5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,5))) +#define TSB_PM_OD_PM6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,6))) +#define TSB_PM_OD_PM7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,7))) +#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) +#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) +#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) +#define TSB_PM_PUP_PM3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,3))) +#define TSB_PM_PUP_PM4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,4))) +#define TSB_PM_PUP_PM5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,5))) +#define TSB_PM_PUP_PM6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,6))) +#define TSB_PM_PUP_PM7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,7))) +#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) +#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) +#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) +#define TSB_PM_PDN_PM3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,3))) +#define TSB_PM_PDN_PM4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,4))) +#define TSB_PM_PDN_PM5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,5))) +#define TSB_PM_PDN_PM6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,6))) +#define TSB_PM_PDN_PM7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,7))) +#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) +#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) +#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) +#define TSB_PM_IE_PM3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,3))) +#define TSB_PM_IE_PM4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,4))) +#define TSB_PM_IE_PM5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,5))) +#define TSB_PM_IE_PM6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,6))) +#define TSB_PM_IE_PM7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,7))) + + +/* Port N */ +#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) +#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) +#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) +#define TSB_PN_DATA_PN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,3))) +#define TSB_PN_DATA_PN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,4))) +#define TSB_PN_DATA_PN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,5))) +#define TSB_PN_DATA_PN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,6))) +#define TSB_PN_DATA_PN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,7))) +#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) +#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) +#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) +#define TSB_PN_CR_PN3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,3))) +#define TSB_PN_CR_PN4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,4))) +#define TSB_PN_CR_PN5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,5))) +#define TSB_PN_CR_PN6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,6))) +#define TSB_PN_CR_PN7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,7))) +#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) +#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) +#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) +#define TSB_PN_OD_PN3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,3))) +#define TSB_PN_OD_PN4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,4))) +#define TSB_PN_OD_PN5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,5))) +#define TSB_PN_OD_PN6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,6))) +#define TSB_PN_OD_PN7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,7))) +#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) +#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) +#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) +#define TSB_PN_PUP_PN3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,3))) +#define TSB_PN_PUP_PN4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,4))) +#define TSB_PN_PUP_PN5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,5))) +#define TSB_PN_PUP_PN6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,6))) +#define TSB_PN_PUP_PN7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,7))) +#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) +#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) +#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) +#define TSB_PN_PDN_PN3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,3))) +#define TSB_PN_PDN_PN4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,4))) +#define TSB_PN_PDN_PN5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,5))) +#define TSB_PN_PDN_PN6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,6))) +#define TSB_PN_PDN_PN7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,7))) +#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) +#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) +#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) +#define TSB_PN_IE_PN3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,3))) +#define TSB_PN_IE_PN4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,4))) +#define TSB_PN_IE_PN5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,5))) +#define TSB_PN_IE_PN6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,6))) +#define TSB_PN_IE_PN7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,7))) + + +/* Port P */ +#define TSB_PP_DATA_PP0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,0))) +#define TSB_PP_DATA_PP1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,1))) +#define TSB_PP_DATA_PP2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,2))) +#define TSB_PP_DATA_PP3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,3))) +#define TSB_PP_DATA_PP4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,4))) +#define TSB_PP_DATA_PP5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,5))) +#define TSB_PP_DATA_PP6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,6))) +#define TSB_PP_DATA_PP7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->DATA,7))) +#define TSB_PP_CR_PP0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,0))) +#define TSB_PP_CR_PP1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,1))) +#define TSB_PP_CR_PP2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,2))) +#define TSB_PP_CR_PP3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,3))) +#define TSB_PP_CR_PP4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,4))) +#define TSB_PP_CR_PP5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,5))) +#define TSB_PP_CR_PP6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,6))) +#define TSB_PP_CR_PP7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->CR,7))) +#define TSB_PP_FR2_PP0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,0))) +#define TSB_PP_FR2_PP1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,1))) +#define TSB_PP_FR2_PP2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,2))) +#define TSB_PP_FR2_PP3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,3))) +#define TSB_PP_FR2_PP4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,4))) +#define TSB_PP_FR2_PP5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,5))) +#define TSB_PP_FR2_PP6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,6))) +#define TSB_PP_FR2_PP7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR2,7))) +#define TSB_PP_FR3_PP0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,0))) +#define TSB_PP_FR3_PP1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,1))) +#define TSB_PP_FR3_PP2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,2))) +#define TSB_PP_FR3_PP3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,3))) +#define TSB_PP_FR3_PP4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,4))) +#define TSB_PP_FR3_PP5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,5))) +#define TSB_PP_FR3_PP6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,6))) +#define TSB_PP_FR3_PP7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR3,7))) +#define TSB_PP_FR5_PP0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,0))) +#define TSB_PP_FR5_PP1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,1))) +#define TSB_PP_FR5_PP2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,2))) +#define TSB_PP_FR5_PP3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,3))) +#define TSB_PP_FR5_PP4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,4))) +#define TSB_PP_FR5_PP5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,5))) +#define TSB_PP_FR5_PP6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,6))) +#define TSB_PP_FR5_PP7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->FR5,7))) +#define TSB_PP_OD_PP0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,0))) +#define TSB_PP_OD_PP1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,1))) +#define TSB_PP_OD_PP2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,2))) +#define TSB_PP_OD_PP3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,3))) +#define TSB_PP_OD_PP4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,4))) +#define TSB_PP_OD_PP5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,5))) +#define TSB_PP_OD_PP6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,6))) +#define TSB_PP_OD_PP7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->OD,7))) +#define TSB_PP_PUP_PP0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,0))) +#define TSB_PP_PUP_PP1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,1))) +#define TSB_PP_PUP_PP2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,2))) +#define TSB_PP_PUP_PP3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,3))) +#define TSB_PP_PUP_PP4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,4))) +#define TSB_PP_PUP_PP5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,5))) +#define TSB_PP_PUP_PP6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,6))) +#define TSB_PP_PUP_PP7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PUP,7))) +#define TSB_PP_PDN_PP0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,0))) +#define TSB_PP_PDN_PP1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,1))) +#define TSB_PP_PDN_PP2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,2))) +#define TSB_PP_PDN_PP3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,3))) +#define TSB_PP_PDN_PP4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,4))) +#define TSB_PP_PDN_PP5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,5))) +#define TSB_PP_PDN_PP6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,6))) +#define TSB_PP_PDN_PP7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->PDN,7))) +#define TSB_PP_IE_PP0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,0))) +#define TSB_PP_IE_PP1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,1))) +#define TSB_PP_IE_PP2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,2))) +#define TSB_PP_IE_PP3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,3))) +#define TSB_PP_IE_PP4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,4))) +#define TSB_PP_IE_PP5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,5))) +#define TSB_PP_IE_PP6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,6))) +#define TSB_PP_IE_PP7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PP->IE,7))) + + +/* Port R */ +#define TSB_PR_DATA_PR0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,0))) +#define TSB_PR_DATA_PR1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,1))) +#define TSB_PR_DATA_PR2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,2))) +#define TSB_PR_DATA_PR3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,3))) +#define TSB_PR_DATA_PR4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,4))) +#define TSB_PR_DATA_PR5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,5))) +#define TSB_PR_DATA_PR6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,6))) +#define TSB_PR_DATA_PR7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->DATA,7))) +#define TSB_PR_CR_PR0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,0))) +#define TSB_PR_CR_PR1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,1))) +#define TSB_PR_CR_PR2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,2))) +#define TSB_PR_CR_PR3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,3))) +#define TSB_PR_CR_PR4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,4))) +#define TSB_PR_CR_PR5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,5))) +#define TSB_PR_CR_PR6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,6))) +#define TSB_PR_CR_PR7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->CR,7))) +#define TSB_PR_FR2_PR0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,0))) +#define TSB_PR_FR2_PR1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,1))) +#define TSB_PR_FR2_PR2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,2))) +#define TSB_PR_FR2_PR3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,3))) +#define TSB_PR_FR2_PR4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,4))) +#define TSB_PR_FR2_PR5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,5))) +#define TSB_PR_FR2_PR6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,6))) +#define TSB_PR_FR2_PR7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR2,7))) +#define TSB_PR_FR3_PR0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,0))) +#define TSB_PR_FR3_PR1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,1))) +#define TSB_PR_FR3_PR2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,2))) +#define TSB_PR_FR3_PR3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,3))) +#define TSB_PR_FR3_PR4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,4))) +#define TSB_PR_FR3_PR5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,5))) +#define TSB_PR_FR3_PR6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,6))) +#define TSB_PR_FR3_PR7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->FR3,7))) +#define TSB_PR_OD_PR0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,0))) +#define TSB_PR_OD_PR1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,1))) +#define TSB_PR_OD_PR2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,2))) +#define TSB_PR_OD_PR3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,3))) +#define TSB_PR_OD_PR4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,4))) +#define TSB_PR_OD_PR5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,5))) +#define TSB_PR_OD_PR6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,6))) +#define TSB_PR_OD_PR7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->OD,7))) +#define TSB_PR_PUP_PR0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,0))) +#define TSB_PR_PUP_PR1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,1))) +#define TSB_PR_PUP_PR2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,2))) +#define TSB_PR_PUP_PR3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,3))) +#define TSB_PR_PUP_PR4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,4))) +#define TSB_PR_PUP_PR5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,5))) +#define TSB_PR_PUP_PR6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,6))) +#define TSB_PR_PUP_PR7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PUP,7))) +#define TSB_PR_PDN_PR0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,0))) +#define TSB_PR_PDN_PR1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,1))) +#define TSB_PR_PDN_PR2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,2))) +#define TSB_PR_PDN_PR3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,3))) +#define TSB_PR_PDN_PR4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,4))) +#define TSB_PR_PDN_PR5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,5))) +#define TSB_PR_PDN_PR6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,6))) +#define TSB_PR_PDN_PR7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->PDN,7))) +#define TSB_PR_IE_PR0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,0))) +#define TSB_PR_IE_PR1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,1))) +#define TSB_PR_IE_PR2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,2))) +#define TSB_PR_IE_PR3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,3))) +#define TSB_PR_IE_PR4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,4))) +#define TSB_PR_IE_PR5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,5))) +#define TSB_PR_IE_PR6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,6))) +#define TSB_PR_IE_PR7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PR->IE,7))) + + +/* Port T */ +#define TSB_PT_DATA_PT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,0))) +#define TSB_PT_DATA_PT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,1))) +#define TSB_PT_DATA_PT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,2))) +#define TSB_PT_DATA_PT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,3))) +#define TSB_PT_DATA_PT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,4))) +#define TSB_PT_DATA_PT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->DATA,5))) +#define TSB_PT_CR_PT0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,0))) +#define TSB_PT_CR_PT1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,1))) +#define TSB_PT_CR_PT2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,2))) +#define TSB_PT_CR_PT3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,3))) +#define TSB_PT_CR_PT4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,4))) +#define TSB_PT_CR_PT5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->CR,5))) +#define TSB_PT_FR1_PT3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR1,3))) +#define TSB_PT_FR2_PT3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,3))) +#define TSB_PT_FR2_PT5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR2,5))) +#define TSB_PT_FR3_PT3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR3,3))) +#define TSB_PT_FR6_PT3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR6,3))) +#define TSB_PT_FR7_PT2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR7,2))) +#define TSB_PT_FR8_PT4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->FR8,4))) +#define TSB_PT_OD_PT0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,0))) +#define TSB_PT_OD_PT1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,1))) +#define TSB_PT_OD_PT2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,2))) +#define TSB_PT_OD_PT3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,3))) +#define TSB_PT_OD_PT4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,4))) +#define TSB_PT_OD_PT5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->OD,5))) +#define TSB_PT_PUP_PT0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,0))) +#define TSB_PT_PUP_PT1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,1))) +#define TSB_PT_PUP_PT2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,2))) +#define TSB_PT_PUP_PT3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,3))) +#define TSB_PT_PUP_PT4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,4))) +#define TSB_PT_PUP_PT5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PUP,5))) +#define TSB_PT_PDN_PT0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,0))) +#define TSB_PT_PDN_PT1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,1))) +#define TSB_PT_PDN_PT2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,2))) +#define TSB_PT_PDN_PT3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,3))) +#define TSB_PT_PDN_PT4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,4))) +#define TSB_PT_PDN_PT5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->PDN,5))) +#define TSB_PT_IE_PT0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,0))) +#define TSB_PT_IE_PT1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,1))) +#define TSB_PT_IE_PT2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,2))) +#define TSB_PT_IE_PT3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,3))) +#define TSB_PT_IE_PT4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,4))) +#define TSB_PT_IE_PT5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PT->IE,5))) + + +/* Port U */ +#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) +#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) +#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) +#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) +#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) +#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6))) +#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7))) +#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) +#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) +#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) +#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) +#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) +#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6))) +#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7))) +#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0))) +#define TSB_PU_FR2_PU2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,2))) +#define TSB_PU_FR2_PU3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,3))) +#define TSB_PU_FR2_PU4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,4))) +#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5))) +#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6))) +#define TSB_PU_FR2_PU7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,7))) +#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0))) +#define TSB_PU_FR3_PU2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,2))) +#define TSB_PU_FR3_PU3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,3))) +#define TSB_PU_FR3_PU4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,4))) +#define TSB_PU_FR3_PU5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,5))) +#define TSB_PU_FR3_PU6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,6))) +#define TSB_PU_FR5_PU0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,0))) +#define TSB_PU_FR5_PU3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,3))) +#define TSB_PU_FR6_PU2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,2))) +#define TSB_PU_FR6_PU3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,3))) +#define TSB_PU_FR6_PU4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,4))) +#define TSB_PU_FR6_PU5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,5))) +#define TSB_PU_FR6_PU6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,6))) +#define TSB_PU_FR6_PU7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,7))) +#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0))) +#define TSB_PU_FR7_PU2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,2))) +#define TSB_PU_FR7_PU3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,3))) +#define TSB_PU_FR7_PU4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,4))) +#define TSB_PU_FR7_PU5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,5))) +#define TSB_PU_FR7_PU6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,6))) +#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7))) +#define TSB_PU_FR8_PU6F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR8,6))) +#define TSB_PU_FR8_PU7F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR8,7))) +#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) +#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) +#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) +#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) +#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) +#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6))) +#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7))) +#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) +#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) +#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) +#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) +#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) +#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6))) +#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7))) +#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) +#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) +#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) +#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) +#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) +#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6))) +#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7))) +#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) +#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) +#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) +#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) +#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) +#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6))) +#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7))) + + +/* Port V */ +#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) +#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) +#define TSB_PV_DATA_PV2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,2))) +#define TSB_PV_DATA_PV3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,3))) +#define TSB_PV_DATA_PV4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,4))) +#define TSB_PV_DATA_PV5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,5))) +#define TSB_PV_DATA_PV6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,6))) +#define TSB_PV_DATA_PV7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,7))) +#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) +#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) +#define TSB_PV_CR_PV2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,2))) +#define TSB_PV_CR_PV3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,3))) +#define TSB_PV_CR_PV4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,4))) +#define TSB_PV_CR_PV5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,5))) +#define TSB_PV_CR_PV6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,6))) +#define TSB_PV_CR_PV7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,7))) +#define TSB_PV_FR1_PV4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,4))) +#define TSB_PV_FR1_PV5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,5))) +#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0))) +#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1))) +#define TSB_PV_FR2_PV2F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,2))) +#define TSB_PV_FR2_PV3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,3))) +#define TSB_PV_FR2_PV4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,4))) +#define TSB_PV_FR2_PV5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,5))) +#define TSB_PV_FR2_PV6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,6))) +#define TSB_PV_FR2_PV7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,7))) +#define TSB_PV_FR3_PV0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,0))) +#define TSB_PV_FR3_PV1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,1))) +#define TSB_PV_FR3_PV2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,2))) +#define TSB_PV_FR3_PV5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,5))) +#define TSB_PV_FR3_PV6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR3,6))) +#define TSB_PV_FR4_PV4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,4))) +#define TSB_PV_FR4_PV5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,5))) +#define TSB_PV_FR4_PV6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,6))) +#define TSB_PV_FR4_PV7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,7))) +#define TSB_PV_FR5_PV0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,0))) +#define TSB_PV_FR5_PV1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,1))) +#define TSB_PV_FR5_PV2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,2))) +#define TSB_PV_FR5_PV3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,3))) +#define TSB_PV_FR5_PV4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,4))) +#define TSB_PV_FR5_PV5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,5))) +#define TSB_PV_FR5_PV6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,6))) +#define TSB_PV_FR5_PV7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR5,7))) +#define TSB_PV_FR6_PV0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,0))) +#define TSB_PV_FR6_PV1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,1))) +#define TSB_PV_FR6_PV2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,2))) +#define TSB_PV_FR6_PV3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,3))) +#define TSB_PV_FR6_PV4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,4))) +#define TSB_PV_FR6_PV5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,5))) +#define TSB_PV_FR6_PV7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR6,7))) +#define TSB_PV_FR7_PV0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,0))) +#define TSB_PV_FR7_PV1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,1))) +#define TSB_PV_FR7_PV2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,2))) +#define TSB_PV_FR7_PV3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,3))) +#define TSB_PV_FR7_PV4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,4))) +#define TSB_PV_FR7_PV5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,5))) +#define TSB_PV_FR7_PV6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,6))) +#define TSB_PV_FR7_PV7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR7,7))) +#define TSB_PV_FR8_PV0F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR8,0))) +#define TSB_PV_FR8_PV1F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR8,1))) +#define TSB_PV_FR8_PV2F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR8,2))) +#define TSB_PV_FR8_PV3F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR8,3))) +#define TSB_PV_FR8_PV4F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR8,4))) +#define TSB_PV_FR8_PV5F8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR8,5))) +#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) +#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) +#define TSB_PV_OD_PV2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,2))) +#define TSB_PV_OD_PV3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,3))) +#define TSB_PV_OD_PV4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,4))) +#define TSB_PV_OD_PV5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,5))) +#define TSB_PV_OD_PV6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,6))) +#define TSB_PV_OD_PV7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,7))) +#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) +#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) +#define TSB_PV_PUP_PV2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,2))) +#define TSB_PV_PUP_PV3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,3))) +#define TSB_PV_PUP_PV4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,4))) +#define TSB_PV_PUP_PV5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,5))) +#define TSB_PV_PUP_PV6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,6))) +#define TSB_PV_PUP_PV7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,7))) +#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) +#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) +#define TSB_PV_PDN_PV2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,2))) +#define TSB_PV_PDN_PV3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,3))) +#define TSB_PV_PDN_PV4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,4))) +#define TSB_PV_PDN_PV5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,5))) +#define TSB_PV_PDN_PV6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,6))) +#define TSB_PV_PDN_PV7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,7))) +#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) +#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) +#define TSB_PV_IE_PV2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,2))) +#define TSB_PV_IE_PV3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,3))) +#define TSB_PV_IE_PV4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,4))) +#define TSB_PV_IE_PV5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,5))) +#define TSB_PV_IE_PV6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,6))) +#define TSB_PV_IE_PV7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,7))) + + +/* Port W */ +#define TSB_PW_DATA_PW0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,0))) +#define TSB_PW_DATA_PW1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,1))) +#define TSB_PW_DATA_PW2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,2))) +#define TSB_PW_DATA_PW3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,3))) +#define TSB_PW_DATA_PW4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,4))) +#define TSB_PW_DATA_PW5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,5))) +#define TSB_PW_DATA_PW6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,6))) +#define TSB_PW_DATA_PW7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->DATA,7))) +#define TSB_PW_CR_PW0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,0))) +#define TSB_PW_CR_PW1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,1))) +#define TSB_PW_CR_PW2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,2))) +#define TSB_PW_CR_PW3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,3))) +#define TSB_PW_CR_PW4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,4))) +#define TSB_PW_CR_PW5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,5))) +#define TSB_PW_CR_PW6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,6))) +#define TSB_PW_CR_PW7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->CR,7))) +#define TSB_PW_FR3_PW4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,4))) +#define TSB_PW_FR3_PW7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR3,7))) +#define TSB_PW_FR4_PW0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,0))) +#define TSB_PW_FR4_PW1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,1))) +#define TSB_PW_FR4_PW2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,2))) +#define TSB_PW_FR4_PW3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR4,3))) +#define TSB_PW_FR5_PW0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,0))) +#define TSB_PW_FR5_PW1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,1))) +#define TSB_PW_FR5_PW2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,2))) +#define TSB_PW_FR5_PW3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,3))) +#define TSB_PW_FR5_PW4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,4))) +#define TSB_PW_FR5_PW5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,5))) +#define TSB_PW_FR5_PW6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,6))) +#define TSB_PW_FR5_PW7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR5,7))) +#define TSB_PW_FR6_PW0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR6,0))) +#define TSB_PW_FR7_PW1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,1))) +#define TSB_PW_FR7_PW2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,2))) +#define TSB_PW_FR7_PW4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,4))) +#define TSB_PW_FR7_PW5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,5))) +#define TSB_PW_FR7_PW6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,6))) +#define TSB_PW_FR7_PW7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->FR7,7))) +#define TSB_PW_OD_PW0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,0))) +#define TSB_PW_OD_PW1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,1))) +#define TSB_PW_OD_PW2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,2))) +#define TSB_PW_OD_PW3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,3))) +#define TSB_PW_OD_PW4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,4))) +#define TSB_PW_OD_PW5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,5))) +#define TSB_PW_OD_PW6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,6))) +#define TSB_PW_OD_PW7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->OD,7))) +#define TSB_PW_PUP_PW0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,0))) +#define TSB_PW_PUP_PW1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,1))) +#define TSB_PW_PUP_PW2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,2))) +#define TSB_PW_PUP_PW3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,3))) +#define TSB_PW_PUP_PW4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,4))) +#define TSB_PW_PUP_PW5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,5))) +#define TSB_PW_PUP_PW6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,6))) +#define TSB_PW_PUP_PW7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PUP,7))) +#define TSB_PW_PDN_PW0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,0))) +#define TSB_PW_PDN_PW1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,1))) +#define TSB_PW_PDN_PW2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,2))) +#define TSB_PW_PDN_PW3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,3))) +#define TSB_PW_PDN_PW4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,4))) +#define TSB_PW_PDN_PW5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,5))) +#define TSB_PW_PDN_PW6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,6))) +#define TSB_PW_PDN_PW7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->PDN,7))) +#define TSB_PW_IE_PW0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,0))) +#define TSB_PW_IE_PW1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,1))) +#define TSB_PW_IE_PW2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,2))) +#define TSB_PW_IE_PW3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,3))) +#define TSB_PW_IE_PW4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,4))) +#define TSB_PW_IE_PW5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,5))) +#define TSB_PW_IE_PW6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,6))) +#define TSB_PW_IE_PW7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PW->IE,7))) + + +/* Port Y */ +#define TSB_PY_DATA_PY0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,0))) +#define TSB_PY_DATA_PY1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,1))) +#define TSB_PY_DATA_PY2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,2))) +#define TSB_PY_DATA_PY3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,3))) +#define TSB_PY_DATA_PY4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->DATA,4))) +#define TSB_PY_CR_PY4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->CR,4))) +#define TSB_PY_FR1_PY4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR1,4))) +#define TSB_PY_FR4_PY4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR4,4))) +#define TSB_PY_FR6_PY4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->FR6,4))) +#define TSB_PY_OD_PY4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->OD,4))) +#define TSB_PY_PUP_PY0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,0))) +#define TSB_PY_PUP_PY1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,1))) +#define TSB_PY_PUP_PY2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,2))) +#define TSB_PY_PUP_PY3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,3))) +#define TSB_PY_PUP_PY4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PUP,4))) +#define TSB_PY_PDN_PY0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,0))) +#define TSB_PY_PDN_PY1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,1))) +#define TSB_PY_PDN_PY2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,2))) +#define TSB_PY_PDN_PY3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,3))) +#define TSB_PY_PDN_PY4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->PDN,4))) +#define TSB_PY_IE_PY0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,0))) +#define TSB_PY_IE_PY1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,1))) +#define TSB_PY_IE_PY2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,2))) +#define TSB_PY_IE_PY3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PY->IE,3))) + + +/* Internal High-speed Oscillation Adjustment */ +#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) + + +/* Oscillation Frequency Detector (OFD) */ +#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) +#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) +#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) +#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) + + + +/* Consumer Electronics Control (CEC) */ +#define TSB_CEC0_EN_CECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->EN,0))) +#define TSB_CEC0_RESET_CECRESET (*((__O uint32_t *)BITBAND_PERI(&TSB_CEC0->RESET,0))) +#define TSB_CEC0_REN_CECREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->REN,0))) +#define TSB_CEC0_RBUF_CECEOM (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,8))) +#define TSB_CEC0_RBUF_CECACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RBUF,9))) +#define TSB_CEC0_RCR1_CECOTH (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,0))) +#define TSB_CEC0_RCR1_CECRIHLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,1))) +#define TSB_CEC0_RCR1_CECACKDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR1,24))) +#define TSB_CEC0_RCR3_CECWAVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,0))) +#define TSB_CEC0_RCR3_CECRSTAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->RCR3,1))) +#define TSB_CEC0_TEN_CECTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,0))) +#define TSB_CEC0_TEN_CECTRANS (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TEN,1))) +#define TSB_CEC0_TBUF_CECTEOM (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TBUF,8))) +#define TSB_CEC0_TCR_CECBRD (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->TCR,4))) +#define TSB_CEC0_RSTAT_CECRIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,0))) +#define TSB_CEC0_RSTAT_CECRISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,1))) +#define TSB_CEC0_RSTAT_CECRIMAX (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,2))) +#define TSB_CEC0_RSTAT_CECRIMIN (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,3))) +#define TSB_CEC0_RSTAT_CECRIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,4))) +#define TSB_CEC0_RSTAT_CECRIOR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,5))) +#define TSB_CEC0_RSTAT_CECRIWAV (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->RSTAT,6))) +#define TSB_CEC0_TSTAT_CECTISTA (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,0))) +#define TSB_CEC0_TSTAT_CECTIEND (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,1))) +#define TSB_CEC0_TSTAT_CECTIAL (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,2))) +#define TSB_CEC0_TSTAT_CECTIACK (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,3))) +#define TSB_CEC0_TSTAT_CECTIUR (*((__I uint32_t *)BITBAND_PERI(&TSB_CEC0->TSTAT,4))) +#define TSB_CEC0_FSSEL_CECCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CEC0->FSSEL,0))) + + +/* Remote Control Signal Preprocessor (RMC) */ +#define TSB_RMC0_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->EN,0))) +#define TSB_RMC0_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->REN,0))) +#define TSB_RMC0_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,24))) +#define TSB_RMC0_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,25))) +#define TSB_RMC0_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,29))) +#define TSB_RMC0_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,30))) +#define TSB_RMC0_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR2,31))) +#define TSB_RMC0_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR3,15))) +#define TSB_RMC0_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->RCR4,7))) +#define TSB_RMC0_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,7))) +#define TSB_RMC0_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,8))) +#define TSB_RMC0_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,11))) +#define TSB_RMC0_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,12))) +#define TSB_RMC0_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,13))) +#define TSB_RMC0_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,14))) +#define TSB_RMC0_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC0->RSTAT,15))) +#define TSB_RMC0_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC0->FSSEL,0))) + +#define TSB_RMC1_EN_RMCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->EN,0))) +#define TSB_RMC1_REN_RMCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->REN,0))) +#define TSB_RMC1_RCR2_RMCPHM (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,24))) +#define TSB_RMC1_RCR2_RMCLD (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,25))) +#define TSB_RMC1_RCR2_RMCRPIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,29))) +#define TSB_RMC1_RCR2_RMCEDIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,30))) +#define TSB_RMC1_RCR2_RMCLIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR2,31))) +#define TSB_RMC1_RCR3_RMCRP (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR3,15))) +#define TSB_RMC1_RCR4_RMCPO (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->RCR4,7))) +#define TSB_RMC1_RSTAT_RMCRLDR (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,7))) +#define TSB_RMC1_RSTAT_RMCRRP (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,8))) +#define TSB_RMC1_RSTAT_RMCRRPIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,11))) +#define TSB_RMC1_RSTAT_RMCEDIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,12))) +#define TSB_RMC1_RSTAT_RMCDMAXIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,13))) +#define TSB_RMC1_RSTAT_RMCLOIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,14))) +#define TSB_RMC1_RSTAT_RMCRLIF (*((__I uint32_t *)BITBAND_PERI(&TSB_RMC1->RSTAT,15))) +#define TSB_RMC1_FSSEL_RMCCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_RMC1->FSSEL,0))) + + +/* */ +#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) +#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) +#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) +#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) +#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) +#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) +#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) +#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) +#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) +#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0))) +#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1))) +#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2))) +#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3))) +#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7))) +#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) +#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) +#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) +#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) +#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) +#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) +#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) +#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) +#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) +#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) +#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) +#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14))) +#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15))) +#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) +#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) +#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) +#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) +#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) +#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) +#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) +#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) +#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) +#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) +#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) +#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) +#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) +#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) +#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) +#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) +#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) +#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) +#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0))) + + +/* */ +#define TSB_ISDA_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->EN,0))) +#define TSB_ISDA_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,0))) +#define TSB_ISDA_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CLKCR,1))) +#define TSB_ISDA_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->OCR0,0))) +#define TSB_ISDA_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->CR,0))) +#define TSB_ISDA_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,0))) +#define TSB_ISDA_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,1))) +#define TSB_ISDA_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,2))) +#define TSB_ISDA_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->BR,3))) +#define TSB_ISDA_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,0))) +#define TSB_ISDA_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,1))) +#define TSB_ISDA_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,2))) +#define TSB_ISDA_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDA->SR,3))) +#define TSB_ISDA_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDA->INTCR,0))) + +#define TSB_ISDB_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->EN,0))) +#define TSB_ISDB_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,0))) +#define TSB_ISDB_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CLKCR,1))) +#define TSB_ISDB_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->OCR0,0))) +#define TSB_ISDB_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->CR,0))) +#define TSB_ISDB_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,0))) +#define TSB_ISDB_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,1))) +#define TSB_ISDB_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,2))) +#define TSB_ISDB_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->BR,3))) +#define TSB_ISDB_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,0))) +#define TSB_ISDB_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,1))) +#define TSB_ISDB_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,2))) +#define TSB_ISDB_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDB->SR,3))) +#define TSB_ISDB_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDB->INTCR,0))) + +#define TSB_ISDC_EN_EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->EN,0))) +#define TSB_ISDC_CLKCR_MS (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,0))) +#define TSB_ISDC_CLKCR_SC (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CLKCR,1))) +#define TSB_ISDC_OCR0_OP (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->OCR0,0))) +#define TSB_ISDC_CR_START (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->CR,0))) +#define TSB_ISDC_BR_B0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,0))) +#define TSB_ISDC_BR_B1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,1))) +#define TSB_ISDC_BR_B2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,2))) +#define TSB_ISDC_BR_B3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->BR,3))) +#define TSB_ISDC_SR_S0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,0))) +#define TSB_ISDC_SR_S1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,1))) +#define TSB_ISDC_SR_S2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,2))) +#define TSB_ISDC_SR_S3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ISDC->SR,3))) +#define TSB_ISDC_INTCR_INTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ISDC->INTCR,0))) + +/** @} */ /* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM4NR_H__ */ + +/** @} */ /* End of group TMPM4NR */ +/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4Nx.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4Nx.h new file mode 100644 index 0000000..ca82f31 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TMPM4Nx.h @@ -0,0 +1,81 @@ +/** + ******************************************************************************* + * @file TMPM4Nx.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4Nx' Group + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifndef __TMPM4Nx_H__ +#define __TMPM4Nx_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER TOSHIBA TXZ MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM4NR TMPM4NQ TMPM4NN + * @{ + */ + +#if !defined(TMPM4NR) && !defined(TMPM4NQ)&& !defined(TMPM4NN) + +/** + * @brief Remove a comment of target device. + */ +#define TMPM4NR /*!< TMPM4NR device */ +/*#define TMPM4NQ*/ /*!< TMPM4NQ device */ +/*#define TMPM4NN*/ /*!< TMPM4NN device */ +#endif + +/** @defgroup Device_Included Device Included + * @{ + */ + +#if defined(TMPM4NR) +#include "TMPM4NR.h" +#elif defined(TMPM4NQ) +#include "TMPM4NQ.h" +#elif defined(TMPM4NN) +#include "TMPM4NN.h" +#else +#error "target device is non-select." +#endif + +/** + * @} + */ /* End of group Device_Included */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM4Nx_H__ */ + +/** + * @} + */ /* End of group TMPM4Nx */ + +/** + * @} + */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_ARM_STD/startup_TMPM4NR.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_ARM_STD/startup_TMPM4NR.S new file mode 100644 index 0000000..4a08b36 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_ARM_STD/startup_TMPM4NR.S @@ -0,0 +1,650 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4NR.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4NR' Device Series +; * @version V1.0.0 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 +; ******************************************************************************* +; */ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt pin 00a/00b + DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b + DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b + DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b + DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b + DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b + DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b + DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b + DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b + DCD INT09_IRQHandler ; 9: Interrupt pin 09a/09b + DCD INT10_IRQHandler ; 10: Interrupt pin 10a/10b + DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b + DCD INT12_IRQHandler ; 12: Interrupt pin 12a/12b + DCD INT13_IRQHandler ; 13: Interrupt pin 13a/13b + DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b + DCD INT15_IRQHandler ; 15: Interrupt pin 15a/15b + DCD INTRTC_IRQHandler ; 16: Real time clock(XHz) interrupt + DCD INTCEC0RX_IRQHandler ; 17: CEC reception interrupt (channel 0) + DCD INTCEC0TX_IRQHandler ; 18: CEC transmission interrupt (channel 0) + DCD INTISDA_IRQHandler ; 19: Interval Sensing Detector interrupt (Unit A) + DCD INTISDB_IRQHandler ; 20: Interval Sensing Detector interrupt (Unit B) + DCD INTISDC_IRQHandler ; 21: Interval Sensing Detector interrupt (Unit C) + DCD INTRMC0_IRQHandler ; 22: Remote control reception interrupt 0 + DCD INTRMC1_IRQHandler ; 23: Remote control reception interrupt 1 + DCD INTLTTMR0_IRQHandler ; 24: Long Term Timer Interrupt(channel 0) + DCD INTHDMAATC_IRQHandler ; 25: HDMA complete of transfer(Unit A) + DCD INTHDMAAERR_IRQHandler ; 26: HDMA transfer error(Unit A) + DCD INTHDMABTC_IRQHandler ; 27: HDMA end of transfer(Unit B) + DCD INTHDMABERR_IRQHandler ; 28: HDMA transfer error(Unit B) + DCD INTMDMAATC_IRQHandler ; 29: MDMA complete of transfer(Unit A) + DCD INTT32A00_A_CT_IRQHandler ; 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A00_B_C01_CPC_IRQHandler; 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A01_A_CT_IRQHandler ; 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A01_B_C01_CPC_IRQHandler; 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A02_A_CT_IRQHandler ; 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A02_B_C01_CPC_IRQHandler; 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A03_A_CT_IRQHandler ; 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A03_B_C01_CPC_IRQHandler; 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A04_A_CT_IRQHandler ; 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A04_B_C01_CPC_IRQHandler; 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A05_A_CT_IRQHandler ; 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A05_B_C01_CPC_IRQHandler; 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A06_A_CT_IRQHandler ; 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A06_B_C01_CPC_IRQHandler; 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A07_A_CT_IRQHandler ; 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A07_B_C01_CPC_IRQHandler; 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A08_A_CT_IRQHandler ; 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A08_B_C01_CPC_IRQHandler; 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A09_A_CT_IRQHandler ; 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A09_B_C01_CPC_IRQHandler; 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A10_A_CT_IRQHandler ; 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A10_B_C01_CPC_IRQHandler; 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A11_A_CT_IRQHandler ; 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A11_B_C01_CPC_IRQHandler; 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A12_A_CT_IRQHandler ; 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A12_B_C01_CPC_IRQHandler; 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTT32A13_A_CT_IRQHandler ; 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow + DCD INTT32A13_B_C01_CPC_IRQHandler; 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + DCD INTEMG0_IRQHandler ; 58: PMD0 EMG interrupt + DCD INTOVV0_IRQHandler ; 59: PMD0 OVV interrupt + DCD INTPWM0_IRQHandler ; 60: PMD0 interrupt + DCD INTT0RX_IRQHandler ; 61: TSPI/SIO reception (channel 0) interrupt + DCD INTT0TX_IRQHandler ; 62: TSPI/SIO transmit (channel 0) interrupt + DCD INTT0ERR_IRQHandler ; 63: TSPI/SIO error (channel 0) interrupt + DCD INTT1RX_IRQHandler ; 64: TSPI/SIO reception (channel 1) interrupt + DCD INTT1TX_IRQHandler ; 65: TSPI/SIO transmit (channel 1) interrupt + DCD INTT1ERR_IRQHandler ; 66: TSPI/SIO error (channel 1) interrupt + DCD INTT2RX_IRQHandler ; 67: TSPI/SIO reception (channel 2) interrupt + DCD INTT2TX_IRQHandler ; 68: TSPI/SIO transmit (channel 2) interrupt + DCD INTT2ERR_IRQHandler ; 69: TSPI/SIO error (channel 2) interrupt + DCD INTT3RX_IRQHandler ; 70: TSPI/SIO reception (channel 3) interrupt + DCD INTT3TX_IRQHandler ; 71: TSPI/SIO transmit (channel 3) interrupt + DCD INTT3ERR_IRQHandler ; 72: TSPI/SIO error (channel 3) interrupt + DCD INTT4RX_IRQHandler ; 73: TSPI/SIO reception (channel 4) interrupt + DCD INTT4TX_IRQHandler ; 74: TSPI/SIO transmit (channel 4) interrupt + DCD INTT4ERR_IRQHandler ; 75: TSPI/SIO error (channel 4) interrupt + DCD INTT5RX_IRQHandler ; 76: TSPI/SIO reception (channel 5) interrupt + DCD INTT5TX_IRQHandler ; 77: TSPI/SIO transmit (channel 5) interrupt + DCD INTT5ERR_IRQHandler ; 78: TSPI/SIO error (channel 5) interrupt + DCD INTT6RX_IRQHandler ; 79: TSPI/SIO reception (channel 6) interrupt + DCD INTT6TX_IRQHandler ; 80: TSPI/SIO transmit (channel 6) interrupt + DCD INTT6ERR_IRQHandler ; 81: TSPI/SIO error (channel 6) interrupt + DCD INTT7RX_IRQHandler ; 82: TSPI/SIO reception (channel 7) interrupt + DCD INTT7TX_IRQHandler ; 83: TSPI/SIO transmit (channel 7) interrupt + DCD INTT7ERR_IRQHandler ; 84: TSPI/SIO error (channel 7) interrupt + DCD INTT8RX_IRQHandler ; 85: TSPI/SIO reception (channel 8) interrupt + DCD INTT8TX_IRQHandler ; 86: TSPI/SIO transmit (channel 8) interrupt + DCD INTT8ERR_IRQHandler ; 87: TSPI/SIO error (channel 8) interrupt + DCD INTSMI0_IRQHandler ; 88: Serial Memory Interface interrupt + DCD INTUART0RX_IRQHandler ; 89: UART reception (channel 0) interrupt + DCD INTUART0TX_IRQHandler ; 90: UART transmit (channel 0) interrupt + DCD INTUART0ERR_IRQHandler ; 91: UART error (channel 0) interrupt + DCD INTUART1RX_IRQHandler ; 92: UART reception (channel 1) interrupt + DCD INTUART1TX_IRQHandler ; 93: UART transmit (channel 1) interrupt + DCD INTUART1ERR_IRQHandler ; 94: UART error (channel 1) interrupt + DCD INTUART2RX_IRQHandler ; 95: UART reception (channel 2) interrupt + DCD INTUART2TX_IRQHandler ; 96: UART transmit (channel 2) interrupt + DCD INTUART2ERR_IRQHandler ; 97: UART error (channel 2) interrupt + DCD INTUART3RX_IRQHandler ; 98: UART reception (channel 3) interrupt + DCD INTUART3TX_IRQHandler ; 99: UART transmit (channel 3) interrupt + DCD INTUART3ERR_IRQHandler ; 100: UART error (channel 3) interrupt + DCD INTUART4RX_IRQHandler ; 101: UART reception (channel 4) interrupt + DCD INTUART4TX_IRQHandler ; 102: UART transmit (channel 4) interrupt + DCD INTUART4ERR_IRQHandler ; 103: UART error (channel 4) interrupt + DCD INTUART5RX_IRQHandler ; 104: UART reception (channel 5) interrupt + DCD INTUART5TX_IRQHandler ; 105: UART transmit (channel 5) interrupt + DCD INTUART5ERR_IRQHandler ; 106: UART error (channel 5) interrupt + DCD INTFUART0_IRQHandler ; 107: FUART interrupt(channel 0) + DCD INTFUART1_IRQHandler ; 108: FUART interrupt(channel 1) + DCD INTI2C0NST_IRQHandler ; 109: I2C0 interrupt / EI2C0 status interrupt + DCD INTI2C0ATX_IRQHandler ; 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C0BRX_IRQHandler ; 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C0NA_IRQHandler ; 112: I2C0 NACK detection interrupt + DCD INTI2C1NST_IRQHandler ; 113: I2C1 interrupt / EI2C0 status interrupt + DCD INTI2C1ATX_IRQHandler ; 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C1BRX_IRQHandler ; 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C1NA_IRQHandler ; 116: I2C1 NACK detection interrupt + DCD INTI2C2NST_IRQHandler ; 117: I2C2 interrupt / EI2C0 status interrupt + DCD INTI2C2ATX_IRQHandler ; 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C2BRX_IRQHandler ; 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C2NA_IRQHandler ; 120: I2C2 NACK detection interrupt + DCD INTI2C3NST_IRQHandler ; 121: I2C3 interrupt / EI2C0 status interrupt + DCD INTI2C3ATX_IRQHandler ; 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C3BRX_IRQHandler ; 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C3NA_IRQHandler ; 124: I2C3 NACK detection interrupt + DCD INTI2C4NST_IRQHandler ; 125: I2C4 interrupt / EI2C0 status interrupt + DCD INTI2C4ATX_IRQHandler ; 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + DCD INTI2C4BRX_IRQHandler ; 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt + DCD INTI2C4NA_IRQHandler ; 128: I2C4 NACK detection interrupt + DCD INTADACP0_IRQHandler ; 129: ADC conversion monitoring function interrupt 0 + DCD INTADACP1_IRQHandler ; 130: ADC conversion monitoring function interrupt 1 + DCD INTADATRG_IRQHandler ; 131: ADC conversion triggered by General purpose is finished + DCD INTADASGL_IRQHandler ; 132: ADC conversion triggered by Single program is finished + DCD INTADACNT_IRQHandler ; 133: ADC conversion triggered by Continuity program is finished + DCD INTADAHP_IRQHandler ; 134: ADC high priority AD conversion interrupt + DCD INTFLDRDY_IRQHandler ; 135: Data FLASH Ready interrupt + DCD INTFLCRDY_IRQHandler ; 136: Code FLASH Area0/1 Ready interrupt + DCD 0 ; 137: Reserved + DCD 0 ; 138: Reserved + DCD INTMDMAABERR_IRQHandler ; 139: MDMA bus error(Unit A) interrupt + DCD INTMDMAADERR_IRQHandler ; 140: MDMA descriptor error(Unit A) interrupt + DCD INTI2S0SI_IRQHandler ; 141: I2S ch0 SI transfer end interrupt + DCD INTI2S0SIERR_IRQHandler ; 142: I2S ch0 SI error interrupt + DCD INTI2S0SO_IRQHandler ; 143: I2S ch0 SO transfer end interrupt + DCD INTI2S0SOERR_IRQHandler ; 144: I2S ch0 SO error interrupt + DCD INTI2S1SI_IRQHandler ; 145: I2S ch1 SI transfer end interrupt + DCD INTI2S1SIERR_IRQHandler ; 146: I2S ch1 SI error interrupt + DCD INTI2S1SO_IRQHandler ; 147: I2S ch1 SO transfer end interrupt + DCD INTI2S1SOERR_IRQHandler ; 148: I2S ch1 SO error interrupt + DCD INTFIR0_IRQHandler ; 149: FIR ch0 interrupt + DCD INTTSSI0RX_IRQHandler ; 150: TSSI ch0 RX interrupt + DCD INTTSSI0TX_IRQHandler ; 151: TSSI ch0 TX interrupt + DCD INTTSSI0ERR_IRQHandler ; 152: TSSI ch0 error interrupt + DCD INTTSSI1RX_IRQHandler ; 153: TSSI ch1 RX interrupt + DCD INTTSSI1TX_IRQHandler ; 154: TSSI ch1 TX interrupt + DCD INTTSSI1ERR_IRQHandler ; 155: TSSI ch1 error interrupt + DCD INTEMA_IRQHandler ; 156: Ether MAC interrupt + DCD INTEMAMP_IRQHandler ; 157: Ether MAC magic packet detection interrupt + DCD INTCAN0RX_IRQHandler ; 158: CAN ch0 receive interrupt + DCD INTCAN0TX_IRQHandler ; 159: CAN ch0 transmission interrupt + DCD INTCAN0GLB_IRQHandler ; 160: CAN ch0 Global interrupt + DCD INTCAN1RX_IRQHandler ; 161: CAN ch1 receive interrupt + DCD INTCAN1TX_IRQHandler ; 162: CAN ch1 transmission interrupt + DCD INTCAN1GLB_IRQHandler ; 163: CAN ch1 Global interrupt + DCD INTUSBOTGA_IRQHandler ; 164: USB OTG unit A interrupt + DCD INTUSBOTGAWK_IRQHandler ; 165: USB OTG unit A Wakeup interrupt + DCD INTUSBOTGB_IRQHandler ; 166: USB OTG unit B interrupt + DCD INTUSBOTGBWK_IRQHandler ; 167: USB OTG unit B Wakeup interrupt + DCD INTT32A14_A_IRQHandler ; 168: T32A14 TimerA all interrupt + DCD INTT32A14_B_IRQHandler ; 169: T32A14 TimerB all interrupt + DCD INTT32A14_CT_IRQHandler ; 170: T32A14 TimerC match, overflow, and underflow Interrupt + DCD INTT32A15_A_IRQHandler ; 171: T32A15 TimerA all interrupt + DCD INTT32A15_B_IRQHandler ; 172: T32A15 TimerB all interrupt + DCD INTT32A15_C_IRQHandler ; 173: T32A15 TimerC all interrupt + DCD INTMDMAADISR_IRQHandler ; 174: MDMAC unit A Descriptor interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INTRTC_IRQHandler [WEAK] + EXPORT INTCEC0RX_IRQHandler [WEAK] + EXPORT INTCEC0TX_IRQHandler [WEAK] + EXPORT INTISDA_IRQHandler [WEAK] + EXPORT INTISDB_IRQHandler [WEAK] + EXPORT INTISDC_IRQHandler [WEAK] + EXPORT INTRMC0_IRQHandler [WEAK] + EXPORT INTRMC1_IRQHandler [WEAK] + EXPORT INTLTTMR0_IRQHandler [WEAK] + EXPORT INTHDMAATC_IRQHandler [WEAK] + EXPORT INTHDMAAERR_IRQHandler [WEAK] + EXPORT INTHDMABTC_IRQHandler [WEAK] + EXPORT INTHDMABERR_IRQHandler [WEAK] + EXPORT INTMDMAATC_IRQHandler [WEAK] + EXPORT INTT32A00_A_CT_IRQHandler [WEAK] + EXPORT INTT32A00_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A01_A_CT_IRQHandler [WEAK] + EXPORT INTT32A01_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A02_A_CT_IRQHandler [WEAK] + EXPORT INTT32A02_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A03_A_CT_IRQHandler [WEAK] + EXPORT INTT32A03_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A04_A_CT_IRQHandler [WEAK] + EXPORT INTT32A04_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A05_A_CT_IRQHandler [WEAK] + EXPORT INTT32A05_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A06_A_CT_IRQHandler [WEAK] + EXPORT INTT32A06_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A07_A_CT_IRQHandler [WEAK] + EXPORT INTT32A07_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A08_A_CT_IRQHandler [WEAK] + EXPORT INTT32A08_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A09_A_CT_IRQHandler [WEAK] + EXPORT INTT32A09_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A10_A_CT_IRQHandler [WEAK] + EXPORT INTT32A10_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A11_A_CT_IRQHandler [WEAK] + EXPORT INTT32A11_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A12_A_CT_IRQHandler [WEAK] + EXPORT INTT32A12_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTT32A13_A_CT_IRQHandler [WEAK] + EXPORT INTT32A13_B_C01_CPC_IRQHandler[WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTPWM0_IRQHandler [WEAK] + EXPORT INTT0RX_IRQHandler [WEAK] + EXPORT INTT0TX_IRQHandler [WEAK] + EXPORT INTT0ERR_IRQHandler [WEAK] + EXPORT INTT1RX_IRQHandler [WEAK] + EXPORT INTT1TX_IRQHandler [WEAK] + EXPORT INTT1ERR_IRQHandler [WEAK] + EXPORT INTT2RX_IRQHandler [WEAK] + EXPORT INTT2TX_IRQHandler [WEAK] + EXPORT INTT2ERR_IRQHandler [WEAK] + EXPORT INTT3RX_IRQHandler [WEAK] + EXPORT INTT3TX_IRQHandler [WEAK] + EXPORT INTT3ERR_IRQHandler [WEAK] + EXPORT INTT4RX_IRQHandler [WEAK] + EXPORT INTT4TX_IRQHandler [WEAK] + EXPORT INTT4ERR_IRQHandler [WEAK] + EXPORT INTT5RX_IRQHandler [WEAK] + EXPORT INTT5TX_IRQHandler [WEAK] + EXPORT INTT5ERR_IRQHandler [WEAK] + EXPORT INTT6RX_IRQHandler [WEAK] + EXPORT INTT6TX_IRQHandler [WEAK] + EXPORT INTT6ERR_IRQHandler [WEAK] + EXPORT INTT7RX_IRQHandler [WEAK] + EXPORT INTT7TX_IRQHandler [WEAK] + EXPORT INTT7ERR_IRQHandler [WEAK] + EXPORT INTT8RX_IRQHandler [WEAK] + EXPORT INTT8TX_IRQHandler [WEAK] + EXPORT INTT8ERR_IRQHandler [WEAK] + EXPORT INTSMI0_IRQHandler [WEAK] + EXPORT INTUART0RX_IRQHandler [WEAK] + EXPORT INTUART0TX_IRQHandler [WEAK] + EXPORT INTUART0ERR_IRQHandler [WEAK] + EXPORT INTUART1RX_IRQHandler [WEAK] + EXPORT INTUART1TX_IRQHandler [WEAK] + EXPORT INTUART1ERR_IRQHandler [WEAK] + EXPORT INTUART2RX_IRQHandler [WEAK] + EXPORT INTUART2TX_IRQHandler [WEAK] + EXPORT INTUART2ERR_IRQHandler [WEAK] + EXPORT INTUART3RX_IRQHandler [WEAK] + EXPORT INTUART3TX_IRQHandler [WEAK] + EXPORT INTUART3ERR_IRQHandler [WEAK] + EXPORT INTUART4RX_IRQHandler [WEAK] + EXPORT INTUART4TX_IRQHandler [WEAK] + EXPORT INTUART4ERR_IRQHandler [WEAK] + EXPORT INTUART5RX_IRQHandler [WEAK] + EXPORT INTUART5TX_IRQHandler [WEAK] + EXPORT INTUART5ERR_IRQHandler [WEAK] + EXPORT INTFUART0_IRQHandler [WEAK] + EXPORT INTFUART1_IRQHandler [WEAK] + EXPORT INTI2C0NST_IRQHandler [WEAK] + EXPORT INTI2C0ATX_IRQHandler [WEAK] + EXPORT INTI2C0BRX_IRQHandler [WEAK] + EXPORT INTI2C0NA_IRQHandler [WEAK] + EXPORT INTI2C1NST_IRQHandler [WEAK] + EXPORT INTI2C1ATX_IRQHandler [WEAK] + EXPORT INTI2C1BRX_IRQHandler [WEAK] + EXPORT INTI2C1NA_IRQHandler [WEAK] + EXPORT INTI2C2NST_IRQHandler [WEAK] + EXPORT INTI2C2ATX_IRQHandler [WEAK] + EXPORT INTI2C2BRX_IRQHandler [WEAK] + EXPORT INTI2C2NA_IRQHandler [WEAK] + EXPORT INTI2C3NST_IRQHandler [WEAK] + EXPORT INTI2C3ATX_IRQHandler [WEAK] + EXPORT INTI2C3BRX_IRQHandler [WEAK] + EXPORT INTI2C3NA_IRQHandler [WEAK] + EXPORT INTI2C4NST_IRQHandler [WEAK] + EXPORT INTI2C4ATX_IRQHandler [WEAK] + EXPORT INTI2C4BRX_IRQHandler [WEAK] + EXPORT INTI2C4NA_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTADAHP_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + EXPORT INTFLCRDY_IRQHandler [WEAK] + EXPORT INTMDMAABERR_IRQHandler [WEAK] + EXPORT INTMDMAADERR_IRQHandler [WEAK] + EXPORT INTI2S0SI_IRQHandler [WEAK] + EXPORT INTI2S0SIERR_IRQHandler [WEAK] + EXPORT INTI2S0SO_IRQHandler [WEAK] + EXPORT INTI2S0SOERR_IRQHandler [WEAK] + EXPORT INTI2S1SI_IRQHandler [WEAK] + EXPORT INTI2S1SIERR_IRQHandler [WEAK] + EXPORT INTI2S1SO_IRQHandler [WEAK] + EXPORT INTI2S1SOERR_IRQHandler [WEAK] + EXPORT INTFIR0_IRQHandler [WEAK] + EXPORT INTTSSI0RX_IRQHandler [WEAK] + EXPORT INTTSSI0TX_IRQHandler [WEAK] + EXPORT INTTSSI0ERR_IRQHandler [WEAK] + EXPORT INTTSSI1RX_IRQHandler [WEAK] + EXPORT INTTSSI1TX_IRQHandler [WEAK] + EXPORT INTTSSI1ERR_IRQHandler [WEAK] + EXPORT INTEMA_IRQHandler [WEAK] + EXPORT INTEMAMP_IRQHandler [WEAK] + EXPORT INTCAN0RX_IRQHandler [WEAK] + EXPORT INTCAN0TX_IRQHandler [WEAK] + EXPORT INTCAN0GLB_IRQHandler [WEAK] + EXPORT INTCAN1RX_IRQHandler [WEAK] + EXPORT INTCAN1TX_IRQHandler [WEAK] + EXPORT INTCAN1GLB_IRQHandler [WEAK] + EXPORT INTUSBOTGA_IRQHandler [WEAK] + EXPORT INTUSBOTGAWK_IRQHandler [WEAK] + EXPORT INTUSBOTGB_IRQHandler [WEAK] + EXPORT INTUSBOTGBWK_IRQHandler [WEAK] + EXPORT INTT32A14_A_IRQHandler [WEAK] + EXPORT INTT32A14_B_IRQHandler [WEAK] + EXPORT INTT32A14_CT_IRQHandler [WEAK] + EXPORT INTT32A15_A_IRQHandler [WEAK] + EXPORT INTT32A15_B_IRQHandler [WEAK] + EXPORT INTT32A15_C_IRQHandler [WEAK] + EXPORT INTMDMAADISR_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INTRTC_IRQHandler +INTCEC0RX_IRQHandler +INTCEC0TX_IRQHandler +INTISDA_IRQHandler +INTISDB_IRQHandler +INTISDC_IRQHandler +INTRMC0_IRQHandler +INTRMC1_IRQHandler +INTLTTMR0_IRQHandler +INTHDMAATC_IRQHandler +INTHDMAAERR_IRQHandler +INTHDMABTC_IRQHandler +INTHDMABERR_IRQHandler +INTMDMAATC_IRQHandler +INTT32A00_A_CT_IRQHandler +INTT32A00_B_C01_CPC_IRQHandler +INTT32A01_A_CT_IRQHandler +INTT32A01_B_C01_CPC_IRQHandler +INTT32A02_A_CT_IRQHandler +INTT32A02_B_C01_CPC_IRQHandler +INTT32A03_A_CT_IRQHandler +INTT32A03_B_C01_CPC_IRQHandler +INTT32A04_A_CT_IRQHandler +INTT32A04_B_C01_CPC_IRQHandler +INTT32A05_A_CT_IRQHandler +INTT32A05_B_C01_CPC_IRQHandler +INTT32A06_A_CT_IRQHandler +INTT32A06_B_C01_CPC_IRQHandler +INTT32A07_A_CT_IRQHandler +INTT32A07_B_C01_CPC_IRQHandler +INTT32A08_A_CT_IRQHandler +INTT32A08_B_C01_CPC_IRQHandler +INTT32A09_A_CT_IRQHandler +INTT32A09_B_C01_CPC_IRQHandler +INTT32A10_A_CT_IRQHandler +INTT32A10_B_C01_CPC_IRQHandler +INTT32A11_A_CT_IRQHandler +INTT32A11_B_C01_CPC_IRQHandler +INTT32A12_A_CT_IRQHandler +INTT32A12_B_C01_CPC_IRQHandler +INTT32A13_A_CT_IRQHandler +INTT32A13_B_C01_CPC_IRQHandler +INTEMG0_IRQHandler +INTOVV0_IRQHandler +INTPWM0_IRQHandler +INTT0RX_IRQHandler +INTT0TX_IRQHandler +INTT0ERR_IRQHandler +INTT1RX_IRQHandler +INTT1TX_IRQHandler +INTT1ERR_IRQHandler +INTT2RX_IRQHandler +INTT2TX_IRQHandler +INTT2ERR_IRQHandler +INTT3RX_IRQHandler +INTT3TX_IRQHandler +INTT3ERR_IRQHandler +INTT4RX_IRQHandler +INTT4TX_IRQHandler +INTT4ERR_IRQHandler +INTT5RX_IRQHandler +INTT5TX_IRQHandler +INTT5ERR_IRQHandler +INTT6RX_IRQHandler +INTT6TX_IRQHandler +INTT6ERR_IRQHandler +INTT7RX_IRQHandler +INTT7TX_IRQHandler +INTT7ERR_IRQHandler +INTT8RX_IRQHandler +INTT8TX_IRQHandler +INTT8ERR_IRQHandler +INTSMI0_IRQHandler +INTUART0RX_IRQHandler +INTUART0TX_IRQHandler +INTUART0ERR_IRQHandler +INTUART1RX_IRQHandler +INTUART1TX_IRQHandler +INTUART1ERR_IRQHandler +INTUART2RX_IRQHandler +INTUART2TX_IRQHandler +INTUART2ERR_IRQHandler +INTUART3RX_IRQHandler +INTUART3TX_IRQHandler +INTUART3ERR_IRQHandler +INTUART4RX_IRQHandler +INTUART4TX_IRQHandler +INTUART4ERR_IRQHandler +INTUART5RX_IRQHandler +INTUART5TX_IRQHandler +INTUART5ERR_IRQHandler +INTFUART0_IRQHandler +INTFUART1_IRQHandler +INTI2C0NST_IRQHandler +INTI2C0ATX_IRQHandler +INTI2C0BRX_IRQHandler +INTI2C0NA_IRQHandler +INTI2C1NST_IRQHandler +INTI2C1ATX_IRQHandler +INTI2C1BRX_IRQHandler +INTI2C1NA_IRQHandler +INTI2C2NST_IRQHandler +INTI2C2ATX_IRQHandler +INTI2C2BRX_IRQHandler +INTI2C2NA_IRQHandler +INTI2C3NST_IRQHandler +INTI2C3ATX_IRQHandler +INTI2C3BRX_IRQHandler +INTI2C3NA_IRQHandler +INTI2C4NST_IRQHandler +INTI2C4ATX_IRQHandler +INTI2C4BRX_IRQHandler +INTI2C4NA_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTADAHP_IRQHandler +INTFLDRDY_IRQHandler +INTFLCRDY_IRQHandler +INTMDMAABERR_IRQHandler +INTMDMAADERR_IRQHandler +INTI2S0SI_IRQHandler +INTI2S0SIERR_IRQHandler +INTI2S0SO_IRQHandler +INTI2S0SOERR_IRQHandler +INTI2S1SI_IRQHandler +INTI2S1SIERR_IRQHandler +INTI2S1SO_IRQHandler +INTI2S1SOERR_IRQHandler +INTFIR0_IRQHandler +INTTSSI0RX_IRQHandler +INTTSSI0TX_IRQHandler +INTTSSI0ERR_IRQHandler +INTTSSI1RX_IRQHandler +INTTSSI1TX_IRQHandler +INTTSSI1ERR_IRQHandler +INTEMA_IRQHandler +INTEMAMP_IRQHandler +INTCAN0RX_IRQHandler +INTCAN0TX_IRQHandler +INTCAN0GLB_IRQHandler +INTCAN1RX_IRQHandler +INTCAN1TX_IRQHandler +INTCAN1GLB_IRQHandler +INTUSBOTGA_IRQHandler +INTUSBOTGAWK_IRQHandler +INTUSBOTGB_IRQHandler +INTUSBOTGBWK_IRQHandler +INTT32A14_A_IRQHandler +INTT32A14_B_IRQHandler +INTT32A14_CT_IRQHandler +INTT32A15_A_IRQHandler +INTT32A15_B_IRQHandler +INTT32A15_C_IRQHandler +INTMDMAADISR_IRQHandler + + B . + + ENDP + + + ALIGN + + + + + + + + + + + + END + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_ARM_STD/tmpm4nrf20fg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_ARM_STD/tmpm4nrf20fg.sct new file mode 100644 index 0000000..02f269a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_ARM_STD/tmpm4nrf20fg.sct @@ -0,0 +1,84 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +/* + * Copyright(C) 2021, Toshiba Electronic Device Solutions Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +;; TMPM4NRF20FG scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) +;; Compatible with ISSM model + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x000200000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x40000 +#endif + + +#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE + +#define VECTOR_SIZE 0x300 + +; TMPM4NR: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x40000) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region +{ + ER_IROM1 MBED_APP_START MBED_APP_SIZE + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 MBED_RAM_START + VECTOR_SIZE (MBED_RAM_SIZE - VECTOR_SIZE - Stack_Size) + { + txz_fc.o (+RO) + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4NR.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4NR.S new file mode 100644 index 0000000..eaae715 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/startup_TMPM4NR.S @@ -0,0 +1,599 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4NR.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4NR' Device Series +; * @version V1.0.0 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 +; ******************************************************************************* +; */ +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long INT00_IRQHandler // 0: Interrupt pin 00a/00b + .long INT01_IRQHandler // 1: Interrupt pin 01a/00b + .long INT02_IRQHandler // 2: Interrupt pin 02a/00b + .long INT03_IRQHandler // 3: Interrupt pin 03a/03b + .long INT04_IRQHandler // 4: Interrupt pin 04a/04b + .long INT05_IRQHandler // 5: Interrupt pin 05a/05b + .long INT06_IRQHandler // 6: Interrupt pin 06a/06b + .long INT07_IRQHandler // 7: Interrupt pin 07a/07b + .long INT08_IRQHandler // 8: Interrupt pin 08a/08b + .long INT09_IRQHandler // 9: Interrupt pin 09a/09b + .long INT10_IRQHandler // 10: Interrupt pin 10a/10b + .long INT11_IRQHandler // 11: Interrupt pin 11a/11b + .long INT12_IRQHandler // 12: Interrupt pin 12a/12b + .long INT13_IRQHandler // 13: Interrupt pin 13a/13b + .long INT14_IRQHandler // 14: Interrupt pin 14a/14b + .long INT15_IRQHandler // 15: Interrupt pin 15a/15b + .long INTRTC_IRQHandler // 16: Real time clock(XHz) interrupt + .long INTCEC0RX_IRQHandler // 17: CEC reception interrupt (channel 0) + .long INTCEC0TX_IRQHandler // 18: CEC transmission interrupt (channel 0) + .long INTISDA_IRQHandler // 19: Interval Sensing Detector interrupt (Unit A) + .long INTISDB_IRQHandler // 20: Interval Sensing Detector interrupt (Unit B) + .long INTISDC_IRQHandler // 21: Interval Sensing Detector interrupt (Unit C) + .long INTRMC0_IRQHandler // 22: Remote control reception interrupt 0 + .long INTRMC1_IRQHandler // 23: Remote control reception interrupt 1 + .long INTLTTMR0_IRQHandler // 24: Long Term Timer Interrupt(channel 0) + .long INTHDMAATC_IRQHandler // 25: HDMA complete of transfer(Unit A) + .long INTHDMAAERR_IRQHandler // 26: HDMA transfer error(Unit A) + .long INTHDMABTC_IRQHandler // 27: HDMA end of transfer(Unit B) + .long INTHDMABERR_IRQHandler // 28: HDMA transfer error(Unit B) + .long INTMDMAATC_IRQHandler // 29: MDMA complete of transfer(Unit A) + .long INTT32A00_A_CT_IRQHandler // 30: T32A00 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A00_B_C01_CPC_IRQHandler// 31: T32A00 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A01_A_CT_IRQHandler // 32: T32A01 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A01_B_C01_CPC_IRQHandler// 33: T32A01 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A02_A_CT_IRQHandler // 34: T32A02 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A02_B_C01_CPC_IRQHandler// 35: T32A02 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A03_A_CT_IRQHandler // 36: T32A03 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A03_B_C01_CPC_IRQHandler// 37: T32A03 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A04_A_CT_IRQHandler // 38: T32A04 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A04_B_C01_CPC_IRQHandler// 39: T32A04 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A05_A_CT_IRQHandler // 40: T32A05 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A05_B_C01_CPC_IRQHandler// 41: T32A05 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A06_A_CT_IRQHandler // 42: T32A06 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A06_B_C01_CPC_IRQHandler// 43: T32A06 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A07_A_CT_IRQHandler // 44: T32A07 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A07_B_C01_CPC_IRQHandler// 45: T32A07 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A08_A_CT_IRQHandler // 46: T32A08 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A08_B_C01_CPC_IRQHandler// 47: T32A08 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A09_A_CT_IRQHandler // 48: T32A09 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A09_B_C01_CPC_IRQHandler// 49: T32A09 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A10_A_CT_IRQHandler // 50: T32A10 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A10_B_C01_CPC_IRQHandler// 51: T32A10 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A11_A_CT_IRQHandler // 52: T32A11 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A11_B_C01_CPC_IRQHandler// 53: T32A11 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A12_A_CT_IRQHandler // 54: T32A12 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A12_B_C01_CPC_IRQHandler// 55: T32A12 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTT32A13_A_CT_IRQHandler // 56: T32A13 TimerA all interrupt /TimerC match, overflow, and underflow + .long INTT32A13_B_C01_CPC_IRQHandler// 57: T32A13 TimerB all interrupt /TimerC capture C0_C1, pulse count interrupt + .long INTEMG0_IRQHandler // 58: PMD0 EMG interrupt + .long INTOVV0_IRQHandler // 59: PMD0 OVV interrupt + .long INTPWM0_IRQHandler // 60: PMD0 interrupt + .long INTT0RX_IRQHandler // 61: TSPI/SIO reception (channel 0) interrupt + .long INTT0TX_IRQHandler // 62: TSPI/SIO transmit (channel 0) interrupt + .long INTT0ERR_IRQHandler // 63: TSPI/SIO error (channel 0) interrupt + .long INTT1RX_IRQHandler // 64: TSPI/SIO reception (channel 1) interrupt + .long INTT1TX_IRQHandler // 65: TSPI/SIO transmit (channel 1) interrupt + .long INTT1ERR_IRQHandler // 66: TSPI/SIO error (channel 1) interrupt + .long INTT2RX_IRQHandler // 67: TSPI/SIO reception (channel 2) interrupt + .long INTT2TX_IRQHandler // 68: TSPI/SIO transmit (channel 2) interrupt + .long INTT2ERR_IRQHandler // 69: TSPI/SIO error (channel 2) interrupt + .long INTT3RX_IRQHandler // 70: TSPI/SIO reception (channel 3) interrupt + .long INTT3TX_IRQHandler // 71: TSPI/SIO transmit (channel 3) interrupt + .long INTT3ERR_IRQHandler // 72: TSPI/SIO error (channel 3) interrupt + .long INTT4RX_IRQHandler // 73: TSPI/SIO reception (channel 4) interrupt + .long INTT4TX_IRQHandler // 74: TSPI/SIO transmit (channel 4) interrupt + .long INTT4ERR_IRQHandler // 75: TSPI/SIO error (channel 4) interrupt + .long INTT5RX_IRQHandler // 76: TSPI/SIO reception (channel 5) interrupt + .long INTT5TX_IRQHandler // 77: TSPI/SIO transmit (channel 5) interrupt + .long INTT5ERR_IRQHandler // 78: TSPI/SIO error (channel 5) interrupt + .long INTT6RX_IRQHandler // 79: TSPI/SIO reception (channel 6) interrupt + .long INTT6TX_IRQHandler // 80: TSPI/SIO transmit (channel 6) interrupt + .long INTT6ERR_IRQHandler // 81: TSPI/SIO error (channel 6) interrupt + .long INTT7RX_IRQHandler // 82: TSPI/SIO reception (channel 7) interrupt + .long INTT7TX_IRQHandler // 83: TSPI/SIO transmit (channel 7) interrupt + .long INTT7ERR_IRQHandler // 84: TSPI/SIO error (channel 7) interrupt + .long INTT8RX_IRQHandler // 85: TSPI/SIO reception (channel 8) interrupt + .long INTT8TX_IRQHandler // 86: TSPI/SIO transmit (channel 8) interrupt + .long INTT8ERR_IRQHandler // 87: TSPI/SIO error (channel 8) interrupt + .long INTSMI0_IRQHandler // 88: Serial Memory Interface interrupt + .long INTUART0RX_IRQHandler // 89: UART reception (channel 0) interrupt + .long INTUART0TX_IRQHandler // 90: UART transmit (channel 0) interrupt + .long INTUART0ERR_IRQHandler // 91: UART error (channel 0) interrupt + .long INTUART1RX_IRQHandler // 92: UART reception (channel 1) interrupt + .long INTUART1TX_IRQHandler // 93: UART transmit (channel 1) interrupt + .long INTUART1ERR_IRQHandler // 94: UART error (channel 1) interrupt + .long INTUART2RX_IRQHandler // 95: UART reception (channel 2) interrupt + .long INTUART2TX_IRQHandler // 96: UART transmit (channel 2) interrupt + .long INTUART2ERR_IRQHandler // 97: UART error (channel 2) interrupt + .long INTUART3RX_IRQHandler // 98: UART reception (channel 3) interrupt + .long INTUART3TX_IRQHandler // 99: UART transmit (channel 3) interrupt + .long INTUART3ERR_IRQHandler // 100: UART error (channel 3) interrupt + .long INTUART4RX_IRQHandler // 101: UART reception (channel 4) interrupt + .long INTUART4TX_IRQHandler // 102: UART transmit (channel 4) interrupt + .long INTUART4ERR_IRQHandler // 103: UART error (channel 4) interrupt + .long INTUART5RX_IRQHandler // 104: UART reception (channel 5) interrupt + .long INTUART5TX_IRQHandler // 105: UART transmit (channel 5) interrupt + .long INTUART5ERR_IRQHandler // 106: UART error (channel 5) interrupt + .long INTFUART0_IRQHandler // 107: FUART interrupt(channel 0) + .long INTFUART1_IRQHandler // 108: FUART interrupt(channel 1) + .long INTI2C0NST_IRQHandler // 109: I2C0 interrupt / EI2C0 status interrupt + .long INTI2C0ATX_IRQHandler // 110: I2C0 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C0BRX_IRQHandler // 111: I2C0 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C0NA_IRQHandler // 112: I2C0 NACK detection interrupt + .long INTI2C1NST_IRQHandler // 113: I2C1 interrupt / EI2C0 status interrupt + .long INTI2C1ATX_IRQHandler // 114: I2C1 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C1BRX_IRQHandler // 115: I2C1 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C1NA_IRQHandler // 116: I2C1 NACK detection interrupt + .long INTI2C2NST_IRQHandler // 117: I2C2 interrupt / EI2C0 status interrupt + .long INTI2C2ATX_IRQHandler // 118: I2C2 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C2BRX_IRQHandler // 119: I2C2 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C2NA_IRQHandler // 120: I2C2 NACK detection interrupt + .long INTI2C3NST_IRQHandler // 121: I2C3 interrupt / EI2C0 status interrupt + .long INTI2C3ATX_IRQHandler // 122: I2C3 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C3BRX_IRQHandler // 123: I2C3 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C3NA_IRQHandler // 124: I2C3 NACK detection interrupt + .long INTI2C4NST_IRQHandler // 125: I2C4 interrupt / EI2C0 status interrupt + .long INTI2C4ATX_IRQHandler // 126: I2C4 arbitration lost detection interrupt / EI2C0 transmit buffer empty interrupt + .long INTI2C4BRX_IRQHandler // 127: I2C4 bus free detection interrupt / EI2C0receive buffer empty interrupt + .long INTI2C4NA_IRQHandler // 128: I2C4 NACK detection interrupt + .long INTADACP0_IRQHandler // 129: ADC conversion monitoring function interrupt 0 + .long INTADACP1_IRQHandler // 130: ADC conversion monitoring function interrupt 1 + .long INTADATRG_IRQHandler // 131: ADC conversion triggered by General purpose is finished + .long INTADASGL_IRQHandler // 132: ADC conversion triggered by Single program is finished + .long INTADACNT_IRQHandler // 133: ADC conversion triggered by Continuity program is finished + .long INTADAHP_IRQHandler // 134: ADC high priority AD conversion interrupt + .long INTFLDRDY_IRQHandler // 135: Data FLASH Ready interrupt + .long INTFLCRDY_IRQHandler // 136: Code FLASH Area0/1 Ready interrupt + .long 0 // 137: Reserved + .long 0 // 138: Reserved + .long INTMDMAABERR_IRQHandler // 139: MDMA bus error(Unit A) interrupt + .long INTMDMAADERR_IRQHandler // 140: MDMA descriptor error(Unit A) interrupt + .long INTI2S0SI_IRQHandler // 141: I2S ch0 SI transfer end interrupt + .long INTI2S0SIERR_IRQHandler // 142: I2S ch0 SI error interrupt + .long INTI2S0SO_IRQHandler // 143: I2S ch0 SO transfer end interrupt + .long INTI2S0SOERR_IRQHandler // 144: I2S ch0 SO error interrupt + .long INTI2S1SI_IRQHandler // 145: I2S ch1 SI transfer end interrupt + .long INTI2S1SIERR_IRQHandler // 146: I2S ch1 SI error interrupt + .long INTI2S1SO_IRQHandler // 147: I2S ch1 SO transfer end interrupt + .long INTI2S1SOERR_IRQHandler // 148: I2S ch1 SO error interrupt + .long INTFIR0_IRQHandler // 149: FIR ch0 interrupt + .long INTTSSI0RX_IRQHandler // 150: TSSI ch0 RX interrupt + .long INTTSSI0TX_IRQHandler // 151: TSSI ch0 TX interrupt + .long INTTSSI0ERR_IRQHandler // 152: TSSI ch0 error interrupt + .long INTTSSI1RX_IRQHandler // 153: TSSI ch1 RX interrupt + .long INTTSSI1TX_IRQHandler // 154: TSSI ch1 TX interrupt + .long INTTSSI1ERR_IRQHandler // 155: TSSI ch1 error interrupt + .long INTEMA_IRQHandler // 156: Ether MAC interrupt + .long INTEMAMP_IRQHandler // 157: Ether MAC magic packet detection interrupt + .long INTCAN0RX_IRQHandler // 158: CAN ch0 receive interrupt + .long INTCAN0TX_IRQHandler // 159: CAN ch0 transmission interrupt + .long INTCAN0GLB_IRQHandler // 160: CAN ch0 Global interrupt + .long INTCAN1RX_IRQHandler // 161: CAN ch1 receive interrupt + .long INTCAN1TX_IRQHandler // 162: CAN ch1 transmission interrupt + .long INTCAN1GLB_IRQHandler // 163: CAN ch1 Global interrupt + .long INTUSBOTGA_IRQHandler // 164: USB OTG unit A interrupt + .long INTUSBOTGAWK_IRQHandler // 165: USB OTG unit A Wakeup interrupt + .long INTUSBOTGB_IRQHandler // 166: USB OTG unit B interrupt + .long INTUSBOTGBWK_IRQHandler // 167: USB OTG unit B Wakeup interrupt + .long INTT32A14_A_IRQHandler // 168: T32A14 TimerA all interrupt + .long INTT32A14_B_IRQHandler // 169: T32A14 TimerB all interrupt + .long INTT32A14_CT_IRQHandler // 170: T32A14 TimerC match, overflow, and underflow Interrupt + .long INTT32A15_A_IRQHandler // 171: T32A15 TimerA all interrupt + .long INTT32A15_B_IRQHandler // 172: T32A15 TimerB all interrupt + .long INTT32A15_C_IRQHandler // 173: T32A15 TimerC all interrupt + .long INTMDMAADISR_IRQHandler // 174: MDMAC unit A Descriptor interrupt + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INTRTC_IRQHandler + def_irq_handler INTCEC0RX_IRQHandler + def_irq_handler INTCEC0TX_IRQHandler + def_irq_handler INTISDA_IRQHandler + def_irq_handler INTISDB_IRQHandler + def_irq_handler INTISDC_IRQHandler + def_irq_handler INTRMC0_IRQHandler + def_irq_handler INTRMC1_IRQHandler + def_irq_handler INTLTTMR0_IRQHandler + def_irq_handler INTHDMAATC_IRQHandler + def_irq_handler INTHDMAAERR_IRQHandler + def_irq_handler INTHDMABTC_IRQHandler + def_irq_handler INTHDMABERR_IRQHandler + def_irq_handler INTMDMAATC_IRQHandler + def_irq_handler INTT32A00_A_CT_IRQHandler + def_irq_handler INTT32A00_B_C01_CPC_IRQHandler + def_irq_handler INTT32A01_A_CT_IRQHandler + def_irq_handler INTT32A01_B_C01_CPC_IRQHandler + def_irq_handler INTT32A02_A_CT_IRQHandler + def_irq_handler INTT32A02_B_C01_CPC_IRQHandler + def_irq_handler INTT32A03_A_CT_IRQHandler + def_irq_handler INTT32A03_B_C01_CPC_IRQHandler + def_irq_handler INTT32A04_A_CT_IRQHandler + def_irq_handler INTT32A04_B_C01_CPC_IRQHandler + def_irq_handler INTT32A05_A_CT_IRQHandler + def_irq_handler INTT32A05_B_C01_CPC_IRQHandler + def_irq_handler INTT32A06_A_CT_IRQHandler + def_irq_handler INTT32A06_B_C01_CPC_IRQHandler + def_irq_handler INTT32A07_A_CT_IRQHandler + def_irq_handler INTT32A07_B_C01_CPC_IRQHandler + def_irq_handler INTT32A08_A_CT_IRQHandler + def_irq_handler INTT32A08_B_C01_CPC_IRQHandler + def_irq_handler INTT32A09_A_CT_IRQHandler + def_irq_handler INTT32A09_B_C01_CPC_IRQHandler + def_irq_handler INTT32A10_A_CT_IRQHandler + def_irq_handler INTT32A10_B_C01_CPC_IRQHandler + def_irq_handler INTT32A11_A_CT_IRQHandler + def_irq_handler INTT32A11_B_C01_CPC_IRQHandler + def_irq_handler INTT32A12_A_CT_IRQHandler + def_irq_handler INTT32A12_B_C01_CPC_IRQHandler + def_irq_handler INTT32A13_A_CT_IRQHandler + def_irq_handler INTT32A13_B_C01_CPC_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTPWM0_IRQHandler + def_irq_handler INTT0RX_IRQHandler + def_irq_handler INTT0TX_IRQHandler + def_irq_handler INTT0ERR_IRQHandler + def_irq_handler INTT1RX_IRQHandler + def_irq_handler INTT1TX_IRQHandler + def_irq_handler INTT1ERR_IRQHandler + def_irq_handler INTT2RX_IRQHandler + def_irq_handler INTT2TX_IRQHandler + def_irq_handler INTT2ERR_IRQHandler + def_irq_handler INTT3RX_IRQHandler + def_irq_handler INTT3TX_IRQHandler + def_irq_handler INTT3ERR_IRQHandler + def_irq_handler INTT4RX_IRQHandler + def_irq_handler INTT4TX_IRQHandler + def_irq_handler INTT4ERR_IRQHandler + def_irq_handler INTT5RX_IRQHandler + def_irq_handler INTT5TX_IRQHandler + def_irq_handler INTT5ERR_IRQHandler + def_irq_handler INTT6RX_IRQHandler + def_irq_handler INTT6TX_IRQHandler + def_irq_handler INTT6ERR_IRQHandler + def_irq_handler INTT7RX_IRQHandler + def_irq_handler INTT7TX_IRQHandler + def_irq_handler INTT7ERR_IRQHandler + def_irq_handler INTT8RX_IRQHandler + def_irq_handler INTT8TX_IRQHandler + def_irq_handler INTT8ERR_IRQHandler + def_irq_handler INTSMI0_IRQHandler + def_irq_handler INTUART0RX_IRQHandler + def_irq_handler INTUART0TX_IRQHandler + def_irq_handler INTUART0ERR_IRQHandler + def_irq_handler INTUART1RX_IRQHandler + def_irq_handler INTUART1TX_IRQHandler + def_irq_handler INTUART1ERR_IRQHandler + def_irq_handler INTUART2RX_IRQHandler + def_irq_handler INTUART2TX_IRQHandler + def_irq_handler INTUART2ERR_IRQHandler + def_irq_handler INTUART3RX_IRQHandler + def_irq_handler INTUART3TX_IRQHandler + def_irq_handler INTUART3ERR_IRQHandler + def_irq_handler INTUART4RX_IRQHandler + def_irq_handler INTUART4TX_IRQHandler + def_irq_handler INTUART4ERR_IRQHandler + def_irq_handler INTUART5RX_IRQHandler + def_irq_handler INTUART5TX_IRQHandler + def_irq_handler INTUART5ERR_IRQHandler + def_irq_handler INTFUART0_IRQHandler + def_irq_handler INTFUART1_IRQHandler + def_irq_handler INTI2C0NST_IRQHandler + def_irq_handler INTI2C0ATX_IRQHandler + def_irq_handler INTI2C0BRX_IRQHandler + def_irq_handler INTI2C0NA_IRQHandler + def_irq_handler INTI2C1NST_IRQHandler + def_irq_handler INTI2C1ATX_IRQHandler + def_irq_handler INTI2C1BRX_IRQHandler + def_irq_handler INTI2C1NA_IRQHandler + def_irq_handler INTI2C2NST_IRQHandler + def_irq_handler INTI2C2ATX_IRQHandler + def_irq_handler INTI2C2BRX_IRQHandler + def_irq_handler INTI2C2NA_IRQHandler + def_irq_handler INTI2C3NST_IRQHandler + def_irq_handler INTI2C3ATX_IRQHandler + def_irq_handler INTI2C3BRX_IRQHandler + def_irq_handler INTI2C3NA_IRQHandler + def_irq_handler INTI2C4NST_IRQHandler + def_irq_handler INTI2C4ATX_IRQHandler + def_irq_handler INTI2C4BRX_IRQHandler + def_irq_handler INTI2C4NA_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTADAHP_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + def_irq_handler INTFLCRDY_IRQHandler + def_irq_handler INTMDMAABERR_IRQHandler + def_irq_handler INTMDMAADERR_IRQHandler + def_irq_handler INTI2S0SI_IRQHandler + def_irq_handler INTI2S0SIERR_IRQHandler + def_irq_handler INTI2S0SO_IRQHandler + def_irq_handler INTI2S0SOERR_IRQHandler + def_irq_handler INTI2S1SI_IRQHandler + def_irq_handler INTI2S1SIERR_IRQHandler + def_irq_handler INTI2S1SO_IRQHandler + def_irq_handler INTI2S1SOERR_IRQHandler + def_irq_handler INTFIR0_IRQHandler + def_irq_handler INTTSSI0RX_IRQHandler + def_irq_handler INTTSSI0TX_IRQHandler + def_irq_handler INTTSSI0ERR_IRQHandler + def_irq_handler INTTSSI1RX_IRQHandler + def_irq_handler INTTSSI1TX_IRQHandler + def_irq_handler INTTSSI1ERR_IRQHandler + def_irq_handler INTEMA_IRQHandler + def_irq_handler INTEMAMP_IRQHandler + def_irq_handler INTCAN0RX_IRQHandler + def_irq_handler INTCAN0TX_IRQHandler + def_irq_handler INTCAN0GLB_IRQHandler + def_irq_handler INTCAN1RX_IRQHandler + def_irq_handler INTCAN1TX_IRQHandler + def_irq_handler INTCAN1GLB_IRQHandler + def_irq_handler INTUSBOTGA_IRQHandler + def_irq_handler INTUSBOTGAWK_IRQHandler + def_irq_handler INTUSBOTGB_IRQHandler + def_irq_handler INTUSBOTGBWK_IRQHandler + def_irq_handler INTT32A14_A_IRQHandler + def_irq_handler INTT32A14_B_IRQHandler + def_irq_handler INTT32A14_CT_IRQHandler + def_irq_handler INTT32A15_A_IRQHandler + def_irq_handler INTT32A15_B_IRQHandler + def_irq_handler INTT32A15_C_IRQHandler + def_irq_handler INTMDMAADISR_IRQHandler + + + .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/tmpm4nrf20fg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/tmpm4nrf20fg.ld new file mode 100644 index 0000000..d1d0cfe --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/TOOLCHAIN_GCC_ARM/tmpm4nrf20fg.ld @@ -0,0 +1,197 @@ +/* + * Copyright(C) 2021, Toshiba Electronic Device Solutions Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Linker script for Toshiba TMPM4NR */ + +/* Linker script to configure memory regions. */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + /* 8_byte_aligned((175 + 16) vect * 4 bytes) = 8_byte_aligned(0x2FC) = 0x300 */ + RAM (rwx) : ORIGIN = (0x20000000 + 0x300), LENGTH = (256K - 0x300) +} + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + *(.ram_func*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis.h new file mode 100644 index 0000000..a2d7fdd --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM4NR.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis_nvic.h new file mode 100644 index 0000000..80cbc9b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/cmsis_nvic.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + + +#if defined(__ICCARM__) +#pragma section=".intvec" +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) +#elif defined(__CC_ARM) +extern uint32_t Load$$LR$$LR_IROM1$$Base[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) +#elif defined(__GNUC__) +extern uint32_t vectors[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors) +#else +#error "Flash vector address not set for this toolchain" +#endif + + +#define NVIC_NUM_VECTORS (191) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/system_TMPM4Nx.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/system_TMPM4Nx.c new file mode 100644 index 0000000..29ec199 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/system_TMPM4Nx.c @@ -0,0 +1,342 @@ +/** + ******************************************************************************* + * @file system_TMPM4Nx.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM4Nx' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#include "TMPM4Nx.h" +#include "txz_flash.h" +#include "txz_hal.h" + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ +#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ +#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ +#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ +#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ +#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ + +#define STBYCR_Val (0x00000000UL) + +#define CG_8M_MUL_24_FPLL (0x00245030UL<<8U) /* fPLL = 8MHz * 24 */ +#define CG_10M_MUL_19_1875_FPLL (0x002E9626UL<<8U) /* fPLL = 10MHz * 19.1875 */ +#define CG_12M_MUL_16_FPLL (0x0036D020UL<<8U) /* fPLL = 12MHz * 16 */ +#define CG_16M_MUL_12_FPLL (0x00495018UL<<8U) /* fPLL = 16MHz * 12 */ +#define CG_24M_MUL_8_FPLL (0x006D9010UL<<8U) /* fPLL = 24MHz * 8 */ + +#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) +#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) +#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) +#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) + +#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) +#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) +#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) + +#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) +#define CG_OSCCR_EOSCEN_SET (0x00000002UL) +#define CG_OSCCR_OSCSEL_SET (0x00000100UL) + +#define CG_WUPHCR_WUON_START_SET (0x00000001UL) + +#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ +#if (CLOCK_SETUP) +#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_12M_MUL_16_FPLL +#else +#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_10M_MUL_19_1875_FPLL +#endif +#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) +#define PLL0SEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define EOSC_8M (8000000UL) +#define EOSC_12M (12000000UL) +#define EOSC_16M (16000000UL) +#define EOSC_24M (24000000UL) +#define IOSC_10M (10000000UL) +#define EXTALH EOSC_12M /* External high-speed oscillator freq */ +#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ +#define EOSC_8M_DIV2_PLLON (192000000UL) /* 8.00MHz * 48.0000 / 2 */ +#define EOSC_12M_DIV2_PLLON (192000000UL) /* 12.00MHz * 32.0000 / 2 */ +#define EOSC_16M_DIV2_PLLON (192000000UL) /* 16.00MHz * 24.0000 / 2 */ +#define EOSC_24M_DIV2_PLLON (192000000UL) /* 24.00MHz * 16.0000 / 2 */ +#define IOSC_10M_DIV2_PLLON (191875000UL) /* 10.00MHz * 38.3750 / 2 */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ +#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ +#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = (warm-up time(us) * IXTALH - 16) / 16 */ +#if (CLOCK_SETUP) +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#else +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#endif + +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (CLOCK_SETUP) +#define CORE_TALH (EXTALH) +#else +#define CORE_TALH (IXTALH) +#endif + +#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ +#if (CORE_TALH == EOSC_8M) /* If input is 8MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_24_FPLL)) +#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 8MHz */ +#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL) +#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#elif (CORE_TALH == EOSC_16M) /* If input is 16MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL) +#define __CORE_CLK EOSC_16M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 16MHz */ +#elif (CORE_TALH == EOSC_24M) /* If input is 24MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL) +#define __CORE_CLK EOSC_24M_DIV2_PLLON /* output clock is 192MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 24MHz */ +#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL) +#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 191.875MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 10MHz */ +#else /* input clock not known */ +#define __CORE_CLK (0U) +#error "Core Oscillator Frequency invalid!" +#endif /* End switch input clock */ +#else +#define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */ +#define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */ +#define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */ +#define __CORE_SYS (__CORE_CLK / 4U ) +#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */ +#define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */ +#define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ +#define __CORE_SYS (0U) +#endif + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ +uint32_t CoreClockInput = 0U; + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ + /* Get Core Clock Frequency */ + uint32_t CoreClock = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pll0sel = 0U; + uint32_t pll0on = 0U; + + CoreClockInput = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = IXTALH; + } + regval = TSB_CG->PLL0SEL; + pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; + pll0on = regval & CG_PLL0SEL_PLL0ON_SET; + if (pll0sel && pll0on) { /* If PLL enabled */ + if (CoreClock == EOSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_24_FPLL) { + CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_16_FPLL) { + CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_16M) { /* If input is 16MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_16M_MUL_12_FPLL) { + CoreClockInput = EOSC_16M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_24M) { /* If input is 24MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_24M_MUL_8_FPLL) { + CoreClockInput = EOSC_24M_DIV2_PLLON; /* output clock is 192MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == IOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_19_1875_FPLL) { + CoreClockInput = IOSC_10M_DIV2_PLLON; /* output clock is 191.875MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { /* If PLL not used */ + CoreClockInput = CoreClock; + } + + switch (TSB_CG->SYSCR & 7U) { + case 0U: /* Gear -> fc */ + SystemCoreClock = CoreClockInput; + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + SystemCoreClock = CoreClockInput / 8U; + break; + case 4U: /* Gear -> fc/16 */ + SystemCoreClock = CoreClockInput / 16U; + break; + case 5U: + case 6U: + case 7U: + SystemCoreClock = 0U; + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ +#if (SIWD_SETUP) /* Watchdog Setup */ + /* SIWD Disable */ + TSB_SIWD0->EN = SIWDEN_Val; + TSB_SIWD0->CR = SIWDCR_Val; +#else + /* SIWD Enable (Setting after a Reset) */ +#endif +#if defined ( __CC_ARM ) + /* set Flash Access Control Register */ + Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API); /* copy flash API to RAM */ +#endif + fc_read_clock_set(__CORE_SYS); + fc_ram_con_reg_set(__CORE_SYS); + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = SYSCR_GEAR_Val; + + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET); + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | EXT_CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + while (!TSB_CG_OSCCR_OSCF) { + ; + } /* Confirm CGOSCCR="1" */ + TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; +#else + /* Internal HOSC Enable (Setting after a Reset) */ +#endif + + TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set */ + while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val)) + != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) { + ; + } + + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLL0SEL_Ready; + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Lockup */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + while (!TSB_CG_PLL0SEL_PLL0ST) { + ; + } /*Confirm CGPLL0SEL = "1" */ +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/system_TMPM4Nx.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/system_TMPM4Nx.h new file mode 100644 index 0000000..c687711 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/device/system_TMPM4Nx.h @@ -0,0 +1,66 @@ +/** + ***************************************************************************** + * @file system_TMPM4Nx.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4Nx' Device Series + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM4Nx_H +#define __SYSTEM_TMPM4Nx_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CoreClockInput; /*!< High speed Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/flash_api.c new file mode 100644 index 0000000..8bb1530 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/flash_api.c @@ -0,0 +1,130 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "flash_api.h" +#include "mbed_critical.h" +#include "txz_fc.h" + +#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once +#define SECTOR_SIZE (0x8000) // 32KB each sectors or block +#define FLASH_CHIP_SIZE (0x00200000) // Flash chip size is 2048 KByte +#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) + +#define SUCCESS (0U) +#define FAIL (-1) +// IHOSC1EN +#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask +#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable +#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable + +static void internal_hosc_enable(void); + +int32_t flash_init(flash_t *obj) +{ + obj->flash_inited = 0; + obj->flash_inited = 1; + internal_hosc_enable(); // Internal HOSC enable + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + obj->flash_inited = 0; + + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + int status = FAIL; + + if (obj->flash_inited == 0) { + flash_init(obj); + } + + // We need to prevent flash accesses during erase operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t *)address)) { + status = SUCCESS; + } else { + // Do nothing + } + + core_util_critical_section_exit(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int status = SUCCESS; + + address &= MASK_CHIP_ID_FROM_ADD; + + // We need to prevent flash accesses during program operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_write_code_flash((uint32_t *)data, (uint32_t *)address, size)) { + // Do nothing + } else { + status = FAIL; + } + + core_util_critical_section_exit(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { + return SECTOR_SIZE; + } else { + // Do nothing + } + + return MBED_FLASH_INVALID_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return PROGRAM_WRITE_MAX; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FC_CODE_FLASH_ADDRESS_TOP; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_CHIP_SIZE; +} + +static void internal_hosc_enable(void) +{ + uint32_t work; + work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); + TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_api.c new file mode 100644 index 0000000..e123873 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_api.c @@ -0,0 +1,127 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "txz_gpio.h" + +#define GPIO_DATA PIN_DATA(0, 2) +#define ALT_FUNC_GPIO 0 + +_gpio_t gpio_port_add = { + .p_pa_instance = TSB_PA, + .p_pb_instance = TSB_PB, + .p_pc_instance = TSB_PC, + .p_pd_instance = TSB_PD, + .p_pe_instance = TSB_PE, + .p_pf_instance = TSB_PF, + .p_pg_instance = TSB_PG, + .p_ph_instance = TSB_PH, + .p_pj_instance = TSB_PJ, + .p_pk_instance = TSB_PK, + .p_pl_instance = TSB_PL, + .p_pm_instance = TSB_PM, + .p_pn_instance = TSB_PN, + .p_pp_instance = TSB_PP, + .p_pr_instance = TSB_PR, + .p_pt_instance = TSB_PT, + .p_pu_instance = TSB_PU, + .p_pv_instance = TSB_PV, + .p_pw_instance = TSB_PW, + .p_py_instance = TSB_PY +}; + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + + // Return pin mask + return (1 << (pin & 0x07)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + obj->pin_num = PIN_POS(pin); + obj->mask = gpio_set(pin); + obj->port = (PortName) PIN_PORT(pin); + // Enable clock for particular port + TSB_CG->FSYSMENB |= (1 << ((obj->port) + 2)); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + // Set pin mode + pin_mode(obj->pin, mode); +} + +// Set gpio object pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INOUT); + break; + default: + break; + } +} + +void gpio_write(gpio_t *obj, int value) +{ + // Write gpio object pin data + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value); +} + +int gpio_read(gpio_t *obj) +{ + // Read gpio object pin data + gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable + gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val); + return val; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_irq_api.c new file mode 100644 index 0000000..f7549d1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_irq_api.c @@ -0,0 +1,297 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_critical.h" +#include "txz_gpio.h" + +#define CHANNEL_NUM (16) +#define DISABLE (0) +#define ENABLE (1) +#define CLR_INT_FLAG (0xC0) + +const PinMap PinMap_GPIO_IRQ[] = { + {PT3, GPIO_IRQ_0, PIN_DATA(0, 0)}, + {PL0, GPIO_IRQ_1, PIN_DATA(0, 0)}, + {PA0, GPIO_IRQ_2, PIN_DATA(0, 0)}, + {PL6, GPIO_IRQ_3, PIN_DATA(0, 0)}, + {PF0, GPIO_IRQ_4, PIN_DATA(0, 0)}, + {PF7, GPIO_IRQ_5, PIN_DATA(0, 0)}, + {PU2, GPIO_IRQ_6, PIN_DATA(0, 0)}, + {PU3, GPIO_IRQ_7, PIN_DATA(0, 0)}, + {PU4, GPIO_IRQ_8, PIN_DATA(0, 0)}, + {PU5, GPIO_IRQ_9, PIN_DATA(0, 0)}, + {PP6, GPIO_IRQ_A, PIN_DATA(0, 0)}, + {PK1, GPIO_IRQ_B, PIN_DATA(0, 0)}, + {PL4, GPIO_IRQ_C, PIN_DATA(0, 0)}, + {PL5, GPIO_IRQ_D, PIN_DATA(0, 0)}, + {PC6, GPIO_IRQ_E, PIN_DATA(0, 0)}, + {PM4, GPIO_IRQ_F, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +extern _gpio_t gpio_port_add; + +static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; +static CG_INTActiveState CurrentState; + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t); +static void INT_IRQHandler(PinName, uint32_t); + +void INT00_IRQHandler(void) +{ + INT_IRQHandler(PT3, 0); +} + +void INT01_IRQHandler(void) +{ + INT_IRQHandler(PL0, 1); +} + +void INT02_IRQHandler(void) +{ + INT_IRQHandler(PA0, 2); +} + +void INT03_IRQHandler(void) +{ + INT_IRQHandler(PL6, 3); +} + +void INT04_IRQHandler(void) +{ + INT_IRQHandler(PF0, 4); +} + +void INT05_IRQHandler(void) +{ + INT_IRQHandler(PF7, 5); +} + +void INT06_IRQHandler(void) +{ + INT_IRQHandler(PU2, 6); +} + +void INT07_IRQHandler(void) +{ + INT_IRQHandler(PU3, 7); +} + +void INT08_IRQHandler(void) +{ + INT_IRQHandler(PU4, 8); +} + +void INT09_IRQHandler(void) +{ + INT_IRQHandler(PU5, 9); +} + +void INT10_IRQHandler(void) +{ + INT_IRQHandler(PP6, 10); +} + +void INT11_IRQHandler(void) +{ + INT_IRQHandler(PK1, 11); +} + +void INT12_IRQHandler(void) +{ + INT_IRQHandler(PL4, 12); +} +void INT13_IRQHandler(void) +{ + INT_IRQHandler(PL5, 13); +} +void INT14_IRQHandler(void) +{ + INT_IRQHandler(PC6, 14); +} + +void INT15_IRQHandler(void) +{ + INT_IRQHandler(PM4, 15); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t id) +{ + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + core_util_critical_section_enter(); + // Get GPIO port and pin num + obj->port = (PortName)PIN_PORT(pin); + obj->pin_num = PIN_POS(pin); + // Set pin level as LOW + gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0); + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + // Get GPIO irq source + obj->irq_src = (CG_INTSrc)obj->irq_id; + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + // Save irq id + channel_ids[obj->irq_src] = id; + // Initialize interrupt event as both edges detection + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + core_util_critical_section_exit(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_ids[obj->irq_src] = 0; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + // Disable GPIO interrupt on obj + gpio_irq_disable(obj); + + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else { + error("Not supported event\n"); + } + } + + CurrentState = obj->event; + if (obj->event != CG_INT_ACTIVE_STATE_INVALID) { + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0); + } else { + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1); + } + + // Clear interrupt request + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} + +static void INT_IRQHandler(PinName pin, uint32_t index) +{ + PortName port; + uint8_t pin_num; + + gpio_pinstate_t data = GPIO_PIN_RESET; + pin_num = PIN_POS(pin); + port = (PortName)PIN_PORT(pin); + + // Clear interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE); + // Get pin value + gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data); + + switch (data) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_ids[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_ids[index], IRQ_RISE); + break; + default: + break; + } + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index)); + // Enable interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE); +} + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState) +{ + uint8_t *ptr; + if (((INTSource == CG_INT_SRC_1) || (INTSource == CG_INT_SRC_2) + || (INTSource == CG_INT_SRC_B) || (INTSource == CG_INT_SRC_E))) { + ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2)); + } else { + ptr = ((uint8_t *)(&(TSB_IA->IMC00)) + (INTSource * 2) + 1); + } + // Clear pending falling and rising edge bit + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + { + uint8_t regval = *ptr; + (void)regval; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_object.h new file mode 100644 index 0000000..b8217fe --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/gpio_object.h @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t pin_num; + uint32_t mask; + PinName pin; + PortName port; +} gpio_t; + +typedef enum { + CG_INT_SRC_0 = 0U, + CG_INT_SRC_1, + CG_INT_SRC_2, + CG_INT_SRC_3, + CG_INT_SRC_4, + CG_INT_SRC_5, + CG_INT_SRC_6, + CG_INT_SRC_7, + CG_INT_SRC_8, + CG_INT_SRC_9, + CG_INT_SRC_A, + CG_INT_SRC_B, + CG_INT_SRC_C, + CG_INT_SRC_D, + CG_INT_SRC_E, + CG_INT_SRC_F +} CG_INTSrc; + +typedef enum { + CG_INT_ACTIVE_STATE_L = 0x00U, + CG_INT_ACTIVE_STATE_H = 0x02U, + CG_INT_ACTIVE_STATE_FALLING = 0x04U, + CG_INT_ACTIVE_STATE_RISING = 0x06U, + CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, + CG_INT_ACTIVE_STATE_INVALID = 0x0AU +} CG_INTActiveState; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName)NC); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/i2c_api.c new file mode 100644 index 0000000..a46dd38 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/i2c_api.c @@ -0,0 +1,300 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "i2c_api.h" + +#if DEVICE_I2C + +#include +#include +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "txz_i2c_api.h" + +#define MAX_I2C_FREQ 1000000 +#define I2C_TRANSFER_STATE_IDLE (0x0U) + +#if DEVICE_I2C_ASYNCH +#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c)) +#else +#define I2C_S(obj) (struct i2c_s *) (obj) +#endif + +static const PinMap PinMap_I2C_SDA[] = { + {PF2, I2C_0, PIN_DATA(7, 2)}, + {PV5, I2C_1, PIN_DATA(6, 2)}, + {PJ6, I2C_2, PIN_DATA(7, 2)}, + {PJ3, I2C_3, PIN_DATA(7, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PF3, I2C_0, PIN_DATA(7, 2)}, + {PV4, I2C_1, PIN_DATA(6, 2)}, + {PJ7, I2C_2, PIN_DATA(7, 2)}, + {PJ2, I2C_3, PIN_DATA(7, 2)}, + {NC, NC, 0} +}; + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + struct i2c_s *obj_s = I2C_S(obj); + MBED_ASSERT(obj_s != NULL); + + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + + MBED_ASSERT((int)i2c_name != NC); + obj_s->index = i2c_name; + obj_s->is_master = 1; + + switch (i2c_name) { + case I2C_0: + TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; // Enable clock for I2C_1 + TSB_CG_FSYSMENB_IPMENB07 = TXZ_ENABLE; // Enable clock for GPIO F + obj_s->my_i2c.i2c.p_instance = TSB_I2C1; + obj_s->irqn = INTI2C1NST_IRQn; + break; + case I2C_1: + TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; // Enable clock for I2C_2 + TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE; // Enable clock for GPIO V + obj_s->my_i2c.i2c.p_instance = TSB_I2C2; + obj_s->irqn = INTI2C1NST_IRQn; + break; + case I2C_2: + TSB_CG_FSYSMENB_IPMENB00 = TXZ_ENABLE; // Enable clock for I2C_3 + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J + obj_s->my_i2c.i2c.p_instance = TSB_I2C3; + obj_s->irqn = INTI2C3NST_IRQn; + break; + case I2C_3: + TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; // Enable clock for I2C_4 + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; // Enable clock for GPIO J + obj_s->my_i2c.i2c.p_instance = TSB_I2C4; + obj_s->irqn = INTI2C4NST_IRQn; + break; + default: + error("I2C is not available"); + break; + } + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + i2c_reset(obj); + i2c_frequency(obj, 100000); + I2C_init(&obj_s->my_i2c.i2c); +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + struct i2c_s *obj_s = I2C_S(obj); + + if (hz > MAX_I2C_FREQ) { + error("Failed : Max I2C frequency is 1000000"); + } + + i2c_frequency_t(&obj_s->my_i2c, hz); + + if (obj_s->is_master) { + I2C_init(&obj_s->my_i2c.i2c); + } else { + I2C_slave_init(&obj_s->my_i2c.i2c); + } +} + +int i2c_start(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_start_t(&obj_s->my_i2c); + + return TXZ_SUCCESS; +} + +int i2c_stop(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_stop_t(&obj_s->my_i2c); + + return TXZ_SUCCESS; +} + +void i2c_reset(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + // Software reset + i2c_reset_t(&obj_s->my_i2c); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_read_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_write_t(&obj_s->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t data = 0; + struct i2c_s *obj_s = I2C_S(obj); + + data = i2c_byte_read_t(&obj_s->my_i2c, last); + + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result = 0; + struct i2c_s *obj_s = I2C_S(obj); + + result = i2c_byte_write_t(&obj_s->my_i2c, data); + + return result; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + struct i2c_s *obj_s = I2C_S(obj); + + obj_s->is_master = 0; + i2c_slave_mode_t(&obj_s->my_i2c, enable_slave); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_slave_address_t(&obj_s->my_i2c, address); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = 0; + struct i2c_s *obj_s = I2C_S(obj); + + result = i2c_slave_receive_t(&obj_s->my_i2c); + + return result; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_slave_read_t(&obj_s->my_i2c, (uint8_t *)data, length); + + return count; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + struct i2c_s *obj_s = I2C_S(obj); + + count = i2c_slave_write_t(&obj_s->my_i2c, (uint8_t *)data, length); + + return count; +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if DEVICE_I2C_ASYNCH + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, + uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct i2c_s *obj_s = I2C_S(obj); + + obj_s->event_mask = event; + //Set irqn table for future use + set_i2c(obj_s->index, &obj_s->my_i2c.info.irqn); + NVIC_SetVector(obj_s->irqn, handler); + i2c_transfer_asynch_t(&obj_s->my_i2c, (uint8_t *)tx, tx_length, (uint8_t *)rx, rx_length, address, stop); +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + uint32_t event = 0; + + event = i2c_irq_handler_asynch_t(&obj_s->my_i2c); + + return (event & obj_s->event_mask); +} + +uint8_t i2c_active(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + uint8_t ret = (obj_s->my_i2c.info.asynch.state != I2C_TRANSFER_STATE_IDLE); + + return ret; +} + +void i2c_abort_asynch(i2c_t *obj) +{ + struct i2c_s *obj_s = I2C_S(obj); + + i2c_abort_asynch_t(&obj_s->my_i2c); +} + +#endif // #if DEVICE_I2C_ASYNCH + +#endif // #if DEVICE_I2C diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/objects.h new file mode 100644 index 0000000..31cf5b7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/objects.h @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "PortNames.h" +#include "PeripheralNames.h" +#include "gpio_object.h" +#include "txz_uart.h" +#include "txz_fuart.h" +#include "txz_tspi.h" +#include "txz_t32a.h" +#include "txz_cg.h" +#include "txz_driver_def.h" +#include "txz_adc.h" +#include "txz_i2c_api.h" +#include "txz_i2c.h" +#include "txz_fuart_include.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + uint32_t mask; + PortName port; +}; + +struct dac_s { + DACName dac; + TSB_DA_TypeDef *DACx; +}; + +typedef struct { + uint32_t BaudRate; + uint32_t DataBits; + uint32_t StopBits; + uint32_t Parity; + uint32_t Mode; + uint32_t FlowCtrl; +} FUART_InitTypeDef; + +struct serial_s { + uint32_t index; + uint32_t mode; + uint8_t is_using_fuart; + TSB_UART_TypeDef *UARTx; + TSB_FURT_TypeDef *FUARTx; + uart_boudrate_t boud_obj; + fuart_boudrate_t boudrate; + FUART_InitTypeDef fuart_config; +}; + +struct pwmout_s { + uint32_t divisor; + uint32_t type; + uint32_t trailing_timing; + uint32_t leading_timing; + float period; + t32a_t p_t32a; + PinName pin; +}; + +struct spi_s { + tspi_t p_obj; + SPIName module; + uint8_t bits; + PinName Slave_SCK; +#if DEVICE_SPI_ASYNCH + uint32_t irqn; + uint32_t event; + uint32_t max_size; + uint32_t state; +#endif +}; + +struct gpio_irq_s { + PortName port; + uint8_t pin_num; + uint32_t irq_id; + CG_INTSrc irq_src; + CG_INTActiveState event; +}; + +struct flash_s { + int flash_inited; +}; + +struct analogin_s { + adc_t p_adc; + PinName pin; + ADCName adc; + adc_channel_setting_t param; +}; + +struct i2c_s { + uint8_t is_master; + uint32_t index; + IRQn_Type irqn; + _i2c_t my_i2c; +#if DEVICE_I2C_ASYNCH + uint32_t event_mask; +#endif +}; + + +#include "gpio_object.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/pinmap.c new file mode 100644 index 0000000..962610d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/pinmap.c @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "txz_gpio.h" + +#define PIN_FUNC_MAX 8 + +extern _gpio_t gpio_port_add; + +void pin_function(PinName pin, int function) +{ + uint32_t port = 0; + uint8_t bit = 0; + uint8_t func = 0; + uint8_t dir = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Calculate pin function and pin direction + func = PIN_FUNC(function); + dir = PIN_DIR(function); + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Find function is in range or not + if (func <= PIN_FUNC_MAX) { + // Set pin function and direction if direction is in range + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT); + break; + default: + break; + } + } else { + // Do nothing + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + uint32_t port = 0; + uint8_t bit = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Check if function is in range + if (mode > OpenDrain) { + return; + } + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Set pin mode + switch (mode) { + case PullNone: + gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_RESET); + break; + case PullUp: + gpio_SetPullUp(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + case PullDown: + gpio_SetPullDown(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + case OpenDrain: + gpio_SetOpenDrain(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, GPIO_PIN_SET); + break; + default: + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/port_api.c new file mode 100644 index 0000000..5ceeabc --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/port_api.c @@ -0,0 +1,144 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "txz_gpio.h" +#include "pinmap.h" + +#define PORT_PIN_NUM (8) +#define ALT_FUNC_GPIO (0) + +extern _gpio_t gpio_port_add; +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num); + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName)((port << 3) | pin_n); + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortY); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + + // Enable the clock for particular port + _gpio_init(&gpio_port_add, obj->port); + + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + for (i = 0; i < PORT_PIN_NUM; i++) { + // Set direction for masked pins + if (obj->mask & (1 << i)) { + gpio_pin_dir(obj, dir, i); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + + // Write data to masked pins of the port + gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data); +} + +int port_read(port_t *obj) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortY); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data of masked pins + data = port_data & obj->mask; + + return data; +} + +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num) +{ + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT); + break; + default: + // error("Invalid direction\n"); + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/pwmout_api.c new file mode 100644 index 0000000..a1677ba --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/pwmout_api.c @@ -0,0 +1,241 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define GPIO_CLK_OFFSET 2 +// Because Timer operating frequency is 3.0 MhZ +#define CALCULATE_RGC1_VAL 2.95 + +static const PinMap PinMap_PWM[] = { + {PW1, PWM_0, PIN_DATA(7, 1)}, + {PW2, PWM_1, PIN_DATA(7, 1)}, + {PT3, PWM_2, PIN_DATA(3, 1)}, + {PD2, PWM_3, PIN_DATA(5, 1)}, + {PD4, PWM_4, PIN_DATA(5, 1)}, + {PE1, PWM_5, PIN_DATA(5, 1)}, + {PE6, PWM_6, PIN_DATA(5, 1)}, + {PL4, PWM_7, PIN_DATA(3, 1)}, + {PL6, PWM_8, PIN_DATA(3, 1)}, + {PC4, PWM_9, PIN_DATA(5, 1)}, + {PW6, PWM_10, PIN_DATA(7, 1)}, + {PU0, PWM_11, PIN_DATA(3, 1)}, + {PU6, PWM_12, PIN_DATA(3, 1)}, + {NC, NC, 0} +}; + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + // Determine the pwm channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + + // Assert input is valid + MBED_ASSERT(pwm != (PWMName)NC); + + switch (pwm) { + case PWM_0: + obj->p_t32a.p_instance = TSB_T32A0; + // Clock enable of T32A ch00 + TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE; + break; + case PWM_1: + obj->p_t32a.p_instance = TSB_T32A1; + // Clock enable of T32A ch01 + TSB_CG_FSYSMENA_IPMENA07 = TXZ_ENABLE; + break; + case PWM_2: + obj->p_t32a.p_instance = TSB_T32A3; + // Clock enable of T32A ch03 + TSB_CG_FSYSMENA_IPMENA09 = TXZ_ENABLE; + break; + case PWM_3: + obj->p_t32a.p_instance = TSB_T32A4; + // Clock enable of T32A ch04 + TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE; + break; + case PWM_4: + obj->p_t32a.p_instance = TSB_T32A5; + // Clock enable of T32A ch05 + TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE; + break; + case PWM_5: + obj->p_t32a.p_instance = TSB_T32A6; + // Clock enable of T32A ch06 + TSB_CG_FSYSMENA_IPMENA12 = TXZ_ENABLE; + break; + case PWM_6: + obj->p_t32a.p_instance = TSB_T32A7; + // Clock enable of T32A ch07 + TSB_CG_FSYSMENA_IPMENA13 = TXZ_ENABLE; + break; + case PWM_7: + obj->p_t32a.p_instance = TSB_T32A8; + // Clock enable of T32A ch08 + TSB_CG_FSYSMENA_IPMENA14 = TXZ_ENABLE; + break; + case PWM_8: + obj->p_t32a.p_instance = TSB_T32A9; + // Clock enable of T32A ch09 + TSB_CG_FSYSMENA_IPMENA15 = TXZ_ENABLE; + break; + case PWM_9: + obj->p_t32a.p_instance = TSB_T32A10; + // Clock enable of T32A ch10 + TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE; + break; + case PWM_10: + obj->p_t32a.p_instance = TSB_T32A11; + // Clock enable of T32A ch11 + TSB_CG_FSYSMENA_IPMENA17 = TXZ_ENABLE; + break; + case PWM_11: + obj->p_t32a.p_instance = TSB_T32A12; + // Clock enable of T32A ch12 + TSB_CG_FSYSMENA_IPMENA18 = TXZ_ENABLE; + break; + case PWM_12: + obj->p_t32a.p_instance = TSB_T32A13; + // Clock enable of T32A ch13 + TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE; + break; + default: + obj->p_t32a.p_instance = NULL; + break; + } + + if (obj->p_t32a.p_instance == NULL) { + return; + } + + // Enable clock for GPIO port. + TSB_CG->FSYSMENB |= (TXZ_ENABLE << ((PIN_PORT(pin)) + GPIO_CLK_OFFSET)); + + // Set pin function as PWM + pinmap_pinout(pin, PinMap_PWM); + + // Default to 20ms, 0% duty cycle + pwmout_period_ms(obj, 20); +} + +void pwmout_free(pwmout_t *obj) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + obj->trailing_timing = TXZ_DISABLE; + obj->leading_timing = TXZ_DISABLE; + obj->p_t32a.p_instance = NULL; +} + +void pwmout_write(pwmout_t *obj, float value) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + + if (value <= 0.0f) { + value = TXZ_DISABLE; + } else if (value >= 1.0f) { + value = TXZ_ENABLE; + } + + // Store the new leading_timing value + obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value); + + // Setting T32A_RGA0 register + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + + // Start PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +float pwmout_read(pwmout_t *obj) +{ + float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + return duty_cycle; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, (ms * 1000)); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t *obj, int us) +{ + uint32_t prscl = 0; + float duty_cycle = 0; + float seconds = (float)((us) / 1000000.0f); + + obj->period = seconds; + // Restore the duty-cycle + duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + prscl = T32A_PRSCLx_32; + + obj->trailing_timing = (us * CALCULATE_RGC1_VAL); + obj->leading_timing = ((obj->trailing_timing) - (obj->trailing_timing * duty_cycle)); + + obj->p_t32a.p_instance->MOD = T32A_MODE_32; + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx); + obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ | + T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ); + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + obj->p_t32a.p_instance->RGC1 = obj->trailing_timing; + obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE; + obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET); + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->trailing_timing; +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (seconds * 1000000.0f)); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, (ms * 1000)); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + float seconds = 0; + float value = 0; + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + pwmout_write(obj, value); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) +{ + return obj->trailing_timing - obj->leading_timing; +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/reset_reason_api.c new file mode 100644 index 0000000..8b30051 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/reset_reason_api.c @@ -0,0 +1,133 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "reset_reason_api.h" + +#ifdef DEVICE_RESET_REASON + +#include "TMPM4NR.h" +#include + +static uint8_t set_bit_count(uint32_t reg); + +typedef enum { + POWER_ON_BIT_POS = 1 << 0, + PIN_RESET_BIT_POS = 1 << 3, + LOW_POWER_BIT_POS = 1 << 4, + BROWN_OUT_BIT_POS = 1 << 5, +} reason_flag0; + +typedef enum { + SOFTWARE_BIT_POS = 1 << 0, + LOCK_BIT_POS = 1 << 1, + WATCHDOG_BIT_POS = 1 << 2, + PLATFORM_BIT_POS = 1 << 3, +} reason_flag1; + +void hal_reset_reason_clear(void) +{ + TSB_RLM->RSTFLG0 = 0; + TSB_RLM->RSTFLG1 = 0; +} + +uint32_t hal_reset_reason_get_raw(void) +{ + uint32_t ret = 0; + + ret = (((TSB_RLM->RSTFLG1 & 0xFF) << 8) | (TSB_RLM->RSTFLG0 & 0xFF)); + + return ret; +} + +reset_reason_t hal_reset_reason_get(void) +{ + reset_reason_t ret; + + uint8_t NoOfSetBitCountReg1 = set_bit_count(TSB_RLM->RSTFLG0); + uint8_t NoOfSetBitCountReg2 = set_bit_count(TSB_RLM->RSTFLG1); + + if (NoOfSetBitCountReg1 != 0x00) { + if (NoOfSetBitCountReg1 > 0x01) { + ret = RESET_REASON_MULTIPLE; + } else { + if (TSB_RLM->RSTFLG0 & POWER_ON_BIT_POS) { + ret = RESET_REASON_POWER_ON; + } else if (TSB_RLM->RSTFLG0 & PIN_RESET_BIT_POS) { + ret = RESET_REASON_PIN_RESET; + } else if (TSB_RLM->RSTFLG0 & LOW_POWER_BIT_POS) { + ret = RESET_REASON_WAKE_LOW_POWER; + } else if (TSB_RLM->RSTFLG0 & BROWN_OUT_BIT_POS) { + ret = RESET_REASON_BROWN_OUT; + } else { + ret = RESET_REASON_UNKNOWN; + } + } + } else if (NoOfSetBitCountReg2 != 0x00) { + if (NoOfSetBitCountReg2 > 0x01) { + ret = RESET_REASON_MULTIPLE; + } else { + if (TSB_RLM->RSTFLG1 & SOFTWARE_BIT_POS) { + ret = RESET_REASON_SOFTWARE; + } else if (TSB_RLM->RSTFLG1 & LOCK_BIT_POS) { + ret = RESET_REASON_LOCKUP; + } else if (TSB_RLM->RSTFLG1 & WATCHDOG_BIT_POS) { + ret = RESET_REASON_WATCHDOG; + } else if (TSB_RLM->RSTFLG1 & PLATFORM_BIT_POS) { + ret = RESET_REASON_PLATFORM; + } else { + ret = RESET_REASON_UNKNOWN; + } + } + } else { + ret = RESET_REASON_UNKNOWN; + } + + return ret; +} + +void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) +{ + cap->reasons = 1 << RESET_REASON_UNKNOWN; + cap->reasons |= 1 << RESET_REASON_POWER_ON; + cap->reasons |= 1 << RESET_REASON_PIN_RESET; + cap->reasons |= 1 << RESET_REASON_WAKE_LOW_POWER; + cap->reasons |= 1 << RESET_REASON_BROWN_OUT; + cap->reasons |= 1 << RESET_REASON_SOFTWARE; + cap->reasons |= 1 << RESET_REASON_LOCKUP; + cap->reasons |= 1 << RESET_REASON_WATCHDOG; + cap->reasons |= 1 << RESET_REASON_PLATFORM; + cap->reasons |= 1 << RESET_REASON_MULTIPLE; + +} + +static uint8_t set_bit_count(uint32_t reg) +{ + uint8_t count = 0; + uint8_t index = 0; + + for (index = 0; index < (sizeof(uint32_t) * 8); index++) { + if (reg & (1 << index)) { + count++; + if (count > 0x01) { + break; + } + } + } + + return count; +} + +#endif // DEVICE_RESET_REASON diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/rtc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/rtc_api.c new file mode 100644 index 0000000..bf57a9f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/rtc_api.c @@ -0,0 +1,241 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "rtc_api.h" +#include "mbed_mktime.h" + +#define RTC_24_HOUR_MODE ((uint8_t)0x01) +#define PAGER_PAGE_ONE ((uint8_t)0x01) +#define PAGER_PAGE_ZERO ((uint8_t)0xEE) +#define RTC_CLK_ENABLE ((uint8_t)0x08) +#define RTC_CLK_DISABLE ((uint8_t)0xE7) +#define RTCRESTR_RSTTMR_MASK ((uint8_t)0x20) +#define RTCRESTR_RSTTMR_R_RUN ((uint8_t)0x20) +#define CGWUPLCR_WUPTL_HIGH_MASK ((uint32_t)0x07FFF000) +#define CGWUPLCR_WULEF_MASK ((uint32_t)0x00000002) +#define CGWUPLCR_WULEF_R_DONE ((uint32_t)0x00000000) +#define CGWUPLCR_WULON_W_ENABLE ((uint32_t)0x00000001) +#define RLMLOSCCR_XTEN_RW_ENABLE ((uint32_t)0x00000001) +#define RLMLOSCCR_DRCOSCL_RW_ENABLE ((uint32_t)0x00000004) +#define ELOSC_CFG_WARM_UP_TIME ((uint64_t)(5000)) +#define ELOSC_CFG_CLOCK ((uint64_t)(32768)) +#define HEX2DEC(val) ((val >> 4U) * 10U + val % 16U) // Hex to Dec conversion macro +#define DEC2HEX(val) ((val / 10U) * 16U + val % 10U) // Dec to Hex conversion macro + +static int rtc_inited = 0; +static int diff_year = 100; //our RTC register only support 2000~2099 +static void external_losc_enable(void); + +void rtc_init(void) +{ + if (!rtc_inited) { + external_losc_enable(); // Enable low-speed oscillator + TSB_RTC->PAGER = 0x00; // Disable clock and alarm + while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { + // Reset RTC sec counter + } + + TSB_RTC->RESTR = 0xE7; + while ((TSB_RTC->RESTR & RTCRESTR_RSTTMR_MASK) == RTCRESTR_RSTTMR_R_RUN) { + // Reset RTC sec counter + } + + TSB_RTC->PAGER |= PAGER_PAGE_ONE; + TSB_RTC->YEARR = 0x03; // Set leap year state + TSB_RTC->MONTHR = RTC_24_HOUR_MODE; // Set hour mode + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Set hour mode + TSB_RTC->YEARR = 0x01; // Set year value + TSB_RTC->MONTHR = (uint8_t)0x01; // Set month value + TSB_RTC->DATER = (uint8_t)0x01; // Set date value + TSB_RTC->DAYR = (uint8_t)0x0; // Set day value + TSB_RTC->HOURR = (uint8_t)0x01; // Set hour value + TSB_RTC->MINR = (uint8_t)0x02; // Set minute value + TSB_RTC->SECR = (uint8_t)0x22; // Set second value + TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock + rtc_inited = 1; // Enable RTC initialzed status + } +} + +void rtc_free(void) +{ + rtc_inited = 0; // Set status of RTC peripheral driver as DISABLE +} + +int rtc_isenabled(void) +{ + return rtc_inited; // Return status of RTC peripheral driver +} + +time_t rtc_read(void) +{ + if (!rtc_inited) { + // Return invalid time for now! + return 0; + } + + struct tm timeinfo; + uint8_t read_1 = 0U; + uint8_t read_2 = 0U; + + timeinfo.tm_isdst = 0; //no summer time + + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; + + read_1 = TSB_RTC->SECR; // Get sec value + timeinfo.tm_sec = HEX2DEC(read_1); + + // Get minute value + do { + read_1 = TSB_RTC->MINR; + read_2 = TSB_RTC->MINR; + } while (read_1 != read_2); + timeinfo.tm_min = HEX2DEC(read_1); + + // Get hour value + do { + read_1 = TSB_RTC->HOURR; + read_2 = TSB_RTC->HOURR; + } while (read_1 != read_2); + timeinfo.tm_hour = HEX2DEC(read_1); + + // Get Month date value + do { + read_1 = TSB_RTC->DATER; + read_2 = TSB_RTC->DATER; + } while (read_1 != read_2); + timeinfo.tm_mday = HEX2DEC(read_1); + + // Get Month value + do { + read_1 = TSB_RTC->MONTHR; + read_2 = TSB_RTC->MONTHR; + } while (read_1 != read_2); + timeinfo.tm_mon = HEX2DEC(read_1) - 1; + + // Get weekday value + do { + read_1 = TSB_RTC->DAYR; + read_2 = TSB_RTC->DAYR; + } while (read_1 != read_2); + timeinfo.tm_wday = HEX2DEC(read_1); + + // Get year value + do { + read_1 = TSB_RTC->YEARR; + read_2 = TSB_RTC->YEARR; + } while (read_1 != read_2); + timeinfo.tm_year = (HEX2DEC(read_1) + diff_year); + + time_t t; + if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return 0; + } + return t; +} + +void rtc_write(time_t t) +{ + if (!rtc_inited) { + // Initialize the RTC as not yet initialized + rtc_init(); + } + + struct tm timeinfo; + if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) { + return; + } + + diff_year = timeinfo.tm_year - (timeinfo.tm_year % 100); + TSB_RTC->PAGER &= RTC_CLK_DISABLE; // Disable clock + + // Check current year is leap year or not + if (((timeinfo.tm_year % 4) == 0 && (timeinfo.tm_year % 100) != 0) || + (timeinfo.tm_year % 400) == 0) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is a leap year + TSB_RTC->YEARR = 0x00; + } else if ((timeinfo.tm_year % 4) == 1) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is the year following a leap year + TSB_RTC->YEARR = 0x01; + } else if ((timeinfo.tm_year % 4) == 2) { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is two years after a leap year + TSB_RTC->YEARR = 0x02; + } else { + TSB_RTC->PAGER |= PAGER_PAGE_ONE; // Current year is three years after a leap year + TSB_RTC->YEARR = 0x03; + } + + TSB_RTC->PAGER &= PAGER_PAGE_ZERO; // Select PAGE 0 + + TSB_RTC->YEARR = (uint8_t)DEC2HEX((timeinfo.tm_year - diff_year)); // Set year value + + // Set month value, tm_mon=0 means Jan while 1 is Jan + TSB_RTC->MONTHR = (uint8_t)DEC2HEX((timeinfo.tm_mon + 1)); + TSB_RTC->DATER = (uint8_t)DEC2HEX(timeinfo.tm_mday); // Set date value + TSB_RTC->DAYR = (uint8_t)(timeinfo.tm_wday); // Set week day value + TSB_RTC->HOURR = (uint8_t)DEC2HEX(timeinfo.tm_hour); // Set hour value + TSB_RTC->MINR = (uint8_t)DEC2HEX(timeinfo.tm_min); // Set minute value + TSB_RTC->SECR = (uint8_t)DEC2HEX(timeinfo.tm_sec); // Set second value + + // Setting Wait + // When stop mode is selected, CaseA or CaseB is need. + // CaseA: Wait for RTC 1Hz interrupt. + // CaseB: Check the clock register setting. + { + uint8_t flag = 1; + time_t time_read = {0}; + while (flag) { + time_read = rtc_read(); + if (time_read == t) { // Wait for setting successfully + flag = 0; + } + } + } + TSB_RTC->PAGER |= RTC_CLK_ENABLE; // Enable Clock +} + +static void external_losc_enable(void) +{ + uint32_t work; + + // [CGWUPLCR] :Warm up time + //-------------------------------------- + // "1"counter (s) = 1 / ELOSC + // "1"counter (us) = (10^6) / ELOSC + // "x"counter (us) = time + //-------------------------------------- + // x : time = 1 : (10^6) / ELOSC + //-------------------------------------- + { + uint64_t x = (uint64_t)((uint64_t)(ELOSC_CFG_WARM_UP_TIME) * (uint64_t)(ELOSC_CFG_CLOCK)); + x = (uint64_t)(x / (uint64_t)(1000000)); + if (x > (uint64_t)(0x7FFFF)) { + /* invalid value */ + } + work = (uint32_t)x; + } + work &= (uint32_t)(0xFFFFFFF0); + work <<= 8; + TSB_CG->WUPLCR = work; + // [RLMLOSCCR] :LOSC Enable + TSB_RLM->LOSCCR = RLMLOSCCR_DRCOSCL_RW_ENABLE | RLMLOSCCR_XTEN_RW_ENABLE; + // [CGWUPLCR] :Enable + work = (uint32_t)(TSB_CG->WUPLCR & CGWUPLCR_WUPTL_HIGH_MASK); + TSB_CG->WUPLCR = (uint32_t)(work | CGWUPLCR_WULON_W_ENABLE); + // [CGWUPLCR] :Read(wait for warm-up) + while ((TSB_CG->WUPLCR & CGWUPLCR_WULEF_MASK) != CGWUPLCR_WULEF_R_DONE) { + // no processing + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/serial_api.c new file mode 100644 index 0000000..75b29c7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/serial_api.c @@ -0,0 +1,668 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_error.h" +#include "serial_api.h" +#include "pinmap.h" + +#define UART_NUM 8 +#define UART_ENABLE_RX ((uint32_t)0x00000001) +#define UART_ENABLE_TX ((uint32_t)0x00000002) +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) +#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) +#define LCR_H_WLEN_MASK ((uint32_t)0xFFFFFF9F) +#define LCR_H_STP2_MASK ((uint32_t)0xFFFFFFF7) +#define LCR_H_PARITY_MASK ((uint32_t)0xFFFFFF79) +#define CR_FLOW_CTRL_MASK ((uint32_t)0x00000F07) +#define CR_MODE_MASK ((uint32_t)0x0000CC07) +#define FUARTxCR_UARTEN_ENABLE_CLEAR ((uint32_t)0xFFFFFF7E) +#define FUART_CTS_RTS_DISABLE_MASK ((uint32_t)0XFFFF3FFF) +#define BAUDRATE_DEFAULT (9600) +#define CLR_REGISTER (0x00) +#define IMSC_TXIM_RXIM_MASK ((uint32_t)0X000007C0) +#define IMSC_RXIM_CLEAR ((uint32_t)0X000007E0) +#define IMSC_TXIM_CLEAR ((uint32_t)0X000007D0) + +static const PinMap PinMap_UART_TX[] = { + {PE3, SERIAL_0, PIN_DATA(7, 1)}, + {PV5, SERIAL_1, PIN_DATA(7, 1)}, + {PV1, SERIAL_2, PIN_DATA(6, 1)}, + {PJ1, SERIAL_3, PIN_DATA(3, 1)}, + {PJ4, SERIAL_4, PIN_DATA(5, 1)}, + {PJ6, SERIAL_5, PIN_DATA(5, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PE2, SERIAL_0, PIN_DATA(7, 0)}, + {PV4, SERIAL_1, PIN_DATA(7, 0)}, + {PV0, SERIAL_2, PIN_DATA(6, 0)}, + {PJ0, SERIAL_3, PIN_DATA(3, 0)}, + {PJ5, SERIAL_4, PIN_DATA(5, 0)}, + {PJ7, SERIAL_5, PIN_DATA(5, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RTS[] = { + {PE0, SERIAL_0, PIN_DATA(7, 1)}, + {PV7, SERIAL_1, PIN_DATA(7, 1)}, + {PV2, SERIAL_2, PIN_DATA(7, 1)}, + {PJ2, SERIAL_3, PIN_DATA(3, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_CTS[] = { + {PE1, SERIAL_0, PIN_DATA(7, 0)}, + {PV6, SERIAL_1, PIN_DATA(7, 0)}, + {PV3, SERIAL_2, PIN_DATA(7, 0)}, + {PJ3, SERIAL_3, PIN_DATA(3, 0)}, + {NC, NC, 0} +}; + +static int serial_irq_ids[UART_NUM] = {0}; +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +static void uart_swreset(TSB_UART_TypeDef *UARTx); +static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + obj->mode = 0; + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal = {0}; + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT((int)uart_name != NC); + + obj->is_using_fuart = 0; + obj->index = uart_name; + // Initialize UART instance + switch (uart_name) { + case SERIAL_0: + obj->UARTx = TSB_UART0; + // Enable clock for UART0 and Port E + TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB06 = TXZ_ENABLE; + break; + case SERIAL_1: + obj->UARTx = TSB_UART1; + // Enable clock for UART1 and Port V + TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE; + break; + case SERIAL_2: + obj->UARTx = TSB_UART3; + // Enable clock for UART3 and Port V + TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB19 = TXZ_ENABLE; + break; + case SERIAL_3: + obj->UARTx = TSB_UART5; + // Enable clock for UART5 and Port J + TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; + break; + case SERIAL_4: + obj->FUARTx = TSB_FURT0; + //Enable clock for UART6 and Port J + TSB_CG_FSYSMENA_IPMENA01 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; + obj->is_using_fuart = 1; + break; + case SERIAL_5: + obj->FUARTx = TSB_FURT1; + //Enable clock for UART7 and Port J + TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB10 = TXZ_ENABLE; + obj->is_using_fuart = 1; + break; + default: + break; + } + + // Set alternate function + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (!(obj->is_using_fuart)) { + if (tx != NC && rx != NC) { + obj->mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->mode = UART_ENABLE_RX; + } + } + } + //software reset + uart_swreset(obj->UARTx); + //mbed default configurations + obj->UARTx->CR0 |= (1U); // data lengh 8 bit No parity one stop bit + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj); + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); + obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO + obj->UARTx->TRANS |= obj->mode; // Enable TX RX block. + obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE); + } else { + if (tx != NC && rx != NC) { + obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE | FUARTxCR_RXE_ENABLE; + } else if (tx != NC) { + obj->fuart_config.Mode = FUARTxCR_TXE_ENABLE; + } else if (rx != NC) { + obj->fuart_config.Mode = FUARTxCR_RXE_ENABLE; + } + + obj->fuart_config.BaudRate = BAUDRATE_DEFAULT; + obj->fuart_config.DataBits = FUART_DATA_LENGTH_8; + obj->fuart_config.StopBits = FUART_STOP_BIT_1; + obj->fuart_config.Parity = FUART_PARITY_DISABLE; + obj->fuart_config.FlowCtrl = FUART_CTS_DISABLE | FUART_RTS_DISABLE; + + fuart_get_boudrate_setting(cg_get_mphyt0(¶mCG), obj->fuart_config.BaudRate, &obj->boudrate); + + fuart_init_config(obj, &obj->fuart_config); + //Enable FUART + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } + + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS = CLR_REGISTER; + obj->UARTx->CR0 = CLR_REGISTER; + obj->UARTx->CR1 = CLR_REGISTER; + obj->UARTx = CLR_REGISTER; + uart_swreset(obj->UARTx); + } else { + obj->FUARTx->CR = CLR_REGISTER; + obj->FUARTx->IMSC = CLR_REGISTER; + obj->FUARTx->ICR = CLR_REGISTER; + obj->FUARTx->LCR_H = CLR_REGISTER; + obj->FUARTx = CLR_REGISTER; + } + obj->index = (uint32_t)NC; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal; + if (!(obj->is_using_fuart)) { + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj); + obj->UARTx->BRD = CLR_REGISTER; //clear BRD register + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); + } else { + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; + obj->fuart_config.BaudRate = baudrate; + fuart_get_boudrate_setting(cg_get_mphyt0(¶mCG), obj->fuart_config.BaudRate, &obj->boudrate); + fuart_init_config(obj, &obj->fuart_config); + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + + } +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint32_t parity_check = 0; + uint32_t data_length = 0; + uint32_t tmp = 0; + uint32_t sblen = 0; + + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + + if (!(obj->is_using_fuart)) { + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits + parity_check = ((parity == ParityOdd) ? 1 : ((parity == ParityEven) ? 3 : 0)); + data_length = (data_bits == 8 ? 1 : ((data_bits == 7) ? 0 : 2)); + sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits + tmp = ((sblen << 4) | (parity_check << 2) | data_length); + obj->UARTx->CR0 = tmp; + } else { + MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; + // Parity bit update + if (parity == ParityOdd) { + obj->fuart_config.Parity = FUART_PARITY_BIT_ODD | FUART_PARITY_ENABLE; + } else if (parity == ParityEven) { + obj->fuart_config.Parity = FUART_PARITY_BIT_EVEN | FUART_PARITY_ENABLE; + } else { + obj->fuart_config.Parity = FUART_PARITY_DISABLE; + } + // Stop bit update + obj->fuart_config.StopBits = (stop_bits == 1) ? FUART_STOP_BIT_1 : FUART_STOP_BIT_2; + // Data length update + obj->fuart_config.DataBits = (data_bits == 7) ? FUART_DATA_LENGTH_7 : FUART_DATA_LENGTH_8; + + fuart_init_config(obj, &obj->fuart_config); + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } +} + +// INTERRUPT HANDLING +void INTUART0RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], RxIrq); +} + +void INTUART0TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_0], TxIrq); +} + +void INTUART1RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], RxIrq); +} + +void INTUART1TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_1], TxIrq); +} + +void INTUART3RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], RxIrq); +} + +void INTUART3TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_2], TxIrq); +} + + +void INTUART5RX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], RxIrq); +} + +void INTUART5TX_IRQHandler(void) +{ + irq_handler(serial_irq_ids[SERIAL_3], TxIrq); +} + +void INTFUART0_IRQHandler(void) +{ + uint32_t int_status; + + int_status = TSB_FURT0->MIS; + if (int_status & (1 << 4U)) { + TSB_FURT0->ICR = int_status & FUARTxMIS_RXMIS_MASK; + irq_handler(serial_irq_ids[SERIAL_4], RxIrq); + } else if (int_status & (1 << 5U)) { + TSB_FURT0->ICR = int_status & FUARTxMIS_TXMIS_MASK; + irq_handler(serial_irq_ids[SERIAL_4], TxIrq); + } else { + return; + } +} + +void INTFUART1_IRQHandler(void) +{ + uint32_t int_status; + + int_status = TSB_FURT1->MIS; + if (int_status & (1 << 4U)) { + irq_handler(serial_irq_ids[SERIAL_5], RxIrq); + } else if (int_status & (1 << 5U)) { + irq_handler(serial_irq_ids[SERIAL_5], TxIrq); + } else { + return; + } +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + uint32_t tmp = 0U; + IRQn_Type irq_n = (IRQn_Type)0; + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTUART0RX_IRQn; + } else { + irq_n = INTUART0TX_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTUART1RX_IRQn; + } else { + irq_n = INTUART1TX_IRQn; + } + break; + case SERIAL_2: + if (irq == RxIrq) { + irq_n = INTUART3RX_IRQn; + } else { + irq_n = INTUART3TX_IRQn; + } + break; + case SERIAL_3: + if (irq == RxIrq) { + irq_n = INTUART5RX_IRQn; + } else { + irq_n = INTUART5TX_IRQn; + } + break; + case SERIAL_4: + irq_n = INTFUART0_IRQn; + break; + case SERIAL_5: + irq_n = INTFUART1_IRQn; + break; + default: + break; + } + + if (obj->is_using_fuart) { + // Set interrupt mask + if (enable) { + if (irq == RxIrq) { + obj->FUARTx->IMSC |= (1 << 4U); + } else { + obj->FUARTx->IMSC |= (1 << 5U); + } + } else { + if (irq == RxIrq) { + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_RXIM_CLEAR; /* Disable Receive interrupt */ + obj->FUARTx->IMSC = tmp; + } else { + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_TXIM_CLEAR; /* Disable Transmit interrupt */ + obj->FUARTx->IMSC = tmp; + } + } + } + NVIC_ClearPendingIRQ(irq_n); + + if (enable) { + NVIC_EnableIRQ(irq_n); + } else { + if (!obj->is_using_fuart) { + NVIC_DisableIRQ(irq_n); + } + } +} + +int serial_getc(serial_t *obj) +{ + int data = 0; + + while (!serial_readable(obj)) { // Wait until Rx buffer is full + // Do nothing + } + + if (!(obj->is_using_fuart)) { + //Read Data Register + data = (obj->UARTx->DR & 0xFFU); + obj->UARTx->SR |= (1U << 6); // clear RXEND flag + } else { + data = (obj->FUARTx->DR & 0xFFU); + } + + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)) { + // Do nothing + } + + // Write Data Register + if (!(obj->is_using_fuart)) { + obj->UARTx->DR = (c & 0xFF); + + while ((obj->UARTx->SR & (1U << 14)) == 0) { + } + + obj->UARTx->SR |= (1U << 14); // clear TXEND flag + } else { + obj->FUARTx->DR = (c & 0xFF); + } +} + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if (!(obj->is_using_fuart)) { + if ((obj->UARTx->SR & 0x000F) != 0) { + ret = 1; + } + } else { + if (obj->FUARTx->FR & (1 << 6U)) { + ret = 1; + } + } + + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if (!(obj->is_using_fuart)) { + if ((obj->UARTx->SR & 0x8000) == 0) { + ret = 1; + } + } else { + if (obj->FUARTx->FR & (1 << 7U)) { + ret = 1; + } + } + + return ret; +} + +void serial_clear(serial_t *obj) +{ + uint32_t dummy; + if (!(obj->is_using_fuart)) { + obj->UARTx->FIFOCLR = 0x03; + } else { + { + dummy = obj->FUARTx->DR; //dummy read + (void)dummy; + } + } +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +// Set flow control +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts); + + if (!(obj->is_using_fuart)) { + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName) NC); + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pin_mode(txflow, PullUp); // initial state of CTS preferably high + obj->UARTx->CR0 |= (1 << 10); // Enable CTS hardware control + + } else if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName) NC); + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + obj->UARTx->CR0 |= (1 << 9); // Enable RTS hardware control + + } else if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_name != (UARTName) NC); + obj->UARTx->CR0 |= (3 << 9); // Enable CTS and RTS hardware flow control + + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + pin_mode(txflow, PullUp); + } else { + obj->UARTx->CR0 &= (~(3 << 9)); // Disable CTS and RTS hardware flow control + } + } else { + obj->FUARTx->CR &= FUARTxCR_UARTEN_ENABLE_CLEAR; // Disable FUART + if (type == FlowControlCTS) { + MBED_ASSERT(uart_cts != (UARTName) NC); + obj->FUARTx->CR |= FUART_CTS_ENABLE; // Enable CTS hardware flow control + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS and RTS function + pin_mode(txflow, PullUp); + + } else if (type == FlowControlRTS) { + MBED_ASSERT(uart_rts != (UARTName) NC); + obj->FUARTx->CR |= FUART_RTS_ENABLE; // Enable RTS hardware flow control + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + + } else if (type == FlowControlRTSCTS) { + MBED_ASSERT(uart_name != (UARTName) NC); + obj->FUARTx->CR |= (FUART_CTS_ENABLE | FUART_RTS_ENABLE); // Enable CTS and RTS hardware flow control + pinmap_pinout(txflow, PinMap_UART_CTS); // Enable the pin for CTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); // Enable the pin for RTS function + pin_mode(txflow, PullUp); + + } else { + obj->FUARTx->CR &= FUART_CTS_RTS_DISABLE_MASK; // Disable CTS and RTS hardware flow control + } + obj->FUARTx->CR |= FUARTxCR_UARTEN_ENABLE; + } +} + +// Pause transmission +void serial_break_set(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS |= 0x08; + } else { + obj->FUARTx->LCR_H |= FUARTxLCR_H_BRK_SEND; + } +} + +// Switch to normal transmission +void serial_break_clear(serial_t *obj) +{ + if (!(obj->is_using_fuart)) { + obj->UARTx->TRANS &= ~(0x08); + } else { + obj->FUARTx->LCR_H &= ~(FUARTxLCR_H_BRK_SEND); + } +} + +static void uart_swreset(TSB_UART_TypeDef *UARTx) +{ + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + + UARTx->SWRST = UARTxSWRST_SWRST_10; + UARTx->SWRST = UARTxSWRST_SWRST_01; + + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } +} + +static void fuart_init_config(serial_t *obj, FUART_InitTypeDef *InitStruct) +{ + uint32_t tmp = 0U; + + + obj->FUARTx->BRD = obj->boudrate.brn; + obj->FUARTx->FBRD = obj->boudrate.brk; + + tmp = obj->FUARTx->LCR_H; + + tmp &= LCR_H_WLEN_MASK; + tmp |= InitStruct->DataBits; + + tmp &= LCR_H_STP2_MASK; + tmp |= InitStruct->StopBits; + + tmp &= LCR_H_PARITY_MASK; + tmp |= InitStruct->Parity; + + obj->FUARTx->LCR_H = tmp; //Set DataBits, StopBits, Parity + + tmp = obj->FUARTx->IMSC; + tmp &= IMSC_TXIM_RXIM_MASK; + tmp |= (FUART_TX_INT_ENABLE | FUART_RX_INT_ENABLE); + obj->FUARTx->IMSC = tmp; + + tmp = obj->FUARTx->CR; + tmp &= CR_FLOW_CTRL_MASK; + tmp |= InitStruct->FlowCtrl; + + tmp &= CR_MODE_MASK; + tmp |= InitStruct->Mode; + + obj->FUARTx->CR = tmp; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/sleep.c new file mode 100644 index 0000000..54860e6 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/sleep.c @@ -0,0 +1,126 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" + +// Number of warm-up cycle = (warming up time (s) / clock period (s)) - 16 +#define CG_WUODR_INT_5MS ((uint16_t)0x0C34) +#define CG_STBY_MODE_IDLE 0x0 +#define CG_STBY_MODE_STOP1 0x1 +#define EXTERNEL_OSC_MASK 0xFFFFFFF1 +#define SIWDT_DISABLE 0xB1 +#define WUPT_LOWER_MASK 0x000F +#define WUPT_UPPER_MASK 0xFFF0 + +static void external_losc_enable(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + TSB_CG->STBYCR = CG_STBY_MODE_IDLE; + + // Enter idle mode + __DSB(); + __WFI(); +} + +void hal_deepsleep(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + uint32_t tmp = 0; + + TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE; + + TSB_SIWD0->EN = TXZ_DISABLE; + TSB_SIWD0->CR = SIWDT_DISABLE; + + + while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) { + // Flash wait + } + + while (TSB_CG_WUPHCR_WUEF) { + // Wait for end of Warming-up for IHOSC1 + } + + TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE; + wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + TSB_CG->STBYCR = CG_STBY_MODE_STOP1; + TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE; + + + while (TSB_CG_PLL0SEL_PLL0ST) { + // Wait for PLL status of fsys until off state(fosc=0) + } + + // Stop PLL of fsys + TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE; + TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE; + TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE; + + while (TSB_CG_OSCCR_OSCF) { + // Wait for fosc status until IHOSC1 = 0 + } + + tmp = TSB_CG->OSCCR; + tmp &= EXTERNEL_OSC_MASK; + TSB_CG->OSCCR = tmp; + + + // Enter stop1 mode + __DSB(); + __WFI(); + + // Switch over from IHOSC to EHOSC + // After coming out off sleep mode, Restore the clock setting to EHOSC. + external_losc_enable(); +} + +static void external_losc_enable(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + + // Enable high-speed oscillator + TSB_CG->OSCCR |= (TXZ_ENABLE << 1); + + // Select internal(fIHOSC) as warm-up clock + wupt_lower = ((CG_WUODR_INT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + + // Start warm-up + TSB_CG->WUPHCR |= TXZ_ENABLE; + + // Wait until EHOSC become stable + while ((TSB_CG->WUPHCR & 0x0002)) { + // Do nothing + } + + // Set fosc source + TSB_CG->OSCCR |= (1 << 8); + + // Wait for to become "1" + while (!((TSB_CG->OSCCR & 0x200) >> 9)) { + // Do nothing + } + + // Stop IHOSC + TSB_CG->OSCCR &= ~TXZ_ENABLE; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/spi_api.c new file mode 100644 index 0000000..dc958ba --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/spi_api.c @@ -0,0 +1,559 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "spi_api.h" +#include "mbed_error.h" +#include "txz_tspi.h" +#include "pinmap.h" + +#define TIMEOUT 5000 +#define INITIAL_SPI_FREQ 1000000 + +#if DEVICE_SPI_ASYNCH +#define SPI_S(obj) (struct spi_s *) (&((obj)->spi)) +#else +#define SPI_S(obj) (struct spi_s *) (obj) +#endif + +#if DEVICE_SPI_ASYNCH +static void spi_irq_handler(spi_t *obj); +static void disable_irq(uint32_t irqn); +static void clear_irq(uint32_t irqn); +enum { + SPI_TRANSFER_STATE_IDLE = 0U, + SPI_TRANSFER_STATE_BUSY +} SPI_TransferState; +typedef struct { + IRQn_Type Tx; + IRQn_Type Rx; + IRQn_Type Error; +} spi_irq_t; +static const spi_irq_t SPI_CH0_IRQN_TBL[1] = { + { INTT0RX_IRQn, INTT0TX_IRQn, INTT0ERR_IRQn } +}; +static const spi_irq_t SPI_CH2_IRQN_TBL[1] = { + { INTT2RX_IRQn, INTT2TX_IRQn, INTT2ERR_IRQn } +}; +#endif + +static const PinMap PinMap_SPI_SCLK[] = { + {PA1, SPI_0, PIN_DATA(7, 1)}, + {PA6, SPI_1, PIN_DATA(7, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SLAVE_SCLK[] = { + {PA1, SPI_0, PIN_DATA(7, 0)}, + {PA6, SPI_1, PIN_DATA(7, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {PA3, SPI_0, PIN_DATA(7, 1)}, + {PA4, SPI_1, PIN_DATA(7, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PA2, SPI_0, PIN_DATA(7, 0)}, + {PA5, SPI_1, PIN_DATA(7, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PA0, SPI_0, PIN_DATA(7, 2)}, + {PA7, SPI_1, PIN_DATA(7, 2)}, + {NC, NC, 0} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + struct spi_s *obj_s = SPI_S(obj); + // Check pin parameters + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + + obj_s->module = (SPIName)pinmap_merge(spi_data, spi_sclk); + obj_s->module = (SPIName)pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj_s->module != NC); + + // Identify SPI module to use + switch ((int)obj_s->module) { + case SPI_0: + obj_s->p_obj.p_instance = TSB_TSPI0; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA04 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH0_IRQN_TBL; +#endif + break; + case SPI_1: + obj_s->p_obj.p_instance = TSB_TSPI2; + // Enable clock for particular Port and SPI + TSB_CG_FSYSENA_IPENA06 = TXZ_ENABLE; + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; +#if DEVICE_SPI_ASYNCH + obj_s->irqn = (uint32_t)&SPI_CH2_IRQN_TBL; +#endif + break; + default: + obj_s->p_obj.p_instance = NULL; + obj_s->module = (SPIName)NC; + error("Cannot found SPI module corresponding with input pins."); + break; + } + + // Pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + obj_s->Slave_SCK = sclk; + + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + // Default configurations 8 bit, 1Mhz frequency + // Control 1 configurations + obj_s->p_obj.init.id = (uint32_t)obj_s->module; + obj_s->p_obj.init.cnt1.inf = TSPI_INF_DISABLE; // Infinite Transfer Control disabled + obj_s->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled + obj_s->p_obj.init.cnt1.trxe = TSPI_TRXE_DISABLE; // Enable Communication + obj_s->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode + obj_s->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // master mode operation + obj_s->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) + obj_s->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid + obj_s->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_CONTINUE;// transfer single frame at a time continuously + + //Control 2 configurations + obj_s->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; + obj_s->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low + obj_s->p_obj.init.cnt2.rxdly = TSPI_RXDLY_8CLK; + obj_s->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level + obj_s->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level + obj_s->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; + obj_s->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; + obj_s->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; + obj_s->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; + obj_s->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; + obj_s->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; + obj_s->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; + + //Control 3 configurations + obj_s->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear + obj_s->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear + + //baudrate settings - 1Mhz default + spi_frequency(obj, (int)INITIAL_SPI_FREQ); + + //Format Control 0 settings + obj_s->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first + obj_s->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; + obj_s->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; + + //Special control on polarity of signal and generation timing + obj_s->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; + obj_s->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; + obj_s->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; + obj_s->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; + + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + obj_s->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; + obj_s->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; + obj_s->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; + + //Format Control 1 settings tspi_fmtr1_t + obj_s->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; + obj_s->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; + + obj_s->p_obj.init.scr0.sect = TSPI_SECT_MODE_FRAME; + + obj_s->bits = (uint8_t)TSPI_DATA_LENGTH_8; + + //initialize SPI + tspi_init(&obj_s->p_obj); +} + +void spi_free(spi_t *obj) +{ + struct spi_s *obj_s = SPI_S(obj); + + tspi_deinit(&obj_s->p_obj); + obj_s->module = (SPIName)NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + struct spi_s *obj_s = SPI_S(obj); + + MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode + MBED_ASSERT((bits >= 8) && (bits <= 32)); + + obj_s->bits = bits; + obj_s->p_obj.init.fmr0.fl = (bits << 24); + + + if ((mode >> 1) & 0x1) { + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; + } else { + obj_s->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + } + + if (mode & 0x1) { + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; + } else { + obj_s->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + } + + if (slave) { + pinmap_pinout(obj_s->Slave_SCK, PinMap_SPI_SLAVE_SCLK); + obj_s->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation + } + tspi_init(&obj_s->p_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + struct spi_s *obj_s = SPI_S(obj); + + + uint8_t brs = 0; + uint8_t brck = 0; + uint16_t prsck = 1; + uint64_t fscl = 0; + uint64_t tmp_fscl = 0; + uint64_t fx = 0; + uint64_t tmpvar = SystemCoreClock; + + SystemCoreClockUpdate(); + tmpvar = tmpvar / 2; + for (prsck = 1; prsck <= 512; prsck *= 2) { + fx = ((uint64_t)tmpvar / prsck); + for (brs = 1; brs <= 16; brs++) { + fscl = fx / brs; + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + obj_s->p_obj.init.brd.brck = (brck << 4); + if (brs == 16) { + obj_s->p_obj.init.brd.brs = 0; + } else { + obj_s->p_obj.init.brd.brs = brs; + } + } + } + brck ++; + } + + tspi_init(&obj_s->p_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + struct spi_s *obj_s = SPI_S(obj); + uint8_t ret_value = 0; + + tspi_transmit_t send_obj; + tspi_receive_t rec_obj; + + // Transmit data + send_obj.tx8.p_data = (uint8_t *)&value; + send_obj.tx8.num = 1; + tspi_master_write(&obj_s->p_obj, &send_obj, TIMEOUT); + + // Read received data + rec_obj.rx8.p_data = &ret_value; + rec_obj.rx8.num = 1; + tspi_master_read(&obj_s->p_obj, &rec_obj, TIMEOUT); + + return ret_value; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_busy(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + int ret = 1; + uint32_t status = 0; + tspi_get_status(&obj->p_obj, &status); + if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { + ret = 0; + } + + return ret; +} + +int spi_slave_receive(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + int ret = 1; + uint32_t status; + + tspi_get_status(&obj->p_obj, &status); + if ((status & (TSPI_RX_REACH_FILL_LEVEL_MASK)) == 0) { + ret = 0; + } + return ret; +} + +int spi_slave_read(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + uint8_t ret_value = 0; + ret_value = obj->p_obj.p_instance->DR & 0xFF; + obj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; + obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + + return ret_value; +} + +void spi_slave_write(spi_t *t_obj, int value) +{ + struct spi_s *obj = SPI_S(t_obj); + + // Enable TSPI Transmission Control. + obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + obj->p_obj.p_instance->DR = value & 0xFF; + +} + +uint8_t spi_get_module(spi_t *t_obj) +{ + struct spi_s *obj = SPI_S(t_obj); + return (uint8_t)(obj->module); +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SLAVE_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#if DEVICE_SPI_ASYNCH + +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, + uint32_t handler, uint32_t event, DMAUsage hint) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_irq_t *p_irqn = (spi_irq_t *)spiobj->irqn; + + + // check which use-case we have + bool use_tx = (tx != NULL && tx_length > 0); + bool use_rx = (rx != NULL && rx_length > 0); + + // don't do anything, if the buffers aren't valid + if (!use_tx && !use_rx) { + return; + } + + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + + obj->rx_buff.buffer = (void *)rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + spiobj->event = 0; + spiobj->state = SPI_TRANSFER_STATE_IDLE; + + + NVIC_SetVector(p_irqn->Error, (uint32_t)handler); + NVIC_SetVector(p_irqn->Tx, (uint32_t)handler); + NVIC_SetVector(p_irqn->Rx, (uint32_t)handler); + + // Enable Error Interrupt, Receive complete interrupt and Transmit complete interrupt + spiobj->p_obj.p_instance->CR2 |= (TSPI_TX_INT_ENABLE | TSPI_RX_INT_ENABLE | TSPI_ERR_INT_ENABLE); + + if (use_tx && use_rx) { + spiobj->max_size = tx_length < rx_length ? rx_length : tx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; + } else if (use_tx) { + spiobj->max_size = tx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = ((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF; + // Enable Interrupt bit in SPI peripheral - Enabled in init() + } else if (use_rx) { + spiobj->max_size = rx_length; + spiobj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + spiobj->p_obj.p_instance->DR = 0xFF; + } + spiobj->state = SPI_TRANSFER_STATE_BUSY; + NVIC_EnableIRQ(p_irqn->Error); + NVIC_EnableIRQ(p_irqn->Tx); + NVIC_EnableIRQ(p_irqn->Rx); +} +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + spi_irq_handler(obj); + return ((spiobj->event & SPI_EVENT_ALL) | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE) ; +} + +uint8_t spi_active(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + uint8_t ret_val = 0; + if (spiobj->state != SPI_TRANSFER_STATE_IDLE) { + ret_val = 1; + } + + return ret_val; +} + +void spi_abort_asynch(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + + disable_irq(spiobj->irqn); + clear_irq(spiobj->irqn); + tspi_init(&spiobj->p_obj); +} + +static void spi_irq_handler(spi_t *obj) +{ + struct spi_s *spiobj = SPI_S(obj); + if ((spiobj->p_obj.p_instance->SR & TSPI_RX_DONE) && + (spiobj->p_obj.p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK)) { + uint8_t rlvl = spiobj->p_obj.p_instance->SR & 0xF; + + while ((rlvl != 0) && (obj->rx_buff.pos < obj->rx_buff.length)) { + ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos++] = spiobj->p_obj.p_instance->DR & 0xFF; + rlvl--; + // transmit complete but receive pending - dummy write + } + + if (obj->rx_buff.pos == spiobj->max_size) { + spiobj->state = SPI_TRANSFER_STATE_IDLE; + } + spiobj->p_obj.p_instance->CR3 |= TSPI_RX_BUFF_CLR_DONE; + } + + if (spiobj->p_obj.p_instance->SR & TSPI_TX_DONE) { + + obj->tx_buff.pos++; + spiobj->p_obj.p_instance->SR |= TSPI_RX_DONE_CLR; + + if (obj->tx_buff.pos == (spiobj->max_size)) { + spiobj->state = SPI_TRANSFER_STATE_IDLE; + } + if ((obj->tx_buff.pos < obj->tx_buff.length) && (obj->tx_buff.pos < spiobj->max_size)) { + spiobj->p_obj.p_instance->DR = (((uint8_t *)obj->tx_buff.buffer)[obj->tx_buff.pos] & 0xFF); + } else if (obj->tx_buff.pos < spiobj->max_size) { + spiobj->p_obj.p_instance->DR = 0xFF; + } + } + + if (spiobj->p_obj.p_instance->ERR) { + spiobj->event = SPI_EVENT_ERROR; + spiobj->state = SPI_TRANSFER_STATE_IDLE; + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + return; + } + + if (spiobj->state == SPI_TRANSFER_STATE_IDLE) { + spiobj->event = SPI_EVENT_COMPLETE; + disable_irq(spiobj->irqn); + spiobj->p_obj.p_instance->SR |= (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + spiobj->p_obj.p_instance->CR3 |= (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + clear_irq(spiobj->irqn); + } + + +} + +static void disable_irq(uint32_t irqn) +{ + spi_irq_t *p_irqn = (spi_irq_t *)irqn; + NVIC_DisableIRQ(p_irqn->Tx); + NVIC_DisableIRQ(p_irqn->Rx); + NVIC_DisableIRQ(p_irqn->Error); +} + +static void clear_irq(uint32_t irqn) +{ + spi_irq_t *p_irqn = (spi_irq_t *)irqn; + NVIC_ClearPendingIRQ(p_irqn->Tx); + NVIC_ClearPendingIRQ(p_irqn->Rx); + NVIC_ClearPendingIRQ(p_irqn->Error); + + //clean-up +} + +#endif //DEVICE_SPI_ASYNCH diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/us_ticker.c new file mode 100644 index 0000000..8099a68 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4NR/us_ticker.c @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2022 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "TMPM4NR.h" +#include "txz_t32a.h" + +#define CLR_TIMER_INT_FLAG (uint8_t)0x41 + +static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? + +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + 3000000, + 32 + }; + return &info; +} + +// Initialize us_ticker +void us_ticker_init(void) +{ + if (us_ticker_inited) { + us_ticker_disable_interrupt(); + return; + } + us_ticker_inited = 1; + + // Enable clock for T32A0 + TSB_CG_FSYSMENA_IPMENA08 = TXZ_ENABLE; + + // T32A ch0 TimerC Reg Match/Over Flow/Under Flow + TSB_IB->IMC026 = TXZ_ENABLE; + + // Configure Timer T32A0 + TSB_T32A2->MOD = T32A_MODE_32; + TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A2->CRC = T32A_PRSCLx_32; + TSB_T32A2->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); + TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); + + NVIC_SetVector(INTT32A02_A_CT_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INTT32A02_A_CT_IRQn); +} + +uint32_t us_ticker_read(void) +{ + uint32_t ret_val = 0; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + ret_val = (TSB_T32A2->TMRC); + return ret_val; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + NVIC_DisableIRQ(INTT32A02_A_CT_IRQn); + TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A2->RGC1 = timestamp ; + NVIC_EnableIRQ(INTT32A02_A_CT_IRQn); + TSB_T32A2->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INTT32A02_A_CT_IRQn); + NVIC_EnableIRQ(INTT32A02_A_CT_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + // Disable interrupts in NVIC + TSB_IB->IMC026 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A02_A_CT_IRQn); + NVIC_DisableIRQ(INTT32A02_A_CT_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + TSB_IB->IMC026 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A02_A_CT_IRQn); +} + +void us_ticker_free(void) +{ + TSB_T32A2->RUNC = T32A_RUN_DISABLE; + TSB_IB->IMC026 = CLR_TIMER_INT_FLAG; + NVIC_ClearPendingIRQ(INTT32A02_A_CT_IRQn); + NVIC_DisableIRQ(INTT32A02_A_CT_IRQn); + TSB_CG_FSYSMENA_IPMENA08 = TXZ_DISABLE; +} diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h index 3c62f5b..51f1776 100644 --- a/targets/TARGET_TOSHIBA/mbed_rtx.h +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library * - * Copyright (C) 2019, Toshiba Electronic Device Solutions Corporation + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2022 * * SPDX-License-Identifier: Apache-2.0 * @@ -44,4 +44,20 @@ #endif +#if defined(TARGET_TMPM4NR) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20040000UL) +#endif + +#endif + +#if defined(TARGET_TMPM4GR) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20040000UL) +#endif + +#endif + #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index 0c2fb20..f26eff2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3207,18 +3207,16 @@ ], "public": false, "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x100000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x50000", "extra_labels_add": [ "STM32H723xG" ], "macros_add": [ + "MBED_SPLIT_HEAP", "STM32H723xx" ], "overrides": { - "system_power_supply": "PWR_LDO_SUPPLY" + "system_power_supply": "PWR_LDO_SUPPLY", + "i2c_timing_value_algo": true } }, "MCU_STM32H725xE": { @@ -3308,6 +3306,49 @@ ], "device_name": "STM32H743ZITx" }, + "NUCLEO_H723ZG": { + "inherits": [ + "MCU_STM32H723xG" + ], + "supported_toolchains": [ + "GCC_ARM" + ], + "extra_labels_add": [ + "STM32H723ZG" + ], + "config": { + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "8000000", + "macro_name": "HSE_VALUE" + }, + "d11_configuration": { + "help": "Value: PB_5 for the default board configuration, PA_7 in case of solder bridge update (SB33 on/ SB35 off)", + "value": "PB_5", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + }, + "usb_speed": { + "help": "USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_HS_IN_FS" + } + }, + "device_has_add": [ + "EMAC", + "USBDEVICE" + ], + "overrides": { + "clock_source": "USE_PLL_HSE_EXTC", + "lse_available": 1, + "network-default-interface-type": "ETHERNET" + }, + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "detect_code": [ + "0836" + ], + "device_name": "STM32H723ZGTx" + }, "MCU_STM32H745xI": { "inherits": [ "MCU_STM32H7" @@ -7380,6 +7421,194 @@ "1306" ] }, + "MCU_M460": { + "core": "Cortex-M4F", + "default_toolchain": "ARM", + "public": false, + "extra_labels": [ + "NUVOTON", + "M460", + "FLASH_CMSIS_ALGO", + "NUVOTON_EMAC" + ], + "is_disk_virtual": true, + "supported_toolchains": [ + "ARM", + "GCC_ARM", + "IAR" + ], + "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, + "usb-uart": { + "help": "Configure USB_UART. USB_UART and USB_UART_TX/USB_UART_RX must be consistent.", + "value": null + }, + "usb-uart-tx": { + "help": "Configure CONSOLE_TX. USB_UART and CONSOLE_TX/CONSOLE_RX must be consistent.", + "value": null + }, + "usb-uart-rx": { + "help": "Configure CONSOLE_RX. USB_UART and CONSOLE_TX/CONSOLE_RX must be consistent.", + "value": null + }, + "stdio-uart": { + "help": "Configure STDIO_UART. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART defaults to USB_UART.", + "value": null + }, + "stdio-uart-tx": { + "help": "Configure STDIO_UART_TX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_TX defaults to CONSOLE_TX.", + "value": null + }, + "stdio-uart-rx": { + "help": "Configure STDIO_UART_RX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_RX defaults to CONSOLE_RX.", + "value": null + }, + "gpio-irq-debounce-enable": { + "help": "Enable GPIO IRQ debounce", + "value": 0 + }, + "gpio-irq-debounce-enable-list": { + "help": "Comma separated pin list to enable GPIO IRQ debounce", + "value": "NC" + }, + "gpio-irq-debounce-clock-source": { + "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC", + "value": "GPIO_DBCTL_DBCLKSRC_LIRC" + }, + "gpio-irq-debounce-sample-rate": { + "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", + "value": "GPIO_DBCTL_DBCLKSEL_16" + }, + "exclude-uno-spi-from-fpga-ci-test-shield-test": { + "help": "Exclude UNO SPI pins (D8/D9/D10/D11/D12/D13) from FPGA CI Test Shield test for wiring to on-board SPI flash", + "options": [false, true], + "value": false + }, + "hbi-enable": { + "help": "Enable HBI for HyperRAM", + "options": [false, true] + }, + "hbi-mfp-reg-list": { + "help": "Comma separated multi-function pin register list to enable HBI for HyperRAM" + }, + "hbi-mfp-reg-msk-list": { + "help": "Comma separated multi-function pin register mask list to enable HBI for HyperRAM" + }, + "hbi-mfp-reg-val-list": { + "help": "Comma separated multi-function pin register value list to enable HBI for HyperRAM" + }, + "usb-device-hsusbd": { + "help": "Select high-speed USB device or not", + "value": 0 + } + }, + "inherits": [ + "Target" + ], + "macros_add": [ + "LPTICKER_DELAY_TICKS=4" + ], + "device_has": [ + "USTICKER", + "LPTICKER", + "RTC", + "ANALOGIN", + "ANALOGOUT", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SERIAL_ASYNCH", + "SERIAL_FC", + "STDIO_MESSAGES", + "SLEEP", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "TRNG", + "FLASH", + "MPU", + "WATCHDOG", + "RESET_REASON", + "EMAC", + "USBDEVICE" + ], + "components_add": [ + "FLASHIAP" + ], + "release_versions": [ + "5" + ], + "sectors": [ + [ + 0, + 4096 + ] + ], + "bootloader_supported": true, + "overrides": { + "deep-sleep-latency": 1, + "tickless-from-us-ticker": true + }, + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ], + "iar": [ + "std" + ] + }, + "supported_application_profiles": [ + "full", "bare-metal" + ] + }, + "NUMAKER_IOT_M467": { + "inherits": [ + "MCU_M460" + ], + "macros_add": [ + "MBEDTLS_CONFIG_HW_SUPPORT" + ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "detect_code": [ + "1313" + ], + "device_name": "M467HJHAE", + "overrides": { + "hxt-present": false, + "lxt-present": true, + "usb-uart": "UART_0", + "usb-uart-tx": "PB_13", + "usb-uart-rx": "PB_12", + "network-default-interface-type": "ETHERNET", + "exclude-uno-spi-from-fpga-ci-test-shield-test": true, + "hbi-enable": false, + "hbi-mfp-reg-list": "0x40000534, 0x4000057C, 0x40000590, 0x40000594", + "hbi-mfp-reg-msk-list": "0xFFFFFF00, 0xFFFFFFFF, 0xFFFF0000, 0xFFFFFFFF", + "hbi-mfp-reg-val-list": "0x10101000, 0x10101010, 0x10100000, 0x10101010" + } + }, "MCU_M480": { "core": "Cortex-M4F", "default_toolchain": "ARM", @@ -7842,7 +8071,8 @@ "SPI", "SPISLAVE", "SPI_ASYNCH", - "MPU" + "MPU", + "USBDEVICE" ], "release_versions": [ "5" @@ -9207,5 +9437,124 @@ "std" ] } + }, + "TMPM4NR": { + "inherits": [ + "Target" + ], + "core": "Cortex-M4F", + "is_disk_virtual": true, + "extra_labels": [ + "TOSHIBA" + ], + "macros": [ + "TMPM4NR" + ], + "supported_toolchains": [ + "GCC_ARM", + "ARM" + ], + "device_has": [ + "ANALOGIN", + "ANALOGOUT", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "RESET_REASON", + "SERIAL", + "SERIAL_FC", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "RTC", + "STDIO_MESSAGES", + "FLASH", + "SLEEP", + "USTICKER", + "MPU" + ], + "device_name": "TMPM4NRF20FG", + "detect_code": [ + "7022" + ], + "release_versions": [ + "5" + ], + "bootloader_supported": true, + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ] + } + + }, + "TMPM4GR": { + "inherits": [ + "Target" + ], + "core": "Cortex-M4F", + "is_disk_virtual": true, + "extra_labels": [ + "TOSHIBA" + ], + "macros": [ + "__TMPM4GR__" + ], + "supported_toolchains": [ + "GCC_ARM", + "ARM" + ], + "device_has": [ + "ANALOGIN", + "ANALOGOUT", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "RESET_REASON", + "SERIAL", + "SERIAL_FC", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "RTC", + "STDIO_MESSAGES", + "FLASH", + "SLEEP", + "USTICKER", + "MPU" + ], + "device_name": "TMPM4GRF20FG", + "detect_code": [ + "7021" + ], + "release_versions": [ + "5" + ], + "bootloader_supported": true, + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ] + } } }