diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_MICRO/gd32f450zi.sct b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_MICRO/gd32f450zi.sct
deleted file mode 100644
index 03be629..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_MICRO/gd32f450zi.sct
+++ /dev/null
@@ -1,26 +0,0 @@
-#! armcc -E
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *****
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START 0x08000000
-#endif
-
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE 0x200000
-#endif
-
-LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (3*1024K)
-
- ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ; 107 vectors (16 core + 91 peripheral) * 4 bytes = 428 bytes to reserve (0x1B0, 8-byte aligned)
- RW_IRAM1 (0x20000000+0x1B0) (0x20000-0x1B0) { ; RW data
- .ANY (+RW +ZI)
- }
-}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_MICRO/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_MICRO/startup_gd32f450.S
deleted file mode 100644
index f111982..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_MICRO/startup_gd32f450.S
+++ /dev/null
@@ -1,458 +0,0 @@
-;/*!
-; \file startup_gd32f450.S
-; \brief start up file
-;
-; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
-; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
-; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
-;*/
-;
-;/*
-; Copyright (c) 2018, GigaDevice Semiconductor Inc.
-;
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-;are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this
-; list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of the copyright holder nor the names of its contributors
-; may be used to endorse or promote products derived from this software without
-; specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-;OF SUCH DAMAGE.
-;*/
-
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000800
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
- EXPORT __initial_sp
-Stack_Mem SPACE Stack_Size
-__initial_sp EQU 0x20020000
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000400
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
- EXPORT __heap_base
- EXPORT __heap_limit
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit EQU (__initial_sp - Stack_Size)
-
- PRESERVE8
- THUMB
-
-; /* reset Vector Mapped to at Address 0 */
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
-; /* external interrupts handler */
- DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
- DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
- DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
- DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
- DCD FMC_IRQHandler ; 20:FMC
- DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
- DCD EXTI0_IRQHandler ; 22:EXTI Line 0
- DCD EXTI1_IRQHandler ; 23:EXTI Line 1
- DCD EXTI2_IRQHandler ; 24:EXTI Line 2
- DCD EXTI3_IRQHandler ; 25:EXTI Line 3
- DCD EXTI4_IRQHandler ; 26:EXTI Line 4
- DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
- DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
- DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
- DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
- DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
- DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
- DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
- DCD ADC_IRQHandler ; 34:ADC
- DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
- DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
- DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
- DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
- DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
- DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
- DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
- DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
- DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
- DCD TIMER1_IRQHandler ; 44:TIMER1
- DCD TIMER2_IRQHandler ; 45:TIMER2
- DCD TIMER3_IRQHandler ; 46:TIMER3
- DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
- DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
- DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
- DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
- DCD SPI0_IRQHandler ; 51:SPI0
- DCD SPI1_IRQHandler ; 52:SPI1
- DCD USART0_IRQHandler ; 53:USART0
- DCD USART1_IRQHandler ; 54:USART1
- DCD USART2_IRQHandler ; 55:USART2
- DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
- DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
- DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
- DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
- DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
- DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
- DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
- DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
- DCD EXMC_IRQHandler ; 64:EXMC
- DCD SDIO_IRQHandler ; 65:SDIO
- DCD TIMER4_IRQHandler ; 66:TIMER4
- DCD SPI2_IRQHandler ; 67:SPI2
- DCD UART3_IRQHandler ; 68:UART3
- DCD UART4_IRQHandler ; 69:UART4
- DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
- DCD TIMER6_IRQHandler ; 71:TIMER6
- DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
- DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
- DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
- DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
- DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
- DCD ENET_IRQHandler ; 77:Ethernet
- DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
- DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
- DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
- DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
- DCD USBFS_IRQHandler ; 83:USBFS
- DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
- DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
- DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
- DCD USART5_IRQHandler ; 87:USART5
- DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
- DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
- DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
- DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
- DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
- DCD USBHS_IRQHandler ; 93:USBHS
- DCD DCI_IRQHandler ; 94:DCI
- DCD 0 ; 95:Reserved
- DCD TRNG_IRQHandler ; 96:TRNG
- DCD FPU_IRQHandler ; 97:FPU
- DCD UART6_IRQHandler ; 98:UART6
- DCD UART7_IRQHandler ; 99:UART7
- DCD SPI3_IRQHandler ; 100:SPI3
- DCD SPI4_IRQHandler ; 101:SPI4
- DCD SPI5_IRQHandler ; 102:SPI5
- DCD 0 ; 103:Reserved
- DCD TLI_IRQHandler ; 104:TLI
- DCD TLI_ER_IRQHandler ; 105:TLI Error
- DCD IPA_IRQHandler ; 106:IPA
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-;/* reset Handler */
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-;/* dummy Exception Handlers */
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler\
- PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler\
- PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-; /* external interrupts handler */
- EXPORT WWDGT_IRQHandler [WEAK]
- EXPORT LVD_IRQHandler [WEAK]
- EXPORT TAMPER_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT RCU_CTC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA0_Channel0_IRQHandler [WEAK]
- EXPORT DMA0_Channel1_IRQHandler [WEAK]
- EXPORT DMA0_Channel2_IRQHandler [WEAK]
- EXPORT DMA0_Channel3_IRQHandler [WEAK]
- EXPORT DMA0_Channel4_IRQHandler [WEAK]
- EXPORT DMA0_Channel5_IRQHandler [WEAK]
- EXPORT DMA0_Channel6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN0_TX_IRQHandler [WEAK]
- EXPORT CAN0_RX0_IRQHandler [WEAK]
- EXPORT CAN0_RX1_IRQHandler [WEAK]
- EXPORT CAN0_EWMC_IRQHandler [WEAK]
- EXPORT EXTI5_9_IRQHandler [WEAK]
- EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
- EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
- EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
- EXPORT TIMER0_Channel_IRQHandler [WEAK]
- EXPORT TIMER1_IRQHandler [WEAK]
- EXPORT TIMER2_IRQHandler [WEAK]
- EXPORT TIMER3_IRQHandler [WEAK]
- EXPORT I2C0_EV_IRQHandler [WEAK]
- EXPORT I2C0_ER_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART0_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI10_15_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT USBFS_WKUP_IRQHandler [WEAK]
- EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
- EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
- EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
- EXPORT TIMER7_Channel_IRQHandler [WEAK]
- EXPORT DMA0_Channel7_IRQHandler [WEAK]
- EXPORT EXMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIMER4_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT TIMER5_DAC_IRQHandler [WEAK]
- EXPORT TIMER6_IRQHandler [WEAK]
- EXPORT DMA1_Channel0_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT ENET_WKUP_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_EWMC_IRQHandler [WEAK]
- EXPORT USBFS_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT USART5_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
- EXPORT USBHS_EP1_In_IRQHandler [WEAK]
- EXPORT USBHS_WKUP_IRQHandler [WEAK]
- EXPORT USBHS_IRQHandler [WEAK]
- EXPORT DCI_IRQHandler [WEAK]
- EXPORT TRNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT TLI_IRQHandler [WEAK]
- EXPORT TLI_ER_IRQHandler [WEAK]
- EXPORT IPA_IRQHandler [WEAK]
-
-;/* external interrupts handler */
-WWDGT_IRQHandler
-LVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FMC_IRQHandler
-RCU_CTC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA0_Channel0_IRQHandler
-DMA0_Channel1_IRQHandler
-DMA0_Channel2_IRQHandler
-DMA0_Channel3_IRQHandler
-DMA0_Channel4_IRQHandler
-DMA0_Channel5_IRQHandler
-DMA0_Channel6_IRQHandler
-ADC_IRQHandler
-CAN0_TX_IRQHandler
-CAN0_RX0_IRQHandler
-CAN0_RX1_IRQHandler
-CAN0_EWMC_IRQHandler
-EXTI5_9_IRQHandler
-TIMER0_BRK_TIMER8_IRQHandler
-TIMER0_UP_TIMER9_IRQHandler
-TIMER0_TRG_CMT_TIMER10_IRQHandler
-TIMER0_Channel_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-I2C0_EV_IRQHandler
-I2C0_ER_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-USART0_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI10_15_IRQHandler
-RTC_Alarm_IRQHandler
-USBFS_WKUP_IRQHandler
-TIMER7_BRK_TIMER11_IRQHandler
-TIMER7_UP_TIMER12_IRQHandler
-TIMER7_TRG_CMT_TIMER13_IRQHandler
-TIMER7_Channel_IRQHandler
-DMA0_Channel7_IRQHandler
-EXMC_IRQHandler
-SDIO_IRQHandler
-TIMER4_IRQHandler
-SPI2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-TIMER5_DAC_IRQHandler
-TIMER6_IRQHandler
-DMA1_Channel0_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-ENET_IRQHandler
-ENET_WKUP_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_EWMC_IRQHandler
-USBFS_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-USART5_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-USBHS_EP1_Out_IRQHandler
-USBHS_EP1_In_IRQHandler
-USBHS_WKUP_IRQHandler
-USBHS_IRQHandler
-DCI_IRQHandler
-TRNG_IRQHandler
-FPU_IRQHandler
-UART6_IRQHandler
-UART7_IRQHandler
-SPI3_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-TLI_IRQHandler
-TLI_ER_IRQHandler
-IPA_IRQHandler
-
- B .
- ENDP
-
- ALIGN
-
-; user Initial Stack & Heap
-
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_STD/gd32f450zi.sct b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_STD/gd32f450zi.sct
deleted file mode 100644
index 25d5e3e..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_STD/gd32f450zi.sct
+++ /dev/null
@@ -1,26 +0,0 @@
-#! armcc -E
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *****
-
-#if !defined(MBED_APP_START)
- #define MBED_APP_START 0x08000000
-#endif
-
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE 0x200000
-#endif
-
-LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (3*1024K)
-
- ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ; 107 vectors (16 core + 91 peripheral) * 4 bytes = 428 bytes to reserve (0x1B0, 8-byte aligned)
- RW_IRAM1 (0x20000000+0x1B0) (0x30000-0x1B0) { ; RW data
- .ANY (+RW +ZI)
- }
-}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_STD/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_STD/startup_gd32f450.S
deleted file mode 100644
index b2a1683..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_ARM_STD/startup_gd32f450.S
+++ /dev/null
@@ -1,458 +0,0 @@
-;/*!
-; \file startup_gd32f450.S
-; \brief start up file
-;
-; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
-; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
-; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
-;*/
-;
-;/*
-; Copyright (c) 2018, GigaDevice Semiconductor Inc.
-;
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-;are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this
-; list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of the copyright holder nor the names of its contributors
-; may be used to endorse or promote products derived from this software without
-; specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-;OF SUCH DAMAGE.
-;*/
-
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000800
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
- EXPORT __initial_sp
-Stack_Mem SPACE Stack_Size
-__initial_sp EQU 0x20030000
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000400
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
- EXPORT __heap_base
- EXPORT __heap_limit
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit EQU (__initial_sp - Stack_Size)
-
- PRESERVE8
- THUMB
-
-; /* reset Vector Mapped to at Address 0 */
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
-; /* external interrupts handler */
- DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
- DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
- DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
- DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
- DCD FMC_IRQHandler ; 20:FMC
- DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
- DCD EXTI0_IRQHandler ; 22:EXTI Line 0
- DCD EXTI1_IRQHandler ; 23:EXTI Line 1
- DCD EXTI2_IRQHandler ; 24:EXTI Line 2
- DCD EXTI3_IRQHandler ; 25:EXTI Line 3
- DCD EXTI4_IRQHandler ; 26:EXTI Line 4
- DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
- DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
- DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
- DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
- DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
- DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
- DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
- DCD ADC_IRQHandler ; 34:ADC
- DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
- DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
- DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
- DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
- DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
- DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
- DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
- DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
- DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
- DCD TIMER1_IRQHandler ; 44:TIMER1
- DCD TIMER2_IRQHandler ; 45:TIMER2
- DCD TIMER3_IRQHandler ; 46:TIMER3
- DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
- DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
- DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
- DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
- DCD SPI0_IRQHandler ; 51:SPI0
- DCD SPI1_IRQHandler ; 52:SPI1
- DCD USART0_IRQHandler ; 53:USART0
- DCD USART1_IRQHandler ; 54:USART1
- DCD USART2_IRQHandler ; 55:USART2
- DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
- DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
- DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
- DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
- DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
- DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
- DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
- DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
- DCD EXMC_IRQHandler ; 64:EXMC
- DCD SDIO_IRQHandler ; 65:SDIO
- DCD TIMER4_IRQHandler ; 66:TIMER4
- DCD SPI2_IRQHandler ; 67:SPI2
- DCD UART3_IRQHandler ; 68:UART3
- DCD UART4_IRQHandler ; 69:UART4
- DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
- DCD TIMER6_IRQHandler ; 71:TIMER6
- DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
- DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
- DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
- DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
- DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
- DCD ENET_IRQHandler ; 77:Ethernet
- DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
- DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
- DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
- DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
- DCD USBFS_IRQHandler ; 83:USBFS
- DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
- DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
- DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
- DCD USART5_IRQHandler ; 87:USART5
- DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
- DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
- DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
- DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
- DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
- DCD USBHS_IRQHandler ; 93:USBHS
- DCD DCI_IRQHandler ; 94:DCI
- DCD 0 ; 95:Reserved
- DCD TRNG_IRQHandler ; 96:TRNG
- DCD FPU_IRQHandler ; 97:FPU
- DCD UART6_IRQHandler ; 98:UART6
- DCD UART7_IRQHandler ; 99:UART7
- DCD SPI3_IRQHandler ; 100:SPI3
- DCD SPI4_IRQHandler ; 101:SPI4
- DCD SPI5_IRQHandler ; 102:SPI5
- DCD 0 ; 103:Reserved
- DCD TLI_IRQHandler ; 104:TLI
- DCD TLI_ER_IRQHandler ; 105:TLI Error
- DCD IPA_IRQHandler ; 106:IPA
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-;/* reset Handler */
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-;/* dummy Exception Handlers */
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler\
- PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler\
- PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-; /* external interrupts handler */
- EXPORT WWDGT_IRQHandler [WEAK]
- EXPORT LVD_IRQHandler [WEAK]
- EXPORT TAMPER_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT RCU_CTC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA0_Channel0_IRQHandler [WEAK]
- EXPORT DMA0_Channel1_IRQHandler [WEAK]
- EXPORT DMA0_Channel2_IRQHandler [WEAK]
- EXPORT DMA0_Channel3_IRQHandler [WEAK]
- EXPORT DMA0_Channel4_IRQHandler [WEAK]
- EXPORT DMA0_Channel5_IRQHandler [WEAK]
- EXPORT DMA0_Channel6_IRQHandler [WEAK]
- EXPORT ADC_IRQHandler [WEAK]
- EXPORT CAN0_TX_IRQHandler [WEAK]
- EXPORT CAN0_RX0_IRQHandler [WEAK]
- EXPORT CAN0_RX1_IRQHandler [WEAK]
- EXPORT CAN0_EWMC_IRQHandler [WEAK]
- EXPORT EXTI5_9_IRQHandler [WEAK]
- EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
- EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
- EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
- EXPORT TIMER0_Channel_IRQHandler [WEAK]
- EXPORT TIMER1_IRQHandler [WEAK]
- EXPORT TIMER2_IRQHandler [WEAK]
- EXPORT TIMER3_IRQHandler [WEAK]
- EXPORT I2C0_EV_IRQHandler [WEAK]
- EXPORT I2C0_ER_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT SPI0_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART0_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT EXTI10_15_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT USBFS_WKUP_IRQHandler [WEAK]
- EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
- EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
- EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
- EXPORT TIMER7_Channel_IRQHandler [WEAK]
- EXPORT DMA0_Channel7_IRQHandler [WEAK]
- EXPORT EXMC_IRQHandler [WEAK]
- EXPORT SDIO_IRQHandler [WEAK]
- EXPORT TIMER4_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT UART3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT TIMER5_DAC_IRQHandler [WEAK]
- EXPORT TIMER6_IRQHandler [WEAK]
- EXPORT DMA1_Channel0_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT ENET_IRQHandler [WEAK]
- EXPORT ENET_WKUP_IRQHandler [WEAK]
- EXPORT CAN1_TX_IRQHandler [WEAK]
- EXPORT CAN1_RX0_IRQHandler [WEAK]
- EXPORT CAN1_RX1_IRQHandler [WEAK]
- EXPORT CAN1_EWMC_IRQHandler [WEAK]
- EXPORT USBFS_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT USART5_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
- EXPORT USBHS_EP1_In_IRQHandler [WEAK]
- EXPORT USBHS_WKUP_IRQHandler [WEAK]
- EXPORT USBHS_IRQHandler [WEAK]
- EXPORT DCI_IRQHandler [WEAK]
- EXPORT TRNG_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT UART6_IRQHandler [WEAK]
- EXPORT UART7_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
- EXPORT SPI5_IRQHandler [WEAK]
- EXPORT TLI_IRQHandler [WEAK]
- EXPORT TLI_ER_IRQHandler [WEAK]
- EXPORT IPA_IRQHandler [WEAK]
-
-;/* external interrupts handler */
-WWDGT_IRQHandler
-LVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FMC_IRQHandler
-RCU_CTC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA0_Channel0_IRQHandler
-DMA0_Channel1_IRQHandler
-DMA0_Channel2_IRQHandler
-DMA0_Channel3_IRQHandler
-DMA0_Channel4_IRQHandler
-DMA0_Channel5_IRQHandler
-DMA0_Channel6_IRQHandler
-ADC_IRQHandler
-CAN0_TX_IRQHandler
-CAN0_RX0_IRQHandler
-CAN0_RX1_IRQHandler
-CAN0_EWMC_IRQHandler
-EXTI5_9_IRQHandler
-TIMER0_BRK_TIMER8_IRQHandler
-TIMER0_UP_TIMER9_IRQHandler
-TIMER0_TRG_CMT_TIMER10_IRQHandler
-TIMER0_Channel_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-I2C0_EV_IRQHandler
-I2C0_ER_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-SPI0_IRQHandler
-SPI1_IRQHandler
-USART0_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-EXTI10_15_IRQHandler
-RTC_Alarm_IRQHandler
-USBFS_WKUP_IRQHandler
-TIMER7_BRK_TIMER11_IRQHandler
-TIMER7_UP_TIMER12_IRQHandler
-TIMER7_TRG_CMT_TIMER13_IRQHandler
-TIMER7_Channel_IRQHandler
-DMA0_Channel7_IRQHandler
-EXMC_IRQHandler
-SDIO_IRQHandler
-TIMER4_IRQHandler
-SPI2_IRQHandler
-UART3_IRQHandler
-UART4_IRQHandler
-TIMER5_DAC_IRQHandler
-TIMER6_IRQHandler
-DMA1_Channel0_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-ENET_IRQHandler
-ENET_WKUP_IRQHandler
-CAN1_TX_IRQHandler
-CAN1_RX0_IRQHandler
-CAN1_RX1_IRQHandler
-CAN1_EWMC_IRQHandler
-USBFS_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-USART5_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-USBHS_EP1_Out_IRQHandler
-USBHS_EP1_In_IRQHandler
-USBHS_WKUP_IRQHandler
-USBHS_IRQHandler
-DCI_IRQHandler
-TRNG_IRQHandler
-FPU_IRQHandler
-UART6_IRQHandler
-UART7_IRQHandler
-SPI3_IRQHandler
-SPI4_IRQHandler
-SPI5_IRQHandler
-TLI_IRQHandler
-TLI_ER_IRQHandler
-IPA_IRQHandler
-
- B .
- ENDP
-
- ALIGN
-
-; user Initial Stack & Heap
-
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap PROC
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
- ENDP
-
- ALIGN
-
- ENDIF
-
- END
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_GCC_ARM/GD32F450xI.ld b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_GCC_ARM/GD32F450xI.ld
deleted file mode 100644
index 65b9f67..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_GCC_ARM/GD32F450xI.ld
+++ /dev/null
@@ -1,131 +0,0 @@
-#if !defined(MBED_APP_START)
- #define MBED_APP_START 0x08000000
-#endif
-
-#if !defined(MBED_APP_SIZE)
- #define MBED_APP_SIZE 2048k
-#endif
-
-/* specify memory regions */
-MEMORY
-{
- FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
- RAM (rwx) : ORIGIN = 0x200001B0, LENGTH = 192K - 0x1B0
- TCMSRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
-}
-
-/* define output sections */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
- _sidata = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- _sdata = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(8);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(8);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(8);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- KEEP(*(.jcr*))
- . = ALIGN(8);
- /* All data end */
- __data_end__ = .;
- _edata = .;
-
- } > RAM
-
- .bss :
- {
- . = ALIGN(8);
- __bss_start__ = .;
- _sbss = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(8);
- __bss_end__ = .;
- _ebss = .;
- } > RAM
-
- .heap (COPY):
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
-
- /* initializes stack on the end of block */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_GCC_ARM/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_GCC_ARM/startup_gd32f450.S
deleted file mode 100644
index d8ca9e6..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_GCC_ARM/startup_gd32f450.S
+++ /dev/null
@@ -1,518 +0,0 @@
-;/*!
-; \file startup_gd32f450.S
-; \brief start up file
-;
-; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
-; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
-; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
-;*/
-;
-;/*
-; Copyright (c) 2018, GigaDevice Semiconductor Inc.
-;
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-;are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this
-; list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of the copyright holder nor the names of its contributors
-; may be used to endorse or promote products derived from this software without
-; specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-;OF SUCH DAMAGE.
-;*/
-
-.syntax unified
-.cpu cortex-m4
-.fpu softvfp
-.thumb
-
-.global VecTab
-.global Default_Handler
-
-/* start address of the initialization .data */
-.word _sidata
-/* start address of the .data section */
-.word _sdata
-/* end address of the .data section */
-.word _edata
-/* start address of the .bss section */
-.word _sbss
-/* end address of the .bss section */
-.word _ebss
-
-/* reset Handler */
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* copy the data segment into RAM */
- movs r1, #0
- b DataInit
-
-CopyData:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-DataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyData
- ldr r2, =_sbss
- ldr r3, =_ebss
- cmp r2, r3
- bcc ZeroFill
-
-ZeroFill:
- movs r3, #0
- str r3, [r2], #4
-
-/* system clock intitialization*/
- bl SystemInit
-/* static constructors */
-// bl __libc_init_array
-/* jump to application's entry point */
-// bl main
- bl _start
-
- bx lr
-
-
-.size Reset_Handler, .-Reset_Handler
-
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-/* infinite loop */
- b .
- .size Default_Handler, .-Default_Handler
-
- .section .isr_vector,"a",%progbits
- .type VecTab, %object
- .size VecTab, .-VecTab
-
-VecTab:
- .word _estack /* Top of Stack */
- .word Reset_Handler /* Reset Handler */
- .word NMI_Handler /* NMI Handler */
- .word HardFault_Handler /* Hard Fault Handler */
- .word MemManage_Handler /* MPU Fault Handler */
- .word BusFault_Handler /* Bus Fault Handler */
- .word UsageFault_Handler /* Usage Fault Handler */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word SVC_Handler /* SVCall Handler */
- .word DebugMon_Handler /* Debug Monitor Handler */
- .word 0 /* Reserved */
- .word PendSV_Handler /* PendSV Handler */
- .word SysTick_Handler /* SysTick Handler */
-
- /* external interrupts handler */
- .word WWDGT_IRQHandler /* 16:Window Watchdog Timer */
- .word LVD_IRQHandler /* 17:LVD through EXTI Line detect */
- .word TAMPER_STAMP_IRQHandler /* 18:Tamper and TimeStamp through EXTI Line detect */
- .word RTC_WKUP_IRQHandler /* 19:RTC Wakeup through EXTI Line */
- .word FMC_IRQHandler /* 20:FMC */
- .word RCU_CTC_IRQHandler /* 21:RCU and CTC */
- .word EXTI0_IRQHandler /* 22:EXTI Line 0 */
- .word EXTI1_IRQHandler /* 23:EXTI Line 1 */
- .word EXTI2_IRQHandler /* 24:EXTI Line 2 */
- .word EXTI3_IRQHandler /* 25:EXTI Line 3 */
- .word EXTI4_IRQHandler /* 26:EXTI Line 4 */
- .word DMA0_Channel0_IRQHandler /* 27:DMA0 Channel0 */
- .word DMA0_Channel1_IRQHandler /* 28:DMA0 Channel1 */
- .word DMA0_Channel2_IRQHandler /* 29:DMA0 Channel2 */
- .word DMA0_Channel3_IRQHandler /* 30:DMA0 Channel3 */
- .word DMA0_Channel4_IRQHandler /* 31:DMA0 Channel4 */
- .word DMA0_Channel5_IRQHandler /* 32:DMA0 Channel5 */
- .word DMA0_Channel6_IRQHandler /* 33:DMA0 Channel6 */
- .word ADC_IRQHandler /* 34:ADC */
- .word CAN0_TX_IRQHandler /* 35:CAN0 TX */
- .word CAN0_RX0_IRQHandler /* 36:CAN0 RX0 */
- .word CAN0_RX1_IRQHandler /* 37:CAN0 RX1 */
- .word CAN0_EWMC_IRQHandler /* 38:CAN0 EWMC */
- .word EXTI5_9_IRQHandler /* 39:EXTI5 to EXTI9 */
- .word TIMER0_BRK_TIMER8_IRQHandler /* 40:TIMER0 Break and TIMER8 */
- .word TIMER0_UP_TIMER9_IRQHandler /* 41:TIMER0 Update and TIMER9 */
- .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* 42:TIMER0 Trigger and Commutation and TIMER10 */
- .word TIMER0_Channel_IRQHandler /* 43:TIMER0 Capture Compare */
- .word TIMER1_IRQHandler /* 44:TIMER1 */
- .word TIMER2_IRQHandler /* 45:TIMER2 */
- .word TIMER3_IRQHandler /* 46:TIMER3 */
- .word I2C0_EV_IRQHandler /* 47:I2C0 Event */
- .word I2C0_ER_IRQHandler /* 48:I2C0 Error */
- .word I2C1_EV_IRQHandler /* 49:I2C1 Event */
- .word I2C1_ER_IRQHandler /* 50:I2C1 Error */
- .word SPI0_IRQHandler /* 51:SPI0 */
- .word SPI1_IRQHandler /* 52:SPI1 */
- .word USART0_IRQHandler /* 53:USART0 */
- .word USART1_IRQHandler /* 54:USART1 */
- .word USART2_IRQHandler /* 55:USART2 */
- .word EXTI10_15_IRQHandler /* 56:EXTI10 to EXTI15 */
- .word RTC_Alarm_IRQHandler /* 57:RTC Alarm */
- .word USBFS_WKUP_IRQHandler /* 58:USBFS Wakeup */
- .word TIMER7_BRK_TIMER11_IRQHandler /* 59:TIMER7 Break and TIMER11 */
- .word TIMER7_UP_TIMER12_IRQHandler /* 60:TIMER7 Update and TIMER12 */
- .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* 61:TIMER7 Trigger and Commutation and TIMER13 */
- .word TIMER7_Channel_IRQHandler /* 62:TIMER7 Channel Capture Compare */
- .word DMA0_Channel7_IRQHandler /* 63:DMA0 Channel7 */
- .word EXMC_IRQHandler /* 64:EXMC */
- .word SDIO_IRQHandler /* 65:SDIO */
- .word TIMER4_IRQHandler /* 66:TIMER4 */
- .word SPI2_IRQHandler /* 67:SPI2 */
- .word UART3_IRQHandler /* 68:UART3 */
- .word UART4_IRQHandler /* 69:UART4 */
- .word TIMER5_DAC_IRQHandler /* 70:TIMER5 and DAC0 DAC1 Underrun error */
- .word TIMER6_IRQHandler /* 71:TIMER6 */
- .word DMA1_Channel0_IRQHandler /* 72:DMA1 Channel0 */
- .word DMA1_Channel1_IRQHandler /* 73:DMA1 Channel1 */
- .word DMA1_Channel2_IRQHandler /* 74:DMA1 Channel2 */
- .word DMA1_Channel3_IRQHandler /* 75:DMA1 Channel3 */
- .word DMA1_Channel4_IRQHandler /* 76:DMA1 Channel4 */
- .word ENET_IRQHandler /* 77:Ethernet */
- .word ENET_WKUP_IRQHandler /* 78:Ethernet Wakeup through EXTI Line */
- .word CAN1_TX_IRQHandler /* 79:CAN1 TX */
- .word CAN1_RX0_IRQHandler /* 80:CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* 81:CAN1 RX1 */
- .word CAN1_EWMC_IRQHandler /* 82:CAN1 EWMC */
- .word USBFS_IRQHandler /* 83:USBFS */
- .word DMA1_Channel5_IRQHandler /* 84:DMA1 Channel5 */
- .word DMA1_Channel6_IRQHandler /* 85:DMA1 Channel6 */
- .word DMA1_Channel7_IRQHandler /* 86:DMA1 Channel7 */
- .word USART5_IRQHandler /* 87:USART5 */
- .word I2C2_EV_IRQHandler /* 88:I2C2 Event */
- .word I2C2_ER_IRQHandler /* 89:I2C2 Error */
- .word USBHS_EP1_Out_IRQHandler /* 90:USBHS Endpoint 1 Out */
- .word USBHS_EP1_In_IRQHandler /* 91:USBHS Endpoint 1 in */
- .word USBHS_WKUP_IRQHandler /* 92:USBHS Wakeup through EXTI Line */
- .word USBHS_IRQHandler /* 93:USBHS */
- .word DCI_IRQHandler /* 94:DCI */
- .word 0 /* 95:Reserved */
- .word TRNG_IRQHandler /* 96:TRNG */
- .word FPU_IRQHandler /* 97:FPU */
- .word UART6_IRQHandler /* 98:UART6 */
- .word UART7_IRQHandler /* 99:UART7 */
- .word SPI3_IRQHandler /* 100:SPI3 */
- .word SPI4_IRQHandler /* 101:SPI4 */
- .word SPI5_IRQHandler /* 102:SPI5 */
- .word 0 /* 103:Reserved */
- .word TLI_IRQHandler /* 104:TLI */
- .word TLI_ER_IRQHandler /* 105:TLI Error */
- .word IPA_IRQHandler /* 106:IPA */
-
-/* dummy Exception Handlers */
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDGT_IRQHandler
- .thumb_set WWDGT_IRQHandler,Default_Handler
-
- .weak LVD_IRQHandler
- .thumb_set LVD_IRQHandler,Default_Handler
-
- .weak TAMPER_STAMP_IRQHandler
- .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
- .thumb_set FMC_IRQHandler,Default_Handler
-
- .weak RCU_CTC_IRQHandler
- .thumb_set RCU_CTC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA0_Channel0_IRQHandler
- .thumb_set DMA0_Channel0_IRQHandler,Default_Handler
-
- .weak DMA0_Channel1_IRQHandler
- .thumb_set DMA0_Channel1_IRQHandler,Default_Handler
-
- .weak DMA0_Channel2_IRQHandler
- .thumb_set DMA0_Channel2_IRQHandler,Default_Handler
-
- .weak DMA0_Channel3_IRQHandler
- .thumb_set DMA0_Channel3_IRQHandler,Default_Handler
-
- .weak DMA0_Channel4_IRQHandler
- .thumb_set DMA0_Channel4_IRQHandler,Default_Handler
-
- .weak DMA0_Channel5_IRQHandler
- .thumb_set DMA0_Channel5_IRQHandler,Default_Handler
-
- .weak DMA0_Channel6_IRQHandler
- .thumb_set DMA0_Channel6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN0_TX_IRQHandler
- .thumb_set CAN0_TX_IRQHandler,Default_Handler
-
- .weak CAN0_RX0_IRQHandler
- .thumb_set CAN0_RX0_IRQHandler,Default_Handler
-
- .weak CAN0_RX1_IRQHandler
- .thumb_set CAN0_RX1_IRQHandler,Default_Handler
-
- .weak CAN0_EWMC_IRQHandler
- .thumb_set CAN0_EWMC_IRQHandler,Default_Handler
-
- .weak EXTI5_9_IRQHandler
- .thumb_set EXTI5_9_IRQHandler,Default_Handler
-
- .weak TIMER0_BRK_TIMER8_IRQHandler
- .thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
-
- .weak TIMER0_UP_TIMER9_IRQHandler
- .thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
-
- .weak TIMER0_TRG_CMT_TIMER10_IRQHandler
- .thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
-
- .weak TIMER0_Channel_IRQHandler
- .thumb_set TIMER0_Channel_IRQHandler,Default_Handler
-
- .weak TIMER1_IRQHandler
- .thumb_set TIMER1_IRQHandler,Default_Handler
-
- .weak TIMER2_IRQHandler
- .thumb_set TIMER2_IRQHandler,Default_Handler
-
- .weak TIMER3_IRQHandler
- .thumb_set TIMER3_IRQHandler,Default_Handler
-
- .weak I2C0_EV_IRQHandler
- .thumb_set I2C0_EV_IRQHandler,Default_Handler
-
- .weak I2C0_ER_IRQHandler
- .thumb_set I2C0_ER_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak SPI0_IRQHandler
- .thumb_set SPI0_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART0_IRQHandler
- .thumb_set USART0_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak EXTI10_15_IRQHandler
- .thumb_set EXTI10_15_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak USBFS_WKUP_IRQHandler
- .thumb_set USBFS_WKUP_IRQHandler,Default_Handler
-
- .weak TIMER7_BRK_TIMER11_IRQHandler
- .thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
-
- .weak TIMER7_UP_TIMER12_IRQHandler
- .thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
-
- .weak TIMER7_TRG_CMT_TIMER13_IRQHandler
- .thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
-
- .weak TIMER7_Channel_IRQHandler
- .thumb_set TIMER7_Channel_IRQHandler,Default_Handler
-
- .weak DMA0_Channel7_IRQHandler
- .thumb_set DMA0_Channel7_IRQHandler,Default_Handler
-
- .weak EXMC_IRQHandler
- .thumb_set EXMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIMER4_IRQHandler
- .thumb_set TIMER4_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak UART3_IRQHandler
- .thumb_set UART3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak TIMER5_DAC_IRQHandler
- .thumb_set TIMER5_DAC_IRQHandler,Default_Handler
-
- .weak TIMER6_IRQHandler
- .thumb_set TIMER6_IRQHandler,Default_Handler
-
- .weak DMA1_Channel0_IRQHandler
- .thumb_set DMA1_Channel0_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_IRQHandler
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
- .weak DMA1_Channel3_IRQHandler
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_IRQHandler
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
- .weak ENET_IRQHandler
- .thumb_set ENET_IRQHandler,Default_Handler
-
- .weak ENET_WKUP_IRQHandler
- .thumb_set ENET_WKUP_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_EWMC_IRQHandler
- .thumb_set CAN1_EWMC_IRQHandler,Default_Handler
-
- .weak USBFS_IRQHandler
- .thumb_set USBFS_IRQHandler,Default_Handler
-
- .weak DMA1_Channel5_IRQHandler
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
- .weak DMA1_Channel6_IRQHandler
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
- .weak DMA1_Channel7_IRQHandler
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
- .weak USART5_IRQHandler
- .thumb_set USART5_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak USBHS_EP1_Out_IRQHandler
- .thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
-
- .weak USBHS_EP1_In_IRQHandler
- .thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
-
- .weak USBHS_WKUP_IRQHandler
- .thumb_set USBHS_WKUP_IRQHandler,Default_Handler
-
- .weak USBHS_IRQHandler
- .thumb_set USBHS_IRQHandler,Default_Handler
-
- .weak DCI_IRQHandler
- .thumb_set DCI_IRQHandler,Default_Handler
-
- .weak TRNG_IRQHandler
- .thumb_set TRNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak UART6_IRQHandler
- .thumb_set UART6_IRQHandler,Default_Handler
-
- .weak UART7_IRQHandler
- .thumb_set UART7_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
- .thumb_set SPI5_IRQHandler,Default_Handler
-
- .weak TLI_IRQHandler
- .thumb_set TLI_IRQHandler,Default_Handler
-
- .weak TLI_ER_IRQHandler
- .thumb_set TLI_ER_IRQHandler,Default_Handler
-
- .weak IPA_IRQHandler
- .thumb_set IPA_IRQHandler,Default_Handler
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_IAR/gd32f450zi.icf b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_IAR/gd32f450zi.icf
deleted file mode 100644
index 8f649ad..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_IAR/gd32f450zi.icf
+++ /dev/null
@@ -1,39 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-
-if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
-if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; }
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
-define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
-define symbol __ICFEDIT_region_TCMSRAM_start__ = 0x10000000;
-define symbol __ICFEDIT_region_TCMSRAM_end__ = 0x1000FFFF;
-define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
-define symbol __ICFEDIT_region_NVIC_end__ = 0x200001AF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x200001B0;
-define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x10000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region TCMSRAM_region = mem:[from __ICFEDIT_region_TCMSRAM_start__ to __ICFEDIT_region_TCMSRAM_end__];
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_IAR/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_IAR/startup_gd32f450.S
deleted file mode 100644
index a8a317c..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/TOOLCHAIN_IAR/startup_gd32f450.S
+++ /dev/null
@@ -1,667 +0,0 @@
-;/*!
-; \file startup_gd32f450.S
-; \brief start up file
-;
-; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
-; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
-; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
-;*/
-;
-;/*
-; Copyright (c) 2018, GigaDevice Semiconductor Inc.
-;
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without modification,
-;are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice, this
-; list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of the copyright holder nor the names of its contributors
-; may be used to endorse or promote products derived from this software without
-; specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-;OF SUCH DAMAGE.
-;*/
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK) ; top of stack
- DCD Reset_Handler ; Vector Number 1,Reset Handler
-
- DCD NMI_Handler ; Vector Number 2,NMI Handler
- DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
- DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
- DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
- DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; Vector Number 11,SVCall Handler
- DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; Vector Number 14,PendSV Handler
- DCD SysTick_Handler ; Vector Number 15,SysTick Handler
-
- ; External Interrupts
- DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
- DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
- DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
- DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
- DCD FMC_IRQHandler ; 20:FMC
- DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
- DCD EXTI0_IRQHandler ; 22:EXTI Line 0
- DCD EXTI1_IRQHandler ; 23:EXTI Line 1
- DCD EXTI2_IRQHandler ; 24:EXTI Line 2
- DCD EXTI3_IRQHandler ; 25:EXTI Line 3
- DCD EXTI4_IRQHandler ; 26:EXTI Line 4
- DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
- DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
- DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
- DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
- DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
- DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
- DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
- DCD ADC_IRQHandler ; 34:ADC
- DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
- DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
- DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
- DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
- DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
- DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
- DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
- DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
- DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
- DCD TIMER1_IRQHandler ; 44:TIMER1
- DCD TIMER2_IRQHandler ; 45:TIMER2
- DCD TIMER3_IRQHandler ; 46:TIMER3
- DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
- DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
- DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
- DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
- DCD SPI0_IRQHandler ; 51:SPI0
- DCD SPI1_IRQHandler ; 52:SPI1
- DCD USART0_IRQHandler ; 53:USART0
- DCD USART1_IRQHandler ; 54:USART1
- DCD USART2_IRQHandler ; 55:USART2
- DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
- DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
- DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
- DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
- DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
- DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
- DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
- DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
- DCD EXMC_IRQHandler ; 64:EXMC
- DCD SDIO_IRQHandler ; 65:SDIO
- DCD TIMER4_IRQHandler ; 66:TIMER4
- DCD SPI2_IRQHandler ; 67:SPI2
- DCD UART3_IRQHandler ; 68:UART3
- DCD UART4_IRQHandler ; 69:UART4
- DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
- DCD TIMER6_IRQHandler ; 71:TIMER6
- DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
- DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
- DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
- DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
- DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
- DCD ENET_IRQHandler ; 77:Ethernet
- DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
- DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
- DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
- DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
- DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
- DCD USBFS_IRQHandler ; 83:USBFS
- DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
- DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
- DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
- DCD USART5_IRQHandler ; 87:USART5
- DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
- DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
- DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
- DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
- DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
- DCD USBHS_IRQHandler ; 93:USBHS
- DCD DCI_IRQHandler ; 94:DCI
- DCD 0 ; 95:Reserved
- DCD TRNG_IRQHandler ; 96:TRNG
- DCD FPU_IRQHandler ; 97:FPU
- DCD UART6_IRQHandler ; 98:UART6
- DCD UART7_IRQHandler ; 99:UART7
- DCD SPI3_IRQHandler ; 100:SPI3
- DCD SPI4_IRQHandler ; 101:SPI4
- DCD SPI5_IRQHandler ; 102:SPI5
- DCD 0 ; 103:Reserved
- DCD TLI_IRQHandler ; 104:TLI
- DCD TLI_ER_IRQHandler ; 105:TLI Error
- DCD IPA_IRQHandler ; 106:IPA
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDGT_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDGT_IRQHandler
- B WWDGT_IRQHandler
-
- PUBWEAK LVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-LVD_IRQHandler
- B LVD_IRQHandler
-
- PUBWEAK TAMPER_STAMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TAMPER_STAMP_IRQHandler
- B TAMPER_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FMC_IRQHandler
- B FMC_IRQHandler
-
- PUBWEAK RCU_CTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCU_CTC_IRQHandler
- B RCU_CTC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
- B EXTI2_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA0_Channel0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel0_IRQHandler
- B DMA0_Channel0_IRQHandler
-
- PUBWEAK DMA0_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel1_IRQHandler
- B DMA0_Channel1_IRQHandler
-
- PUBWEAK DMA0_Channel2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel2_IRQHandler
- B DMA0_Channel2_IRQHandler
-
- PUBWEAK DMA0_Channel3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel3_IRQHandler
- B DMA0_Channel3_IRQHandler
-
- PUBWEAK DMA0_Channel4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel4_IRQHandler
- B DMA0_Channel4_IRQHandler
-
- PUBWEAK DMA0_Channel5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel5_IRQHandler
- B DMA0_Channel5_IRQHandler
-
- PUBWEAK DMA0_Channel6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel6_IRQHandler
- B DMA0_Channel6_IRQHandler
-
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
- B ADC_IRQHandler
-
- PUBWEAK CAN0_TX_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN0_TX_IRQHandler
- B CAN0_TX_IRQHandler
-
- PUBWEAK CAN0_RX0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN0_RX0_IRQHandler
- B CAN0_RX0_IRQHandler
-
- PUBWEAK CAN0_RX1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN0_RX1_IRQHandler
- B CAN0_RX1_IRQHandler
-
- PUBWEAK CAN0_EWMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN0_EWMC_IRQHandler
- B CAN0_EWMC_IRQHandler
-
- PUBWEAK EXTI5_9_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI5_9_IRQHandler
- B EXTI5_9_IRQHandler
-
- PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER0_BRK_TIMER8_IRQHandler
- B TIMER0_BRK_TIMER8_IRQHandler
-
- PUBWEAK TIMER0_UP_TIMER9_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER0_UP_TIMER9_IRQHandler
- B TIMER0_UP_TIMER9_IRQHandler
-
- PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER0_TRG_CMT_TIMER10_IRQHandler
- B TIMER0_TRG_CMT_TIMER10_IRQHandler
-
- PUBWEAK TIMER0_Channel_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER0_Channel_IRQHandler
- B TIMER0_Channel_IRQHandler
-
- PUBWEAK TIMER1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER1_IRQHandler
- B TIMER1_IRQHandler
-
- PUBWEAK TIMER2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER2_IRQHandler
- B TIMER2_IRQHandler
-
- PUBWEAK TIMER3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER3_IRQHandler
- B TIMER3_IRQHandler
-
- PUBWEAK I2C0_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C0_EV_IRQHandler
- B I2C0_EV_IRQHandler
-
- PUBWEAK I2C0_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C0_ER_IRQHandler
- B I2C0_ER_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK SPI0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI0_IRQHandler
- B SPI0_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK USART0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART0_IRQHandler
- B USART0_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK EXTI10_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI10_15_IRQHandler
- B EXTI10_15_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK USBFS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBFS_WKUP_IRQHandler
- B USBFS_WKUP_IRQHandler
-
- PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER7_BRK_TIMER11_IRQHandler
- B TIMER7_BRK_TIMER11_IRQHandler
-
- PUBWEAK TIMER7_UP_TIMER12_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER7_UP_TIMER12_IRQHandler
- B TIMER7_UP_TIMER12_IRQHandler
-
- PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER7_TRG_CMT_TIMER13_IRQHandler
- B TIMER7_TRG_CMT_TIMER13_IRQHandler
-
- PUBWEAK TIMER7_Channel_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER7_Channel_IRQHandler
- B TIMER7_Channel_IRQHandler
-
- PUBWEAK DMA0_Channel7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA0_Channel7_IRQHandler
- B DMA0_Channel7_IRQHandler
-
- PUBWEAK EXMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXMC_IRQHandler
- B EXMC_IRQHandler
-
- PUBWEAK SDIO_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SDIO_IRQHandler
- B SDIO_IRQHandler
-
- PUBWEAK TIMER4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER4_IRQHandler
- B TIMER4_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK UART3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART3_IRQHandler
- B UART3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK TIMER5_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER5_DAC_IRQHandler
- B TIMER5_DAC_IRQHandler
-
- PUBWEAK TIMER6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIMER6_IRQHandler
- B TIMER6_IRQHandler
-
- PUBWEAK DMA1_Channel0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel0_IRQHandler
- B DMA1_Channel0_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK ENET_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ENET_IRQHandler
- B ENET_IRQHandler
-
- PUBWEAK ENET_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ENET_WKUP_IRQHandler
- B ENET_WKUP_IRQHandler
-
- PUBWEAK CAN1_TX_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN1_TX_IRQHandler
- B CAN1_TX_IRQHandler
-
- PUBWEAK CAN1_RX0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN1_RX0_IRQHandler
- B CAN1_RX0_IRQHandler
-
- PUBWEAK CAN1_RX1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN1_RX1_IRQHandler
- B CAN1_RX1_IRQHandler
-
- PUBWEAK CAN1_EWMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN1_EWMC_IRQHandler
- B CAN1_EWMC_IRQHandler
-
- PUBWEAK USBFS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBFS_IRQHandler
- B USBFS_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK USART5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART5_IRQHandler
- B USART5_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK USBHS_EP1_Out_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBHS_EP1_Out_IRQHandler
- B USBHS_EP1_Out_IRQHandler
-
- PUBWEAK USBHS_EP1_In_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBHS_EP1_In_IRQHandler
- B USBHS_EP1_In_IRQHandler
-
- PUBWEAK USBHS_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBHS_WKUP_IRQHandler
- B USBHS_WKUP_IRQHandler
-
- PUBWEAK USBHS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBHS_IRQHandler
- B USBHS_IRQHandler
-
- PUBWEAK DCI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DCI_IRQHandler
- B DCI_IRQHandler
-
- PUBWEAK TRNG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TRNG_IRQHandler
- B TRNG_IRQHandler
-
- PUBWEAK FPU_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FPU_IRQHandler
- B FPU_IRQHandler
-
- PUBWEAK UART6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART6_IRQHandler
- B UART6_IRQHandler
-
- PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART7_IRQHandler
- B UART7_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- PUBWEAK SPI5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI5_IRQHandler
- B SPI5_IRQHandler
-
- PUBWEAK TLI_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TLI_IRQHandler
- B TLI_IRQHandler
-
- PUBWEAK TLI_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TLI_ER_IRQHandler
- B TLI_ER_IRQHandler
-
- PUBWEAK IPA_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-IPA_IRQHandler
- B IPA_IRQHandler
- END
\ No newline at end of file
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/cmsis.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/cmsis.h
deleted file mode 100644
index f3ba817..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/cmsis.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
-
- Copyright (c) 2018, GigaDevice Semiconductor Inc. All rights reserved.
-
- SPDX-License-Identifier: BSD-3-Clause
-
- Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-OF SUCH DAMAGE.
-*/
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "gd32f4xx.h"
-#include "cmsis_nvic.h"
-
-#endif /* MBED_CMSIS_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/cmsis_nvic.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/cmsis_nvic.h
deleted file mode 100644
index 1368242..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/cmsis_nvic.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2011 ARM Limited. All rights reserved.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of ARM Limited nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#define NVIC_NUM_VECTORS (16 + 91) /* ARM CORE:16 Vectors; MCU Peripherals:91 Vectors */
-#define NVIC_RAM_VECTOR_ADDRESS 0x20000000
-
-
-#endif /* MBED_CMSIS_NVIC_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/gd32f4xx.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/gd32f4xx.h
deleted file mode 100644
index a21ec31..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/gd32f4xx.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/*!
- \file gd32f4xx.h
- \brief general definitions for GD32E10x
-
- \version 2016-08-15, V1.0.0, firmware for GD32F4xx
- \version 2018-12-12, V2.0.0, firmware for GD32F4xx
- \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
-*/
-
-/*
- Copyright (c) 2018, GigaDevice Semiconductor Inc.
-
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F4XX_H
-#define GD32F4XX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* define GD32F4xx */
-#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
-/* #define GD32F450 */
-/* #define GD32F405 */
-/* #define GD32F407 */
-#endif /* define GD32F4xx */
-
-#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
-#error "Please select the target GD32F4xx device in gd32f4xx.h file"
-#endif /* undefine GD32F4xx tip */
-
-/* define value of high speed crystal oscillator (HXTAL) in Hz */
-#if !defined (HXTAL_VALUE)
-#define HXTAL_VALUE ((uint32_t)25000000)
-#endif /* high speed crystal oscillator value */
-
-/* define startup timeout value of high speed crystal oscillator (HXTAL) */
-#if !defined (HXTAL_STARTUP_TIMEOUT)
-#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
-#endif /* high speed crystal oscillator startup timeout */
-
-/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
-#if !defined (IRC16M_VALUE)
-#define IRC16M_VALUE ((uint32_t)16000000)
-#endif /* internal 16MHz RC oscillator value */
-
-/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
-#if !defined (IRC16M_STARTUP_TIMEOUT)
-#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
-#endif /* internal 16MHz RC oscillator startup timeout */
-
-/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
-#if !defined (IRC32K_VALUE)
-#define IRC32K_VALUE ((uint32_t)32000)
-#endif /* internal 32KHz RC oscillator value */
-
-/* define value of low speed crystal oscillator (LXTAL)in Hz */
-#if !defined (LXTAL_VALUE)
-#define LXTAL_VALUE ((uint32_t)32768)
-#endif /* low speed crystal oscillator value */
-
-/* I2S external clock in selection */
-//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
-
-/* GD32F4xx firmware library version number V1.0 */
-#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
-#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
- |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
- |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
- |(__GD32F4xx_STDPERIPH_VERSION_RC))
-
-/* configuration of the cortex-M4 processor and core peripherals */
-#define __CM4_REV 0x0001 /*!< core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */
-#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
-#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
-/* define interrupt number */
-typedef enum IRQn {
- /* cortex-M4 processor exceptions numbers */
- NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */
- BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */
- UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */
- SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */
- PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */
- SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */
- /* interruput numbers */
- WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
- LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
- TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */
- RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */
- FMC_IRQn = 4, /*!< FMC interrupt */
- RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
- EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
- EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
- EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
- EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
- EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
- DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */
- DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */
- DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
- DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
- DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
- DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
- DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
- ADC_IRQn = 18, /*!< ADC interrupt */
- CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
- CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
- CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
- CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
- EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
- TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
- TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
- TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
- TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
- TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
- TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
- TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
- I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
- I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
- I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
- I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
- SPI0_IRQn = 35, /*!< SPI0 interrupt */
- SPI1_IRQn = 36, /*!< SPI1 interrupt */
- USART0_IRQn = 37, /*!< USART0 interrupt */
- USART1_IRQn = 38, /*!< USART1 interrupt */
- USART2_IRQn = 39, /*!< USART2 interrupt */
- EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
- USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
- TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
- TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
- TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
- TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
- DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
-
-#if defined (GD32F450)
- EXMC_IRQn = 48, /*!< EXMC interrupt */
- SDIO_IRQn = 49, /*!< SDIO interrupt */
- TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
- SPI2_IRQn = 51, /*!< SPI2 interrupt */
- UART3_IRQn = 52, /*!< UART3 interrupt */
- UART4_IRQn = 53, /*!< UART4 interrupt */
- TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
- TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
- DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
- DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
- DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
- DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
- DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
- ENET_IRQn = 61, /*!< ENET interrupt */
- ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
- CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
- CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
- CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
- CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
- USBFS_IRQn = 67, /*!< USBFS interrupt */
- DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
- DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
- DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
- USART5_IRQn = 71, /*!< USART5 interrupt */
- I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
- I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
- USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
- USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
- USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
- USBHS_IRQn = 77, /*!< USBHS interrupt */
- DCI_IRQn = 78, /*!< DCI interrupt */
- TRNG_IRQn = 80, /*!< TRNG interrupt */
- FPU_IRQn = 81, /*!< FPU interrupt */
- UART6_IRQn = 82, /*!< UART6 interrupt */
- UART7_IRQn = 83, /*!< UART7 interrupt */
- SPI3_IRQn = 84, /*!< SPI3 interrupt */
- SPI4_IRQn = 85, /*!< SPI4 interrupt */
- SPI5_IRQn = 86, /*!< SPI5 interrupt */
- TLI_IRQn = 88, /*!< TLI interrupt */
- TLI_ER_IRQn = 89, /*!< TLI error interrupt */
- IPA_IRQn = 90, /*!< IPA interrupt */
-#endif /* GD32F450 */
-
-#if defined (GD32F405)
- SDIO_IRQn = 49, /*!< SDIO interrupt */
- TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
- SPI2_IRQn = 51, /*!< SPI2 interrupt */
- UART3_IRQn = 52, /*!< UART3 interrupt */
- UART4_IRQn = 53, /*!< UART4 interrupt */
- TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
- TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
- DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
- DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
- DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
- DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
- DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
- CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
- CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
- CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
- CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
- USBFS_IRQn = 67, /*!< USBFS interrupt */
- DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
- DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
- DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
- USART5_IRQn = 71, /*!< USART5 interrupt */
- I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
- I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
- USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */
- USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
- USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
- USBHS_IRQn = 77, /*!< USBHS interrupt */
- DCI_IRQn = 78, /*!< DCI interrupt */
- TRNG_IRQn = 80, /*!< TRNG interrupt */
- FPU_IRQn = 81, /*!< FPU interrupt */
-#endif /* GD32F405 */
-
-#if defined (GD32F407)
- EXMC_IRQn = 48, /*!< EXMC interrupt */
- SDIO_IRQn = 49, /*!< SDIO interrupt */
- TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
- SPI2_IRQn = 51, /*!< SPI2 interrupt */
- UART3_IRQn = 52, /*!< UART3 interrupt */
- UART4_IRQn = 53, /*!< UART4 interrupt */
- TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
- TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
- DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
- DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
- DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
- DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
- DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
- ENET_IRQn = 61, /*!< ENET interrupt */
- ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
- CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
- CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
- CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
- CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
- USBFS_IRQn = 67, /*!< USBFS interrupt */
- DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
- DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
- DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
- USART5_IRQn = 71, /*!< USART5 interrupt */
- I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
- I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
- USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
- USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
- USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
- USBHS_IRQn = 77, /*!< USBHS interrupt */
- DCI_IRQn = 78, /*!< DCI interrupt */
- TRNG_IRQn = 80, /*!< TRNG interrupt */
- FPU_IRQn = 81, /*!< FPU interrupt */
-#endif /* GD32F407 */
-
-} IRQn_Type;
-
-/* includes */
-#include "core_cm4.h"
-#include "system_gd32f4xx.h"
-#include
-
-#define GD_MBED_USED
-
-#ifdef GD_MBED_USED
-typedef enum {
- GD_OK = 0x00U,
- GD_ERROR = 0x01U,
- GD_BUSY = 0x02U,
- GD_TIMEOUT = 0x03U
-} gd_status_enum;
-
-typedef enum {
- OP_STATE_RESET = 0x00U,
- OP_STATE_READY = 0x01U,
- OP_STATE_BUSY = 0x02U,
- OP_STATE_TIMEOUT = 0x03U,
- OP_STATE_ERROR = 0x04U,
- OP_STATE_ABORT = 0x05U,
- OP_STATE_LISTEN = 0x06U,
-
- OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */
- OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */
-
- OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */
- OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */
-
- OP_STATE_BUTT
-} operation_state_enum;
-#endif
-
-/* enum definitions */
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
-typedef enum {RESET = 0, SET = !RESET} FlagStatus;
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
-
-/* bit operations */
-#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
-#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
-#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
-#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
-#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
-#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
-
-/* main flash and SRAM memory map */
-#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
-#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
-#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
-#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
-
-/* peripheral memory map */
-#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
-#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
-#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
-#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
-
-/* EXMC memory map */
-#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
-
-/* advanced peripheral bus 1 memory map */
-#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
-#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
-#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
-#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
-#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
-#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
-#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
-#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
-#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
-#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
-#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
-#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
-#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
-
-/* advanced peripheral bus 2 memory map */
-#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
-#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
-#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
-#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
-#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
-/* advanced high performance bus 1 memory map */
-#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
-#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
-#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
-#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
-#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
-#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
-#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
-#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
-#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
-
-/* advanced high performance bus 2 memory map */
-#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
-#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
-#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
-/* option byte and debug memory map */
-#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
-#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
-
-/* define marco USE_STDPERIPH_DRIVER */
-#if !defined USE_STDPERIPH_DRIVER
-#define USE_STDPERIPH_DRIVER
-#endif
-#ifdef USE_STDPERIPH_DRIVER
-#include "gd32f4xx_libopt.h"
-#endif /* USE_STDPERIPH_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif
-#endif
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/gd32f4xx_libopt.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/gd32f4xx_libopt.h
deleted file mode 100644
index cb8c81a..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/gd32f4xx_libopt.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*!
- \file gd32f4xx_libopt.h
- \brief library optional for gd32f4xx
-
- \version 2016-08-15, V1.0.0, firmware for GD32F4xx
- \version 2018-12-12, V2.0.0, firmware for GD32F4xx
- \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
-*/
-
-/*
- Copyright (c) 2018, GigaDevice Semiconductor Inc.
-
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors
- may be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-OF SUCH DAMAGE.
-*/
-
-#ifndef GD32F4XX_LIBOPT_H
-#define GD32F4XX_LIBOPT_H
-
-#if defined (GD32F450) || defined (GD32F405) || defined (GD32F407)
-#include "gd32f4xx_rcu.h"
-#include "gd32f4xx_adc.h"
-#include "gd32f4xx_can.h"
-#include "gd32f4xx_crc.h"
-#include "gd32f4xx_ctc.h"
-#include "gd32f4xx_dac.h"
-#include "gd32f4xx_dbg.h"
-#include "gd32f4xx_dci.h"
-#include "gd32f4xx_dma.h"
-#include "gd32f4xx_exti.h"
-#include "gd32f4xx_fmc.h"
-#include "gd32f4xx_fwdgt.h"
-#include "gd32f4xx_gpio.h"
-#include "gd32f4xx_syscfg.h"
-#include "gd32f4xx_i2c.h"
-#include "gd32f4xx_iref.h"
-#include "gd32f4xx_pmu.h"
-#include "gd32f4xx_rtc.h"
-#include "gd32f4xx_sdio.h"
-#include "gd32f4xx_spi.h"
-#include "gd32f4xx_timer.h"
-#include "gd32f4xx_trng.h"
-#include "gd32f4xx_usart.h"
-#include "gd32f4xx_wwdgt.h"
-#include "gd32f4xx_misc.h"
-#endif
-
-#if defined (GD32F450)
-#include "gd32f4xx_enet.h"
-#include "gd32f4xx_exmc.h"
-#include "gd32f4xx_ipa.h"
-#include "gd32f4xx_tli.h"
-#endif
-
-#if defined (GD32F407)
-#include "gd32f4xx_enet.h"
-#include "gd32f4xx_exmc.h"
-#endif
-
-#endif /* GD32F4XX_LIBOPT_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/hal_tick.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/hal_tick.h
deleted file mode 100644
index f7b3043..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/hal_tick.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2018 GigaDevice Semiconductor Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "gd32f4xx.h"
-#include "cmsis_nvic.h"
-
-#define TICKER_TIMER TIMER8
-#define TICKER_TIMER_IRQ TIMER0_BRK_TIMER8_IRQn
-#define TICKER_TIMER_RCU_CLOCK_ENABLE rcu_periph_clock_enable(RCU_TIMER8);
-#define TICKER_TIMER_DEBUG_STOP dbg_periph_enable(DBG_TIMER8_HOLD);
-
-#define TICKER_TIMER_RESET_ENABLE rcu_periph_reset_enable(RCU_TIMER8RST)
-#define TICKER_TIMER_RESET_DISABLE rcu_periph_reset_disable(RCU_TIMER8RST)
-
-/* 16 for 16-bit timer, 32 for 32-bit timer */
-#define TICKER_TIMER_WIDTH_BIT 16
-
-/* 0 for CK_APB1, 1 for CK_APB2 */
-#define TICKER_TIMER_CKAPB 1
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __HAL_TICK_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/system_gd32f4xx.c b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/system_gd32f4xx.c
deleted file mode 100644
index 9c9f60d..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/system_gd32f4xx.c
+++ /dev/null
@@ -1,916 +0,0 @@
-/*!
- \file system_gd32f4xx.c
- \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
- GD32F4xx Device Series
-*/
-
-/* Copyright (c) 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
-
-#include "gd32f4xx.h"
-
-/* system frequency define */
-#define __IRC16M (IRC16M_VALUE) /* internal 16 MHz RC oscillator frequency */
-#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
-#define __SYS_OSC_CLK (__IRC16M) /* main oscillator frequency */
-
-/* select a system clock by uncommenting the following line */
-//#define __SYSTEM_CLOCK_IRC16M (uint32_t)(__IRC16M)
-//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
-//#define __SYSTEM_CLOCK_120M_PLL_IRC16M (uint32_t)(120000000)
-//#define __SYSTEM_CLOCK_120M_PLL_8M_HXTAL (uint32_t)(120000000)
-//#define __SYSTEM_CLOCK_120M_PLL_25M_HXTAL (uint32_t)(120000000)
-//#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000)
-//#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000)
-//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000)
-//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000)
-//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000)
-#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000)
-
-#define SEL_IRC16M 0x00U
-#define SEL_HXTAL 0x01U
-#define SEL_PLLP 0x02U
-#define RCU_MODIFY {volatile uint32_t i; \
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
- for(i=0;i<50000;i++);}
-
-/* set the system clock frequency and declare the system clock configuration function */
-#ifdef __SYSTEM_CLOCK_IRC16M
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M;
-static void system_clock_16m_irc16m(void);
-#elif defined (__SYSTEM_CLOCK_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
-static void system_clock_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC16M;
-static void system_clock_120m_irc16m(void);
-#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_8M_HXTAL;
-static void system_clock_120m_8m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_25M_HXTAL;
-static void system_clock_120m_25m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_IRC16M;
-static void system_clock_168m_irc16m(void);
-#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_8M_HXTAL;
-static void system_clock_168m_8m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_25M_HXTAL;
-static void system_clock_168m_25m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_IRC16M;
-static void system_clock_200m_irc16m(void);
-#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_8M_HXTAL;
-static void system_clock_200m_8m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL;
-static void system_clock_200m_25m_hxtal(void);
-
-#endif /* __SYSTEM_CLOCK_IRC16M */
-
-/* configure the system clock */
-static void system_clock_config(void);
-
-/*!
- \brief setup the microcontroller system, initialize the system
- \param[in] none
- \param[out] none
- \retval none
-*/
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
-#endif
- /* Reset the RCU clock configuration to the default reset state ------------*/
- /* Set IRC16MEN bit */
- RCU_CTL |= RCU_CTL_IRC16MEN;
-
- RCU_MODIFY
-
- /* Reset CFG0 register */
- RCU_CFG0 = 0x00000000U;
-
- /* Reset HXTALEN, CKMEN and PLLEN bits */
- RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
-
- /* Reset PLLCFGR register */
- RCU_PLL = 0x24003010U;
-
- /* Reset HSEBYP bit */
- RCU_CTL &= ~(RCU_CTL_HXTALBPS);
-
- /* Disable all interrupts */
- RCU_INT = 0x00000000U;
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings ----------------------------------*/
- system_clock_config();
-}
-/*!
- \brief configure the system clock
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_config(void)
-{
-#ifdef __SYSTEM_CLOCK_IRC16M
- system_clock_16m_irc16m();
-#elif defined (__SYSTEM_CLOCK_HXTAL)
- system_clock_hxtal();
-#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
- system_clock_120m_irc16m();
-#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
- system_clock_120m_8m_hxtal();
-#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
- system_clock_120m_25m_hxtal();
-#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
- system_clock_168m_irc16m();
-#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
- system_clock_168m_8m_hxtal();
-#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
- system_clock_168m_25m_hxtal();
-#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
- system_clock_200m_irc16m();
-#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
- system_clock_200m_8m_hxtal();
-#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
- system_clock_200m_25m_hxtal();
-#endif /* __SYSTEM_CLOCK_IRC16M */
-}
-
-#ifdef __SYSTEM_CLOCK_IRC16M
-/*!
- \brief configure the system clock to 16M by IRC16M
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_16m_irc16m(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable IRC16M */
- RCU_CTL |= RCU_CTL_IRC16MEN;
-
- /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
- } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
- while (1) {
- }
- }
-
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
- /* APB1 = AHB */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-
- /* select IRC16M as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_IRC16M;
-
- /* wait until IRC16M is selected as system clock */
- while (0 != (RCU_CFG0 & RCU_SCSS_IRC16M)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_HXTAL)
-/*!
- \brief configure the system clock to HXTAL
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_hxtal(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable HXTAL */
- RCU_CTL |= RCU_CTL_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
- } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
- while (1) {
- }
- }
-
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
- /* APB1 = AHB */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
-
- /* select HXTAL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
-
- /* wait until HXTAL is selected as system clock */
- while (0 == (RCU_CFG0 & RCU_SCSS_HXTAL)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
-/*!
- \brief configure the system clock to 120M by PLL which selects IRC16M as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_120m_irc16m(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable IRC16M */
- RCU_CTL |= RCU_CTL_IRC16MEN;
-
- /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
- } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* IRC16M is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
- RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_IRC16M) | (5U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 120 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
-/*!
- \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_120m_8m_hxtal(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable HXTAL */
- RCU_CTL |= RCU_CTL_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
- } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
- RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_HXTAL) | (5U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 120 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
-/*!
- \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_120m_25m_hxtal(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable HXTAL */
- RCU_CTL |= RCU_CTL_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
- } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
- RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_HXTAL) | (5U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 120 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
-/*!
- \brief configure the system clock to 168M by PLL which selects IRC16M as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_168m_irc16m(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable IRC16M */
- RCU_CTL |= RCU_CTL_IRC16MEN;
-
- /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
- } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* IRC16M is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
- RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_IRC16M) | (7U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 168 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
-/*!
- \brief configure the system clock to 168M by PLL which selects HXTAL(8M) as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_168m_8m_hxtal(void)
-{
- uint32_t timeout = 0U;
-
- /* enable HXTAL */
- RCU_CTL |= RCU_CTL_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- while ((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)) {
- }
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
- RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_HXTAL) | (7 << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 168 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
-/*!
- \brief configure the system clock to 168M by PLL which selects HXTAL(25M) as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_168m_25m_hxtal(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable HXTAL */
- RCU_CTL |= RCU_CTL_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
- } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
- RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_HXTAL) | (7U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 168 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
-/*!
- \brief configure the system clock to 200M by PLL which selects IRC16M as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_200m_irc16m(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable IRC16M */
- RCU_CTL |= RCU_CTL_IRC16MEN;
-
- /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
- } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* IRC16M is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
- RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_IRC16M) | (9U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 200 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
-/*!
- \brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_200m_8m_hxtal(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable HXTAL */
- RCU_CTL |= RCU_CTL_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
- } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
- RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_HXTAL) | (9U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 200 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
-/*!
- \brief configure the system clock to 200M by PLL which selects HXTAL(25M) as its clock source
- \param[in] none
- \param[out] none
- \retval none
-*/
-static void system_clock_200m_25m_hxtal(void)
-{
- uint32_t timeout = 0U;
- uint32_t stab_flag = 0U;
-
- /* enable HXTAL */
- RCU_CTL |= RCU_CTL_HXTALEN;
-
- /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
- do {
- timeout++;
- stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
- } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
- /* if fail */
- if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
- while (1) {
- }
- }
-
- RCU_APB1EN |= RCU_APB1EN_PMUEN;
- PMU_CTL |= PMU_CTL_LDOVS;
-
- /* HXTAL is stable */
- /* AHB = SYSCLK */
- RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
- /* APB2 = AHB/2 */
- RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
- /* APB1 = AHB/4 */
- RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
-
- /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
- RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
- (RCU_PLLSRC_HXTAL) | (9U << 24U));
-
- /* enable PLL */
- RCU_CTL |= RCU_CTL_PLLEN;
-
- /* wait until PLL is stable */
- while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
- }
-
- /* Enable the high-drive to extend the clock frequency to 200 Mhz */
- PMU_CTL |= PMU_CTL_HDEN;
- while (0U == (PMU_CS & PMU_CS_HDRF)) {
- }
-
- /* select the high-drive mode */
- PMU_CTL |= PMU_CTL_HDS;
- while (0U == (PMU_CS & PMU_CS_HDSRF)) {
- }
-
- /* select PLL as system clock */
- RCU_CFG0 &= ~RCU_CFG0_SCS;
- RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
-
- /* wait until PLL is selected as system clock */
- while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
- }
-}
-
-#endif /* __SYSTEM_CLOCK_IRC16M */
-/*!
- \brief update the SystemCoreClock with current core clock retrieved from cpu registers
- \param[in] none
- \param[out] none
- \retval none
-*/
-void SystemCoreClockUpdate(void)
-{
- uint32_t sws;
- uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp;
-
- /* exponent of AHB, APB1 and APB2 clock divider */
- const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
- sws = GET_BITS(RCU_CFG0, 2, 3);
- switch (sws) {
- /* IRC16M is selected as CK_SYS */
- case SEL_IRC16M:
- SystemCoreClock = IRC16M_VALUE;
- break;
- /* HXTAL is selected as CK_SYS */
- case SEL_HXTAL:
- SystemCoreClock = HXTAL_VALUE;
- break;
- /* PLLP is selected as CK_SYS */
- case SEL_PLLP:
- /* get the value of PLLPSC[5:0] */
- pllpsc = GET_BITS(RCU_PLL, 0U, 5U);
- plln = GET_BITS(RCU_PLL, 6U, 14U);
- pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U;
- /* PLL clock source selection, HXTAL or IRC8M/2 */
- pllsel = (RCU_PLL & RCU_PLL_PLLSEL);
- if (RCU_PLLSRC_HXTAL == pllsel) {
- ck_src = HXTAL_VALUE;
- } else {
- ck_src = IRC16M_VALUE;
- }
- SystemCoreClock = ((ck_src / pllpsc) * plln) / pllp;
- break;
- /* IRC16M is selected as CK_SYS */
- default:
- SystemCoreClock = IRC16M_VALUE;
- break;
- }
- /* calculate AHB clock frequency */
- idx = GET_BITS(RCU_CFG0, 4, 7);
- clk_exp = ahb_exp[idx];
- SystemCoreClock = SystemCoreClock >> clk_exp;
-}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/system_gd32f4xx.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/system_gd32f4xx.h
deleted file mode 100644
index 0ecd532..0000000
--- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/TARGET_GD32F450ZI/device/system_gd32f4xx.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*!
- \file system_gd32f4xx.h
- \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
- GD32F4xx Device Series
-*/
-
-/* Copyright (c) 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
-
-#ifndef SYSTEM_GD32F4XX_H
-#define SYSTEM_GD32F4XX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-
-/* system clock frequency (core clock) */
-extern uint32_t SystemCoreClock;
-
-/* function declarations */
-/* initialize the system and update the SystemCoreClock variable */
-extern void SystemInit(void);
-/* update the SystemCoreClock with current core clock retrieved from cpu registers */
-extern void SystemCoreClockUpdate(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_GD32F4XX_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_MICRO/gd32f450zi.sct b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_MICRO/gd32f450zi.sct
new file mode 100644
index 0000000..03be629
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_MICRO/gd32f450zi.sct
@@ -0,0 +1,26 @@
+#! armcc -E
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *****
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (3*1024K)
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 107 vectors (16 core + 91 peripheral) * 4 bytes = 428 bytes to reserve (0x1B0, 8-byte aligned)
+ RW_IRAM1 (0x20000000+0x1B0) (0x20000-0x1B0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_MICRO/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_MICRO/startup_gd32f450.S
new file mode 100644
index 0000000..f111982
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_MICRO/startup_gd32f450.S
@@ -0,0 +1,458 @@
+;/*!
+; \file startup_gd32f450.S
+; \brief start up file
+;
+; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
+; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
+; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20020000
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
+ DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
+ DCD ADC_IRQHandler ; 34:ADC
+ DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
+ DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
+ DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
+ DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD SDIO_IRQHandler ; 65:SDIO
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
+ DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
+ DCD ENET_IRQHandler ; 77:Ethernet
+ DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
+ DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
+ DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
+ DCD USBFS_IRQHandler ; 83:USBFS
+ DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
+ DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
+ DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
+ DCD USART5_IRQHandler ; 87:USART5
+ DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
+ DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
+ DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
+ DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
+ DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
+ DCD USBHS_IRQHandler ; 93:USBHS
+ DCD DCI_IRQHandler ; 94:DCI
+ DCD 0 ; 95:Reserved
+ DCD TRNG_IRQHandler ; 96:TRNG
+ DCD FPU_IRQHandler ; 97:FPU
+ DCD UART6_IRQHandler ; 98:UART6
+ DCD UART7_IRQHandler ; 99:UART7
+ DCD SPI3_IRQHandler ; 100:SPI3
+ DCD SPI4_IRQHandler ; 101:SPI4
+ DCD SPI5_IRQHandler ; 102:SPI5
+ DCD 0 ; 103:Reserved
+ DCD TLI_IRQHandler ; 104:TLI
+ DCD TLI_ER_IRQHandler ; 105:TLI Error
+ DCD IPA_IRQHandler ; 106:IPA
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT TAMPER_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_CTC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel0_IRQHandler [WEAK]
+ EXPORT DMA0_Channel1_IRQHandler [WEAK]
+ EXPORT DMA0_Channel2_IRQHandler [WEAK]
+ EXPORT DMA0_Channel3_IRQHandler [WEAK]
+ EXPORT DMA0_Channel4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel5_IRQHandler [WEAK]
+ EXPORT DMA0_Channel6_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT CAN0_TX_IRQHandler [WEAK]
+ EXPORT CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_EWMC_IRQHandler [WEAK]
+ EXPORT EXTI5_9_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
+ EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
+ EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI10_15_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBFS_WKUP_IRQHandler [WEAK]
+ EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
+ EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
+ EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
+ EXPORT TIMER7_Channel_IRQHandler [WEAK]
+ EXPORT DMA0_Channel7_IRQHandler [WEAK]
+ EXPORT EXMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIMER4_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT TIMER5_DAC_IRQHandler [WEAK]
+ EXPORT TIMER6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel0_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT ENET_WKUP_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_EWMC_IRQHandler [WEAK]
+ EXPORT USBFS_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT USART5_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
+ EXPORT USBHS_EP1_In_IRQHandler [WEAK]
+ EXPORT USBHS_WKUP_IRQHandler [WEAK]
+ EXPORT USBHS_IRQHandler [WEAK]
+ EXPORT DCI_IRQHandler [WEAK]
+ EXPORT TRNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART6_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT TLI_IRQHandler [WEAK]
+ EXPORT TLI_ER_IRQHandler [WEAK]
+ EXPORT IPA_IRQHandler [WEAK]
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FMC_IRQHandler
+RCU_CTC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC_IRQHandler
+CAN0_TX_IRQHandler
+CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_TIMER8_IRQHandler
+TIMER0_UP_TIMER9_IRQHandler
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBFS_WKUP_IRQHandler
+TIMER7_BRK_TIMER11_IRQHandler
+TIMER7_UP_TIMER12_IRQHandler
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+TIMER7_Channel_IRQHandler
+DMA0_Channel7_IRQHandler
+EXMC_IRQHandler
+SDIO_IRQHandler
+TIMER4_IRQHandler
+SPI2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+TIMER5_DAC_IRQHandler
+TIMER6_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+ENET_IRQHandler
+ENET_WKUP_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_EWMC_IRQHandler
+USBFS_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+USART5_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+USBHS_EP1_Out_IRQHandler
+USBHS_EP1_In_IRQHandler
+USBHS_WKUP_IRQHandler
+USBHS_IRQHandler
+DCI_IRQHandler
+TRNG_IRQHandler
+FPU_IRQHandler
+UART6_IRQHandler
+UART7_IRQHandler
+SPI3_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+TLI_IRQHandler
+TLI_ER_IRQHandler
+IPA_IRQHandler
+
+ B .
+ ENDP
+
+ ALIGN
+
+; user Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_STD/gd32f450zi.sct b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_STD/gd32f450zi.sct
new file mode 100644
index 0000000..25d5e3e
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_STD/gd32f450zi.sct
@@ -0,0 +1,26 @@
+#! armcc -E
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *****
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 0x200000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (3*1024K)
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ ; 107 vectors (16 core + 91 peripheral) * 4 bytes = 428 bytes to reserve (0x1B0, 8-byte aligned)
+ RW_IRAM1 (0x20000000+0x1B0) (0x30000-0x1B0) { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_STD/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_STD/startup_gd32f450.S
new file mode 100644
index 0000000..b2a1683
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_ARM_STD/startup_gd32f450.S
@@ -0,0 +1,458 @@
+;/*!
+; \file startup_gd32f450.S
+; \brief start up file
+;
+; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
+; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
+; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000800
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20030000
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000400
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit EQU (__initial_sp - Stack_Size)
+
+ PRESERVE8
+ THUMB
+
+; /* reset Vector Mapped to at Address 0 */
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+; /* external interrupts handler */
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
+ DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
+ DCD ADC_IRQHandler ; 34:ADC
+ DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
+ DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
+ DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
+ DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD SDIO_IRQHandler ; 65:SDIO
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
+ DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
+ DCD ENET_IRQHandler ; 77:Ethernet
+ DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
+ DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
+ DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
+ DCD USBFS_IRQHandler ; 83:USBFS
+ DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
+ DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
+ DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
+ DCD USART5_IRQHandler ; 87:USART5
+ DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
+ DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
+ DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
+ DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
+ DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
+ DCD USBHS_IRQHandler ; 93:USBHS
+ DCD DCI_IRQHandler ; 94:DCI
+ DCD 0 ; 95:Reserved
+ DCD TRNG_IRQHandler ; 96:TRNG
+ DCD FPU_IRQHandler ; 97:FPU
+ DCD UART6_IRQHandler ; 98:UART6
+ DCD UART7_IRQHandler ; 99:UART7
+ DCD SPI3_IRQHandler ; 100:SPI3
+ DCD SPI4_IRQHandler ; 101:SPI4
+ DCD SPI5_IRQHandler ; 102:SPI5
+ DCD 0 ; 103:Reserved
+ DCD TLI_IRQHandler ; 104:TLI
+ DCD TLI_ER_IRQHandler ; 105:TLI Error
+ DCD IPA_IRQHandler ; 106:IPA
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+;/* reset Handler */
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+;/* dummy Exception Handlers */
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+; /* external interrupts handler */
+ EXPORT WWDGT_IRQHandler [WEAK]
+ EXPORT LVD_IRQHandler [WEAK]
+ EXPORT TAMPER_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT RCU_CTC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel0_IRQHandler [WEAK]
+ EXPORT DMA0_Channel1_IRQHandler [WEAK]
+ EXPORT DMA0_Channel2_IRQHandler [WEAK]
+ EXPORT DMA0_Channel3_IRQHandler [WEAK]
+ EXPORT DMA0_Channel4_IRQHandler [WEAK]
+ EXPORT DMA0_Channel5_IRQHandler [WEAK]
+ EXPORT DMA0_Channel6_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT CAN0_TX_IRQHandler [WEAK]
+ EXPORT CAN0_RX0_IRQHandler [WEAK]
+ EXPORT CAN0_RX1_IRQHandler [WEAK]
+ EXPORT CAN0_EWMC_IRQHandler [WEAK]
+ EXPORT EXTI5_9_IRQHandler [WEAK]
+ EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
+ EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
+ EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
+ EXPORT TIMER0_Channel_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT I2C0_EV_IRQHandler [WEAK]
+ EXPORT I2C0_ER_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART0_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI10_15_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT USBFS_WKUP_IRQHandler [WEAK]
+ EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
+ EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
+ EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
+ EXPORT TIMER7_Channel_IRQHandler [WEAK]
+ EXPORT DMA0_Channel7_IRQHandler [WEAK]
+ EXPORT EXMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIMER4_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT TIMER5_DAC_IRQHandler [WEAK]
+ EXPORT TIMER6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel0_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT ENET_WKUP_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_EWMC_IRQHandler [WEAK]
+ EXPORT USBFS_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT USART5_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
+ EXPORT USBHS_EP1_In_IRQHandler [WEAK]
+ EXPORT USBHS_WKUP_IRQHandler [WEAK]
+ EXPORT USBHS_IRQHandler [WEAK]
+ EXPORT DCI_IRQHandler [WEAK]
+ EXPORT TRNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART6_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT TLI_IRQHandler [WEAK]
+ EXPORT TLI_ER_IRQHandler [WEAK]
+ EXPORT IPA_IRQHandler [WEAK]
+
+;/* external interrupts handler */
+WWDGT_IRQHandler
+LVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FMC_IRQHandler
+RCU_CTC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA0_Channel0_IRQHandler
+DMA0_Channel1_IRQHandler
+DMA0_Channel2_IRQHandler
+DMA0_Channel3_IRQHandler
+DMA0_Channel4_IRQHandler
+DMA0_Channel5_IRQHandler
+DMA0_Channel6_IRQHandler
+ADC_IRQHandler
+CAN0_TX_IRQHandler
+CAN0_RX0_IRQHandler
+CAN0_RX1_IRQHandler
+CAN0_EWMC_IRQHandler
+EXTI5_9_IRQHandler
+TIMER0_BRK_TIMER8_IRQHandler
+TIMER0_UP_TIMER9_IRQHandler
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+TIMER0_Channel_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+I2C0_EV_IRQHandler
+I2C0_ER_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+USART0_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI10_15_IRQHandler
+RTC_Alarm_IRQHandler
+USBFS_WKUP_IRQHandler
+TIMER7_BRK_TIMER11_IRQHandler
+TIMER7_UP_TIMER12_IRQHandler
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+TIMER7_Channel_IRQHandler
+DMA0_Channel7_IRQHandler
+EXMC_IRQHandler
+SDIO_IRQHandler
+TIMER4_IRQHandler
+SPI2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+TIMER5_DAC_IRQHandler
+TIMER6_IRQHandler
+DMA1_Channel0_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+ENET_IRQHandler
+ENET_WKUP_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_EWMC_IRQHandler
+USBFS_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+USART5_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+USBHS_EP1_Out_IRQHandler
+USBHS_EP1_In_IRQHandler
+USBHS_WKUP_IRQHandler
+USBHS_IRQHandler
+DCI_IRQHandler
+TRNG_IRQHandler
+FPU_IRQHandler
+UART6_IRQHandler
+UART7_IRQHandler
+SPI3_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+TLI_IRQHandler
+TLI_ER_IRQHandler
+IPA_IRQHandler
+
+ B .
+ ENDP
+
+ ALIGN
+
+; user Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_GCC_ARM/GD32F450xI.ld b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_GCC_ARM/GD32F450xI.ld
new file mode 100644
index 0000000..65b9f67
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_GCC_ARM/GD32F450xI.ld
@@ -0,0 +1,131 @@
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE 2048k
+#endif
+
+/* specify memory regions */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ RAM (rwx) : ORIGIN = 0x200001B0, LENGTH = 192K - 0x1B0
+ TCMSRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+}
+
+/* define output sections */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* initializes stack on the end of block */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_GCC_ARM/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_GCC_ARM/startup_gd32f450.S
new file mode 100644
index 0000000..d8ca9e6
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_GCC_ARM/startup_gd32f450.S
@@ -0,0 +1,518 @@
+;/*!
+; \file startup_gd32f450.S
+; \brief start up file
+;
+; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
+; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
+; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global VecTab
+.global Default_Handler
+
+/* start address of the initialization .data */
+.word _sidata
+/* start address of the .data section */
+.word _sdata
+/* end address of the .data section */
+.word _edata
+/* start address of the .bss section */
+.word _sbss
+/* end address of the .bss section */
+.word _ebss
+
+/* reset Handler */
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ mov sp, r0 /* set stack pointer */
+
+/* copy the data segment into RAM */
+ movs r1, #0
+ b DataInit
+
+CopyData:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+DataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyData
+ ldr r2, =_sbss
+ ldr r3, =_ebss
+ cmp r2, r3
+ bcc ZeroFill
+
+ZeroFill:
+ movs r3, #0
+ str r3, [r2], #4
+
+/* system clock intitialization*/
+ bl SystemInit
+/* static constructors */
+// bl __libc_init_array
+/* jump to application's entry point */
+// bl main
+ bl _start
+
+ bx lr
+
+
+.size Reset_Handler, .-Reset_Handler
+
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+/* infinite loop */
+ b .
+ .size Default_Handler, .-Default_Handler
+
+ .section .isr_vector,"a",%progbits
+ .type VecTab, %object
+ .size VecTab, .-VecTab
+
+VecTab:
+ .word _estack /* Top of Stack */
+ .word Reset_Handler /* Reset Handler */
+ .word NMI_Handler /* NMI Handler */
+ .word HardFault_Handler /* Hard Fault Handler */
+ .word MemManage_Handler /* MPU Fault Handler */
+ .word BusFault_Handler /* Bus Fault Handler */
+ .word UsageFault_Handler /* Usage Fault Handler */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SVC_Handler /* SVCall Handler */
+ .word DebugMon_Handler /* Debug Monitor Handler */
+ .word 0 /* Reserved */
+ .word PendSV_Handler /* PendSV Handler */
+ .word SysTick_Handler /* SysTick Handler */
+
+ /* external interrupts handler */
+ .word WWDGT_IRQHandler /* 16:Window Watchdog Timer */
+ .word LVD_IRQHandler /* 17:LVD through EXTI Line detect */
+ .word TAMPER_STAMP_IRQHandler /* 18:Tamper and TimeStamp through EXTI Line detect */
+ .word RTC_WKUP_IRQHandler /* 19:RTC Wakeup through EXTI Line */
+ .word FMC_IRQHandler /* 20:FMC */
+ .word RCU_CTC_IRQHandler /* 21:RCU and CTC */
+ .word EXTI0_IRQHandler /* 22:EXTI Line 0 */
+ .word EXTI1_IRQHandler /* 23:EXTI Line 1 */
+ .word EXTI2_IRQHandler /* 24:EXTI Line 2 */
+ .word EXTI3_IRQHandler /* 25:EXTI Line 3 */
+ .word EXTI4_IRQHandler /* 26:EXTI Line 4 */
+ .word DMA0_Channel0_IRQHandler /* 27:DMA0 Channel0 */
+ .word DMA0_Channel1_IRQHandler /* 28:DMA0 Channel1 */
+ .word DMA0_Channel2_IRQHandler /* 29:DMA0 Channel2 */
+ .word DMA0_Channel3_IRQHandler /* 30:DMA0 Channel3 */
+ .word DMA0_Channel4_IRQHandler /* 31:DMA0 Channel4 */
+ .word DMA0_Channel5_IRQHandler /* 32:DMA0 Channel5 */
+ .word DMA0_Channel6_IRQHandler /* 33:DMA0 Channel6 */
+ .word ADC_IRQHandler /* 34:ADC */
+ .word CAN0_TX_IRQHandler /* 35:CAN0 TX */
+ .word CAN0_RX0_IRQHandler /* 36:CAN0 RX0 */
+ .word CAN0_RX1_IRQHandler /* 37:CAN0 RX1 */
+ .word CAN0_EWMC_IRQHandler /* 38:CAN0 EWMC */
+ .word EXTI5_9_IRQHandler /* 39:EXTI5 to EXTI9 */
+ .word TIMER0_BRK_TIMER8_IRQHandler /* 40:TIMER0 Break and TIMER8 */
+ .word TIMER0_UP_TIMER9_IRQHandler /* 41:TIMER0 Update and TIMER9 */
+ .word TIMER0_TRG_CMT_TIMER10_IRQHandler /* 42:TIMER0 Trigger and Commutation and TIMER10 */
+ .word TIMER0_Channel_IRQHandler /* 43:TIMER0 Capture Compare */
+ .word TIMER1_IRQHandler /* 44:TIMER1 */
+ .word TIMER2_IRQHandler /* 45:TIMER2 */
+ .word TIMER3_IRQHandler /* 46:TIMER3 */
+ .word I2C0_EV_IRQHandler /* 47:I2C0 Event */
+ .word I2C0_ER_IRQHandler /* 48:I2C0 Error */
+ .word I2C1_EV_IRQHandler /* 49:I2C1 Event */
+ .word I2C1_ER_IRQHandler /* 50:I2C1 Error */
+ .word SPI0_IRQHandler /* 51:SPI0 */
+ .word SPI1_IRQHandler /* 52:SPI1 */
+ .word USART0_IRQHandler /* 53:USART0 */
+ .word USART1_IRQHandler /* 54:USART1 */
+ .word USART2_IRQHandler /* 55:USART2 */
+ .word EXTI10_15_IRQHandler /* 56:EXTI10 to EXTI15 */
+ .word RTC_Alarm_IRQHandler /* 57:RTC Alarm */
+ .word USBFS_WKUP_IRQHandler /* 58:USBFS Wakeup */
+ .word TIMER7_BRK_TIMER11_IRQHandler /* 59:TIMER7 Break and TIMER11 */
+ .word TIMER7_UP_TIMER12_IRQHandler /* 60:TIMER7 Update and TIMER12 */
+ .word TIMER7_TRG_CMT_TIMER13_IRQHandler /* 61:TIMER7 Trigger and Commutation and TIMER13 */
+ .word TIMER7_Channel_IRQHandler /* 62:TIMER7 Channel Capture Compare */
+ .word DMA0_Channel7_IRQHandler /* 63:DMA0 Channel7 */
+ .word EXMC_IRQHandler /* 64:EXMC */
+ .word SDIO_IRQHandler /* 65:SDIO */
+ .word TIMER4_IRQHandler /* 66:TIMER4 */
+ .word SPI2_IRQHandler /* 67:SPI2 */
+ .word UART3_IRQHandler /* 68:UART3 */
+ .word UART4_IRQHandler /* 69:UART4 */
+ .word TIMER5_DAC_IRQHandler /* 70:TIMER5 and DAC0 DAC1 Underrun error */
+ .word TIMER6_IRQHandler /* 71:TIMER6 */
+ .word DMA1_Channel0_IRQHandler /* 72:DMA1 Channel0 */
+ .word DMA1_Channel1_IRQHandler /* 73:DMA1 Channel1 */
+ .word DMA1_Channel2_IRQHandler /* 74:DMA1 Channel2 */
+ .word DMA1_Channel3_IRQHandler /* 75:DMA1 Channel3 */
+ .word DMA1_Channel4_IRQHandler /* 76:DMA1 Channel4 */
+ .word ENET_IRQHandler /* 77:Ethernet */
+ .word ENET_WKUP_IRQHandler /* 78:Ethernet Wakeup through EXTI Line */
+ .word CAN1_TX_IRQHandler /* 79:CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* 80:CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* 81:CAN1 RX1 */
+ .word CAN1_EWMC_IRQHandler /* 82:CAN1 EWMC */
+ .word USBFS_IRQHandler /* 83:USBFS */
+ .word DMA1_Channel5_IRQHandler /* 84:DMA1 Channel5 */
+ .word DMA1_Channel6_IRQHandler /* 85:DMA1 Channel6 */
+ .word DMA1_Channel7_IRQHandler /* 86:DMA1 Channel7 */
+ .word USART5_IRQHandler /* 87:USART5 */
+ .word I2C2_EV_IRQHandler /* 88:I2C2 Event */
+ .word I2C2_ER_IRQHandler /* 89:I2C2 Error */
+ .word USBHS_EP1_Out_IRQHandler /* 90:USBHS Endpoint 1 Out */
+ .word USBHS_EP1_In_IRQHandler /* 91:USBHS Endpoint 1 in */
+ .word USBHS_WKUP_IRQHandler /* 92:USBHS Wakeup through EXTI Line */
+ .word USBHS_IRQHandler /* 93:USBHS */
+ .word DCI_IRQHandler /* 94:DCI */
+ .word 0 /* 95:Reserved */
+ .word TRNG_IRQHandler /* 96:TRNG */
+ .word FPU_IRQHandler /* 97:FPU */
+ .word UART6_IRQHandler /* 98:UART6 */
+ .word UART7_IRQHandler /* 99:UART7 */
+ .word SPI3_IRQHandler /* 100:SPI3 */
+ .word SPI4_IRQHandler /* 101:SPI4 */
+ .word SPI5_IRQHandler /* 102:SPI5 */
+ .word 0 /* 103:Reserved */
+ .word TLI_IRQHandler /* 104:TLI */
+ .word TLI_ER_IRQHandler /* 105:TLI Error */
+ .word IPA_IRQHandler /* 106:IPA */
+
+/* dummy Exception Handlers */
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDGT_IRQHandler
+ .thumb_set WWDGT_IRQHandler,Default_Handler
+
+ .weak LVD_IRQHandler
+ .thumb_set LVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_STAMP_IRQHandler
+ .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak RCU_CTC_IRQHandler
+ .thumb_set RCU_CTC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel0_IRQHandler
+ .thumb_set DMA0_Channel0_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel1_IRQHandler
+ .thumb_set DMA0_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel2_IRQHandler
+ .thumb_set DMA0_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel3_IRQHandler
+ .thumb_set DMA0_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel4_IRQHandler
+ .thumb_set DMA0_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel5_IRQHandler
+ .thumb_set DMA0_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel6_IRQHandler
+ .thumb_set DMA0_Channel6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak CAN0_TX_IRQHandler
+ .thumb_set CAN0_TX_IRQHandler,Default_Handler
+
+ .weak CAN0_RX0_IRQHandler
+ .thumb_set CAN0_RX0_IRQHandler,Default_Handler
+
+ .weak CAN0_RX1_IRQHandler
+ .thumb_set CAN0_RX1_IRQHandler,Default_Handler
+
+ .weak CAN0_EWMC_IRQHandler
+ .thumb_set CAN0_EWMC_IRQHandler,Default_Handler
+
+ .weak EXTI5_9_IRQHandler
+ .thumb_set EXTI5_9_IRQHandler,Default_Handler
+
+ .weak TIMER0_BRK_TIMER8_IRQHandler
+ .thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
+
+ .weak TIMER0_UP_TIMER9_IRQHandler
+ .thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
+
+ .weak TIMER0_TRG_CMT_TIMER10_IRQHandler
+ .thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
+
+ .weak TIMER0_Channel_IRQHandler
+ .thumb_set TIMER0_Channel_IRQHandler,Default_Handler
+
+ .weak TIMER1_IRQHandler
+ .thumb_set TIMER1_IRQHandler,Default_Handler
+
+ .weak TIMER2_IRQHandler
+ .thumb_set TIMER2_IRQHandler,Default_Handler
+
+ .weak TIMER3_IRQHandler
+ .thumb_set TIMER3_IRQHandler,Default_Handler
+
+ .weak I2C0_EV_IRQHandler
+ .thumb_set I2C0_EV_IRQHandler,Default_Handler
+
+ .weak I2C0_ER_IRQHandler
+ .thumb_set I2C0_ER_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI0_IRQHandler
+ .thumb_set SPI0_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART0_IRQHandler
+ .thumb_set USART0_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI10_15_IRQHandler
+ .thumb_set EXTI10_15_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak USBFS_WKUP_IRQHandler
+ .thumb_set USBFS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIMER7_BRK_TIMER11_IRQHandler
+ .thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
+
+ .weak TIMER7_UP_TIMER12_IRQHandler
+ .thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
+
+ .weak TIMER7_TRG_CMT_TIMER13_IRQHandler
+ .thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
+
+ .weak TIMER7_Channel_IRQHandler
+ .thumb_set TIMER7_Channel_IRQHandler,Default_Handler
+
+ .weak DMA0_Channel7_IRQHandler
+ .thumb_set DMA0_Channel7_IRQHandler,Default_Handler
+
+ .weak EXMC_IRQHandler
+ .thumb_set EXMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIMER4_IRQHandler
+ .thumb_set TIMER4_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak UART3_IRQHandler
+ .thumb_set UART3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak TIMER5_DAC_IRQHandler
+ .thumb_set TIMER5_DAC_IRQHandler,Default_Handler
+
+ .weak TIMER6_IRQHandler
+ .thumb_set TIMER6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel0_IRQHandler
+ .thumb_set DMA1_Channel0_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak ENET_IRQHandler
+ .thumb_set ENET_IRQHandler,Default_Handler
+
+ .weak ENET_WKUP_IRQHandler
+ .thumb_set ENET_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_EWMC_IRQHandler
+ .thumb_set CAN1_EWMC_IRQHandler,Default_Handler
+
+ .weak USBFS_IRQHandler
+ .thumb_set USBFS_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak USART5_IRQHandler
+ .thumb_set USART5_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak USBHS_EP1_Out_IRQHandler
+ .thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
+
+ .weak USBHS_EP1_In_IRQHandler
+ .thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
+
+ .weak USBHS_WKUP_IRQHandler
+ .thumb_set USBHS_WKUP_IRQHandler,Default_Handler
+
+ .weak USBHS_IRQHandler
+ .thumb_set USBHS_IRQHandler,Default_Handler
+
+ .weak DCI_IRQHandler
+ .thumb_set DCI_IRQHandler,Default_Handler
+
+ .weak TRNG_IRQHandler
+ .thumb_set TRNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART6_IRQHandler
+ .thumb_set UART6_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak TLI_IRQHandler
+ .thumb_set TLI_IRQHandler,Default_Handler
+
+ .weak TLI_ER_IRQHandler
+ .thumb_set TLI_ER_IRQHandler,Default_Handler
+
+ .weak IPA_IRQHandler
+ .thumb_set IPA_IRQHandler,Default_Handler
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_IAR/gd32f450zi.icf b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_IAR/gd32f450zi.icf
new file mode 100644
index 0000000..8f649ad
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_IAR/gd32f450zi.icf
@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; }
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_TCMSRAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_TCMSRAM_end__ = 0x1000FFFF;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x200001AF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x200001B0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x10000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region TCMSRAM_region = mem:[from __ICFEDIT_region_TCMSRAM_start__ to __ICFEDIT_region_TCMSRAM_end__];
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_IAR/startup_gd32f450.S b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_IAR/startup_gd32f450.S
new file mode 100644
index 0000000..a8a317c
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/TOOLCHAIN_IAR/startup_gd32f450.S
@@ -0,0 +1,667 @@
+;/*!
+; \file startup_gd32f450.S
+; \brief start up file
+;
+; \version 2016-08-15, V1.0.0, firmware for GD32F4xx
+; \version 2018-12-12, V2.0.0, firmware for GD32F4xx
+; \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
+;*/
+;
+;/*
+; Copyright (c) 2018, GigaDevice Semiconductor Inc.
+;
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without modification,
+;are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice, this
+; list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+; this list of conditions and the following disclaimer in the documentation
+; and/or other materials provided with the distribution.
+; 3. Neither the name of the copyright holder nor the names of its contributors
+; may be used to endorse or promote products derived from this software without
+; specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+;OF SUCH DAMAGE.
+;*/
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; top of stack
+ DCD Reset_Handler ; Vector Number 1,Reset Handler
+
+ DCD NMI_Handler ; Vector Number 2,NMI Handler
+ DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
+ DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
+ DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
+ DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; Vector Number 11,SVCall Handler
+ DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; Vector Number 14,PendSV Handler
+ DCD SysTick_Handler ; Vector Number 15,SysTick Handler
+
+ ; External Interrupts
+ DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
+ DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
+ DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
+ DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
+ DCD FMC_IRQHandler ; 20:FMC
+ DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
+ DCD EXTI0_IRQHandler ; 22:EXTI Line 0
+ DCD EXTI1_IRQHandler ; 23:EXTI Line 1
+ DCD EXTI2_IRQHandler ; 24:EXTI Line 2
+ DCD EXTI3_IRQHandler ; 25:EXTI Line 3
+ DCD EXTI4_IRQHandler ; 26:EXTI Line 4
+ DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
+ DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
+ DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
+ DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
+ DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
+ DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
+ DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
+ DCD ADC_IRQHandler ; 34:ADC
+ DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
+ DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
+ DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
+ DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
+ DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
+ DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
+ DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
+ DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
+ DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
+ DCD TIMER1_IRQHandler ; 44:TIMER1
+ DCD TIMER2_IRQHandler ; 45:TIMER2
+ DCD TIMER3_IRQHandler ; 46:TIMER3
+ DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
+ DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
+ DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
+ DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
+ DCD SPI0_IRQHandler ; 51:SPI0
+ DCD SPI1_IRQHandler ; 52:SPI1
+ DCD USART0_IRQHandler ; 53:USART0
+ DCD USART1_IRQHandler ; 54:USART1
+ DCD USART2_IRQHandler ; 55:USART2
+ DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
+ DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
+ DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
+ DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
+ DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
+ DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
+ DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
+ DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
+ DCD EXMC_IRQHandler ; 64:EXMC
+ DCD SDIO_IRQHandler ; 65:SDIO
+ DCD TIMER4_IRQHandler ; 66:TIMER4
+ DCD SPI2_IRQHandler ; 67:SPI2
+ DCD UART3_IRQHandler ; 68:UART3
+ DCD UART4_IRQHandler ; 69:UART4
+ DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
+ DCD TIMER6_IRQHandler ; 71:TIMER6
+ DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
+ DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
+ DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
+ DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
+ DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
+ DCD ENET_IRQHandler ; 77:Ethernet
+ DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
+ DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
+ DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
+ DCD USBFS_IRQHandler ; 83:USBFS
+ DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
+ DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
+ DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
+ DCD USART5_IRQHandler ; 87:USART5
+ DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
+ DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
+ DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
+ DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
+ DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
+ DCD USBHS_IRQHandler ; 93:USBHS
+ DCD DCI_IRQHandler ; 94:DCI
+ DCD 0 ; 95:Reserved
+ DCD TRNG_IRQHandler ; 96:TRNG
+ DCD FPU_IRQHandler ; 97:FPU
+ DCD UART6_IRQHandler ; 98:UART6
+ DCD UART7_IRQHandler ; 99:UART7
+ DCD SPI3_IRQHandler ; 100:SPI3
+ DCD SPI4_IRQHandler ; 101:SPI4
+ DCD SPI5_IRQHandler ; 102:SPI5
+ DCD 0 ; 103:Reserved
+ DCD TLI_IRQHandler ; 104:TLI
+ DCD TLI_ER_IRQHandler ; 105:TLI Error
+ DCD IPA_IRQHandler ; 106:IPA
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDGT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDGT_IRQHandler
+ B WWDGT_IRQHandler
+
+ PUBWEAK LVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_IRQHandler
+ B LVD_IRQHandler
+
+ PUBWEAK TAMPER_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_STAMP_IRQHandler
+ B TAMPER_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK RCU_CTC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCU_CTC_IRQHandler
+ B RCU_CTC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA0_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel0_IRQHandler
+ B DMA0_Channel0_IRQHandler
+
+ PUBWEAK DMA0_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel1_IRQHandler
+ B DMA0_Channel1_IRQHandler
+
+ PUBWEAK DMA0_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel2_IRQHandler
+ B DMA0_Channel2_IRQHandler
+
+ PUBWEAK DMA0_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel3_IRQHandler
+ B DMA0_Channel3_IRQHandler
+
+ PUBWEAK DMA0_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel4_IRQHandler
+ B DMA0_Channel4_IRQHandler
+
+ PUBWEAK DMA0_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel5_IRQHandler
+ B DMA0_Channel5_IRQHandler
+
+ PUBWEAK DMA0_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel6_IRQHandler
+ B DMA0_Channel6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK CAN0_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_TX_IRQHandler
+ B CAN0_TX_IRQHandler
+
+ PUBWEAK CAN0_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX0_IRQHandler
+ B CAN0_RX0_IRQHandler
+
+ PUBWEAK CAN0_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_IRQHandler
+ B CAN0_RX1_IRQHandler
+
+ PUBWEAK CAN0_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EWMC_IRQHandler
+ B CAN0_EWMC_IRQHandler
+
+ PUBWEAK EXTI5_9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_9_IRQHandler
+ B EXTI5_9_IRQHandler
+
+ PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_BRK_TIMER8_IRQHandler
+ B TIMER0_BRK_TIMER8_IRQHandler
+
+ PUBWEAK TIMER0_UP_TIMER9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_UP_TIMER9_IRQHandler
+ B TIMER0_UP_TIMER9_IRQHandler
+
+ PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_TRG_CMT_TIMER10_IRQHandler
+ B TIMER0_TRG_CMT_TIMER10_IRQHandler
+
+ PUBWEAK TIMER0_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER0_Channel_IRQHandler
+ B TIMER0_Channel_IRQHandler
+
+ PUBWEAK TIMER1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER1_IRQHandler
+ B TIMER1_IRQHandler
+
+ PUBWEAK TIMER2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER2_IRQHandler
+ B TIMER2_IRQHandler
+
+ PUBWEAK TIMER3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER3_IRQHandler
+ B TIMER3_IRQHandler
+
+ PUBWEAK I2C0_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_IRQHandler
+ B I2C0_EV_IRQHandler
+
+ PUBWEAK I2C0_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ER_IRQHandler
+ B I2C0_ER_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_IRQHandler
+ B SPI0_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_IRQHandler
+ B USART0_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI10_15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_15_IRQHandler
+ B EXTI10_15_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK USBFS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_WKUP_IRQHandler
+ B USBFS_WKUP_IRQHandler
+
+ PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_BRK_TIMER11_IRQHandler
+ B TIMER7_BRK_TIMER11_IRQHandler
+
+ PUBWEAK TIMER7_UP_TIMER12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_UP_TIMER12_IRQHandler
+ B TIMER7_UP_TIMER12_IRQHandler
+
+ PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_TRG_CMT_TIMER13_IRQHandler
+ B TIMER7_TRG_CMT_TIMER13_IRQHandler
+
+ PUBWEAK TIMER7_Channel_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER7_Channel_IRQHandler
+ B TIMER7_Channel_IRQHandler
+
+ PUBWEAK DMA0_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA0_Channel7_IRQHandler
+ B DMA0_Channel7_IRQHandler
+
+ PUBWEAK EXMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXMC_IRQHandler
+ B EXMC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIMER4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER4_IRQHandler
+ B TIMER4_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK TIMER5_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER5_DAC_IRQHandler
+ B TIMER5_DAC_IRQHandler
+
+ PUBWEAK TIMER6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIMER6_IRQHandler
+ B TIMER6_IRQHandler
+
+ PUBWEAK DMA1_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel0_IRQHandler
+ B DMA1_Channel0_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK ENET_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ENET_WKUP_IRQHandler
+ B ENET_WKUP_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_EWMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_EWMC_IRQHandler
+ B CAN1_EWMC_IRQHandler
+
+ PUBWEAK USBFS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBFS_IRQHandler
+ B USBFS_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK USART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART5_IRQHandler
+ B USART5_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK USBHS_EP1_Out_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBHS_EP1_Out_IRQHandler
+ B USBHS_EP1_Out_IRQHandler
+
+ PUBWEAK USBHS_EP1_In_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBHS_EP1_In_IRQHandler
+ B USBHS_EP1_In_IRQHandler
+
+ PUBWEAK USBHS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBHS_WKUP_IRQHandler
+ B USBHS_WKUP_IRQHandler
+
+ PUBWEAK USBHS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USBHS_IRQHandler
+ B USBHS_IRQHandler
+
+ PUBWEAK DCI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCI_IRQHandler
+ B DCI_IRQHandler
+
+ PUBWEAK TRNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TRNG_IRQHandler
+ B TRNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART6_IRQHandler
+ B UART6_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK TLI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TLI_IRQHandler
+ B TLI_IRQHandler
+
+ PUBWEAK TLI_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TLI_ER_IRQHandler
+ B TLI_ER_IRQHandler
+
+ PUBWEAK IPA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+IPA_IRQHandler
+ B IPA_IRQHandler
+ END
\ No newline at end of file
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/cmsis.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/cmsis.h
new file mode 100644
index 0000000..f3ba817
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+
+ Copyright (c) 2018, GigaDevice Semiconductor Inc. All rights reserved.
+
+ SPDX-License-Identifier: BSD-3-Clause
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "gd32f4xx.h"
+#include "cmsis_nvic.h"
+
+#endif /* MBED_CMSIS_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/cmsis_nvic.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/cmsis_nvic.h
new file mode 100644
index 0000000..1368242
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/cmsis_nvic.h
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 91) /* ARM CORE:16 Vectors; MCU Peripherals:91 Vectors */
+#define NVIC_RAM_VECTOR_ADDRESS 0x20000000
+
+
+#endif /* MBED_CMSIS_NVIC_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/gd32f4xx.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/gd32f4xx.h
new file mode 100644
index 0000000..a21ec31
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/gd32f4xx.h
@@ -0,0 +1,395 @@
+/*!
+ \file gd32f4xx.h
+ \brief general definitions for GD32E10x
+
+ \version 2016-08-15, V1.0.0, firmware for GD32F4xx
+ \version 2018-12-12, V2.0.0, firmware for GD32F4xx
+ \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
+*/
+
+/*
+ Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F4XX_H
+#define GD32F4XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* define GD32F4xx */
+#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
+/* #define GD32F450 */
+/* #define GD32F405 */
+/* #define GD32F407 */
+#endif /* define GD32F4xx */
+
+#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407)
+#error "Please select the target GD32F4xx device in gd32f4xx.h file"
+#endif /* undefine GD32F4xx tip */
+
+/* define value of high speed crystal oscillator (HXTAL) in Hz */
+#if !defined (HXTAL_VALUE)
+#define HXTAL_VALUE ((uint32_t)25000000)
+#endif /* high speed crystal oscillator value */
+
+/* define startup timeout value of high speed crystal oscillator (HXTAL) */
+#if !defined (HXTAL_STARTUP_TIMEOUT)
+#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
+#endif /* high speed crystal oscillator startup timeout */
+
+/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
+#if !defined (IRC16M_VALUE)
+#define IRC16M_VALUE ((uint32_t)16000000)
+#endif /* internal 16MHz RC oscillator value */
+
+/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
+#if !defined (IRC16M_STARTUP_TIMEOUT)
+#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
+#endif /* internal 16MHz RC oscillator startup timeout */
+
+/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
+#if !defined (IRC32K_VALUE)
+#define IRC32K_VALUE ((uint32_t)32000)
+#endif /* internal 32KHz RC oscillator value */
+
+/* define value of low speed crystal oscillator (LXTAL)in Hz */
+#if !defined (LXTAL_VALUE)
+#define LXTAL_VALUE ((uint32_t)32768)
+#endif /* low speed crystal oscillator value */
+
+/* I2S external clock in selection */
+//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
+
+/* GD32F4xx firmware library version number V1.0 */
+#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
+#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
+#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
+ |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__GD32F4xx_STDPERIPH_VERSION_RC))
+
+/* configuration of the cortex-M4 processor and core peripherals */
+#define __CM4_REV 0x0001 /*!< core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */
+#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
+#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+/* define interrupt number */
+typedef enum IRQn {
+ /* cortex-M4 processor exceptions numbers */
+ NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */
+ BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */
+ UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */
+ SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */
+ PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */
+ SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */
+ /* interruput numbers */
+ WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
+ LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */
+ RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */
+ FMC_IRQn = 4, /*!< FMC interrupt */
+ RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
+ EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
+ EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
+ EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
+ EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
+ DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */
+ DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */
+ DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
+ DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
+ DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
+ DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
+ DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
+ ADC_IRQn = 18, /*!< ADC interrupt */
+ CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
+ CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
+ CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
+ CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
+ EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
+ TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
+ TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
+ TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
+ TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
+ TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
+ TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
+ TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
+ I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
+ I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
+ I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
+ I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
+ SPI0_IRQn = 35, /*!< SPI0 interrupt */
+ SPI1_IRQn = 36, /*!< SPI1 interrupt */
+ USART0_IRQn = 37, /*!< USART0 interrupt */
+ USART1_IRQn = 38, /*!< USART1 interrupt */
+ USART2_IRQn = 39, /*!< USART2 interrupt */
+ EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
+ USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
+ TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
+ TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
+ TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
+ TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
+ DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
+
+#if defined (GD32F450)
+ EXMC_IRQn = 48, /*!< EXMC interrupt */
+ SDIO_IRQn = 49, /*!< SDIO interrupt */
+ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
+ SPI2_IRQn = 51, /*!< SPI2 interrupt */
+ UART3_IRQn = 52, /*!< UART3 interrupt */
+ UART4_IRQn = 53, /*!< UART4 interrupt */
+ TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
+ TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
+ DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
+ DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
+ DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
+ DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
+ DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
+ ENET_IRQn = 61, /*!< ENET interrupt */
+ ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
+ CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
+ CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
+ CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
+ CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
+ USBFS_IRQn = 67, /*!< USBFS interrupt */
+ DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
+ DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
+ DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
+ USART5_IRQn = 71, /*!< USART5 interrupt */
+ I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
+ I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
+ USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
+ USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
+ USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
+ USBHS_IRQn = 77, /*!< USBHS interrupt */
+ DCI_IRQn = 78, /*!< DCI interrupt */
+ TRNG_IRQn = 80, /*!< TRNG interrupt */
+ FPU_IRQn = 81, /*!< FPU interrupt */
+ UART6_IRQn = 82, /*!< UART6 interrupt */
+ UART7_IRQn = 83, /*!< UART7 interrupt */
+ SPI3_IRQn = 84, /*!< SPI3 interrupt */
+ SPI4_IRQn = 85, /*!< SPI4 interrupt */
+ SPI5_IRQn = 86, /*!< SPI5 interrupt */
+ TLI_IRQn = 88, /*!< TLI interrupt */
+ TLI_ER_IRQn = 89, /*!< TLI error interrupt */
+ IPA_IRQn = 90, /*!< IPA interrupt */
+#endif /* GD32F450 */
+
+#if defined (GD32F405)
+ SDIO_IRQn = 49, /*!< SDIO interrupt */
+ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
+ SPI2_IRQn = 51, /*!< SPI2 interrupt */
+ UART3_IRQn = 52, /*!< UART3 interrupt */
+ UART4_IRQn = 53, /*!< UART4 interrupt */
+ TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
+ TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
+ DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
+ DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
+ DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
+ DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
+ DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
+ CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
+ CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
+ CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
+ CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
+ USBFS_IRQn = 67, /*!< USBFS interrupt */
+ DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
+ DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
+ DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
+ USART5_IRQn = 71, /*!< USART5 interrupt */
+ I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
+ I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
+ USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */
+ USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
+ USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
+ USBHS_IRQn = 77, /*!< USBHS interrupt */
+ DCI_IRQn = 78, /*!< DCI interrupt */
+ TRNG_IRQn = 80, /*!< TRNG interrupt */
+ FPU_IRQn = 81, /*!< FPU interrupt */
+#endif /* GD32F405 */
+
+#if defined (GD32F407)
+ EXMC_IRQn = 48, /*!< EXMC interrupt */
+ SDIO_IRQn = 49, /*!< SDIO interrupt */
+ TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
+ SPI2_IRQn = 51, /*!< SPI2 interrupt */
+ UART3_IRQn = 52, /*!< UART3 interrupt */
+ UART4_IRQn = 53, /*!< UART4 interrupt */
+ TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
+ TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
+ DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
+ DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
+ DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
+ DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
+ DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
+ ENET_IRQn = 61, /*!< ENET interrupt */
+ ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
+ CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
+ CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
+ CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
+ CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
+ USBFS_IRQn = 67, /*!< USBFS interrupt */
+ DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
+ DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
+ DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
+ USART5_IRQn = 71, /*!< USART5 interrupt */
+ I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
+ I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
+ USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
+ USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
+ USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
+ USBHS_IRQn = 77, /*!< USBHS interrupt */
+ DCI_IRQn = 78, /*!< DCI interrupt */
+ TRNG_IRQn = 80, /*!< TRNG interrupt */
+ FPU_IRQn = 81, /*!< FPU interrupt */
+#endif /* GD32F407 */
+
+} IRQn_Type;
+
+/* includes */
+#include "core_cm4.h"
+#include "system_gd32f4xx.h"
+#include
+
+#define GD_MBED_USED
+
+#ifdef GD_MBED_USED
+typedef enum {
+ GD_OK = 0x00U,
+ GD_ERROR = 0x01U,
+ GD_BUSY = 0x02U,
+ GD_TIMEOUT = 0x03U
+} gd_status_enum;
+
+typedef enum {
+ OP_STATE_RESET = 0x00U,
+ OP_STATE_READY = 0x01U,
+ OP_STATE_BUSY = 0x02U,
+ OP_STATE_TIMEOUT = 0x03U,
+ OP_STATE_ERROR = 0x04U,
+ OP_STATE_ABORT = 0x05U,
+ OP_STATE_LISTEN = 0x06U,
+
+ OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */
+ OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */
+
+ OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */
+ OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */
+
+ OP_STATE_BUTT
+} operation_state_enum;
+#endif
+
+/* enum definitions */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
+typedef enum {RESET = 0, SET = !RESET} FlagStatus;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
+
+/* bit operations */
+#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
+#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
+#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
+#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
+#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
+#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
+
+/* main flash and SRAM memory map */
+#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
+#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
+#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
+#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
+
+/* peripheral memory map */
+#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
+#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
+#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
+#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
+
+/* EXMC memory map */
+#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
+
+/* advanced peripheral bus 1 memory map */
+#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
+#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
+#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
+#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
+#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
+#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
+#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
+#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
+#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
+#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
+#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
+#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
+#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
+
+/* advanced peripheral bus 2 memory map */
+#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
+#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
+#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
+#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
+#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
+/* advanced high performance bus 1 memory map */
+#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
+#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
+#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
+#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
+#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
+#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
+#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
+#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
+#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
+
+/* advanced high performance bus 2 memory map */
+#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
+#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
+#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
+/* option byte and debug memory map */
+#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
+#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
+
+/* define marco USE_STDPERIPH_DRIVER */
+#if !defined USE_STDPERIPH_DRIVER
+#define USE_STDPERIPH_DRIVER
+#endif
+#ifdef USE_STDPERIPH_DRIVER
+#include "gd32f4xx_libopt.h"
+#endif /* USE_STDPERIPH_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/gd32f4xx_libopt.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/gd32f4xx_libopt.h
new file mode 100644
index 0000000..cb8c81a
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/gd32f4xx_libopt.h
@@ -0,0 +1,82 @@
+/*!
+ \file gd32f4xx_libopt.h
+ \brief library optional for gd32f4xx
+
+ \version 2016-08-15, V1.0.0, firmware for GD32F4xx
+ \version 2018-12-12, V2.0.0, firmware for GD32F4xx
+ \version 2018-12-25, V2.1.0, firmware for GD32F4xx (The version is for mbed)
+*/
+
+/*
+ Copyright (c) 2018, GigaDevice Semiconductor Inc.
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+#ifndef GD32F4XX_LIBOPT_H
+#define GD32F4XX_LIBOPT_H
+
+#if defined (GD32F450) || defined (GD32F405) || defined (GD32F407)
+#include "gd32f4xx_rcu.h"
+#include "gd32f4xx_adc.h"
+#include "gd32f4xx_can.h"
+#include "gd32f4xx_crc.h"
+#include "gd32f4xx_ctc.h"
+#include "gd32f4xx_dac.h"
+#include "gd32f4xx_dbg.h"
+#include "gd32f4xx_dci.h"
+#include "gd32f4xx_dma.h"
+#include "gd32f4xx_exti.h"
+#include "gd32f4xx_fmc.h"
+#include "gd32f4xx_fwdgt.h"
+#include "gd32f4xx_gpio.h"
+#include "gd32f4xx_syscfg.h"
+#include "gd32f4xx_i2c.h"
+#include "gd32f4xx_iref.h"
+#include "gd32f4xx_pmu.h"
+#include "gd32f4xx_rtc.h"
+#include "gd32f4xx_sdio.h"
+#include "gd32f4xx_spi.h"
+#include "gd32f4xx_timer.h"
+#include "gd32f4xx_trng.h"
+#include "gd32f4xx_usart.h"
+#include "gd32f4xx_wwdgt.h"
+#include "gd32f4xx_misc.h"
+#endif
+
+#if defined (GD32F450)
+#include "gd32f4xx_enet.h"
+#include "gd32f4xx_exmc.h"
+#include "gd32f4xx_ipa.h"
+#include "gd32f4xx_tli.h"
+#endif
+
+#if defined (GD32F407)
+#include "gd32f4xx_enet.h"
+#include "gd32f4xx_exmc.h"
+#endif
+
+#endif /* GD32F4XX_LIBOPT_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/hal_tick.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/hal_tick.h
new file mode 100644
index 0000000..f7b3043
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/hal_tick.h
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 GigaDevice Semiconductor Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "gd32f4xx.h"
+#include "cmsis_nvic.h"
+
+#define TICKER_TIMER TIMER8
+#define TICKER_TIMER_IRQ TIMER0_BRK_TIMER8_IRQn
+#define TICKER_TIMER_RCU_CLOCK_ENABLE rcu_periph_clock_enable(RCU_TIMER8);
+#define TICKER_TIMER_DEBUG_STOP dbg_periph_enable(DBG_TIMER8_HOLD);
+
+#define TICKER_TIMER_RESET_ENABLE rcu_periph_reset_enable(RCU_TIMER8RST)
+#define TICKER_TIMER_RESET_DISABLE rcu_periph_reset_disable(RCU_TIMER8RST)
+
+/* 16 for 16-bit timer, 32 for 32-bit timer */
+#define TICKER_TIMER_WIDTH_BIT 16
+
+/* 0 for CK_APB1, 1 for CK_APB2 */
+#define TICKER_TIMER_CKAPB 1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HAL_TICK_H */
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/system_gd32f4xx.c b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/system_gd32f4xx.c
new file mode 100644
index 0000000..9c9f60d
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/system_gd32f4xx.c
@@ -0,0 +1,916 @@
+/*!
+ \file system_gd32f4xx.c
+ \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
+ GD32F4xx Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#include "gd32f4xx.h"
+
+/* system frequency define */
+#define __IRC16M (IRC16M_VALUE) /* internal 16 MHz RC oscillator frequency */
+#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
+#define __SYS_OSC_CLK (__IRC16M) /* main oscillator frequency */
+
+/* select a system clock by uncommenting the following line */
+//#define __SYSTEM_CLOCK_IRC16M (uint32_t)(__IRC16M)
+//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
+//#define __SYSTEM_CLOCK_120M_PLL_IRC16M (uint32_t)(120000000)
+//#define __SYSTEM_CLOCK_120M_PLL_8M_HXTAL (uint32_t)(120000000)
+//#define __SYSTEM_CLOCK_120M_PLL_25M_HXTAL (uint32_t)(120000000)
+//#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000)
+//#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000)
+//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000)
+//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000)
+//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000)
+#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000)
+
+#define SEL_IRC16M 0x00U
+#define SEL_HXTAL 0x01U
+#define SEL_PLLP 0x02U
+#define RCU_MODIFY {volatile uint32_t i; \
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
+ for(i=0;i<50000;i++);}
+
+/* set the system clock frequency and declare the system clock configuration function */
+#ifdef __SYSTEM_CLOCK_IRC16M
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M;
+static void system_clock_16m_irc16m(void);
+#elif defined (__SYSTEM_CLOCK_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
+static void system_clock_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC16M;
+static void system_clock_120m_irc16m(void);
+#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_8M_HXTAL;
+static void system_clock_120m_8m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_25M_HXTAL;
+static void system_clock_120m_25m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_IRC16M;
+static void system_clock_168m_irc16m(void);
+#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_8M_HXTAL;
+static void system_clock_168m_8m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_25M_HXTAL;
+static void system_clock_168m_25m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_IRC16M;
+static void system_clock_200m_irc16m(void);
+#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_8M_HXTAL;
+static void system_clock_200m_8m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL;
+static void system_clock_200m_25m_hxtal(void);
+
+#endif /* __SYSTEM_CLOCK_IRC16M */
+
+/* configure the system clock */
+static void system_clock_config(void);
+
+/*!
+ \brief setup the microcontroller system, initialize the system
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCU clock configuration to the default reset state ------------*/
+ /* Set IRC16MEN bit */
+ RCU_CTL |= RCU_CTL_IRC16MEN;
+
+ RCU_MODIFY
+
+ /* Reset CFG0 register */
+ RCU_CFG0 = 0x00000000U;
+
+ /* Reset HXTALEN, CKMEN and PLLEN bits */
+ RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
+
+ /* Reset PLLCFGR register */
+ RCU_PLL = 0x24003010U;
+
+ /* Reset HSEBYP bit */
+ RCU_CTL &= ~(RCU_CTL_HXTALBPS);
+
+ /* Disable all interrupts */
+ RCU_INT = 0x00000000U;
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings ----------------------------------*/
+ system_clock_config();
+}
+/*!
+ \brief configure the system clock
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_config(void)
+{
+#ifdef __SYSTEM_CLOCK_IRC16M
+ system_clock_16m_irc16m();
+#elif defined (__SYSTEM_CLOCK_HXTAL)
+ system_clock_hxtal();
+#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
+ system_clock_120m_irc16m();
+#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
+ system_clock_120m_8m_hxtal();
+#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
+ system_clock_120m_25m_hxtal();
+#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
+ system_clock_168m_irc16m();
+#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
+ system_clock_168m_8m_hxtal();
+#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
+ system_clock_168m_25m_hxtal();
+#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
+ system_clock_200m_irc16m();
+#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
+ system_clock_200m_8m_hxtal();
+#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
+ system_clock_200m_25m_hxtal();
+#endif /* __SYSTEM_CLOCK_IRC16M */
+}
+
+#ifdef __SYSTEM_CLOCK_IRC16M
+/*!
+ \brief configure the system clock to 16M by IRC16M
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_16m_irc16m(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable IRC16M */
+ RCU_CTL |= RCU_CTL_IRC16MEN;
+
+ /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
+ } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
+ while (1) {
+ }
+ }
+
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+ /* APB1 = AHB */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+
+ /* select IRC16M as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_IRC16M;
+
+ /* wait until IRC16M is selected as system clock */
+ while (0 != (RCU_CFG0 & RCU_SCSS_IRC16M)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_HXTAL)
+/*!
+ \brief configure the system clock to HXTAL
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_hxtal(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL |= RCU_CTL_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+ } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+ while (1) {
+ }
+ }
+
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+ /* APB1 = AHB */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
+
+ /* select HXTAL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
+
+ /* wait until HXTAL is selected as system clock */
+ while (0 == (RCU_CFG0 & RCU_SCSS_HXTAL)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M)
+/*!
+ \brief configure the system clock to 120M by PLL which selects IRC16M as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_120m_irc16m(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable IRC16M */
+ RCU_CTL |= RCU_CTL_IRC16MEN;
+
+ /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
+ } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* IRC16M is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
+ RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_IRC16M) | (5U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 120 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL)
+/*!
+ \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_120m_8m_hxtal(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL |= RCU_CTL_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+ } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
+ RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_HXTAL) | (5U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 120 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL)
+/*!
+ \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_120m_25m_hxtal(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL |= RCU_CTL_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+ } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */
+ RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_HXTAL) | (5U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 120 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M)
+/*!
+ \brief configure the system clock to 168M by PLL which selects IRC16M as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_168m_irc16m(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable IRC16M */
+ RCU_CTL |= RCU_CTL_IRC16MEN;
+
+ /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
+ } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* IRC16M is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
+ RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_IRC16M) | (7U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 168 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL)
+/*!
+ \brief configure the system clock to 168M by PLL which selects HXTAL(8M) as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_168m_8m_hxtal(void)
+{
+ uint32_t timeout = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL |= RCU_CTL_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ while ((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)) {
+ }
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
+ RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_HXTAL) | (7 << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 168 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL)
+/*!
+ \brief configure the system clock to 168M by PLL which selects HXTAL(25M) as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_168m_25m_hxtal(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL |= RCU_CTL_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+ } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */
+ RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_HXTAL) | (7U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 168 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M)
+/*!
+ \brief configure the system clock to 200M by PLL which selects IRC16M as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_200m_irc16m(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable IRC16M */
+ RCU_CTL |= RCU_CTL_IRC16MEN;
+
+ /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB);
+ } while ((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_IRC16MSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* IRC16M is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
+ RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_IRC16M) | (9U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 200 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL)
+/*!
+ \brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_200m_8m_hxtal(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL |= RCU_CTL_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+ } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
+ RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_HXTAL) | (9U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 200 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL)
+/*!
+ \brief configure the system clock to 200M by PLL which selects HXTAL(25M) as its clock source
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+static void system_clock_200m_25m_hxtal(void)
+{
+ uint32_t timeout = 0U;
+ uint32_t stab_flag = 0U;
+
+ /* enable HXTAL */
+ RCU_CTL |= RCU_CTL_HXTALEN;
+
+ /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+ do {
+ timeout++;
+ stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+ } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+ /* if fail */
+ if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
+ while (1) {
+ }
+ }
+
+ RCU_APB1EN |= RCU_APB1EN_PMUEN;
+ PMU_CTL |= PMU_CTL_LDOVS;
+
+ /* HXTAL is stable */
+ /* AHB = SYSCLK */
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+ /* APB2 = AHB/2 */
+ RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
+ /* APB1 = AHB/4 */
+ RCU_CFG0 |= RCU_APB1_CKAHB_DIV4;
+
+ /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */
+ RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) |
+ (RCU_PLLSRC_HXTAL) | (9U << 24U));
+
+ /* enable PLL */
+ RCU_CTL |= RCU_CTL_PLLEN;
+
+ /* wait until PLL is stable */
+ while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
+ }
+
+ /* Enable the high-drive to extend the clock frequency to 200 Mhz */
+ PMU_CTL |= PMU_CTL_HDEN;
+ while (0U == (PMU_CS & PMU_CS_HDRF)) {
+ }
+
+ /* select the high-drive mode */
+ PMU_CTL |= PMU_CTL_HDS;
+ while (0U == (PMU_CS & PMU_CS_HDSRF)) {
+ }
+
+ /* select PLL as system clock */
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
+ RCU_CFG0 |= RCU_CKSYSSRC_PLLP;
+
+ /* wait until PLL is selected as system clock */
+ while (0U == (RCU_CFG0 & RCU_SCSS_PLLP)) {
+ }
+}
+
+#endif /* __SYSTEM_CLOCK_IRC16M */
+/*!
+ \brief update the SystemCoreClock with current core clock retrieved from cpu registers
+ \param[in] none
+ \param[out] none
+ \retval none
+*/
+void SystemCoreClockUpdate(void)
+{
+ uint32_t sws;
+ uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp;
+
+ /* exponent of AHB, APB1 and APB2 clock divider */
+ const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+ sws = GET_BITS(RCU_CFG0, 2, 3);
+ switch (sws) {
+ /* IRC16M is selected as CK_SYS */
+ case SEL_IRC16M:
+ SystemCoreClock = IRC16M_VALUE;
+ break;
+ /* HXTAL is selected as CK_SYS */
+ case SEL_HXTAL:
+ SystemCoreClock = HXTAL_VALUE;
+ break;
+ /* PLLP is selected as CK_SYS */
+ case SEL_PLLP:
+ /* get the value of PLLPSC[5:0] */
+ pllpsc = GET_BITS(RCU_PLL, 0U, 5U);
+ plln = GET_BITS(RCU_PLL, 6U, 14U);
+ pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U;
+ /* PLL clock source selection, HXTAL or IRC8M/2 */
+ pllsel = (RCU_PLL & RCU_PLL_PLLSEL);
+ if (RCU_PLLSRC_HXTAL == pllsel) {
+ ck_src = HXTAL_VALUE;
+ } else {
+ ck_src = IRC16M_VALUE;
+ }
+ SystemCoreClock = ((ck_src / pllpsc) * plln) / pllp;
+ break;
+ /* IRC16M is selected as CK_SYS */
+ default:
+ SystemCoreClock = IRC16M_VALUE;
+ break;
+ }
+ /* calculate AHB clock frequency */
+ idx = GET_BITS(RCU_CFG0, 4, 7);
+ clk_exp = ahb_exp[idx];
+ SystemCoreClock = SystemCoreClock >> clk_exp;
+}
diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/system_gd32f4xx.h b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/system_gd32f4xx.h
new file mode 100644
index 0000000..0ecd532
--- /dev/null
+++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/device/system_gd32f4xx.h
@@ -0,0 +1,58 @@
+/*!
+ \file system_gd32f4xx.h
+ \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
+ GD32F4xx Device Series
+*/
+
+/* Copyright (c) 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
+
+#ifndef SYSTEM_GD32F4XX_H
+#define SYSTEM_GD32F4XX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+/* system clock frequency (core clock) */
+extern uint32_t SystemCoreClock;
+
+/* function declarations */
+/* initialize the system and update the SystemCoreClock variable */
+extern void SystemInit(void);
+/* update the SystemCoreClock with current core clock retrieved from cpu registers */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GD32F4XX_H */